From f0fd20a54f882bb8f1cfc345d5f8e034d528d984 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 12 Jun 2020 11:59:09 +0200 Subject: ARM: tegra: Do not mark host1x as simple bus The host1x is not a simple bus, so drop the corresponding compatible string. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts/tegra30.dtsi') diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index d2d05f1da274..0b58863e570e 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -111,7 +111,7 @@ }; host1x@50000000 { - compatible = "nvidia,tegra30-host1x", "simple-bus"; + compatible = "nvidia,tegra30-host1x"; reg = <0x50000000 0x00024000>; interrupts = , /* syncpt */ ; /* general */ -- cgit From 6cc05ba2e27a211ef8feef24cb11e554f6559452 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 12 Jun 2020 12:00:03 +0200 Subject: ARM: tegra: Add missing host1x properties The host1x device tree bindings require the clock- and interrupt-names properties to be present, so add them where missing. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/boot/dts/tegra30.dtsi') diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 0b58863e570e..27000f0ba35b 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -115,7 +115,9 @@ reg = <0x50000000 0x00024000>; interrupts = , /* syncpt */ ; /* general */ + interrupt-names = "syncpt", "host1x"; clocks = <&tegra_car TEGRA30_CLK_HOST1X>; + clock-names = "host1x"; resets = <&tegra_car 28>; reset-names = "host1x"; iommus = <&mc TEGRA_SWGROUP_HC>; -- cgit From 32c096c2276acd191f8db5b1a45b3dee9502258a Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 11 Jun 2020 19:21:17 +0200 Subject: ARM: tegra: Rename sdhci nodes to mmc The new json-schema based validation tools require SD/MMC controller nodes to be named mmc. Rename all references to them. Cc: Marcel Ziswiler Cc: Philippe Schenker Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm/boot/dts/tegra30.dtsi') diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 27000f0ba35b..4780ae3b000e 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -853,7 +853,7 @@ }; }; - sdhci@78000000 { + mmc@78000000 { compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; reg = <0x78000000 0x200>; interrupts = ; @@ -863,7 +863,7 @@ status = "disabled"; }; - sdhci@78000200 { + mmc@78000200 { compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; reg = <0x78000200 0x200>; interrupts = ; @@ -873,7 +873,7 @@ status = "disabled"; }; - sdhci@78000400 { + mmc@78000400 { compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; reg = <0x78000400 0x200>; interrupts = ; @@ -883,7 +883,7 @@ status = "disabled"; }; - sdhci@78000600 { + mmc@78000600 { compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; reg = <0x78000600 0x200>; interrupts = ; -- cgit From 4c0bb8caad384da3b598ee2dfe8f8823ccfc3cae Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 11 Jun 2020 19:28:34 +0200 Subject: ARM: tegra: Add missing #phy-cells property to USB PHYs USB PHYs must have a #phy-cells property, so add one to the Tegra USB PHYs which don't have one. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30.dtsi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/boot/dts/tegra30.dtsi') diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 4780ae3b000e..c3dbf80c0e03 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -916,6 +916,7 @@ clock-names = "reg", "pll_u", "utmi-pads"; resets = <&tegra_car 22>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; nvidia,hssync-start-delay = <9>; nvidia,idle-wait-delay = <17>; nvidia,elastic-limit = <16>; @@ -953,6 +954,7 @@ clock-names = "reg", "pll_u", "utmi-pads"; resets = <&tegra_car 58>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; nvidia,hssync-start-delay = <9>; nvidia,idle-wait-delay = <17>; nvidia,elastic-limit = <16>; @@ -989,6 +991,7 @@ clock-names = "reg", "pll_u", "utmi-pads"; resets = <&tegra_car 59>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; nvidia,hssync-start-delay = <0>; nvidia,idle-wait-delay = <17>; nvidia,elastic-limit = <16>; -- cgit From 9482a17008fa98a7a8807ce6a91b8765d75ada68 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 11 Jun 2020 19:41:30 +0200 Subject: ARM: tegra: Use proper tuple notation Tuple boundaries should be marked by < and > to make it clear which cells are part of the same tuple. This also helps the json-schema based validation tooling to properly parse this data. While at it, also remove the "immovable" bit from PCI addresses. All of these addresses are in fact "movable". Cc: Marcel Ziswiler Cc: Philippe Schenker Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30.dtsi | 69 ++++++++++++++++++++++-------------------- 1 file changed, 36 insertions(+), 33 deletions(-) (limited to 'arch/arm/boot/dts/tegra30.dtsi') diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index c3dbf80c0e03..a3ea45c43bdf 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -20,12 +20,12 @@ pcie@3000 { compatible = "nvidia,tegra30-pcie"; device_type = "pci"; - reg = <0x00003000 0x00000800 /* PADS registers */ - 0x00003800 0x00000200 /* AFI registers */ - 0x10000000 0x10000000>; /* configuration space */ + reg = <0x00003000 0x00000800>, /* PADS registers */ + <0x00003800 0x00000200>, /* AFI registers */ + <0x10000000 0x10000000>; /* configuration space */ reg-names = "pads", "afi", "cs"; - interrupts = ; /* MSI interrupt */ + interrupts = , /* controller interrupt */ + ; /* MSI interrupt */ interrupt-names = "intr", "msi"; #interrupt-cells = <1>; @@ -36,12 +36,12 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */ - 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */ - 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */ - 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */ - 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */ + ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */ + <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */ + <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */ + <0x01000000 0 0 0x02000000 0 0x00010000>, /* downstream I/O */ + <0x02000000 0 0x20000000 0x20000000 0 0x08000000>, /* non-prefetchable memory */ + <0x42000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */ clocks = <&tegra_car TEGRA30_CLK_PCIE>, <&tegra_car TEGRA30_CLK_AFI>, @@ -185,8 +185,8 @@ gr3d@54180000 { compatible = "nvidia,tegra30-gr3d"; reg = <0x54180000 0x00040000>; - clocks = <&tegra_car TEGRA30_CLK_GR3D - &tegra_car TEGRA30_CLK_GR3D2>; + clocks = <&tegra_car TEGRA30_CLK_GR3D>, + <&tegra_car TEGRA30_CLK_GR3D2>; clock-names = "3d", "3d2"; resets = <&tegra_car 24>, <&tegra_car 98>; @@ -275,8 +275,8 @@ intc: interrupt-controller@50041000 { compatible = "arm,cortex-a9-gic"; - reg = <0x50041000 0x1000 - 0x50040100 0x0100>; + reg = <0x50041000 0x1000>, + <0x50040100 0x0100>; interrupt-controller; #interrupt-cells = <3>; interrupt-parent = <&intc>; @@ -406,15 +406,15 @@ vde@6001a000 { compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde"; - reg = <0x6001a000 0x1000 /* Syntax Engine */ - 0x6001b000 0x1000 /* Video Bitstream Engine */ - 0x6001c000 0x100 /* Macroblock Engine */ - 0x6001c200 0x100 /* Post-processing Engine */ - 0x6001c400 0x100 /* Motion Compensation Engine */ - 0x6001c600 0x100 /* Transform Engine */ - 0x6001c800 0x100 /* Pixel prediction block */ - 0x6001ca00 0x100 /* Video DMA */ - 0x6001d800 0x400>; /* Video frame controls */ + reg = <0x6001a000 0x1000>, /* Syntax Engine */ + <0x6001b000 0x1000>, /* Video Bitstream Engine */ + <0x6001c000 0x100>, /* Macroblock Engine */ + <0x6001c200 0x100>, /* Post-processing Engine */ + <0x6001c400 0x100>, /* Motion Compensation Engine */ + <0x6001c600 0x100>, /* Transform Engine */ + <0x6001c800 0x100>, /* Pixel prediction block */ + <0x6001ca00 0x100>, /* Video DMA */ + <0x6001d800 0x400>; /* Video frame controls */ reg-names = "sxe", "bsev", "mbe", "ppe", "mce", "tfe", "ppb", "vdma", "frameid"; iram = <&vde_pool>; /* IRAM region */ @@ -430,14 +430,14 @@ apbmisc@70000800 { compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc"; - reg = <0x70000800 0x64 /* Chip revision */ - 0x70000008 0x04>; /* Strapping options */ + reg = <0x70000800 0x64>, /* Chip revision */ + <0x70000008 0x04>; /* Strapping options */ }; pinmux: pinmux@70000868 { compatible = "nvidia,tegra30-pinmux"; - reg = <0x70000868 0xd4 /* Pad control registers */ - 0x70003000 0x3e4>; /* Mux registers */ + reg = <0x70000868 0x0d4>, /* Pad control registers */ + <0x70003000 0x3e4>; /* Mux registers */ }; /* @@ -772,8 +772,8 @@ ahub@70080000 { compatible = "nvidia,tegra30-ahub"; - reg = <0x70080000 0x200 - 0x70080200 0x100>; + reg = <0x70080000 0x200>, + <0x70080200 0x100>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>, <&tegra_car TEGRA30_CLK_APBIF>; @@ -908,7 +908,8 @@ phy1: usb-phy@7d000000 { compatible = "nvidia,tegra30-usb-phy"; - reg = <0x7d000000 0x4000 0x7d000000 0x4000>; + reg = <0x7d000000 0x4000>, + <0x7d000000 0x4000>; phy_type = "utmi"; clocks = <&tegra_car TEGRA30_CLK_USBD>, <&tegra_car TEGRA30_CLK_PLL_U>, @@ -946,7 +947,8 @@ phy2: usb-phy@7d004000 { compatible = "nvidia,tegra30-usb-phy"; - reg = <0x7d004000 0x4000 0x7d000000 0x4000>; + reg = <0x7d004000 0x4000>, + <0x7d000000 0x4000>; phy_type = "utmi"; clocks = <&tegra_car TEGRA30_CLK_USB2>, <&tegra_car TEGRA30_CLK_PLL_U>, @@ -983,7 +985,8 @@ phy3: usb-phy@7d008000 { compatible = "nvidia,tegra30-usb-phy"; - reg = <0x7d008000 0x4000 0x7d000000 0x4000>; + reg = <0x7d008000 0x4000>, + <0x7d000000 0x4000>; phy_type = "utmi"; clocks = <&tegra_car TEGRA30_CLK_USB3>, <&tegra_car TEGRA30_CLK_PLL_U>, -- cgit From f538588bdbc8d1c4bc79311a5e7f84224ffcda7a Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 11 Jun 2020 19:52:07 +0200 Subject: ARM: tegra: Add missing clock-names for SDHCI controllers The Tegra SDHCI controllers need to have a clock-names property according to the bindings. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot/dts/tegra30.dtsi') diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index a3ea45c43bdf..def18a86a36a 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -858,6 +858,7 @@ reg = <0x78000000 0x200>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_SDMMC1>; + clock-names = "sdhci"; resets = <&tegra_car 14>; reset-names = "sdhci"; status = "disabled"; @@ -868,6 +869,7 @@ reg = <0x78000200 0x200>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_SDMMC2>; + clock-names = "sdhci"; resets = <&tegra_car 9>; reset-names = "sdhci"; status = "disabled"; @@ -878,6 +880,7 @@ reg = <0x78000400 0x200>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; + clock-names = "sdhci"; resets = <&tegra_car 69>; reset-names = "sdhci"; status = "disabled"; @@ -888,6 +891,7 @@ reg = <0x78000600 0x200>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_SDMMC4>; + clock-names = "sdhci"; resets = <&tegra_car 15>; reset-names = "sdhci"; status = "disabled"; -- cgit From 7fb099528bbe92157a5e2bdc94b6f5e0269f0dd6 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 11 Jun 2020 19:58:33 +0200 Subject: ARM: tegra: Use standard names for SRAM nodes SRAM nodes should be named sram@ to match the bindings. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts/tegra30.dtsi') diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index def18a86a36a..2007c603aba2 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -97,14 +97,14 @@ }; }; - iram@40000000 { + sram@40000000 { compatible = "mmio-sram"; reg = <0x40000000 0x40000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x40000000 0x40000>; - vde_pool: vde@400 { + vde_pool: sram@400 { reg = <0x400 0x3fc00>; pool; }; -- cgit From eb6563a681e2fdf5e33a3ede03c8768059d3a8d3 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 11 Jun 2020 19:59:25 +0200 Subject: ARM: tegra: Add parent clock to DSI output The DSI output needs to specify a parent clock that will be used to drive both the output and the display controller. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts/tegra30.dtsi') diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 2007c603aba2..08d0ee4ad7c1 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -257,7 +257,9 @@ dsi@54300000 { compatible = "nvidia,tegra30-dsi"; reg = <0x54300000 0x00040000>; - clocks = <&tegra_car TEGRA30_CLK_DSIA>; + clocks = <&tegra_car TEGRA30_CLK_DSIA>, + <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; + clock-names = "dsi", "parent"; resets = <&tegra_car 48>; reset-names = "dsi"; status = "disabled"; -- cgit From 06227e3a0baf64fcc60b267db9e68b93e32f477f Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 11 Jun 2020 20:01:38 +0200 Subject: ARM: tegra: The Tegra30 DC is not backwards-compatible The display controller on Tegra30 is in fact not backwards-compatible with the instantiation found on earlier SoCs. Drop the misleading compatible string. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts/tegra30.dtsi') diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 08d0ee4ad7c1..8930255a5ff6 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -197,7 +197,7 @@ }; dc@54200000 { - compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc"; + compatible = "nvidia,tegra30-dc"; reg = <0x54200000 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_DISP1>, -- cgit From f3de06b4fa7cbdeece84003d74f650abc64729aa Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 11 Jun 2020 20:02:42 +0200 Subject: ARM: tegra: The Tegra30 SDHCI is not backwards-compatible The SDHCI on Tegra30 is in fact not backwards-compatible with the instantiation found on earlier SoCs. Drop the misleading compatible string. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm/boot/dts/tegra30.dtsi') diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 8930255a5ff6..325b593f394e 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -856,7 +856,7 @@ }; mmc@78000000 { - compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + compatible = "nvidia,tegra30-sdhci"; reg = <0x78000000 0x200>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_SDMMC1>; @@ -867,7 +867,7 @@ }; mmc@78000200 { - compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + compatible = "nvidia,tegra30-sdhci"; reg = <0x78000200 0x200>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_SDMMC2>; @@ -878,7 +878,7 @@ }; mmc@78000400 { - compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + compatible = "nvidia,tegra30-sdhci"; reg = <0x78000400 0x200>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; @@ -889,7 +889,7 @@ }; mmc@78000600 { - compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + compatible = "nvidia,tegra30-sdhci"; reg = <0x78000600 0x200>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_SDMMC4>; -- cgit From 7ee1e9feff08211c8e566a6ffac4e1af4ee529bf Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 15 Jul 2020 11:47:43 +0200 Subject: ARM: tegra: Add missing DSI controller on Tegra30 Tegra30 has a DSI controller, although it is never used on any of the devices supported by the upstream Linux kernel. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm/boot/dts/tegra30.dtsi') diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 325b593f394e..aeae8c092d41 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -264,6 +264,17 @@ reset-names = "dsi"; status = "disabled"; }; + + dsi@54400000 { + compatible = "nvidia,tegra30-dsi"; + reg = <0x54400000 0x00040000>; + clocks = <&tegra_car TEGRA30_CLK_DSIB>, + <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; + clock-names = "dsi", "parent"; + resets = <&tegra_car 84>; + reset-names = "dsi"; + status = "disabled"; + }; }; timer@50040600 { -- cgit