From 368400e242dc04963ca5ff0b70654f1470344a0a Mon Sep 17 00:00:00 2001 From: Christoffer Dall Date: Sat, 10 Dec 2016 21:13:51 +0100 Subject: ARM: dts: vexpress: Support GICC_DIR operations The GICv2 CPU interface registers span across 8K, not 4K as indicated in the DT. Only the GICC_DIR register is located after the initial 4K boundary, leaving a functional system but without support for separately EOI'ing and deactivating interrupts. After this change the system supports split priority drop and interrupt deactivation. Acked-by: Marc Zyngier Signed-off-by: Christoffer Dall [sudeep.holla@arm.com: included same fix for tc1 platform too] Signed-off-by: Sudeep Holla --- arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts') diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts index 102838fcc588..15f4fd3f4695 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts @@ -81,7 +81,7 @@ #address-cells = <0>; interrupt-controller; reg = <0 0x2c001000 0 0x1000>, - <0 0x2c002000 0 0x1000>, + <0 0x2c002000 0 0x2000>, <0 0x2c004000 0 0x2000>, <0 0x2c006000 0 0x2000>; interrupts = <1 9 0xf04>; -- cgit