From 3c220bf420908319cc1dc0715eb822e6a7c663e3 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 14 Feb 2017 17:40:21 +0100 Subject: arm: zynq: Label whole PL part as fpga_full region This will simplify dt overlay structure for the whole PL. Signed-off-by: Michal Simek --- arch/arm/boot/dts/zynq-7000.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/boot/dts/zynq-7000.dtsi') diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index f3ac9bfe580e..0f79fe1ccd9d 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -42,6 +42,14 @@ }; }; + fpga_full: fpga-full { + compatible = "fpga-region"; + fpga-mgr = <&devcfg>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + }; + pmu@f8891000 { compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>; -- cgit