From 311b57f051eac4dc56a4fa6295b14e48bac79487 Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Tue, 27 Aug 2019 16:30:55 +0930 Subject: ARM: dts: ast2600-evb: eMMC configuration Enable the eMMC controller and limit it to 52MHz to avoid the host controller reporting bus error conditions. Reviewed-by: Joel Stanley Signed-off-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-ast2600-evb.dts | 8 +++++++- arch/arm/boot/dts/aspeed-g6.dtsi | 4 ++-- 2 files changed, 9 insertions(+), 3 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts index 9870553919b7..9443d3e34a61 100644 --- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts @@ -71,10 +71,16 @@ phy-handle = <ðphy3>; }; -&emmc { +&emmc_controller { status = "okay"; }; +&emmc { + non-removable; + bus-width = <4>; + max-frequency = <52000000>; +}; + &rtc { status = "okay"; }; diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index 3a1422f7c49c..7ca45b0ce3c3 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -235,7 +235,7 @@ }; }; - emmc: sdc@1e750000 { + emmc_controller: sdc@1e750000 { compatible = "aspeed,ast2600-sd-controller"; reg = <0x1e750000 0x100>; #address-cells = <1>; @@ -244,7 +244,7 @@ clocks = <&syscon ASPEED_CLK_GATE_EMMCCLK>; status = "disabled"; - sdhci@1e750100 { + emmc: sdhci@1e750100 { compatible = "aspeed,ast2600-sdhci"; reg = <0x100 0x100>; sdhci,auto-cmd12; -- cgit From 8dbcb5b709b9fbc0d6abdccc9e7803641fbff586 Mon Sep 17 00:00:00 2001 From: Rashmica Gupta Date: Thu, 22 Aug 2019 17:13:15 +1000 Subject: ARM: dts: aspeed-g6: Add gpio devices The AST2600 has 208 normal GPIO pins and 36 1.8V GPIOs. Signed-off-by: Rashmica Gupta Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g6.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index 7ca45b0ce3c3..e7ba75a35855 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -168,6 +168,32 @@ quality = <100>; }; + gpio0: gpio@1e780000 { + #gpio-cells = <2>; + gpio-controller; + compatible = "aspeed,ast2600-gpio"; + reg = <0x1e780000 0x800>; + interrupts = ; + gpio-ranges = <&pinctrl 0 0 208>; + ngpios = <208>; + clocks = <&syscon ASPEED_CLK_APB2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@1e780800 { + #gpio-cells = <2>; + gpio-controller; + compatible = "aspeed,ast2600-gpio"; + reg = <0x1e780800 0x800>; + interrupts = ; + gpio-ranges = <&pinctrl 0 208 36>; + ngpios = <36>; + clocks = <&syscon ASPEED_CLK_APB1>; + interrupt-controller; + #interrupt-cells = <2>; + }; + rtc: rtc@1e781000 { compatible = "aspeed,ast2600-rtc"; reg = <0x1e781000 0x18>; -- cgit From 9ee6d17b18804fabe8ed879e13843f755d9e59f9 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Sun, 15 Sep 2019 15:56:47 +0100 Subject: ARM: dts: aspeed-g6: Add i2c buses The AST2600 has 16 I2C buses each with their own global IRQ line. Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g6.dtsi | 266 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 266 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index e7ba75a35855..30542945a386 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -12,6 +12,22 @@ interrupt-parent = <&gic>; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c11 = &i2c11; + i2c12 = &i2c12; + i2c13 = &i2c13; + i2c14 = &i2c14; + i2c15 = &i2c15; serial4 = &uart5; }; @@ -280,8 +296,258 @@ pinctrl-0 = <&pinctrl_emmc_default>; }; }; + + i2c: bus@1e78a000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1e78a000 0x1000>; + }; + }; }; }; #include "aspeed-g6-pinctrl.dtsi" + +&i2c { + i2c0: i2c-bus@40 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x80 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB1>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; + status = "disabled"; + }; + + i2c1: i2c-bus@100 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x100 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB1>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_default>; + status = "disabled"; + }; + + i2c2: i2c-bus@180 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x180 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB1>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_default>; + status = "disabled"; + }; + + i2c3: i2c-bus@200 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x200 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB1>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4_default>; + status = "disabled"; + }; + + i2c4: i2c-bus@280 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x280 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB1>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c5_default>; + status = "disabled"; + }; + + i2c5: i2c-bus@300 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x300 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB1>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c6_default>; + status = "disabled"; + }; + + i2c6: i2c-bus@380 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x380 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB1>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c7_default>; + status = "disabled"; + }; + + i2c7: i2c-bus@400 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x400 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB1>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c8_default>; + status = "disabled"; + }; + + i2c8: i2c-bus@480 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x480 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB1>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c9_default>; + status = "disabled"; + }; + + i2c9: i2c-bus@500 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x500 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB1>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c10_default>; + status = "disabled"; + }; + + i2c10: i2c-bus@580 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x580 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB1>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c11_default>; + status = "disabled"; + }; + + i2c11: i2c-bus@600 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x600 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB1>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c12_default>; + status = "disabled"; + }; + + i2c12: i2c-bus@680 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x680 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB1>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c13_default>; + status = "disabled"; + }; + + i2c13: i2c-bus@700 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x700 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB1>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c14_default>; + status = "disabled"; + }; + + i2c14: i2c-bus@780 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x780 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB1>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c15_default>; + status = "disabled"; + }; + + i2c15: i2c-bus@800 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x800 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB1>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c16_default>; + status = "disabled"; + }; +}; -- cgit From 2aed40eeb446ed92ddc2e47587335459c73ad419 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 2 Oct 2019 19:53:25 +0930 Subject: ARM: dts: aspeed-g6: Add VUART descriptions The AST2600 has two VUART devices. Reviewed-by: Eddie James Reviewed-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g6.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index 30542945a386..736b4f88a3ad 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -29,6 +29,8 @@ i2c14 = &i2c14; i2c15 = &i2c15; serial4 = &uart5; + serial5 = &vuart1; + serial6 = &vuart2; }; @@ -297,6 +299,26 @@ }; }; + vuart1: serial@1e787000 { + compatible = "aspeed,ast2500-vuart"; + reg = <0x1e787000 0x40>; + reg-shift = <2>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_APB1>; + no-loopback-test; + status = "disabled"; + }; + + vuart2: serial@1e788000 { + compatible = "aspeed,ast2500-vuart"; + reg = <0x1e788000 0x40>; + reg-shift = <2>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_APB1>; + no-loopback-test; + status = "disabled"; + }; + i2c: bus@1e78a000 { compatible = "simple-bus"; #address-cells = <1>; -- cgit From 12ce8bd361c72847eb7990d88df97dc0575c763a Mon Sep 17 00:00:00 2001 From: Brad Bishop Date: Wed, 25 Sep 2019 08:56:06 -0400 Subject: ARM: dts: aspeed-g6: Add lpc devices Everything is the same as G5, except the devices have their own interrupt now. Acked-by: Andrew Jeffery Signed-off-by: Brad Bishop Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g6.dtsi | 87 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index 736b4f88a3ad..c6207cbc1140 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -251,6 +251,93 @@ status = "disabled"; }; + lpc: lpc@1e789000 { + compatible = "aspeed,ast2600-lpc", "simple-mfd"; + reg = <0x1e789000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e789000 0x1000>; + + lpc_bmc: lpc-bmc@0 { + compatible = "aspeed,ast2600-lpc-bmc", "simple-mfd", "syscon"; + reg = <0x0 0x80>; + reg-io-width = <4>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x80>; + + kcs1: kcs1@0 { + compatible = "aspeed,ast2600-kcs-bmc"; + interrupts = ; + kcs_chan = <1>; + status = "disabled"; + }; + kcs2: kcs2@0 { + compatible = "aspeed,ast2600-kcs-bmc"; + interrupts = ; + kcs_chan = <2>; + status = "disabled"; + }; + kcs3: kcs3@0 { + compatible = "aspeed,ast2600-kcs-bmc"; + interrupts = ; + kcs_chan = <3>; + status = "disabled"; + }; + }; + + lpc_host: lpc-host@80 { + compatible = "aspeed,ast2600-lpc-host", "simple-mfd", "syscon"; + reg = <0x80 0x1e0>; + reg-io-width = <4>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x80 0x1e0>; + + kcs4: kcs4@0 { + compatible = "aspeed,ast2600-kcs-bmc"; + interrupts = ; + kcs_chan = <4>; + status = "disabled"; + }; + + lpc_ctrl: lpc-ctrl@0 { + compatible = "aspeed,ast2600-lpc-ctrl"; + reg = <0x0 0x80>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; + status = "disabled"; + }; + + lpc_snoop: lpc-snoop@0 { + compatible = "aspeed,ast2600-lpc-snoop"; + reg = <0x0 0x80>; + interrupts = ; + status = "disabled"; + }; + + lhc: lhc@20 { + compatible = "aspeed,ast2600-lhc"; + reg = <0x20 0x24 0x48 0x8>; + }; + + lpc_reset: reset-controller@18 { + compatible = "aspeed,ast2600-lpc-reset"; + reg = <0x18 0x4>; + #reset-cells = <1>; + }; + + ibt: ibt@c0 { + compatible = "aspeed,ast2600-ibt-bmc"; + reg = <0xc0 0x18>; + interrupts = ; + status = "disabled"; + }; + }; + }; + sdc: sdc@1e740000 { compatible = "aspeed,ast2600-sd-controller"; reg = <0x1e740000 0x100>; -- cgit From 51d5d1bf73b93479149e4fd873d2261007391925 Mon Sep 17 00:00:00 2001 From: Cédric Le Goater Date: Wed, 25 Sep 2019 14:42:27 +0200 Subject: ARM: dts: aspeed-g6: Add FMC and SPI devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Cédric Le Goater Reviewed-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g6.dtsi | 79 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index c6207cbc1140..c39b8ac19261 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -82,6 +82,85 @@ <0x40466000 0x2000>; }; + fmc: spi@1e620000 { + reg = < 0x1e620000 0xc4 + 0x20000000 0x10000000 >; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2600-fmc"; + clocks = <&syscon ASPEED_CLK_AHB>; + status = "disabled"; + interrupts = ; + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + flash@1 { + reg = < 1 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + flash@2 { + reg = < 2 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + }; + + spi1: spi@1e630000 { + reg = < 0x1e630000 0xc4 + 0x30000000 0x10000000 >; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2600-spi"; + clocks = <&syscon ASPEED_CLK_AHB>; + status = "disabled"; + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + flash@1 { + reg = < 1 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + }; + + spi2: spi@1e631000 { + reg = < 0x1e631000 0xc4 + 0x50000000 0x10000000 >; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2600-spi"; + clocks = <&syscon ASPEED_CLK_AHB>; + status = "disabled"; + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + flash@1 { + reg = < 1 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + flash@2 { + reg = < 2 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + }; + mdio0: mdio@1e650000 { compatible = "aspeed,ast2600-mdio"; reg = <0x1e650000 0x8>; -- cgit From b58135ad1ecf1aef457eeaf04c8941f4c6031d39 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Thu, 22 Aug 2019 22:15:04 +0930 Subject: ARM: dts: aspeed: Add Tacoma machine This is an AST2600 based BMC card for a Power9 system. Signed-off-by: Joel Stanley --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts | 441 ++++++++++++++++++++++++++++ 2 files changed, 442 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b21b3a64641a..dd24c3894375 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1298,6 +1298,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-opp-palmetto.dtb \ aspeed-bmc-opp-romulus.dtb \ aspeed-bmc-opp-swift.dtb \ + aspeed-bmc-opp-tacoma.dtb \ aspeed-bmc-opp-vesnin.dtb \ aspeed-bmc-opp-witherspoon.dtb \ aspeed-bmc-opp-zaius.dtb \ diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts new file mode 100644 index 000000000000..c2b68281cd7f --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts @@ -0,0 +1,441 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2019 IBM Corp. +/dts-v1/; + +#include "aspeed-g6.dtsi" + +/ { + model = "Tacoma"; + compatible = "ibm,tacoma-bmc", "aspeed,ast2600"; + + aliases { + serial4 = &uart5; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + flash_memory: region@ba000000 { + no-map; + reg = <0xba000000 0x2000000>; /* 32M */ + }; + }; +}; + +&mac2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii3_default>; + use-ncsi; +}; + +&emmc { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + + bmp: bmp280@77 { + compatible = "bosch,bmp280"; + reg = <0x77>; + #io-channel-cells = <1>; + }; + + max31785@52 { + compatible = "maxim,max31785a"; + reg = <0x52>; + #address-cells = <1>; + #size-cells = <0>; + + fan@0 { + compatible = "pmbus-fan"; + reg = <0>; + tach-pulses = <2>; + maxim,fan-rotor-input = "tach"; + maxim,fan-pwm-freq = <25000>; + maxim,fan-dual-tach; + maxim,fan-no-watchdog; + maxim,fan-no-fault-ramp; + maxim,fan-ramp = <2>; + maxim,fan-fault-pin-mon; + }; + + fan@1 { + compatible = "pmbus-fan"; + reg = <1>; + tach-pulses = <2>; + maxim,fan-rotor-input = "tach"; + maxim,fan-pwm-freq = <25000>; + maxim,fan-dual-tach; + maxim,fan-no-watchdog; + maxim,fan-no-fault-ramp; + maxim,fan-ramp = <2>; + maxim,fan-fault-pin-mon; + }; + + fan@2 { + compatible = "pmbus-fan"; + reg = <2>; + tach-pulses = <2>; + maxim,fan-rotor-input = "tach"; + maxim,fan-pwm-freq = <25000>; + maxim,fan-dual-tach; + maxim,fan-no-watchdog; + maxim,fan-no-fault-ramp; + maxim,fan-ramp = <2>; + maxim,fan-fault-pin-mon; + }; + + fan@3 { + compatible = "pmbus-fan"; + reg = <3>; + tach-pulses = <2>; + maxim,fan-rotor-input = "tach"; + maxim,fan-pwm-freq = <25000>; + maxim,fan-dual-tach; + maxim,fan-no-watchdog; + maxim,fan-no-fault-ramp; + maxim,fan-ramp = <2>; + maxim,fan-fault-pin-mon; + }; + }; + + dps: dps310@76 { + compatible = "infineon,dps310"; + reg = <0x76>; + #io-channel-cells = <0>; + }; + + pca0: pca9552@60 { + compatible = "nxp,pca9552"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = ; + }; + + gpio@1 { + reg = <1>; + type = ; + }; + + gpio@2 { + reg = <2>; + type = ; + }; + + gpio@3 { + reg = <3>; + type = ; + }; + + gpio@4 { + reg = <4>; + type = ; + }; + + gpio@5 { + reg = <5>; + type = ; + }; + + gpio@6 { + reg = <6>; + type = ; + }; + + gpio@7 { + reg = <7>; + type = ; + }; + + gpio@8 { + reg = <8>; + type = ; + }; + + gpio@9 { + reg = <9>; + type = ; + }; + + gpio@10 { + reg = <10>; + type = ; + }; + + gpio@11 { + reg = <11>; + type = ; + }; + + gpio@12 { + reg = <12>; + type = ; + }; + + gpio@13 { + reg = <13>; + type = ; + }; + + gpio@14 { + reg = <14>; + type = ; + }; + + gpio@15 { + reg = <15>; + type = ; + }; + }; + + power-supply@68 { + compatible = "ibm,cffps1"; + reg = <0x68>; + }; + + power-supply@69 { + compatible = "ibm,cffps1"; + reg = <0x69>; + }; +}; + +&i2c4 { + status = "okay"; + + tmp423a@4c { + compatible = "ti,tmp423"; + reg = <0x4c>; + }; + + ir35221@70 { + compatible = "infineon,ir35221"; + reg = <0x70>; + }; + + ir35221@71 { + compatible = "infineon,ir35221"; + reg = <0x71>; + }; +}; + +&i2c5 { + status = "okay"; + + tmp423a@4c { + compatible = "ti,tmp423"; + reg = <0x4c>; + }; + + ir35221@70 { + compatible = "infineon,ir35221"; + reg = <0x70>; + }; + + ir35221@71 { + compatible = "infineon,ir35221"; + reg = <0x71>; + }; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; + + tmp275@4a { + compatible = "ti,tmp275"; + reg = <0x4a>; + }; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; + + pca9552: pca9552@60 { + compatible = "nxp,pca9552"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = "PS_SMBUS_RESET_N", "APSS_RESET_N", + "GPU0_TH_OVERT_N_BUFF", "GPU1_TH_OVERT_N_BUFF", + "GPU2_TH_OVERT_N_BUFF", "GPU3_TH_OVERT_N_BUFF", + "GPU4_TH_OVERT_N_BUFF", "GPU5_TH_OVERT_N_BUFF", + "GPU0_PWR_GOOD_BUFF", "GPU1_PWR_GOOD_BUFF", + "GPU2_PWR_GOOD_BUFF", "GPU3_PWR_GOOD_BUFF", + "GPU4_PWR_GOOD_BUFF", "GPU5_PWR_GOOD_BUFF", + "12V_BREAKER_FLT_N", "THROTTLE_UNLATCHED_N"; + + gpio@0 { + reg = <0>; + type = ; + }; + + gpio@1 { + reg = <1>; + type = ; + }; + + gpio@2 { + reg = <2>; + type = ; + }; + + gpio@3 { + reg = <3>; + type = ; + }; + + gpio@4 { + reg = <4>; + type = ; + }; + + gpio@5 { + reg = <5>; + type = ; + }; + + gpio@6 { + reg = <6>; + type = ; + }; + + gpio@7 { + reg = <7>; + type = ; + }; + + gpio@8 { + reg = <8>; + type = ; + }; + + gpio@9 { + reg = <9>; + type = ; + }; + + gpio@10 { + reg = <10>; + type = ; + }; + + gpio@11 { + reg = <11>; + type = ; + }; + + gpio@12 { + reg = <12>; + type = ; + }; + + gpio@13 { + reg = <13>; + type = ; + }; + + gpio@14 { + reg = <14>; + type = ; + }; + + gpio@15 { + reg = <15>; + type = ; + }; + }; + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; + + ucd90160@64 { + compatible = "ti,ucd90160"; + reg = <0x64>; + }; +}; + +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; +}; + +&ibt { + status = "okay"; +}; + +&vuart1 { + status = "okay"; +}; + +&lpc_ctrl { + status = "okay"; + memory-region = <&flash_memory>; + flash = <&spi1>; +}; + +&wdt1 { + aspeed,reset-type = "none"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; +}; + +&wdt2 { + status = "okay"; +}; -- cgit From 606bcdde672461ba3d7ee9af54bcf7710aaacb49 Mon Sep 17 00:00:00 2001 From: Eddie James Date: Fri, 13 Sep 2019 11:15:53 -0500 Subject: ARM: dts: aspeed: tacoma: Enable I2C busses Enable all the I2C busses on Tacoma and add the I2C slave devices that exist on the busses. Signed-off-by: Eddie James Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts | 368 ++++++++++++++++++++++++++++ 1 file changed, 368 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts index c2b68281cd7f..7119ff6df7c7 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts @@ -3,6 +3,7 @@ /dts-v1/; #include "aspeed-g6.dtsi" +#include / { model = "Tacoma"; @@ -439,3 +440,370 @@ &wdt2 { status = "okay"; }; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + + bmp: bmp280@77 { + compatible = "bosch,bmp280"; + reg = <0x77>; + #io-channel-cells = <1>; + }; + + max31785@52 { + compatible = "maxim,max31785a"; + reg = <0x52>; + #address-cells = <1>; + #size-cells = <0>; + + fan@0 { + compatible = "pmbus-fan"; + reg = <0>; + tach-pulses = <2>; + maxim,fan-rotor-input = "tach"; + maxim,fan-pwm-freq = <25000>; + maxim,fan-dual-tach; + maxim,fan-no-watchdog; + maxim,fan-no-fault-ramp; + maxim,fan-ramp = <2>; + maxim,fan-fault-pin-mon; + }; + + fan@1 { + compatible = "pmbus-fan"; + reg = <1>; + tach-pulses = <2>; + maxim,fan-rotor-input = "tach"; + maxim,fan-pwm-freq = <25000>; + maxim,fan-dual-tach; + maxim,fan-no-watchdog; + maxim,fan-no-fault-ramp; + maxim,fan-ramp = <2>; + maxim,fan-fault-pin-mon; + }; + + fan@2 { + compatible = "pmbus-fan"; + reg = <2>; + tach-pulses = <2>; + maxim,fan-rotor-input = "tach"; + maxim,fan-pwm-freq = <25000>; + maxim,fan-dual-tach; + maxim,fan-no-watchdog; + maxim,fan-no-fault-ramp; + maxim,fan-ramp = <2>; + maxim,fan-fault-pin-mon; + }; + + fan@3 { + compatible = "pmbus-fan"; + reg = <3>; + tach-pulses = <2>; + maxim,fan-rotor-input = "tach"; + maxim,fan-pwm-freq = <25000>; + maxim,fan-dual-tach; + maxim,fan-no-watchdog; + maxim,fan-no-fault-ramp; + maxim,fan-ramp = <2>; + maxim,fan-fault-pin-mon; + }; + }; + + dps: dps310@76 { + compatible = "infineon,dps310"; + reg = <0x76>; + #io-channel-cells = <0>; + }; + + pca0: pca9552@60 { + compatible = "nxp,pca9552"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = ; + }; + + gpio@1 { + reg = <1>; + type = ; + }; + + gpio@2 { + reg = <2>; + type = ; + }; + + gpio@3 { + reg = <3>; + type = ; + }; + + gpio@4 { + reg = <4>; + type = ; + }; + + gpio@5 { + reg = <5>; + type = ; + }; + + gpio@6 { + reg = <6>; + type = ; + }; + + gpio@7 { + reg = <7>; + type = ; + }; + + gpio@8 { + reg = <8>; + type = ; + }; + + gpio@9 { + reg = <9>; + type = ; + }; + + gpio@10 { + reg = <10>; + type = ; + }; + + gpio@11 { + reg = <11>; + type = ; + }; + + gpio@12 { + reg = <12>; + type = ; + }; + + gpio@13 { + reg = <13>; + type = ; + }; + + gpio@14 { + reg = <14>; + type = ; + }; + + gpio@15 { + reg = <15>; + type = ; + }; + }; + + power-supply@68 { + compatible = "ibm,cffps1"; + reg = <0x68>; + }; + + power-supply@69 { + compatible = "ibm,cffps1"; + reg = <0x69>; + }; +}; + +&i2c4 { + status = "okay"; + + tmp423a@4c { + compatible = "ti,tmp423"; + reg = <0x4c>; + }; + + ir35221@70 { + compatible = "infineon,ir35221"; + reg = <0x70>; + }; + + ir35221@71 { + compatible = "infineon,ir35221"; + reg = <0x71>; + }; +}; + +&i2c5 { + status = "okay"; + + tmp423a@4c { + compatible = "ti,tmp423"; + reg = <0x4c>; + }; + + ir35221@70 { + compatible = "infineon,ir35221"; + reg = <0x70>; + }; + + ir35221@71 { + compatible = "infineon,ir35221"; + reg = <0x71>; + }; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; + + tmp275@4a { + compatible = "ti,tmp275"; + reg = <0x4a>; + }; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; + + pca9552: pca9552@60 { + compatible = "nxp,pca9552"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = "PS_SMBUS_RESET_N", "APSS_RESET_N", + "GPU0_TH_OVERT_N_BUFF", "GPU1_TH_OVERT_N_BUFF", + "GPU2_TH_OVERT_N_BUFF", "GPU3_TH_OVERT_N_BUFF", + "GPU4_TH_OVERT_N_BUFF", "GPU5_TH_OVERT_N_BUFF", + "GPU0_PWR_GOOD_BUFF", "GPU1_PWR_GOOD_BUFF", + "GPU2_PWR_GOOD_BUFF", "GPU3_PWR_GOOD_BUFF", + "GPU4_PWR_GOOD_BUFF", "GPU5_PWR_GOOD_BUFF", + "12V_BREAKER_FLT_N", "THROTTLE_UNLATCHED_N"; + + gpio@0 { + reg = <0>; + type = ; + }; + + gpio@1 { + reg = <1>; + type = ; + }; + + gpio@2 { + reg = <2>; + type = ; + }; + + gpio@3 { + reg = <3>; + type = ; + }; + + gpio@4 { + reg = <4>; + type = ; + }; + + gpio@5 { + reg = <5>; + type = ; + }; + + gpio@6 { + reg = <6>; + type = ; + }; + + gpio@7 { + reg = <7>; + type = ; + }; + + gpio@8 { + reg = <8>; + type = ; + }; + + gpio@9 { + reg = <9>; + type = ; + }; + + gpio@10 { + reg = <10>; + type = ; + }; + + gpio@11 { + reg = <11>; + type = ; + }; + + gpio@12 { + reg = <12>; + type = ; + }; + + gpio@13 { + reg = <13>; + type = ; + }; + + gpio@14 { + reg = <14>; + type = ; + }; + + gpio@15 { + reg = <15>; + type = ; + }; + }; + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; + + ucd90160@64 { + compatible = "ti,ucd90160"; + reg = <0x64>; + }; +}; + +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; +}; -- cgit From d52ce2beca2a00b0e49a86f3b31d08d94e388fdf Mon Sep 17 00:00:00 2001 From: Chicago Duan Date: Wed, 4 Sep 2019 10:16:20 +0800 Subject: ARM: dts: aspeed: fp5280g2: Add LED configuration Change BMC init-ok from GPIO to LED, which needs to blink when BMC initialization is complete. Use TAB to align some lines. Signed-off-by: Chicago Duan Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts | 55 +++++++++++++++++------- 1 file changed, 40 insertions(+), 15 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts b/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts index e9d714a46a60..2339913b2171 100644 --- a/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts +++ b/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts @@ -148,14 +148,48 @@ }; leds { - compatible = "gpio-leds"; + compatible = "gpio-leds"; - power { - label = "power"; - /* TODO: dummy gpio */ - gpios = <&gpio ASPEED_GPIO(R, 1) GPIO_ACTIVE_LOW>; - }; + power { + label = "power"; + /* TODO: dummy gpio */ + gpios = <&gpio ASPEED_GPIO(R, 1) GPIO_ACTIVE_LOW>; + }; + + init-ok { + label = "init-ok"; + gpios = <&gpio ASPEED_GPIO(B, 7) GPIO_ACTIVE_LOW>; + }; + + front-memory { + label = "front-memory"; + gpios = <&gpio ASPEED_GPIO(F, 4) GPIO_ACTIVE_LOW>; + }; + + front-syshot { + label = "front-syshot"; + gpios = <&gpio ASPEED_GPIO(I, 1) GPIO_ACTIVE_LOW>; + }; + + front-syshealth { + label = "front-syshealth"; + gpios = <&gpio ASPEED_GPIO(I, 0) GPIO_ACTIVE_LOW>; + }; + front-fan { + label = "front-fan"; + gpios = <&gpio ASPEED_GPIO(H, 4) GPIO_ACTIVE_LOW>; + }; + + front-psu { + label = "front-psu"; + gpios = <&gpio ASPEED_GPIO(B, 2) GPIO_ACTIVE_LOW>; + }; + + identify { + label = "identify"; + gpios = <&gpio ASPEED_GPIO(Z, 7) GPIO_ACTIVE_LOW>; + }; }; iio-hwmon-battery { @@ -749,15 +783,6 @@ aspeed,external-nodes = <&gfx &lhc>; }; -&gpio { - pin_gpio_b7 { - gpio-hog; - gpios = ; - output-high; - line-name = "BMC_INIT_OK"; - }; -}; - &wdt1 { aspeed,reset-type = "none"; aspeed,external-signal; -- cgit From 4caa4e302c6a43edadcfe1bc4f0effc1de03c875 Mon Sep 17 00:00:00 2001 From: Brad Bishop Date: Wed, 25 Sep 2019 22:32:29 -0400 Subject: ARM: dts: Add 128MiB OpenBMC flash layout MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is an alternate layout used by OpenBMC systems that require more space on the BMC's flash. In addition to more space for the rootfs, it supports a larger u-boot and Linux kernel FIT image. The division of space is as follows: u-boot + env: 1MB kernel/FIT: 9MB rwfs: 86MB rofs: 32MB Reviewed-by: Cédric Le Goater Signed-off-by: Brad Bishop Signed-off-by: Joel Stanley --- arch/arm/boot/dts/openbmc-flash-layout-128.dtsi | 32 +++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 arch/arm/boot/dts/openbmc-flash-layout-128.dtsi (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/openbmc-flash-layout-128.dtsi b/arch/arm/boot/dts/openbmc-flash-layout-128.dtsi new file mode 100644 index 000000000000..05101a38c5bd --- /dev/null +++ b/arch/arm/boot/dts/openbmc-flash-layout-128.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ + +partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + u-boot@0 { + reg = <0x0 0xe0000>; // 896KB + label = "u-boot"; + }; + + u-boot-env@e0000 { + reg = <0xe0000 0x20000>; // 128KB + label = "u-boot-env"; + }; + + kernel@100000 { + reg = <0x100000 0x900000>; // 9MB + label = "kernel"; + }; + + rofs@a00000 { + reg = <0xa00000 0x5600000>; // 86MB + label = "rofs"; + }; + + rwfs@6000000 { + reg = <0x6000000 0x2000000>; // 32MB + label = "rwfs"; + }; +}; -- cgit From 961216c135a881b8f81d1eb39215525d4e96783e Mon Sep 17 00:00:00 2001 From: Brad Bishop Date: Wed, 25 Sep 2019 08:56:07 -0400 Subject: ARM: dts: aspeed: Add Rainier system Rainier is a new IBM server with POWER host processors and an AST2600 BMC. Signed-off-by: Brad Bishop Reviewed-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 53 ++++++++++++++++++++++++++++ 2 files changed, 54 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index dd24c3894375..eb12559fbd75 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1288,6 +1288,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-facebook-wedge40.dtb \ aspeed-bmc-facebook-wedge100.dtb \ aspeed-bmc-facebook-yamp.dtb \ + aspeed-bmc-ibm-rainier.dtb \ aspeed-bmc-intel-s2600wf.dtb \ aspeed-bmc-inspur-fp5280g2.dtb \ aspeed-bmc-lenovo-hr630.dtb \ diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts new file mode 100644 index 000000000000..3703769ad8de --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2019 IBM Corp. +/dts-v1/; + +#include "aspeed-g6.dtsi" + +/ { + model = "Rainier"; + compatible = "ibm,rainier-bmc", "aspeed,ast2600"; + + aliases { + serial4 = &uart5; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + flash_memory: region@B8000000 { + no-map; + reg = <0xB8000000 0x04000000>; /* 64M */ + }; + }; + +}; + +&emmc_controller { + status = "okay"; +}; + +&emmc { + status = "okay"; +}; + +&ibt { + status = "okay"; +}; + +&lpc_ctrl { + status = "okay"; + memory-region = <&flash_memory>; +}; -- cgit From 99e3cfa266a5100c7c5164bc453e2ff239866985 Mon Sep 17 00:00:00 2001 From: Brad Bishop Date: Wed, 25 Sep 2019 08:56:09 -0400 Subject: ARM: dts: aspeed: rainier: Add mac devices Rainier contains two NCSI network devices. Reviewed-by: Andrew Jeffery Signed-off-by: Brad Bishop Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index 3703769ad8de..bcdd472c9321 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -51,3 +51,17 @@ status = "okay"; memory-region = <&flash_memory>; }; + +&mac2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii3_default>; + use-ncsi; +}; + +&mac3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii4_default>; + use-ncsi; +}; -- cgit From 2efc118ce3c35a66ef8b74fd3118a3981b649e2e Mon Sep 17 00:00:00 2001 From: Brad Bishop Date: Wed, 25 Sep 2019 08:56:10 -0400 Subject: ARM: dts: aspeed: rainier: Add i2c devices Add fan controllers, regulators, temperature sensors, power supplies and regulators. Acked-by: Andrew Jeffery Signed-off-by: Brad Bishop Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 365 +++++++++++++++++++++++++++ 1 file changed, 365 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index bcdd472c9321..773f725ab7e9 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -47,6 +47,371 @@ status = "okay"; }; +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + + power-supply@68 { + compatible = "ibm,cffps2"; + reg = <0x68>; + }; + + power-supply@69 { + compatible = "ibm,cffps2"; + reg = <0x69>; + }; + + power-supply@6a { + compatible = "ibm,cffps2"; + reg = <0x6a>; + }; + + power-supply@6b { + compatible = "ibm,cffps2"; + reg = <0x6b>; + }; +}; + +&i2c4 { + status = "okay"; + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + tmp275@49 { + compatible = "ti,tmp275"; + reg = <0x49>; + }; + + tmp275@4a { + compatible = "ti,tmp275"; + reg = <0x4a>; + }; +}; + +&i2c5 { + status = "okay"; + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + tmp275@49 { + compatible = "ti,tmp275"; + reg = <0x49>; + }; +}; + +&i2c6 { + status = "okay"; + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + tmp275@4a { + compatible = "ti,tmp275"; + reg = <0x4a>; + }; + + tmp275@4b { + compatible = "ti,tmp275"; + reg = <0x4b>; + }; +}; + +&i2c7 { + status = "okay"; + + si7021-a20@20 { + compatible = "silabs,si7020"; + reg = <0x20>; + }; + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + max31785@52 { + compatible = "maxim,max31785a"; + reg = <0x52>; + #address-cells = <1>; + #size-cells = <0>; + + fan@0 { + compatible = "pmbus-fan"; + reg = <0>; + tach-pulses = <2>; + }; + + fan@1 { + compatible = "pmbus-fan"; + reg = <1>; + tach-pulses = <2>; + }; + + fan@2 { + compatible = "pmbus-fan"; + reg = <2>; + tach-pulses = <2>; + }; + + fan@3 { + compatible = "pmbus-fan"; + reg = <3>; + tach-pulses = <2>; + }; + }; + + pca0: pca9552@60 { + compatible = "nxp,pca9552"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + }; + + gpio@1 { + reg = <1>; + }; + + gpio@2 { + reg = <2>; + }; + + gpio@3 { + reg = <3>; + }; + + gpio@4 { + reg = <4>; + }; + + gpio@5 { + reg = <5>; + }; + + gpio@6 { + reg = <6>; + }; + + gpio@7 { + reg = <7>; + }; + + gpio@8 { + reg = <8>; + }; + + gpio@9 { + reg = <9>; + }; + + gpio@10 { + reg = <10>; + }; + + gpio@11 { + reg = <11>; + }; + + gpio@12 { + reg = <12>; + }; + + gpio@13 { + reg = <13>; + }; + + gpio@14 { + reg = <14>; + }; + + gpio@15 { + reg = <15>; + }; + }; + + dps: dps310@76 { + compatible = "infineon,dps310"; + reg = <0x76>; + #io-channel-cells = <0>; + }; +}; + +&i2c8 { + status = "okay"; + + ucd90320@b { + compatible = "ti,ucd90160"; + reg = <0x0b>; + }; + + ucd90320@c { + compatible = "ti,ucd90160"; + reg = <0x0c>; + }; + + ucd90320@11 { + compatible = "ti,ucd90160"; + reg = <0x11>; + }; + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + tmp275@4a { + compatible = "ti,tmp275"; + reg = <0x4a>; + }; +}; + +&i2c9 { + status = "okay"; + + ir35221@42 { + compatible = "infineon,ir35221"; + reg = <0x42>; + }; + + ir35221@43 { + compatible = "infineon,ir35221"; + reg = <0x43>; + }; + + ir35221@44 { + compatible = "infineon,ir35221"; + reg = <0x44>; + }; + + tmp423a@4c { + compatible = "ti,tmp423"; + reg = <0x4c>; + }; + + tmp423b@4d { + compatible = "ti,tmp423"; + reg = <0x4d>; + }; + + ir35221@72 { + compatible = "infineon,ir35221"; + reg = <0x72>; + }; + + ir35221@73 { + compatible = "infineon,ir35221"; + reg = <0x73>; + }; + + ir35221@74 { + compatible = "infineon,ir35221"; + reg = <0x74>; + }; +}; + +&i2c10 { + status = "okay"; + + ir35221@42 { + compatible = "infineon,ir35221"; + reg = <0x42>; + }; + + ir35221@43 { + compatible = "infineon,ir35221"; + reg = <0x43>; + }; + + ir35221@44 { + compatible = "infineon,ir35221"; + reg = <0x44>; + }; + + tmp423a@4c { + compatible = "ti,tmp423"; + reg = <0x4c>; + }; + + tmp423b@4d { + compatible = "ti,tmp423"; + reg = <0x4d>; + }; + + ir35221@72 { + compatible = "infineon,ir35221"; + reg = <0x72>; + }; + + ir35221@73 { + compatible = "infineon,ir35221"; + reg = <0x73>; + }; + + ir35221@74 { + compatible = "infineon,ir35221"; + reg = <0x74>; + }; +}; + +&i2c11 { + status = "okay"; + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + tmp275@49 { + compatible = "ti,tmp275"; + reg = <0x49>; + }; +}; + +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; +}; + +&i2c14 { + status = "okay"; +}; + +&i2c15 { + status = "okay"; +}; + &lpc_ctrl { status = "okay"; memory-region = <&flash_memory>; -- cgit From f97fa21f48808d011aa3507ff64763a6bac06b63 Mon Sep 17 00:00:00 2001 From: Cédric Le Goater Date: Wed, 25 Sep 2019 14:42:28 +0200 Subject: ARM: dts: aspeed: rainier: Enable FMC and SPI devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Cédric Le Goater Acked-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 31 ++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index 773f725ab7e9..98b559d4acae 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -430,3 +430,34 @@ pinctrl-0 = <&pinctrl_rmii4_default>; use-ncsi; }; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-128.dtsi" + }; + + flash@1 { + status = "okay"; + m25p,fast-read; + label = "alt-bmc"; + spi-max-frequency = <50000000>; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + spi-max-frequency = <100000000>; + }; +}; -- cgit From 8db6997f2b58dad565feb19b54984b4b6402af75 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Thu, 26 Sep 2019 14:54:29 +0930 Subject: ARM: dts: aspeed: tacoma: Enable FMC and SPI devices Tacoma has two SPI flash devices attached to the FMC, and one on the SPI controller. Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts | 31 +++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts index 7119ff6df7c7..ad80f7cb800d 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts @@ -35,6 +35,37 @@ }; }; +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-128.dtsi" + }; + + flash@1 { + status = "okay"; + m25p,fast-read; + label = "alt-bmc"; + spi-max-frequency = <50000000>; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + spi-max-frequency = <100000000>; + }; +}; + &mac2 { status = "okay"; pinctrl-names = "default"; -- cgit From 6700acf6662c4684fbe88c0a126de6b16d734e6d Mon Sep 17 00:00:00 2001 From: Cédric Le Goater Date: Wed, 25 Sep 2019 14:42:30 +0200 Subject: ARM: dts: ast2600-evb: Enable FMC and SPI devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Cédric Le Goater Acked-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-ast2600-evb.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts index 9443d3e34a61..a3fae3783235 100644 --- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts @@ -84,3 +84,27 @@ &rtc { status = "okay"; }; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + spi-max-frequency = <100000000>; + }; +}; -- cgit From a45d88725d18f611ac6ee41c710d9648b728c5b3 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Thu, 26 Sep 2019 16:35:40 +0930 Subject: ARM: dts: aspeed: ast2600evb: Use custom flash layout MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The AST2600 u-boot and kernel images have outgrown the OpenBMC layout. While BMC machines use 128MB SPI NOR chips, we only have 64MB on the EVB so use a layout that has a smaller region for the ro and rw filesystems. Reviewed-by: Cédric Le Goater Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-ast2600-evb.dts | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts index a3fae3783235..3c81b3ed8e79 100644 --- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts @@ -92,7 +92,37 @@ m25p,fast-read; label = "bmc"; spi-max-frequency = <50000000>; -#include "openbmc-flash-layout.dtsi" + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + u-boot@0 { + reg = <0x0 0xe0000>; // 896KB + label = "u-boot"; + }; + + u-boot-env@e0000 { + reg = <0xe0000 0x20000>; // 128KB + label = "u-boot-env"; + }; + + kernel@100000 { + reg = <0x100000 0x900000>; // 9MB + label = "kernel"; + }; + + rofs@a00000 { + reg = <0xa00000 0x2000000>; // 32MB + label = "rofs"; + }; + + rwfs@6000000 { + reg = <0x2a00000 0x1600000>; // 22MB + label = "rwfs"; + }; + }; }; }; -- cgit From 9f5a341eb96bd858ef7567f6f45a7357d86bbca9 Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Thu, 26 Sep 2019 23:06:05 +0930 Subject: ARM: dts: aspeed-g6: Fix EMMC function in pinctrl dtsi The binding was updated to better reflect the intended use of the hardware and the existing function/groups for SD3 were dropped. Signed-off-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi index 5b8bf58e89cb..045ce66ca876 100644 --- a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi +++ b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi @@ -852,14 +852,9 @@ groups = "SD2"; }; - pinctrl_sd3_default: sd3_default { - function = "SD3"; - groups = "SD3"; - }; - pinctrl_emmc_default: emmc_default { - function = "SD3"; - groups = "EMMC"; + function = "EMMC"; + groups = "EMMCG4"; }; pinctrl_sgpm1_default: sgpm1_default { -- cgit From d29f8a6e42dbbecf5254e46241fe7fbf07206b4f Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Thu, 26 Sep 2019 23:06:06 +0930 Subject: ARM: dts: aspeed-g6: Add pinctrl properties to MDIO nodes This way enabling the MDIO controllers automatically requests the right pinmux configuration. Signed-off-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g6.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index c39b8ac19261..89182169046d 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -167,6 +167,8 @@ #address-cells = <1>; #size-cells = <0>; status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio1_default>; }; mdio1: mdio@1e650008 { @@ -175,6 +177,8 @@ #address-cells = <1>; #size-cells = <0>; status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio2_default>; }; mdio2: mdio@1e650010 { @@ -183,6 +187,8 @@ #address-cells = <1>; #size-cells = <0>; status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio3_default>; }; mdio3: mdio@1e650018 { @@ -191,6 +197,8 @@ #address-cells = <1>; #size-cells = <0>; status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio4_default>; }; mac0: ftgmac@1e660000 { -- cgit From ad5d1027840d60aa555bc9113b0eeacebc76793d Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Thu, 26 Sep 2019 23:06:07 +0930 Subject: ARM: dts: ast2600-evb: Add pinmux properties for enabled MACs All 2600-evb MACs use RGMII/MDIO. Signed-off-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-ast2600-evb.dts | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts index 3c81b3ed8e79..d42a9b968fc2 100644 --- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts @@ -55,6 +55,9 @@ phy-mode = "rgmii"; phy-handle = <ðphy1>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default>; }; &mac2 { @@ -62,6 +65,9 @@ phy-mode = "rgmii"; phy-handle = <ðphy2>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii3_default>; }; &mac3 { @@ -69,6 +75,9 @@ phy-mode = "rgmii"; phy-handle = <ðphy3>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii4_default>; }; &emmc_controller { -- cgit From 6dbc7d979516fce26783c454a8fabaaee52d28db Mon Sep 17 00:00:00 2001 From: Eddie James Date: Thu, 3 Oct 2019 17:24:14 -0500 Subject: ARM: dts: aspeed: tacoma: Add gpio-key definitions Add gpio-keys for various signals on Tacoma. Signed-off-by: Eddie James Acked-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts | 60 +++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts index ad80f7cb800d..6843adf259c3 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts @@ -3,6 +3,7 @@ /dts-v1/; #include "aspeed-g6.dtsi" +#include #include / { @@ -33,6 +34,65 @@ reg = <0xba000000 0x2000000>; /* 32M */ }; }; + + gpio-keys { + compatible = "gpio-keys"; + + air-water { + label = "air-water"; + gpios = <&gpio0 ASPEED_GPIO(Q, 7) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + checkstop { + label = "checkstop"; + gpios = <&gpio0 ASPEED_GPIO(E, 3) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + ps0-presence { + label = "ps0-presence"; + gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + ps1-presence { + label = "ps1-presence"; + gpios = <&gpio0 ASPEED_GPIO(E, 5) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <1000>; + + fan0-presence { + label = "fan0-presence"; + gpios = <&pca0 4 GPIO_ACTIVE_LOW>; + linux,code = <4>; + }; + + fan1-presence { + label = "fan1-presence"; + gpios = <&pca0 5 GPIO_ACTIVE_LOW>; + linux,code = <5>; + }; + + fan2-presence { + label = "fan2-presence"; + gpios = <&pca0 6 GPIO_ACTIVE_LOW>; + linux,code = <6>; + }; + + fan3-presence { + label = "fan3-presence"; + gpios = <&pca0 7 GPIO_ACTIVE_LOW>; + linux,code = <7>; + }; + }; }; &fmc { -- cgit From 10afc900f4f8ce4092b5110cb7018885bf12b41a Mon Sep 17 00:00:00 2001 From: Alexander Filippov Date: Wed, 18 Sep 2019 15:38:15 +0300 Subject: ARM: dts: vesnin: Add power_green led Adds a new power_green led to show the host state. Signed-off-by: Alexander Filippov Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts index a27c88d23056..affd2c8743b1 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts @@ -43,6 +43,10 @@ gpios = <&gpio ASPEED_GPIO(N, 1) GPIO_ACTIVE_LOW>; }; + power_green { + gpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>; + }; + id_blue { gpios = <&gpio ASPEED_GPIO(O, 0) GPIO_ACTIVE_LOW>; }; -- cgit From b46aaf8a663da643109597ab073fd6076b4e6eaa Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Wed, 24 Jul 2019 17:43:11 +0930 Subject: ARM: dts: aspeed: Migrate away from aspeed, g[45].* compatibles Use the SoC-specific compatible strings instead. Signed-off-by: Andrew Jeffery Acked-by: Linus Walleij Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g4.dtsi | 2 +- arch/arm/boot/dts/aspeed-g5.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index dffb595d30e4..36df031e82d6 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -182,7 +182,7 @@ #reset-cells = <1>; pinctrl: pinctrl { - compatible = "aspeed,g4-pinctrl"; + compatible = "aspeed,ast2400-pinctrl"; }; p2a: p2a-control { diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index e8feb8b66a2f..d9ff5bf16223 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -215,7 +215,7 @@ #reset-cells = <1>; pinctrl: pinctrl { - compatible = "aspeed,g5-pinctrl"; + compatible = "aspeed,ast2500-pinctrl"; aspeed,external-nodes = <&gfx &lhc>; }; -- cgit From 876c5d891c9d7442d2734871317bc6480cd9f80e Mon Sep 17 00:00:00 2001 From: Cédric Le Goater Date: Fri, 22 Jun 2018 09:09:36 +0200 Subject: ARM: dts: aspeed: Add "spi-max-frequency" property MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Keep the FMC controller chips at a safe 50 MHz rate and use 100 MHz for the PNOR on the machines using a AST2500 SoC. Signed-off-by: Cédric Le Goater Reviewed-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-ast2500-evb.dts | 2 ++ arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 2 ++ arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts | 2 ++ arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts | 4 +++- arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts | 2 ++ arch/arm/boot/dts/aspeed-g4.dtsi | 2 ++ arch/arm/boot/dts/aspeed-g5.dtsi | 7 +++++++ 7 files changed, 20 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts index c9d88c90135e..8bec21ed0de5 100644 --- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts @@ -40,6 +40,7 @@ status = "okay"; m25p,fast-read; label = "bmc"; + spi-max-frequency = <50000000>; #include "openbmc-flash-layout.dtsi" }; }; @@ -50,6 +51,7 @@ status = "okay"; m25p,fast-read; label = "pnor"; + spi-max-frequency = <100000000>; }; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts index b0cb34ccb135..eb4e93a57ff4 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts @@ -87,6 +87,7 @@ status = "okay"; m25p,fast-read; label = "bmc"; + spi-max-frequency = <50000000>; #include "openbmc-flash-layout.dtsi" }; }; @@ -99,6 +100,7 @@ flash@0 { status = "okay"; m25p,fast-read; + spi-max-frequency = <50000000>; label = "pnor"; }; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts index 9628ecb879cf..bb513f245a5e 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts @@ -112,6 +112,7 @@ status = "okay"; m25p,fast-read; label = "bmc"; + spi-max-frequency = <50000000>; #include "openbmc-flash-layout.dtsi" }; }; @@ -125,6 +126,7 @@ status = "okay"; m25p,fast-read; label = "pnor"; + spi-max-frequency = <100000000>; }; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts index 31ea34e14c79..bf30fbdbe8f3 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts @@ -200,6 +200,7 @@ status = "okay"; label = "bmc"; m25p,fast-read; + spi-max-frequency = <50000000>; partitions { #address-cells = < 1 >; @@ -224,6 +225,7 @@ status = "okay"; label = "alt-bmc"; m25p,fast-read; + spi-max-frequency = <50000000>; partitions { #address-cells = < 1 >; @@ -242,7 +244,6 @@ label = "alt-obmc-ubi"; }; }; - }; }; @@ -255,6 +256,7 @@ status = "okay"; label = "pnor"; m25p,fast-read; + spi-max-frequency = <100000000>; }; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts index 30624378316d..3c514dfc7fee 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts @@ -130,6 +130,7 @@ status = "okay"; label = "bmc"; m25p,fast-read; + spi-max-frequency = <50000000>; #include "openbmc-flash-layout.dtsi" }; }; @@ -143,6 +144,7 @@ status = "okay"; label = "pnor"; m25p,fast-read; + spi-max-frequency = <100000000>; }; }; diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index 36df031e82d6..46c0891aac5a 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -65,6 +65,7 @@ flash@0 { reg = < 0 >; compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; status = "disabled"; }; flash@1 { @@ -100,6 +101,7 @@ flash@0 { reg = < 0 >; compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index d9ff5bf16223..3449bcc93d7b 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -72,16 +72,19 @@ flash@0 { reg = < 0 >; compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; status = "disabled"; }; flash@1 { reg = < 1 >; compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; status = "disabled"; }; flash@2 { reg = < 2 >; compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; status = "disabled"; }; }; @@ -97,11 +100,13 @@ flash@0 { reg = < 0 >; compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; status = "disabled"; }; flash@1 { reg = < 1 >; compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; status = "disabled"; }; }; @@ -117,11 +122,13 @@ flash@0 { reg = < 0 >; compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; status = "disabled"; }; flash@1 { reg = < 1 >; compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; status = "disabled"; }; }; -- cgit From 0fe4e304782c810950d823d3373331003a5d7429 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Thu, 22 Aug 2019 17:13:07 +0930 Subject: ARM: dts: aspeed-g6: Describe FSI masters The ast2600 has two FSI masters on the APB. Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g6.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index 89182169046d..5c237adbad53 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -159,6 +159,26 @@ spi-max-frequency = <50000000>; status = "disabled"; }; + + fsim0: fsi@1e79b000 { + compatible = "aspeed,ast2600-fsi-master", "fsi-master"; + reg = <0x1e79b000 0x94>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fsi1_default>; + clocks = <&syscon ASPEED_CLK_GATE_FSICLK>; + status = "disabled"; + }; + + fsim1: fsi@1e79b100 { + compatible = "aspeed,ast2600-fsi-master", "fsi-master"; + reg = <0x1e79b100 0x94>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fsi2_default>; + clocks = <&syscon ASPEED_CLK_GATE_FSICLK>; + status = "disabled"; + }; }; mdio0: mdio@1e650000 { -- cgit From 9c44db7096e0b73c16996cda5b601ab7c9a80cdc Mon Sep 17 00:00:00 2001 From: Brad Bishop Date: Wed, 25 Sep 2019 08:56:10 -0400 Subject: ARM: dts: aspeed: rainier: Add i2c devices Add fan controllers, regulators, temperature sensors, power supplies and regulators. Acked-by: Andrew Jeffery Signed-off-by: Brad Bishop Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 365 +++++++++++++++++++++++++++ 1 file changed, 365 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index 98b559d4acae..94d7881a7db0 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -412,6 +412,371 @@ status = "okay"; }; +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + + power-supply@68 { + compatible = "ibm,cffps2"; + reg = <0x68>; + }; + + power-supply@69 { + compatible = "ibm,cffps2"; + reg = <0x69>; + }; + + power-supply@6a { + compatible = "ibm,cffps2"; + reg = <0x6a>; + }; + + power-supply@6b { + compatible = "ibm,cffps2"; + reg = <0x6b>; + }; +}; + +&i2c4 { + status = "okay"; + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + tmp275@49 { + compatible = "ti,tmp275"; + reg = <0x49>; + }; + + tmp275@4a { + compatible = "ti,tmp275"; + reg = <0x4a>; + }; +}; + +&i2c5 { + status = "okay"; + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + tmp275@49 { + compatible = "ti,tmp275"; + reg = <0x49>; + }; +}; + +&i2c6 { + status = "okay"; + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + tmp275@4a { + compatible = "ti,tmp275"; + reg = <0x4a>; + }; + + tmp275@4b { + compatible = "ti,tmp275"; + reg = <0x4b>; + }; +}; + +&i2c7 { + status = "okay"; + + si7021-a20@20 { + compatible = "silabs,si7020"; + reg = <0x20>; + }; + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + max31785@52 { + compatible = "maxim,max31785a"; + reg = <0x52>; + #address-cells = <1>; + #size-cells = <0>; + + fan@0 { + compatible = "pmbus-fan"; + reg = <0>; + tach-pulses = <2>; + }; + + fan@1 { + compatible = "pmbus-fan"; + reg = <1>; + tach-pulses = <2>; + }; + + fan@2 { + compatible = "pmbus-fan"; + reg = <2>; + tach-pulses = <2>; + }; + + fan@3 { + compatible = "pmbus-fan"; + reg = <3>; + tach-pulses = <2>; + }; + }; + + pca0: pca9552@60 { + compatible = "nxp,pca9552"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + }; + + gpio@1 { + reg = <1>; + }; + + gpio@2 { + reg = <2>; + }; + + gpio@3 { + reg = <3>; + }; + + gpio@4 { + reg = <4>; + }; + + gpio@5 { + reg = <5>; + }; + + gpio@6 { + reg = <6>; + }; + + gpio@7 { + reg = <7>; + }; + + gpio@8 { + reg = <8>; + }; + + gpio@9 { + reg = <9>; + }; + + gpio@10 { + reg = <10>; + }; + + gpio@11 { + reg = <11>; + }; + + gpio@12 { + reg = <12>; + }; + + gpio@13 { + reg = <13>; + }; + + gpio@14 { + reg = <14>; + }; + + gpio@15 { + reg = <15>; + }; + }; + + dps: dps310@76 { + compatible = "infineon,dps310"; + reg = <0x76>; + #io-channel-cells = <0>; + }; +}; + +&i2c8 { + status = "okay"; + + ucd90320@b { + compatible = "ti,ucd90160"; + reg = <0x0b>; + }; + + ucd90320@c { + compatible = "ti,ucd90160"; + reg = <0x0c>; + }; + + ucd90320@11 { + compatible = "ti,ucd90160"; + reg = <0x11>; + }; + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + tmp275@4a { + compatible = "ti,tmp275"; + reg = <0x4a>; + }; +}; + +&i2c9 { + status = "okay"; + + ir35221@42 { + compatible = "infineon,ir35221"; + reg = <0x42>; + }; + + ir35221@43 { + compatible = "infineon,ir35221"; + reg = <0x43>; + }; + + ir35221@44 { + compatible = "infineon,ir35221"; + reg = <0x44>; + }; + + tmp423a@4c { + compatible = "ti,tmp423"; + reg = <0x4c>; + }; + + tmp423b@4d { + compatible = "ti,tmp423"; + reg = <0x4d>; + }; + + ir35221@72 { + compatible = "infineon,ir35221"; + reg = <0x72>; + }; + + ir35221@73 { + compatible = "infineon,ir35221"; + reg = <0x73>; + }; + + ir35221@74 { + compatible = "infineon,ir35221"; + reg = <0x74>; + }; +}; + +&i2c10 { + status = "okay"; + + ir35221@42 { + compatible = "infineon,ir35221"; + reg = <0x42>; + }; + + ir35221@43 { + compatible = "infineon,ir35221"; + reg = <0x43>; + }; + + ir35221@44 { + compatible = "infineon,ir35221"; + reg = <0x44>; + }; + + tmp423a@4c { + compatible = "ti,tmp423"; + reg = <0x4c>; + }; + + tmp423b@4d { + compatible = "ti,tmp423"; + reg = <0x4d>; + }; + + ir35221@72 { + compatible = "infineon,ir35221"; + reg = <0x72>; + }; + + ir35221@73 { + compatible = "infineon,ir35221"; + reg = <0x73>; + }; + + ir35221@74 { + compatible = "infineon,ir35221"; + reg = <0x74>; + }; +}; + +&i2c11 { + status = "okay"; + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + tmp275@49 { + compatible = "ti,tmp275"; + reg = <0x49>; + }; +}; + +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; +}; + +&i2c14 { + status = "okay"; +}; + +&i2c15 { + status = "okay"; +}; + &lpc_ctrl { status = "okay"; memory-region = <&flash_memory>; -- cgit From 8737481e381c6e97c1e11081faa0e41dcbccf21e Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Thu, 26 Sep 2019 14:54:29 +0930 Subject: ARM: dts: aspeed: tacoma: Enable FMC and SPI devices Tacoma has two SPI flash devices attached to the FMC, and one on the SPI controller. Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts | 31 +++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts index 6843adf259c3..01eb09cd6921 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts @@ -126,6 +126,37 @@ }; }; +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-128.dtsi" + }; + + flash@1 { + status = "okay"; + m25p,fast-read; + label = "alt-bmc"; + spi-max-frequency = <50000000>; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + spi-max-frequency = <100000000>; + }; +}; + &mac2 { status = "okay"; pinctrl-names = "default"; -- cgit From 37ece7e341e8c44ee9a7afe7277619a0ee377abe Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Thu, 26 Sep 2019 01:04:39 +0930 Subject: ARM: dts: aspeed: Add RCLK to MAC clocks for RMII interfaces We need to ungate RCLK on AST2500- and AST2600-based platforms for RMII to function. RMII interfaces are commonly used for NCSI. Signed-off-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts | 3 +++ arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts | 3 +++ arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts | 3 +++ arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 6 ++++++ arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts | 3 +++ arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts | 3 +++ arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts | 3 +++ arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts | 3 +++ arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts | 3 +++ arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts | 3 +++ arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts | 3 +++ arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts | 3 +++ arch/arm/boot/dts/aspeed-bmc-opp-swift.dts | 3 +++ arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts | 3 +++ arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts | 3 +++ arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts | 3 +++ arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts | 6 ++++++ 17 files changed, 57 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts b/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts index 521afbea2c5b..2c29ac037d32 100644 --- a/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts +++ b/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts @@ -92,6 +92,9 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rmii2_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>, + <&syscon ASPEED_CLK_MAC2RCLK>; + clock-names = "MACCLK", "RCLK"; use-ncsi; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts index 682f729ea25e..5d7cbd9164d4 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts @@ -126,6 +126,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; use-ncsi; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts index 4e09a9cf32b7..ee175dd06cae 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts @@ -90,6 +90,9 @@ no-hw-checksum; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; }; &i2c0 { diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index 94d7881a7db0..1571a797a4f4 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -786,6 +786,9 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rmii3_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>, + <&syscon ASPEED_CLK_MAC3RCLK>; + clock-names = "MACCLK", "RCLK"; use-ncsi; }; @@ -793,6 +796,9 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rmii4_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC4CLK>, + <&syscon ASPEED_CLK_MAC4RCLK>; + clock-names = "MACCLK", "RCLK"; use-ncsi; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts b/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts index 2339913b2171..c17bb7fce7ff 100644 --- a/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts +++ b/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts @@ -273,6 +273,9 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; use-ncsi; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts b/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts index 2337ee23f5c4..80c92e065a10 100644 --- a/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts +++ b/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts @@ -77,6 +77,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; use-ncsi; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts b/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts index 22dade6393d0..1deb30ec912c 100644 --- a/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts +++ b/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts @@ -69,6 +69,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; use-ncsi; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts index d3695a32e8e0..c29e5f4d86ad 100644 --- a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts +++ b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts @@ -133,6 +133,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; use-ncsi; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts index 118eb8bbbf1b..084c455ad4cb 100644 --- a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts +++ b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts @@ -139,6 +139,9 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; use-ncsi; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts b/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts index de95112e2a04..42b37a204241 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts @@ -178,6 +178,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; use-ncsi; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts b/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts index e55cc454b17f..f7e935ede919 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts @@ -449,6 +449,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; use-ncsi; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts index bb513f245a5e..edfa44fe1f75 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts @@ -162,6 +162,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; }; &i2c1 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts b/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts index f67fef1ac5e1..b8fdd2a8a2c9 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts @@ -322,6 +322,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rmii1_default>; use-ncsi; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; }; &i2c2 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts index 01eb09cd6921..fddd29da8671 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts @@ -161,6 +161,9 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rmii3_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>, + <&syscon ASPEED_CLK_MAC3RCLK>; + clock-names = "MACCLK", "RCLK"; use-ncsi; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts index bf30fbdbe8f3..569dad93e162 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts @@ -295,6 +295,9 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; use-ncsi; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts index 3c514dfc7fee..bc60ec291681 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts @@ -189,6 +189,9 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; use-ncsi; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts b/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts index 33d704541de6..4a1ca8f5b6a7 100644 --- a/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts +++ b/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts @@ -80,12 +80,18 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rmii1_default &pinctrl_mdio1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; }; &mac1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rmii2_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>, + <&syscon ASPEED_CLK_MAC2RCLK>; + clock-names = "MACCLK", "RCLK"; use-ncsi; }; -- cgit From 8bba55f74321b72a156e0c9b5cefe133b4eb479c Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 16 Oct 2019 13:18:57 +1030 Subject: ARM: dts: aspeed-g6: Fix i2c clock source The upstream clock for the I2C buses is APB2. Reviewed-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g6.dtsi | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index 5c237adbad53..8ee90bf68679 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -527,13 +527,13 @@ #include "aspeed-g6-pinctrl.dtsi" &i2c { - i2c0: i2c-bus@40 { + i2c0: i2c-bus@80 { #address-cells = <1>; #size-cells = <0>; #interrupt-cells = <1>; reg = <0x80 0x80>; compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB1>; + clocks = <&syscon ASPEED_CLK_APB2>; resets = <&syscon ASPEED_RESET_I2C>; interrupts = ; bus-frequency = <100000>; @@ -548,7 +548,7 @@ #interrupt-cells = <1>; reg = <0x100 0x80>; compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB1>; + clocks = <&syscon ASPEED_CLK_APB2>; resets = <&syscon ASPEED_RESET_I2C>; interrupts = ; bus-frequency = <100000>; @@ -563,7 +563,7 @@ #interrupt-cells = <1>; reg = <0x180 0x80>; compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB1>; + clocks = <&syscon ASPEED_CLK_APB2>; resets = <&syscon ASPEED_RESET_I2C>; interrupts = ; bus-frequency = <100000>; @@ -578,7 +578,7 @@ #interrupt-cells = <1>; reg = <0x200 0x80>; compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB1>; + clocks = <&syscon ASPEED_CLK_APB2>; resets = <&syscon ASPEED_RESET_I2C>; interrupts = ; bus-frequency = <100000>; @@ -593,7 +593,7 @@ #interrupt-cells = <1>; reg = <0x280 0x80>; compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB1>; + clocks = <&syscon ASPEED_CLK_APB2>; resets = <&syscon ASPEED_RESET_I2C>; interrupts = ; bus-frequency = <100000>; @@ -608,7 +608,7 @@ #interrupt-cells = <1>; reg = <0x300 0x80>; compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB1>; + clocks = <&syscon ASPEED_CLK_APB2>; resets = <&syscon ASPEED_RESET_I2C>; interrupts = ; bus-frequency = <100000>; @@ -623,7 +623,7 @@ #interrupt-cells = <1>; reg = <0x380 0x80>; compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB1>; + clocks = <&syscon ASPEED_CLK_APB2>; resets = <&syscon ASPEED_RESET_I2C>; interrupts = ; bus-frequency = <100000>; @@ -638,7 +638,7 @@ #interrupt-cells = <1>; reg = <0x400 0x80>; compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB1>; + clocks = <&syscon ASPEED_CLK_APB2>; resets = <&syscon ASPEED_RESET_I2C>; interrupts = ; bus-frequency = <100000>; @@ -653,7 +653,7 @@ #interrupt-cells = <1>; reg = <0x480 0x80>; compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB1>; + clocks = <&syscon ASPEED_CLK_APB2>; resets = <&syscon ASPEED_RESET_I2C>; interrupts = ; bus-frequency = <100000>; @@ -668,7 +668,7 @@ #interrupt-cells = <1>; reg = <0x500 0x80>; compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB1>; + clocks = <&syscon ASPEED_CLK_APB2>; resets = <&syscon ASPEED_RESET_I2C>; interrupts = ; bus-frequency = <100000>; @@ -683,7 +683,7 @@ #interrupt-cells = <1>; reg = <0x580 0x80>; compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB1>; + clocks = <&syscon ASPEED_CLK_APB2>; resets = <&syscon ASPEED_RESET_I2C>; interrupts = ; bus-frequency = <100000>; @@ -698,7 +698,7 @@ #interrupt-cells = <1>; reg = <0x600 0x80>; compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB1>; + clocks = <&syscon ASPEED_CLK_APB2>; resets = <&syscon ASPEED_RESET_I2C>; interrupts = ; bus-frequency = <100000>; @@ -713,7 +713,7 @@ #interrupt-cells = <1>; reg = <0x680 0x80>; compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB1>; + clocks = <&syscon ASPEED_CLK_APB2>; resets = <&syscon ASPEED_RESET_I2C>; interrupts = ; bus-frequency = <100000>; @@ -728,7 +728,7 @@ #interrupt-cells = <1>; reg = <0x700 0x80>; compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB1>; + clocks = <&syscon ASPEED_CLK_APB2>; resets = <&syscon ASPEED_RESET_I2C>; interrupts = ; bus-frequency = <100000>; @@ -743,7 +743,7 @@ #interrupt-cells = <1>; reg = <0x780 0x80>; compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB1>; + clocks = <&syscon ASPEED_CLK_APB2>; resets = <&syscon ASPEED_RESET_I2C>; interrupts = ; bus-frequency = <100000>; @@ -758,7 +758,7 @@ #interrupt-cells = <1>; reg = <0x800 0x80>; compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB1>; + clocks = <&syscon ASPEED_CLK_APB2>; resets = <&syscon ASPEED_RESET_I2C>; interrupts = ; bus-frequency = <100000>; -- cgit From c0d3e181d78223247343a6bd07a15c0585d605aa Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 16 Oct 2019 22:29:01 +1030 Subject: ARM: dts: aspeed-g6: Add remaining UARTs The AST2600 has five UARTs. Add UART 1 to 4. Tested-by: Eddie James Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g6.dtsi | 60 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index 8ee90bf68679..c800e4cf866d 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -28,6 +28,10 @@ i2c13 = &i2c13; i2c14 = &i2c14; i2c15 = &i2c15; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; serial4 = &uart5; serial5 = &vuart1; serial6 = &vuart2; @@ -326,6 +330,20 @@ status = "disabled"; }; + uart1: serial@1e783000 { + compatible = "ns16550a"; + reg = <0x1e783000 0x20>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>; + resets = <&lpc_reset 4>; + no-loopback-test; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default &pinctrl_rxd1_default>; + status = "disabled"; + }; + uart5: serial@1e784000 { compatible = "ns16550a"; reg = <0x1e784000 0x1000>; @@ -513,6 +531,48 @@ status = "disabled"; }; + uart2: serial@1e78d000 { + compatible = "ns16550a"; + reg = <0x1e78d000 0x20>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>; + resets = <&lpc_reset 5>; + no-loopback-test; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; + status = "disabled"; + }; + + uart3: serial@1e78e000 { + compatible = "ns16550a"; + reg = <0x1e78e000 0x20>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>; + resets = <&lpc_reset 6>; + no-loopback-test; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>; + status = "disabled"; + }; + + uart4: serial@1e78f000 { + compatible = "ns16550a"; + reg = <0x1e78f000 0x20>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>; + resets = <&lpc_reset 7>; + no-loopback-test; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd4_default &pinctrl_rxd4_default>; + status = "disabled"; + }; + i2c: bus@1e78a000 { compatible = "simple-bus"; #address-cells = <1>; -- cgit From 77ef1b3991e9fc9b4c48edd3be8962c4ea62b01d Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 16 Oct 2019 22:29:02 +1030 Subject: ARM: dts: aspeed: tacoma: Add UART1 and workaround The UARTs on the AST2600 A0 have a known issue that can be worked around by using the Synopsys driver. Tested-by: Eddie James Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts index fddd29da8671..0ca831344181 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts @@ -10,10 +10,6 @@ model = "Tacoma"; compatible = "ibm,tacoma-bmc", "aspeed,ast2600"; - aliases { - serial4 = &uart5; - }; - chosen { stdout-path = &uart5; bootargs = "console=ttyS4,115200n8"; @@ -542,6 +538,17 @@ status = "okay"; }; +&uart1 { + status = "okay"; + // Workaround for A0 + compatible = "snps,dw-apb-uart"; +}; + +&uart5 { + // Workaround for A0 + compatible = "snps,dw-apb-uart"; +}; + &vuart1 { status = "okay"; }; -- cgit From a750904577e8fdadcc3dc73acea0f8379063e4b3 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 16 Oct 2019 22:29:03 +1030 Subject: ARM: dts: ast2600evb: Enable UART workaround The UART has an issue on A0 that can be worked around by using the Synopsis driver. Tested-by: Eddie James Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-ast2600-evb.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts index d42a9b968fc2..47afc71ed0de 100644 --- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts @@ -147,3 +147,8 @@ spi-max-frequency = <100000000>; }; }; + +&uart5 { + // Workaround for A0 + compatible = "snps,dw-apb-uart"; +}; -- cgit From a981c93300ef7d68080081ee525d60936affd7b2 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Thu, 17 Oct 2019 10:59:53 +1030 Subject: ARM: dts: aspeed: tacoma: Add host FSI description This adds the description of the Power9 CPUs that are attached to the BMC. Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts | 247 ++++++++++++++++++++++++++++ 1 file changed, 247 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts index 0ca831344181..35865033277f 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts @@ -165,6 +165,253 @@ &emmc { status = "okay"; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + i2c@1800 { + compatible = "ibm,fsi-i2c-master"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam0_i2c0: i2c-bus@0 { + reg = <0>; + }; + + cfam0_i2c1: i2c-bus@1 { + reg = <1>; + }; + + cfam0_i2c2: i2c-bus@2 { + reg = <2>; + }; + + cfam0_i2c3: i2c-bus@3 { + reg = <3>; + }; + + cfam0_i2c4: i2c-bus@4 { + reg = <4>; + }; + + cfam0_i2c5: i2c-bus@5 { + reg = <5>; + }; + + cfam0_i2c6: i2c-bus@6 { + reg = <6>; + }; + + cfam0_i2c7: i2c-bus@7 { + reg = <7>; + }; + + cfam0_i2c8: i2c-bus@8 { + reg = <8>; + }; + + cfam0_i2c9: i2c-bus@9 { + reg = <9>; + }; + + cfam0_i2c10: i2c-bus@a { + reg = <10>; + }; + + cfam0_i2c11: i2c-bus@b { + reg = <11>; + }; + + cfam0_i2c12: i2c-bus@c { + reg = <12>; + }; + + cfam0_i2c13: i2c-bus@d { + reg = <13>; + }; + + cfam0_i2c14: i2c-bus@e { + reg = <14>; + }; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ0: occ { + compatible = "ibm,p9-occ"; + }; + }; + + fsi_hub0: hub@3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + no-scan-on-init; + }; + }; +}; + +&fsi_hub0 { + cfam@1,0 { + reg = <1 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <1>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + i2c@1800 { + compatible = "ibm,fsi-i2c-master"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam1_i2c0: i2c-bus@0 { + reg = <0>; + }; + + cfam1_i2c1: i2c-bus@1 { + reg = <1>; + }; + + cfam1_i2c2: i2c-bus@2 { + reg = <2>; + }; + + cfam1_i2c3: i2c-bus@3 { + reg = <3>; + }; + + cfam1_i2c4: i2c-bus@4 { + reg = <4>; + }; + + cfam1_i2c5: i2c-bus@5 { + reg = <5>; + }; + + cfam1_i2c6: i2c-bus@6 { + reg = <6>; + }; + + cfam1_i2c7: i2c-bus@7 { + reg = <7>; + }; + + cfam1_i2c8: i2c-bus@8 { + reg = <8>; + }; + + cfam1_i2c9: i2c-bus@9 { + reg = <9>; + }; + + cfam1_i2c10: i2c-bus@a { + reg = <10>; + }; + + cfam1_i2c11: i2c-bus@b { + reg = <11>; + }; + + cfam1_i2c12: i2c-bus@c { + reg = <12>; + }; + + cfam1_i2c13: i2c-bus@d { + reg = <13>; + }; + + cfam1_i2c14: i2c-bus@e { + reg = <14>; + }; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ1: occ { + compatible = "ibm,p9-occ"; + }; + }; + + fsi_hub1: hub@3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + no-scan-on-init; + }; + }; +}; + +/* Legacy OCC numbering (to get rid of when userspace is fixed) */ +&fsi_occ0 { + reg = <1>; +}; + +&fsi_occ1 { + reg = <2>; +}; + +/ { + aliases { + i2c100 = &cfam0_i2c0; + i2c101 = &cfam0_i2c1; + i2c102 = &cfam0_i2c2; + i2c103 = &cfam0_i2c3; + i2c104 = &cfam0_i2c4; + i2c105 = &cfam0_i2c5; + i2c106 = &cfam0_i2c6; + i2c107 = &cfam0_i2c7; + i2c108 = &cfam0_i2c8; + i2c109 = &cfam0_i2c9; + i2c110 = &cfam0_i2c10; + i2c111 = &cfam0_i2c11; + i2c112 = &cfam0_i2c12; + i2c113 = &cfam0_i2c13; + i2c114 = &cfam0_i2c14; + i2c200 = &cfam1_i2c0; + i2c201 = &cfam1_i2c1; + i2c202 = &cfam1_i2c2; + i2c203 = &cfam1_i2c3; + i2c204 = &cfam1_i2c4; + i2c205 = &cfam1_i2c5; + i2c206 = &cfam1_i2c6; + i2c207 = &cfam1_i2c7; + i2c208 = &cfam1_i2c8; + i2c209 = &cfam1_i2c9; + i2c210 = &cfam1_i2c10; + i2c211 = &cfam1_i2c11; + i2c212 = &cfam1_i2c12; + i2c213 = &cfam1_i2c13; + i2c214 = &cfam1_i2c14; + }; + }; &i2c0 { -- cgit From 575640201e666251f7ec0ff71f3e8ea9a68bdceb Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Thu, 17 Oct 2019 10:59:54 +1030 Subject: ARM: dts: aspeed: tacoma: Use 64MB for firmware memory OpenBMC requires a window the same size as the image being loaded. Reviewed-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts index 35865033277f..f88e71c2b557 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts @@ -27,7 +27,7 @@ flash_memory: region@ba000000 { no-map; - reg = <0xba000000 0x2000000>; /* 32M */ + reg = <0xb8000000 0x4000000>; /* 64M */ }; }; -- cgit From a3bff4fec5e1a148b599c74a59b2849e5ac2b19c Mon Sep 17 00:00:00 2001 From: Jinu Thomas Date: Wed, 16 Oct 2019 11:47:46 +0530 Subject: ARM: dts: aspeed: rainier: Add i2c eeproms Added eeproms for the below VPD devices - BMC - TPM - System Planar - DCM 0 VRM - DCM 1 VRM - Base Op panel - Lcd Op panel - DASD (All) - PCIe Cards (All) Signed-off-by: Jinu Joy Thomas Reviewed-by: Santosh Puranik Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 105 +++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index 1571a797a4f4..765514b083ef 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -49,6 +49,11 @@ &i2c0 { status = "okay"; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; }; &i2c1 { @@ -100,6 +105,21 @@ compatible = "ti,tmp275"; reg = <0x4a>; }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; + + eeprom@52 { + compatible = "atmel,24c64"; + reg = <0x52>; + }; }; &i2c5 { @@ -114,6 +134,16 @@ compatible = "ti,tmp275"; reg = <0x49>; }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; }; &i2c6 { @@ -133,6 +163,26 @@ compatible = "ti,tmp275"; reg = <0x4b>; }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; + + eeprom@52 { + compatible = "atmel,24c64"; + reg = <0x52>; + }; + + eeprom@53 { + compatible = "atmel,24c64"; + reg = <0x53>; + }; }; &i2c7 { @@ -258,6 +308,16 @@ reg = <0x76>; #io-channel-cells = <0>; }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; }; &i2c8 { @@ -292,6 +352,16 @@ compatible = "ti,tmp275"; reg = <0x4a>; }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; }; &i2c9 { @@ -336,6 +406,11 @@ compatible = "infineon,ir35221"; reg = <0x74>; }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; }; &i2c10 { @@ -380,6 +455,11 @@ compatible = "infineon,ir35221"; reg = <0x74>; }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; }; &i2c11 { @@ -394,6 +474,16 @@ compatible = "ti,tmp275"; reg = <0x49>; }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; }; &i2c12 { @@ -767,14 +857,29 @@ &i2c13 { status = "okay"; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; }; &i2c14 { status = "okay"; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; }; &i2c15 { status = "okay"; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; }; &lpc_ctrl { -- cgit From 8fc6327f0f0bb179b189e0301251a69cc27cc976 Mon Sep 17 00:00:00 2001 From: Brad Bishop Date: Thu, 17 Oct 2019 14:14:12 -0400 Subject: ARM: dts: aspeed: rainier: Enable VUART1 Like most OpenPower machines the VUART is expected to be at /dev/ttyS5 for communication with the host over LPC. Signed-off-by: Brad Bishop Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index 765514b083ef..a6081d82433b 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -882,6 +882,10 @@ }; }; +&vuart1 { + status = "okay"; +}; + &lpc_ctrl { status = "okay"; memory-region = <&flash_memory>; -- cgit From 253d39f5a6c51a0c49c493e889670805ea1883fb Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Tue, 22 Oct 2019 15:47:36 +1100 Subject: ARM: dts: tacoma: Hog LPC pinmux Requesting pinmux configuration is done at driver probe time. The LPC IP is composed of many sub-devices, each with their own driver, and no driver exists for the entire IP block. Avoid having each sub-device request the LPC pinmux by just hogging it in the pinctrl node. Signed-off-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts index f88e71c2b557..f02de4ab058c 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts @@ -1186,3 +1186,10 @@ &i2c13 { status = "okay"; }; + +&pinctrl { + /* Hog these as no driver is probed for the entire LPC block */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpc_default>, + <&pinctrl_lsirq_default>; +}; -- cgit From 7f4a0ad5f0f2ac9a06a8685d58ce65f2eae3879b Mon Sep 17 00:00:00 2001 From: Jinu Thomas Date: Wed, 30 Oct 2019 15:31:51 +0530 Subject: ARM: dts: aspeed: rainier: Fix i2c eeprom size Fix the size of the Proc VRM card's eeprom used for vpd storage. The size is changed from 64Kbit to 128Kbit. Signed-off-by: Jinu Joy Thomas Reviewed-by: Santosh Puranik Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index a6081d82433b..a63b0642f104 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -408,7 +408,7 @@ }; eeprom@50 { - compatible = "atmel,24c64"; + compatible = "atmel,24c128"; reg = <0x50>; }; }; @@ -457,7 +457,7 @@ }; eeprom@50 { - compatible = "atmel,24c64"; + compatible = "atmel,24c128"; reg = <0x50>; }; }; -- cgit From 1dd785ba304d9f72330921acd72133591d362a43 Mon Sep 17 00:00:00 2001 From: Brandon Wyman Date: Mon, 28 Oct 2019 16:47:54 -0500 Subject: ARM: dts: aspeed: rainier: gpio-keys for PSU presence Add in a gpio-keys section to the Rainier device tree source, add in the power supply presence GPIOs. Signed-off-by: Brandon Wyman Reviewed-by: Eddie James Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 29 ++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index a63b0642f104..c1c9cd30f980 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -3,6 +3,7 @@ /dts-v1/; #include "aspeed-g6.dtsi" +#include / { model = "Rainier"; @@ -33,6 +34,34 @@ }; }; + gpio-keys { + compatible = "gpio-keys"; + + ps0-presence { + label = "ps0-presence"; + gpios = <&gpio0 ASPEED_GPIO(S, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + ps1-presence { + label = "ps1-presence"; + gpios = <&gpio0 ASPEED_GPIO(S, 1) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + ps2-presence { + label = "ps2-presence"; + gpios = <&gpio0 ASPEED_GPIO(S, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + ps3-presence { + label = "ps3-presence"; + gpios = <&gpio0 ASPEED_GPIO(S, 3) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + }; &emmc_controller { -- cgit From 2b7ca63ccdec8795e6d308a60469b85b6abde96e Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Mon, 21 Oct 2019 12:48:17 -0700 Subject: ARM: dts: aspeed: Common dtsi for Facebook AST2500 Network BMCs This common descirption is included by all Facebook AST2500 Network BMC platforms to minimize duplicated device entries across Facebook Network BMC device trees. Signed-off-by: Tao Ren Signed-off-by: Joel Stanley --- .../boot/dts/ast2500-facebook-netbmc-common.dtsi | 96 ++++++++++++++++++++++ 1 file changed, 96 insertions(+) create mode 100644 arch/arm/boot/dts/ast2500-facebook-netbmc-common.dtsi (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ast2500-facebook-netbmc-common.dtsi b/arch/arm/boot/dts/ast2500-facebook-netbmc-common.dtsi new file mode 100644 index 000000000000..7a395ba56512 --- /dev/null +++ b/arch/arm/boot/dts/ast2500-facebook-netbmc-common.dtsi @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2019 Facebook Inc. + +#include "aspeed-g5.dtsi" + +/ { + memory@80000000 { + reg = <0x80000000 0x40000000>; + }; +}; + +/* + * Update reset type to "system" (full chip) to fix warm reboot hang issue + * when reset type is set to default ("soc", gated by reset mask registers). + */ +&wdt1 { + status = "okay"; + aspeed,reset-type = "system"; +}; + +&wdt2 { + status = "disabled"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default>; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd3_default + &pinctrl_rxd3_default>; +}; + +&uart5 { + status = "okay"; +}; + +&fmc { + status = "okay"; + + fmc_flash0: flash@0 { + status = "okay"; + m25p,fast-read; + label = "spi0.0"; + +#include "facebook-bmc-flash-layout.dtsi" + }; + + fmc_flash1: flash@1 { + status = "okay"; + m25p,fast-read; + label = "spi0.1"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + flash1@0 { + reg = <0x0 0x2000000>; + label = "flash1"; + }; + }; + }; +}; + +&mac1 { + status = "okay"; + no-hw-checksum; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&rtc { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; + +&sdmmc { + status = "okay"; +}; + +&sdhci1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd2_default>; +}; -- cgit From 7e4dd1ed48e82a7860fda856979dd153b7f8cad4 Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Mon, 21 Oct 2019 12:48:18 -0700 Subject: ARM: dts: aspeed: cmm: Use common dtsi Simplify the CMM device tree by using the common dtsi. In addition this enables the second firmware flash and the emmc device in slot #0. Signed-off-by: Tao Ren Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts | 66 +++++++-------------------- 1 file changed, 16 insertions(+), 50 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts index d519d307aa2a..016bbcb99bb6 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts @@ -2,7 +2,7 @@ // Copyright (c) 2018 Facebook Inc. /dts-v1/; -#include "aspeed-g5.dtsi" +#include "ast2500-facebook-netbmc-common.dtsi" / { model = "Facebook Backpack CMM BMC"; @@ -53,10 +53,6 @@ bootargs = "console=ttyS1,9600n8 root=/dev/ram rw earlyprintk"; }; - memory@80000000 { - reg = <0x80000000 0x20000000>; - }; - ast-adc-hwmon { compatible = "iio-hwmon"; io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, @@ -64,39 +60,7 @@ }; }; -&pinctrl { - aspeed,external-nodes = <&gfx &lhc>; -}; - -/* - * Update reset type to "system" (full chip) to fix warm reboot hang issue - * when reset type is set to default ("soc", gated by reset mask registers). - */ -&wdt1 { - status = "okay"; - aspeed,reset-type = "system"; -}; - -/* - * wdt2 is not used by Backpack CMM. - */ -&wdt2 { - status = "disabled"; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; -#include "facebook-bmc-flash-layout.dtsi" - }; -}; - &uart1 { - status = "okay"; - pinctrl-names = "default"; pinctrl-0 = <&pinctrl_txd1_default &pinctrl_rxd1_default &pinctrl_ncts1_default @@ -107,8 +71,6 @@ }; &uart3 { - status = "okay"; - pinctrl-names = "default"; pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default &pinctrl_ncts3_default @@ -123,17 +85,6 @@ &pinctrl_rxd4_default>; }; -&uart5 { - status = "okay"; -}; - -&mac1 { - status = "okay"; - no-hw-checksum; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - /* * I2C bus reserved for communication with COM-E. */ @@ -380,3 +331,18 @@ &ehci1 { status = "okay"; }; + +&vhub { + status = "disabled"; +}; + +&sdhci0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd1_default>; +}; + +&sdhci1 { + status = "disabled"; +}; -- cgit From 2bd4c3d3f405da26237661f24e24828279e7f6d8 Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Mon, 21 Oct 2019 12:48:19 -0700 Subject: ARM: dts: aspeed: minipack: Use common dtsi Simplify the Minipack device tree by using the common dtsi. In addition this enables the enabling the second firmware flash, and updates it's size from 32MB to 64MB. It also enables the eMMC device in slot #1. Signed-off-by: Tao Ren Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts | 59 +++++++--------------- 1 file changed, 19 insertions(+), 40 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts index c05478296446..88ce4ff9f47e 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts @@ -2,7 +2,7 @@ // Copyright (c) 2018 Facebook Inc. /dts-v1/; -#include "aspeed-g5.dtsi" +#include "ast2500-facebook-netbmc-common.dtsi" / { model = "Facebook Minipack 100 BMC"; @@ -76,35 +76,36 @@ stdout-path = &uart1; bootargs = "debug console=ttyS1,9600n8 root=/dev/ram rw"; }; - - memory@80000000 { - reg = <0x80000000 0x20000000>; - }; }; -&wdt1 { +&wdt2 { status = "okay"; aspeed,reset-type = "system"; }; -&wdt2 { - status = "okay"; - aspeed,reset-type = "system"; +/* + * Both firmware flashes are 64MB on Minipack BMC. + */ +&fmc_flash0 { + partitions { + data0@1c00000 { + reg = <0x1c00000 0x2400000>; + }; + flash0@0 { + reg = <0x0 0x4000000>; + }; + }; }; -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; -#include "facebook-bmc-flash-layout.dtsi" +&fmc_flash1 { + partitions { + flash1@0 { + reg = <0x0 0x4000000>; + }; }; }; &uart1 { - status = "okay"; - pinctrl-names = "default"; pinctrl-0 = <&pinctrl_txd1_default &pinctrl_rxd1_default &pinctrl_ncts1_default @@ -120,13 +121,6 @@ &pinctrl_rxd2_default>; }; -&uart3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd3_default - &pinctrl_rxd3_default>; -}; - &uart4 { status = "okay"; pinctrl-names = "default"; @@ -134,17 +128,6 @@ &pinctrl_rxd4_default>; }; -&uart5 { - status = "okay"; -}; - -&mac1 { - status = "okay"; - no-hw-checksum; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - &i2c0 { status = "okay"; bus-frequency = <400000>; @@ -423,7 +406,3 @@ &i2c13 { status = "okay"; }; - -&vhub { - status = "okay"; -}; -- cgit From 8c014e90bd6f4de070a8b0646d64c2decc201baa Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Mon, 21 Oct 2019 12:48:20 -0700 Subject: ARM: dts: aspeed: yamp: Use common dtsi Simplify the Yamp device tree by using the common dtsi. In addition this enables the following the second firmware flash and the eMMC device in slot #1. Signed-off-by: Tao Ren Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts | 62 +++----------------------- 1 file changed, 5 insertions(+), 57 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts index ee175dd06cae..52933598aac6 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts @@ -2,7 +2,7 @@ // Copyright (c) 2018 Facebook Inc. /dts-v1/; -#include "aspeed-g5.dtsi" +#include "ast2500-facebook-netbmc-common.dtsi" / { model = "Facebook YAMP 100 BMC"; @@ -23,47 +23,6 @@ stdout-path = &uart5; bootargs = "console=ttyS0,9600n8 root=/dev/ram rw"; }; - - memory@80000000 { - reg = <0x80000000 0x20000000>; - }; -}; - -&pinctrl { - aspeed,external-nodes = <&gfx &lhc>; -}; - -/* - * Update reset type to "system" (full chip) to fix warm reboot hang issue - * when reset type is set to default ("soc", gated by reset mask registers). - */ -&wdt1 { - status = "okay"; - aspeed,reset-type = "system"; -}; - -/* - * wdt2 is not used by Yamp. - */ -&wdt2 { - status = "disabled"; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; -#include "facebook-bmc-flash-layout.dtsi" - }; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default>; }; &uart2 { @@ -73,17 +32,6 @@ &pinctrl_rxd2_default>; }; -&uart3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd3_default - &pinctrl_rxd3_default>; -}; - -&uart5 { - status = "okay"; -}; - &mac0 { status = "okay"; use-ncsi; @@ -95,6 +43,10 @@ clock-names = "MACCLK", "RCLK"; }; +&mac1 { + status = "disabled"; +}; + &i2c0 { status = "okay"; }; @@ -157,7 +109,3 @@ &i2c13 { status = "okay"; }; - -&vhub { - status = "okay"; -}; -- cgit From 7671be39c4d9c09bf73d7b16fc8d50e8f57f295c Mon Sep 17 00:00:00 2001 From: Hongwei Zhang Date: Wed, 25 Sep 2019 15:22:16 -0400 Subject: ARM: dts: aspeed-g5: Add SGPIO description Add SGPIO node to the ASPEED AST2500 device tree. Signed-off-by: Hongwei Zhang Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g5.dtsi | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index 3449bcc93d7b..a8ce59a3c88d 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -306,7 +306,7 @@ #gpio-cells = <2>; gpio-controller; compatible = "aspeed,ast2500-gpio"; - reg = <0x1e780000 0x1000>; + reg = <0x1e780000 0x200>; interrupts = <20>; gpio-ranges = <&pinctrl 0 0 232>; clocks = <&syscon ASPEED_CLK_APB>; @@ -314,6 +314,21 @@ #interrupt-cells = <2>; }; + sgpio: sgpio@1e780200 { + #gpio-cells = <2>; + compatible = "aspeed,ast2500-sgpio"; + gpio-controller; + interrupts = <40>; + reg = <0x1e780200 0x0100>; + clocks = <&syscon ASPEED_CLK_APB>; + interrupt-controller; + ngpios = <8>; + bus-frequency = <12000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgpm_default>; + status = "disabled"; + }; + rtc: rtc@1e781000 { compatible = "aspeed,ast2500-rtc"; reg = <0x1e781000 0x18>; -- cgit From ea4bb33a9da21da30604fc89f3341f1526b97a49 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 16 Oct 2019 14:38:11 +1030 Subject: ARM: dts: aspeed: ast2600evb: Enable i2c buses With the exception of i2c10 and i2c11 which conflict with the pins for the third and forth MDIO controllers. i2c0 has an ADT7490 fan controller/thermal monitor device connected. The devicetree describes an adt74490 on i2c0, however bus that it appears on depends on jumper settings, so it may not be present on all EVBs. It is included to assist testing of I2C. Reviewed-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-ast2600-evb.dts | 61 ++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts index 47afc71ed0de..4afa8662c4e8 100644 --- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts @@ -152,3 +152,64 @@ // Workaround for A0 compatible = "snps,dw-apb-uart"; }; + +&i2c0 { + status = "okay"; + + temp@2e { + compatible = "adi,adt7490"; + reg = <0x2e>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; +}; + +&i2c14 { + status = "okay"; +}; + +&i2c15 { + status = "okay"; +}; -- cgit From 3eca037f2dfce07a31da0a837ac35d6d846614b0 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 6 Nov 2019 19:47:02 +1030 Subject: ARM: dts: aspeed-g6: Add timer description MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The AST2600 has 8 32-bit timers on the APB bus. Reviewed-by: Cédric Le Goater Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g6.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index c800e4cf866d..5f6142d99eeb 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -330,6 +330,21 @@ status = "disabled"; }; + timer: timer@1e782000 { + compatible = "aspeed,ast2600-timer"; + reg = <0x1e782000 0x90>; + interrupts-extended = <&gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_APB1>; + clock-names = "PCLK"; + }; + uart1: serial@1e783000 { compatible = "ns16550a"; reg = <0x1e783000 0x20>; -- cgit