From 5f9cfe9e94a6eef576f89bbf5a946f8ae63c0f71 Mon Sep 17 00:00:00 2001 From: Matthew Hagan Date: Fri, 15 Oct 2021 23:50:22 +0100 Subject: ARM: dts: NSP: MX65: add qca8k falling-edge, PLL properties This patch enables two properties for the QCA8337 switches on the MX65. Set the SGMII transmit clock to falling edge "qca,sgmii-txclk-falling-edge" to conform to the OEM configuration [1]. The new explicit PLL enable option "qca,sgmii-enable-pll" is required [2]. [1] https://git.kernel.org/netdev/net-next/c/6c43809bf1be [2] https://git.kernel.org/netdev/net-next/c/bbc4799e8bb6 Signed-off-by: Matthew Hagan Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi index 102acd85fab2..ba01054a76cf 100644 --- a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi +++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi @@ -118,6 +118,8 @@ reg = <0>; ethernet = <&sgmii1>; phy-mode = "sgmii"; + qca,sgmii-enable-pll; + qca,sgmii-txclk-falling-edge; fixed-link { speed = <1000>; full-duplex; @@ -194,6 +196,8 @@ reg = <0>; ethernet = <&sgmii0>; phy-mode = "sgmii"; + qca,sgmii-enable-pll; + qca,sgmii-txclk-falling-edge; fixed-link { speed = <1000>; full-duplex; -- cgit From 8c9f00d4b05134164e462f27b21c8295255ffa64 Mon Sep 17 00:00:00 2001 From: Arınç ÜNAL Date: Wed, 27 Oct 2021 00:57:03 +0800 Subject: ARM: dts: BCM5301X: remove unnecessary address & size cells from Asus RT-AC88U MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove the unnecessary #address-cells & #size-cells in the gpio-keys node from the device tree of Asus RT-AC88U. Signed-off-by: Arınç ÜNAL Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts index 448060561cd0..b0cee1d87600 100644 --- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts +++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts @@ -68,8 +68,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; wps { label = "WPS"; -- cgit From 3d2d52a0d1835b56f6bd67d268f6c39df0e41692 Mon Sep 17 00:00:00 2001 From: Arınç ÜNAL Date: Wed, 27 Oct 2021 00:57:06 +0800 Subject: ARM: dts: BCM5301X: define RTL8365MB switch on Asus RT-AC88U MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define the Realtek RTL8365MB switch without interrupt support on the device tree of Asus RT-AC88U. Signed-off-by: Arınç ÜNAL Acked-by: Alvin Šipraga Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 77 ++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts index b0cee1d87600..16dea851719f 100644 --- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts +++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts @@ -93,6 +93,83 @@ gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; }; }; + + switch { + compatible = "realtek,rtl8365mb"; + /* 7 = MDIO (has input reads), 6 = MDC (clock, output only) */ + mdc-gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; + mdio-gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; + realtek,disable-leds; + dsa,member = <1 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + port@0 { + reg = <0>; + label = "lan5"; + phy-handle = <ðphy0>; + }; + + port@1 { + reg = <1>; + label = "lan6"; + phy-handle = <ðphy1>; + }; + + port@2 { + reg = <2>; + label = "lan7"; + phy-handle = <ðphy2>; + }; + + port@3 { + reg = <3>; + label = "lan8"; + phy-handle = <ðphy3>; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&sw0_p5>; + phy-mode = "rgmii"; + tx-internal-delay-ps = <2000>; + rx-internal-delay-ps = <2000>; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; + + mdio { + compatible = "realtek,smi-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + reg = <1>; + }; + + ethphy2: ethernet-phy@2 { + reg = <2>; + }; + + ethphy3: ethernet-phy@3 { + reg = <3>; + }; + }; + }; }; &srab { -- cgit From de7880016665afe7fa7d40e1fafa859260d53ba1 Mon Sep 17 00:00:00 2001 From: Christian Lamparter Date: Thu, 28 Oct 2021 09:03:44 +0200 Subject: ARM: BCM53016: MR32: convert to Broadcom iProc I2C Driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit replaces the bit-banged i2c-gpio provided i2c functionality with the hardware in the SoC. During review of the MR32, Florian Fainelli pointed out that the SoC has a real I2C-controller. Furthermore, the connected pins (SDA and SCL) would line up perfectly for use. Back then I couldn't get it working though and I left it with i2c-gpio (which worked). Now we know the reason: the interrupt was incorrectly specified. (Hence, this patch depends on Florian Fainelli's "ARM: dts: BCM5301X: Fix I2C controller interrupt" patch). Cc: Florian Fainelli Cc: Rafał Miłecki Cc: Matthew Hagan Signed-off-by: Christian Lamparter Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 62 ++++++++++++++---------------- 1 file changed, 28 insertions(+), 34 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts index 64f973e1ef12..66c64a6ec414 100644 --- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts +++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts @@ -84,40 +84,6 @@ max-brightness = <255>; }; }; - - i2c { - /* - * The platform provided I2C does not budge. - * This is a replacement until I can figure - * out what are the missing bits... - */ - - compatible = "i2c-gpio"; - sda-gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; - scl-gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; - i2c-gpio,delay-us = <10>; /* close to 100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - - current_sense: ina219@45 { - compatible = "ti,ina219"; - reg = <0x45>; - shunt-resistor = <60000>; /* = 60 mOhms */ - }; - - eeprom: eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - read-only; - #address-cells = <1>; - #size-cells = <1>; - - mac_address: mac-address@66 { - reg = <0x66 0x6>; - }; - }; - }; }; &uart0 { @@ -228,3 +194,31 @@ }; }; }; + +&i2c0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_i2c>; + + clock-frequency = <100000>; + + current_sense: ina219@45 { + compatible = "ti,ina219"; + reg = <0x45>; + shunt-resistor = <60000>; /* = 60 mOhms */ + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + read-only; + #address-cells = <1>; + #size-cells = <1>; + + mac_address: mac-address@66 { + reg = <0x66 0x6>; + }; + }; +}; -- cgit From 31fd9b79dc580301c53a001482755ba7e88c2809 Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Fri, 29 Oct 2021 18:05:23 +0200 Subject: ARM: dts: BCM5301X: update CRU block description MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This describes CRU in a way matching documentation and fixes: arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dt.yaml: cru@100: $nodename:0: 'cru@100' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /lib/python3.6/site-packages/dtschema/schemas/simple-bus.yaml Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm5301x.dtsi | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index d4f355015e3c..e1cffef4935a 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -421,14 +421,14 @@ #address-cells = <1>; #size-cells = <1>; - cru@100 { - compatible = "simple-bus"; + cru-bus@100 { + compatible = "brcm,ns-cru", "simple-mfd"; reg = <0x100 0x1a4>; ranges; #address-cells = <1>; #size-cells = <1>; - lcpll0: lcpll0@100 { + lcpll0: clock-controller@100 { #clock-cells = <1>; compatible = "brcm,nsp-lcpll0"; reg = <0x100 0x14>; @@ -437,7 +437,7 @@ "sdio", "ddr_phy"; }; - genpll: genpll@140 { + genpll: clock-controller@140 { #clock-cells = <1>; compatible = "brcm,nsp-genpll"; reg = <0x140 0x24>; @@ -448,6 +448,11 @@ "sata1", "sata2"; }; + syscon@180 { + compatible = "brcm,cru-clkset", "syscon"; + reg = <0x180 0x4>; + }; + pinctrl: pin-controller@1c0 { compatible = "brcm,bcm4708-pinmux"; reg = <0x1c0 0x24>; -- cgit From 1a46061a2a4130a08841941ce6dcaa32be2ce312 Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Tue, 23 Nov 2021 10:03:33 +0100 Subject: ARM: dts: BCM5301X: use non-deprecated USB 2.0 PHY binding MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The new binding covers a single reg and uses syscon to reference shared register. References: 55b9b741712d ("dt-bindings: phy: brcm,ns-usb2-phy: bind just a PHY block") Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm5301x.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index e1cffef4935a..588e57db6859 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -148,15 +148,6 @@ }; }; - usb2_phy: usb2-phy@1800c000 { - compatible = "brcm,ns-usb2-phy"; - reg = <0x1800c000 0x1000>; - reg-names = "dmu"; - #phy-cells = <0>; - clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>; - clock-names = "phy-ref-clk"; - }; - axi@18000000 { compatible = "brcm,bus-axi"; reg = <0x18000000 0x1000>; @@ -448,7 +439,16 @@ "sata1", "sata2"; }; - syscon@180 { + usb2_phy: phy@164 { + compatible = "brcm,ns-usb2-phy"; + reg = <0x164 0x4>; + brcm,syscon-clkset = <&cru_clkset>; + clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>; + clock-names = "phy-ref-clk"; + #phy-cells = <0>; + }; + + cru_clkset: syscon@180 { compatible = "brcm,cru-clkset", "syscon"; reg = <0x180 0x4>; }; -- cgit From 5e8c1bf1a0a5c728cee2b6c2162348a9dfddf1bf Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Tue, 30 Nov 2021 17:11:47 +0100 Subject: ARM: dts: bcm2711-rpi-4-b: Add gpio offsets to line name array MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit this helps human readers considerably to determine the line name for a given offset or vice versa. Signed-off-by: Uwe Kleine-König [ nsaenz: corrected patch title ] Signed-off-by: Nicolas Saenz Julienne Link: https://lore.kernel.org/r/20211130161147.317653-1-u.kleine-koenig@pengutronix.de --- arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts index 631dd5baf68d..4432412044de 100644 --- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts +++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts @@ -65,12 +65,12 @@ }; &expgpio { - gpio-line-names = "BT_ON", + gpio-line-names = "BT_ON", /* 0 */ "WL_ON", "PWR_LED_OFF", "GLOBAL_RESET", "VDD_SD_IO_SEL", - "CAM_GPIO", + "CAM_GPIO", /* 5 */ "SD_PWR_ON", ""; }; @@ -84,66 +84,66 @@ * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ - gpio-line-names = "ID_SDA", + gpio-line-names = "ID_SDA", /* 0 */ "ID_SCL", "SDA1", "SCL1", "GPIO_GCLK", - "GPIO5", + "GPIO5", /* 5 */ "GPIO6", "SPI_CE1_N", "SPI_CE0_N", "SPI_MISO", - "SPI_MOSI", + "SPI_MOSI", /* 10 */ "SPI_SCLK", "GPIO12", "GPIO13", /* Serial port */ "TXD1", - "RXD1", + "RXD1", /* 15 */ "GPIO16", "GPIO17", "GPIO18", "GPIO19", - "GPIO20", + "GPIO20", /* 20 */ "GPIO21", "GPIO22", "GPIO23", "GPIO24", - "GPIO25", + "GPIO25", /* 25 */ "GPIO26", "GPIO27", "RGMII_MDIO", "RGMIO_MDC", /* Used by BT module */ - "CTS0", + "CTS0", /* 30 */ "RTS0", "TXD0", "RXD0", /* Used by Wifi */ "SD1_CLK", - "SD1_CMD", + "SD1_CMD", /* 35 */ "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* Shared with SPI flash */ - "PWM0_MISO", + "PWM0_MISO", /* 40 */ "PWM1_MOSI", "STATUS_LED_G_CLK", "SPIFLASH_CE_N", "SDA0", - "SCL0", + "SCL0", /* 45 */ "RGMII_RXCLK", "RGMII_RXCTL", "RGMII_RXD0", "RGMII_RXD1", - "RGMII_RXD2", + "RGMII_RXD2", /* 50 */ "RGMII_RXD3", "RGMII_TXCLK", "RGMII_TXCTL", "RGMII_TXD0", - "RGMII_TXD1", + "RGMII_TXD1", /* 55 */ "RGMII_TXD2", "RGMII_TXD3"; }; -- cgit From 13391025039fe86c68741e45a8b7bc158c69d68e Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Thu, 2 Dec 2021 15:14:13 -0800 Subject: ARM: dts: Cygnus: Fixed iProc PCIe controller properties Rename the msi controller unit name to 'msi' to avoid collisions with the 'msi-controller' boolean property. We also need to re-arrange the 'ranges' property to show the two cells as being separate instead of combined since the DT checker is not able to differentiate otherwise. Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-cygnus.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index 8ecb7861ce10..e73a19409d71 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -274,8 +274,8 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - ranges = <0x81000000 0 0 0x28000000 0 0x00010000 - 0x82000000 0 0x20000000 0x20000000 0 0x04000000>; + ranges = <0x81000000 0 0 0x28000000 0 0x00010000>, + <0x82000000 0 0x20000000 0x20000000 0 0x04000000>; phys = <&pcie0_phy>; phy-names = "pcie-phy"; @@ -283,7 +283,7 @@ status = "disabled"; msi-parent = <&msi0>; - msi0: msi-controller { + msi0: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; @@ -309,8 +309,8 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - ranges = <0x81000000 0 0 0x48000000 0 0x00010000 - 0x82000000 0 0x40000000 0x40000000 0 0x04000000>; + ranges = <0x81000000 0 0 0x48000000 0 0x00010000>, + <0x82000000 0 0x40000000 0x40000000 0 0x04000000>; phys = <&pcie1_phy>; phy-names = "pcie-phy"; @@ -318,7 +318,7 @@ status = "disabled"; msi-parent = <&msi1>; - msi1: msi-controller { + msi1: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; -- cgit From 89b9492c113c4a22361f32639c6af041bcada2b6 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 7 Dec 2021 16:06:22 -0800 Subject: ARM: dts: Cygnus: Update PCIe PHY node unit name(s) Update the PCIe PHY node unit name and its sub-nodes to help with upcoming changes converting the Cygnus PCIe PHY DT binding to YAML and later the iProc PCIe controller binding to YAML. Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-cygnus.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index e73a19409d71..ad65be871938 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -112,18 +112,18 @@ status = "disabled"; }; - pcie_phy: phy@301d0a0 { + pcie_phy: pcie_phy@301d0a0 { compatible = "brcm,cygnus-pcie-phy"; reg = <0x0301d0a0 0x14>; #address-cells = <1>; #size-cells = <0>; - pcie0_phy: phy@0 { + pcie0_phy: pcie-phy@0 { reg = <0>; #phy-cells = <0>; }; - pcie1_phy: phy@1 { + pcie1_phy: pcie-phy@1 { reg = <1>; #phy-cells = <0>; }; -- cgit From d2b820bb16c509b313b87f616dcf6aa612d01fb9 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Thu, 2 Dec 2021 15:15:27 -0800 Subject: ARM: dts: HR2: Fixed iProc PCIe MSI sub-node Rename the msi controller unit name to 'msi' to avoid collisions with the 'msi-controller' boolean property. Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-hr2.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/bcm-hr2.dtsi b/arch/arm/boot/dts/bcm-hr2.dtsi index 84cda16f68a2..33e6ba63a1ee 100644 --- a/arch/arm/boot/dts/bcm-hr2.dtsi +++ b/arch/arm/boot/dts/bcm-hr2.dtsi @@ -318,7 +318,7 @@ status = "disabled"; msi-parent = <&msi0>; - msi0: msi-controller { + msi0: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; @@ -354,7 +354,7 @@ status = "disabled"; msi-parent = <&msi1>; - msi1: msi-controller { + msi1: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; -- cgit From 69c4e53bdd055ecc27761f6971a50c631ff9072e Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Thu, 2 Dec 2021 15:16:27 -0800 Subject: ARM: dts: NSP: Fixed iProc PCIe MSI sub-node Rename the msi controller unit name to 'msi' to avoid collisions with the 'msi-controller' boolean property. Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index 1c08daa18858..f242763c3bde 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -587,7 +587,7 @@ status = "disabled"; msi-parent = <&msi0>; - msi0: msi-controller { + msi0: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; @@ -624,7 +624,7 @@ status = "disabled"; msi-parent = <&msi1>; - msi1: msi-controller { + msi1: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; @@ -661,7 +661,7 @@ status = "disabled"; msi-parent = <&msi2>; - msi2: msi-controller { + msi2: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; -- cgit From 9a68c53f875e88edd3403c001ad85f4ac0ed3486 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 7 Dec 2021 10:19:09 -0800 Subject: ARM: dts: NSP: Rename SATA unit name Rename the SATA controller unit name from ahci to sata in preparation for adding the Broadcom SATA3 controller YAML binding which will bring validation. Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index f242763c3bde..5b1dc58d40ba 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -534,7 +534,7 @@ }; }; - sata: ahci@41000 { + sata: sata@41000 { compatible = "brcm,bcm-nsp-ahci"; reg-names = "ahci", "top-ctrl"; reg = <0x41000 0x1000>, <0x40020 0x1c>; -- cgit From 5e33f1c4a7cb914a003a304ab8eef705b17aabb7 Mon Sep 17 00:00:00 2001 From: Arınç ÜNAL Date: Fri, 17 Dec 2021 00:03:19 +0800 Subject: ARM: dts: BCM5301X: correct RX delay and enable flow control on Asus RT-AC88U MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The current 'rx-internal-delay-ps' property value on the Realtek switch node, 2000, will be divided by 300, resulting in 6.66, which will be rounded to the closest step value, 7. Change it to 2100 to be accurate. See ef136837aaf6 ("net: dsa: rtl8365mb: set RGMII RX delay in steps of 0.3 ns") for reference. Flow control needs to be enabled on both sides of the internal and external switch. It is already enabled on the CPU port of the Realtek switch so we also enable it on the external switch port of the Broadcom switch as well. Signed-off-by: Arınç ÜNAL Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts index 16dea851719f..df8199fd4eb4 100644 --- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts +++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts @@ -138,7 +138,7 @@ ethernet = <&sw0_p5>; phy-mode = "rgmii"; tx-internal-delay-ps = <2000>; - rx-internal-delay-ps = <2000>; + rx-internal-delay-ps = <2100>; fixed-link { speed = <1000>; @@ -213,6 +213,7 @@ fixed-link { speed = <1000>; full-duplex; + pause; }; }; -- cgit