From 5418e4604ab982772a7274d9ec5b59296e822d7c Mon Sep 17 00:00:00 2001
From: Javier Martinez Canillas <javier@osg.samsung.com>
Date: Fri, 9 Sep 2016 10:01:02 -0400
Subject: ARM: dts: rockchip: Remove skeleton.dtsi inclusion in rk3036.dtsi
The skeleton.dtsi file was removed in ARM64 for different reasons as
explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi").
These also applies to ARM and it will also allow to get rid of the
following DTC warnings in the future:
"Node /memory has a reg or ranges property, but no unit name"
The disassembled DTB are almost the same, besides empty chosen nodes
being removed. So the change should not have a functional impact.
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/boot/dts/rk3036.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index a935523a1eb8..81691ae50199 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -44,9 +44,11 @@
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3036-cru.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
-#include "skeleton.dtsi"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
compatible = "rockchip,rk3036";
interrupt-parent = <&gic>;
--
cgit
From 0193273d99efbd7b8a8c5695505d0385470297f5 Mon Sep 17 00:00:00 2001
From: Javier Martinez Canillas <javier@osg.samsung.com>
Date: Fri, 9 Sep 2016 10:01:03 -0400
Subject: ARM: dts: rockchip: Remove skeleton.dtsi inclusion in rk322x.dtsi
The skeleton.dtsi file was removed in ARM64 for different reasons as
explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi").
These also applies to ARM and it will also allow to get rid of the
following DTC warnings in the future:
"Node /memory has a reg or ranges property, but no unit name"
The disassembled DTB are almost the same, besides empty chosen nodes
being removed. So the change should not have a functional impact.
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/boot/dts/rk322x.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index 9e6bf0e311bb..6ea8126d7a5f 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -44,9 +44,11 @@
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3228-cru.h>
#include <dt-bindings/thermal/thermal.h>
-#include "skeleton.dtsi"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
interrupt-parent = <&gic>;
aliases {
--
cgit
From c6b2d392093c891ccaeb95f734259f59fd236e1e Mon Sep 17 00:00:00 2001
From: Javier Martinez Canillas <javier@osg.samsung.com>
Date: Fri, 9 Sep 2016 10:01:04 -0400
Subject: ARM: dts: rockchip: Remove skeleton.dtsi inclusion in rk3288.dtsi
The skeleton.dtsi file was removed in ARM64 for different reasons as
explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi").
These also applies to ARM and it will also allow to get rid of the
following DTC warnings in the future:
"Node /memory has a reg or ranges property, but no unit name"
The disassembled DTB are almost the same, besides empty chosen nodes
being removed. So the change should not have a functional impact.
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/boot/dts/rk3288.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 17ec2e2d7a60..2cf1eb2e6202 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -46,9 +46,11 @@
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/power/rk3288-power.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
-#include "skeleton.dtsi"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
compatible = "rockchip,rk3288";
interrupt-parent = <&gic>;
--
cgit
From 80f6defc921debc3401f092c7d2373dd312c1ce0 Mon Sep 17 00:00:00 2001
From: Javier Martinez Canillas <javier@osg.samsung.com>
Date: Fri, 9 Sep 2016 10:01:05 -0400
Subject: ARM: dts: rockchip: Remove skeleton.dtsi inclusion in rk3xxx.dtsi
The skeleton.dtsi file was removed in ARM64 for different reasons as
explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi").
These also applies to ARM and it will also allow to get rid of the
following DTC warnings in the future:
"Node /memory has a reg or ranges property, but no unit name"
The disassembled DTB are almost the same, besides empty chosen nodes
being removed. So the change should not have a functional impact.
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/boot/dts/rk3xxx.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index e15beb3c671e..0394312f392d 100644
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -44,9 +44,11 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
-#include "skeleton.dtsi"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
interrupt-parent = <&gic>;
aliases {
--
cgit
From 4c2b306f69cdb545824ca2a18321e93d36d82575 Mon Sep 17 00:00:00 2001
From: Javier Martinez Canillas <javier@osg.samsung.com>
Date: Fri, 9 Sep 2016 10:01:06 -0400
Subject: ARM: dts: rockchip: Add missing unit name to memory nodes in rk3036
boards
This patch fixes the following DTC warnings:
"Node /memory has a reg or ranges property, but no unit name"
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/boot/dts/rk3036-evb.dts | 2 +-
arch/arm/boot/dts/rk3036-kylin.dts | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/rk3036-evb.dts b/arch/arm/boot/dts/rk3036-evb.dts
index 8db9e9b197a2..2f5f15524fba 100644
--- a/arch/arm/boot/dts/rk3036-evb.dts
+++ b/arch/arm/boot/dts/rk3036-evb.dts
@@ -46,7 +46,7 @@
model = "Rockchip RK3036 Evaluation board";
compatible = "rockchip,rk3036-evb", "rockchip,rk3036";
- memory {
+ memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts
index 1df1557a46c3..3de958ec29c0 100644
--- a/arch/arm/boot/dts/rk3036-kylin.dts
+++ b/arch/arm/boot/dts/rk3036-kylin.dts
@@ -46,7 +46,7 @@
model = "Rockchip RK3036 KylinBoard";
compatible = "rockchip,rk3036-kylin", "rockchip,rk3036";
- memory {
+ memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x20000000>;
};
--
cgit
From 09fbc4a08e8c5b08540dd6758c6951f52b4b4e5f Mon Sep 17 00:00:00 2001
From: Javier Martinez Canillas <javier@osg.samsung.com>
Date: Fri, 9 Sep 2016 10:01:07 -0400
Subject: ARM: dts: rockchip: Add missing unit name to memory nodes in rk322x
boards
This patch fixes the following DTC warnings:
"Node /memory has a reg or ranges property, but no unit name"
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/boot/dts/rk3228-evb.dts | 2 +-
arch/arm/boot/dts/rk3229-evb.dts | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/rk3228-evb.dts b/arch/arm/boot/dts/rk3228-evb.dts
index 904668e2e666..58834330a5ba 100644
--- a/arch/arm/boot/dts/rk3228-evb.dts
+++ b/arch/arm/boot/dts/rk3228-evb.dts
@@ -46,7 +46,7 @@
model = "Rockchip RK3228 Evaluation board";
compatible = "rockchip,rk3228-evb", "rockchip,rk3228";
- memory {
+ memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/rk3229-evb.dts b/arch/arm/boot/dts/rk3229-evb.dts
index b6a12035a6bb..dcdd0cee619e 100644
--- a/arch/arm/boot/dts/rk3229-evb.dts
+++ b/arch/arm/boot/dts/rk3229-evb.dts
@@ -46,7 +46,7 @@
model = "Rockchip RK3229 Evaluation board";
compatible = "rockchip,rk3229-evb", "rockchip,rk3229";
- memory {
+ memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x40000000>;
};
--
cgit
From 0b639b815f15e70bd01c6e07c135828051a574c2 Mon Sep 17 00:00:00 2001
From: Javier Martinez Canillas <javier@osg.samsung.com>
Date: Fri, 9 Sep 2016 10:01:08 -0400
Subject: ARM: dts: rockchip: Add missing unit name to memory nodes in rk3288
boards
This patch fixes the following DTC warnings:
"Node /memory has a reg or ranges property, but no unit name"
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/boot/dts/rk3288-evb.dtsi | 2 +-
arch/arm/boot/dts/rk3288-fennec.dts | 2 +-
arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi | 2 +-
arch/arm/boot/dts/rk3288-firefly.dtsi | 2 +-
arch/arm/boot/dts/rk3288-miqi.dts | 2 +-
arch/arm/boot/dts/rk3288-popmetal.dts | 2 +-
arch/arm/boot/dts/rk3288-r89.dts | 2 +-
arch/arm/boot/dts/rk3288-rock2-som.dtsi | 2 +-
arch/arm/boot/dts/rk3288-veyron.dtsi | 2 +-
9 files changed, 9 insertions(+), 9 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi
index d59208b5eb6c..bf7ccfad3260 100644
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -43,7 +43,7 @@
#include "rk3288.dtsi"
/ {
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x0 0x80000000>;
};
diff --git a/arch/arm/boot/dts/rk3288-fennec.dts b/arch/arm/boot/dts/rk3288-fennec.dts
index 2e3c34135ed8..805c0d26770b 100644
--- a/arch/arm/boot/dts/rk3288-fennec.dts
+++ b/arch/arm/boot/dts/rk3288-fennec.dts
@@ -46,7 +46,7 @@
model = "Rockchip RK3288 Fennec Board";
compatible = "rockchip,rk3288-fennec", "rockchip,rk3288";
- memory {
+ memory@0 {
reg = <0x0 0x80000000>;
device_type = "memory";
};
diff --git a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi
index ec418c99de95..d242588bae0d 100644
--- a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi
+++ b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi
@@ -45,7 +45,7 @@
#include "rk3288.dtsi"
/ {
- memory {
+ memory@0 {
device_type = "memory";
reg = <0 0x80000000>;
};
diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi
index 114c90fb65e2..44935af1fb0e 100644
--- a/arch/arm/boot/dts/rk3288-firefly.dtsi
+++ b/arch/arm/boot/dts/rk3288-firefly.dtsi
@@ -44,7 +44,7 @@
#include "rk3288.dtsi"
/ {
- memory {
+ memory@0 {
device_type = "memory";
reg = <0 0x80000000>;
};
diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
index 24488421f0f0..441d450fd151 100644
--- a/arch/arm/boot/dts/rk3288-miqi.dts
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
@@ -52,7 +52,7 @@
stdout-path = "serial2:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0 0x80000000>;
};
diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts
index 56dd377d5658..23003a221234 100644
--- a/arch/arm/boot/dts/rk3288-popmetal.dts
+++ b/arch/arm/boot/dts/rk3288-popmetal.dts
@@ -48,7 +48,7 @@
model = "PopMetal-RK3288";
compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288";
- memory{
+ memory@0 {
device_type = "memory";
reg = <0 0x80000000>;
};
diff --git a/arch/arm/boot/dts/rk3288-r89.dts b/arch/arm/boot/dts/rk3288-r89.dts
index 4b8a8adb243c..04faa72dbd95 100644
--- a/arch/arm/boot/dts/rk3288-r89.dts
+++ b/arch/arm/boot/dts/rk3288-r89.dts
@@ -48,7 +48,7 @@
/ {
compatible = "netxeon,r89", "rockchip,rk3288";
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x0 0x80000000>;
};
diff --git a/arch/arm/boot/dts/rk3288-rock2-som.dtsi b/arch/arm/boot/dts/rk3288-rock2-som.dtsi
index bb1f01e037ba..b25ba806d5ee 100644
--- a/arch/arm/boot/dts/rk3288-rock2-som.dtsi
+++ b/arch/arm/boot/dts/rk3288-rock2-som.dtsi
@@ -42,7 +42,7 @@
#include "rk3288.dtsi"
/ {
- memory {
+ memory@0 {
reg = <0x0 0x80000000>;
device_type = "memory";
};
diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi
index 3dd2cca48c11..2251d28e9d2a 100644
--- a/arch/arm/boot/dts/rk3288-veyron.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi
@@ -47,7 +47,7 @@
#include "rk3288.dtsi"
/ {
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x0 0x80000000>;
};
--
cgit
From adc9e3a688409eb8f1ad809eca09be830518570c Mon Sep 17 00:00:00 2001
From: Javier Martinez Canillas <javier@osg.samsung.com>
Date: Fri, 9 Sep 2016 10:01:09 -0400
Subject: ARM: dts: rockchip: Add missing unit name to memory nodes in rk3xxx
boards
This patch fixes the following DTC warnings:
"Node /memory has a reg or ranges property, but no unit name"
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/boot/dts/rk3066a-bqcurie2.dts | 2 +-
arch/arm/boot/dts/rk3066a-marsboard.dts | 2 +-
arch/arm/boot/dts/rk3066a-rayeager.dts | 2 +-
arch/arm/boot/dts/rk3188-radxarock.dts | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
index bc674ee206ec..c0d8b5446ba7 100644
--- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts
+++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
@@ -49,7 +49,7 @@
model = "bq Curie 2";
compatible = "mundoreader,bq-curie2", "rockchip,rk3066a";
- memory {
+ memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/rk3066a-marsboard.dts b/arch/arm/boot/dts/rk3066a-marsboard.dts
index a2b763e949b4..0a54c4beff8d 100644
--- a/arch/arm/boot/dts/rk3066a-marsboard.dts
+++ b/arch/arm/boot/dts/rk3066a-marsboard.dts
@@ -47,7 +47,7 @@
model = "MarsBoard RK3066";
compatible = "haoyu,marsboard-rk3066", "rockchip,rk3066a";
- memory {
+ memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts
index 6e7f2187a0e3..82465b644443 100644
--- a/arch/arm/boot/dts/rk3066a-rayeager.dts
+++ b/arch/arm/boot/dts/rk3066a-rayeager.dts
@@ -48,7 +48,7 @@
model = "Rayeager PX2";
compatible = "chipspark,rayeager-px2", "rockchip,rk3066a";
- memory {
+ memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts
index 1da46d138029..5e8a235ed02d 100644
--- a/arch/arm/boot/dts/rk3188-radxarock.dts
+++ b/arch/arm/boot/dts/rk3188-radxarock.dts
@@ -48,7 +48,7 @@
model = "Radxa Rock";
compatible = "radxa,rock", "rockchip,rk3188";
- memory {
+ memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x80000000>;
};
--
cgit
From 3f22c76b21b59870b7dbc9263c8651844f92e294 Mon Sep 17 00:00:00 2001
From: Andy Yan <andy.yan@rock-chips.com>
Date: Sun, 11 Sep 2016 01:44:00 +0800
Subject: ARM: dts: rockchip: add rockchip PX3 Evaluation board
PX3 EVB is designed by Rockchip for automotive field,
with integrated CVBS (TP2825) / MIPI DSI / LVDS / HDMI
video input/output interface, WIFI/BT/GPS (on a module
named S500 which based on MT6620), Gsensor BMA250E and
light&proximity sensor STK3410.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/rk3188-px3-evb.dts | 330 +++++++++++++++++++++++++++++++++++
2 files changed, 331 insertions(+)
create mode 100644 arch/arm/boot/dts/rk3188-px3-evb.dts
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index befcd2619902..0df336c66a44 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -640,6 +640,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3066a-bqcurie2.dtb \
rk3066a-marsboard.dtb \
rk3066a-rayeager.dtb \
+ rk3188-px3-evb.dtb \
rk3188-radxarock.dtb \
rk3228-evb.dtb \
rk3229-evb.dtb \
diff --git a/arch/arm/boot/dts/rk3188-px3-evb.dts b/arch/arm/boot/dts/rk3188-px3-evb.dts
new file mode 100644
index 000000000000..79a5f17b1694
--- /dev/null
+++ b/arch/arm/boot/dts/rk3188-px3-evb.dts
@@ -0,0 +1,330 @@
+/*
+ * Copyright (c) 2016 Andy Yan <andy.yan@rock-chips.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include "rk3188.dtsi"
+
+/ {
+ model = "Rockchip PX3-EVB";
+ compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188";
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ memory@60000000 {
+ reg = <0x60000000 0x80000000>;
+ device_type = "memory";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+
+ power {
+ gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ label = "GPIO Key Power";
+ linux,input-type = <1>;
+ wakeup-source;
+ debounce-interval = <100>;
+ };
+ };
+
+ vcc_sys: vsys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vsys";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ };
+};
+
+&cpu0 {
+ cpu0-supply = <&vdd_cpu>;
+};
+
+&emmc {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ disable-wp;
+ non-removable;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_rst>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ accelerometer@18 {
+ compatible = "bosch,bma250";
+ reg = <0x18>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ rk808: pmic@1c {
+ compatible = "rockchip,rk818";
+ reg = <0x1c>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ rockchip,system-power-controller;
+ wakeup-source;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk808-clkout2";
+
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc6-supply = <&vcc_sys>;
+ vcc7-supply = <&vcc_sys>;
+ vcc8-supply = <&vcc_io>;
+ vcc9-supply = <&vcc_io>;
+
+ regulators {
+ vdd_cpu: DCDC_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-name = "vdd_arm";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-name = "vdd_gpu";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc_ddr";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_io: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_io";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_cif: LDO_REG1 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_cif";
+ };
+
+ vcc_jetta33: LDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_jetta33";
+ };
+
+ vdd_10: LDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-name = "vdd_10";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ lvds_12: LDO_REG4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "lvds_12";
+ };
+
+ lvds_25: LDO_REG5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "lvds_25";
+ };
+
+ cif_18: LDO_REG6 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-name = "cif_18";
+ };
+
+ vcc_sd: LDO_REG7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_sd";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ wl_18: LDO_REG8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "wl_18";
+ };
+
+ lcd_33: SWITCH_REG1 {
+ regulator-name = "lcd_33";
+ };
+ };
+ };
+
+};
+
+&i2c2 {
+ gsl1680: touchscreen@40 {
+ compatible = "silead,gsl1680";
+ reg = <0x40>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
+ power-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+ touchscreen-size-x = <800>;
+ touchscreen-size-y = <1280>;
+ silead,max-fingers = <5>;
+ };
+};
+
+&mmc0 {
+ num-slots = <1>;
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
+ vmmc-supply = <&vcc_sd>;
+
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+};
+
+&pinctrl {
+ pcfg_output_low: pcfg-output-low {
+ output-low;
+ };
+
+ usb {
+ host_vbus_drv: host-vbus-drv {
+ rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ otg_vbus_drv: otg-vbus-drv {
+ rockchip,pins = <2 31 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&pwm3 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
+
+&usb_host {
+ status = "okay";
+};
+
+&usb_otg {
+ status = "okay";
+};
+
+&wdt {
+ status = "okay";
+};
--
cgit
From 85b72602df53ee555ca7d457bcc009fb36fbc0be Mon Sep 17 00:00:00 2001
From: Finley Xiao <finley.xiao@rock-chips.com>
Date: Thu, 1 Sep 2016 20:16:55 -0700
Subject: ARM: dts: rockchip: update compatible strings for Rockchip efuse
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/boot/dts/rk3066a.dtsi | 2 +-
arch/arm/boot/dts/rk3188.dtsi | 2 +-
arch/arm/boot/dts/rk3288.dtsi | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index 0d0dae3a1694..b8c83d80593f 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -162,7 +162,7 @@
};
efuse: efuse@20010000 {
- compatible = "rockchip,rockchip-efuse";
+ compatible = "rockchip,rk3066a-efuse";
reg = <0x20010000 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index 31f81b265cef..869e189331ec 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -147,7 +147,7 @@
};
efuse: efuse@20010000 {
- compatible = "rockchip,rockchip-efuse";
+ compatible = "rockchip,rk3188-efuse";
reg = <0x20010000 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 2cf1eb2e6202..2f814ffeb605 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -1118,7 +1118,7 @@
};
efuse: efuse@ffb40000 {
- compatible = "rockchip,rockchip-efuse";
+ compatible = "rockchip,rk3288-efuse";
reg = <0xffb40000 0x20>;
#address-cells = <1>;
#size-cells = <1>;
--
cgit
From 3a2766cc68e7caa564e1bd56376d2a13cfa687c4 Mon Sep 17 00:00:00 2001
From: Shawn Lin <shawn.lin@rock-chips.com>
Date: Fri, 23 Sep 2016 08:09:10 +0800
Subject: ARM: dts: rockchip: remove always-on and boot-on from vcc_sd for
px3-evb
Please don't add these for vcc_sd, and mmc-core/driver will control
it. Otherwise, it will waste energy even without sdmmc in slot.
Moreover, it will causes a bug:
If we insert/remove sd card, we could see
[9.337271] mmc0: new ultra high speed SDR25 SDHC card at address 0007
[9.345144] mmcblk0: mmc0:0007 SD32G 29.3 GiB
This is okay for normal sd insert/remove test, but when I debug some
issues for sdmmc, I did unbind/bind test. And there is a interesting
phenomenon when we bind the driver again:
[58.314069] mmc0: new high speed SDHC card at address 0007
[58.320282] mmcblk0: mmc0:0007 SD32G 29.3 GiB
So the sd card could just support high speed without power cycle
since the vcc_sd is always on, which makes the sd card fail to
reinit its internal ocr mask.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/boot/dts/rk3188-px3-evb.dts | 2 --
1 file changed, 2 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/rk3188-px3-evb.dts b/arch/arm/boot/dts/rk3188-px3-evb.dts
index 79a5f17b1694..df727bafd6dc 100644
--- a/arch/arm/boot/dts/rk3188-px3-evb.dts
+++ b/arch/arm/boot/dts/rk3188-px3-evb.dts
@@ -219,8 +219,6 @@
};
vcc_sd: LDO_REG7 {
- regulator-always-on;
- regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_sd";
--
cgit
From 9daa25528c31d3a9e093d13360ea5edb16876e50 Mon Sep 17 00:00:00 2001
From: Shawn Lin <shawn.lin@rock-chips.com>
Date: Mon, 10 Oct 2016 20:33:45 +0800
Subject: ARM: dts: rockchip: Support UHS mode for SD card on PopMetal-RK3288
board
PopMetal-RK3288 board could enable SD3.0 card but need vccio_sd
to support the voltage range from 1V8 to 3V3 and we also need to
add more UHS mode here.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/boot/dts/rk3288-popmetal.dts | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts
index 23003a221234..3831cd5e470d 100644
--- a/arch/arm/boot/dts/rk3288-popmetal.dts
+++ b/arch/arm/boot/dts/rk3288-popmetal.dts
@@ -165,6 +165,10 @@
num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
vmmc-supply = <&vcc_sd>;
vqmmc-supply = <&vccio_sd>;
status = "okay";
@@ -280,7 +284,7 @@
vccio_sd: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
- regulator-min-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_sd";
regulator-state-mem {
--
cgit
From 864c9c021fe6d50446e1f8accb65e4afdffd62fa Mon Sep 17 00:00:00 2001
From: Shawn Lin <shawn.lin@rock-chips.com>
Date: Mon, 10 Oct 2016 20:33:46 +0800
Subject: ARM: dts: rockchip: enable HS200/DDR52 mode for emmc on
rk3288-popmetal
Enable these two modes to speed up the booting and improve
the performance.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/boot/dts/rk3288-popmetal.dts | 2 ++
1 file changed, 2 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts
index 3831cd5e470d..3bf1fc3ba31b 100644
--- a/arch/arm/boot/dts/rk3288-popmetal.dts
+++ b/arch/arm/boot/dts/rk3288-popmetal.dts
@@ -147,6 +147,8 @@
bus-width = <8>;
cap-mmc-highspeed;
disable-wp;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
non-removable;
num-slots = <1>;
pinctrl-names = "default";
--
cgit
From 6c35a666566cf48faaa95699b0d79c6b8cad824c Mon Sep 17 00:00:00 2001
From: Chris Brandt <chris.brandt@renesas.com>
Date: Thu, 15 Sep 2016 15:34:02 -0400
Subject: ARM: dts: r7s72100: add mmcif clock to device tree
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r7s72100.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index fb9ef9ca120e..e18d4e645d6e 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -117,6 +117,15 @@
clock-output-names = "ether";
};
+ mstp8_clks: mstp8_clks@fcfe0434 {
+ #clock-cells = <1>;
+ compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+ reg = <0xfcfe0434 4>;
+ clocks = <&p1_clk>;
+ clock-indices = <R7S72100_CLK_MMCIF>;
+ clock-output-names = "mmcif";
+ };
+
mstp9_clks: mstp9_clks@fcfe0438 {
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
--
cgit
From 1efd670a73a6ac1be3126f48f2025a6e9f173ba1 Mon Sep 17 00:00:00 2001
From: Simon Horman <horms+renesas@verge.net.au>
Date: Tue, 13 Sep 2016 12:57:01 +0200
Subject: ARM: dts: r8a7791: set maximum frequency for SDHI clocks
Define the upper limit otherwise the driver cannot utilize max speeds.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7791.dtsi | 3 +++
1 file changed, 3 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 162b55c665a3..b07c799f72f2 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -584,6 +584,7 @@
dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
<&dmac1 0xcd>, <&dmac1 0xce>;
dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <195000000>;
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
status = "disabled";
};
@@ -596,6 +597,7 @@
dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
<&dmac1 0xc1>, <&dmac1 0xc2>;
dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
status = "disabled";
};
@@ -608,6 +610,7 @@
dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
<&dmac1 0xd3>, <&dmac1 0xd4>;
dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
status = "disabled";
};
--
cgit
From 7f43049b40505cf21a01667a6ad42e6a3df6e4de Mon Sep 17 00:00:00 2001
From: Vladimir Murzin <vladimir.murzin@arm.com>
Date: Mon, 17 Oct 2016 12:47:29 +0100
Subject: ARM: dts: mps2: remove skeleton.dtsi include and fix unit address
warnings
Removale of skeleton.dtsi allows us also to fix the following
warning from the dts compiler:
Warning (unit_address_vs_reg): Node /memory has a reg or ranges
property, but no unit name
by adding proper unit addresses to the memory nodes.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
---
arch/arm/boot/dts/mps2-an385.dts | 2 +-
arch/arm/boot/dts/mps2-an399.dts | 2 +-
arch/arm/boot/dts/mps2.dtsi | 4 +++-
3 files changed, 5 insertions(+), 3 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/mps2-an385.dts b/arch/arm/boot/dts/mps2-an385.dts
index 31c374d72a6f..aebbebfc25d1 100644
--- a/arch/arm/boot/dts/mps2-an385.dts
+++ b/arch/arm/boot/dts/mps2-an385.dts
@@ -59,7 +59,7 @@
stdout-path = "serial0:9600n8";
};
- memory {
+ memory@21000000 {
device_type = "memory";
reg = <0x21000000 0x1000000>;
};
diff --git a/arch/arm/boot/dts/mps2-an399.dts b/arch/arm/boot/dts/mps2-an399.dts
index 5e7e5ca2edbf..349abf70b2a5 100644
--- a/arch/arm/boot/dts/mps2-an399.dts
+++ b/arch/arm/boot/dts/mps2-an399.dts
@@ -59,7 +59,7 @@
stdout-path = "serial0:9600n8";
};
- memory {
+ memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x1000000>;
};
diff --git a/arch/arm/boot/dts/mps2.dtsi b/arch/arm/boot/dts/mps2.dtsi
index efb8a03cb970..23467390558d 100644
--- a/arch/arm/boot/dts/mps2.dtsi
+++ b/arch/arm/boot/dts/mps2.dtsi
@@ -42,10 +42,12 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include "skeleton.dtsi"
#include "armv7-m.dtsi"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
oscclk0: clk-osc0 {
compatible = "fixed-clock";
#clock-cells = <0>;
--
cgit
From 83a70ff01a25eaf0761f30451a8335946a33c59e Mon Sep 17 00:00:00 2001
From: Uwe Kleine-König <uwe@kleine-koenig.org>
Date: Thu, 29 Sep 2016 20:22:05 +0200
Subject: ARM: dts: armada-370-rn104: add pinmuxing for i2c0
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Up to now a working i2c bus depended on the bootloader to configure the
pinmuxing. Make it explicit.
As a side effect this change makes i2c work in barebox.
Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm/boot/dts/armada-370-netgear-rn104.dts | 4 ++++
1 file changed, 4 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
index 11565752b9f6..d44a850d879c 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
@@ -128,6 +128,10 @@
i2c@11000 {
compatible = "marvell,mv64xxx-i2c";
clock-frequency = <100000>;
+
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+
status = "okay";
isl12057: isl12057@68 {
--
cgit
From 43940ce3b089962f97de544d72b783bd146ef362 Mon Sep 17 00:00:00 2001
From: Uwe Kleine-König <uwe@kleine-koenig.org>
Date: Thu, 29 Sep 2016 20:22:06 +0200
Subject: ARM: dts: armada-370-rn104: drop specification of compatible for i2c0
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
The compatible string is already provided by armada-370.dtsi.
Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm/boot/dts/armada-370-netgear-rn104.dts | 1 -
1 file changed, 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
index d44a850d879c..14c379699350 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
@@ -126,7 +126,6 @@
};
i2c@11000 {
- compatible = "marvell,mv64xxx-i2c";
clock-frequency = <100000>;
pinctrl-0 = <&i2c0_pins>;
--
cgit
From fcfd3da305ad108c9fc255b3b106edab5840c8c3 Mon Sep 17 00:00:00 2001
From: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Date: Thu, 29 Sep 2016 20:52:21 +0200
Subject: ARM: dts: armada-xp-rn2120: drop wrong compatible for i2c0
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
The compatible is supposed to be "marvell,mv78230-i2c", "marvell,mv64xxx-i2c",
as provided by armada-xp.dtsi.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm/boot/dts/armada-xp-netgear-rn2120.dts | 1 -
1 file changed, 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
index d19f44c70925..3e930fdbaabc 100644
--- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
+++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
@@ -97,7 +97,6 @@
};
i2c@11000 {
- compatible = "marvell,mv64xxx-i2c";
clock-frequency = <400000>;
status = "okay";
--
cgit
From ae6f00209dcbaad41ab0645c3f9109b3eae7ba05 Mon Sep 17 00:00:00 2001
From: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Date: Thu, 29 Sep 2016 21:00:10 +0200
Subject: ARM: dts: armada-xp-rn2120: add pinmuxing for ethernet
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Up to now working ethernet depended on the bootloader to configure the
pinmuxing. Make it explicit.
As a side effect this change makes ethernet work in barebox.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm/boot/dts/armada-xp-netgear-rn2120.dts | 6 ++++++
1 file changed, 6 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
index 3e930fdbaabc..b6bf5344fbbe 100644
--- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
+++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
@@ -164,12 +164,18 @@
};
ethernet@70000 {
+ pinctrl-0 = <&ge0_rgmii_pins>;
+ pinctrl-names = "default";
+
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
ethernet@74000 {
+ pinctrl-0 = <&ge1_rgmii_pins>;
+ pinctrl-names = "default";
+
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
--
cgit
From 69d7fbb0faf41821d89b4172f5271727f6900fec Mon Sep 17 00:00:00 2001
From: Sylwester Nawrocki <s.nawrocki@samsung.com>
Date: Fri, 16 Sep 2016 10:33:45 +0200
Subject: ARM: dts: exynos: Remove "simple-bus" compatible from fimc-is node
The "simple-bus" compatible was originally added for fimc-is only
to ensure the child devices instantiation. The child devices are
now being created by the parent device driver so remove the
"simple-bus" compatible.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/boot/dts/exynos4x12.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index 3394bdcf10ae..0074f566cd3b 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -147,7 +147,7 @@
};
fimc_is: fimc-is@12000000 {
- compatible = "samsung,exynos4212-fimc-is", "simple-bus";
+ compatible = "samsung,exynos4212-fimc-is";
reg = <0x12000000 0x260000>;
interrupts = <0 90 0>, <0 95 0>;
power-domains = <&pd_isp>;
--
cgit
From ad3b5ef7ee99530620cece4aeee2aa291d034905 Mon Sep 17 00:00:00 2001
From: Sylwester Nawrocki <s.nawrocki@samsung.com>
Date: Fri, 16 Sep 2016 13:22:00 +0200
Subject: ARM: dts: exynos: Add entries for sound support on Odroid-XU board
This patch adds device nodes for the AUDSS clock controller,
peripheral DMA 0/1 controllers and the Audio Subsystem I2S controller.
These entries are required for sound support on Odroid-XU board.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/boot/dts/exynos5410-odroidxu.dts | 69 +++++++++++++++++++++++++++++++
arch/arm/boot/dts/exynos5410-pinctrl.dtsi | 9 ++++
arch/arm/boot/dts/exynos5410.dtsi | 59 ++++++++++++++++++++++++++
3 files changed, 137 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts
index 3c271cb4b2be..c4de1353e5df 100644
--- a/arch/arm/boot/dts/exynos5410-odroidxu.dts
+++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts
@@ -15,6 +15,7 @@
#include <dt-bindings/clock/maxim,max77802.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/sound/samsung-i2s.h>
#include "exynos54xx-odroidxu-leds.dtsi"
/ {
@@ -57,6 +58,61 @@
compatible = "samsung,secure-firmware";
reg = <0x02073000 0x1000>;
};
+
+ sound: sound {
+ compatible = "simple-audio-card";
+
+ simple-audio-card,name = "Odroid-XU";
+ simple-audio-card,widgets =
+ "Headphone", "Headphone Jack",
+ "Speakers", "Speakers";
+ simple-audio-card,routing =
+ "Headphone Jack", "HPL",
+ "Headphone Jack", "HPR",
+ "Headphone Jack", "MICBIAS",
+ "IN1", "Headphone Jack",
+ "Speakers", "SPKL",
+ "Speakers", "SPKR";
+
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&link0_codec>;
+ simple-audio-card,frame-master = <&link0_codec>;
+
+ simple-audio-card,cpu {
+ sound-dai = <&audi2s0 0>;
+ system-clock-frequency = <19200000>;
+ };
+
+ link0_codec: simple-audio-card,codec {
+ sound-dai = <&max98090>;
+ clocks = <&audi2s0 CLK_I2S_CDCLK>;
+ };
+ };
+};
+
+&audi2s0 {
+ status = "okay";
+};
+
+&clock {
+ clocks = <&fin_pll>;
+ assigned-clocks = <&clock CLK_FOUT_EPLL>;
+ assigned-clock-rates = <192000000>;
+};
+
+&clock_audss {
+ assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
+ <&clock_audss EXYNOS_MOUT_I2S>,
+ <&clock_audss EXYNOS_DOUT_SRP>,
+ <&clock_audss EXYNOS_DOUT_AUD_BUS>;
+
+ assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
+ <&clock_audss EXYNOS_MOUT_AUDSS>;
+
+ assigned-clock-rates = <0>,
+ <0>,
+ <96000000>,
+ <19200000>;
};
&cpu0_thermal {
@@ -440,6 +496,19 @@
};
};
+&i2c_1 {
+ status = "okay";
+ max98090: max98090@10 {
+ compatible = "maxim,max98090";
+ reg = <0x10>;
+ interrupt-parent = <&gpj3>;
+ interrupts = <0 IRQ_TYPE_NONE>;
+ clocks = <&audi2s0 CLK_I2S_CDCLK>;
+ clock-names = "mclk";
+ #sound-dai-cells = <0>;
+ };
+};
+
&mmc_0 {
status = "okay";
mmc-pwrseq = <&emmc_pwrseq>;
diff --git a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi
index a083d23fdee3..ff46a1c27182 100644
--- a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi
@@ -615,4 +615,13 @@
interrupt-controller;
#interrupt-cells = <2>;
};
+
+ audi2s0_bus: audi2s0-bus {
+ samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
+ "gpz-4";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
};
diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
index 137f48464f8b..9a91685d8890 100644
--- a/arch/arm/boot/dts/exynos5410.dtsi
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -16,6 +16,7 @@
#include "exynos54xx.dtsi"
#include "exynos-syscon-restart.dtsi"
#include <dt-bindings/clock/exynos5410.h>
+#include <dt-bindings/clock/exynos-audss-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
@@ -82,6 +83,14 @@
#clock-cells = <1>;
};
+ clock_audss: audss-clock-controller@3810000 {
+ compatible = "samsung,exynos5410-audss-clock";
+ reg = <0x03810000 0x0C>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>, <&clock CLK_FOUT_EPLL>;
+ clock-names = "pll_ref", "pll_in";
+ };
+
tmu_cpu0: tmu@10060000 {
compatible = "samsung,exynos5420-tmu";
reg = <0x10060000 0x100>;
@@ -183,6 +192,56 @@
reg = <0x03860000 0x1000>;
interrupts = <0 47 0>;
};
+
+ amba {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ pdma0: pdma@12680000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x121A0000 0x1000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_NONE>;
+ clocks = <&clock CLK_PDMA0>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ };
+
+ pdma1: pdma@12690000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x121B0000 0x1000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
+ clocks = <&clock CLK_PDMA1>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ };
+ };
+
+ audi2s0: i2s@03830000 {
+ compatible = "samsung,exynos5420-i2s";
+ reg = <0x03830000 0x100>;
+ dmas = <&pdma0 10
+ &pdma0 9
+ &pdma0 8>;
+ dma-names = "tx", "rx", "tx-sec";
+ clocks = <&clock_audss EXYNOS_I2S_BUS>,
+ <&clock_audss EXYNOS_I2S_BUS>,
+ <&clock_audss EXYNOS_SCLK_I2S>;
+ clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
+ #clock-cells = <1>;
+ clock-output-names = "i2s_cdclk0";
+ #sound-dai-cells = <1>;
+ samsung,idma-addr = <0x03000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&audi2s0_bus>;
+ status = "disabled";
+ };
};
thermal-zones {
--
cgit
From b01c3994817dc4e117c5642c3e09e0a231b5b477 Mon Sep 17 00:00:00 2001
From: Juri Lelli <juri.lelli@arm.com>
Date: Mon, 17 Oct 2016 16:46:44 +0100
Subject: ARM: dts: vexpress: add TC2 cpu capacity-dmips-mhz information
Add TC2 cpu capacity information.
Cc: Liviu Dudau <liviu.dudau@arm.com>
Cc: Sudeep Holla <sudeep.holla@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: devicetree@vger.kernel.org
Signed-off-by: Juri Lelli <juri.lelli@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
---
arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 5 +++++
1 file changed, 5 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index 0205c97efdef..45d08cc37b01 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -39,6 +39,7 @@
reg = <0>;
cci-control-port = <&cci_control1>;
cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
+ capacity-dmips-mhz = <1024>;
};
cpu1: cpu@1 {
@@ -47,6 +48,7 @@
reg = <1>;
cci-control-port = <&cci_control1>;
cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
+ capacity-dmips-mhz = <1024>;
};
cpu2: cpu@2 {
@@ -55,6 +57,7 @@
reg = <0x100>;
cci-control-port = <&cci_control2>;
cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
+ capacity-dmips-mhz = <516>;
};
cpu3: cpu@3 {
@@ -63,6 +66,7 @@
reg = <0x101>;
cci-control-port = <&cci_control2>;
cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
+ capacity-dmips-mhz = <516>;
};
cpu4: cpu@4 {
@@ -71,6 +75,7 @@
reg = <0x102>;
cci-control-port = <&cci_control2>;
cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
+ capacity-dmips-mhz = <516>;
};
idle-states {
--
cgit
From 21ff843931b2e5a9b628ac56fd0f2e4355890096 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Mon, 19 Sep 2016 10:43:18 +0200
Subject: ARM: dts: bcm283x: Define standard pinctrl groups in the gpio node.
The BCM2835-ARM-Peripherals.pdf documentation specifies what the
function selects do for the pins, and there are a bunch of obvious
groupings to be made. With these created, we'll be able to replace
bcm2835-rpi.dtsi's main "set all of these pins to alt0" with
references to specific groups we want enabled.
Also add pinctrl groups for emmc and sdhost.
Based on patches by Eric Anholt, with fixups by Gerd Hoffmann.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
---
arch/arm/boot/dts/bcm283x.dtsi | 203 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 203 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi
index 46d46d894a44..2123d0eb1890 100644
--- a/arch/arm/boot/dts/bcm283x.dtsi
+++ b/arch/arm/boot/dts/bcm283x.dtsi
@@ -132,6 +132,209 @@
interrupt-controller;
#interrupt-cells = <2>;
+
+ /* Defines pin muxing groups according to
+ * BCM2835-ARM-Peripherals.pdf page 102.
+ *
+ * While each pin can have its mux selected
+ * for various functions individually, some
+ * groups only make sense to switch to a
+ * particular function together.
+ */
+ dpi_gpio0: dpi_gpio0 {
+ brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
+ 12 13 14 15 16 17 18 19
+ 20 21 22 23 24 25 26 27>;
+ brcm,function = <BCM2835_FSEL_ALT2>;
+ };
+ emmc_gpio22: emmc_gpio22 {
+ brcm,pins = <22 23 24 25 26 27>;
+ brcm,function = <BCM2835_FSEL_ALT3>;
+ };
+ emmc_gpio34: emmc_gpio34 {
+ brcm,pins = <34 35 36 37 38 39>;
+ brcm,function = <BCM2835_FSEL_ALT3>;
+ brcm,pull = <BCM2835_PUD_OFF
+ BCM2835_PUD_UP
+ BCM2835_PUD_UP
+ BCM2835_PUD_UP
+ BCM2835_PUD_UP
+ BCM2835_PUD_UP>;
+ };
+ emmc_gpio48: emmc_gpio48 {
+ brcm,pins = <48 49 50 51 52 53>;
+ brcm,function = <BCM2835_FSEL_ALT3>;
+ };
+
+ gpclk0_gpio4: gpclk0_gpio4 {
+ brcm,pins = <4>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ gpclk1_gpio5: gpclk1_gpio5 {
+ brcm,pins = <5>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ gpclk1_gpio42: gpclk1_gpio42 {
+ brcm,pins = <42>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ gpclk1_gpio44: gpclk1_gpio44 {
+ brcm,pins = <44>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ gpclk2_gpio6: gpclk2_gpio6 {
+ brcm,pins = <6>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ gpclk2_gpio43: gpclk2_gpio43 {
+ brcm,pins = <43>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+
+ i2c0_gpio0: i2c0_gpio0 {
+ brcm,pins = <0 1>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ i2c0_gpio32: i2c0_gpio32 {
+ brcm,pins = <32 34>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ i2c0_gpio44: i2c0_gpio44 {
+ brcm,pins = <44 45>;
+ brcm,function = <BCM2835_FSEL_ALT1>;
+ };
+ i2c1_gpio2: i2c1_gpio2 {
+ brcm,pins = <2 3>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ i2c1_gpio44: i2c1_gpio44 {
+ brcm,pins = <44 45>;
+ brcm,function = <BCM2835_FSEL_ALT2>;
+ };
+ i2c_slave_gpio18: i2c_slave_gpio18 {
+ brcm,pins = <18 19 20 21>;
+ brcm,function = <BCM2835_FSEL_ALT3>;
+ };
+
+ jtag_gpio4: jtag_gpio4 {
+ brcm,pins = <4 5 6 12 13>;
+ brcm,function = <BCM2835_FSEL_ALT4>;
+ };
+ jtag_gpio22: jtag_gpio22 {
+ brcm,pins = <22 23 24 25 26 27>;
+ brcm,function = <BCM2835_FSEL_ALT4>;
+ };
+
+ pcm_gpio18: pcm_gpio18 {
+ brcm,pins = <18 19 20 21>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ pcm_gpio28: pcm_gpio28 {
+ brcm,pins = <28 29 30 31>;
+ brcm,function = <BCM2835_FSEL_ALT2>;
+ };
+
+ pwm0_gpio12: pwm0_gpio12 {
+ brcm,pins = <12>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ pwm0_gpio18: pwm0_gpio18 {
+ brcm,pins = <18>;
+ brcm,function = <BCM2835_FSEL_ALT5>;
+ };
+ pwm0_gpio40: pwm0_gpio40 {
+ brcm,pins = <40>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ pwm1_gpio13: pwm1_gpio13 {
+ brcm,pins = <13>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ pwm1_gpio19: pwm1_gpio19 {
+ brcm,pins = <19>;
+ brcm,function = <BCM2835_FSEL_ALT5>;
+ };
+ pwm1_gpio41: pwm1_gpio41 {
+ brcm,pins = <41>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ pwm1_gpio45: pwm1_gpio45 {
+ brcm,pins = <45>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+
+ sdhost_gpio48: sdhost_gpio48 {
+ brcm,pins = <48 49 50 51 52 53>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+
+ spi0_gpio7: spi0_gpio7 {
+ brcm,pins = <7 8 9 10 11>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ spi0_gpio35: spi0_gpio35 {
+ brcm,pins = <35 36 37 38 39>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ spi1_gpio16: spi1_gpio16 {
+ brcm,pins = <16 17 18 19 20 21>;
+ brcm,function = <BCM2835_FSEL_ALT4>;
+ };
+ spi2_gpio40: spi2_gpio40 {
+ brcm,pins = <40 41 42 43 44 45>;
+ brcm,function = <BCM2835_FSEL_ALT4>;
+ };
+
+ uart0_gpio14: uart0_gpio14 {
+ brcm,pins = <14 15>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ /* Separate from the uart0_gpio14 group
+ * because it conflicts with spi1_gpio16, and
+ * people often run uart0 on the two pins
+ * without flow contrl.
+ */
+ uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
+ brcm,pins = <16 17>;
+ brcm,function = <BCM2835_FSEL_ALT3>;
+ };
+ uart0_gpio30: uart0_gpio30 {
+ brcm,pins = <30 31>;
+ brcm,function = <BCM2835_FSEL_ALT3>;
+ };
+ uart0_ctsrts_gpio32: uart0_ctsrts_gpio32 {
+ brcm,pins = <32 33>;
+ brcm,function = <BCM2835_FSEL_ALT3>;
+ };
+
+ uart1_gpio14: uart1_gpio14 {
+ brcm,pins = <14 15>;
+ brcm,function = <BCM2835_FSEL_ALT5>;
+ };
+ uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 {
+ brcm,pins = <16 17>;
+ brcm,function = <BCM2835_FSEL_ALT5>;
+ };
+ uart1_gpio32: uart1_gpio32 {
+ brcm,pins = <32 33>;
+ brcm,function = <BCM2835_FSEL_ALT5>;
+ };
+ uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
+ brcm,pins = <30 31>;
+ brcm,function = <BCM2835_FSEL_ALT5>;
+ };
+ uart1_gpio36: uart1_gpio36 {
+ brcm,pins = <36 37 38 39>;
+ brcm,function = <BCM2835_FSEL_ALT2>;
+ };
+ uart1_gpio40: uart1_gpio40 {
+ brcm,pins = <40 41>;
+ brcm,function = <BCM2835_FSEL_ALT5>;
+ };
+ uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 {
+ brcm,pins = <42 43>;
+ brcm,function = <BCM2835_FSEL_ALT5>;
+ };
};
uart0: serial@7e201000 {
--
cgit
From 14e0ea34058ce13794877206f05a6ab5034e147b Mon Sep 17 00:00:00 2001
From: Gerd Hoffmann <kraxel@redhat.com>
Date: Mon, 19 Sep 2016 10:43:19 +0200
Subject: ARM: dts: bcm283x: add pinctrl group to &pwm, drop pins from &gpio
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
---
arch/arm/boot/dts/bcm2835-rpi.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi
index e9b47b2bbc33..5663772fc460 100644
--- a/arch/arm/boot/dts/bcm2835-rpi.dtsi
+++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi
@@ -39,7 +39,7 @@
};
alt0: alt0 {
- brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 14 15 40 45>;
+ brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 14 15>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
@@ -69,6 +69,8 @@
};
&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>;
status = "okay";
};
--
cgit
From e6e199712008374edb4de979e74ae5acb1f40845 Mon Sep 17 00:00:00 2001
From: Gerd Hoffmann <kraxel@redhat.com>
Date: Mon, 19 Sep 2016 10:43:20 +0200
Subject: ARM: dts: bcm283x: add pinctrl group to &i2c0, drop pins from &gpio
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
---
arch/arm/boot/dts/bcm2835-rpi.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi
index 5663772fc460..096891fd7047 100644
--- a/arch/arm/boot/dts/bcm2835-rpi.dtsi
+++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi
@@ -39,7 +39,7 @@
};
alt0: alt0 {
- brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 14 15>;
+ brcm,pins = <2 3 4 5 7 8 9 10 11 14 15>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
@@ -50,6 +50,8 @@
};
&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_gpio0>;
status = "okay";
clock-frequency = <100000>;
};
--
cgit
From 4eb65cbfa721db9d7bbe2f76e8b1909fa0320273 Mon Sep 17 00:00:00 2001
From: Gerd Hoffmann <kraxel@redhat.com>
Date: Mon, 19 Sep 2016 10:43:21 +0200
Subject: ARM: dts: bcm283x: add pinctrl group to &i2c1, drop pins from &gpio
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
---
arch/arm/boot/dts/bcm2835-rpi.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi
index 096891fd7047..8b3ff38cc4ba 100644
--- a/arch/arm/boot/dts/bcm2835-rpi.dtsi
+++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi
@@ -39,7 +39,7 @@
};
alt0: alt0 {
- brcm,pins = <2 3 4 5 7 8 9 10 11 14 15>;
+ brcm,pins = <4 5 7 8 9 10 11 14 15>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
@@ -57,6 +57,8 @@
};
&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_gpio2>;
status = "okay";
clock-frequency = <100000>;
};
--
cgit
From f8bef3619bb219ed27dfe11cd20547e5b709650a Mon Sep 17 00:00:00 2001
From: Gerd Hoffmann <kraxel@redhat.com>
Date: Mon, 19 Sep 2016 10:43:22 +0200
Subject: ARM: dts: bcm283x: add pinctrl group to &sdhci, drop pins from &gpio
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
---
arch/arm/boot/dts/bcm2835-rpi.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi
index 8b3ff38cc4ba..7c63e667425f 100644
--- a/arch/arm/boot/dts/bcm2835-rpi.dtsi
+++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi
@@ -44,7 +44,7 @@
};
alt3: alt3 {
- brcm,pins = <48 49 50 51 52 53>;
+ brcm,pins = <>;
brcm,function = <BCM2835_FSEL_ALT3>;
};
};
@@ -68,6 +68,8 @@
};
&sdhci {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_gpio48>;
status = "okay";
bus-width = <4>;
};
--
cgit
From a6d962aeb22fbf73c023334bdf55dc45c9fd7dba Mon Sep 17 00:00:00 2001
From: Gerd Hoffmann <kraxel@redhat.com>
Date: Mon, 19 Sep 2016 10:43:23 +0200
Subject: ARM: dts: bcm283x: drop alt3 from &gpio
As the alt3 group has no pins left drop it from &gpio.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
---
arch/arm/boot/dts/bcm2835-rpi-a-plus.dts | 2 +-
arch/arm/boot/dts/bcm2835-rpi-a.dts | 2 +-
arch/arm/boot/dts/bcm2835-rpi-b-plus.dts | 2 +-
arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts | 2 +-
arch/arm/boot/dts/bcm2835-rpi-b.dts | 2 +-
arch/arm/boot/dts/bcm2835-rpi-zero.dts | 2 +-
arch/arm/boot/dts/bcm2835-rpi.dtsi | 5 -----
arch/arm/boot/dts/bcm2836-rpi-2-b.dts | 2 +-
8 files changed, 7 insertions(+), 12 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
index f7f9db355d98..21507c922783 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
@@ -22,7 +22,7 @@
};
&gpio {
- pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>;
+ pinctrl-0 = <&gpioout &alt0 &i2s_alt0>;
/* I2S interface */
i2s_alt0: i2s_alt0 {
diff --git a/arch/arm/boot/dts/bcm2835-rpi-a.dts b/arch/arm/boot/dts/bcm2835-rpi-a.dts
index 8be102f5d826..5afba0900449 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-a.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-a.dts
@@ -15,7 +15,7 @@
};
&gpio {
- pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>;
+ pinctrl-0 = <&gpioout &alt0 &i2s_alt2>;
/* I2S interface */
i2s_alt2: i2s_alt2 {
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
index 35cde65c975e..38f66aa244fe 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
@@ -23,7 +23,7 @@
};
&gpio {
- pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>;
+ pinctrl-0 = <&gpioout &alt0 &i2s_alt0>;
/* I2S interface */
i2s_alt0: i2s_alt0 {
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts
index 84df85ea6296..75e045aba7ce 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts
@@ -16,7 +16,7 @@
};
&gpio {
- pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>;
+ pinctrl-0 = <&gpioout &alt0 &i2s_alt2>;
/* I2S interface */
i2s_alt2: i2s_alt2 {
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts
index 8e626a80fe24..76a254b3219a 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts
@@ -16,7 +16,7 @@
};
&gpio {
- pinctrl-0 = <&gpioout &alt0 &alt3>;
+ pinctrl-0 = <&gpioout &alt0>;
};
&hdmi {
diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero.dts b/arch/arm/boot/dts/bcm2835-rpi-zero.dts
index 60e359fafc5b..7c1c18048948 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-zero.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-zero.dts
@@ -26,7 +26,7 @@
};
&gpio {
- pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>;
+ pinctrl-0 = <&gpioout &alt0 &i2s_alt0>;
/* I2S interface */
i2s_alt0: i2s_alt0 {
diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi
index 7c63e667425f..6ddf7dfe3f72 100644
--- a/arch/arm/boot/dts/bcm2835-rpi.dtsi
+++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi
@@ -42,11 +42,6 @@
brcm,pins = <4 5 7 8 9 10 11 14 15>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
-
- alt3: alt3 {
- brcm,pins = <>;
- brcm,function = <BCM2835_FSEL_ALT3>;
- };
};
&i2c0 {
diff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
index 39dccf62ac96..bf19e8cfb9e6 100644
--- a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
+++ b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
@@ -27,7 +27,7 @@
};
&gpio {
- pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>;
+ pinctrl-0 = <&gpioout &alt0 &i2s_alt0>;
/* I2S interface */
i2s_alt0: i2s_alt0 {
--
cgit
From accc477c9c30b10a7ae8d88523a1700292b2923e Mon Sep 17 00:00:00 2001
From: Randy Li <ayaka@soulik.info>
Date: Wed, 19 Oct 2016 01:18:48 +0800
Subject: ARM: dts: exynos: Add TOPEET itop core board SCP package version
The TOPEET itop is a Samsung Exynos4412 core board, which has
two package versions. This patch adds the support for SCP version.
Currently supported are USB3503A HSIC, USB OTG, eMMC, RTC and
PMIC. The future features are in the based board. Also MFC and
watchdog have been enabled.
Signed-off-by: Randy Li <ayaka@soulik.info>
[krzk: fixup pin function macro, adjust commit msg]
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi | 501 ++++++++++++++++++++++++
1 file changed, 501 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
new file mode 100644
index 000000000000..a36cd36a26b8
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
@@ -0,0 +1,501 @@
+/*
+ * TOPEET's Exynos4412 based itop board device tree source
+ *
+ * Copyright (c) 2016 SUMOMO Computer Association
+ * https://www.sumomo.mobi
+ * Randy Li <ayaka@soulik.info>
+ *
+ * Device tree source file for TOPEET iTop Exynos 4412 SCP package core
+ * board which is based on Samsung's Exynos4412 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <dt-bindings/clock/samsung,s2mps11.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "exynos4412.dtsi"
+#include "exynos4412-ppmu-common.dtsi"
+#include "exynos-mfc-reserved-memory.dtsi"
+
+/ {
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x40000000 0x40000000>;
+ };
+
+ firmware@0203F000 {
+ compatible = "samsung,secure-firmware";
+ reg = <0x0203F000 0x1000>;
+ };
+
+ fixed-rate-clocks {
+ xxti {
+ compatible = "samsung,clock-xxti";
+ clock-frequency = <0>;
+ };
+
+ xusbxti {
+ compatible = "samsung,clock-xusbxti";
+ clock-frequency = <24000000>;
+ };
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ cooling-maps {
+ map0 {
+ /* Corresponds to 800MHz at freq_table */
+ cooling-device = <&cpu0 7 7>;
+ };
+ map1 {
+ /* Corresponds to 200MHz at freq_table */
+ cooling-device = <&cpu0 13 13>;
+ };
+ };
+ };
+ };
+
+ usb-hub {
+ compatible = "smsc,usb3503a";
+ reset-gpios = <&gpm2 4 GPIO_ACTIVE_LOW>;
+ connect-gpios = <&gpm3 3 GPIO_ACTIVE_HIGH>;
+ intn-gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hsic_reset>;
+ };
+};
+
+&bus_dmc {
+ devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
+ vdd-supply = <&buck1_reg>;
+ status = "okay";
+};
+
+&bus_acp {
+ devfreq = <&bus_dmc>;
+ status = "okay";
+};
+
+&bus_c2c {
+ devfreq = <&bus_dmc>;
+ status = "okay";
+};
+
+&bus_leftbus {
+ devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
+ vdd-supply = <&buck3_reg>;
+ status = "okay";
+};
+
+&bus_rightbus {
+ devfreq = <&bus_leftbus>;
+ status = "okay";
+};
+
+&bus_fsys {
+ devfreq = <&bus_leftbus>;
+ status = "okay";
+};
+
+&bus_peri {
+ devfreq = <&bus_leftbus>;
+ status = "okay";
+};
+
+&bus_mfc {
+ devfreq = <&bus_leftbus>;
+ status = "okay";
+};
+
+&cpu0 {
+ cpu0-supply = <&buck2_reg>;
+};
+
+&hsotg {
+ vusb_d-supply = <&ldo15_reg>;
+ vusb_a-supply = <&ldo12_reg>;
+};
+
+&i2c_1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-max-bus-freq = <400000>;
+ pinctrl-0 = <&i2c1_bus>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ s5m8767: s5m8767-pmic@66 {
+ compatible = "samsung,s5m8767-pmic";
+ reg = <0x66>;
+
+ s5m8767,pmic-buck-default-dvs-idx = <3>;
+
+ s5m8767,pmic-buck-dvs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>,
+ <&gpb 6 GPIO_ACTIVE_HIGH>,
+ <&gpb 7 GPIO_ACTIVE_HIGH>;
+
+ s5m8767,pmic-buck-ds-gpios = <&gpm3 5 GPIO_ACTIVE_HIGH>,
+ <&gpm3 6 GPIO_ACTIVE_HIGH>,
+ <&gpm3 7 GPIO_ACTIVE_HIGH>;
+
+ /* VDD_ARM */
+ s5m8767,pmic-buck2-dvs-voltage = <1356250>, <1300000>,
+ <1243750>, <1118750>,
+ <1068750>, <1012500>,
+ <956250>, <900000>;
+ /* VDD_INT */
+ s5m8767,pmic-buck3-dvs-voltage = <1000000>, <1000000>,
+ <925000>, <925000>,
+ <887500>, <887500>,
+ <850000>, <850000>;
+ /* VDD_G3D */
+ s5m8767,pmic-buck4-dvs-voltage = <1081250>, <1081250>,
+ <1025000>, <950000>,
+ <918750>, <900000>,
+ <875000>, <831250>;
+
+ regulators {
+ ldo1_reg: LDO1 {
+ regulator-name = "VDD_ALIVE";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ regulator-boot-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ /* SCP uses 1.5v, POP uses 1.2v */
+ ldo2_reg: LDO2 {
+ regulator-name = "VDDQ_M12";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo3_reg: LDO3 {
+ regulator-name = "VDDIOAP_18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo4_reg: LDO4 {
+ regulator-name = "VDDQ_PRE";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo5_reg: LDO5 {
+ regulator-name = "VDD_LDO5";
+ op_mode = <0>; /* Always off Mode */
+ };
+
+ ldo6_reg: LDO6 {
+ regulator-name = "VDD10_MPLL";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo7_reg: LDO7 {
+ regulator-name = "VDD10_XPLL";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo8_reg: LDO8 {
+ regulator-name = "VDD10_MIPI";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo9_reg: LDO9 {
+ regulator-name = "VDD33_LCD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo10_reg: LDO10 {
+ regulator-name = "VDD18_MIPI";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo11_reg: LDO11 {
+ regulator-name = "VDD18_ABB1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo12_reg: LDO12 {
+ regulator-name = "VDD33_UOTG";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo13_reg: LDO13 {
+ regulator-name = "VDDIOPERI_18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo14_reg: LDO14 {
+ regulator-name = "VDD18_ABB02";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo15_reg: LDO15 {
+ regulator-name = "VDD10_USH";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo16_reg: LDO16 {
+ regulator-name = "VDD18_HSIC";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo17_reg: LDO17 {
+ regulator-name = "VDDIOAP_MMC012_28";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ /* Used by HSIC */
+ ldo18_reg: LDO18 {
+ regulator-name = "VDDIOPERI_28";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo19_reg: LDO19 {
+ regulator-name = "VDD_LDO19";
+ op_mode = <0>; /* Always off Mode */
+ };
+
+ ldo20_reg: LDO20 {
+ regulator-name = "VDD28_CAM";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2800000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo21_reg: LDO21 {
+ regulator-name = "VDD28_AF";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2800000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo22_reg: LDO22 {
+ regulator-name = "VDDA28_2M";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo23_reg: LDO23 {
+ regulator-name = "VDD28_TF";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo24_reg: LDO24 {
+ regulator-name = "VDD33_A31";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo25_reg: LDO25 {
+ regulator-name = "VDD18_CAM";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo26_reg: LDO26 {
+ regulator-name = "VDD18_A31";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo27_reg: LDO27 {
+ regulator-name = "GPS_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo28_reg: LDO28 {
+ regulator-name = "DVDD12";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ buck1_reg: BUCK1 {
+ regulator-name = "vdd_mif";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ regulator-boot-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ buck2_reg: BUCK2 {
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1456250>;
+ regulator-always-on;
+ regulator-boot-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ buck3_reg: BUCK3 {
+ regulator-name = "vdd_int";
+ regulator-min-microvolt = <875000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ buck4_reg: BUCK4 {
+ regulator-name = "vdd_g3d";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ buck5_reg: BUCK5 {
+ regulator-name = "vdd_m12";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ buck6_reg: BUCK6 {
+ regulator-name = "vdd12_5m";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ buck7_reg: BUCK7 {
+ regulator-name = "pvdd_buck7";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ buck8_reg: BUCK8 {
+ regulator-name = "pvdd_buck8";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-boot-on;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ buck9_reg: BUCK9 {
+ regulator-name = "vddf28_emmc";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <3000000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+ };
+
+ s5m8767_osc: clocks {
+ #clock-cells = <1>;
+ clock-output-names = "s5m8767_ap",
+ "s5m8767_cp", "s5m8767_bt";
+ };
+
+ };
+};
+
+&mfc {
+ status = "okay";
+};
+
+&mshc_0 {
+ pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
+ pinctrl-names = "default";
+ status = "okay";
+ vmmc-supply = <&buck9_reg>;
+ num-slots = <1>;
+ broken-cd;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+ bus-width = <8>;
+ cap-mmc-highspeed;
+};
+
+&pinctrl_1 {
+ hsic_reset: hsic-reset {
+ samsung,pins = "gpm2-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+};
+
+&rtc {
+ status = "okay";
+ clocks = <&clock CLK_RTC>, <&s5m8767_osc S2MPS11_CLK_AP>;
+ clock-names = "rtc", "rtc_src";
+};
+
+&tmu {
+ vtmu-supply = <&ldo16_reg>;
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
--
cgit
From 339b2fb36a67ee5a7c4e534e4237f4326f251dc4 Mon Sep 17 00:00:00 2001
From: Randy Li <ayaka@soulik.info>
Date: Wed, 19 Oct 2016 01:18:49 +0800
Subject: ARM: dts: exynos: Add TOPEET itop elite based board
The TOPEET itop Exynos4412 has three versions of base boards. The
Elite version is the cheap one without too much peripheral devices
on it.
Currently supported are serial console, wired networking (USB), USB OTG
in peripheral mode, USB host, SD storage, GPIO buttons, PWM beeper, ADC
and LEDs. The WM8960 analog audio codec is also enabled.
The FIMC is not used for camera currently, I enabled it just for a
colorspace converter.
Signed-off-by: Randy Li <ayaka@soulik.info>
Acked-by: Rob Herring <robh@kernel.org>
[krzk: fixup pin function macro, adjust commit msg]
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/exynos4412-itop-elite.dts | 240 ++++++++++++++++++++++++++++
2 files changed, 241 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos4412-itop-elite.dts
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index befcd2619902..d709f74c2f54 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -136,6 +136,7 @@ dtb-$(CONFIG_ARCH_EXYNOS4) += \
exynos4210-smdkv310.dtb \
exynos4210-trats.dtb \
exynos4210-universal_c210.dtb \
+ exynos4412-itop-elite.dtb \
exynos4412-odroidu3.dtb \
exynos4412-odroidx.dtb \
exynos4412-odroidx2.dtb \
diff --git a/arch/arm/boot/dts/exynos4412-itop-elite.dts b/arch/arm/boot/dts/exynos4412-itop-elite.dts
new file mode 100644
index 000000000000..76d87f397178
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-itop-elite.dts
@@ -0,0 +1,240 @@
+/*
+ * TOPEET's Exynos4412 based itop board device tree source
+ *
+ * Copyright (c) 2016 SUMOMO Computer Association
+ * https://www.sumomo.mobi
+ * Randy Li <ayaka@soulik.info>
+ *
+ * Device tree source file for TOPEET iTop Exynos 4412 core board
+ * which is based on Samsung's Exynos4412 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/sound/samsung-i2s.h>
+#include "exynos4412-itop-scp-core.dtsi"
+
+/ {
+ model = "TOPEET iTop 4412 Elite board based on Exynos4412";
+ compatible = "topeet,itop4412-elite", "samsung,exynos4412", "samsung,exynos4";
+
+ chosen {
+ bootargs = "root=/dev/mmcblk0p2 rw rootfstype=ext4 rootdelay=1 rootwait";
+ stdout-path = "serial2:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led2 {
+ label = "red:system";
+ gpios = <&gpx1 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "heartbeat";
+ };
+
+ led3 {
+ label = "red:user";
+ gpios = <&gpk1 1 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ home {
+ label = "GPIO Key Home";
+ linux,code = <KEY_HOME>;
+ gpios = <&gpx1 1 GPIO_ACTIVE_LOW>;
+ };
+
+ back {
+ label = "GPIO Key Back";
+ linux,code = <KEY_BACK>;
+ gpios = <&gpx1 2 GPIO_ACTIVE_LOW>;
+ };
+
+ sleep {
+ label = "GPIO Key Sleep";
+ linux,code = <KEY_POWER>;
+ gpios = <&gpx3 3 GPIO_ACTIVE_LOW>;
+ };
+
+ vol-up {
+ label = "GPIO Key Vol+";
+ linux,code = <KEY_UP>;
+ gpios = <&gpx2 1 GPIO_ACTIVE_LOW>;
+ };
+
+ vol-down {
+ label = "GPIO Key Vol-";
+ linux,code = <KEY_DOWN>;
+ gpios = <&gpx2 0 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "wm-sound";
+
+ assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
+ <&clock_audss EXYNOS_MOUT_I2S>,
+ <&clock_audss EXYNOS_DOUT_SRP>,
+ <&clock_audss EXYNOS_DOUT_AUD_BUS>;
+ assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
+ <&clock_audss EXYNOS_MOUT_AUDSS>;
+ assigned-clock-rates = <0>,
+ <0>,
+ <112896000>,
+ <11289600>;
+
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&link0_codec>;
+ simple-audio-card,frame-master = <&link0_codec>;
+
+ simple-audio-card,widgets =
+ "Microphone", "Mic Jack",
+ "Line", "Line In",
+ "Line", "Line Out",
+ "Speaker", "Speaker",
+ "Headphone", "Headphone Jack";
+ simple-audio-card,routing =
+ "Headphone Jack", "HP_L",
+ "Headphone Jack", "HP_R",
+ "Speaker", "SPK_LP",
+ "Speaker", "SPK_LN",
+ "Speaker", "SPK_RP",
+ "Speaker", "SPK_RN",
+ "LINPUT1", "Mic Jack",
+ "LINPUT3", "Mic Jack",
+ "RINPUT1", "Mic Jack",
+ "RINPUT2", "Mic Jack";
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s0 0>;
+ };
+
+ link0_codec: simple-audio-card,codec {
+ sound-dai = <&codec>;
+ clocks = <&i2s0 CLK_I2S_CDCLK>;
+ system-clock-frequency = <11289600>;
+ };
+ };
+
+ beep {
+ compatible = "pwm-beeper";
+ pwms = <&pwm 0 4000000 PWM_POLARITY_INVERTED>;
+ };
+
+ camera: camera {
+ pinctrl-0 = <&cam_port_a_clk_active>;
+ pinctrl-names = "default";
+ status = "okay";
+ assigned-clocks = <&clock CLK_MOUT_CAM0>;
+ assigned-clock-parents = <&clock CLK_XUSBXTI>;
+ };
+};
+
+&adc {
+ vdd-supply = <&ldo3_reg>;
+ status = "okay";
+};
+
+&ehci {
+ status = "okay";
+ /* In order to reset USB ethernet */
+ samsung,vbus-gpio = <&gpc0 1 GPIO_ACTIVE_HIGH>;
+
+ port@0 {
+ status = "okay";
+ };
+
+ port@2 {
+ status = "okay";
+ };
+};
+
+&exynos_usbphy {
+ status = "okay";
+};
+
+&fimc_0 {
+ status = "okay";
+ assigned-clocks = <&clock CLK_MOUT_FIMC0>,
+ <&clock CLK_SCLK_FIMC0>;
+ assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
+ assigned-clock-rates = <0>, <176000000>;
+};
+
+&hsotg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&i2c_4 {
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-slave-addr = <0x10>;
+ samsung,i2c-max-bus-freq = <100000>;
+ pinctrl-0 = <&i2c4_bus>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ codec: wm8960@1a {
+ compatible = "wlf,wm8960";
+ reg = <0x1a>;
+ clocks = <&pmu_system_controller 0>;
+ clock-names = "MCLK1";
+ wlf,shared-lrclk;
+ #sound-dai-cells = <0>;
+ };
+};
+
+&i2s0 {
+ pinctrl-0 = <&i2s0_bus>;
+ pinctrl-names = "default";
+ status = "okay";
+ clocks = <&clock_audss EXYNOS_I2S_BUS>,
+ <&clock_audss EXYNOS_DOUT_AUD_BUS>,
+ <&clock_audss EXYNOS_SCLK_I2S>;
+ clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
+};
+
+&pinctrl_1 {
+ ether-reset {
+ samsung,pins = "gpc0-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+};
+
+&pwm {
+ status = "okay";
+ pinctrl-0 = <&pwm0_out>;
+ pinctrl-names = "default";
+ samsung,pwm-outputs = <0>;
+};
+
+&sdhci_2 {
+ bus-width = <4>;
+ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>;
+ pinctrl-names = "default";
+ cd-gpio = <&gpx0 7 GPIO_ACTIVE_LOW>;
+ cap-sd-highspeed;
+ vmmc-supply = <&ldo23_reg>;
+ vqmmc-supply = <&ldo17_reg>;
+ status = "okay";
+};
+
+&serial_1 {
+ status = "okay";
+};
+
+&serial_2 {
+ status = "okay";
+};
--
cgit
From 587aed72c6b98612190bbae77330f341cf98f4f7 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Mon, 19 Sep 2016 21:40:43 +0000
Subject: ARM: dts: socfpga: Add new MCVEVK manufacturer compat
The board is now manufactured by Aries Embedded GmbH, update compat string.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi | 2 +-
arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi b/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi
index f86f9c060d7a..6ad3b1eb9b86 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi
+++ b/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi
@@ -18,7 +18,7 @@
#include "socfpga_cyclone5.dtsi"
/ {
- model = "DENX MCV";
+ model = "Aries/DENX MCV";
compatible = "altr,socfpga-cyclone5", "altr,socfpga";
memory {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts b/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts
index 7186a29b8b86..424523b0d381 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts
@@ -18,7 +18,7 @@
#include "socfpga_cyclone5_mcv.dtsi"
/ {
- model = "DENX MCV EVK";
+ model = "Aries/DENX MCV EVK";
compatible = "altr,socfpga-cyclone5", "altr,socfpga";
aliases {
--
cgit
From 73c7d4203c2fd9aa888df0196f7e8c058186baaa Mon Sep 17 00:00:00 2001
From: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Date: Sat, 24 Sep 2016 23:59:45 +0000
Subject: ARM: dts: socfpga: Add Macnica sodia board
Add support for board based on the Altera Cyclone V SoC.
This board has the following functions:
- 1 GiB of DRAM
- 1 Gigabit ethernet
- 1 SD card slot
- 1 USB gadget port
- QSPI NOR Flash
- I2C EEPROMs and I2C RTC
- DVI output
- Audio port
This commit supports without QSPI, DVI and Audio.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/socfpga_cyclone5_sodia.dts | 123 +++++++++++++++++++++++++++
2 files changed, 124 insertions(+)
create mode 100644 arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index befcd2619902..7c5f0c31b6f6 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -696,6 +696,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_cyclone5_de0_sockit.dtb \
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb \
+ socfpga_cyclone5_sodia.dtb \
socfpga_cyclone5_vining_fpga.dtb \
socfpga_vt.dtb
dtb-$(CONFIG_ARCH_SPEAR13XX) += \
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
new file mode 100644
index 000000000000..9aaf413b80de
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
@@ -0,0 +1,123 @@
+/*
+ * Copyright (C) 2016 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "socfpga_cyclone5.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Altera SOCFPGA Cyclone V SoC Macnica Sodia board";
+ compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+
+ chosen {
+ bootargs = "earlyprintk";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x40000000>;
+ };
+
+ aliases {
+ ethernet0 = &gmac1;
+ };
+
+ regulator_3_3v: 3-3-v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ leds: gpio-leds {
+ compatible = "gpio-leds";
+
+ hps_led0 {
+ label = "hps:green:led0";
+ gpios = <&portb 12 GPIO_ACTIVE_LOW>;
+ };
+
+ hps_led1 {
+ label = "hps:green:led1";
+ gpios = <&portb 13 GPIO_ACTIVE_LOW>;
+ };
+
+ hps_led2 {
+ label = "hps:green:led2";
+ gpios = <&portb 14 GPIO_ACTIVE_LOW>;
+ };
+
+ hps_led3 {
+ label = "hps:green:led3";
+ gpios = <&portb 15 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&gmac1 {
+ status = "okay";
+ phy-mode = "rgmii";
+ phy = <&phy0>;
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ rxd0-skew-ps = <0>;
+ rxd1-skew-ps = <0>;
+ rxd2-skew-ps = <0>;
+ rxd3-skew-ps = <0>;
+ rxdv-skew-ps = <0>;
+ rxc-skew-ps = <3000>;
+ txen-skew-ps = <0>;
+ txc-skew-ps = <3000>;
+ };
+ };
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ eeprom@51 {
+ compatible = "atmel,24c32";
+ reg = <0x51>;
+ pagesize = <32>;
+ };
+
+ rtc@68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ };
+};
+
+&mmc0 {
+ cd-gpios = <&portb 18 0>;
+ vmmc-supply = <®ulator_3_3v>;
+ vqmmc-supply = <®ulator_3_3v>;
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
--
cgit
From ecba2390e350cdce2c47800cde34d0fe91b53870 Mon Sep 17 00:00:00 2001
From: Dinh Nguyen <dinguyen@opensource.altera.com>
Date: Mon, 26 Sep 2016 14:29:30 -0500
Subject: ARM: dts: socfpga: enable arm,shared-override in the pl310
Enable the bit(22) shared-override bit for the SoCFPGA family. While at it,
enable the prefetch-data and prefetch-instr settings for the Arria10.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
arch/arm/boot/dts/socfpga.dtsi | 1 +
arch/arm/boot/dts/socfpga_arria10.dtsi | 3 +++
2 files changed, 4 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 9f48141270b8..28ff6e4cd54e 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -686,6 +686,7 @@
arm,data-latency = <2 1 1>;
prefetch-data = <1>;
prefetch-instr = <1>;
+ arm,shared-override;
};
mmc: dwmmc0@ff704000 {
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index f520cbff5e1c..ac0e19ca14b0 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -573,6 +573,9 @@
interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
cache-unified;
cache-level = <2>;
+ prefetch-data = <1>;
+ prefetch-instr = <1>;
+ arm,shared-override;
};
mmc: dwmmc0@ff808000 {
--
cgit
From f2d6f8f8178142519c5b576582bec5cf9eabbaaf Mon Sep 17 00:00:00 2001
From: Thor Thayer <tthayer@opensource.altera.com>
Date: Thu, 2 Jun 2016 17:52:25 +0000
Subject: ARM: dts: socfpga: Add SPI Master1 for Arria10 SR chip
Add the Altera Arria10 SPI Master Node in preparation for
the A10SR MFD node.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index ac0e19ca14b0..1149216c78c5 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -562,6 +562,21 @@
status = "disabled";
};
+ spi1: spi@ffda5000 {
+ compatible = "snps,dw-apb-ssi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xffda5000 0x100>;
+ interrupts = <0 102 4>;
+ num-chipselect = <4>;
+ bus-num = <0>;
+ /*32bit_access;*/
+ tx-dma-channel = <&pdma 16>;
+ rx-dma-channel = <&pdma 17>;
+ clocks = <&spi_m_clk>;
+ status = "disabled";
+ };
+
sdr: sdr@ffc25000 {
compatible = "syscon";
reg = <0xffcfb100 0x80>;
--
cgit
From 5984be047d35379012184310cafcac9efac366b8 Mon Sep 17 00:00:00 2001
From: Thor Thayer <tthayer@opensource.altera.com>
Date: Thu, 2 Jun 2016 17:52:26 +0000
Subject: ARM: dts: socfpga: Add Devkit A10-SR fields for Arria10
Add the Altera Arria10 System Resource node. This is a Multi-Function
device with GPIO expander support.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
arch/arm/boot/dts/socfpga_arria10_socdk.dtsi | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
index 8e3a4adc389f..9f97756693f4 100644
--- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
@@ -75,6 +75,27 @@
status = "okay";
};
+&spi1 {
+ status = "okay";
+
+ resource-manager@0 {
+ compatible = "altr,a10sr";
+ reg = <0>;
+ spi-max-frequency = <100000>;
+ /* low-level active IRQ at GPIO1_5 */
+ interrupt-parent = <&portb>;
+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ a10sr_gpio: gpio-controller {
+ compatible = "altr,a10sr-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+};
+
&i2c1 {
speed-mode = <0>;
status = "okay";
--
cgit
From 07e75f4393b42b6c82c5d31714ceeba429fa34c3 Mon Sep 17 00:00:00 2001
From: Thor Thayer <tthayer@opensource.altera.com>
Date: Thu, 2 Jun 2016 17:52:27 +0000
Subject: ARM: dts: socfpga: Enable GPIO parent for Arria10 SR chip
Enable the Altera Arria10 GPIO parent for MFD operation.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
arch/arm/boot/dts/socfpga_arria10_socdk.dtsi | 4 ++++
1 file changed, 4 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
index 9f97756693f4..693fa508cb97 100644
--- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
@@ -75,6 +75,10 @@
status = "okay";
};
+&gpio1 {
+ status = "okay";
+};
+
&spi1 {
status = "okay";
--
cgit
From acf3b20c23861d38a911f3e0b916fc39ff4211f6 Mon Sep 17 00:00:00 2001
From: Thor Thayer <tthayer@opensource.altera.com>
Date: Thu, 2 Jun 2016 17:52:28 +0000
Subject: ARM: dts: socfpga: Add LED framework to A10-SR GPIO
Add the LED framework to the Arria10 System Resource chip GPIO hooks.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
arch/arm/boot/dts/socfpga_arria10_socdk.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
index 693fa508cb97..eb00ae37f316 100644
--- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
@@ -36,6 +36,30 @@
reg = <0x0 0x40000000>; /* 1GB */
};
+ a10leds {
+ compatible = "gpio-leds";
+
+ a10sr_led0 {
+ label = "a10sr-led0";
+ gpios = <&a10sr_gpio 0 1>;
+ };
+
+ a10sr_led1 {
+ label = "a10sr-led1";
+ gpios = <&a10sr_gpio 1 1>;
+ };
+
+ a10sr_led2 {
+ label = "a10sr-led2";
+ gpios = <&a10sr_gpio 2 1>;
+ };
+
+ a10sr_led3 {
+ label = "a10sr-led3";
+ gpios = <&a10sr_gpio 3 1>;
+ };
+ };
+
soc {
clkmgr@ffd04000 {
clocks {
--
cgit
From c6deff00b90496d5453d471277a8b469dc3e150d Mon Sep 17 00:00:00 2001
From: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Date: Tue, 18 Oct 2016 07:43:02 +0000
Subject: ARM: dts: socfpga: add qspi node
Add the qspi node to the socfpga dtsi file.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
arch/arm/boot/dts/socfpga.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 28ff6e4cd54e..dda6b4500b9a 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -706,6 +706,20 @@
reg = <0xffff0000 0x10000>;
};
+ qspi: spi@ff705000 {
+ compatible = "cdns,qspi-nor";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xff705000 0x1000>,
+ <0xffa00000 0x1000>;
+ interrupts = <0 151 4>;
+ cdns,fifo-depth = <128>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x00000000>;
+ clocks = <&qspi_clk>;
+ status = "disabled";
+ };
+
rst: rstmgr@ffd05000 {
#reset-cells = <1>;
compatible = "altr,rst-mgr";
--
cgit
From c96f5919e6b0d132aa9afe9f1adc872fc107d5bb Mon Sep 17 00:00:00 2001
From: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Date: Tue, 18 Oct 2016 07:43:03 +0000
Subject: ARM: dts: socfpga: socrates: enable qspi
Enable the qspi controller on the socrates and add the flash chip.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
arch/arm/boot/dts/socfpga_cyclone5_socrates.dts | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
index d79853775061..c3d52f27b21e 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
@@ -80,3 +80,22 @@
&mmc {
status = "okay";
};
+
+&qspi {
+ status = "okay";
+
+ flash: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q256a";
+ reg = <0>;
+ spi-max-frequency = <100000000>;
+ m25p,fast-read;
+ cdns,read-delay = <4>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+ status = "okay";
+ };
+};
--
cgit
From 05b3c64d56370c836499c22ea83df68fe0083841 Mon Sep 17 00:00:00 2001
From: Rafał Miłecki <rafal@milecki.pl>
Date: Tue, 23 Aug 2016 08:40:32 +0200
Subject: ARM: BCM5301X: Add DT for Netgear R8500
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Netgear R8500 is another BCM47094 device, it just has three BCM4366
wireless chipsets. It's a very standard DT with mostly GPIO devices.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/bcm47094-netgear-r8500.dts | 104 +++++++++++++++++++++++++++
2 files changed, 105 insertions(+)
create mode 100644 arch/arm/boot/dts/bcm47094-netgear-r8500.dts
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index befcd2619902..93ec71e8bedf 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -87,6 +87,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
bcm4709-netgear-r7000.dtb \
bcm4709-netgear-r8000.dtb \
bcm47094-dlink-dir-885l.dtb \
+ bcm47094-netgear-r8500.dtb \
bcm94708.dtb \
bcm94709.dtb \
bcm953012er.dtb \
diff --git a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts
new file mode 100644
index 000000000000..10db4f8f2a44
--- /dev/null
+++ b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts
@@ -0,0 +1,104 @@
+/*
+ * Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
+ *
+ * Licensed under the ISC license.
+ */
+
+/dts-v1/;
+
+#include "bcm4708.dtsi"
+#include "bcm5301x-nand-cs0-bch8.dtsi"
+
+/ {
+ compatible = "netgear,r8500", "brcm,bcm47094", "brcm,bcm4708";
+ model = "Netgear R8500";
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ };
+
+ memory {
+ reg = <0x00000000 0x08000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ power0 {
+ label = "bcm53xx:white:power";
+ gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-on";
+ };
+
+ power1 {
+ label = "bcm53xx:amber:power";
+ gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-off";
+ };
+
+ 5ghz-1 {
+ label = "bcm53xx:white:5ghz-1";
+ gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-off";
+ };
+
+ 5ghz-2 {
+ label = "bcm53xx:white:5ghz-2";
+ gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-off";
+ };
+
+ 2ghz {
+ label = "bcm53xx:white:2ghz";
+ gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-off";
+ };
+
+ usb2 {
+ label = "bcm53xx:white:usb2";
+ gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-off";
+ };
+
+ usb3 {
+ label = "bcm53xx:white:usb3";
+ gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-off";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ brightness {
+ label = "Backlight";
+ linux,code = <KEY_BRIGHTNESS_ZERO>;
+ gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>;
+ };
+
+ restart {
+ label = "Reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
+ };
+
+ wps {
+ label = "WPS";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
+ };
+
+ rfkill {
+ label = "WiFi";
+ linux,code = <KEY_RFKILL>;
+ gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+ clock-frequency = <125000000>;
+};
--
cgit
From e90d2d51c41202ae6a99b4d5e1342482c1c8735b Mon Sep 17 00:00:00 2001
From: Rafał Miłecki <zajec5@gmail.com>
Date: Tue, 23 Aug 2016 07:37:43 +0200
Subject: ARM: BCM5301X: Add basic dts for BCM53573 based Tenda AC9
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
BCM53573 seems to be low priced alternative for Northstar chipsts. It
uses single core Cortex-A7 and doesn't have SDU or local (TWD) timer. It
was also stripped out of independent SPI controller and 2 GMACs.
DTS for Tenda AC9 isn't completed yet. It misses e.g. switch entry (we
still need some b53 fixes) and probably some clocks. It adds support for
basic features however and can be improved later.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/bcm47189-tenda-ac9.dts | 74 ++++++++++++++++
arch/arm/boot/dts/bcm53573.dtsi | 147 +++++++++++++++++++++++++++++++
3 files changed, 223 insertions(+)
create mode 100644 arch/arm/boot/dts/bcm47189-tenda-ac9.dts
create mode 100644 arch/arm/boot/dts/bcm53573.dtsi
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 93ec71e8bedf..103c2cf56f68 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -92,6 +92,8 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
bcm94709.dtb \
bcm953012er.dtb \
bcm953012k.dtb
+dtb-$(CONFIG_ARCH_BCM_53573) += \
+ bcm47189-tenda-ac9.dtb
dtb-$(CONFIG_ARCH_BCM_63XX) += \
bcm963138dvt.dtb
dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
diff --git a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts
new file mode 100644
index 000000000000..4403ae8790c2
--- /dev/null
+++ b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
+ *
+ * Licensed under the ISC license.
+ */
+
+/dts-v1/;
+
+#include "bcm53573.dtsi"
+
+/ {
+ compatible = "tenda,ac9", "brcm,bcm47189", "brcm,bcm53573";
+ model = "Tenda AC9";
+
+ chosen {
+ bootargs = "console=ttyS0,115200 earlycon";
+ };
+
+ memory {
+ reg = <0x00000000 0x08000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ usb {
+ label = "bcm53xx:blue:usb";
+ gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-off";
+ };
+
+ wps {
+ label = "bcm53xx:blue:wps";
+ gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-off";
+ };
+
+ 5ghz {
+ label = "bcm53xx:blue:5ghz";
+ gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-off";
+ };
+
+ system {
+ label = "bcm53xx:blue:system";
+ gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "timer";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rfkill {
+ label = "WiFi";
+ linux,code = <KEY_RFKILL>;
+ gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
+ };
+
+ restart {
+ label = "Reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
+ };
+
+ wps {
+ label = "WPS";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/bcm53573.dtsi b/arch/arm/boot/dts/bcm53573.dtsi
new file mode 100644
index 000000000000..efa07de50969
--- /dev/null
+++ b/arch/arm/boot/dts/bcm53573.dtsi
@@ -0,0 +1,147 @@
+/*
+ * Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
+ *
+ * Licensed under the ISC license.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "skeleton.dtsi"
+
+/ {
+ interrupt-parent = <&gic>;
+
+ chosen {
+ stdout-path = &uart0;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ };
+ };
+
+ mpcore {
+ compatible = "simple-bus";
+ ranges = <0x00000000 0x18310000 0x00008000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ gic: interrupt-controller@1000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x1000 0x1000>,
+ <0x2000 0x0100>;
+ };
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ alp: oscillator {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <40000000>;
+ };
+ };
+
+ axi@18000000 {
+ compatible = "brcm,bus-axi";
+ reg = <0x18000000 0x1000>;
+ ranges = <0x00000000 0x18000000 0x00100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x000fffff 0xffff>;
+ interrupt-map =
+ /* ChipCommon */
+ <0x00000000 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+
+ /* IEEE 802.11 0 */
+ <0x00001000 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+
+ /* PCIe Controller 0 */
+ <0x00002000 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00002000 1 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00002000 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00002000 3 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00002000 4 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00002000 5 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+
+ /* USB 2.0 Controller */
+ <0x00004000 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+
+ /* Ethernet Controller 0 */
+ <0x00005000 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+
+ /* IEEE 802.11 1 */
+ <0x0000a000 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+
+ /* Ethernet Controller 1 */
+ <0x0000b000 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+
+ chipcommon: chipcommon@0 {
+ compatible = "simple-bus";
+ reg = <0x00000000 0x1000>;
+ ranges;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ uart0: serial@0300 {
+ compatible = "ns16550a";
+ reg = <0x0300 0x100>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&alp>;
+ status = "okay";
+ };
+ };
+
+ usb2: usb2@4000 {
+ reg = <0x4000 0x1000>;
+ ranges;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ehci: ehci@4000 {
+ compatible = "generic-ehci";
+ reg = <0x4000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ ohci: ohci@d000 {
+ #usb-cells = <0>;
+
+ compatible = "generic-ohci";
+ reg = <0xd000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ gmac0: ethernet@5000 {
+ reg = <0x5000 0x1000>;
+ };
+
+ gmac1: ethernet@b000 {
+ reg = <0xb000 0x1000>;
+ };
+ };
+};
--
cgit
From 329f98c1974e2323d9cc30964620e305113adac7 Mon Sep 17 00:00:00 2001
From: Kamal Dasu <kdasu.kdev@gmail.com>
Date: Wed, 24 Aug 2016 18:04:27 -0400
Subject: ARM: dts: NSP: Add QSPI nodes to NSPI and bcm958625k DTSes
Adding QSPI Device Tree node compatible with the new spi-bcm-qspi driver for
the Broadcom Northstar Plus SoC DTSI and bcm958625k reference board.
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/bcm-nsp.dtsi | 31 ++++++++++++++++++++++++++++++-
arch/arm/boot/dts/bcm958625k.dts | 34 ++++++++++++++++++++++++++++++++++
2 files changed, 64 insertions(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 7c9e0fae9bb9..7502556143f0 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -160,7 +160,7 @@
axi {
compatible = "simple-bus";
- ranges = <0x00000000 0x18000000 0x0011ba08>;
+ ranges = <0x00000000 0x18000000 0x0011c40a>;
#address-cells = <1>;
#size-cells = <1>;
@@ -254,6 +254,35 @@
reg = <0x33000 0x14>;
};
+ qspi: qspi@27200 {
+ compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi";
+ reg = <0x027200 0x184>,
+ <0x027000 0x124>,
+ <0x11c408 0x004>,
+ <0x0273a0 0x01c>;
+ reg-names = "mspi", "bspi", "intr_regs",
+ "intr_status_reg";
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "spi_lr_fullness_reached",
+ "spi_lr_session_aborted",
+ "spi_lr_impatient",
+ "spi_lr_session_done",
+ "spi_lr_overhead",
+ "mspi_done",
+ "mspi_halted";
+ clocks = <&iprocmed>;
+ clock-names = "iprocmed";
+ num-cs = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
ccbtimer0: timer@34000 {
compatible = "arm,sp804";
reg = <0x34000 0x1000>;
diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts
index 05c5f98c8782..59d96fb91583 100644
--- a/arch/arm/boot/dts/bcm958625k.dts
+++ b/arch/arm/boot/dts/bcm958625k.dts
@@ -139,3 +139,37 @@
groups = "nand_grp";
};
};
+
+&qspi {
+ bspi-sel = <0>;
+ flash: m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "m25p80";
+ reg = <0x0>;
+ spi-max-frequency = <12500000>;
+ m25p,fast-read;
+ spi-cpol;
+ spi-cpha;
+
+ partition@0 {
+ label = "boot";
+ reg = <0x00000000 0x000a0000>;
+ };
+
+ partition@a0000 {
+ label = "env";
+ reg = <0x000a0000 0x00060000>;
+ };
+
+ partition@100000 {
+ label = "system";
+ reg = <0x00100000 0x00600000>;
+ };
+
+ partition@700000 {
+ label = "rootfs";
+ reg = <0x00700000 0x01900000>;
+ };
+ };
+};
--
cgit
From 54b902a4cd020cf0208d6cdb7e859adecdcd8216 Mon Sep 17 00:00:00 2001
From: Rafał Miłecki <rafal@milecki.pl>
Date: Wed, 21 Sep 2016 22:58:32 +0200
Subject: ARM: BCM5301X: Add separated DTS include file for BCM47094
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Use it to store BCM47094 specific properties/values and avoid repeating
them in device DTS files.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts | 3 +--
arch/arm/boot/dts/bcm47094-netgear-r8500.dts | 3 +--
arch/arm/boot/dts/bcm47094.dtsi | 11 +++++++++++
3 files changed, 13 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/boot/dts/bcm47094.dtsi
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
index c8c0b3616935..661348dbb7ce 100644
--- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
+++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
@@ -9,7 +9,7 @@
/dts-v1/;
-#include "bcm4708.dtsi"
+#include "bcm47094.dtsi"
#include "bcm5301x-nand-cs0-bch1.dtsi"
/ {
@@ -107,7 +107,6 @@
&uart0 {
status = "okay";
- clock-frequency = <125000000>;
};
&usb3 {
diff --git a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts
index 10db4f8f2a44..521b4155de60 100644
--- a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts
+++ b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts
@@ -6,7 +6,7 @@
/dts-v1/;
-#include "bcm4708.dtsi"
+#include "bcm47094.dtsi"
#include "bcm5301x-nand-cs0-bch8.dtsi"
/ {
@@ -100,5 +100,4 @@
&uart0 {
status = "okay";
- clock-frequency = <125000000>;
};
diff --git a/arch/arm/boot/dts/bcm47094.dtsi b/arch/arm/boot/dts/bcm47094.dtsi
new file mode 100644
index 000000000000..f03976597a6d
--- /dev/null
+++ b/arch/arm/boot/dts/bcm47094.dtsi
@@ -0,0 +1,11 @@
+/*
+ * Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
+ *
+ * Licensed under the ISC license.
+ */
+
+#include "bcm4708.dtsi"
+
+&uart0 {
+ clock-frequency = <125000000>;
+};
--
cgit
From fa87b008da3fcfc030545a48310dbfddd538a3c7 Mon Sep 17 00:00:00 2001
From: Rafał Miłecki <rafal@milecki.pl>
Date: Wed, 21 Sep 2016 22:58:33 +0200
Subject: ARM: BCM5301X: Enable UART on Netgear R8000
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
It was tested by LEDE users, all we need is to adjust clock frequency.
While we're at it create a separated DTS include file to share code with
other BCM4709 devices easier.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts | 2 +-
arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts | 2 +-
arch/arm/boot/dts/bcm4709-netgear-r7000.dts | 2 +-
arch/arm/boot/dts/bcm4709-netgear-r8000.dts | 6 +++++-
arch/arm/boot/dts/bcm4709.dtsi | 11 +++++++++++
5 files changed, 19 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/boot/dts/bcm4709.dtsi
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts
index 8ade7def2e8a..eac0f52e5ebd 100644
--- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts
+++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts
@@ -9,7 +9,7 @@
/dts-v1/;
-#include "bcm4708.dtsi"
+#include "bcm4709.dtsi"
#include "bcm5301x-nand-cs0-bch8.dtsi"
/ {
diff --git a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts
index 0653e7ef248c..aab39c9864da 100644
--- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts
+++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts
@@ -9,7 +9,7 @@
/dts-v1/;
-#include "bcm4708.dtsi"
+#include "bcm4709.dtsi"
#include "bcm5301x-nand-cs0-bch8.dtsi"
/ {
diff --git a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts
index a22ed144040b..fd38d2aa3521 100644
--- a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts
+++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts
@@ -9,7 +9,7 @@
/dts-v1/;
-#include "bcm4708.dtsi"
+#include "bcm4709.dtsi"
#include "bcm5301x-nand-cs0-bch8.dtsi"
/ {
diff --git a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts
index ca181516c28a..92f8a7219e98 100644
--- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts
+++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts
@@ -9,7 +9,7 @@
/dts-v1/;
-#include "bcm4708.dtsi"
+#include "bcm4709.dtsi"
#include "bcm5301x-nand-cs0-bch8.dtsi"
/ {
@@ -107,6 +107,10 @@
};
};
+&uart0 {
+ status = "okay";
+};
+
&usb2 {
vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>;
};
diff --git a/arch/arm/boot/dts/bcm4709.dtsi b/arch/arm/boot/dts/bcm4709.dtsi
new file mode 100644
index 000000000000..f03976597a6d
--- /dev/null
+++ b/arch/arm/boot/dts/bcm4709.dtsi
@@ -0,0 +1,11 @@
+/*
+ * Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
+ *
+ * Licensed under the ISC license.
+ */
+
+#include "bcm4708.dtsi"
+
+&uart0 {
+ clock-frequency = <125000000>;
+};
--
cgit
From 92b7b6ad1a095fd72561a33855f93dfde5b2324f Mon Sep 17 00:00:00 2001
From: Rafał Miłecki <rafal@milecki.pl>
Date: Wed, 21 Sep 2016 22:58:34 +0200
Subject: ARM: BCM5301X: Specify USB 3.0 PHY in DT
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Driver for Northstar USB 3.0 PHY has been recently added under the name
phy-bcm-ns-usb3. Add binding for it into the DT files.
The only slightly tricky part is BCM47094 which uses different PHY
version and requires different compatible value.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/bcm47094.dtsi | 6 ++++++
arch/arm/boot/dts/bcm5301x.dtsi | 7 +++++++
2 files changed, 13 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/bcm47094.dtsi b/arch/arm/boot/dts/bcm47094.dtsi
index f03976597a6d..4f09aa0114e6 100644
--- a/arch/arm/boot/dts/bcm47094.dtsi
+++ b/arch/arm/boot/dts/bcm47094.dtsi
@@ -6,6 +6,12 @@
#include "bcm4708.dtsi"
+/ {
+ usb3_phy: usb3-phy {
+ compatible = "brcm,ns-bx-usb3-phy";
+ };
+};
+
&uart0 {
clock-frequency = <125000000>;
};
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index ae4b3880616d..f09a2bb08979 100644
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -149,6 +149,13 @@
clock-names = "phy-ref-clk";
};
+ usb3_phy: usb3-phy {
+ compatible = "brcm,ns-ax-usb3-phy";
+ reg = <0x18105000 0x1000>, <0x18003000 0x1000>;
+ reg-names = "dmp", "ccb-mii";
+ #phy-cells = <0>;
+ };
+
axi@18000000 {
compatible = "brcm,bus-axi";
reg = <0x18000000 0x1000>;
--
cgit
From fe91846397ca9ac1b4b0f913676a057b1ecabbc2 Mon Sep 17 00:00:00 2001
From: Dan Haab <dhaab@luxul.com>
Date: Tue, 27 Sep 2016 11:27:10 -0600
Subject: ARM: BCM5301X: Add DT for Luxul XAP-1510
Luxul XAP-1510 is an AP device based on BCM4708 SoC with 2 x BCM4360
chipsets on PCB connected using PCIe.
Signed-off-by: Dan Haab <dhaab@luxul.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts | 64 ++++++++++++++++++++++++++++
2 files changed, 65 insertions(+)
create mode 100644 arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 103c2cf56f68..fd4e299871a7 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -75,6 +75,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
bcm4708-asus-rt-ac56u.dtb \
bcm4708-asus-rt-ac68u.dtb \
bcm4708-buffalo-wzr-1750dhp.dtb \
+ bcm4708-luxul-xap-1510.dtb \
bcm4708-luxul-xwc-1000.dtb \
bcm4708-netgear-r6250.dtb \
bcm4708-netgear-r6300-v2.dtb \
diff --git a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts
new file mode 100644
index 000000000000..35e6ed6a3ef7
--- /dev/null
+++ b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts
@@ -0,0 +1,64 @@
+/*
+ * Copyright 2016 Luxul Inc.
+ *
+ * Licensed under the ISC license.
+ */
+
+/dts-v1/;
+
+#include "bcm4708.dtsi"
+
+/ {
+ compatible = "luxul,xap-1510v1", "brcm,bcm4708";
+ model = "Luxul XAP-1510 V1";
+
+ chosen {
+ bootargs = "console=ttyS0,115200 earlycon";
+ };
+
+ memory {
+ reg = <0x00000000 0x08000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ 5ghz {
+ label = "bcm53xx:blue:5ghz";
+ gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "none";
+ };
+
+ 2ghz {
+ label = "bcm53xx:blue:2ghz";
+ gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "none";
+ };
+
+ status {
+ label = "bcm53xx:green:status";
+ gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "timer";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ restart {
+ label = "Reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&spi_nor {
+ status = "okay";
+};
--
cgit
From 4335e6fd58b8771ac15f949307b088f7df60c592 Mon Sep 17 00:00:00 2001
From: Dan Haab <dhaab@luxul.com>
Date: Tue, 27 Sep 2016 11:27:11 -0600
Subject: ARM: BCM5301X: Add DT for Luxul XWR-3100
Luxul XWR-3100 is a wireless router based on BCM47094 SoC with two
4366c0 FullMAC PCIe cards on the PCB. It uses NAND with BCH-4 ECC
algorithm.
Signed-off-by: Dan Haab <dhaab@luxul.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts | 111 ++++++++++++++++++++++++++
arch/arm/boot/dts/bcm5301x-nand-cs0-bch4.dtsi | 13 +++
3 files changed, 125 insertions(+)
create mode 100644 arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
create mode 100644 arch/arm/boot/dts/bcm5301x-nand-cs0-bch4.dtsi
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index fd4e299871a7..837703ac79e8 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -88,6 +88,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
bcm4709-netgear-r7000.dtb \
bcm4709-netgear-r8000.dtb \
bcm47094-dlink-dir-885l.dtb \
+ bcm47094-luxul-xwr-3100.dtb \
bcm47094-netgear-r8500.dtb \
bcm94708.dtb \
bcm94709.dtb \
diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
new file mode 100644
index 000000000000..169b35fe5651
--- /dev/null
+++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
@@ -0,0 +1,111 @@
+/*
+ * Copyright 2016 Luxul Inc.
+ *
+ * Licensed under the ISC license.
+ */
+
+/dts-v1/;
+
+#include "bcm47094.dtsi"
+#include "bcm5301x-nand-cs0-bch4.dtsi"
+
+/ {
+ compatible = "luxul,xwr-3100v1", "brcm,bcm47094", "brcm,bcm4708";
+ model = "Luxul XWR-3100 V1";
+
+ chosen {
+ bootargs = "console=ttyS0,115200 earlycon";
+ };
+
+ memory {
+ reg = <0x00000000 0x08000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ power {
+ label = "bcm53xx:green:power";
+ gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-on";
+ };
+
+ lan3 {
+ label = "bcm53xx:green:lan1";
+ gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-off";
+ };
+
+ lan4 {
+ label = "bcm53xx:green:lan0";
+ gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-off";
+ };
+
+ wan {
+ label = "bcm53xx:green:wan";
+ gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-off";
+ };
+
+ lan1 {
+ label = "bcm53xx:green:lan3";
+ gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-off";
+ };
+
+ lan2 {
+ label = "bcm53xx:green:lan2";
+ gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-off";
+ };
+
+ usb3 {
+ label = "bcm53xx:green:usb3";
+ gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-off";
+ };
+
+ status {
+ label = "bcm53xx:green:status";
+ gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "timer";
+ };
+
+ 2ghz {
+ label = "bcm53xx:green:2ghz";
+ gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-off";
+ };
+
+ 5ghz {
+ label = "bcm53xx:green:5ghz";
+ gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-off";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ restart {
+ label = "Reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&usb3 {
+ vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>;
+};
+
+&spi_nor {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm5301x-nand-cs0-bch4.dtsi b/arch/arm/boot/dts/bcm5301x-nand-cs0-bch4.dtsi
new file mode 100644
index 000000000000..b4e875df9528
--- /dev/null
+++ b/arch/arm/boot/dts/bcm5301x-nand-cs0-bch4.dtsi
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2016 Luxul Inc.
+ *
+ * Licensed under the ISC license.
+ */
+
+#include "bcm5301x-nand-cs0.dtsi"
+
+&nandcs {
+ nand-ecc-algo = "bch";
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+};
--
cgit
From 547f23183d9d77b51754689a71e3e58d085ccaec Mon Sep 17 00:00:00 2001
From: Rafał Miłecki <rafal@milecki.pl>
Date: Sat, 17 Sep 2016 22:13:46 +0200
Subject: ARM: BCM53573: Specify PMU and its ILP clock in the DT
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
ILP clock (sometimes called a "slow clock") is a part of PMU (Power
Management Unit). There has been recently added a driver for it, so add
a proper entry in the DT as well.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/bcm53573.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/bcm53573.dtsi b/arch/arm/boot/dts/bcm53573.dtsi
index efa07de50969..e2c496a96c32 100644
--- a/arch/arm/boot/dts/bcm53573.dtsi
+++ b/arch/arm/boot/dts/bcm53573.dtsi
@@ -143,5 +143,17 @@
gmac1: ethernet@b000 {
reg = <0xb000 0x1000>;
};
+
+ pmu@12000 {
+ compatible = "simple-mfd", "syscon";
+ reg = <0x00012000 0x00001000>;
+
+ ilp: ilp {
+ compatible = "brcm,bcm53573-ilp";
+ clocks = <&alp>;
+ #clock-cells = <0>;
+ clock-output-names = "ilp";
+ };
+ };
};
};
--
cgit
From b350e9dd1f782933ff587d20259371acdc1213c8 Mon Sep 17 00:00:00 2001
From: Scott Branden <scott.branden@broadcom.com>
Date: Sat, 8 Oct 2016 13:34:26 -0700
Subject: ARM: dts: cygnus: fix naming of pinctrl node
Remove 0x from pinctrl node to match device tree naming convention.
Signed-off-by: Scott Branden <scott.branden@broadcom.com>
Reviewed-by: Ray Jui <ray.jui@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/bcm-cygnus.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi
index fabc9f36c408..539c58f12f51 100644
--- a/arch/arm/boot/dts/bcm-cygnus.dtsi
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -108,7 +108,7 @@
};
};
- pinctrl: pinctrl@0x0301d0c8 {
+ pinctrl: pinctrl@0301d0c8 {
compatible = "brcm,cygnus-pinmux";
reg = <0x0301d0c8 0x30>,
<0x0301d24c 0x2c>;
--
cgit
From d724f945958966f2b92dfbd7cf888ac4bcc4805f Mon Sep 17 00:00:00 2001
From: Patrice Chotard <patrice.chotard@st.com>
Date: Thu, 20 Oct 2016 15:15:02 +0200
Subject: ARM: dts: remove STiH416-b2020e.dts
Since v4.8, STiH415/416 clock support has
been removed [1], these platform doesn't boot.
We can remove DTS files related to these socs.
[1] https://patchwork.kernel.org/patch/9157571/
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/Makefile | 1 -
arch/arm/boot/dts/stih416-b2020e.dts | 65 ------------------------------------
2 files changed, 66 deletions(-)
delete mode 100644 arch/arm/boot/dts/stih416-b2020e.dts
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index befcd2619902..7d694e753c18 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -716,7 +716,6 @@ dtb-$(CONFIG_ARCH_STI) += \
stih415-b2020.dtb \
stih416-b2000.dtb \
stih416-b2020.dtb \
- stih416-b2020e.dtb \
stih418-b2199.dtb
dtb-$(CONFIG_ARCH_STM32)+= \
stm32f429-disco.dtb \
diff --git a/arch/arm/boot/dts/stih416-b2020e.dts b/arch/arm/boot/dts/stih416-b2020e.dts
deleted file mode 100644
index de320cd067de..000000000000
--- a/arch/arm/boot/dts/stih416-b2020e.dts
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Copyright (C) 2014 STMicroelectronics (R&D) Limited.
- * Author: Lee Jones <lee.jones@linaro.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * publishhed by the Free Software Foundation.
- */
-/dts-v1/;
-#include "stih416.dtsi"
-#include "stih41x-b2020.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-/ {
- model = "STiH416 B2020 REV-E";
- compatible = "st,stih416-b2020", "st,stih416";
-
- soc {
- leds {
- compatible = "gpio-leds";
- red {
- label = "Front Panel LED";
- gpios = <&pio4 1 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- green {
- gpios = <&pio1 3 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
- };
-
- ethernet1: dwmac@fef08000 {
- snps,reset-gpio = <&pio0 7>;
- };
-
- mmc1: sdhci@fe81f000 {
- status = "okay";
- bus-width = <8>;
- non-removable;
- };
-
- miphy365x_phy: phy@fe382000 {
- phy_port0: port@fe382000 {
- st,sata-gen = <3>;
- };
-
- phy_port1: port@fe38a000 {
- st,pcie-tx-pol-inv;
- };
- };
-
- sata0: sata@fe380000{
- status = "okay";
- };
-
- /* SAS PWM Module */
- pwm0: pwm@fed10000 {
- status = "okay";
- };
-
- /* SBC PWM Module */
- pwm1: pwm@fe510000 {
- status = "okay";
- };
- };
-};
--
cgit
From ee6310e8b2095e593a7d6f391105d572adad5a06 Mon Sep 17 00:00:00 2001
From: Patrice Chotard <patrice.chotard@st.com>
Date: Thu, 20 Oct 2016 15:15:43 +0200
Subject: ARM: dts: remove STiH416-b2020.dts
Since v4.8, STiH415/416 clock support has
been removed [1], these platform doesn't boot.
We can remove DTS files related to these socs.
[1] https://patchwork.kernel.org/patch/9157571/
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/Makefile | 1 -
arch/arm/boot/dts/stih416-b2020.dts | 37 -------------------------------------
2 files changed, 38 deletions(-)
delete mode 100644 arch/arm/boot/dts/stih416-b2020.dts
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7d694e753c18..3ea1a9dd6cd1 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -715,7 +715,6 @@ dtb-$(CONFIG_ARCH_STI) += \
stih415-b2000.dtb \
stih415-b2020.dtb \
stih416-b2000.dtb \
- stih416-b2020.dtb \
stih418-b2199.dtb
dtb-$(CONFIG_ARCH_STM32)+= \
stm32f429-disco.dtb \
diff --git a/arch/arm/boot/dts/stih416-b2020.dts b/arch/arm/boot/dts/stih416-b2020.dts
deleted file mode 100644
index 200a81844765..000000000000
--- a/arch/arm/boot/dts/stih416-b2020.dts
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
- * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * publishhed by the Free Software Foundation.
- */
-/dts-v1/;
-#include "stih416.dtsi"
-#include "stih41x-b2020.dtsi"
-/ {
- model = "STiH416 B2020";
- compatible = "st,stih416-b2020", "st,stih416";
-
- soc {
- mmc1: sdhci@fe81f000 {
- status = "okay";
- bus-width = <8>;
- non-removable;
- };
-
- miphy365x_phy: phy@fe382000 {
- phy_port0: port@fe382000 {
- st,sata-gen = <3>;
- };
-
- phy_port1: port@fe38a000 {
- st,pcie-tx-pol-inv;
- };
- };
-
- sata0: sata@fe380000{
- status = "okay";
- };
- };
-};
--
cgit
From 495075275949123481a990103d3f9364b8f9ea0c Mon Sep 17 00:00:00 2001
From: Patrice Chotard <patrice.chotard@st.com>
Date: Thu, 20 Oct 2016 15:16:33 +0200
Subject: ARM: dts: remove STiH416-b2000.dts
Since v4.8, STiH415/416 clock support has
been removed [1], these platform doesn't boot.
We can remove DTS files related to these socs.
[1] https://patchwork.kernel.org/patch/9157571/
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/Makefile | 1 -
arch/arm/boot/dts/stih416-b2000.dts | 15 ---------------
2 files changed, 16 deletions(-)
delete mode 100644 arch/arm/boot/dts/stih416-b2000.dts
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 3ea1a9dd6cd1..d81154228fd3 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -714,7 +714,6 @@ dtb-$(CONFIG_ARCH_STI) += \
stih410-b2260.dtb \
stih415-b2000.dtb \
stih415-b2020.dtb \
- stih416-b2000.dtb \
stih418-b2199.dtb
dtb-$(CONFIG_ARCH_STM32)+= \
stm32f429-disco.dtb \
diff --git a/arch/arm/boot/dts/stih416-b2000.dts b/arch/arm/boot/dts/stih416-b2000.dts
deleted file mode 100644
index 488e80a5d69d..000000000000
--- a/arch/arm/boot/dts/stih416-b2000.dts
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
- * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * publishhed by the Free Software Foundation.
- */
-/dts-v1/;
-#include "stih416.dtsi"
-#include "stih41x-b2000.dtsi"
-/ {
- model = "STiH416 B2000";
- compatible = "st,stih416-b2000", "st,stih416";
-};
--
cgit
From 1047121a1cedb99dba6ca2af76b9f17c554207eb Mon Sep 17 00:00:00 2001
From: Patrice Chotard <patrice.chotard@st.com>
Date: Thu, 20 Oct 2016 15:17:33 +0200
Subject: ARM: dts: remove STiH416-clock.dtsi
Since v4.8, STiH415/416 clock support has
been removed [1], these platform doesn't boot.
We can remove DTS files related to these socs.
[1] https://patchwork.kernel.org/patch/9157571/
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stih416-clock.dtsi | 756 -----------------------------------
1 file changed, 756 deletions(-)
delete mode 100644 arch/arm/boot/dts/stih416-clock.dtsi
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/stih416-clock.dtsi b/arch/arm/boot/dts/stih416-clock.dtsi
deleted file mode 100644
index 5b4fb838cddb..000000000000
--- a/arch/arm/boot/dts/stih416-clock.dtsi
+++ /dev/null
@@ -1,756 +0,0 @@
-/*
- * Copyright (C) 2013 STMicroelectronics R&D Limited
- * <stlinux-devel@stlinux.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <dt-bindings/clock/stih416-clks.h>
-
-/ {
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- /*
- * Fixed 30MHz oscillator inputs to SoC
- */
- clk_sysin: clk-sysin {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <30000000>;
- };
-
- /*
- * ClockGenAs on SASG2
- */
- clockgen-a@fee62000 {
- reg = <0xfee62000 0xb48>;
-
- clk_s_a0_pll: clk-s-a0-pll {
- #clock-cells = <1>;
- compatible = "st,clkgena-plls-c65";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-a0-pll0-hs",
- "clk-s-a0-pll0-ls",
- "clk-s-a0-pll1";
- };
-
- clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
- #clock-cells = <0>;
- compatible = "st,clkgena-prediv-c65",
- "st,clkgena-prediv";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-a0-osc-prediv";
- };
-
- clk_s_a0_hs: clk-s-a0-hs {
- #clock-cells = <1>;
- compatible = "st,clkgena-divmux-c65-hs",
- "st,clkgena-divmux";
-
- clocks = <&clk_s_a0_osc_prediv>,
- <&clk_s_a0_pll 0>, /* PLL0 HS */
- <&clk_s_a0_pll 2>; /* PLL1 */
-
- clock-output-names = "clk-s-fdma-0",
- "clk-s-fdma-1",
- ""; /* clk-s-jit-sense */
- /* Fourth output unused */
- };
-
- clk_s_a0_ls: clk-s-a0-ls {
- #clock-cells = <1>;
- compatible = "st,clkgena-divmux-c65-ls",
- "st,clkgena-divmux";
-
- clocks = <&clk_s_a0_osc_prediv>,
- <&clk_s_a0_pll 1>, /* PLL0 LS */
- <&clk_s_a0_pll 2>; /* PLL1 */
-
- clock-output-names = "clk-s-icn-reg-0",
- "clk-s-icn-if-0",
- "clk-s-icn-reg-lp-0",
- "clk-s-emiss",
- "clk-s-eth1-phy",
- "clk-s-mii-ref-out";
- /* Remaining outputs unused */
- };
- };
-
- clockgen-a@fee81000 {
- reg = <0xfee81000 0xb48>;
-
- clk_s_a1_pll: clk-s-a1-pll {
- #clock-cells = <1>;
- compatible = "st,clkgena-plls-c65";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-a1-pll0-hs",
- "clk-s-a1-pll0-ls",
- "clk-s-a1-pll1";
- };
-
- clk_s_a1_osc_prediv: clk-s-a1-osc-prediv {
- #clock-cells = <0>;
- compatible = "st,clkgena-prediv-c65",
- "st,clkgena-prediv";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-a1-osc-prediv";
- };
-
- clk_s_a1_hs: clk-s-a1-hs {
- #clock-cells = <1>;
- compatible = "st,clkgena-divmux-c65-hs",
- "st,clkgena-divmux";
-
- clocks = <&clk_s_a1_osc_prediv>,
- <&clk_s_a1_pll 0>, /* PLL0 HS */
- <&clk_s_a1_pll 2>; /* PLL1 */
-
- clock-output-names = "", /* Reserved */
- "", /* Reserved */
- "clk-s-stac-phy",
- "clk-s-vtac-tx-phy";
- };
-
- clk_s_a1_ls: clk-s-a1-ls {
- #clock-cells = <1>;
- compatible = "st,clkgena-divmux-c65-ls",
- "st,clkgena-divmux";
-
- clocks = <&clk_s_a1_osc_prediv>,
- <&clk_s_a1_pll 1>, /* PLL0 LS */
- <&clk_s_a1_pll 2>; /* PLL1 */
-
- clock-output-names = "clk-s-icn-if-2",
- "clk-s-card-mmc-0",
- "clk-s-icn-if-1",
- "clk-s-gmac0-phy",
- "clk-s-nand-ctrl",
- "", /* Reserved */
- "clk-s-mii0-ref-out",
- "clk-s-stac-sys",
- "clk-s-card-mmc-1";
- /* Remaining outputs unused */
- };
- };
-
- /*
- * ClockGenAs on MPE42
- */
- clockgen-a@fde12000 {
- reg = <0xfde12000 0xb50>;
-
- clk_m_a0_pll0: clk-m-a0-pll0 {
- #clock-cells = <1>;
- compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-m-a0-pll0-phi0",
- "clk-m-a0-pll0-phi1",
- "clk-m-a0-pll0-phi2",
- "clk-m-a0-pll0-phi3";
- };
-
- clk_m_a0_pll1: clk-m-a0-pll1 {
- #clock-cells = <1>;
- compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-m-a0-pll1-phi0",
- "clk-m-a0-pll1-phi1",
- "clk-m-a0-pll1-phi2",
- "clk-m-a0-pll1-phi3";
- };
-
- clk_m_a0_osc_prediv: clk-m-a0-osc-prediv {
- #clock-cells = <0>;
- compatible = "st,clkgena-prediv-c32",
- "st,clkgena-prediv";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-m-a0-osc-prediv";
- };
-
- clk_m_a0_div0: clk-m-a0-div0 {
- #clock-cells = <1>;
- compatible = "st,clkgena-divmux-c32-odf0",
- "st,clkgena-divmux";
-
- clocks = <&clk_m_a0_osc_prediv>,
- <&clk_m_a0_pll0 0>, /* PLL0 PHI0 */
- <&clk_m_a0_pll1 0>; /* PLL1 PHI0 */
-
- clock-output-names = "", /* Unused */
- "", /* Unused */
- "clk-m-fdma-12",
- "", /* Unused */
- "clk-m-pp-dmu-0",
- "clk-m-pp-dmu-1",
- "clk-m-icm-lmi",
- "clk-m-vid-dmu-0";
- };
-
- clk_m_a0_div1: clk-m-a0-div1 {
- #clock-cells = <1>;
- compatible = "st,clkgena-divmux-c32-odf1",
- "st,clkgena-divmux";
-
- clocks = <&clk_m_a0_osc_prediv>,
- <&clk_m_a0_pll0 1>, /* PLL0 PHI1 */
- <&clk_m_a0_pll1 1>; /* PLL1 PHI1 */
-
- clock-output-names = "clk-m-vid-dmu-1",
- "", /* Unused */
- "clk-m-a9-ext2f",
- "clk-m-st40rt",
- "clk-m-st231-dmu-0",
- "clk-m-st231-dmu-1",
- "clk-m-st231-aud",
- "clk-m-st231-gp-0";
- };
-
- clk_m_a0_div2: clk-m-a0-div2 {
- #clock-cells = <1>;
- compatible = "st,clkgena-divmux-c32-odf2",
- "st,clkgena-divmux";
-
- clocks = <&clk_m_a0_osc_prediv>,
- <&clk_m_a0_pll0 2>, /* PLL0 PHI2 */
- <&clk_m_a0_pll1 2>; /* PLL1 PHI2 */
-
- clock-output-names = "clk-m-st231-gp-1",
- "clk-m-icn-cpu",
- "clk-m-icn-stac",
- "clk-m-tx-icn-dmu-0",
- "clk-m-tx-icn-dmu-1",
- "clk-m-tx-icn-ts",
- "clk-m-icn-vdp-0",
- "clk-m-icn-vdp-1";
- };
-
- clk_m_a0_div3: clk-m-a0-div3 {
- #clock-cells = <1>;
- compatible = "st,clkgena-divmux-c32-odf3",
- "st,clkgena-divmux";
-
- clocks = <&clk_m_a0_osc_prediv>,
- <&clk_m_a0_pll0 3>, /* PLL0 PHI3 */
- <&clk_m_a0_pll1 3>; /* PLL1 PHI3 */
-
- clock-output-names = "", /* Unused */
- "", /* Unused */
- "", /* Unused */
- "", /* Unused */
- "clk-m-icn-vp8",
- "", /* Unused */
- "clk-m-icn-reg-11",
- "clk-m-a9-trace";
- };
- };
-
- clockgen-a@fd6db000 {
- reg = <0xfd6db000 0xb50>;
-
- clk_m_a1_pll0: clk-m-a1-pll0 {
- #clock-cells = <1>;
- compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-m-a1-pll0-phi0",
- "clk-m-a1-pll0-phi1",
- "clk-m-a1-pll0-phi2",
- "clk-m-a1-pll0-phi3";
- };
-
- clk_m_a1_pll1: clk-m-a1-pll1 {
- #clock-cells = <1>;
- compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-m-a1-pll1-phi0",
- "clk-m-a1-pll1-phi1",
- "clk-m-a1-pll1-phi2",
- "clk-m-a1-pll1-phi3";
- };
-
- clk_m_a1_osc_prediv: clk-m-a1-osc-prediv {
- #clock-cells = <0>;
- compatible = "st,clkgena-prediv-c32",
- "st,clkgena-prediv";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-m-a1-osc-prediv";
- };
-
- clk_m_a1_div0: clk-m-a1-div0 {
- #clock-cells = <1>;
- compatible = "st,clkgena-divmux-c32-odf0",
- "st,clkgena-divmux";
-
- clocks = <&clk_m_a1_osc_prediv>,
- <&clk_m_a1_pll0 0>, /* PLL0 PHI0 */
- <&clk_m_a1_pll1 0>; /* PLL1 PHI0 */
-
- clock-output-names = "", /* Unused */
- "clk-m-fdma-10",
- "clk-m-fdma-11",
- "clk-m-hva-alt",
- "clk-m-proc-sc",
- "clk-m-tp",
- "clk-m-rx-icn-dmu-0",
- "clk-m-rx-icn-dmu-1";
- };
-
- clk_m_a1_div1: clk-m-a1-div1 {
- #clock-cells = <1>;
- compatible = "st,clkgena-divmux-c32-odf1",
- "st,clkgena-divmux";
-
- clocks = <&clk_m_a1_osc_prediv>,
- <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */
- <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */
-
- clock-output-names = "clk-m-rx-icn-ts",
- "clk-m-rx-icn-vdp-0",
- "", /* Unused */
- "clk-m-prv-t1-bus",
- "clk-m-icn-reg-12",
- "clk-m-icn-reg-10",
- "", /* Unused */
- "clk-m-icn-st231";
- };
-
- clk_m_a1_div2: clk-m-a1-div2 {
- #clock-cells = <1>;
- compatible = "st,clkgena-divmux-c32-odf2",
- "st,clkgena-divmux";
-
- clocks = <&clk_m_a1_osc_prediv>,
- <&clk_m_a1_pll0 2>, /* PLL0 PHI2 */
- <&clk_m_a1_pll1 2>; /* PLL1 PHI2 */
-
- clock-output-names = "clk-m-fvdp-proc-alt",
- "clk-m-icn-reg-13",
- "clk-m-tx-icn-gpu",
- "clk-m-rx-icn-gpu",
- "", /* Unused */
- "", /* Unused */
- "", /* clk-m-apb-pm-12 */
- ""; /* Unused */
- };
-
- clk_m_a1_div3: clk-m-a1-div3 {
- #clock-cells = <1>;
- compatible = "st,clkgena-divmux-c32-odf3",
- "st,clkgena-divmux";
-
- clocks = <&clk_m_a1_osc_prediv>,
- <&clk_m_a1_pll0 3>, /* PLL0 PHI3 */
- <&clk_m_a1_pll1 3>; /* PLL1 PHI3 */
-
- clock-output-names = "", /* Unused */
- "", /* Unused */
- "", /* Unused */
- "", /* Unused */
- "", /* Unused */
- "", /* Unused */
- "", /* Unused */
- ""; /* clk-m-gpu-alt */
- };
- };
-
- clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2 {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&clk_m_a0_div1 2>;
- clock-div = <2>;
- clock-mult = <1>;
- };
-
- clockgen-a@fd345000 {
- reg = <0xfd345000 0xb50>;
-
- clk_m_a2_pll0: clk-m-a2-pll0 {
- #clock-cells = <1>;
- compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-m-a2-pll0-phi0",
- "clk-m-a2-pll0-phi1",
- "clk-m-a2-pll0-phi2",
- "clk-m-a2-pll0-phi3";
- };
-
- clk_m_a2_pll1: clk-m-a2-pll1 {
- #clock-cells = <1>;
- compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-m-a2-pll1-phi0",
- "clk-m-a2-pll1-phi1",
- "clk-m-a2-pll1-phi2",
- "clk-m-a2-pll1-phi3";
- };
-
- clk_m_a2_osc_prediv: clk-m-a2-osc-prediv {
- #clock-cells = <0>;
- compatible = "st,clkgena-prediv-c32",
- "st,clkgena-prediv";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-m-a2-osc-prediv";
- };
-
- clk_m_a2_div0: clk-m-a2-div0 {
- #clock-cells = <1>;
- compatible = "st,clkgena-divmux-c32-odf0",
- "st,clkgena-divmux";
-
- clocks = <&clk_m_a2_osc_prediv>,
- <&clk_m_a2_pll0 0>, /* PLL0 PHI0 */
- <&clk_m_a2_pll1 0>; /* PLL1 PHI0 */
-
- clock-output-names = "clk-m-vtac-main-phy",
- "clk-m-vtac-aux-phy",
- "clk-m-stac-phy",
- "clk-m-stac-sys",
- "", /* clk-m-mpestac-pg */
- "", /* clk-m-mpestac-wc */
- "", /* clk-m-mpevtacaux-pg*/
- ""; /* clk-m-mpevtacmain-pg*/
- };
-
- clk_m_a2_div1: clk-m-a2-div1 {
- #clock-cells = <1>;
- compatible = "st,clkgena-divmux-c32-odf1",
- "st,clkgena-divmux";
-
- clocks = <&clk_m_a2_osc_prediv>,
- <&clk_m_a2_pll0 1>, /* PLL0 PHI1 */
- <&clk_m_a2_pll1 1>; /* PLL1 PHI1 */
-
- clock-output-names = "", /* clk-m-mpevtacrx0-wc */
- "", /* clk-m-mpevtacrx1-wc */
- "clk-m-compo-main",
- "clk-m-compo-aux",
- "clk-m-bdisp-0",
- "clk-m-bdisp-1",
- "clk-m-icn-bdisp",
- "clk-m-icn-compo";
- };
-
- clk_m_a2_div2: clk-m-a2-div2 {
- #clock-cells = <1>;
- compatible = "st,clkgena-divmux-c32-odf2",
- "st,clkgena-divmux";
-
- clocks = <&clk_m_a2_osc_prediv>,
- <&clk_m_a2_pll0 2>, /* PLL0 PHI2 */
- <&clk_m_a2_pll1 2>; /* PLL1 PHI2 */
-
- clock-output-names = "clk-m-icn-vdp-2",
- "", /* Unused */
- "clk-m-icn-reg-14",
- "clk-m-mdtp",
- "clk-m-jpegdec",
- "", /* Unused */
- "clk-m-dcephy-impctrl",
- ""; /* Unused */
- };
-
- clk_m_a2_div3: clk-m-a2-div3 {
- #clock-cells = <1>;
- compatible = "st,clkgena-divmux-c32-odf3",
- "st,clkgena-divmux";
-
- clocks = <&clk_m_a2_osc_prediv>,
- <&clk_m_a2_pll0 3>, /* PLL0 PHI3 */
- <&clk_m_a2_pll1 3>; /* PLL1 PHI3 */
-
- clock-output-names = "", /* Unused */
- ""; /* clk-m-apb-pm-11 */
- /* Remaining outputs unused */
- };
- };
-
- /*
- * A9 PLL
- */
- clockgen-a9@fdde08b0 {
- reg = <0xfdde08b0 0x70>;
-
- clockgen_a9_pll: clockgen-a9-pll {
- #clock-cells = <1>;
- compatible = "st,stih416-plls-c32-a9", "st,clkgen-plls-c32";
-
- clocks = <&clk_sysin>;
- clock-output-names = "clockgen-a9-pll-odf";
- };
- };
-
- /*
- * ARM CPU related clocks
- */
- clk_m_a9: clk-m-a9@fdde08ac {
- #clock-cells = <0>;
- compatible = "st,stih416-clkgen-a9-mux", "st,clkgen-mux";
- reg = <0xfdde08ac 0x4>;
- clocks = <&clockgen_a9_pll 0>,
- <&clockgen_a9_pll 0>,
- <&clk_m_a0_div1 2>,
- <&clk_m_a9_ext2f_div2>;
- };
-
- /*
- * ARM Peripheral clock for timers
- */
- arm_periph_clk: clk-m-a9-periphs {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&clk_m_a9>;
- clock-div = <2>;
- clock-mult = <1>;
- };
-
- /*
- * Frequency synthesizers on the SASG2
- */
- clockgen_b0: clockgen-b0@fee108b4 {
- #clock-cells = <1>;
- compatible = "st,stih416-quadfs216", "st,quadfs";
- reg = <0xfee108b4 0x44>;
-
- clocks = <&clk_sysin>;
- clock-output-names = "clk-s-usb48",
- "clk-s-dss",
- "clk-s-stfe-frc-2",
- "clk-s-thsens-scard";
- };
-
- clockgen_b1: clockgen-b1@fe8308c4 {
- #clock-cells = <1>;
- compatible = "st,stih416-quadfs216", "st,quadfs";
- reg = <0xfe8308c4 0x44>;
-
- clocks = <&clk_sysin>;
- clock-output-names = "clk-s-pcm-0",
- "clk-s-pcm-1",
- "clk-s-pcm-2",
- "clk-s-pcm-3";
- };
-
- clockgen_c: clockgen-c@fe8307d0 {
- #clock-cells = <1>;
- compatible = "st,stih416-quadfs432", "st,quadfs";
- reg = <0xfe8307d0 0x44>;
-
- clocks = <&clk_sysin>;
- clock-output-names = "clk-s-c-fs0-ch0",
- "clk-s-c-vcc-sd",
- "clk-s-c-fs0-ch2";
- };
-
- clk_s_vcc_hd: clk-s-vcc-hd@fe8308b8 {
- #clock-cells = <0>;
- compatible = "st,stih416-clkgenc-vcc-hd", "st,clkgen-mux";
- reg = <0xfe8308b8 0x4>; /* SYSCFG2558 */
-
- clocks = <&clk_sysin>,
- <&clockgen_c 0>;
- };
-
- /*
- * Add a dummy clock for the HDMI PHY for the VCC input mux
- */
- clk_s_tmds_fromphy: clk-s-tmds-fromphy {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
-
- clockgen_c_vcc: clockgen-c-vcc@fe8308ac {
- #clock-cells = <1>;
- compatible = "st,stih416-clkgenc", "st,clkgen-vcc";
- reg = <0xfe8308ac 0xc>; /* SYSCFG2555,2556,2557 */
-
- clocks = <&clk_s_vcc_hd>,
- <&clockgen_c 1>,
- <&clk_s_tmds_fromphy>,
- <&clockgen_c 2>;
-
- clock-output-names = "clk-s-pix-hdmi",
- "clk-s-pix-dvo",
- "clk-s-out-dvo",
- "clk-s-pix-hd",
- "clk-s-hddac",
- "clk-s-denc",
- "clk-s-sddac",
- "clk-s-pix-main",
- "clk-s-pix-aux",
- "clk-s-stfe-frc-0",
- "clk-s-ref-mcru",
- "clk-s-slave-mcru",
- "clk-s-tmds-hdmi",
- "clk-s-hdmi-reject-pll",
- "clk-s-thsens";
- };
-
- clockgen_d: clockgen-d@fee107e0 {
- #clock-cells = <1>;
- compatible = "st,stih416-quadfs216", "st,quadfs";
- reg = <0xfee107e0 0x44>;
-
- clocks = <&clk_sysin>;
- clock-output-names = "clk-s-ccsc",
- "clk-s-stfe-frc-1",
- "clk-s-tsout-1",
- "clk-s-mchi";
- };
-
- /*
- * Frequency synthesizers on the MPE42
- */
- clockgen_e: clockgen-e@fd3208bc {
- #clock-cells = <1>;
- compatible = "st,stih416-quadfs660-E", "st,quadfs";
- reg = <0xfd3208bc 0xb0>;
-
- clocks = <&clk_sysin>;
- clock-output-names = "clk-m-pix-mdtp-0",
- "clk-m-pix-mdtp-1",
- "clk-m-pix-mdtp-2",
- "clk-m-mpelpc";
- };
-
- clockgen_f: clockgen-f@fd320878 {
- #clock-cells = <1>;
- compatible = "st,stih416-quadfs660-F", "st,quadfs";
- reg = <0xfd320878 0xf0>;
-
- clocks = <&clk_sysin>;
- clock-output-names = "clk-m-main-vidfs",
- "clk-m-hva-fs",
- "clk-m-fvdp-vcpu",
- "clk-m-fvdp-proc-fs";
- };
-
- clk_m_fvdp_proc: clk-m-fvdp-proc@fd320910 {
- #clock-cells = <0>;
- compatible = "st,stih416-clkgenf-vcc-fvdp", "st,clkgen-mux";
- reg = <0xfd320910 0x4>; /* SYSCFG8580 */
-
- clocks = <&clk_m_a1_div2 0>,
- <&clockgen_f 3>;
- };
-
- clk_m_hva: clk-m-hva@fd690868 {
- #clock-cells = <0>;
- compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux";
- reg = <0xfd690868 0x4>; /* SYSCFG9538 */
-
- clocks = <&clockgen_f 1>,
- <&clk_m_a1_div0 3>;
- };
-
- clk_m_f_vcc_hd: clk-m-f-vcc-hd@fd32086c {
- #clock-cells = <0>;
- compatible = "st,stih416-clkgenf-vcc-hd", "st,clkgen-mux";
- reg = <0xfd32086c 0x4>; /* SYSCFG8539 */
-
- clocks = <&clockgen_c_vcc 7>,
- <&clockgen_f 0>;
- };
-
- clk_m_f_vcc_sd: clk-m-f-vcc-sd@fd32086c {
- #clock-cells = <0>;
- compatible = "st,stih416-clkgenf-vcc-sd", "st,clkgen-mux";
- reg = <0xfd32086c 0x4>; /* SYSCFG8539 */
-
- clocks = <&clockgen_c_vcc 8>,
- <&clockgen_f 1>;
- };
-
- /*
- * Add a dummy clock for the HDMIRx external signal clock
- */
- clk_m_pix_hdmirx_sas: clk-m-pix-hdmirx-sas {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
-
- clockgen_f_vcc: clockgen-f-vcc@fd32086c {
- #clock-cells = <1>;
- compatible = "st,stih416-clkgenf", "st,clkgen-vcc";
- reg = <0xfd32086c 0xc>; /* SYSCFG8539,8540,8541 */
-
- clocks = <&clk_m_f_vcc_hd>,
- <&clk_m_f_vcc_sd>,
- <&clockgen_f 0>,
- <&clk_m_pix_hdmirx_sas>;
-
- clock-output-names = "clk-m-pix-main-pipe",
- "clk-m-pix-aux-pipe",
- "clk-m-pix-main-cru",
- "clk-m-pix-aux-cru",
- "clk-m-xfer-be-compo",
- "clk-m-xfer-pip-compo",
- "clk-m-xfer-aux-compo",
- "clk-m-vsens",
- "clk-m-pix-hdmirx-0",
- "clk-m-pix-hdmirx-1";
- };
-
- /*
- * DDR PLL
- */
- clockgen-ddr@0xfdde07d8 {
- reg = <0xfdde07d8 0x110>;
-
- clockgen_ddr_pll: clockgen-ddr-pll {
- #clock-cells = <1>;
- compatible = "st,stih416-plls-c32-ddr", "st,clkgen-plls-c32";
-
- clocks = <&clk_sysin>;
- clock-output-names = "clockgen-ddr0",
- "clockgen-ddr1";
- };
- };
-
- /*
- * GPU PLL
- */
- clockgen-gpu@fd68ff00 {
- reg = <0xfd68ff00 0x910>;
-
- clockgen_gpu_pll: clockgen-gpu-pll {
- #clock-cells = <1>;
- compatible = "st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32";
-
- clocks = <&clk_sysin>;
- clock-output-names = "clockgen-gpu-pll";
- };
- };
- };
-};
--
cgit
From 3b3deba776d6cad94a084619c33ee649fbd2edb1 Mon Sep 17 00:00:00 2001
From: Patrice Chotard <patrice.chotard@st.com>
Date: Thu, 20 Oct 2016 15:18:10 +0200
Subject: ARM: dts: remove STiH416-pinctrl.dtsi
Since v4.8, STiH415/416 clock support has
been removed [1], these platform doesn't boot.
We can remove DTS files related to these socs.
[1] https://patchwork.kernel.org/patch/9157571/
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stih416-pinctrl.dtsi | 692 ---------------------------------
1 file changed, 692 deletions(-)
delete mode 100644 arch/arm/boot/dts/stih416-pinctrl.dtsi
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi
deleted file mode 100644
index 9c97f7e651a0..000000000000
--- a/arch/arm/boot/dts/stih416-pinctrl.dtsi
+++ /dev/null
@@ -1,692 +0,0 @@
-
-/*
- * Copyright (C) 2013 STMicroelectronics Limited.
- * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * publishhed by the Free Software Foundation.
- */
-#include "st-pincfg.h"
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-/ {
-
- aliases {
- gpio0 = &pio0;
- gpio1 = &pio1;
- gpio2 = &pio2;
- gpio3 = &pio3;
- gpio4 = &pio4;
- gpio5 = &pio40;
- gpio6 = &pio5;
- gpio7 = &pio6;
- gpio8 = &pio7;
- gpio9 = &pio8;
- gpio10 = &pio9;
- gpio11 = &pio10;
- gpio12 = &pio11;
- gpio13 = &pio12;
- gpio14 = &pio30;
- gpio15 = &pio31;
- gpio16 = &pio13;
- gpio17 = &pio14;
- gpio18 = &pio15;
- gpio19 = &pio16;
- gpio20 = &pio17;
- gpio21 = &pio18;
- gpio22 = &pio100;
- gpio23 = &pio101;
- gpio24 = &pio102;
- gpio25 = &pio103;
- gpio26 = &pio104;
- gpio27 = &pio105;
- gpio28 = &pio106;
- gpio29 = &pio107;
- };
-
- soc {
- pin-controller-sbc {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stih416-sbc-pinctrl";
- st,syscfg = <&syscfg_sbc>;
- reg = <0xfe61f080 0x4>;
- reg-names = "irqmux";
- interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irqmux";
- ranges = <0 0xfe610000 0x6000>;
-
- pio0: gpio@fe610000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0 0x100>;
- st,bank-name = "PIO0";
- };
- pio1: gpio@fe611000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1000 0x100>;
- st,bank-name = "PIO1";
- };
- pio2: gpio@fe612000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2000 0x100>;
- st,bank-name = "PIO2";
- };
- pio3: gpio@fe613000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x3000 0x100>;
- st,bank-name = "PIO3";
- };
- pio4: gpio@fe614000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x4000 0x100>;
- st,bank-name = "PIO4";
- };
- pio40: gpio@fe615000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x5000 0x100>;
- st,bank-name = "PIO40";
- st,retime-pin-mask = <0x7f>;
- };
-
- rc{
- pinctrl_ir: ir0 {
- st,pins {
- ir = <&pio4 0 ALT2 IN>;
- };
- };
- };
- sbc_serial1 {
- pinctrl_sbc_serial1: sbc_serial1 {
- st,pins {
- tx = <&pio2 6 ALT3 OUT>;
- rx = <&pio2 7 ALT3 IN>;
- };
- };
- };
-
- keyscan {
- pinctrl_keyscan: keyscan {
- st,pins {
- keyin0 = <&pio0 2 ALT2 IN>;
- keyin1 = <&pio0 3 ALT2 IN>;
- keyin2 = <&pio0 4 ALT2 IN>;
- keyin3 = <&pio2 6 ALT2 IN>;
-
- keyout0 = <&pio1 6 ALT2 OUT>;
- keyout1 = <&pio1 7 ALT2 OUT>;
- keyout2 = <&pio0 6 ALT2 OUT>;
- keyout3 = <&pio2 7 ALT2 OUT>;
- };
- };
- };
-
- sbc_i2c0 {
- pinctrl_sbc_i2c0_default: sbc_i2c0-default {
- st,pins {
- sda = <&pio4 6 ALT1 BIDIR>;
- scl = <&pio4 5 ALT1 BIDIR>;
- };
- };
- };
-
- usb {
- pinctrl_usb3: usb3 {
- st,pins {
- oc-detect = <&pio40 0 ALT1 IN>;
- pwr-enable = <&pio40 1 ALT1 OUT>;
- };
- };
- };
-
- sbc_i2c1 {
- pinctrl_sbc_i2c1_default: sbc_i2c1-default {
- st,pins {
- sda = <&pio3 2 ALT2 BIDIR>;
- scl = <&pio3 1 ALT2 BIDIR>;
- };
- };
- };
-
- gmac1 {
- pinctrl_mii1: mii1 {
- st,pins {
- txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
- txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
- txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
- txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
- txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
- txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
- txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
- col = <&pio0 7 ALT1 IN BYPASS 1000>;
-
- mdio = <&pio1 0 ALT1 OUT BYPASS 1500>;
- mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
- crs = <&pio1 2 ALT1 IN BYPASS 1000>;
- mdint = <&pio1 3 ALT1 IN BYPASS 0>;
- rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
-
- rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
- phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
- };
- };
- pinctrl_rgmii1: rgmii1-0 {
- st,pins {
- txd0 = <&pio0 0 ALT1 OUT DE_IO 500 CLK_A>;
- txd1 = <&pio0 1 ALT1 OUT DE_IO 500 CLK_A>;
- txd2 = <&pio0 2 ALT1 OUT DE_IO 500 CLK_A>;
- txd3 = <&pio0 3 ALT1 OUT DE_IO 500 CLK_A>;
- txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>;
- txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
-
- mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
- mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
- rxd0 = <&pio1 4 ALT1 IN DE_IO 500 CLK_A>;
- rxd1 = <&pio1 5 ALT1 IN DE_IO 500 CLK_A>;
- rxd2 = <&pio1 6 ALT1 IN DE_IO 500 CLK_A>;
- rxd3 = <&pio1 7 ALT1 IN DE_IO 500 CLK_A>;
-
- rxdv = <&pio2 0 ALT1 IN DE_IO 500 CLK_A>;
- rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
- phyclk = <&pio2 3 ALT4 OUT NICLK 0 CLK_B>;
-
- clk125= <&pio3 7 ALT4 IN NICLK 0 CLK_A>;
- };
- };
- };
-
- pwm1 {
- pinctrl_pwm1_chan0_default: pwm1-0-default {
- st,pins {
- pwm-out = <&pio3 0 ALT1 OUT>;
- pwm-capturein = <&pio3 2 ALT1 IN>;
-
- };
- };
- pinctrl_pwm1_chan1_default: pwm1-1-default {
- st,pins {
- pwm-out = <&pio4 4 ALT1 OUT>;
- pwm-capturein = <&pio4 3 ALT1 IN>;
- };
- };
- pinctrl_pwm1_chan2_default: pwm1-2-default {
- st,pins {
- pwm-out = <&pio4 6 ALT3 OUT>;
- };
- };
- pinctrl_pwm1_chan3_default: pwm1-3-default {
- st,pins {
- pwm-out = <&pio4 7 ALT3 OUT>;
- };
- };
- };
- };
-
- pin-controller-front {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stih416-front-pinctrl";
- st,syscfg = <&syscfg_front>;
- reg = <0xfee0f080 0x4>;
- reg-names = "irqmux";
- interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irqmux";
- ranges = <0 0xfee00000 0x10000>;
-
- pio5: gpio@fee00000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0 0x100>;
- st,bank-name = "PIO5";
- };
- pio6: gpio@fee01000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1000 0x100>;
- st,bank-name = "PIO6";
- };
- pio7: gpio@fee02000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2000 0x100>;
- st,bank-name = "PIO7";
- };
- pio8: gpio@fee03000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x3000 0x100>;
- st,bank-name = "PIO8";
- };
- pio9: gpio@fee04000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x4000 0x100>;
- st,bank-name = "PIO9";
- };
- pio10: gpio@fee05000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x5000 0x100>;
- st,bank-name = "PIO10";
- };
- pio11: gpio@fee06000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x6000 0x100>;
- st,bank-name = "PIO11";
- };
- pio12: gpio@fee07000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x7000 0x100>;
- st,bank-name = "PIO12";
- };
- pio30: gpio@fee08000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x8000 0x100>;
- st,bank-name = "PIO30";
- };
- pio31: gpio@fee09000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x9000 0x100>;
- st,bank-name = "PIO31";
- };
-
- pwm0 {
- pinctrl_pwm0_chan0_default: pwm0-0-default {
- st,pins {
- pwm-out = <&pio9 7 ALT2 OUT>;
- pwm-capturein = <&pio9 6 ALT2 IN>;
- };
- };
- };
-
- serial2-oe {
- pinctrl_serial2_oe: serial2-1 {
- st,pins {
- output-enable = <&pio11 3 ALT2 OUT>;
- };
- };
- };
-
- i2c0 {
- pinctrl_i2c0_default: i2c0-default {
- st,pins {
- sda = <&pio9 3 ALT1 BIDIR>;
- scl = <&pio9 2 ALT1 BIDIR>;
- };
- };
- };
-
- usb {
- pinctrl_usb0: usb0 {
- st,pins {
- oc-detect = <&pio9 4 ALT1 IN>;
- pwr-enable = <&pio9 5 ALT1 OUT>;
- };
- };
- };
-
-
- i2c1 {
- pinctrl_i2c1_default: i2c1-default {
- st,pins {
- sda = <&pio12 1 ALT1 BIDIR>;
- scl = <&pio12 0 ALT1 BIDIR>;
- };
- };
- };
-
- fsm {
- pinctrl_fsm: fsm {
- st,pins {
- spi-fsm-clk = <&pio12 2 ALT1 OUT>;
- spi-fsm-cs = <&pio12 3 ALT1 OUT>;
- spi-fsm-mosi = <&pio12 4 ALT1 OUT>;
- spi-fsm-miso = <&pio12 5 ALT1 IN>;
- spi-fsm-hol = <&pio12 6 ALT1 OUT>;
- spi-fsm-wp = <&pio12 7 ALT1 OUT>;
- };
- };
- };
- };
-
- pin-controller-rear {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stih416-rear-pinctrl";
- st,syscfg = <&syscfg_rear>;
- reg = <0xfe82f080 0x4>;
- reg-names = "irqmux";
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irqmux";
- ranges = <0 0xfe820000 0x6000>;
-
- pio13: gpio@fe820000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0 0x100>;
- st,bank-name = "PIO13";
- };
- pio14: gpio@fe821000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1000 0x100>;
- st,bank-name = "PIO14";
- };
- pio15: gpio@fe822000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2000 0x100>;
- st,bank-name = "PIO15";
- };
- pio16: gpio@fe823000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x3000 0x100>;
- st,bank-name = "PIO16";
- };
- pio17: gpio@fe824000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x4000 0x100>;
- st,bank-name = "PIO17";
- };
- pio18: gpio@fe825000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x5000 0x100>;
- st,bank-name = "PIO18";
- st,retime-pin-mask = <0xf>;
- };
-
- serial2 {
- pinctrl_serial2: serial2-0 {
- st,pins {
- tx = <&pio17 4 ALT2 OUT>;
- rx = <&pio17 5 ALT2 IN>;
- };
- };
- };
-
- gmac0 {
- pinctrl_mii0: mii0 {
- st,pins {
- mdint = <&pio13 6 ALT2 IN BYPASS 0>;
- txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
- txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
- txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
- txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
- txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
-
- txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>;
- txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
- crs = <&pio15 2 ALT2 IN BYPASS 1000>;
- col = <&pio15 3 ALT2 IN BYPASS 1000>;
- mdio= <&pio15 4 ALT2 OUT BYPASS 1500>;
- mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>;
-
- rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
- rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
- rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
- rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
- rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
- rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
- rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>;
- phyclk = <&pio13 5 ALT2 OUT NICLK 0 CLK_B>;
- };
- };
-
- pinctrl_gmii0: gmii0 {
- st,pins {
- };
- };
- pinctrl_rgmii0: rgmii0 {
- st,pins {
- phyclk = <&pio13 5 ALT4 OUT NICLK 0 CLK_B>;
- txen = <&pio13 7 ALT2 OUT DE_IO 0 CLK_A>;
- txd0 = <&pio14 0 ALT2 OUT DE_IO 500 CLK_A>;
- txd1 = <&pio14 1 ALT2 OUT DE_IO 500 CLK_A>;
- txd2 = <&pio14 2 ALT2 OUT DE_IO 500 CLK_B>;
- txd3 = <&pio14 3 ALT2 OUT DE_IO 500 CLK_B>;
- txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>;
-
- mdio = <&pio15 4 ALT2 OUT BYPASS 0>;
- mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>;
-
- rxdv = <&pio15 6 ALT2 IN DE_IO 500 CLK_A>;
- rxd0 =<&pio16 0 ALT2 IN DE_IO 500 CLK_A>;
- rxd1 =<&pio16 1 ALT2 IN DE_IO 500 CLK_A>;
- rxd2 =<&pio16 2 ALT2 IN DE_IO 500 CLK_A>;
- rxd3 =<&pio16 3 ALT2 IN DE_IO 500 CLK_A>;
- rxclk =<&pio17 0 ALT2 IN NICLK 0 CLK_A>;
-
- clk125=<&pio17 6 ALT1 IN NICLK 0 CLK_A>;
- };
- };
- };
-
- mmc0 {
- pinctrl_mmc0: mmc0 {
- st,pins {
- mmcclk = <&pio13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>;
- data0 = <&pio14 4 ALT4 BIDIR_PU BYPASS 0>;
- data1 = <&pio14 5 ALT4 BIDIR_PU BYPASS 0>;
- data2 = <&pio14 6 ALT4 BIDIR_PU BYPASS 0>;
- data3 = <&pio14 7 ALT4 BIDIR_PU BYPASS 0>;
- cmd = <&pio15 1 ALT4 BIDIR_PU BYPASS 0>;
- wp = <&pio15 3 ALT4 IN>;
- data4 = <&pio16 4 ALT4 BIDIR_PU BYPASS 0>;
- data5 = <&pio16 5 ALT4 BIDIR_PU BYPASS 0>;
- data6 = <&pio16 6 ALT4 BIDIR_PU BYPASS 0>;
- data7 = <&pio16 7 ALT4 BIDIR_PU BYPASS 0>;
- pwr = <&pio17 1 ALT4 OUT>;
- cd = <&pio17 2 ALT4 IN>;
- led = <&pio17 3 ALT4 OUT>;
- };
- };
- };
- mmc1 {
- pinctrl_mmc1: mmc1 {
- st,pins {
- mmcclk = <&pio15 0 ALT3 BIDIR_PU NICLK 0 CLK_B>;
- data0 = <&pio13 7 ALT3 BIDIR_PU BYPASS 0>;
- data1 = <&pio14 1 ALT3 BIDIR_PU BYPASS 0>;
- data2 = <&pio14 2 ALT3 BIDIR_PU BYPASS 0>;
- data3 = <&pio14 3 ALT3 BIDIR_PU BYPASS 0>;
- cmd = <&pio15 4 ALT3 BIDIR_PU BYPASS 0>;
- data4 = <&pio15 6 ALT3 BIDIR_PU BYPASS 0>;
- data5 = <&pio15 7 ALT3 BIDIR_PU BYPASS 0>;
- data6 = <&pio16 0 ALT3 BIDIR_PU BYPASS 0>;
- data7 = <&pio16 1 ALT3 BIDIR_PU BYPASS 0>;
- pwr = <&pio16 2 ALT3 OUT>;
- nreset = <&pio13 6 ALT3 OUT>;
- };
- };
- };
-
- usb {
- pinctrl_usb1: usb1 {
- st,pins {
- oc-detect = <&pio18 0 ALT1 IN>;
- pwr-enable = <&pio18 1 ALT1 OUT>;
- };
- };
- pinctrl_usb2: usb2 {
- st,pins {
- oc-detect = <&pio18 2 ALT1 IN>;
- pwr-enable = <&pio18 3 ALT1 OUT>;
- };
- };
- };
-
- pwm0 {
- pinctrl_pwm0_chan1_default: pwm0-1-default {
- st,pins {
- pwm-out = <&pio13 2 ALT2 OUT>;
- pwm-capturein = <&pio13 1 ALT2 IN>;
- };
- };
- pinctrl_pwm0_chan2_default: pwm0-2-default {
- st,pins {
- pwm-out = <&pio15 2 ALT4 OUT>;
- };
- };
- pinctrl_pwm0_chan3_default: pwm0-3-default {
- st,pins {
- pwm-out = <&pio17 4 ALT1 OUT>;
- };
- };
- };
-
- };
-
- pin-controller-fvdp-fe {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stih416-fvdp-fe-pinctrl";
- st,syscfg = <&syscfg_fvdp_fe>;
- reg = <0xfd6bf080 0x4>;
- reg-names = "irqmux";
- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irqmux";
- ranges = <0 0xfd6b0000 0x3000>;
-
- pio100: gpio@fd6b0000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0 0x100>;
- st,bank-name = "PIO100";
- };
- pio101: gpio@fd6b1000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1000 0x100>;
- st,bank-name = "PIO101";
- };
- pio102: gpio@fd6b2000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2000 0x100>;
- st,bank-name = "PIO102";
- };
- };
-
- pin-controller-fvdp-lite {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stih416-fvdp-lite-pinctrl";
- st,syscfg = <&syscfg_fvdp_lite>;
- reg = <0xfd33f080 0x4>;
- reg-names = "irqmux";
- interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irqmux";
- ranges = <0 0xfd330000 0x5000>;
-
- pio103: gpio@fd330000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0 0x100>;
- st,bank-name = "PIO103";
- };
- pio104: gpio@fd331000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1000 0x100>;
- st,bank-name = "PIO104";
- };
- pio105: gpio@fd332000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2000 0x100>;
- st,bank-name = "PIO105";
- };
- pio106: gpio@fd333000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x3000 0x100>;
- st,bank-name = "PIO106";
- };
-
- pio107: gpio@fd334000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x4000 0x100>;
- st,bank-name = "PIO107";
- st,retime-pin-mask = <0xf>;
- };
- };
- };
-};
--
cgit
From 1a770b724d2d9f54a1a8c7aed7b4db1596dff677 Mon Sep 17 00:00:00 2001
From: Patrice Chotard <patrice.chotard@st.com>
Date: Thu, 20 Oct 2016 15:20:50 +0200
Subject: ARM: dts: remove STiH415-b2020.dts
Since v4.8, STiH415/416 clock support has
been removed [1], these platform doesn't boot.
We can remove DTS files related to these socs.
[1] https://patchwork.kernel.org/patch/9157571/
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/Makefile | 1 -
arch/arm/boot/dts/stih415-b2020.dts | 15 ---------------
2 files changed, 16 deletions(-)
delete mode 100644 arch/arm/boot/dts/stih415-b2020.dts
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d81154228fd3..594275c7d163 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -713,7 +713,6 @@ dtb-$(CONFIG_ARCH_STI) += \
stih410-b2120.dtb \
stih410-b2260.dtb \
stih415-b2000.dtb \
- stih415-b2020.dtb \
stih418-b2199.dtb
dtb-$(CONFIG_ARCH_STM32)+= \
stm32f429-disco.dtb \
diff --git a/arch/arm/boot/dts/stih415-b2020.dts b/arch/arm/boot/dts/stih415-b2020.dts
deleted file mode 100644
index 71903a87bd31..000000000000
--- a/arch/arm/boot/dts/stih415-b2020.dts
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
- * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * publishhed by the Free Software Foundation.
- */
-/dts-v1/;
-#include "stih415.dtsi"
-#include "stih41x-b2020.dtsi"
-/ {
- model = "STiH415 B2020 Board";
- compatible = "st,stih415-b2020", "st,stih415";
-};
--
cgit
From ce1dfb3817523dbbfad30c815eae024b50c00890 Mon Sep 17 00:00:00 2001
From: Patrice Chotard <patrice.chotard@st.com>
Date: Thu, 20 Oct 2016 15:21:07 +0200
Subject: ARM: dts: remove STiH415-b2000.dts
Since v4.8, STiH415/416 clock support has
been removed [1], these platform doesn't boot.
We can remove DTS files related to these socs.
[1] https://patchwork.kernel.org/patch/9157571/
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/Makefile | 1 -
arch/arm/boot/dts/stih415-b2000.dts | 15 ---------------
2 files changed, 16 deletions(-)
delete mode 100644 arch/arm/boot/dts/stih415-b2000.dts
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 594275c7d163..376db94a695f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -712,7 +712,6 @@ dtb-$(CONFIG_ARCH_STI) += \
stih407-b2120.dtb \
stih410-b2120.dtb \
stih410-b2260.dtb \
- stih415-b2000.dtb \
stih418-b2199.dtb
dtb-$(CONFIG_ARCH_STM32)+= \
stm32f429-disco.dtb \
diff --git a/arch/arm/boot/dts/stih415-b2000.dts b/arch/arm/boot/dts/stih415-b2000.dts
deleted file mode 100644
index bdfbd3765db2..000000000000
--- a/arch/arm/boot/dts/stih415-b2000.dts
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
- * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * publishhed by the Free Software Foundation.
- */
-/dts-v1/;
-#include "stih415.dtsi"
-#include "stih41x-b2000.dtsi"
-/ {
- model = "STiH415 B2000 Board";
- compatible = "st,stih415-b2000", "st,stih415";
-};
--
cgit
From e92e2f324b8f044b32454e66aa09f09688508fd8 Mon Sep 17 00:00:00 2001
From: Patrice Chotard <patrice.chotard@st.com>
Date: Thu, 20 Oct 2016 15:21:30 +0200
Subject: ARM: dts: remove STiH415-clock.dtsi
Since v4.8, STiH415/416 clock support has
been removed [1], these platform doesn't boot.
We can remove DTS files related to these socs.
[1] https://patchwork.kernel.org/patch/9157571/
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stih415-clock.dtsi | 533 -----------------------------------
1 file changed, 533 deletions(-)
delete mode 100644 arch/arm/boot/dts/stih415-clock.dtsi
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/stih415-clock.dtsi b/arch/arm/boot/dts/stih415-clock.dtsi
deleted file mode 100644
index 3ee34514bc4b..000000000000
--- a/arch/arm/boot/dts/stih415-clock.dtsi
+++ /dev/null
@@ -1,533 +0,0 @@
-/*
- * Copyright (C) 2013 STMicroelectronics (R&D) Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <dt-bindings/clock/stih415-clks.h>
-
-/ {
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- /*
- * Fixed 30MHz oscillator input to SoC
- */
- clk_sysin: clk-sysin {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <30000000>;
- };
-
- /*
- * ClockGenAs on SASG1
- */
- clockgen-a@fee62000 {
- reg = <0xfee62000 0xb48>;
-
- clk_s_a0_pll: clk-s-a0-pll {
- #clock-cells = <1>;
- compatible = "st,clkgena-plls-c65";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-a0-pll0-hs",
- "clk-s-a0-pll0-ls",
- "clk-s-a0-pll1";
- };
-
- clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
- #clock-cells = <0>;
- compatible = "st,clkgena-prediv-c65",
- "st,clkgena-prediv";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-a0-osc-prediv";
- };
-
- clk_s_a0_hs: clk-s-a0-hs {
- #clock-cells = <1>;
- compatible = "st,clkgena-divmux-c65-hs",
- "st,clkgena-divmux";
-
- clocks = <&clk_s_a0_osc_prediv>,
- <&clk_s_a0_pll 0>, /* PLL0 HS */
- <&clk_s_a0_pll 2>; /* PLL1 */
-
- clock-output-names = "clk-s-fdma-0",
- "clk-s-fdma-1",
- ""; /* clk-s-jit-sense */
- /* Fourth output unused */
- };
-
- clk_s_a0_ls: clk-s-a0-ls {
- #clock-cells = <1>;
- compatible = "st,clkgena-divmux-c65-ls",
- "st,clkgena-divmux";
-
- clocks = <&clk_s_a0_osc_prediv>,
- <&clk_s_a0_pll 1>, /* PLL0 LS */
- <&clk_s_a0_pll 2>; /* PLL1 */
-
- clock-output-names = "clk-s-icn-reg-0",
- "clk-s-icn-if-0",
- "clk-s-icn-reg-lp-0",
- "clk-s-emiss",
- "clk-s-eth1-phy",
- "clk-s-mii-ref-out";
- /* Remaining outputs unused */
- };
- };
-
- clockgen-a@fee81000 {
- reg = <0xfee81000 0xb48>;
-
- clk_s_a1_pll: clk-s-a1-pll {
- #clock-cells = <1>;
- compatible = "st,clkgena-plls-c65";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-a1-pll0-hs",
- "clk-s-a1-pll0-ls",
- "clk-s-a1-pll1";
- };
-
- clk_s_a1_osc_prediv: clk-s-a1-osc-prediv {
- #clock-cells = <0>;
- compatible = "st,clkgena-prediv-c65",
- "st,clkgena-prediv";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-a1-osc-prediv";
- };
-
- clk_s_a1_hs: clk-s-a1-hs {
- #clock-cells = <1>;
- compatible = "st,clkgena-divmux-c65-hs",
- "st,clkgena-divmux";
-
- clocks = <&clk_s_a1_osc_prediv>,
- <&clk_s_a1_pll 0>, /* PLL0 HS */
- <&clk_s_a1_pll 2>; /* PLL1 */
-
- clock-output-names = "", /* Reserved */
- "", /* Reserved */
- "clk-s-stac-phy",
- "clk-s-vtac-tx-phy";
- };
-
- clk_s_a1_ls: clk-s-a1-ls {
- #clock-cells = <1>;
- compatible = "st,clkgena-divmux-c65-ls",
- "st,clkgena-divmux";
-
- clocks = <&clk_s_a1_osc_prediv>,
- <&clk_s_a1_pll 1>, /* PLL0 LS */
- <&clk_s_a1_pll 2>; /* PLL1 */
-
- clock-output-names = "clk-s-icn-if-2",
- "clk-s-card-mmc",
- "clk-s-icn-if-1",
- "clk-s-gmac0-phy",
- "clk-s-nand-ctrl",
- "", /* Reserved */
- "clk-s-mii0-ref-out",
- ""; /* clk-s-stac-sys */
- /* Remaining outputs unused */
- };
- };
-
- /*
- * ClockGenAs on MPE41
- */
- clockgen-a@fde12000 {
- reg = <0xfde12000 0xb50>;
-
- clk_m_a0_pll0: clk-m-a0-pll0 {
- #clock-cells = <1>;
- compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-m-a0-pll0-phi0",
- "clk-m-a0-pll0-phi1",
- "clk-m-a0-pll0-phi2",
- "clk-m-a0-pll0-phi3";
- };
-
- clk_m_a0_pll1: clk-m-a0-pll1 {
- #clock-cells = <1>;
- compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-m-a0-pll1-phi0",
- "clk-m-a0-pll1-phi1",
- "clk-m-a0-pll1-phi2",
- "clk-m-a0-pll1-phi3";
- };
-
- clk_m_a0_osc_prediv: clk-m-a0-osc-prediv {
- #clock-cells = <0>;
- compatible = "st,clkgena-prediv-c32",
- "st,clkgena-prediv";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-m-a0-osc-prediv";
- };
-
- clk_m_a0_div0: clk-m-a0-div0 {
- #clock-cells = <1>;
- compatible = "st,clkgena-divmux-c32-odf0",
- "st,clkgena-divmux";
-
- clocks = <&clk_m_a0_osc_prediv>,
- <&clk_m_a0_pll0 0>, /* PLL0 PHI0 */
- <&clk_m_a0_pll1 0>; /* PLL1 PHI0 */
-
- clock-output-names = "clk-m-apb-pm", /* Unused */
- "", /* Unused */
- "", /* Unused */
- "", /* Unused */
- "clk-m-pp-dmu-0",
- "clk-m-pp-dmu-1",
- "clk-m-icm-disp",
- ""; /* Unused */
- };
-
- clk_m_a0_div1: clk-m-a0-div1 {
- #clock-cells = <1>;
- compatible = "st,clkgena-divmux-c32-odf1",
- "st,clkgena-divmux";
-
- clocks = <&clk_m_a0_osc_prediv>,
- <&clk_m_a0_pll0 1>, /* PLL0 PHI1 */
- <&clk_m_a0_pll1 1>; /* PLL1 PHI1 */
-
- clock-output-names = "", /* Unused */
- "", /* Unused */
- "clk-m-a9-ext2f",
- "clk-m-st40rt",
- "clk-m-st231-dmu-0",
- "clk-m-st231-dmu-1",
- "clk-m-st231-aud",
- "clk-m-st231-gp-0";
- };
-
- clk_m_a0_div2: clk-m-a0-div2 {
- #clock-cells = <1>;
- compatible = "st,clkgena-divmux-c32-odf2",
- "st,clkgena-divmux";
-
- clocks = <&clk_m_a0_osc_prediv>,
- <&clk_m_a0_pll0 2>, /* PLL0 PHI2 */
- <&clk_m_a0_pll1 2>; /* PLL1 PHI2 */
-
- clock-output-names = "clk-m-st231-gp-1",
- "clk-m-icn-cpu",
- "clk-m-icn-stac",
- "clk-m-icn-dmu-0",
- "clk-m-icn-dmu-1",
- "", /* Unused */
- "", /* Unused */
- ""; /* Unused */
- };
-
- clk_m_a0_div3: clk-m-a0-div3 {
- #clock-cells = <1>;
- compatible = "st,clkgena-divmux-c32-odf3",
- "st,clkgena-divmux";
-
- clocks = <&clk_m_a0_osc_prediv>,
- <&clk_m_a0_pll0 3>, /* PLL0 PHI3 */
- <&clk_m_a0_pll1 3>; /* PLL1 PHI3 */
-
- clock-output-names = "", /* Unused */
- "", /* Unused */
- "", /* Unused */
- "", /* Unused */
- "", /* Unused */
- "", /* Unused */
- "clk-m-icn-eram",
- "clk-m-a9-trace";
- };
- };
-
- clockgen-a@fd6db000 {
- reg = <0xfd6db000 0xb50>;
-
- clk_m_a1_pll0: clk-m-a1-pll0 {
- #clock-cells = <1>;
- compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-m-a1-pll0-phi0",
- "clk-m-a1-pll0-phi1",
- "clk-m-a1-pll0-phi2",
- "clk-m-a1-pll0-phi3";
- };
-
- clk_m_a1_pll1: clk-m-a1-pll1 {
- #clock-cells = <1>;
- compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-m-a1-pll1-phi0",
- "clk-m-a1-pll1-phi1",
- "clk-m-a1-pll1-phi2",
- "clk-m-a1-pll1-phi3";
- };
-
- clk_m_a1_osc_prediv: clk-m-a1-osc-prediv {
- #clock-cells = <0>;
- compatible = "st,clkgena-prediv-c32",
- "st,clkgena-prediv";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-m-a1-osc-prediv";
- };
-
- clk_m_a1_div0: clk-m-a1-div0 {
- #clock-cells = <1>;
- compatible = "st,clkgena-divmux-c32-odf0",
- "st,clkgena-divmux";
-
- clocks = <&clk_m_a1_osc_prediv>,
- <&clk_m_a1_pll0 0>, /* PLL0 PHI0 */
- <&clk_m_a1_pll1 0>; /* PLL1 PHI0 */
-
- clock-output-names = "clk-m-fdma-12",
- "clk-m-fdma-10",
- "clk-m-fdma-11",
- "clk-m-hva-lmi",
- "clk-m-proc-sc",
- "clk-m-tp",
- "clk-m-icn-gpu",
- "clk-m-icn-vdp-0";
- };
-
- clk_m_a1_div1: clk-m-a1-div1 {
- #clock-cells = <1>;
- compatible = "st,clkgena-divmux-c32-odf1",
- "st,clkgena-divmux";
-
- clocks = <&clk_m_a1_osc_prediv>,
- <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */
- <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */
-
- clock-output-names = "clk-m-icn-vdp-1",
- "clk-m-icn-vdp-2",
- "clk-m-icn-vdp-3",
- "clk-m-prv-t1-bus",
- "clk-m-icn-vdp-4",
- "clk-m-icn-reg-10",
- "", /* Unused */
- ""; /* clk-m-icn-st231 */
- };
-
- clk_m_a1_div2: clk-m-a1-div2 {
- #clock-cells = <1>;
- compatible = "st,clkgena-divmux-c32-odf2",
- "st,clkgena-divmux";
-
- clocks = <&clk_m_a1_osc_prediv>,
- <&clk_m_a1_pll0 2>, /* PLL0 PHI2 */
- <&clk_m_a1_pll1 2>; /* PLL1 PHI2 */
-
- clock-output-names = "clk-m-fvdp-proc-alt",
- "", /* Unused */
- "", /* Unused */
- "", /* Unused */
- "", /* Unused */
- "", /* Unused */
- "", /* Unused */
- ""; /* Unused */
- };
-
- clk_m_a1_div3: clk-m-a1-div3 {
- #clock-cells = <1>;
- compatible = "st,clkgena-divmux-c32-odf3",
- "st,clkgena-divmux";
-
- clocks = <&clk_m_a1_osc_prediv>,
- <&clk_m_a1_pll0 3>, /* PLL0 PHI3 */
- <&clk_m_a1_pll1 3>; /* PLL1 PHI3 */
-
- clock-output-names = "", /* Unused */
- "", /* Unused */
- "", /* Unused */
- "", /* Unused */
- "", /* Unused */
- "", /* Unused */
- "", /* Unused */
- ""; /* Unused */
- };
- };
-
- clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2 {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&clk_m_a0_div1 2>;
- clock-div = <2>;
- clock-mult = <1>;
- };
-
- clockgen-a@fd345000 {
- reg = <0xfd345000 0xb50>;
-
- clk_m_a2_pll0: clk-m-a2-pll0 {
- #clock-cells = <1>;
- compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-m-a2-pll0-phi0",
- "clk-m-a2-pll0-phi1",
- "clk-m-a2-pll0-phi2",
- "clk-m-a2-pll0-phi3";
- };
-
- clk_m_a2_pll1: clk-m-a2-pll1 {
- #clock-cells = <1>;
- compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-m-a2-pll1-phi0",
- "clk-m-a2-pll1-phi1",
- "clk-m-a2-pll1-phi2",
- "clk-m-a2-pll1-phi3";
- };
-
- clk_m_a2_osc_prediv: clk-m-a2-osc-prediv {
- #clock-cells = <0>;
- compatible = "st,clkgena-prediv-c32",
- "st,clkgena-prediv";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-m-a2-osc-prediv";
- };
-
- clk_m_a2_div0: clk-m-a2-div0 {
- #clock-cells = <1>;
- compatible = "st,clkgena-divmux-c32-odf0",
- "st,clkgena-divmux";
-
- clocks = <&clk_m_a2_osc_prediv>,
- <&clk_m_a2_pll0 0>, /* PLL0 PHI0 */
- <&clk_m_a2_pll1 0>; /* PLL1 PHI0 */
-
- clock-output-names = "clk-m-vtac-main-phy",
- "clk-m-vtac-aux-phy",
- "clk-m-stac-phy",
- "clk-m-stac-sys",
- "", /* clk-m-mpestac-pg */
- "", /* clk-m-mpestac-wc */
- "", /* clk-m-mpevtacaux-pg*/
- ""; /* clk-m-mpevtacmain-pg*/
- };
-
- clk_m_a2_div1: clk-m-a2-div1 {
- #clock-cells = <1>;
- compatible = "st,clkgena-divmux-c32-odf1",
- "st,clkgena-divmux";
-
- clocks = <&clk_m_a2_osc_prediv>,
- <&clk_m_a2_pll0 1>, /* PLL0 PHI1 */
- <&clk_m_a2_pll1 1>; /* PLL1 PHI1 */
-
- clock-output-names = "", /* clk-m-mpevtacrx0-wc */
- "", /* clk-m-mpevtacrx1-wc */
- "clk-m-compo-main",
- "clk-m-compo-aux",
- "clk-m-bdisp-0",
- "clk-m-bdisp-1",
- "clk-m-icn-bdisp-0",
- "clk-m-icn-bdisp-1";
- };
-
- clk_m_a2_div2: clk-m-a2-div2 {
- #clock-cells = <1>;
- compatible = "st,clkgena-divmux-c32-odf2",
- "st,clkgena-divmux";
-
- clocks = <&clk_m_a2_osc_prediv>,
- <&clk_m_a2_pll0 2>, /* PLL0 PHI2 */
- <&clk_m_a2_pll1 2>; /* PLL1 PHI2 */
-
- clock-output-names = "", /* clk-m-icn-hqvdp0 */
- "", /* clk-m-icn-hqvdp1 */
- "clk-m-icn-compo",
- "", /* clk-m-icn-vdpaux */
- "clk-m-icn-ts",
- "clk-m-icn-reg-lp-10",
- "clk-m-dcephy-impctrl",
- ""; /* Unused */
- };
-
- clk_m_a2_div3: clk-m-a2-div3 {
- #clock-cells = <1>;
- compatible = "st,clkgena-divmux-c32-odf3",
- "st,clkgena-divmux";
-
- clocks = <&clk_m_a2_osc_prediv>,
- <&clk_m_a2_pll0 3>, /* PLL0 PHI3 */
- <&clk_m_a2_pll1 3>; /* PLL1 PHI3 */
-
- clock-output-names = ""; /* Unused */
- /* Remaining outputs unused */
- };
- };
-
- /*
- * A9 PLL
- */
- clockgen-a9@fdde00d8 {
- reg = <0xfdde00d8 0x70>;
-
- clockgen_a9_pll: clockgen-a9-pll {
- #clock-cells = <1>;
- compatible = "st,stih415-plls-c32-a9", "st,clkgen-plls-c32";
-
- clocks = <&clk_sysin>;
- clock-output-names = "clockgen-a9-pll-odf";
- };
- };
-
- /*
- * ARM CPU related clocks
- */
- clk_m_a9: clk-m-a9@fdde00d8 {
- #clock-cells = <0>;
- compatible = "st,stih415-clkgen-a9-mux", "st,clkgen-mux";
- reg = <0xfdde00d8 0x4>;
- clocks = <&clockgen_a9_pll 0>,
- <&clockgen_a9_pll 0>,
- <&clk_m_a0_div1 2>,
- <&clk_m_a9_ext2f_div2>;
- };
-
- /*
- * ARM Peripheral clock for timers
- */
- arm_periph_clk: clk-m-a9-periphs {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&clk_m_a9>;
- clock-div = <2>;
- clock-mult = <1>;
- };
- };
-};
--
cgit
From ebdce1119e8a1930427732bce049276973dec7b5 Mon Sep 17 00:00:00 2001
From: Patrice Chotard <patrice.chotard@st.com>
Date: Thu, 20 Oct 2016 15:21:45 +0200
Subject: ARM: dts: remove STiH415-pinctrl.dtsi
Since v4.8, STiH415/416 clock support has
been removed [1], these platform doesn't boot.
We can remove DTS files related to these socs.
[1] https://patchwork.kernel.org/patch/9157571/
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stih415-pinctrl.dtsi | 545 ---------------------------------
1 file changed, 545 deletions(-)
delete mode 100644 arch/arm/boot/dts/stih415-pinctrl.dtsi
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi
deleted file mode 100644
index bd028ce98b61..000000000000
--- a/arch/arm/boot/dts/stih415-pinctrl.dtsi
+++ /dev/null
@@ -1,545 +0,0 @@
-/*
- * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
- * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * publishhed by the Free Software Foundation.
- */
-#include "st-pincfg.h"
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-/ {
-
- aliases {
- gpio0 = &pio0;
- gpio1 = &pio1;
- gpio2 = &pio2;
- gpio3 = &pio3;
- gpio4 = &pio4;
- gpio5 = &pio5;
- gpio6 = &pio6;
- gpio7 = &pio7;
- gpio8 = &pio8;
- gpio9 = &pio9;
- gpio10 = &pio10;
- gpio11 = &pio11;
- gpio12 = &pio12;
- gpio13 = &pio13;
- gpio14 = &pio14;
- gpio15 = &pio15;
- gpio16 = &pio16;
- gpio17 = &pio17;
- gpio18 = &pio18;
- gpio19 = &pio100;
- gpio20 = &pio101;
- gpio21 = &pio102;
- gpio22 = &pio103;
- gpio23 = &pio104;
- gpio24 = &pio105;
- gpio25 = &pio106;
- gpio26 = &pio107;
- };
-
- soc {
- pin-controller-sbc {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stih415-sbc-pinctrl";
- st,syscfg = <&syscfg_sbc>;
- reg = <0xfe61f080 0x4>;
- reg-names = "irqmux";
- interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irqmux";
- ranges = <0 0xfe610000 0x5000>;
-
- pio0: gpio@fe610000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0 0x100>;
- st,bank-name = "PIO0";
- };
- pio1: gpio@fe611000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1000 0x100>;
- st,bank-name = "PIO1";
- };
- pio2: gpio@fe612000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2000 0x100>;
- st,bank-name = "PIO2";
- };
- pio3: gpio@fe613000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x3000 0x100>;
- st,bank-name = "PIO3";
- };
- pio4: gpio@fe614000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x4000 0x100>;
- st,bank-name = "PIO4";
- };
-
- sbc_serial1 {
- pinctrl_sbc_serial1:sbc_serial1 {
- st,pins {
- tx = <&pio2 6 ALT3 OUT>;
- rx = <&pio2 7 ALT3 IN>;
- };
- };
- };
-
- keyscan {
- pinctrl_keyscan: keyscan {
- st,pins {
- keyin0 = <&pio0 2 ALT2 IN>;
- keyin1 = <&pio0 3 ALT2 IN>;
- keyin2 = <&pio0 4 ALT2 IN>;
- keyin3 = <&pio2 6 ALT2 IN>;
-
- keyout0 = <&pio1 6 ALT2 OUT>;
- keyout1 = <&pio1 7 ALT2 OUT>;
- keyout2 = <&pio0 6 ALT2 OUT>;
- keyout3 = <&pio2 7 ALT2 OUT>;
- };
- };
- };
-
- sbc_i2c0 {
- pinctrl_sbc_i2c0_default: sbc_i2c0-default {
- st,pins {
- sda = <&pio4 6 ALT1 BIDIR>;
- scl = <&pio4 5 ALT1 BIDIR>;
- };
- };
- };
-
- sbc_i2c1 {
- pinctrl_sbc_i2c1_default: sbc_i2c1-default {
- st,pins {
- sda = <&pio3 2 ALT2 BIDIR>;
- scl = <&pio3 1 ALT2 BIDIR>;
- };
- };
- };
-
- rc{
- pinctrl_ir: ir0 {
- st,pins {
- ir = <&pio4 0 ALT2 IN>;
- };
- };
- };
-
- gmac1 {
- pinctrl_mii1: mii1 {
- st,pins {
- txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
- txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
- txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
- txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
- txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
- txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
- txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
- col = <&pio0 7 ALT1 IN BYPASS 1000>;
- mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
- mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
- crs = <&pio1 2 ALT1 IN BYPASS 1000>;
- mdint = <&pio1 3 ALT1 IN BYPASS 0>;
- rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
- phyclk = <&pio2 3 ALT1 IN NICLK 1000 CLK_A>;
- };
- };
-
- pinctrl_rgmii1: rgmii1-0 {
- st,pins {
- txd0 = <&pio0 0 ALT1 OUT DE_IO 1000 CLK_A>;
- txd1 = <&pio0 1 ALT1 OUT DE_IO 1000 CLK_A>;
- txd2 = <&pio0 2 ALT1 OUT DE_IO 1000 CLK_A>;
- txd3 = <&pio0 3 ALT1 OUT DE_IO 1000 CLK_A>;
- txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>;
- txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
- mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
- mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
- rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>;
- rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>;
- rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>;
- rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>;
-
- rxdv = <&pio2 0 ALT1 IN DE_IO 500 CLK_A>;
- rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
- phyclk = <&pio2 3 ALT4 OUT NICLK 0 CLK_B>;
-
- clk125= <&pio3 7 ALT4 IN NICLK 0 CLK_A>;
- };
- };
- };
- };
-
- pin-controller-front {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stih415-front-pinctrl";
- st,syscfg = <&syscfg_front>;
- reg = <0xfee0f080 0x4>;
- reg-names = "irqmux";
- interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irqmux";
- ranges = <0 0xfee00000 0x8000>;
-
- pio5: gpio@fee00000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0 0x100>;
- st,bank-name = "PIO5";
- };
- pio6: gpio@fee01000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1000 0x100>;
- st,bank-name = "PIO6";
- };
- pio7: gpio@fee02000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2000 0x100>;
- st,bank-name = "PIO7";
- };
- pio8: gpio@fee03000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x3000 0x100>;
- st,bank-name = "PIO8";
- };
- pio9: gpio@fee04000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x4000 0x100>;
- st,bank-name = "PIO9";
- };
- pio10: gpio@fee05000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x5000 0x100>;
- st,bank-name = "PIO10";
- };
- pio11: gpio@fee06000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x6000 0x100>;
- st,bank-name = "PIO11";
- };
- pio12: gpio@fee07000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x7000 0x100>;
- st,bank-name = "PIO12";
- };
-
- i2c0 {
- pinctrl_i2c0_default: i2c0-default {
- st,pins {
- sda = <&pio9 3 ALT1 BIDIR>;
- scl = <&pio9 2 ALT1 BIDIR>;
- };
- };
- };
-
- i2c1 {
- pinctrl_i2c1_default: i2c1-default {
- st,pins {
- sda = <&pio12 1 ALT1 BIDIR>;
- scl = <&pio12 0 ALT1 BIDIR>;
- };
- };
- };
- };
-
- pin-controller-rear {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stih415-rear-pinctrl";
- st,syscfg = <&syscfg_rear>;
- reg = <0xfe82f080 0x4>;
- reg-names = "irqmux";
- interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irqmux";
- ranges = <0 0xfe820000 0x8000>;
-
- pio13: gpio@fe820000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0 0x100>;
- st,bank-name = "PIO13";
- };
- pio14: gpio@fe821000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1000 0x100>;
- st,bank-name = "PIO14";
- };
- pio15: gpio@fe822000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2000 0x100>;
- st,bank-name = "PIO15";
- };
- pio16: gpio@fe823000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x3000 0x100>;
- st,bank-name = "PIO16";
- };
- pio17: gpio@fe824000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x4000 0x100>;
- st,bank-name = "PIO17";
- };
- pio18: gpio@fe825000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x5000 0x100>;
- st,bank-name = "PIO18";
- };
-
- serial2 {
- pinctrl_serial2: serial2-0 {
- st,pins {
- tx = <&pio17 4 ALT2 OUT>;
- rx = <&pio17 5 ALT2 IN>;
- };
- };
- };
-
- gmac0{
- pinctrl_mii0: mii0 {
- st,pins {
- mdint = <&pio13 6 ALT2 IN BYPASS 0>;
- txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
-
- txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
- txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
- txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
- txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
-
- txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>;
- txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
- crs = <&pio15 2 ALT2 IN BYPASS 1000>;
- col = <&pio15 3 ALT2 IN BYPASS 1000>;
- mdio = <&pio15 4 ALT2 OUT BYPASS 3000>;
- mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>;
-
- rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
- rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
- rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
- rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
- rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
- rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
- rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>;
- phyclk = <&pio13 5 ALT2 OUT NICLK 1000 CLK_A>;
-
- };
- };
-
- pinctrl_gmii0: gmii0 {
- st,pins {
- mdint = <&pio13 6 ALT2 IN BYPASS 0>;
- mdio = <&pio15 4 ALT2 OUT BYPASS 3000>;
- mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>;
- txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
-
- txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
- txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
- txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
- txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
- txd4 = <&pio14 4 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
- txd5 = <&pio14 5 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
- txd6 = <&pio14 6 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
- txd7 = <&pio14 7 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
-
- txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>;
- txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
- crs = <&pio15 2 ALT2 IN BYPASS 1000>;
- col = <&pio15 3 ALT2 IN BYPASS 1000>;
- rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
- rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
-
- rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
- rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
- rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
- rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
- rxd4 = <&pio16 4 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
- rxd5 = <&pio16 5 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
- rxd6 = <&pio16 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
- rxd7 = <&pio16 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
-
- rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>;
- clk125 = <&pio17 6 ALT1 IN NICLK 0 CLK_A>;
- phyclk = <&pio13 5 ALT4 OUT NICLK 0 CLK_B>;
-
-
- };
- };
- };
-
- mmc0 {
- pinctrl_mmc0: mmc0 {
- st,pins {
- mmcclk = <&pio13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>;
- data0 = <&pio14 4 ALT4 BIDIR_PU BYPASS 0>;
- data1 = <&pio14 5 ALT4 BIDIR_PU BYPASS 0>;
- data2 = <&pio14 6 ALT4 BIDIR_PU BYPASS 0>;
- data3 = <&pio14 7 ALT4 BIDIR_PU BYPASS 0>;
- cmd = <&pio15 1 ALT4 BIDIR_PU BYPASS 0>;
- wp = <&pio15 3 ALT4 IN>;
- data4 = <&pio16 4 ALT4 BIDIR_PU BYPASS 0>;
- data5 = <&pio16 5 ALT4 BIDIR_PU BYPASS 0>;
- data6 = <&pio16 6 ALT4 BIDIR_PU BYPASS 0>;
- data7 = <&pio16 7 ALT4 BIDIR_PU BYPASS 0>;
- pwr = <&pio17 1 ALT4 OUT>;
- cd = <&pio17 2 ALT4 IN>;
- led = <&pio17 3 ALT4 OUT>;
- };
- };
- };
- };
-
- pin-controller-left {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stih415-left-pinctrl";
- st,syscfg = <&syscfg_left>;
- reg = <0xfd6bf080 0x4>;
- reg-names = "irqmux";
- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irqmux";
- ranges = <0 0xfd6b0000 0x3000>;
-
- pio100: gpio@fd6b0000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0 0x100>;
- st,bank-name = "PIO100";
- };
- pio101: gpio@fd6b1000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1000 0x100>;
- st,bank-name = "PIO101";
- };
- pio102: gpio@fd6b2000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2000 0x100>;
- st,bank-name = "PIO102";
- };
- };
-
- pin-controller-right {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stih415-right-pinctrl";
- st,syscfg = <&syscfg_right>;
- reg = <0xfd33f080 0x4>;
- reg-names = "irqmux";
- interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irqmux";
- ranges = <0 0xfd330000 0x5000>;
-
- pio103: gpio@fd330000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0 0x100>;
- st,bank-name = "PIO103";
- };
- pio104: gpio@fd331000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1000 0x100>;
- st,bank-name = "PIO104";
- };
- pio105: gpio@fd332000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2000 0x100>;
- st,bank-name = "PIO105";
- };
- pio106: gpio@fd333000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x3000 0x100>;
- st,bank-name = "PIO106";
- };
- pio107: gpio@fd334000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x4000 0x100>;
- st,bank-name = "PIO107";
- };
- };
- };
-};
--
cgit
From 5e7f8d1619efd015184f2801a100e4e22f24b4a9 Mon Sep 17 00:00:00 2001
From: Patrice Chotard <patrice.chotard@st.com>
Date: Thu, 20 Oct 2016 15:22:36 +0200
Subject: ARM: dts: remove STiH415.dtsi
Since v4.8, STiH415/416 clock support has
been removed [1], these platform doesn't boot.
We can remove DTS files related to these socs.
[1] https://patchwork.kernel.org/patch/9157571/
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stih415.dtsi | 234 -----------------------------------------
1 file changed, 234 deletions(-)
delete mode 100644 arch/arm/boot/dts/stih415.dtsi
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
deleted file mode 100644
index 12427e651e5e..000000000000
--- a/arch/arm/boot/dts/stih415.dtsi
+++ /dev/null
@@ -1,234 +0,0 @@
-/*
- * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
- * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * publishhed by the Free Software Foundation.
- */
-#include "stih41x.dtsi"
-#include "stih415-clock.dtsi"
-#include "stih415-pinctrl.dtsi"
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/reset/stih415-resets.h>
-/ {
-
- L2: cache-controller {
- compatible = "arm,pl310-cache";
- reg = <0xfffe2000 0x1000>;
- arm,data-latency = <3 2 2>;
- arm,tag-latency = <1 1 1>;
- cache-unified;
- cache-level = <2>;
- };
-
- soc {
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&intc>;
- ranges;
- compatible = "simple-bus";
-
- powerdown: powerdown-controller {
- #reset-cells = <1>;
- compatible = "st,stih415-powerdown";
- };
-
- softreset: softreset-controller {
- #reset-cells = <1>;
- compatible = "st,stih415-softreset";
- };
-
- syscfg_sbc: sbc-syscfg@fe600000{
- compatible = "st,stih415-sbc-syscfg", "syscon";
- reg = <0xfe600000 0xb4>;
- };
-
- syscfg_front: front-syscfg@fee10000{
- compatible = "st,stih415-front-syscfg", "syscon";
- reg = <0xfee10000 0x194>;
- };
-
- syscfg_rear: rear-syscfg@fe830000{
- compatible = "st,stih415-rear-syscfg", "syscon";
- reg = <0xfe830000 0x190>;
- };
-
- /* MPE syscfgs */
- syscfg_left: left-syscfg@fd690000{
- compatible = "st,stih415-left-syscfg", "syscon";
- reg = <0xfd690000 0x78>;
- };
-
- syscfg_right: right-syscfg@fd320000{
- compatible = "st,stih415-right-syscfg", "syscon";
- reg = <0xfd320000 0x180>;
- };
-
- syscfg_system: system-syscfg@fdde0000 {
- compatible = "st,stih415-system-syscfg", "syscon";
- reg = <0xfdde0000 0x15c>;
- };
-
- syscfg_lpm: lpm-syscfg@fe4b5100{
- compatible = "st,stih415-lpm-syscfg", "syscon";
- reg = <0xfe4b5100 0x08>;
- };
-
- serial2: serial@fed32000 {
- compatible = "st,asc";
- status = "disabled";
- reg = <0xfed32000 0x2c>;
- interrupts = <0 197 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_serial2>;
- clocks = <&clk_s_a0_ls CLK_ICN_REG>;
- };
-
- /* SBC comms block ASCs in SASG1 */
- sbc_serial1: serial@fe531000 {
- compatible = "st,asc";
- status = "disabled";
- reg = <0xfe531000 0x2c>;
- interrupts = <0 210 0>;
- clocks = <&clk_sysin>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sbc_serial1>;
- };
-
- i2c@fed40000 {
- compatible = "st,comms-ssc4-i2c";
- reg = <0xfed40000 0x110>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_a0_ls CLK_ICN_REG>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0_default>;
-
- status = "disabled";
- };
-
- i2c@fed41000 {
- compatible = "st,comms-ssc4-i2c";
- reg = <0xfed41000 0x110>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_a0_ls CLK_ICN_REG>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1_default>;
-
- status = "disabled";
- };
-
- i2c@fe540000 {
- compatible = "st,comms-ssc4-i2c";
- reg = <0xfe540000 0x110>;
- interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_sysin>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sbc_i2c0_default>;
-
- status = "disabled";
- };
-
- i2c@fe541000 {
- compatible = "st,comms-ssc4-i2c";
- reg = <0xfe541000 0x110>;
- interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_sysin>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sbc_i2c1_default>;
-
- status = "disabled";
- };
-
- ethernet0: dwmac@fe810000 {
- device_type = "network";
- compatible = "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610";
- status = "disabled";
-
- reg = <0xfe810000 0x8000>;
- reg-names = "stmmaceth";
-
- interrupts = <0 147 0>, <0 148 0>, <0 149 0>;
- interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
- resets = <&softreset STIH415_ETH0_SOFTRESET>;
- reset-names = "stmmaceth";
-
- snps,pbl = <32>;
- snps,mixed-burst;
- snps,force_sf_dma_mode;
-
- st,syscon = <&syscfg_rear 0x148>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_mii0>;
- clock-names = "stmmaceth", "sti-ethclk";
- clocks = <&clk_s_a1_ls CLK_ICN_IF_2>, <&clk_s_a1_ls CLK_GMAC0_PHY>;
- };
-
- ethernet1: dwmac@fef08000 {
- device_type = "network";
- compatible = "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610";
- status = "disabled";
- reg = <0xfef08000 0x8000>;
- reg-names = "stmmaceth";
- interrupts = <0 150 0>, <0 151 0>, <0 152 0>;
- interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
-
- snps,pbl = <32>;
- snps,mixed-burst;
- snps,force_sf_dma_mode;
-
- st,syscon = <&syscfg_sbc 0x74>;
-
- resets = <&softreset STIH415_ETH1_SOFTRESET>;
- reset-names = "stmmaceth";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_mii1>;
- clock-names = "stmmaceth", "sti-ethclk";
- clocks = <&clk_s_a0_ls CLK_ICN_REG>, <&clk_s_a0_ls CLK_ETH1_PHY>;
- };
-
- rc: rc@fe518000 {
- compatible = "st,comms-irb";
- reg = <0xfe518000 0x234>;
- interrupts = <0 203 0>;
- clocks = <&clk_sysin>;
- rx-mode = "infrared";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ir>;
- resets = <&softreset STIH415_IRB_SOFTRESET>;
- };
-
- keyscan: keyscan@fe4b0000 {
- compatible = "st,sti-keyscan";
- status = "disabled";
- reg = <0xfe4b0000 0x2000>;
- interrupts = <GIC_SPI 212 IRQ_TYPE_NONE>;
- clocks = <&clk_sysin>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_keyscan>;
- resets = <&powerdown STIH415_KEYSCAN_POWERDOWN>,
- <&softreset STIH415_KEYSCAN_SOFTRESET>;
- };
-
- mmc0: sdhci@fe81e000 {
- compatible = "st,sdhci";
- status = "disabled";
- reg = <0xfe81e000 0x1000>;
- interrupts = <GIC_SPI 145 IRQ_TYPE_NONE>;
- interrupt-names = "mmcirq";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_mmc0>;
- clock-names = "mmc";
- clocks = <&clk_s_a1_ls 1>;
- };
- };
-};
--
cgit
From 27356509813dbbe1647340396109eeb859b38932 Mon Sep 17 00:00:00 2001
From: Patrice Chotard <patrice.chotard@st.com>
Date: Thu, 20 Oct 2016 15:22:49 +0200
Subject: ARM: dts: remove STiH416.dtsi
Since v4.8, STiH415/416 clock support has
been removed [1], these platform doesn't boot.
We can remove DTS files related to these socs.
[1] https://patchwork.kernel.org/patch/9157571/
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stih416.dtsi | 517 -----------------------------------------
1 file changed, 517 deletions(-)
delete mode 100644 arch/arm/boot/dts/stih416.dtsi
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
deleted file mode 100644
index fe1f9cf770e4..000000000000
--- a/arch/arm/boot/dts/stih416.dtsi
+++ /dev/null
@@ -1,517 +0,0 @@
-/*
- * Copyright (C) 2012 STMicroelectronics Limited.
- * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * publishhed by the Free Software Foundation.
- */
-#include "stih41x.dtsi"
-#include "stih416-clock.dtsi"
-#include "stih416-pinctrl.dtsi"
-
-#include <dt-bindings/phy/phy.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/reset/stih416-resets.h>
-#include <dt-bindings/interrupt-controller/irq-st.h>
-/ {
- L2: cache-controller {
- compatible = "arm,pl310-cache";
- reg = <0xfffe2000 0x1000>;
- arm,data-latency = <3 3 3>;
- arm,tag-latency = <2 2 2>;
- cache-unified;
- cache-level = <2>;
- };
-
- arm-pmu {
- compatible = "arm,cortex-a9-pmu";
- interrupt-parent = <&intc>;
- interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- soc {
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&intc>;
- ranges;
- compatible = "simple-bus";
-
- restart {
- compatible = "st,stih416-restart";
- st,syscfg = <&syscfg_sbc>;
- status = "okay";
- };
-
- powerdown: powerdown-controller {
- #reset-cells = <1>;
- compatible = "st,stih416-powerdown";
- };
-
- softreset: softreset-controller {
- #reset-cells = <1>;
- compatible = "st,stih416-softreset";
- };
-
- syscfg_sbc:sbc-syscfg@fe600000{
- compatible = "st,stih416-sbc-syscfg", "syscon";
- reg = <0xfe600000 0x1000>;
- };
-
- syscfg_front:front-syscfg@fee10000{
- compatible = "st,stih416-front-syscfg", "syscon";
- reg = <0xfee10000 0x1000>;
- };
-
- syscfg_rear:rear-syscfg@fe830000{
- compatible = "st,stih416-rear-syscfg", "syscon";
- reg = <0xfe830000 0x1000>;
- };
-
- /* MPE */
- syscfg_fvdp_fe:fvdp-fe-syscfg@fddf0000{
- compatible = "st,stih416-fvdp-fe-syscfg", "syscon";
- reg = <0xfddf0000 0x1000>;
- };
-
- syscfg_fvdp_lite:fvdp-lite-syscfg@fd6a0000{
- compatible = "st,stih416-fvdp-lite-syscfg", "syscon";
- reg = <0xfd6a0000 0x1000>;
- };
-
- syscfg_cpu:cpu-syscfg@fdde0000{
- compatible = "st,stih416-cpu-syscfg", "syscon";
- reg = <0xfdde0000 0x1000>;
- };
-
- syscfg_compo:compo-syscfg@fd320000{
- compatible = "st,stih416-compo-syscfg", "syscon";
- reg = <0xfd320000 0x1000>;
- };
-
- syscfg_transport:transport-syscfg@fd690000{
- compatible = "st,stih416-transport-syscfg", "syscon";
- reg = <0xfd690000 0x1000>;
- };
-
- syscfg_lpm:lpm-syscfg@fe4b5100{
- compatible = "st,stih416-lpm-syscfg", "syscon";
- reg = <0xfe4b5100 0x8>;
- };
-
- irq-syscfg {
- compatible = "st,stih416-irq-syscfg";
- st,syscfg = <&syscfg_cpu>;
- st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
- <ST_IRQ_SYSCFG_PMU_1>;
- st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
- <ST_IRQ_SYSCFG_DISABLED>;
- };
-
- serial2: serial@fed32000{
- compatible = "st,asc";
- status = "disabled";
- reg = <0xfed32000 0x2c>;
- interrupts = <0 197 0>;
- clocks = <&clk_s_a0_ls CLK_ICN_REG>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_serial2 &pinctrl_serial2_oe>;
- };
-
- /* SBC_UART1 */
- sbc_serial1: serial@fe531000 {
- compatible = "st,asc";
- status = "disabled";
- reg = <0xfe531000 0x2c>;
- interrupts = <0 210 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sbc_serial1>;
- clocks = <&clk_sysin>;
- };
-
- i2c@fed40000 {
- compatible = "st,comms-ssc4-i2c";
- reg = <0xfed40000 0x110>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_a0_ls CLK_ICN_REG>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0_default>;
-
- status = "disabled";
- };
-
- i2c@fed41000 {
- compatible = "st,comms-ssc4-i2c";
- reg = <0xfed41000 0x110>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_a0_ls CLK_ICN_REG>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1_default>;
-
- status = "disabled";
- };
-
- i2c@fe540000 {
- compatible = "st,comms-ssc4-i2c";
- reg = <0xfe540000 0x110>;
- interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_sysin>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sbc_i2c0_default>;
-
- status = "disabled";
- };
-
- i2c@fe541000 {
- compatible = "st,comms-ssc4-i2c";
- reg = <0xfe541000 0x110>;
- interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_sysin>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sbc_i2c1_default>;
-
- status = "disabled";
- };
-
- ethernet0: dwmac@fe810000 {
- device_type = "network";
- compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
- status = "disabled";
- reg = <0xfe810000 0x8000>;
- reg-names = "stmmaceth";
-
- interrupts = <0 133 0>, <0 134 0>, <0 135 0>;
- interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
-
- snps,pbl = <32>;
- snps,mixed-burst;
-
- st,syscon = <&syscfg_rear 0x8bc>;
- resets = <&softreset STIH416_ETH0_SOFTRESET>;
- reset-names = "stmmaceth";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_mii0>;
- clock-names = "stmmaceth", "sti-ethclk";
- clocks = <&clk_s_a1_ls CLK_ICN_IF_2>, <&clk_s_a1_ls CLK_GMAC0_PHY>;
- };
-
- ethernet1: dwmac@fef08000 {
- device_type = "network";
- compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
- status = "disabled";
- reg = <0xfef08000 0x8000>;
- reg-names = "stmmaceth";
- interrupts = <0 136 0>, <0 137 0>, <0 138 0>;
- interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
-
- snps,pbl = <32>;
- snps,mixed-burst;
-
- st,syscon = <&syscfg_sbc 0x7f0>;
-
- resets = <&softreset STIH416_ETH1_SOFTRESET>;
- reset-names = "stmmaceth";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_mii1>;
- clock-names = "stmmaceth", "sti-ethclk";
- clocks = <&clk_s_a0_ls CLK_ICN_REG>, <&clk_s_a0_ls CLK_ETH1_PHY>;
- };
-
- rc: rc@fe518000 {
- compatible = "st,comms-irb";
- reg = <0xfe518000 0x234>;
- interrupts = <0 203 0>;
- rx-mode = "infrared";
- clocks = <&clk_sysin>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ir>;
- resets = <&softreset STIH416_IRB_SOFTRESET>;
- };
-
- /* FSM */
- spifsm: spifsm@fe902000 {
- compatible = "st,spi-fsm";
- reg = <0xfe902000 0x1000>;
- pinctrl-0 = <&pinctrl_fsm>;
-
- st,syscfg = <&syscfg_rear>;
- st,boot-device-reg = <0x958>;
- st,boot-device-spi = <0x1a>;
-
- status = "disabled";
- };
-
- keyscan: keyscan@fe4b0000 {
- compatible = "st,sti-keyscan";
- status = "disabled";
- reg = <0xfe4b0000 0x2000>;
- interrupts = <GIC_SPI 212 IRQ_TYPE_NONE>;
- clocks = <&clk_sysin>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_keyscan>;
- resets = <&powerdown STIH416_KEYSCAN_POWERDOWN>,
- <&softreset STIH416_KEYSCAN_SOFTRESET>;
- };
-
- temp0 {
- compatible = "st,stih416-sas-thermal";
- clock-names = "thermal";
- clocks = <&clockgen_c_vcc 14>;
-
- status = "okay";
- };
-
- temp1@fdfe8000 {
- compatible = "st,stih416-mpe-thermal";
- reg = <0xfdfe8000 0x10>;
- clocks = <&clockgen_e 3>;
- clock-names = "thermal";
- interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
-
- status = "okay";
- };
-
- mmc0: sdhci@fe81e000 {
- compatible = "st,sdhci";
- status = "disabled";
- reg = <0xfe81e000 0x1000>;
- interrupts = <GIC_SPI 127 IRQ_TYPE_NONE>;
- interrupt-names = "mmcirq";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_mmc0>;
- clock-names = "mmc";
- clocks = <&clk_s_a1_ls 1>;
- };
-
- mmc1: sdhci@fe81f000 {
- compatible = "st,sdhci";
- status = "disabled";
- reg = <0xfe81f000 0x1000>;
- interrupts = <GIC_SPI 128 IRQ_TYPE_NONE>;
- interrupt-names = "mmcirq";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_mmc1>;
- clock-names = "mmc";
- clocks = <&clk_s_a1_ls 8>;
- };
-
- miphy365x_phy: phy@fe382000 {
- compatible = "st,miphy365x-phy";
- st,syscfg = <&syscfg_rear 0x824 0x828>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- phy_port0: port@fe382000 {
- #phy-cells = <1>;
- reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
- reg-names = "sata", "pcie";
- };
-
- phy_port1: port@fe38a000 {
- #phy-cells = <1>;
- reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;
- reg-names = "sata", "pcie";
- };
- };
-
- sata0: sata@fe380000 {
- compatible = "st,sti-ahci";
- reg = <0xfe380000 0x1000>;
- interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
- interrupt-names = "hostc";
- phys = <&phy_port0 PHY_TYPE_SATA>;
- phy-names = "sata-phy";
- resets = <&powerdown STIH416_SATA0_POWERDOWN>,
- <&softreset STIH416_SATA0_SOFTRESET>;
- reset-names = "pwr-dwn", "sw-rst";
- clock-names = "ahci_clk";
- clocks = <&clk_s_a0_ls CLK_ICN_REG>;
-
- status = "disabled";
- };
-
- usb2_phy: phy@0 {
- compatible = "st,stih416-usb-phy";
- #phy-cells = <0>;
- st,syscfg = <&syscfg_rear>;
- clocks = <&clk_sysin>;
- clock-names = "osc_phy";
- };
-
- ehci0: usb@fe1ffe00 {
- compatible = "st,st-ehci-300x";
- reg = <0xfe1ffe00 0x100>;
- interrupts = <GIC_SPI 148 IRQ_TYPE_NONE>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0>;
- clocks = <&clk_s_a1_ls 0>,
- <&clockgen_b0 0>;
- clock-names = "ic", "clk48";
- phys = <&usb2_phy>;
- phy-names = "usb";
- resets = <&powerdown STIH416_USB0_POWERDOWN>,
- <&softreset STIH416_USB0_SOFTRESET>;
- reset-names = "power", "softreset";
- };
-
- ohci0: usb@fe1ffc00 {
- compatible = "st,st-ohci-300x";
- reg = <0xfe1ffc00 0x100>;
- interrupts = <GIC_SPI 149 IRQ_TYPE_NONE>;
- clocks = <&clk_s_a1_ls 0>,
- <&clockgen_b0 0>;
- clock-names = "ic", "clk48";
- phys = <&usb2_phy>;
- phy-names = "usb";
- status = "okay";
- resets = <&powerdown STIH416_USB0_POWERDOWN>,
- <&softreset STIH416_USB0_SOFTRESET>;
- reset-names = "power", "softreset";
- };
-
- ehci1: usb@fe203e00 {
- compatible = "st,st-ehci-300x";
- reg = <0xfe203e00 0x100>;
- interrupts = <GIC_SPI 150 IRQ_TYPE_NONE>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1>;
- clocks = <&clk_s_a1_ls 0>,
- <&clockgen_b0 0>;
- clock-names = "ic", "clk48";
- phys = <&usb2_phy>;
- phy-names = "usb";
- resets = <&powerdown STIH416_USB1_POWERDOWN>,
- <&softreset STIH416_USB1_SOFTRESET>;
- reset-names = "power", "softreset";
- };
-
- ohci1: usb@fe203c00 {
- compatible = "st,st-ohci-300x";
- reg = <0xfe203c00 0x100>;
- interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
- clocks = <&clk_s_a1_ls 0>,
- <&clockgen_b0 0>;
- clock-names = "ic", "clk48";
- phys = <&usb2_phy>;
- phy-names = "usb";
- resets = <&powerdown STIH416_USB1_POWERDOWN>,
- <&softreset STIH416_USB1_SOFTRESET>;
- reset-names = "power", "softreset";
- };
-
- ehci2: usb@fe303e00 {
- compatible = "st,st-ehci-300x";
- reg = <0xfe303e00 0x100>;
- interrupts = <GIC_SPI 152 IRQ_TYPE_NONE>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb2>;
- clocks = <&clk_s_a1_ls 0>,
- <&clockgen_b0 0>;
- clock-names = "ic", "clk48";
- phys = <&usb2_phy>;
- phy-names = "usb";
- resets = <&powerdown STIH416_USB2_POWERDOWN>,
- <&softreset STIH416_USB2_SOFTRESET>;
- reset-names = "power", "softreset";
- };
-
- ohci2: usb@fe303c00 {
- compatible = "st,st-ohci-300x";
- reg = <0xfe303c00 0x100>;
- interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
- clocks = <&clk_s_a1_ls 0>,
- <&clockgen_b0 0>;
- clock-names = "ic", "clk48";
- phys = <&usb2_phy>;
- phy-names = "usb";
- resets = <&powerdown STIH416_USB2_POWERDOWN>,
- <&softreset STIH416_USB2_SOFTRESET>;
- reset-names = "power", "softreset";
- };
-
- ehci3: usb@fe343e00 {
- compatible = "st,st-ehci-300x";
- reg = <0xfe343e00 0x100>;
- interrupts = <GIC_SPI 154 IRQ_TYPE_NONE>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb3>;
- clocks = <&clk_s_a1_ls 0>,
- <&clockgen_b0 0>;
- clock-names = "ic", "clk48";
- phys = <&usb2_phy>;
- phy-names = "usb";
- resets = <&powerdown STIH416_USB3_POWERDOWN>,
- <&softreset STIH416_USB3_SOFTRESET>;
- reset-names = "power", "softreset";
- };
-
- ohci3: usb@fe343c00 {
- compatible = "st,st-ohci-300x";
- reg = <0xfe343c00 0x100>;
- interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>;
- clocks = <&clk_s_a1_ls 0>,
- <&clockgen_b0 0>;
- clock-names = "ic", "clk48";
- phys = <&usb2_phy>;
- phy-names = "usb";
- resets = <&powerdown STIH416_USB3_POWERDOWN>,
- <&softreset STIH416_USB3_SOFTRESET>;
- reset-names = "power", "softreset";
- };
-
- /* SAS PWM Module */
- pwm0: pwm@fed10000 {
- compatible = "st,sti-pwm";
- status = "disabled";
- #pwm-cells = <2>;
- reg = <0xfed10000 0x68>;
- interrupts = <GIC_SPI 200 IRQ_TYPE_NONE>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm0_chan0_default
- &pinctrl_pwm0_chan1_default
- &pinctrl_pwm0_chan2_default
- &pinctrl_pwm0_chan3_default>;
-
- clock-names = "pwm", "capture";
- clocks = <&clk_sysin>, <&clk_s_a0_ls CLK_ICN_REG>;
-
- st,pwm-num-chan = <4>;
- st,capture-num-chan = <2>;
- };
-
- /* SBC PWM Module */
- pwm1: pwm@fe510000 {
- compatible = "st,sti-pwm";
- status = "disabled";
- #pwm-cells = <2>;
- reg = <0xfe510000 0x68>;
- interrupts = <GIC_SPI 202 IRQ_TYPE_NONE>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm1_chan0_default
- /*
- * Shared with SBC_OBS_NOTRST. Don't
- * enable unless you really know what
- * you're doing.
- *
- * &pinctrl_pwm1_chan1_default
- */
- &pinctrl_pwm1_chan2_default
- &pinctrl_pwm1_chan3_default>;
-
- clock-names = "pwm";
- clocks = <&clk_sysin>;
- st,pwm-num-chan = <3>;
- };
- };
-};
--
cgit
From 01a66a33d0fba3e2beadd468d28233a835008af9 Mon Sep 17 00:00:00 2001
From: Patrice Chotard <patrice.chotard@st.com>
Date: Thu, 20 Oct 2016 15:23:47 +0200
Subject: ARM: dts: remove STiH41x.dtsi
Since v4.8, STiH415/416 clock support has
been removed [1], these platform doesn't boot.
We can remove DTS files related to these socs.
[1] https://patchwork.kernel.org/patch/9157571/
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stih41x.dtsi | 47 ------------------------------------------
1 file changed, 47 deletions(-)
delete mode 100644 arch/arm/boot/dts/stih41x.dtsi
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/stih41x.dtsi b/arch/arm/boot/dts/stih41x.dtsi
deleted file mode 100644
index 5cb0e63376b5..000000000000
--- a/arch/arm/boot/dts/stih41x.dtsi
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright (C) 2014 STMicroelectronics Limited.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * publishhed by the Free Software Foundation.
- */
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0>;
- };
- cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <1>;
- };
- };
-
- intc: interrupt-controller@fffe1000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0xfffe1000 0x1000>,
- <0xfffe0100 0x100>;
- };
-
- scu@fffe0000 {
- compatible = "arm,cortex-a9-scu";
- reg = <0xfffe0000 0x1000>;
- };
-
- timer@fffe0200 {
- interrupt-parent = <&intc>;
- compatible = "arm,cortex-a9-global-timer";
- reg = <0xfffe0200 0x100>;
- interrupts = <1 11 0x04>;
- clocks = <&arm_periph_clk>;
- };
-};
--
cgit
From 10da42c9001c8b47a7abdd283c965c42334ce0a2 Mon Sep 17 00:00:00 2001
From: Patrice Chotard <patrice.chotard@st.com>
Date: Thu, 20 Oct 2016 15:24:06 +0200
Subject: ARM: dts: remove STiH41x-b2020.dtsi
Since v4.8, STiH415/416 clock support has
been removed [1], these platform doesn't boot.
We can remove DTS files related to these socs.
[1] https://patchwork.kernel.org/patch/9157571/
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stih41x-b2020x.dtsi | 32 --------------------------------
1 file changed, 32 deletions(-)
delete mode 100644 arch/arm/boot/dts/stih41x-b2020x.dtsi
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/stih41x-b2020x.dtsi b/arch/arm/boot/dts/stih41x-b2020x.dtsi
deleted file mode 100644
index f797a0607382..000000000000
--- a/arch/arm/boot/dts/stih41x-b2020x.dtsi
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
- * Author: Lee Jones <lee.jones@linaro.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * publishhed by the Free Software Foundation.
- */
-/ {
- soc {
- mmc0: sdhci@fe81e000 {
- status = "okay";
- };
-
- spifsm: spifsm@fe902000 {
- #address-cells = <1>;
- #size-cells = <1>;
-
- status = "okay";
-
- partition@0 {
- label = "SerialFlash1";
- reg = <0x00000000 0x00500000>;
- };
-
- partition@500000 {
- label = "SerialFlash2";
- reg = <0x00500000 0x00b00000>;
- };
- };
- };
-};
--
cgit
From 8690d17e5716e1576c0bd93439461114666f3bf5 Mon Sep 17 00:00:00 2001
From: Patrice Chotard <patrice.chotard@st.com>
Date: Thu, 20 Oct 2016 15:25:10 +0200
Subject: ARM: dts: remove STiH41x-b2000.dtsi
Since v4.8, STiH415/416 clock support has
been removed [1], these platform doesn't boot.
We can remove DTS files related to these socs.
[1] https://patchwork.kernel.org/patch/9157571/
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stih41x-b2000.dtsi | 96 ------------------------------------
1 file changed, 96 deletions(-)
delete mode 100644 arch/arm/boot/dts/stih41x-b2000.dtsi
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/stih41x-b2000.dtsi b/arch/arm/boot/dts/stih41x-b2000.dtsi
deleted file mode 100644
index 9bfa0674b452..000000000000
--- a/arch/arm/boot/dts/stih41x-b2000.dtsi
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
- * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * publishhed by the Free Software Foundation.
- */
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-
- memory{
- device_type = "memory";
- reg = <0x60000000 0x40000000>;
- };
-
- chosen {
- bootargs = "console=ttyAS0,115200 clk_ignore_unused";
- linux,stdout-path = &serial2;
- };
-
- aliases {
- ttyAS0 = &serial2;
- ethernet0 = ðernet0;
- ethernet1 = ðernet1;
- };
-
- soc {
- serial2: serial@fed32000 {
- status = "okay";
- };
-
- leds {
- compatible = "gpio-leds";
- fp_led {
- label = "Front Panel LED";
- gpios = <&pio105 7 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- /* HDMI Tx I2C */
- i2c@fed41000 {
- /* HDMI V1.3a supports Standard mode only */
- clock-frequency = <100000>;
- i2c-min-scl-pulse-width-us = <0>;
- i2c-min-sda-pulse-width-us = <5>;
-
- status = "okay";
- };
-
- ethernet0: dwmac@fe810000 {
- status = "okay";
- phy-mode = "mii";
- pinctrl-0 = <&pinctrl_mii0>;
-
- snps,reset-gpio = <&pio106 2>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 10000>;
- };
-
- ethernet1: dwmac@fef08000 {
- status = "disabled";
- phy-mode = "mii";
- st,tx-retime-src = "txclk";
-
- snps,reset-gpio = <&pio4 7>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 10000>;
- };
-
- keyscan: keyscan@fe4b0000 {
- keypad,num-rows = <4>;
- keypad,num-columns = <4>;
- st,debounce-us = <5000>;
- linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_F13)
- MATRIX_KEY(0x00, 0x01, KEY_F9)
- MATRIX_KEY(0x00, 0x02, KEY_F5)
- MATRIX_KEY(0x00, 0x03, KEY_F1)
- MATRIX_KEY(0x01, 0x00, KEY_F14)
- MATRIX_KEY(0x01, 0x01, KEY_F10)
- MATRIX_KEY(0x01, 0x02, KEY_F6)
- MATRIX_KEY(0x01, 0x03, KEY_F2)
- MATRIX_KEY(0x02, 0x00, KEY_F15)
- MATRIX_KEY(0x02, 0x01, KEY_F11)
- MATRIX_KEY(0x02, 0x02, KEY_F7)
- MATRIX_KEY(0x02, 0x03, KEY_F3)
- MATRIX_KEY(0x03, 0x00, KEY_F16)
- MATRIX_KEY(0x03, 0x01, KEY_F12)
- MATRIX_KEY(0x03, 0x02, KEY_F8)
- MATRIX_KEY(0x03, 0x03, KEY_F4) >;
- };
- };
-};
--
cgit
From 11079647c20ea9d4b9b0ddfa205049835d414233 Mon Sep 17 00:00:00 2001
From: Patrice Chotard <patrice.chotard@st.com>
Date: Thu, 20 Oct 2016 15:25:35 +0200
Subject: ARM: dts: remove STiH41x-b2020.dtsi
Since v4.8, STiH415/416 clock support has
been removed [1], these platform doesn't boot.
We can remove DTS files related to these socs.
[1] https://patchwork.kernel.org/patch/9157571/
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stih41x-b2020.dtsi | 82 ------------------------------------
1 file changed, 82 deletions(-)
delete mode 100644 arch/arm/boot/dts/stih41x-b2020.dtsi
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi
deleted file mode 100644
index 322e0e95176c..000000000000
--- a/arch/arm/boot/dts/stih41x-b2020.dtsi
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
- * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * publishhed by the Free Software Foundation.
- */
-#include "stih41x-b2020x.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-/ {
- memory{
- device_type = "memory";
- reg = <0x40000000 0x80000000>;
- };
-
- chosen {
- bootargs = "console=ttyAS0,115200 clk_ignore_unused";
- linux,stdout-path = &sbc_serial1;
- };
-
- aliases {
- ttyAS0 = &sbc_serial1;
- ethernet1 = ðernet1;
- };
- soc {
- sbc_serial1: serial@fe531000 {
- status = "okay";
- };
-
- leds {
- compatible = "gpio-leds";
- red {
- label = "Front Panel LED";
- gpios = <&pio4 1 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- green {
- gpios = <&pio4 7 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
- };
-
- i2c@fed40000 {
- status = "okay";
- };
-
- /* HDMI Tx I2C */
- i2c@fed41000 {
- /* HDMI V1.3a supports Standard mode only */
- clock-frequency = <100000>;
- i2c-min-scl-pulse-width-us = <0>;
- i2c-min-sda-pulse-width-us = <5>;
-
- status = "okay";
- };
-
- i2c@fe540000 {
- status = "okay";
- };
-
- i2c@fe541000 {
- status = "okay";
- };
-
- ethernet1: dwmac@fef08000 {
- status = "okay";
- phy-mode = "rgmii-id";
- max-speed = <1000>;
- st,tx-retime-src = "clk_125";
- snps,reset-gpio = <&pio3 0>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 10000>;
-
- pinctrl-0 = <&pinctrl_rgmii1>;
- };
-
- mmc0: sdhci@fe81e000 {
- bus-width = <8>;
- };
- };
-};
--
cgit
From a6f1c53a720e3cbf1f679dcfae3cf659f97b0423 Mon Sep 17 00:00:00 2001
From: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Date: Tue, 4 Oct 2016 18:11:00 +0200
Subject: ARM: dts: STiH407-family: sti sound card field cleaning
Cleaning of some uni-players and uni-reader fields.
Associated configurations are now handled in driver based
on compatible string.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stih407-family.dtsi | 32 ++++++--------------------------
1 file changed, 6 insertions(+), 26 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
index 91096a49efa9..d29960b6c47b 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -900,7 +900,7 @@
};
sti_uni_player0: sti-uni-player@8d80000 {
- compatible = "st,sti-uni-player";
+ compatible = "st,stih407-uni-player-hdmi";
#sound-dai-cells = <0>;
st,syscfg = <&syscfg_core>;
clocks = <&clk_s_d0_flexgen CLK_PCM_0>;
@@ -910,17 +910,13 @@
reg = <0x8d80000 0x158>;
interrupts = <GIC_SPI 84 IRQ_TYPE_NONE>;
dmas = <&fdma0 2 0 1>;
- dai-name = "Uni Player #0 (HDMI)";
dma-names = "tx";
- st,uniperiph-id = <0>;
- st,version = <5>;
- st,mode = "HDMI";
status = "disabled";
};
sti_uni_player1: sti-uni-player@8d81000 {
- compatible = "st,sti-uni-player";
+ compatible = "st,stih407-uni-player-pcm-out";
#sound-dai-cells = <0>;
st,syscfg = <&syscfg_core>;
clocks = <&clk_s_d0_flexgen CLK_PCM_1>;
@@ -930,17 +926,13 @@
reg = <0x8d81000 0x158>;
interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
dmas = <&fdma0 3 0 1>;
- dai-name = "Uni Player #1 (PIO)";
dma-names = "tx";
- st,uniperiph-id = <1>;
- st,version = <5>;
- st,mode = "PCM";
status = "disabled";
};
sti_uni_player2: sti-uni-player@8d82000 {
- compatible = "st,sti-uni-player";
+ compatible = "st,stih407-uni-player-dac";
#sound-dai-cells = <0>;
st,syscfg = <&syscfg_core>;
clocks = <&clk_s_d0_flexgen CLK_PCM_2>;
@@ -950,17 +942,13 @@
reg = <0x8d82000 0x158>;
interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
dmas = <&fdma0 4 0 1>;
- dai-name = "Uni Player #1 (DAC)";
dma-names = "tx";
- st,uniperiph-id = <2>;
- st,version = <5>;
- st,mode = "PCM";
status = "disabled";
};
sti_uni_player3: sti-uni-player@8d85000 {
- compatible = "st,sti-uni-player";
+ compatible = "st,stih407-uni-player-spdif";
#sound-dai-cells = <0>;
st,syscfg = <&syscfg_core>;
clocks = <&clk_s_d0_flexgen CLK_SPDIFF>;
@@ -971,38 +959,30 @@
interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
dmas = <&fdma0 7 0 1>;
dma-names = "tx";
- dai-name = "Uni Player #1 (PIO)";
- st,uniperiph-id = <3>;
- st,version = <5>;
- st,mode = "SPDIF";
status = "disabled";
};
sti_uni_reader0: sti-uni-reader@8d83000 {
- compatible = "st,sti-uni-reader";
+ compatible = "st,stih407-uni-reader-pcm_in";
#sound-dai-cells = <0>;
st,syscfg = <&syscfg_core>;
reg = <0x8d83000 0x158>;
interrupts = <GIC_SPI 87 IRQ_TYPE_NONE>;
dmas = <&fdma0 5 0 1>;
dma-names = "rx";
- dai-name = "Uni Reader #0 (PCM IN)";
- st,version = <3>;
status = "disabled";
};
sti_uni_reader1: sti-uni-reader@8d84000 {
- compatible = "st,sti-uni-reader";
+ compatible = "st,stih407-uni-reader-hdmi";
#sound-dai-cells = <0>;
st,syscfg = <&syscfg_core>;
reg = <0x8d84000 0x158>;
interrupts = <GIC_SPI 88 IRQ_TYPE_NONE>;
dmas = <&fdma0 6 0 1>;
dma-names = "rx";
- dai-name = "Uni Reader #1 (HDMI RX)";
- st,version = <3>;
status = "disabled";
};
--
cgit
From eec7f93f6c652c3fd3380a9d71d34f27012fadb6 Mon Sep 17 00:00:00 2001
From: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Date: Tue, 4 Oct 2016 18:11:00 +0200
Subject: ARM: dts: STiH407: Add label for sti-hdmi node
Needed to declare HDMI device in sound card
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stih407.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi
index 291ffacbd2e0..fa149837df14 100644
--- a/arch/arm/boot/dts/stih407.dtsi
+++ b/arch/arm/boot/dts/stih407.dtsi
@@ -102,7 +102,7 @@
<&clk_s_d2_quadfs 0>;
};
- sti-hdmi@8d04000 {
+ sti_hdmi: sti-hdmi@8d04000 {
compatible = "st,stih407-hdmi";
reg = <0x8d04000 0x1000>;
reg-names = "hdmi-reg";
--
cgit
From 24595472ff96e13d06798087bf4f377a2c164702 Mon Sep 17 00:00:00 2001
From: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Date: Tue, 4 Oct 2016 18:11:00 +0200
Subject: ARM: dts: STiH410: Add label for sti-hdmi node
Needed to declare HDMI device in sound card
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stih410.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi
index a3ef7341c051..281a12424cf6 100644
--- a/arch/arm/boot/dts/stih410.dtsi
+++ b/arch/arm/boot/dts/stih410.dtsi
@@ -193,7 +193,7 @@
<&clk_s_d2_quadfs 0>;
};
- sti-hdmi@8d04000 {
+ sti_hdmi: sti-hdmi@8d04000 {
compatible = "st,stih407-hdmi";
reg = <0x8d04000 0x1000>;
reg-names = "hdmi-reg";
--
cgit
From 800b1388300a0c4d150aee920c7b024bdca9a890 Mon Sep 17 00:00:00 2001
From: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Date: Tue, 4 Oct 2016 18:11:00 +0200
Subject: ARM: dts: STiHxxx-b2120: Add support of HDMI audio
Add new dai link in sound card to support HDMI output
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stihxxx-b2120.dtsi | 19 ++++++++++++++++++-
1 file changed, 18 insertions(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi
index ed2b7a99ecff..313c1f8686d4 100644
--- a/arch/arm/boot/dts/stihxxx-b2120.dtsi
+++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi
@@ -135,6 +135,10 @@
};
};
+ sti_uni_player0: sti-uni-player@8d80000 {
+ status = "okay";
+ };
+
sti_uni_player2: sti-uni-player@8d82000 {
status = "okay";
};
@@ -155,9 +159,22 @@
status = "okay";
simple-audio-card,dai-link@0 {
+ /* HDMI */
+ format = "i2s";
+ mclk-fs = <128>;
+ cpu {
+ sound-dai = <&sti_uni_player0>;
+ };
+
+ codec {
+ sound-dai = <&sti_hdmi>;
+ };
+ };
+ simple-audio-card,dai-link@1 {
/* DAC */
format = "i2s";
mclk-fs = <256>;
+ frame-inversion = <1>;
cpu {
sound-dai = <&sti_uni_player2>;
};
@@ -166,7 +183,7 @@
sound-dai = <&sti_sasg_codec 1>;
};
};
- simple-audio-card,dai-link@1 {
+ simple-audio-card,dai-link@2 {
/* SPDIF */
format = "left_j";
mclk-fs = <128>;
--
cgit
From 7b25718e806476e4b286ab3a4a7244e5e909043f Mon Sep 17 00:00:00 2001
From: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Date: Tue, 4 Oct 2016 18:11:00 +0200
Subject: ARM: dts: STiH410-B2260: clean unnecessary hdmi node overlay
sti-hdmi is already enabled in stih410.dtsi.
So no need to declare it here.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stih410-b2260.dts | 6 ------
1 file changed, 6 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/stih410-b2260.dts b/arch/arm/boot/dts/stih410-b2260.dts
index ef2ff2f518f6..511a1098741e 100644
--- a/arch/arm/boot/dts/stih410-b2260.dts
+++ b/arch/arm/boot/dts/stih410-b2260.dts
@@ -174,12 +174,6 @@
status = "okay";
};
- sti-display-subsystem {
- sti_hdmi: sti-hdmi@8d04000 {
- status = "okay";
- };
- };
-
miphy28lp_phy: miphy28lp@9b22000 {
phy_port1: port@9b2a000 {
--
cgit
From 97a0b97f9e8197429eee5f87ce14373f73dbd9d3 Mon Sep 17 00:00:00 2001
From: Peter Griffin <peter.griffin@linaro.org>
Date: Tue, 18 Oct 2016 17:35:00 +0200
Subject: ARM: dts: stih410-clocks: Add PROC_STFE as a critical clock
Once the ST frontend demux HW IP has been enabled, the clock can't
be disabled otherwise the system will hang and the board will
be unserviceable.
To allow balanced clock enable/disable calls in the driver we use
the critical clock infrastructure to take an extra reference on the
clock so the clock will never actually be disabled.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stih410-clock.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi
index 8598effd6c01..07c8ef9d77f6 100644
--- a/arch/arm/boot/dts/stih410-clock.dtsi
+++ b/arch/arm/boot/dts/stih410-clock.dtsi
@@ -208,7 +208,8 @@
"clk-clust-hades",
"clk-hwpe-hades",
"clk-fc-hades";
- clock-critical = <CLK_ICN_CPU>,
+ clock-critical = <CLK_PROC_STFE>,
+ <CLK_ICN_CPU>,
<CLK_TX_ICN_DMU>,
<CLK_EXT2F_A9>,
<CLK_ICN_LMI>,
--
cgit
From e0dce187559c83116b280038c31af9bb3aa3e901 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Mon, 19 Sep 2016 23:40:44 +0200
Subject: ARM: dts: at91: sama5d4: Add new MA5D4EVK manufacturer compat
The board is now manufactured by Aries Embedded GmbH, update compat string.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi | 4 ++--
arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi b/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi
index a92c6e0ca854..b5a5a91bc2ef 100644
--- a/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi
+++ b/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi
@@ -12,8 +12,8 @@
#include "sama5d4.dtsi"
/ {
- model = "DENX MA5D4";
- compatible = "denx,ma5d4", "atmel,sama5d4", "atmel,sama5";
+ model = "Aries/DENX MA5D4";
+ compatible = "aries,ma5d4", "denx,ma5d4", "atmel,sama5d4", "atmel,sama5";
memory {
reg = <0x20000000 0x10000000>;
diff --git a/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts b/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts
index eac4ea2744cc..84be29f38dae 100644
--- a/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts
+++ b/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts
@@ -13,8 +13,8 @@
#include "at91-sama5d4_ma5d4.dtsi"
/ {
- model = "DENX MA5D4EVK";
- compatible = "denx,ma5d4evk", "atmel,sama5d4", "atmel,sama5";
+ model = "Aries/DENX MA5D4EVK";
+ compatible = "aries,ma5d4evk", "denx,ma5d4evk", "atmel,sama5d4", "atmel,sama5";
chosen {
stdout-path = "serial3:115200n8";
--
cgit
From 54475c8d78003d834ccb835bbe37357855b6ab4c Mon Sep 17 00:00:00 2001
From: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Date: Wed, 5 Oct 2016 18:53:07 +0200
Subject: ARM: dts: at91: sama5d2: enable FIFOs for high-speed i2c controllers
This patch enables the RX and TX FIFOs (16 data each) of the two
high-speed i2c controllers (i2c0 and i2c1).
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/boot/dts/sama5d2.dtsi | 2 ++
1 file changed, 2 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
index 7173ec9059a1..a0dd649db455 100644
--- a/arch/arm/boot/dts/sama5d2.dtsi
+++ b/arch/arm/boot/dts/sama5d2.dtsi
@@ -1030,6 +1030,7 @@
#address-cells = <1>;
#size-cells = <0>;
clocks = <&twi0_clk>;
+ atmel,fifo-size = <16>;
status = "disabled";
};
@@ -1231,6 +1232,7 @@
#address-cells = <1>;
#size-cells = <0>;
clocks = <&twi1_clk>;
+ atmel,fifo-size = <16>;
status = "disabled";
};
--
cgit
From 138c2b2f175b781242342ee96fa125558c34a245 Mon Sep 17 00:00:00 2001
From: Sylvain Rochet <sylvain.rochet@finsecur.com>
Date: Sun, 16 Oct 2016 18:21:45 +0200
Subject: ARM: dts: at91: fixes dbgu pinctrl, set pullup on rx, clear pullup on
tx
Remove pullup on dbgu DTXD signal, it is a push-pull output thus the
pullup is pointless.
Add pullup on dbgu DRXD signal, it prevents the DRXD signal to be left
floating and so consuming a useless extra amount of power in crowbarred
state if nothing is externally connected to dbgu.
Signed-off-by: Sylvain Rochet <sylvain.rochet@finsecur.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/boot/dts/at91rm9200.dtsi | 4 ++--
arch/arm/boot/dts/at91sam9260.dtsi | 4 ++--
arch/arm/boot/dts/at91sam9261.dtsi | 4 ++--
arch/arm/boot/dts/at91sam9263.dtsi | 4 ++--
arch/arm/boot/dts/at91sam9g45.dtsi | 4 ++--
arch/arm/boot/dts/at91sam9n12.dtsi | 4 ++--
arch/arm/boot/dts/at91sam9rl.dtsi | 4 ++--
arch/arm/boot/dts/at91sam9x5.dtsi | 4 ++--
arch/arm/boot/dts/sama5d3.dtsi | 4 ++--
arch/arm/boot/dts/sama5d4.dtsi | 4 ++--
10 files changed, 20 insertions(+), 20 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index 4e913c2ccb79..f057e0b15a6f 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -481,8 +481,8 @@
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
- <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A */
- AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA31 periph with pullup */
+ <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index a3e363d79122..9e035b21e1b6 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -412,8 +412,8 @@
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
- <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */
- AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB15 periph with pullup */
+ <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi
index 32752d7883f1..3fe77c38bd0d 100644
--- a/arch/arm/boot/dts/at91sam9261.dtsi
+++ b/arch/arm/boot/dts/at91sam9261.dtsi
@@ -302,8 +302,8 @@
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
- <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE>,
- <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
+ <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
+ <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index aeb1a36373f4..a1888f6d892b 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -412,8 +412,8 @@
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
- <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC30 periph A */
- AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC31 periph with pullup */
+ <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index b3501ae2a3bd..e567d5fd3f9d 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -478,8 +478,8 @@
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
- <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */
- AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */
+ <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 3b3eb3edcb47..f43d7695352d 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -500,8 +500,8 @@
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
- <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */
- AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA10 periph with pullup */
+ <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi
index 70adf940d98c..f4c129a98f17 100644
--- a/arch/arm/boot/dts/at91sam9rl.dtsi
+++ b/arch/arm/boot/dts/at91sam9rl.dtsi
@@ -438,8 +438,8 @@
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
- <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>,
- <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
+ <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
+ <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index ed4e4bd8a8f1..f66bae925705 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -460,8 +460,8 @@
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
- <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */
- AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA10 periph A with pullup */
+ <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index 4c84d333fc7e..b06448ba6649 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -549,8 +549,8 @@
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
- <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB30 periph A */
- AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB31 periph A with pullup */
+ <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
index 65e725fb5679..f7bfc6229285 100644
--- a/arch/arm/boot/dts/sama5d4.dtsi
+++ b/arch/arm/boot/dts/sama5d4.dtsi
@@ -1461,8 +1461,8 @@
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
- <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>, /* conflicts with D14 and TDI */
- <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* conflicts with D15 and TDO */
+ <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* conflicts with D14 and TDI */
+ AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with D15 and TDO */
};
};
--
cgit
From fd166a3e0534de98f44f3b1d3fdd221e855c449e Mon Sep 17 00:00:00 2001
From: Geert Uytterhoeven <geert+renesas@glider.be>
Date: Fri, 21 Oct 2016 10:51:00 +0200
Subject: ARM: dts: STiH407: DT fix s/interrupts-names/interrupt-names/
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
---
arch/arm/boot/dts/stih407-pinctrl.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi
index c325cc059ae4..daab16b5ae64 100644
--- a/arch/arm/boot/dts/stih407-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi
@@ -1157,7 +1157,7 @@
reg = <0x0923f080 0x4>;
reg-names = "irqmux";
interrupts = <GIC_SPI 192 IRQ_TYPE_NONE>;
- interrupts-names = "irqmux";
+ interrupt-names = "irqmux";
ranges = <0 0x09230000 0x3000>;
pio40: gpio@09230000 {
--
cgit
From 305b54750d6bd4f36535b6b80c6f5bd6fb519e40 Mon Sep 17 00:00:00 2001
From: Paweł Jarosz <paweljarosz3691@gmail.com>
Date: Fri, 14 Oct 2016 14:16:54 +0200
Subject: ARM: dts: rockchip: initialize rk3066 PLL clock rate
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Initialize PLL, cpu bus and peripherial bus rate while kernel init.
No other module does than.
This gives us performance boost observable for example in mmc transfers.
Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/boot/dts/rk3066a.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index b8c83d80593f..f3a51099f5e0 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -151,6 +151,14 @@
#clock-cells = <1>;
#reset-cells = <1>;
+ assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,
+ <&cru ACLK_CPU>, <&cru HCLK_CPU>,
+ <&cru PCLK_CPU>, <&cru ACLK_PERI>,
+ <&cru HCLK_PERI>, <&cru PCLK_PERI>;
+ assigned-clock-rates = <400000000>, <594000000>,
+ <300000000>, <150000000>,
+ <75000000>, <300000000>,
+ <150000000>, <75000000>;
};
timer@2000e000 {
--
cgit
From cbab82029c87b92c30ee1effb777c312c468fc0b Mon Sep 17 00:00:00 2001
From: Paweł Jarosz <paweljarosz3691@gmail.com>
Date: Sat, 8 Oct 2016 22:22:30 +0200
Subject: ARM: dts: rockchip: Add rk3066 MK808 board
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
MK808 is a tv stick which has rockchip rk3066 CPU inside, two usb ports
- host and otg, micro sd card slot and onboard wifi RK901.
Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
Reviewed-by: Shawn Lin <shawn.lin@rock-chip.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/rk3066a-mk808.dts | 195 ++++++++++++++++++++++++++++++++++++
2 files changed, 196 insertions(+)
create mode 100644 arch/arm/boot/dts/rk3066a-mk808.dts
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 0df336c66a44..e49476a78250 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -639,6 +639,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3036-kylin.dtb \
rk3066a-bqcurie2.dtb \
rk3066a-marsboard.dtb \
+ rk3066a-mk808.dtb \
rk3066a-rayeager.dtb \
rk3188-px3-evb.dtb \
rk3188-radxarock.dtb \
diff --git a/arch/arm/boot/dts/rk3066a-mk808.dts b/arch/arm/boot/dts/rk3066a-mk808.dts
new file mode 100644
index 000000000000..658eb7ddeaf5
--- /dev/null
+++ b/arch/arm/boot/dts/rk3066a-mk808.dts
@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2016 Paweł Jarosz <paweljarosz3691@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "rk3066a.dtsi"
+
+/ {
+ model = "Rikomagic MK808";
+ compatible = "rikomagic,mk808", "rockchip,rk3066a";
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ memory@60000000 {
+ reg = <0x60000000 0x40000000>;
+ device_type = "memory";
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ blue {
+ label = "mk808:blue:power";
+ gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "default-on";
+ };
+ };
+
+ vcc_io: vcc-io {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_io";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vcc_host: usb-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&host_drv>;
+ pinctrl-names = "default";
+ regulator-always-on;
+ regulator-name = "host-pwr";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ startup-delay-us = <100000>;
+ vin-supply = <&vcc_io>;
+ };
+
+ vcc_otg: usb-otg-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&otg_drv>;
+ pinctrl-names = "default";
+ regulator-always-on;
+ regulator-name = "vcc_otg";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ startup-delay-us = <100000>;
+ vin-supply = <&vcc_io>;
+ };
+
+ vcc_sd: sdmmc-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio3 7 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&sdmmc_pwr>;
+ pinctrl-names = "default";
+ regulator-name = "vcc_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ vin-supply = <&vcc_io>;
+ };
+
+ vcc_wifi: sdio-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio3 24 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&wifi_pwr>;
+ pinctrl-names = "default";
+ regulator-name = "vcc_wifi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ vin-supply = <&vcc_io>;
+ };
+};
+
+&mmc0 {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ num-slots = <1>;
+ vmmc-supply = <&vcc_sd>;
+ status = "okay";
+};
+
+&mmc1 {
+ bus-width = <4>;
+ disable-wp;
+ non-removable;
+ num-slots = <1>;
+ pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>;
+ pinctrl-names = "default";
+ vmmc-supply = <&vcc_wifi>;
+ status = "okay";
+};
+
+&pinctrl {
+ usb-host {
+ host_drv: host-drv {
+ rockchip,pins = <RK_GPIO0 6 RK_FUNC_GPIO &pcfg_pull_default>;
+ };
+ };
+
+ usb-otg {
+ otg_drv: otg-drv {
+ rockchip,pins = <RK_GPIO0 5 RK_FUNC_GPIO &pcfg_pull_default>;
+ };
+ };
+
+ sdmmc {
+ sdmmc_pwr: sdmmc-pwr {
+ rockchip,pins = <RK_GPIO3 7 RK_FUNC_GPIO &pcfg_pull_default>;
+ };
+ };
+
+ sdio {
+ wifi_pwr: wifi-pwr {
+ rockchip,pins = <RK_GPIO3 24 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb_host {
+ status = "okay";
+};
+
+&usb_otg {
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
+
+&wdt {
+ status = "okay";
+};
--
cgit
From c959ab8be2332aef1a13ea624a0bfa995cfa583c Mon Sep 17 00:00:00 2001
From: Andy Yan <andy.yan@rock-chips.com>
Date: Wed, 7 Sep 2016 09:02:13 +0800
Subject: ARM: dts: rockchip: use pin constants to describe gpios on
Popmetal-RK3288
Use definition in rockchip pinctrl header to describe
gpios, this will make it more clear.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/boot/dts/rk3288-popmetal.dts | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts
index 3bf1fc3ba31b..bc6d10054f6a 100644
--- a/arch/arm/boot/dts/rk3288-popmetal.dts
+++ b/arch/arm/boot/dts/rk3288-popmetal.dts
@@ -68,7 +68,7 @@
pinctrl-0 = <&pwrbtn>;
power {
- gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
label = "GPIO Key Power";
linux,input-type = <1>;
@@ -79,7 +79,7 @@
ir: ir-receiver {
compatible = "gpio-ir-receiver";
- gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&ir_int>;
};
@@ -94,7 +94,7 @@
vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";
- gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
+ gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_pwr>;
regulator-name = "vcc_sd";
@@ -128,7 +128,7 @@
vcc28_dvp: vcc28-dvp-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&dvp_pwr>;
regulator-name = "vcc28_dvp";
@@ -180,7 +180,7 @@
phy-supply = <&vcc_lan>;
phy-mode = "rgmii";
clock_in_out = "input";
- snps,reset-gpio = <&gpio4 7 0>;
+ snps,reset-gpio = <&gpio4 RK_PB0 0>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 1000000>;
assigned-clocks = <&cru SCLK_MAC>;
@@ -449,43 +449,43 @@
&pinctrl {
ak8963 {
comp_int: comp-int {
- rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_up>;
+ rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
buttons {
pwrbtn: pwrbtn {
- rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
dvp {
dvp_pwr: dvp-pwr {
- rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
ir {
ir_int: ir-int {
- rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_up>;
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
mma8452 {
gsensor_int: gsensor-int {
- rockchip,pins = <8 0 RK_FUNC_GPIO &pcfg_pull_up>;
+ rockchip,pins = <8 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
pmic {
pmic_int: pmic-int {
- rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
sdmmc {
sdmmc_pwr: sdmmc-pwr {
- rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
--
cgit
From fc48e76489fd7627457f9f8d27a683967bbf687c Mon Sep 17 00:00:00 2001
From: Sanchayan Maity <maitysanchayan@gmail.com>
Date: Wed, 21 Sep 2016 16:54:38 +0530
Subject: ARM: dts: imx6: Add support for Toradex Colibri iMX6 module
Add support for Toradex Colibri iMX6 module.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts | 253 ++++++++
arch/arm/boot/dts/imx6qdl-colibri.dtsi | 890 +++++++++++++++++++++++++++
3 files changed, 1144 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
create mode 100644 arch/arm/boot/dts/imx6qdl-colibri.dtsi
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index befcd2619902..019976b50fbf 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -330,6 +330,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-aristainetos_7.dtb \
imx6dl-aristainetos2_4.dtb \
imx6dl-aristainetos2_7.dtb \
+ imx6dl-colibri-eval-v3.dtb \
imx6dl-cubox-i.dtb \
imx6dl-dfi-fs700-m60.dtb \
imx6dl-gw51xx.dtb \
diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
new file mode 100644
index 000000000000..e0c21727866d
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
@@ -0,0 +1,253 @@
+/*
+ * Copyright 2014-2016 Toradex AG
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "imx6dl.dtsi"
+#include "imx6qdl-colibri.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6DL/S on Colibri Evaluation Board V3";
+ compatible = "toradex,colibri_imx6dl-eval-v3", "toradex,colibri_imx6dl",
+ "fsl,imx6dl";
+
+ aliases {
+ i2c0 = &i2c2;
+ i2c1 = &i2c3;
+ };
+
+ aliases {
+ rtc0 = &rtc_i2c;
+ rtc1 = &snvs_rtc;
+ };
+
+ clocks {
+ /* Fixed crystal dedicated to mcp251x */
+ clk16m: clk@1 {
+ compatible = "fixed-clock";
+ reg = <1>;
+ #clock-cells = <0>;
+ clock-frequency = <16000000>;
+ clock-output-names = "clk16m";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ wakeup {
+ label = "Wake-Up";
+ gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* SODIMM 45 */
+ linux,code = <KEY_WAKEUP>;
+ debounce-interval = <10>;
+ wakeup-source;
+ };
+ };
+
+ lcd_display: display@di0 {
+ compatible = "fsl,imx-parallel-display";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interface-pix-fmt = "bgr666";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_lcdif>;
+ status = "okay";
+
+ port@0 {
+ reg = <0>;
+
+ lcd_display_in: endpoint {
+ remote-endpoint = <&ipu1_di0_disp0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lcd_display_out: endpoint {
+ remote-endpoint = <&lcd_panel_in>;
+ };
+ };
+ };
+
+ panel: panel {
+ /*
+ * edt,et057090dhu: EDT 5.7" LCD TFT
+ * edt,et070080dh6: EDT 7.0" LCD TFT
+ */
+ compatible = "edt,et057090dhu";
+ backlight = <&backlight>;
+
+ port {
+ lcd_panel_in: endpoint {
+ remote-endpoint = <&lcd_display_out>;
+ };
+ };
+ };
+};
+
+&backlight {
+ brightness-levels = <0 127 191 223 239 247 251 255>;
+ default-brightness-level = <1>;
+ status = "okay";
+};
+
+/* Colibri SSP */
+&ecspi4 {
+ status = "okay";
+
+ mcp251x0: mcp251x@1 {
+ compatible = "microchip,mcp2515";
+ reg = <0>;
+ clocks = <&clk16m>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <27 0x2>;
+ spi-max-frequency = <10000000>;
+ status = "okay";
+ };
+};
+
+&hdmi {
+ status = "okay";
+};
+
+/*
+ * Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
+ */
+&i2c3 {
+ status = "okay";
+
+ /* M41T0M6 real time clock on carrier board */
+ rtc_i2c: rtc@68 {
+ compatible = "st,m41t00";
+ reg = <0x68>;
+ };
+};
+
+&ipu1_di0_disp0 {
+ remote-endpoint = <&lcd_display_in>;
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&pwm3 {
+ status = "okay";
+};
+
+&pwm4 {
+ status = "okay";
+};
+
+®_usb_host_vbus {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&usbh1 {
+ vbus-supply = <®_usb_host_vbus>;
+ status = "okay";
+};
+
+&usbotg {
+ status = "okay";
+};
+
+/* Colibri MMC */
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mmc_cd>;
+ cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */
+ status = "okay";
+};
+
+&weim {
+ status = "okay";
+
+ /* weim memory map: 32MB on CS0, 32MB on CS1, 32MB on CS2 */
+ ranges = <0 0 0x08000000 0x02000000
+ 1 0 0x0a000000 0x02000000
+ 2 0 0x0c000000 0x02000000>;
+
+ /* SRAM on Colibri nEXT_CS0 */
+ sram@0,0 {
+ compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram";
+ reg = <0 0 0x00010000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bank-width = <2>;
+ fsl,weim-cs-timing = <0x00010081 0x00000000 0x04000000
+ 0x00000000 0x04000040 0x00000000>;
+ };
+
+ /* SRAM on Colibri nEXT_CS1 */
+ sram@1,0 {
+ compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram";
+ reg = <1 0 0x00010000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bank-width = <2>;
+ fsl,weim-cs-timing = <0x00010081 0x00000000 0x04000000
+ 0x00000000 0x04000040 0x00000000>;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
new file mode 100644
index 000000000000..e6faa653f91a
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
@@ -0,0 +1,890 @@
+/*
+ * Copyright 2014-2016 Toradex AG
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Toradex Colibri iMX6DL/S Module";
+ compatible = "toradex,colibri_imx6dl", "fsl,imx6dl";
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_bl_on>;
+ pwms = <&pwm3 0 5000000>;
+ enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */
+ status = "disabled";
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "1P8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ reg_2p5v: regulator-2p5v {
+ compatible = "regulator-fixed";
+ regulator-name = "2P5V";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_usb_host_vbus: regulator-usb-host-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
+ regulator-name = "usb_host_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */
+ status = "disabled";
+ };
+
+ sound {
+ compatible = "fsl,imx-audio-sgtl5000";
+ model = "imx6dl-colibri-sgtl5000";
+ ssi-controller = <&ssi1>;
+ audio-codec = <&codec>;
+ audio-routing =
+ "Headphone Jack", "HP_OUT",
+ "LINE_IN", "Line In Jack",
+ "MIC_IN", "Mic Jack",
+ "Mic Jack", "Mic Bias";
+ mux-int-port = <1>;
+ mux-ext-port = <5>;
+ };
+
+ /* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */
+ sound_spdif: sound-spdif {
+ compatible = "fsl,imx-audio-spdif";
+ model = "imx-spdif";
+ spdif-controller = <&spdif>;
+ spdif-in;
+ spdif-out;
+ status = "disabled";
+ };
+};
+
+&audmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux &pinctrl_mic_gnd>;
+ status = "okay";
+};
+
+/* Optional on SODIMM 55/63 */
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ status = "disabled";
+};
+
+/* Optional on SODIMM 178/188 */
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ status = "disabled";
+};
+
+/* Colibri SSP */
+&ecspi4 {
+ fsl,spi-num-chipselects = <1>;
+ cs-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi4>;
+ status = "disabled";
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rmii";
+ status = "okay";
+};
+
+&hdmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hdmi_ddc>;
+ status = "disabled";
+};
+
+/*
+ * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
+ * touch screen controller
+ */
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ pmic: pfuze100@08 {
+ compatible = "fsl,pfuze100";
+ reg = <0x08>;
+
+ regulators {
+ sw1a_reg: sw1ab {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw1c_reg: sw1c {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw3a_reg: sw3a {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vgen1: unused */
+
+ vgen2_reg: vgen2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vgen3: unused */
+
+ vgen4_reg: vgen4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen5_reg: vgen5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen6_reg: vgen6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+
+ codec: sgtl5000@0a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ clocks = <&clks IMX6QDL_CLK_CKO>;
+ VDDA-supply = <®_2p5v>;
+ VDDIO-supply = <®_3p3v>;
+ };
+
+ /* STMPE811 touch screen controller */
+ stmpe811@41 {
+ compatible = "st,stmpe811";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_touch_int>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x41>;
+ interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio6>;
+ interrupt-controller;
+ id = <0>;
+ blocks = <0x5>;
+ irq-trigger = <0x1>;
+
+ stmpe_touchscreen {
+ compatible = "st,stmpe-ts";
+ reg = <0>;
+ /* 3.25 MHz ADC clock speed */
+ st,adc-freq = <1>;
+ /* 8 sample average control */
+ st,ave-ctrl = <3>;
+ /* 7 length fractional part in z */
+ st,fraction-z = <7>;
+ /*
+ * 50 mA typical 80 mA max touchscreen drivers
+ * current limit value
+ */
+ st,i-drive = <1>;
+ /* 12-bit ADC */
+ st,mod-12b = <1>;
+ /* internal ADC reference */
+ st,ref-sel = <0>;
+ /* ADC converstion time: 80 clocks */
+ st,sample-time = <4>;
+ /* 1 ms panel driver settling time */
+ st,settling = <3>;
+ /* 5 ms touch detect interrupt delay */
+ st,touch-det-delay = <5>;
+ };
+ };
+};
+
+/*
+ * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
+ */
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "recovery";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_recovery>;
+ scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+};
+
+/* Colibri PWM<B> */
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "disabled";
+};
+
+/* Colibri PWM<D> */
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>;
+ status = "disabled";
+};
+
+/* Colibri PWM<A> */
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>;
+ status = "disabled";
+};
+
+/* Colibri PWM<C> */
+&pwm4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm4>;
+ status = "disabled";
+};
+
+/* Optional S/PDIF out on SODIMM 137 */
+&spdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spdif>;
+ status = "disabled";
+};
+
+&ssi1 {
+ status = "okay";
+};
+
+/* Colibri UART_A */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
+ fsl,dte-mode;
+ uart-has-rtscts;
+ status = "disabled";
+};
+
+/* Colibri UART_B */
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2_dte>;
+ fsl,dte-mode;
+ uart-has-rtscts;
+ status = "disabled";
+};
+
+/* Colibri UART_C */
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3_dte>;
+ fsl,dte-mode;
+ status = "disabled";
+};
+
+&usbotg {
+ pinctrl-names = "default";
+ disable-over-current;
+ dr_mode = "peripheral";
+ status = "disabled";
+};
+
+/* Colibri MMC */
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ vqmmc-supply = <®_3p3v>;
+ bus-width = <4>;
+ voltage-ranges = <3300 3300>;
+ status = "disabled";
+};
+
+/* eMMC */
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ vqmmc-supply = <®_3p3v>;
+ bus-width = <8>;
+ voltage-ranges = <3300 3300>;
+ non-removable;
+ status = "okay";
+};
+
+&weim {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_weim_sram &pinctrl_weim_cs0
+ &pinctrl_weim_cs1 &pinctrl_weim_cs2
+ &pinctrl_weim_rdnwr &pinctrl_weim_npwe>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ status = "disabled";
+};
+
+&iomuxc {
+ pinctrl_audmux: audmuxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
+ MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0
+ MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
+ MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0
+ /* SGTL5000 sys_mclk */
+ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0
+ >;
+ };
+
+ pinctrl_cam_mclk: cammclkgrp {
+ fsl,pins = <
+ /* Parallel Camera CAM sys_mclk */
+ MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0
+ >;
+ };
+
+ pinctrl_ecspi4: ecspi4grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
+ MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
+ MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
+ /* SPI CS */
+ MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1
+ >;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
+ MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
+ MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
+ MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
+ MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
+ MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
+ MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0)
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
+ MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
+ MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
+ >;
+ };
+
+ pinctrl_gpio_bl_on: gpioblon {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0
+ >;
+ };
+
+ pinctrl_gpio_keys: gpiokeys {
+ fsl,pins = <
+ /* Power button */
+ MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0
+ >;
+ };
+
+ pinctrl_hdmi_ddc: hdmiddcgrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3_recovery: i2c3recoverygrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
+ >;
+ };
+
+ pinctrl_ipu1_csi0: ipu1csi0grp { /* Parallel Camera */
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0xb0b1
+ MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0xb0b1
+ MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0xb0b1
+ MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0xb0b1
+ MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0xb0b1
+ MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0xb0b1
+ MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0xb0b1
+ MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0xb0b1
+ MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0xb0b1
+ MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0xb0b1
+ MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0xb0b1
+ /* Disable PWM pins on camera interface */
+ MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40
+ MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x40
+ >;
+ };
+
+ pinctrl_ipu1_lcdif: ipu1lcdifgrp {
+ fsl,pins = <
+ MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xa1
+ MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xa1
+ MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0xa1
+ MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0xa1
+ MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xa1
+ MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xa1
+ MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xa1
+ MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xa1
+ MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xa1
+ MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xa1
+ MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xa1
+ MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xa1
+ MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xa1
+ MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xa1
+ MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xa1
+ MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xa1
+ MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xa1
+ MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xa1
+ MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xa1
+ MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xa1
+ MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xa1
+ MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xa1
+ >;
+ };
+
+ pinctrl_mic_gnd: gpiomicgnd {
+ fsl,pins = <
+ /* Controls Mic GND, PU or '1' pull Mic GND to GND */
+ MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0
+ >;
+ };
+
+ pinctrl_mmc_cd: gpiommccd {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x80000000
+ >;
+ };
+
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
+ MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x00040
+ >;
+ };
+
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
+ MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x00040
+ >;
+ };
+
+ pinctrl_pwm4: pwm4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
+ fsl,pins = <
+ /* USBH_EN */
+ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0f058
+ >;
+ };
+
+ pinctrl_spdif: spdifgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
+ >;
+ };
+
+ pinctrl_touch_int: gpiotouchintgrp {
+ fsl,pins = <
+ /* STMPE811 interrupt */
+ MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x1b0b0
+ >;
+ };
+
+ pinctrl_uart1_dce: uart1dcegrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
+ >;
+ };
+
+ /* DTE mode */
+ pinctrl_uart1_dte: uart1dtegrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
+ MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
+ >;
+ };
+
+ /* Additional DTR, DSR, DCD */
+ pinctrl_uart1_ctrl: uart1ctrlgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
+ MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
+ MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
+ >;
+ };
+
+ pinctrl_uart2_dte: uart2dtegrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1
+ MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1
+ MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart3_dte: uart3dtegrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbc_det: usbcdetgrp {
+ fsl,pins = <
+ /* USBC_DET */
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
+ /* USBC_DET_EN */
+ MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x0f058
+ /* USBC_DET_OVERWRITE */
+ MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x0f058
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+ /* eMMC reset */
+ MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3100mhzgrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
+ /* eMMC reset */
+ MX6QDL_PAD_SD3_RST__SD3_RESET 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3200mhzgrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
+ /* eMMC reset */
+ MX6QDL_PAD_SD3_RST__SD3_RESET 0x170f9
+ >;
+ };
+
+ pinctrl_weim_cs0: weimcs0grp {
+ fsl,pins = <
+ /* nEXT_CS0 */
+ MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
+ >;
+ };
+
+ pinctrl_weim_cs1: weimcs1grp {
+ fsl,pins = <
+ /* nEXT_CS1 */
+ MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1
+ >;
+ };
+
+ pinctrl_weim_cs2: weimcs2grp {
+ fsl,pins = <
+ /* nEXT_CS2 */
+ MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0xb0b1
+ >;
+ };
+
+ pinctrl_weim_sram: weimsramgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
+ MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
+ /* Data */
+ MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0
+ MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0
+ /* Address */
+ MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
+ MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
+ MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
+ MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
+ MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
+ MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
+ MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
+ MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
+ MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
+ MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
+ MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
+ MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
+ MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
+ MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
+ MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
+ MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
+ >;
+ };
+
+ pinctrl_weim_rdnwr: weimrdnwr {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0040
+ MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x130b0
+ >;
+ };
+
+ pinctrl_weim_npwe: weimnpwe {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x0040
+ MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x130b0
+ >;
+ };
+
+ /* ADDRESS[16:18] [25] used as GPIO */
+ pinctrl_weim_gpio_1: weimgpio-1 {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
+ MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
+ MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
+ MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
+ MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0
+ MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0
+ MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
+ MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0
+ MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0
+ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
+ >;
+ };
+
+ /* ADDRESS[19:24] used as GPIO */
+ pinctrl_weim_gpio_2: weimgpio-2 {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
+ MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
+ MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
+ MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0
+ MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0
+ MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
+ MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0
+ MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0
+ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
+ >;
+ };
+
+ /* DATA[16:31] used as GPIO */
+ pinctrl_weim_gpio_3: weimgpio-3 {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0
+ MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
+ MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0
+ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0
+ MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0
+ MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0
+ MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0
+ MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0
+ MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
+ MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
+ MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0
+ MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
+ MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
+ >;
+ };
+
+ /* DQM[0:3] used as GPIO */
+ pinctrl_weim_gpio_4: weimgpio-4 {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0
+ MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0
+ MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0
+ MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
+ >;
+ };
+
+ /* RDY used as GPIO */
+ pinctrl_weim_gpio_5: weimgpio-5 {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0
+ >;
+ };
+
+ /* ADDRESS[16] DATA[30] used as GPIO */
+ pinctrl_weim_gpio_6: weimgpio-6 {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
+ MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0
+ >;
+ };
+};
--
cgit
From aacf62465acac596a323c193ca49e06418498c98 Mon Sep 17 00:00:00 2001
From: Sanchayan Maity <maitysanchayan@gmail.com>
Date: Mon, 19 Sep 2016 10:41:52 +0530
Subject: ARM: dts: imx6q-apalis-ixora: Remove use of pwm-leds
Remove use of pwm-leds and use the standard /sys/class/pwm
interface from PWM subsystem.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/imx6q-apalis-ixora.dts | 22 ----------------------
1 file changed, 22 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora.dts b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
index 207b85b91ada..0ea75f7b6039 100644
--- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts
+++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
@@ -147,28 +147,6 @@
gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
};
};
-
- pwmleds {
- compatible = "pwm-leds";
-
- ledpwm1 {
- label = "PWM1";
- pwms = <&pwm1 0 50000>;
- max-brightness = <255>;
- };
-
- ledpwm2 {
- label = "PWM2";
- pwms = <&pwm2 0 50000>;
- max-brightness = <255>;
- };
-
- ledpwm3 {
- label = "PWM3";
- pwms = <&pwm3 0 50000>;
- max-brightness = <255>;
- };
- };
};
&backlight {
--
cgit
From ebedca04ec6fe9805f5824093b60c7a94478cb1f Mon Sep 17 00:00:00 2001
From: Sanchayan Maity <maitysanchayan@gmail.com>
Date: Mon, 19 Sep 2016 10:41:53 +0530
Subject: ARM: dts: imx6qdl-apalis: Use enable-gpios property for backlight
Use enable-gpios property of PWM backlight driver for backlight
control.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/imx6qdl-apalis.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
index 99e323b57261..8c8a049eb3d0 100644
--- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
@@ -49,7 +49,10 @@
backlight: backlight {
compatible = "pwm-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_bl_on>;
pwms = <&pwm4 0 5000000>;
+ enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
@@ -620,6 +623,12 @@
>;
};
+ pinctrl_gpio_bl_on: gpioblon {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0
+ >;
+ };
+
pinctrl_gpio_keys: gpio1io04grp {
fsl,pins = <
/* Power button */
--
cgit
From 371a8dd6fa75ef3682bd8398c3e32b354d0e2677 Mon Sep 17 00:00:00 2001
From: Jaret Cantu <jaret.cantu@timesys.com>
Date: Wed, 14 Sep 2016 17:14:49 -0400
Subject: ARM: dts: imx: b650v3: Calibrate USB PHY to pass eye diagram test
Calibrate the USB PHY TX settings to pass the eye diagram signal
integrity test. The settings are taken from the i.MX6 reference
manual's recommended configuration for USB certification (66.2.6).
Signed-off-by: Jaret Cantu <jaret.cantu@timesys.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/imx6q-b650v3.dts | 6 ++++++
1 file changed, 6 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/imx6q-b650v3.dts b/arch/arm/boot/dts/imx6q-b650v3.dts
index d85388725426..1dcaee23ed9c 100644
--- a/arch/arm/boot/dts/imx6q-b650v3.dts
+++ b/arch/arm/boot/dts/imx6q-b650v3.dts
@@ -98,3 +98,9 @@
line-name = "PCA9539-P05";
};
};
+
+&usbphy1 {
+ fsl,tx-cal-45-dn-ohms = <55>;
+ fsl,tx-cal-45-dp-ohms = <55>;
+ fsl,tx-d-cal = <100>;
+};
--
cgit
From 05c183e44be769d4e0942f0f5b210ee42d39da0d Mon Sep 17 00:00:00 2001
From: Jagan Teki <jteki@openedev.com>
Date: Fri, 14 Oct 2016 15:09:28 +0530
Subject: ARM: dts: imx6qdl: Fix "WARNING: please, no space before tabs"
Fixed no space before tabs warnings in respetcive imx6qdl dtsi files.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/imx6qdl-apf6dev.dtsi | 14 +++++++-------
arch/arm/boot/dts/imx6qdl-tx6.dtsi | 32 ++++++++++++++++----------------
arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 4 ++--
3 files changed, 25 insertions(+), 25 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi b/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
index edbce222c782..5e7792d6bf58 100644
--- a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
@@ -347,13 +347,13 @@
fsl,pins = <
MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x100b1
MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1
- MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x100b1
- MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x100b1
- MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x100b1
- MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x100b1
- MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x100b1
- MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x100b1
- MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x100b1
+ MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x100b1
+ MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x100b1
+ MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x100b1
+ MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x100b1
+ MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x100b1
+ MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x100b1
+ MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x100b1
>;
};
diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi
index ac9529f85593..2bf2e623ac1e 100644
--- a/arch/arm/boot/dts/imx6qdl-tx6.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-tx6.dtsi
@@ -429,8 +429,8 @@
pinctrl_edt_ft5x06: edt-ft5x06grp {
fsl,pins = <
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Interrupt */
- MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */
- MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */
+ MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */
+ MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */
>;
};
@@ -481,21 +481,21 @@
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1
- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1
- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1
+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1
+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1
+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000
- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1
- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1
- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1
- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1
- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1
- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1
- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1
- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1
- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1
- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1
- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1
+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1
+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1
+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1
+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1
+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1
+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1
+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1
+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1
+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1
+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1
+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1
>;
};
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
index 2b9c2be436f9..82dc5744ae19 100644
--- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
@@ -129,8 +129,8 @@
pinctrl_i2c1: i2c1grp {
fsl,pins = <
- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
--
cgit
From bf5393c5ec9caf042f6121c3e1c5541f47fedf57 Mon Sep 17 00:00:00 2001
From: Jagan Teki <jteki@openedev.com>
Date: Fri, 14 Oct 2016 15:09:29 +0530
Subject: ARM: dts: imx6qdl: Fix "ERROR: code indent should use tabs where
possible"
Fixed code indent tabs in respetcive imx6qdl dtsi files.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | 4 ++--
arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 4 ++--
arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 4 ++--
arch/arm/boot/dts/imx6qdl-gw552x.dtsi | 2 +-
arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 6 +++---
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 2 +-
arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 4 ++--
arch/arm/boot/dts/imx6qdl.dtsi | 6 +++---
8 files changed, 16 insertions(+), 16 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
index a7100f99123e..54aca3a07ce4 100644
--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
@@ -153,9 +153,9 @@
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
- <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
- <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
};
&ecspi3 {
diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
index 8953eba0573d..88e5cb3b6be9 100644
--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
@@ -154,9 +154,9 @@
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
- <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
- <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
};
&fec {
diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
index 6ac41c7ed32e..1753ab720b0b 100644
--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
@@ -144,9 +144,9 @@
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
- <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
- <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
};
&fec {
diff --git a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
index 805e23674a94..ee83161f674b 100644
--- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
@@ -291,7 +291,7 @@
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
>;
- };
+ };
pinctrl_wdog: wdoggrp {
fsl,pins = <
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
index e0280cac2484..e9801a26f3b4 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
@@ -427,10 +427,10 @@
};
&usdhc3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc3
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3
&pinctrl_usdhc3_cdwp>;
cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
- status = "disabled";
+ status = "disabled";
};
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index e000e6f12bf5..80064678ba3c 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -283,7 +283,7 @@
VD-supply = <®_audio>;
VLS-supply = <®_audio>;
VLC-supply = <®_audio>;
- };
+ };
};
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index 8e9e0d98db2f..55ef53571fdd 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -129,8 +129,8 @@
pinctrl-0 = <&pinctrl_gpio_leds>;
red {
- gpios = <&gpio1 2 0>;
- default-state = "on";
+ gpios = <&gpio1 2 0>;
+ default-state = "on";
};
};
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index b13b0b2db881..1bbd36f40424 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -204,9 +204,9 @@
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
<&clks IMX6QDL_CLK_LVDS1_GATE>,
<&clks IMX6QDL_CLK_PCIE_REF_125M>;
--
cgit
From 49bc67b61c608be5ce3aeb8246cd47b2390ff0bb Mon Sep 17 00:00:00 2001
From: Jagan Teki <jteki@openedev.com>
Date: Fri, 14 Oct 2016 15:09:30 +0530
Subject: ARM: dts: imx6qdl-wandboard-revb: Fix "ERROR: trailing whitespace"
Fixed error in trailing whitespace in wandboard-rev1 dtsi.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi
index ef7fa62b9898..a32089132263 100644
--- a/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi
@@ -28,7 +28,7 @@
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 /* RGMII_nRST */
MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x80000000 /* BT_ON */
MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x80000000 /* BT_WAKE */
- MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x80000000 /* BT_HOST_WAKE */
+ MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x80000000 /* BT_HOST_WAKE */
>;
};
};
--
cgit
From 227802b18dfa31830552f137bdd95f5e5fe0fa13 Mon Sep 17 00:00:00 2001
From: Andrey Smirnov <andrew.smirnov@gmail.com>
Date: Sat, 1 Oct 2016 18:28:39 -0700
Subject: ARM: dts: vf610-zii-dev-rev-b: Remove I2C3
I2C3 bus was only brought out in revision A1 of the board and revision
B1 only brings out 3 I2C busses (I2C0, I2C1 and I2C2).
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/vf610-zii-dev-rev-b.dts | 14 --------------
1 file changed, 14 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
index 5c1fcab4a6f7..fa19cfdc33fb 100644
--- a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
+++ b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
@@ -499,13 +499,6 @@
};
};
-&i2c3 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- status = "okay";
-};
-
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
@@ -663,13 +656,6 @@
>;
};
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- VF610_PAD_PTA30__I2C3_SCL 0x37ff
- VF610_PAD_PTA31__I2C3_SDA 0x37ff
- >;
- };
-
pinctrl_leds_debug: pinctrl-leds-debug {
fsl,pins = <
VF610_PAD_PTD20__GPIO_74 0x31c2
--
cgit
From fa8d20c8dbb772dbdd930817f83949d95f733e8e Mon Sep 17 00:00:00 2001
From: Andrey Smirnov <andrew.smirnov@gmail.com>
Date: Sat, 1 Oct 2016 18:30:22 -0700
Subject: ARM: dts: vfxxx: Add node corresponding to OCOTP
Add node corresponding to OCOTP IP block.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/vfxxx.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
index 2c13ec696ac5..75850c033545 100644
--- a/arch/arm/boot/dts/vfxxx.dtsi
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -520,6 +520,12 @@
status = "disabled";
};
+ ocotp: ocotp@400a5000 {
+ compatible = "fsl,vf610-ocotp";
+ reg = <0x400a5000 0x1000>;
+ clocks = <&clks VF610_CLK_OCOTP>;
+ };
+
snvs0: snvs@400a7000 {
compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
reg = <0x400a7000 0x2000>;
--
cgit
From f7f3b484d5505b9a8f09d9db6a2ec172d7f49e0f Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Sun, 2 Oct 2016 18:44:35 +0200
Subject: ARM: dts: imx6sx: Fix LCDIF interrupt type
The LCDIF interrupt should be triggered by the rising edge of the
IRQ line because we only want the interrupt to trigger once per each
frame. It seems the LCDIF IRQ line cannot be explicitly de-asserted
by software, so the previous behavior before this patch, where the
interrupt was triggered by level-high status of the IRQ line, caused
the interrupt to fire again immediatelly after it was handled, which
caused the system to lock up due to the high rate of interrupts.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/imx6sx.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 1a473e83efbf..9526c3854b28 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -1143,7 +1143,7 @@
lcdif1: lcdif@02220000 {
compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
reg = <0x02220000 0x4000>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>;
clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
<&clks IMX6SX_CLK_LCDIF_APB>,
<&clks IMX6SX_CLK_DISPLAY_AXI>;
@@ -1154,7 +1154,7 @@
lcdif2: lcdif@02224000 {
compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
reg = <0x02224000 0x4000>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>;
clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
<&clks IMX6SX_CLK_LCDIF_APB>,
<&clks IMX6SX_CLK_DISPLAY_AXI>;
--
cgit
From 14c4163368206bfe0163e2e8fe58fec93bbc305d Mon Sep 17 00:00:00 2001
From: Sanchayan Maity <maitysanchayan@gmail.com>
Date: Mon, 3 Oct 2016 18:20:37 +0530
Subject: ARM: dts: vfxxx: Enable DMA for DSPI on Vybrid
Enable DMA for DSPI on Vybrid.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/vf-colibri.dtsi | 4 ++++
arch/arm/boot/dts/vfxxx.dtsi | 6 ++++++
2 files changed, 10 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/vf-colibri.dtsi b/arch/arm/boot/dts/vf-colibri.dtsi
index b7417094dc11..21bfef957b68 100644
--- a/arch/arm/boot/dts/vf-colibri.dtsi
+++ b/arch/arm/boot/dts/vf-colibri.dtsi
@@ -108,6 +108,10 @@
status = "okay";
};
+&edma1 {
+ status = "okay";
+};
+
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>;
diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
index 75850c033545..000550f7b9dd 100644
--- a/arch/arm/boot/dts/vfxxx.dtsi
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -194,6 +194,9 @@
clocks = <&clks VF610_CLK_DSPI0>;
clock-names = "dspi";
spi-num-chipselects = <6>;
+ dmas = <&edma1 1 12>,
+ <&edma1 1 13>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -206,6 +209,9 @@
clocks = <&clks VF610_CLK_DSPI1>;
clock-names = "dspi";
spi-num-chipselects = <4>;
+ dmas = <&edma1 1 14>,
+ <&edma1 1 15>;
+ dma-names = "rx", "tx";
status = "disabled";
};
--
cgit
From 4d9e9cbb61fdf8d037e5ad95ed03c414073b1443 Mon Sep 17 00:00:00 2001
From: Hongtao Jia <hongtao.jia@nxp.com>
Date: Sun, 9 Oct 2016 14:47:04 +0800
Subject: ARM: dts: ls1021a: Add TMU device tree support for LS1021A
Also add nodes and properties for thermal management support.
Signed-off-by: Jia Hongtao <hongtao.jia@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/ls1021a.dtsi | 84 +++++++++++++++++++++++++++++++++++++++++-
1 file changed, 82 insertions(+), 2 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 368e21934285..282d854f4342 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -47,6 +47,7 @@
#include "skeleton64.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "fsl,ls1021a";
@@ -70,14 +71,15 @@
#address-cells = <1>;
#size-cells = <0>;
- cpu@f00 {
+ cpu0: cpu@f00 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf00>;
clocks = <&cluster1_clk>;
+ #cooling-cells = <2>;
};
- cpu@f01 {
+ cpu1: cpu@f01 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf01>;
@@ -251,6 +253,84 @@
};
};
+ tmu: tmu@1f00000 {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0x0 0x1f00000 0x0 0x10000>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x30061>;
+ fsl,tmu-calibration = <0x00000000 0x0000000f
+ 0x00000001 0x00000017
+ 0x00000002 0x0000001e
+ 0x00000003 0x00000026
+ 0x00000004 0x0000002e
+ 0x00000005 0x00000035
+ 0x00000006 0x0000003d
+ 0x00000007 0x00000044
+ 0x00000008 0x0000004c
+ 0x00000009 0x00000053
+ 0x0000000a 0x0000005b
+ 0x0000000b 0x00000064
+
+ 0x00010000 0x00000011
+ 0x00010001 0x0000001c
+ 0x00010002 0x00000024
+ 0x00010003 0x0000002b
+ 0x00010004 0x00000034
+ 0x00010005 0x00000039
+ 0x00010006 0x00000042
+ 0x00010007 0x0000004c
+ 0x00010008 0x00000051
+ 0x00010009 0x0000005a
+ 0x0001000a 0x00000063
+
+ 0x00020000 0x00000013
+ 0x00020001 0x00000019
+ 0x00020002 0x00000024
+ 0x00020003 0x0000002c
+ 0x00020004 0x00000035
+ 0x00020005 0x0000003d
+ 0x00020006 0x00000046
+ 0x00020007 0x00000050
+ 0x00020008 0x00000059
+
+ 0x00030000 0x00000002
+ 0x00030001 0x0000000d
+ 0x00030002 0x00000019
+ 0x00030003 0x00000024>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+
+ thermal-sensors = <&tmu 0>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_crit: cpu-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
dspi0: dspi@2100000 {
compatible = "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;
--
cgit
From 76e691fc7653b85d390e58710e5c7db73ca49367 Mon Sep 17 00:00:00 2001
From: Andreas Färber <afaerber@suse.de>
Date: Sun, 16 Oct 2016 16:44:23 +0200
Subject: ARM: dts: imx6sx: Add UDOO Neo support
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Add initial device trees for UDOO Neo Basic, Extended and Full boards:
* Serial console is enabled, other serial ports are prepared.
* I2C based PMIC is enabled.
* Ethernet is enabled for Basic and Full.
* SDHC is enabled, with the SDIO_PWR GPIO modeled as a regulator.
* Both user LEDs are enabled, with the orange one reserved for the M4
and with the SD card as default trigger for the red LED.
The decision on a board compatible string is deferred to later.
Cc: Ettore Chimenti <ettore.chimenti@udoo.org>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/Makefile | 5 +-
arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts | 69 ++++++
arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts | 54 +++++
arch/arm/boot/dts/imx6sx-udoo-neo-full.dts | 69 ++++++
arch/arm/boot/dts/imx6sx-udoo-neo.dtsi | 293 +++++++++++++++++++++++++
5 files changed, 489 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts
create mode 100644 arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts
create mode 100644 arch/arm/boot/dts/imx6sx-udoo-neo-full.dts
create mode 100644 arch/arm/boot/dts/imx6sx-udoo-neo.dtsi
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 019976b50fbf..da0197dfc284 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -417,7 +417,10 @@ dtb-$(CONFIG_SOC_IMX6SX) += \
imx6sx-sabreauto.dtb \
imx6sx-sdb-reva.dtb \
imx6sx-sdb-sai.dtb \
- imx6sx-sdb.dtb
+ imx6sx-sdb.dtb \
+ imx6sx-udoo-neo-basic.dtb \
+ imx6sx-udoo-neo-extended.dtb \
+ imx6sx-udoo-neo-full.dtb
dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-14x14-evk.dtb \
imx6ul-geam-kit.dtb \
diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts b/arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts
new file mode 100644
index 000000000000..0b888789efc6
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2016 Andreas Färber
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6sx-udoo-neo.dtsi"
+
+/ {
+ model = "UDOO Neo Basic";
+ compatible = "fsl,imx6sx";
+
+ memory {
+ reg = <0x80000000 0x20000000>;
+ };
+};
+
+&fec1 {
+ phy-handle = <ðphy1>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts b/arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts
new file mode 100644
index 000000000000..d6fdd17cd3ac
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2016 Andreas Färber
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6sx-udoo-neo.dtsi"
+
+/ {
+ model = "UDOO Neo Extended";
+ compatible = "fsl,imx6sx";
+
+ memory {
+ reg = <0x80000000 0x40000000>;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo-full.dts b/arch/arm/boot/dts/imx6sx-udoo-neo-full.dts
new file mode 100644
index 000000000000..d8c3577c9dd5
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sx-udoo-neo-full.dts
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2016 Andreas Färber
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6sx-udoo-neo.dtsi"
+
+/ {
+ model = "UDOO Neo Full";
+ compatible = "fsl,imx6sx";
+
+ memory {
+ reg = <0x80000000 0x40000000>;
+ };
+};
+
+&fec1 {
+ phy-handle = <ðphy1>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi b/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi
new file mode 100644
index 000000000000..2b65d26f4396
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi
@@ -0,0 +1,293 @@
+/*
+ * Copyright (c) 2016 Andreas Färber
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "imx6sx.dtsi"
+
+/ {
+ compatible = "fsl,imx6sx";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ red {
+ label = "udoo-neo:red:mmc";
+ gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "mmc0";
+ };
+
+ orange {
+ label = "udoo-neo:orange:user";
+ gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>;
+ default-state = "keep";
+ };
+ };
+
+ reg_sdio_pwr: regulator-sdio-pwr {
+ compatible = "regulator-fixed";
+ gpio = <&gpio6 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-name = "SDIO_PWR";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ };
+};
+
+&cpu0 {
+ arm-supply = <&sw1a_reg>;
+ soc-supply = <&sw1c_reg>;
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ phy-mode = "rmii";
+ phy-reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clock-frequency = <100000>;
+ status = "okay";
+
+ pmic: pmic@08 {
+ compatible = "fsl,pfuze3000";
+ reg = <0x08>;
+
+ regulators {
+ sw1a_reg: sw1a {
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1475000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw1c_reg: sw1b {
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1475000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw2_reg: sw2 {
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3a_reg: sw3 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1650000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ };
+
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen1_reg: vldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen2_reg: vldo2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ vgen3_reg: vccsd {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen4_reg: v33 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen5_reg: vldo3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen6_reg: vldo4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&iomuxc {
+ pinctrl_enet1: enet1grp {
+ fsl,pins =
+ <MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0xa0b1>,
+ <MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1>,
+ <MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1>,
+ <MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1>,
+ <MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1>,
+ <MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1>,
+
+ <MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x3081>,
+ <MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x3081>,
+ <MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081>,
+ <MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081>,
+ <MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081>,
+ <MX6SX_PAD_RGMII1_RXC__ENET1_RX_ER 0x3081>,
+
+ <MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91>;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins =
+ <MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1>,
+ <MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1>;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins =
+ <MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1>,
+ <MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1>;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins =
+ <MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1>,
+ <MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1>;
+ };
+
+ pinctrl_uart5: uart5grp {
+ fsl,pins =
+ <MX6SX_PAD_SD4_DATA4__UART5_RX 0x1b0b1>,
+ <MX6SX_PAD_SD4_DATA5__UART5_TX 0x1b0b1>;
+ };
+
+ pinctrl_uart6: uart6grp {
+ fsl,pins =
+ <MX6SX_PAD_CSI_DATA00__UART6_RI_B 0x1b0b1>,
+ <MX6SX_PAD_CSI_DATA01__UART6_DSR_B 0x1b0b1>,
+ <MX6SX_PAD_CSI_DATA02__UART6_DTR_B 0x1b0b1>,
+ <MX6SX_PAD_CSI_DATA03__UART6_DCD_B 0x1b0b1>,
+ <MX6SX_PAD_CSI_DATA04__UART6_RX 0x1b0b1>,
+ <MX6SX_PAD_CSI_DATA05__UART6_TX 0x1b0b1>,
+ <MX6SX_PAD_CSI_DATA06__UART6_RTS_B 0x1b0b1>,
+ <MX6SX_PAD_CSI_DATA07__UART6_CTS_B 0x1b0b1>;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins =
+ <MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059>,
+ <MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059>,
+ <MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059>,
+ <MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059>,
+ <MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059>,
+ <MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059>,
+ <MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x17059>; /* CD */
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+/* Cortex-M4 serial */
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "disabled";
+};
+
+/* Arduino serial */
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>;
+ status = "disabled";
+};
+
+&uart6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart6>;
+ uart-has-rtscts;
+ status = "disabled";
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ vmmc-supply = <®_sdio_pwr>;
+ bus-width = <4>;
+ cd-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ keep-power-in-suspend;
+ wakeup-source;
+ status = "okay";
+};
--
cgit
From 95a36c119781c55795099c3f5eba0a8b42f8e965 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Mon, 17 Oct 2016 18:34:49 +0200
Subject: ARM: dts: novena: Enable PWM1
Enable PWM1, otherwise the backlight cannot work.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/imx6q-novena.dts | 4 ++++
1 file changed, 4 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/imx6q-novena.dts b/arch/arm/boot/dts/imx6q-novena.dts
index 1723e89e3acc..758bca96786f 100644
--- a/arch/arm/boot/dts/imx6q-novena.dts
+++ b/arch/arm/boot/dts/imx6q-novena.dts
@@ -451,6 +451,10 @@
status = "okay";
};
+&pwm1 {
+ status = "okay";
+};
+
&sata {
target-supply = <®_sata>;
fsl,transmit-level-mV = <1025>;
--
cgit
From 1317efa1699ffd7d733d7014e7e10b5bde4a8764 Mon Sep 17 00:00:00 2001
From: Marcin Niestroj <m.niestroj@grinn-global.com>
Date: Fri, 21 Oct 2016 17:07:16 +0200
Subject: ARM: dts: imx6ul: Add DTS for liteSOM module
This is a SOM (System on Module), so it will be part of another boards.
Hence, this is a "dtsi" file that will be included from another device
tree files.
Hardware specification:
* Freescale i.MX6UL SoC
* up to 512 MB RAM
* eMMC on uSDHC2
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/imx6ul-litesom.dtsi | 82 +++++++++++++++++++++++++++++++++++
1 file changed, 82 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6ul-litesom.dtsi
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/imx6ul-litesom.dtsi b/arch/arm/boot/dts/imx6ul-litesom.dtsi
new file mode 100644
index 000000000000..461292d33417
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-litesom.dtsi
@@ -0,0 +1,82 @@
+/*
+ * Copyright 2016 Grinn
+ *
+ * Author: Marcin Niestroj <m.niestroj@grinn-global.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "imx6ul.dtsi"
+
+/ {
+ model = "Grinn i.MX6UL liteSOM";
+ compatible = "grinn,imx6ul-litesom", "fsl,imx6ul";
+
+ memory {
+ reg = <0x80000000 0x20000000>;
+ };
+};
+
+&iomuxc {
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
+ MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17059
+ >;
+ };
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ no-1-8-v;
+ non-removable;
+ keep-power-in-suspend;
+ wakeup-source;
+ bus-width = <8>;
+ status = "okay";
+};
--
cgit
From 478c9440b328b08b93ce83b166424b3af1a7654f Mon Sep 17 00:00:00 2001
From: Marcin Niestroj <m.niestroj@grinn-global.com>
Date: Fri, 21 Oct 2016 17:07:17 +0200
Subject: ARM: dts: imx6ul: Add DTS for liteBoard
liteBoard is a development board which uses liteSOM as its base.
Hardware specification:
* liteSOM (i.MX6UL, DRAM, eMMC)
* Ethernet PHY (id 0)
* USB host (usb_otg1)
* MicroSD slot (uSDHC1)
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6ul-liteboard.dts | 147 +++++++++++++++++++++++++++++++++
2 files changed, 148 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6ul-liteboard.dts
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index da0197dfc284..7ae5b0272033 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -424,6 +424,7 @@ dtb-$(CONFIG_SOC_IMX6SX) += \
dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-14x14-evk.dtb \
imx6ul-geam-kit.dtb \
+ imx6ul-liteboard.dtb \
imx6ul-pico-hobbit.dtb \
imx6ul-tx6ul-0010.dtb \
imx6ul-tx6ul-0011.dtb \
diff --git a/arch/arm/boot/dts/imx6ul-liteboard.dts b/arch/arm/boot/dts/imx6ul-liteboard.dts
new file mode 100644
index 000000000000..6e04cb9202f4
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-liteboard.dts
@@ -0,0 +1,147 @@
+/*
+ * Copyright 2016 Grinn
+ *
+ * Author: Marcin Niestroj <m.niestroj@grinn-global.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6ul-litesom.dtsi"
+
+/ {
+ model = "Grinn i.MX6UL liteBoard";
+ compatible = "grinn,imx6ul-liteboard", "grinn,imx6ul-litesom",
+ "fsl,imx6ul";
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_otg1_vbus>;
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio2 8 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&iomuxc {
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
+ MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
+ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usb_otg1_vbus: usb-otg1-vbus {
+ fsl,pins = <
+ MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x79
+ >;
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ phy-mode = "rmii";
+ phy-handle = <ðphy0>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&usbotg1 {
+ vbus-supply = <®_usb_otg1_vbus>;
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ keep-power-in-suspend;
+ wakeup-source;
+ status = "okay";
+};
--
cgit
From 2c5e596524e7c4a6c56d7d116607b10964be658b Mon Sep 17 00:00:00 2001
From: Neil Armstrong <narmstrong@baylibre.com>
Date: Sat, 3 Sep 2016 14:53:45 +0200
Subject: ARM: dts: Add MDM9615 dtsi
In order to support the Qualcomm MDM9615 SoC, add the SoC dtsi.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
---
arch/arm/boot/dts/qcom-mdm9615.dtsi | 557 ++++++++++++++++++++++++++++++++++++
1 file changed, 557 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-mdm9615.dtsi
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi
new file mode 100644
index 000000000000..5ae4ec59e6ea
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi
@@ -0,0 +1,557 @@
+/*
+ * Device Tree Source for Qualcomm MDM9615 SoC
+ *
+ * Copyright (C) 2016 BayLibre, SAS.
+ * Author : Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,gcc-mdm9615.h>
+#include <dt-bindings/reset/qcom,gcc-mdm9615.h>
+#include <dt-bindings/mfd/qcom-rpm.h>
+#include <dt-bindings/soc/qcom,gsbi.h>
+
+/ {
+ model = "Qualcomm MDM9615";
+ compatible = "qcom,mdm9615";
+ interrupt-parent = <&intc>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a5";
+ device_type = "cpu";
+ next-level-cache = <&L2>;
+ };
+ };
+
+ cpu-pmu {
+ compatible = "arm,cortex-a5-pmu";
+ interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ clocks {
+ cxo_board {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <19200000>;
+ };
+ };
+
+ regulators {
+ vsdcc_fixed: vsdcc-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "SDCC Power";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+ regulator-always-on;
+ };
+ };
+
+ soc: soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ compatible = "simple-bus";
+
+ L2: l2-cache@2040000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x02040000 0x1000>;
+ arm,data-latency = <2 2 0>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ intc: interrupt-controller@2000000 {
+ compatible = "qcom,msm-qgic2";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x02000000 0x1000>,
+ <0x02002000 0x1000>;
+ };
+
+ timer@200a000 {
+ compatible = "qcom,kpss-timer", "qcom,msm-timer";
+ interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>,
+ <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>;
+ reg = <0x0200a000 0x100>;
+ clock-frequency = <27000000>,
+ <32768>;
+ cpu-offset = <0x80000>;
+ };
+
+ msmgpio: pinctrl@800000 {
+ compatible = "qcom,mdm9615-pinctrl";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x800000 0x4000>;
+ };
+
+ gcc: clock-controller@900000 {
+ compatible = "qcom,gcc-mdm9615";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ reg = <0x900000 0x4000>;
+ };
+
+ lcc: clock-controller@28000000 {
+ compatible = "qcom,lcc-mdm9615";
+ reg = <0x28000000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ l2cc: clock-controller@2011000 {
+ compatible = "syscon";
+ reg = <0x02011000 0x1000>;
+ };
+
+ rng@1a500000 {
+ compatible = "qcom,prng";
+ reg = <0x1a500000 0x200>;
+ clocks = <&gcc PRNG_CLK>;
+ clock-names = "core";
+ assigned-clocks = <&gcc PRNG_CLK>;
+ assigned-clock-rates = <32000000>;
+ };
+
+ gsbi2: gsbi@16100000 {
+ compatible = "qcom,gsbi-v1.0.0";
+ cell-index = <2>;
+ reg = <0x16100000 0x100>;
+ clocks = <&gcc GSBI2_H_CLK>;
+ clock-names = "iface";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gsbi2_i2c: i2c@16180000 {
+ compatible = "qcom,i2c-qup-v1.1.1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x16180000 0x1000>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+ };
+
+ gsbi3: gsbi@16200000 {
+ compatible = "qcom,gsbi-v1.0.0";
+ cell-index = <3>;
+ reg = <0x16200000 0x100>;
+ clocks = <&gcc GSBI3_H_CLK>;
+ clock-names = "iface";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gsbi3_spi: spi@16280000 {
+ compatible = "qcom,spi-qup-v1.1.1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x16280000 0x1000>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <24000000>;
+
+ clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+ };
+
+ gsbi4: gsbi@16300000 {
+ compatible = "qcom,gsbi-v1.0.0";
+ cell-index = <4>;
+ reg = <0x16300000 0x100>;
+ clocks = <&gcc GSBI4_H_CLK>;
+ clock-names = "iface";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ syscon-tcsr = <&tcsr>;
+
+ gsbi4_serial: serial@16340000 {
+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
+ reg = <0x16340000 0x1000>,
+ <0x16300000 0x1000>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+ };
+
+ gsbi5: gsbi@16400000 {
+ compatible = "qcom,gsbi-v1.0.0";
+ cell-index = <5>;
+ reg = <0x16400000 0x100>;
+ clocks = <&gcc GSBI5_H_CLK>;
+ clock-names = "iface";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ syscon-tcsr = <&tcsr>;
+
+ gsbi5_i2c: i2c@16480000 {
+ compatible = "qcom,i2c-qup-v1.1.1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x16480000 0x1000>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+
+ /* QUP clock is not initialized, set rate */
+ assigned-clocks = <&gcc GSBI5_QUP_CLK>;
+ assigned-clock-rates = <24000000>;
+
+ clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ gsbi5_serial: serial@16440000 {
+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
+ reg = <0x16440000 0x1000>,
+ <0x16400000 0x1000>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+ };
+
+ qcom,ssbi@500000 {
+ compatible = "qcom,ssbi";
+ reg = <0x500000 0x1000>;
+ qcom,controller-type = "pmic-arbiter";
+
+ pmicintc: pmic@0 {
+ compatible = "qcom,pm8018", "qcom,pm8921";
+ interrupts = <GIC_PPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pwrkey@1c {
+ compatible = "qcom,pm8018-pwrkey", "qcom,pm8921-pwrkey";
+ reg = <0x1c>;
+ interrupt-parent = <&pmicintc>;
+ interrupts = <50 IRQ_TYPE_EDGE_RISING>,
+ <51 IRQ_TYPE_EDGE_RISING>;
+ debounce = <15625>;
+ pull-up;
+ };
+
+ pmicmpp: mpp@50 {
+ compatible = "qcom,pm8018-mpp", "qcom,ssbi-mpp";
+ interrupt-parent = <&pmicintc>;
+ interrupts = <24 IRQ_TYPE_NONE>,
+ <25 IRQ_TYPE_NONE>,
+ <26 IRQ_TYPE_NONE>,
+ <27 IRQ_TYPE_NONE>,
+ <28 IRQ_TYPE_NONE>,
+ <29 IRQ_TYPE_NONE>;
+ reg = <0x50>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ rtc@11d {
+ compatible = "qcom,pm8018-rtc", "qcom,pm8921-rtc";
+ interrupt-parent = <&pmicintc>;
+ interrupts = <39 IRQ_TYPE_EDGE_RISING>;
+ reg = <0x11d>;
+ allow-set-time;
+ };
+
+ pmicgpio: gpio@150 {
+ compatible = "qcom,pm8018-gpio", "qcom,ssbi-gpio";
+ interrupt-parent = <&pmicintc>;
+ interrupts = <24 IRQ_TYPE_NONE>,
+ <25 IRQ_TYPE_NONE>,
+ <26 IRQ_TYPE_NONE>,
+ <27 IRQ_TYPE_NONE>,
+ <28 IRQ_TYPE_NONE>,
+ <29 IRQ_TYPE_NONE>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+ };
+
+ sdcc1bam: dma@12182000{
+ compatible = "qcom,bam-v1.3.0";
+ reg = <0x12182000 0x8000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc SDC1_H_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ };
+
+ sdcc2bam: dma@12142000{
+ compatible = "qcom,bam-v1.3.0";
+ reg = <0x12142000 0x8000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc SDC2_H_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ };
+
+ amba {
+ compatible = "arm,amba-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ sdcc1: sdcc@12180000 {
+ status = "disabled";
+ compatible = "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x00051180>;
+ reg = <0x12180000 0x2000>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cmd_irq";
+ clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
+ clock-names = "mclk", "apb_pclk";
+ bus-width = <8>;
+ max-frequency = <48000000>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ vmmc-supply = <&vsdcc_fixed>;
+ dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
+ dma-names = "tx", "rx";
+ assigned-clocks = <&gcc SDC1_CLK>;
+ assigned-clock-rates = <400000>;
+ };
+
+ sdcc2: sdcc@12140000 {
+ compatible = "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x00051180>;
+ status = "disabled";
+ reg = <0x12140000 0x2000>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cmd_irq";
+ clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
+ clock-names = "mclk", "apb_pclk";
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <48000000>;
+ no-1-8-v;
+ vmmc-supply = <&vsdcc_fixed>;
+ dmas = <&sdcc2bam 2>, <&sdcc2bam 1>;
+ dma-names = "tx", "rx";
+ assigned-clocks = <&gcc SDC2_CLK>;
+ assigned-clock-rates = <400000>;
+ };
+ };
+
+ tcsr: syscon@1a400000 {
+ compatible = "qcom,tcsr-mdm9615", "syscon";
+ reg = <0x1a400000 0x100>;
+ };
+
+ rpm: rpm@108000 {
+ compatible = "qcom,rpm-mdm9615";
+ reg = <0x108000 0x1000>;
+
+ qcom,ipc = <&l2cc 0x8 2>;
+
+ interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ack", "err", "wakeup";
+
+ regulators {
+ compatible = "qcom,rpm-pm8018-regulators";
+
+ vin_lvs1-supply = <&pm8018_s3>;
+
+ vdd_l7-supply = <&pm8018_s4>;
+ vdd_l8-supply = <&pm8018_s3>;
+ vdd_l9_l10_l11_l12-supply = <&pm8018_s5>;
+
+ /* Buck SMPS */
+ pm8018_s1: s1 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1150000>;
+ qcom,switch-mode-frequency = <1600000>;
+ bias-pull-down;
+ };
+
+ pm8018_s2: s2 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1300000>;
+ qcom,switch-mode-frequency = <1600000>;
+ bias-pull-down;
+ };
+
+ pm8018_s3: s3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ qcom,switch-mode-frequency = <1600000>;
+ bias-pull-down;
+ };
+
+ pm8018_s4: s4 {
+ regulator-min-microvolt = <2100000>;
+ regulator-max-microvolt = <2200000>;
+ qcom,switch-mode-frequency = <1600000>;
+ bias-pull-down;
+ };
+
+ pm8018_s5: s5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ qcom,switch-mode-frequency = <1600000>;
+ bias-pull-down;
+ };
+
+ /* PMOS LDO */
+ pm8018_l2: l2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ bias-pull-down;
+ };
+
+ pm8018_l3: l3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ bias-pull-down;
+ };
+
+ pm8018_l4: l4 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ bias-pull-down;
+ };
+
+ pm8018_l5: l5 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ bias-pull-down;
+ };
+
+ pm8018_l6: l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2850000>;
+ bias-pull-down;
+ };
+
+ pm8018_l7: l7 {
+ regulator-min-microvolt = <1850000>;
+ regulator-max-microvolt = <1900000>;
+ bias-pull-down;
+ };
+
+ pm8018_l8: l8 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ bias-pull-down;
+ };
+
+ pm8018_l9: l9 {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1150000>;
+ bias-pull-down;
+ };
+
+ pm8018_l10: l10 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ bias-pull-down;
+ };
+
+ pm8018_l11: l11 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ bias-pull-down;
+ };
+
+ pm8018_l12: l12 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ bias-pull-down;
+ };
+
+ pm8018_l13: l13 {
+ regulator-min-microvolt = <1850000>;
+ regulator-max-microvolt = <2950000>;
+ bias-pull-down;
+ };
+
+ pm8018_l14: l14 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ bias-pull-down;
+ };
+
+ /* Low Voltage Switch */
+ pm8018_lvs1: lvs1 {
+ bias-pull-down;
+ };
+ };
+ };
+ };
+};
--
cgit
From 1754906fffcabdd166f6aec85eb9a3a28de531b8 Mon Sep 17 00:00:00 2001
From: Sylvain Lemieux <slemieux@tycoint.com>
Date: Thu, 8 Sep 2016 13:47:53 -0400
Subject: ARM: dts: lpc32xx: set default parent clock for pwm1 & pwm2
The change setup the peripheral clock (PERIPH_CLK) as the default
parent clock for PWM1 & PWM2.
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
---
arch/arm/boot/dts/lpc32xx.dtsi | 4 ++++
1 file changed, 4 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index b5841fab51c1..d81fe433e3c8 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -479,6 +479,8 @@
compatible = "nxp,lpc3220-pwm";
reg = <0x4005C000 0x4>;
clocks = <&clk LPC32XX_CLK_PWM1>;
+ assigned-clocks = <&clk LPC32XX_CLK_PWM1>;
+ assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>;
status = "disabled";
};
@@ -486,6 +488,8 @@
compatible = "nxp,lpc3220-pwm";
reg = <0x4005C004 0x4>;
clocks = <&clk LPC32XX_CLK_PWM2>;
+ assigned-clocks = <&clk LPC32XX_CLK_PWM2>;
+ assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>;
status = "disabled";
};
--
cgit
From 4cf986348522f4a0e9a24d13f371178e600d417d Mon Sep 17 00:00:00 2001
From: Javier Martinez Canillas <javier@osg.samsung.com>
Date: Thu, 27 Oct 2016 14:11:41 -0300
Subject: ARM: dts: exynos: Document eMMC/SD/SDIO devices in Snow and Peach
boards
There's a cognitive load to figure out which mmc device node corresponds
to the eMMC flash, uSD card and WiFI SDIO module on the Snow, Peach Pi
and Pit boards.
So it's better to have comments in the DTS to make this more clear.
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
[krzk: Squashed three patches into one]
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/boot/dts/exynos5250-snow-common.dtsi | 4 ++++
arch/arm/boot/dts/exynos5420-peach-pit.dts | 3 +++
arch/arm/boot/dts/exynos5800-peach-pi.dts | 3 +++
3 files changed, 10 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/exynos5250-snow-common.dtsi
index d5d51916bb74..8f3a80430748 100644
--- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi
+++ b/arch/arm/boot/dts/exynos5250-snow-common.dtsi
@@ -523,6 +523,7 @@
status = "okay";
};
+/* eMMC flash */
&mmc_0 {
status = "okay";
num-slots = <1>;
@@ -536,6 +537,7 @@
cap-mmc-highspeed;
};
+/* uSD card */
&mmc_2 {
status = "okay";
num-slots = <1>;
@@ -553,6 +555,8 @@
/*
* On Snow we've got SIP WiFi and so can keep drive strengths low to
* reduce EMI.
+ *
+ * WiFi SDIO module
*/
&mmc_3 {
status = "okay";
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index ec4a00f1ce01..1f964ec35c5e 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -697,6 +697,7 @@
status = "okay";
};
+/* eMMC flash */
&mmc_0 {
status = "okay";
num-slots = <1>;
@@ -714,6 +715,7 @@
bus-width = <8>;
};
+/* WiFi SDIO module */
&mmc_1 {
status = "okay";
num-slots = <1>;
@@ -733,6 +735,7 @@
vqmmc-supply = <&buck10_reg>;
};
+/* uSD card */
&mmc_2 {
status = "okay";
num-slots = <1>;
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 01f466816fea..f9ff7f07ae0c 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -665,6 +665,7 @@
status = "okay";
};
+/* eMMC flash */
&mmc_0 {
status = "okay";
num-slots = <1>;
@@ -683,6 +684,7 @@
bus-width = <8>;
};
+/* WiFi SDIO module */
&mmc_1 {
status = "okay";
num-slots = <1>;
@@ -702,6 +704,7 @@
vqmmc-supply = <&buck10_reg>;
};
+/* uSD card */
&mmc_2 {
status = "okay";
num-slots = <1>;
--
cgit
From f28b7824310d849bf0dd143c1700465a7c34cab0 Mon Sep 17 00:00:00 2001
From: Karl Beldan <kbeldan@baylibre.com>
Date: Wed, 5 Oct 2016 15:05:32 +0200
Subject: ARM: dts: da850: add a node for the LCD controller
Add pins used by the LCD controller and a disabled LCDC node to be
reused in device trees including da850.dtsi.
Signed-off-by: Karl Beldan <kbeldan@baylibre.com>
[Bartosz:
- added the commit description
- changed the dt node name to a generic one
- added a da850-specific compatible string
- removed the tilcdc,panel node
- moved the pins definitions to da850.dtsi as suggested by
Sekhar Nori (was in: da850-lcdk.dts)]
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
[nsekhar@ti.com: fix compatible property and remove interrupt-parent]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
arch/arm/boot/dts/da850.dtsi | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index f79e1b91c680..901d5c98d5f0 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -186,6 +186,27 @@
0xc 0x88888888 0xffffffff
>;
};
+ lcd_pins: pinmux_lcd_pins {
+ pinctrl-single,bits = <
+ /*
+ * LCD_D[2], LCD_D[3], LCD_D[4], LCD_D[5],
+ * LCD_D[6], LCD_D[7]
+ */
+ 0x40 0x22222200 0xffffff00
+ /*
+ * LCD_D[10], LCD_D[11], LCD_D[12], LCD_D[13],
+ * LCD_D[14], LCD_D[15], LCD_D[0], LCD_D[1]
+ */
+ 0x44 0x22222222 0xffffffff
+ /* LCD_D[8], LCD_D[9] */
+ 0x48 0x00000022 0x000000ff
+
+ /* LCD_PCLK */
+ 0x48 0x02000000 0x0f000000
+ /* LCD_AC_ENB_CS, LCD_VSYNC, LCD_HSYNC */
+ 0x4c 0x02000022 0x0f0000ff
+ >;
+ };
};
edma0: edma@0 {
@@ -399,6 +420,13 @@
<&edma0 0 1>;
dma-names = "tx", "rx";
};
+
+ display: display@213000 {
+ compatible = "ti,da850-tilcdc";
+ reg = <0x213000 0x1000>;
+ interrupts = <52>;
+ status = "disabled";
+ };
};
aemif: aemif@68000000 {
compatible = "ti,da850-aemif";
--
cgit
From b5028b287242b346ed396f14edb2e6156a368951 Mon Sep 17 00:00:00 2001
From: David Lechner <david@lechnology.com>
Date: Tue, 25 Oct 2016 18:32:48 -0500
Subject: ARM: dts: da850: Add DMA to SPI0
Add the bindings for DMA on SPI0
Signed-off-by: David Lechner <david@lechnology.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
arch/arm/boot/dts/da850.dtsi | 2 ++
1 file changed, 2 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 901d5c98d5f0..4c836133a183 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -357,6 +357,8 @@
num-cs = <6>;
ti,davinci-spi-intr-line = <1>;
interrupts = <20>;
+ dmas = <&edma0 14 0>, <&edma0 15 0>;
+ dma-names = "rx", "tx";
status = "disabled";
};
spi1: spi@30e000 {
--
cgit
From 7d891a685dd46b925cf25b74ada0280a2531c34f Mon Sep 17 00:00:00 2001
From: Stefan Wahren <stefan.wahren@i2se.com>
Date: Sun, 30 Oct 2016 17:22:19 +0000
Subject: ARM: dts: bcm283x: fix typo in mailbox address
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
The address of the mailbox node in the bcm283x.dtsi also has a typo.
So fix it accordingly.
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Fixes: 05b682b7a3b2 ("ARM: bcm2835: dt: Add the mailbox to the device tree")
Signed-off-by: Eric Anholt <eric@anholt.net>
---
arch/arm/boot/dts/bcm283x.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi
index 2123d0eb1890..eae6ab88d1a6 100644
--- a/arch/arm/boot/dts/bcm283x.dtsi
+++ b/arch/arm/boot/dts/bcm283x.dtsi
@@ -104,7 +104,7 @@
reg = <0x7e104000 0x10>;
};
- mailbox: mailbox@7e00b800 {
+ mailbox: mailbox@7e00b880 {
compatible = "brcm,bcm2835-mbox";
reg = <0x7e00b880 0x40>;
interrupts = <0 1>;
--
cgit
From 1b499f255589204466d8f8ab26e6b577d7b5c88f Mon Sep 17 00:00:00 2001
From: David Lechner <david@lechnology.com>
Date: Mon, 31 Oct 2016 15:47:19 -0500
Subject: ARM: dts: da850: Add cfgchip syscon node
Add a syscon node for the SoC CFGCHIPn registers. It includes a child node
for the USB PHY that is part of this range of registers.
Signed-off-by: David Lechner <david@lechnology.com>
[nsekhar@ti.com: drop OF_DEV_AUXDATA() addition]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
arch/arm/boot/dts/da850.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 4c836133a183..2534aab851e1 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -209,6 +209,16 @@
};
};
+ cfgchip: chip-controller@1417c {
+ compatible = "ti,da830-cfgchip", "syscon", "simple-mfd";
+ reg = <0x1417c 0x14>;
+
+ usb_phy: usb-phy {
+ compatible = "ti,da830-usb-phy";
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+ };
edma0: edma@0 {
compatible = "ti,edma3-tpcc";
/* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */
--
cgit
From a16fe2c1f65ec22d26acd78ea15290f36e5e4455 Mon Sep 17 00:00:00 2001
From: Peter Chen <peter.chen@nxp.com>
Date: Tue, 2 Aug 2016 17:08:23 +0800
Subject: ARM: dts: imx6ul-14x14-evk: add USB dual-role support
With commit 851ce932242d ("usb: chipidea: otg: don't wait vbus
drops below BSV when starts host"), the driver can support
enabling vbus output without software control, so this board
(control vbus output through ID pin) can support dual-role now.
Signed-off-by: Peter Chen <peter.chen@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/imx6ul-14x14-evk.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dts b/arch/arm/boot/dts/imx6ul-14x14-evk.dts
index e281d5087d4a..c5cf9424ae35 100644
--- a/arch/arm/boot/dts/imx6ul-14x14-evk.dts
+++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dts
@@ -225,7 +225,7 @@
};
&usbotg1 {
- dr_mode = "peripheral";
+ dr_mode = "otg";
status = "okay";
};
--
cgit
From 6df11287f7c976754511c0808012a71b494d4a0a Mon Sep 17 00:00:00 2001
From: Jagan Teki <jagan@amarulasolutions.com>
Date: Fri, 21 Oct 2016 13:35:51 +0530
Subject: ARM: dts: imx6q: Add Engicam i.CoreM6 Quad/Dual initial support
i.CoreM6 Quad/Dual modules are system on module solutions manufactured
by Engicam with following characteristics:
CPU NXP i.MX6 DQ, 800MHz
RAM 1GB, 32, 64 bit, DDR3-800/1066
NAND SLC,512MB
Power supply Single 5V
MAX LCD RES FULLHD
and more info at
http://www.engicam.com/en/products/embedded/som/sodimm/i-core-m6s-dl-d-q
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6q-icore.dts | 59 +++++++++
arch/arm/boot/dts/imx6qdl-icore.dtsi | 234 +++++++++++++++++++++++++++++++++++
3 files changed, 294 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6q-icore.dts
create mode 100644 arch/arm/boot/dts/imx6qdl-icore.dtsi
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7ae5b0272033..b4732f956925 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -382,6 +382,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-gw553x.dtb \
imx6q-h100.dtb \
imx6q-hummingboard.dtb \
+ imx6q-icore.dtb \
imx6q-icore-rqs.dtb \
imx6q-marsboard.dtb \
imx6q-nitrogen6x.dtb \
diff --git a/arch/arm/boot/dts/imx6q-icore.dts b/arch/arm/boot/dts/imx6q-icore.dts
new file mode 100644
index 000000000000..025f54350c28
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-icore.dts
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-icore.dtsi"
+
+/ {
+ model = "Engicam i.CoreM6 Quad/Dual Starter Kit";
+ compatible = "engicam,imx6-icore", "fsl,imx6q";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&can2 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6qdl-icore.dtsi b/arch/arm/boot/dts/imx6qdl-icore.dtsi
new file mode 100644
index 000000000000..0a1b60a4e4b6
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-icore.dtsi
@@ -0,0 +1,234 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ memory {
+ reg = <0x10000000 0x80000000>;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_usb_h1_vbus: regulator-usb-h1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_h1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_usb_otg_vbus: regulator-usb-otg-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ xceiver-supply = <®_3p3v>;
+};
+
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ xceiver-supply = <®_3p3v>;
+};
+
+&clks {
+ assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>;
+};
+
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
+ nand-on-flash-bbt;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&usbh1 {
+ vbus-supply = <®_usb_h1_vbus>;
+ disable-over-current;
+ status = "okay";
+};
+
+&usbotg {
+ vbus-supply = <®_usb_otg_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ disable-over-current;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020
+ MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020
+ MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020
+ >;
+ };
+
+ pinctrl_gpmi_nand: gpmi-nand {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
+ MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
+ MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
+ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
+ MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17070
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10070
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17070
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17070
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17070
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17070
+ >;
+ };
+};
--
cgit
From 9daee307694027eac4b10baa9cd3f2070f7459ba Mon Sep 17 00:00:00 2001
From: Jagan Teki <jagan@amarulasolutions.com>
Date: Fri, 21 Oct 2016 13:35:52 +0530
Subject: ARM: dts: imx6q: Add Engicam i.CoreM6 DualLite/Solo initial support
i.CoreM6 DualLite/Solo modules are system on module solutions manufactured
by Engicam with following characteristics:
CPU NXP i.MX6 DL, 800MHz
RAM 1GB, 32, 64 bit, DDR3-800/1066
NAND SLC,512MB
Power supply Single 5V
MAX LCD RES FULLHD
and more info at
http://www.engicam.com/en/products/embedded/som/sodimm/i-core-m6s-dl-d-q
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6dl-icore.dts | 59 ++++++++++++++++++++++++++++++++++++++
2 files changed, 60 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6dl-icore.dts
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b4732f956925..37630f9a90b8 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -341,6 +341,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-gw552x.dtb \
imx6dl-gw553x.dtb \
imx6dl-hummingboard.dtb \
+ imx6dl-icore.dtb \
imx6dl-nit6xlite.dtb \
imx6dl-nitrogen6x.dtb \
imx6dl-phytec-pbab01.dtb \
diff --git a/arch/arm/boot/dts/imx6dl-icore.dts b/arch/arm/boot/dts/imx6dl-icore.dts
new file mode 100644
index 000000000000..aec332c14af1
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-icore.dts
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-icore.dtsi"
+
+/ {
+ model = "Engicam i.CoreM6 DualLite/Solo Starter Kit";
+ compatible = "engicam,imx6-icore", "fsl,imx6dl";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&can2 {
+ status = "okay";
+};
--
cgit
From 801173fe6f488b310dab26eddcb6d77833beab8e Mon Sep 17 00:00:00 2001
From: Jagan Teki <jagan@amarulasolutions.com>
Date: Fri, 21 Oct 2016 13:35:53 +0530
Subject: ARM: dts: imx6qdl-icore: Add FEC support
Add FEC support for Engicam i.CoreM6 dql modules.
Observed similar 'eth0: link is not ready' issue which was
discussed in [1] due rmii mode with external ref_clk, so added
clock node along with the properties mentioned by Shawn in [2]
FEC link log:
------------
$ ifconfig eth0 up
[ 27.905187] SMSC LAN8710/LAN8720 2188000.ethernet:00: attached PHY driver
[SMSC LAN8710/LAN8720] (mii_bus:phy_addr=2188000.ethernet:00, irq=-1)
[ 27.918982] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
[1] https://patchwork.kernel.org/patch/3491061/
[2] https://patchwork.kernel.org/patch/3490511/
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/imx6qdl-icore.dtsi | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/imx6qdl-icore.dtsi b/arch/arm/boot/dts/imx6qdl-icore.dtsi
index 0a1b60a4e4b6..023839a02dd0 100644
--- a/arch/arm/boot/dts/imx6qdl-icore.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-icore.dtsi
@@ -74,6 +74,12 @@
regulator-boot-on;
regulator-always-on;
};
+
+ rmii_clk: clock-rmii-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>; /* 25MHz for example */
+ };
};
&can1 {
@@ -93,6 +99,15 @@
assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>;
};
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
+ clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>;
+ phy-mode = "rmii";
+ status = "okay";
+};
+
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
@@ -150,6 +165,22 @@
};
&iomuxc {
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b1
+ MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
+ MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
+ MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
+ MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
+ MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
+ >;
+ };
+
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020
--
cgit
From 3faa1bb2e89cebd8ee0a2260ba770660a2862650 Mon Sep 17 00:00:00 2001
From: Gary Bisson <gary.bisson@boundarydevices.com>
Date: Tue, 1 Nov 2016 18:10:02 +0100
Subject: ARM: dts: imx: add Boundary Devices Nitrogen6_SOM2 support
SoM based on i.MX6 Quad with 1GB of DDR3.
https://boundarydevices.com/product/nit6x-som-v2/
Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6q-nitrogen6_som2.dts | 53 ++
arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi | 770 ++++++++++++++++++++++++++
3 files changed, 824 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6q-nitrogen6_som2.dts
create mode 100644 arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 37630f9a90b8..5363b994f513 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -388,6 +388,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-marsboard.dtb \
imx6q-nitrogen6x.dtb \
imx6q-nitrogen6_max.dtb \
+ imx6q-nitrogen6_som2.dtb \
imx6q-novena.dtb \
imx6q-phytec-pbab01.dtb \
imx6q-rex-pro.dtb \
diff --git a/arch/arm/boot/dts/imx6q-nitrogen6_som2.dts b/arch/arm/boot/dts/imx6q-nitrogen6_som2.dts
new file mode 100644
index 000000000000..cf4feefe02c5
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-nitrogen6_som2.dts
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2016 Boundary Devices, Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-nitrogen6_som2.dtsi"
+
+/ {
+ model = "Boundary Devices i.MX6 Quad Nitrogen6_SOM2 Board";
+ compatible = "boundary,imx6q-nitrogen6_som2", "fsl,imx6q";
+};
+
+&sata {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
new file mode 100644
index 000000000000..d80f21abea62
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
@@ -0,0 +1,770 @@
+/*
+ * Copyright 2016 Boundary Devices, Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ memory {
+ reg = <0x10000000 0x40000000>;
+ };
+
+ backlight_lcd: backlight-lcd {
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 5000000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <7>;
+ power-supply = <®_3p3v>;
+ status = "okay";
+ };
+
+ backlight_lvds0: backlight-lvds0 {
+ compatible = "pwm-backlight";
+ pwms = <&pwm4 0 5000000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <7>;
+ power-supply = <®_3p3v>;
+ status = "okay";
+ };
+
+ backlight_lvds1: backlight-lvds1 {
+ compatible = "gpio-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_backlight_lvds1>;
+ gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>;
+ default-on;
+ status = "okay";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ power {
+ label = "Power Button";
+ gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ wakeup-source;
+ };
+
+ menu {
+ label = "Menu";
+ gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_MENU>;
+ };
+
+ home {
+ label = "Home";
+ gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_HOME>;
+ };
+
+ back {
+ label = "Back";
+ gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_BACK>;
+ };
+
+ volume-up {
+ label = "Volume Up";
+ gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ };
+
+ volume-down {
+ label = "Volume Down";
+ gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ };
+ };
+
+ lcd_display: display@di0 {
+ compatible = "fsl,imx-parallel-display";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interface-pix-fmt = "bgr666";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_j15>;
+ status = "okay";
+
+ port@0 {
+ reg = <0>;
+
+ lcd_display_in: endpoint {
+ remote-endpoint = <&ipu1_di0_disp0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lcd_display_out: endpoint {
+ remote-endpoint = <&lcd_panel_in>;
+ };
+ };
+ };
+
+ panel-lcd {
+ compatible = "okaya,rs800480t-7x0gp";
+ backlight = <&backlight_lcd>;
+
+ port {
+ lcd_panel_in: endpoint {
+ remote-endpoint = <&lcd_display_out>;
+ };
+ };
+ };
+
+ panel-lvds0 {
+ compatible = "hannstar,hsd100pxn1";
+ backlight = <&backlight_lvds0>;
+
+ port {
+ panel_in_lvds0: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+ };
+
+ panel-lvds1 {
+ compatible = "hannstar,hsd100pxn1";
+ backlight = <&backlight_lvds1>;
+
+ port {
+ panel_in_lvds1: endpoint {
+ remote-endpoint = <&lvds1_out>;
+ };
+ };
+ };
+
+ reg_1p8v: regulator-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "1P8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ reg_2p5v: regulator-2v5 {
+ compatible = "regulator-fixed";
+ regulator-name = "2P5V";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_can_xcvr: regulator-can-xcvr {
+ compatible = "regulator-fixed";
+ regulator-name = "CAN XCVR";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can_xcvr>;
+ gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ };
+
+ reg_usb_h1_vbus: regulator-usb-h1-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh1>;
+ regulator-name = "usb_h1_vbus";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ reg_usb_otg_vbus: regulator-usb-otg-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_wlan_vmmc: regulator-wlan-vmmc {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wlan_vmmc>;
+ regulator-name = "reg_wlan_vmmc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
+
+ sound {
+ compatible = "fsl,imx6q-nitrogen6_som2-sgtl5000",
+ "fsl,imx-audio-sgtl5000";
+ model = "imx6q-nitrogen6_som2-sgtl5000";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sgtl5000>;
+ ssi-controller = <&ssi1>;
+ audio-codec = <&codec>;
+ audio-routing =
+ "MIC_IN", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "Headphone Jack", "HP_OUT";
+ mux-int-port = <1>;
+ mux-ext-port = <3>;
+ };
+};
+
+&audmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux>;
+ status = "okay";
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1>;
+ xceiver-supply = <®_can_xcvr>;
+ status = "okay";
+};
+
+&clks {
+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+};
+
+&ecspi1 {
+ fsl,spi-num-chipselects = <1>;
+ cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ status = "okay";
+
+ flash: m25p80@0 {
+ compatible = "microchip,sst25vf016b";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii";
+ interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,err006687-workaround-present;
+ status = "okay";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c2>;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ codec: sgtl5000@0a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ clocks = <&clks IMX6QDL_CLK_CKO>;
+ VDDA-supply = <®_2p5v>;
+ VDDIO-supply = <®_3p3v>;
+ };
+
+ rtc@68 {
+ compatible = "st,rv4162";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rv4162>;
+ reg = <0x68>;
+ interrupts-extended = <&gpio6 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ touchscreen@04 {
+ compatible = "eeti,egalax_ts";
+ reg = <0x04>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
+ wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+ };
+
+ touchscreen@38 {
+ compatible = "edt,edt-ft5x06";
+ reg = <0x38>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
+ };
+};
+
+&iomuxc {
+ pinctrl_audmux: audmuxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
+ MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
+ MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
+ MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
+ >;
+ };
+
+ pinctrl_backlight_lvds1: backlight-lvds1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x0b0b0
+ >;
+ };
+
+ pinctrl_can1: can1grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
+ MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
+ >;
+ };
+
+ pinctrl_can_xcvr: can-xcvrgrp {
+ fsl,pins = <
+ /* Flexcan XCVR enable */
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1
+ >;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x130b0
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0
+ MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0
+ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
+ MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
+ >;
+ };
+
+ pinctrl_gpio_keys: gpio-keysgrp {
+ fsl,pins = <
+ /* Power Button */
+ MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
+ /* Menu Button */
+ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
+ /* Home Button */
+ MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0
+ /* Back Button */
+ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
+ /* Volume Up Button */
+ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0
+ /* Volume Down Button */
+ MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
+ >;
+ };
+
+ pinctrl_i2c3mux: i2c3muxgrp {
+ fsl,pins = <
+ /* PCIe I2C enable */
+ MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x000b0
+ >;
+ };
+
+ pinctrl_j15: j15grp {
+ fsl,pins = <
+ MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
+ MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
+ MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
+ MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
+ MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
+ MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
+ MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
+ MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
+ MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
+ MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
+ MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
+ MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
+ MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
+ MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
+ MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
+ MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
+ MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
+ MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
+ MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
+ MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
+ MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
+ MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
+ MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
+ MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
+ MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
+ MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
+ MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
+ MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
+ >;
+ };
+
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <
+ /* PCIe reset */
+ MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x030b0
+ MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x030b0
+ >;
+ };
+
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x030b1
+ >;
+ };
+
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x030b1
+ >;
+ };
+
+ pinctrl_pwm4: pwm4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x030b1
+ >;
+ };
+
+ pinctrl_rv4162: rv4162grp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
+ >;
+ };
+
+ pinctrl_sgtl5000: sgtl5000grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0
+ MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x130b0
+ MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x130b0
+ MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x130b0
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
+ MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbh1: usbh1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
+ MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
+ /* power enable, high active */
+ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17071
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17071
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17071
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17071
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17071
+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0
+ >;
+ };
+
+ pinctrl_usdhc4: usdhc4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
+ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
+ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
+ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
+ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
+ MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
+ MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
+ MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
+ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_wlan_vmmc: wlan-vmmcgrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x100b0
+ MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x030b0
+ MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x030b0
+ MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0
+ >;
+ };
+};
+
+&ipu1_di0_disp0 {
+ remote-endpoint = <&lcd_display_in>;
+};
+
+&ldb {
+ status = "okay";
+
+ lvds-channel@0 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <18>;
+ status = "okay";
+
+ port@4 {
+ reg = <4>;
+
+ lvds0_out: endpoint {
+ remote-endpoint = <&panel_in_lvds0>;
+ };
+ };
+ };
+
+ lvds-channel@1 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <18>;
+ status = "okay";
+
+ port@4 {
+ reg = <4>;
+
+ lvds1_out: endpoint {
+ remote-endpoint = <&panel_in_lvds1>;
+ };
+ };
+ };
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie>;
+ reset-gpio = <&gpio6 31 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "okay";
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>;
+ status = "okay";
+};
+
+&pwm4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm4>;
+ status = "okay";
+};
+
+&ssi1 {
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&usbh1 {
+ vbus-supply = <®_usb_h1_vbus>;
+ status = "okay";
+};
+
+&usbotg {
+ vbus-supply = <®_usb_otg_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ disable-over-current;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ bus-width = <4>;
+ non-removable;
+ vmmc-supply = <®_wlan_vmmc>;
+ cap-power-off-card;
+ keep-power-in-suspend;
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wlcore: wlcore@2 {
+ compatible = "ti,wl1271";
+ reg = <2>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
+ ref-clock-frequency = <38400000>;
+ };
+};
+
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ vmmc-supply = <®_3p3v>;
+ status = "okay";
+};
+
+&usdhc4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc4>;
+ bus-width = <8>;
+ non-removable;
+ vmmc-supply = <®_1p8v>;
+ keep-power-in-suspend;
+ status = "okay";
+};
--
cgit
From 4abe28eaae6955b01ea582b907e1ae0714574a15 Mon Sep 17 00:00:00 2001
From: Gary Bisson <gary.bisson@boundarydevices.com>
Date: Tue, 1 Nov 2016 18:10:03 +0100
Subject: ARM: dts: imx6qdl-sabrelite: use hyphens for nodes name
Also aligning the panel nodes name across all platforms.
Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
index 81dd6cd1937d..1f9076e271e4 100644
--- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
@@ -153,7 +153,7 @@
mux-ext-port = <4>;
};
- backlight_lcd: backlight_lcd {
+ backlight_lcd: backlight-lcd {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@@ -162,7 +162,7 @@
status = "okay";
};
- backlight_lvds: backlight_lvds {
+ backlight_lvds: backlight-lvds {
compatible = "pwm-backlight";
pwms = <&pwm4 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@@ -197,7 +197,7 @@
};
};
- lcd_panel {
+ panel-lcd {
compatible = "okaya,rs800480t-7x0gp";
backlight = <&backlight_lcd>;
@@ -208,7 +208,7 @@
};
};
- panel {
+ panel-lvds0 {
compatible = "hannstar,hsd100pxn1";
backlight = <&backlight_lvds>;
@@ -378,7 +378,7 @@
>;
};
- pinctrl_gpio_keys: gpio_keysgrp {
+ pinctrl_gpio_keys: gpio-keysgrp {
fsl,pins = <
/* Power Button */
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
--
cgit
From 986fb9e4a0380bd6d337316d96781e9b8ffb10e1 Mon Sep 17 00:00:00 2001
From: Gary Bisson <gary.bisson@boundarydevices.com>
Date: Tue, 1 Nov 2016 18:10:04 +0100
Subject: ARM: dts: imx6qdl-nitrogen6x: use hyphens for nodes name
Also aligning the panel nodes name across all platforms.
Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
index db868bc42c0f..e476d01959ea 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
@@ -167,7 +167,7 @@
mux-ext-port = <3>;
};
- backlight_lcd: backlight_lcd {
+ backlight_lcd: backlight-lcd {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@@ -176,7 +176,7 @@
status = "okay";
};
- backlight_lvds: backlight_lvds {
+ backlight_lvds: backlight-lvds {
compatible = "pwm-backlight";
pwms = <&pwm4 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@@ -211,7 +211,7 @@
};
};
- lcd_panel {
+ panel-lcd {
compatible = "okaya,rs800480t-7x0gp";
backlight = <&backlight_lcd>;
@@ -222,7 +222,7 @@
};
};
- panel {
+ panel-lvds0 {
compatible = "hannstar,hsd100pxn1";
backlight = <&backlight_lvds>;
@@ -413,7 +413,7 @@
>;
};
- pinctrl_gpio_keys: gpio_keysgrp {
+ pinctrl_gpio_keys: gpio-keysgrp {
fsl,pins = <
/* Power Button */
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
@@ -561,7 +561,7 @@
>;
};
- pinctrl_wlan_vmmc: wlan_vmmcgrp {
+ pinctrl_wlan_vmmc: wlan-vmmcgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0
--
cgit
From 241f8f6fec2f1e4e644e890f833fcf39984dfa45 Mon Sep 17 00:00:00 2001
From: Gary Bisson <gary.bisson@boundarydevices.com>
Date: Tue, 1 Nov 2016 18:10:05 +0100
Subject: ARM: dts: imx6qdl-nit6xlite: use hyphens for nodes name
Therefore aligning the panel nodes name across all platforms.
Also removing the bt_rfkill node since the mainline rfkill-gpio driver
doesn't support device trees.
Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi | 32 +++++---------------------------
1 file changed, 5 insertions(+), 27 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
index 880bd782a5b7..63acd54f5278 100644
--- a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
@@ -97,15 +97,6 @@
};
};
- bt_rfkill {
- compatible = "rfkill-gpio";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_bt_rfkill>;
- gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;
- name = "bt_rfkill";
- type = <2>;
- };
-
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
@@ -160,7 +151,7 @@
};
};
- backlight_lcd {
+ backlight-lcd {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@@ -169,7 +160,7 @@
status = "okay";
};
- backlight_lvds0: backlight_lvds0 {
+ backlight_lvds0: backlight-lvds0 {
compatible = "pwm-backlight";
pwms = <&pwm4 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@@ -178,7 +169,7 @@
status = "okay";
};
- panel_lvds0 {
+ panel-lvds0 {
compatible = "hannstar,hsd100pxn1";
backlight = <&backlight_lvds0>;
@@ -328,19 +319,6 @@
>;
};
- pinctrl_bt_rfkill: bt_rfkillgrp {
- fsl,pins = <
- /* BT wake */
- MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
- /* BT reset */
- MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0b0b0
- /* BT reg en */
- MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0
- /* BT host wake irq */
- MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x100b0
- >;
- };
-
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
@@ -374,7 +352,7 @@
>;
};
- pinctrl_gpio_keys: gpio_keysgrp {
+ pinctrl_gpio_keys: gpio-keysgrp {
fsl,pins = <
/* Home Button: J14 pin 5 */
MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0
@@ -457,7 +435,7 @@
>;
};
- pinctrl_wlan_vmmc: wlan_vmmcgrp {
+ pinctrl_wlan_vmmc: wlan-vmmcgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b0
>;
--
cgit
From a7859df4fd7df0667e486c9ebe32aa425d64c023 Mon Sep 17 00:00:00 2001
From: Gary Bisson <gary.bisson@boundarydevices.com>
Date: Tue, 1 Nov 2016 18:10:06 +0100
Subject: ARM: dts: imx6qdl-nitrogen6_max: use hyphens for nodes name
Therefore aligning the panel nodes name across all platforms.
Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
index b0b3220a1fd9..34887a10c5f1 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
@@ -229,7 +229,7 @@
};
};
- backlight_lcd: backlight_lcd {
+ backlight_lcd: backlight-lcd {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@@ -238,7 +238,7 @@
status = "okay";
};
- backlight_lvds0: backlight_lvds0 {
+ backlight_lvds0: backlight-lvds0 {
compatible = "pwm-backlight";
pwms = <&pwm4 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@@ -247,7 +247,7 @@
status = "okay";
};
- backlight_lvds1: backlight_lvds1 {
+ backlight_lvds1: backlight-lvds1 {
compatible = "pwm-backlight";
pwms = <&pwm2 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@@ -282,7 +282,7 @@
};
};
- panel_lcd {
+ panel-lcd {
compatible = "okaya,rs800480t-7x0gp";
backlight = <&backlight_lcd>;
@@ -293,7 +293,7 @@
};
};
- panel_lvds0 {
+ panel-lvds0 {
compatible = "hannstar,hsd100pxn1";
backlight = <&backlight_lvds0>;
@@ -304,7 +304,7 @@
};
};
- panel_lvds1 {
+ panel-lvds1 {
compatible = "hannstar,hsd100pxn1";
backlight = <&backlight_lvds1>;
@@ -447,7 +447,7 @@
};
&iomuxc {
- imx6q-nitrogen6_max {
+ imx6q-nitrogen6-max {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
@@ -504,7 +504,7 @@
>;
};
- pinctrl_gpio_keys: gpio_keysgrp {
+ pinctrl_gpio_keys: gpio-keysgrp {
fsl,pins = <
/* Power Button */
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
@@ -720,7 +720,7 @@
>;
};
- pinctrl_wlan_vmmc: wlan_vmmcgrp {
+ pinctrl_wlan_vmmc: wlan-vmmcgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0
--
cgit
From 46311707939f0cac228e07c59e0d86c310efa95c Mon Sep 17 00:00:00 2001
From: Jagan Teki <jagan@openedev.com>
Date: Wed, 26 Oct 2016 15:31:01 +0530
Subject: ARM: dts: imx: Fix "ERROR: code indent should use tabs where
possible"
Fixed code indent tabs in respetcive imx23, imx51, imx53, imx6dl, imx6q
and imx6sx dtsi and dts files.
Signed-off-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/imx23.dtsi | 2 +-
arch/arm/boot/dts/imx50.dtsi | 44 +++++++++---------
arch/arm/boot/dts/imx51.dtsi | 44 +++++++++---------
arch/arm/boot/dts/imx53.dtsi | 68 ++++++++++++++--------------
arch/arm/boot/dts/imx6dl-riotboard.dts | 2 +-
arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts | 2 +-
arch/arm/boot/dts/imx6dl-tx6u-801x.dts | 2 +-
arch/arm/boot/dts/imx6q-phytec-pbab01.dts | 2 +-
arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts | 2 +-
arch/arm/boot/dts/imx6q-tx6q-1010.dts | 2 +-
arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts | 2 +-
arch/arm/boot/dts/imx6q-tx6q-1020.dts | 2 +-
arch/arm/boot/dts/imx6sx-sdb.dtsi | 8 ++--
arch/arm/boot/dts/imx6sx.dtsi | 6 +--
14 files changed, 94 insertions(+), 94 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 440ee9a4a158..8e1543f7aea7 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -464,7 +464,7 @@
reg = <0x80038000 0x2000>;
status = "disabled";
};
- };
+ };
apbx@80040000 {
compatible = "simple-bus";
diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi
index 8fe8beeb68a4..92a03bc54f75 100644
--- a/arch/arm/boot/dts/imx50.dtsi
+++ b/arch/arm/boot/dts/imx50.dtsi
@@ -103,8 +103,8 @@
reg = <0x50004000 0x4000>;
interrupts = <1>;
clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
- <&clks IMX5_CLK_DUMMY>,
- <&clks IMX5_CLK_ESDHC1_PER_GATE>;
+ <&clks IMX5_CLK_DUMMY>,
+ <&clks IMX5_CLK_ESDHC1_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@@ -115,8 +115,8 @@
reg = <0x50008000 0x4000>;
interrupts = <2>;
clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
- <&clks IMX5_CLK_DUMMY>,
- <&clks IMX5_CLK_ESDHC2_PER_GATE>;
+ <&clks IMX5_CLK_DUMMY>,
+ <&clks IMX5_CLK_ESDHC2_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@@ -127,7 +127,7 @@
reg = <0x5000c000 0x4000>;
interrupts = <33>;
clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
- <&clks IMX5_CLK_UART3_PER_GATE>;
+ <&clks IMX5_CLK_UART3_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -139,7 +139,7 @@
reg = <0x50010000 0x4000>;
interrupts = <36>;
clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
- <&clks IMX5_CLK_ECSPI1_PER_GATE>;
+ <&clks IMX5_CLK_ECSPI1_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -164,8 +164,8 @@
reg = <0x50020000 0x4000>;
interrupts = <3>;
clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
- <&clks IMX5_CLK_DUMMY>,
- <&clks IMX5_CLK_ESDHC3_PER_GATE>;
+ <&clks IMX5_CLK_DUMMY>,
+ <&clks IMX5_CLK_ESDHC3_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@@ -176,8 +176,8 @@
reg = <0x50024000 0x4000>;
interrupts = <4>;
clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
- <&clks IMX5_CLK_DUMMY>,
- <&clks IMX5_CLK_ESDHC4_PER_GATE>;
+ <&clks IMX5_CLK_DUMMY>,
+ <&clks IMX5_CLK_ESDHC4_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@@ -279,7 +279,7 @@
reg = <0x53fa0000 0x4000>;
interrupts = <39>;
clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
- <&clks IMX5_CLK_GPT_HF_GATE>;
+ <&clks IMX5_CLK_GPT_HF_GATE>;
clock-names = "ipg", "per";
};
@@ -298,7 +298,7 @@
compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
reg = <0x53fb4000 0x4000>;
clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
- <&clks IMX5_CLK_PWM1_HF_GATE>;
+ <&clks IMX5_CLK_PWM1_HF_GATE>;
clock-names = "ipg", "per";
interrupts = <61>;
};
@@ -308,7 +308,7 @@
compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
reg = <0x53fb8000 0x4000>;
clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
- <&clks IMX5_CLK_PWM2_HF_GATE>;
+ <&clks IMX5_CLK_PWM2_HF_GATE>;
clock-names = "ipg", "per";
interrupts = <94>;
};
@@ -318,7 +318,7 @@
reg = <0x53fbc000 0x4000>;
interrupts = <31>;
clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
- <&clks IMX5_CLK_UART1_PER_GATE>;
+ <&clks IMX5_CLK_UART1_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -328,7 +328,7 @@
reg = <0x53fc0000 0x4000>;
interrupts = <32>;
clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
- <&clks IMX5_CLK_UART2_PER_GATE>;
+ <&clks IMX5_CLK_UART2_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -383,7 +383,7 @@
reg = <0x53ff0000 0x4000>;
interrupts = <13>;
clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
- <&clks IMX5_CLK_UART4_PER_GATE>;
+ <&clks IMX5_CLK_UART4_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -401,7 +401,7 @@
reg = <0x63f90000 0x4000>;
interrupts = <86>;
clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
- <&clks IMX5_CLK_UART5_PER_GATE>;
+ <&clks IMX5_CLK_UART5_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -420,7 +420,7 @@
reg = <0x63fac000 0x4000>;
interrupts = <37>;
clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
- <&clks IMX5_CLK_ECSPI2_PER_GATE>;
+ <&clks IMX5_CLK_ECSPI2_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -430,7 +430,7 @@
reg = <0x63fb0000 0x4000>;
interrupts = <6>;
clocks = <&clks IMX5_CLK_SDMA_GATE>,
- <&clks IMX5_CLK_SDMA_GATE>;
+ <&clks IMX5_CLK_SDMA_GATE>;
clock-names = "ipg", "ahb";
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
};
@@ -442,7 +442,7 @@
reg = <0x63fc0000 0x4000>;
interrupts = <38>;
clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
- <&clks IMX5_CLK_CSPI_IPG_GATE>;
+ <&clks IMX5_CLK_CSPI_IPG_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -492,8 +492,8 @@
reg = <0x63fec000 0x4000>;
interrupts = <87>;
clocks = <&clks IMX5_CLK_FEC_GATE>,
- <&clks IMX5_CLK_FEC_GATE>,
- <&clks IMX5_CLK_FEC_GATE>;
+ <&clks IMX5_CLK_FEC_GATE>,
+ <&clks IMX5_CLK_FEC_GATE>;
clock-names = "ipg", "ahb", "ptp";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index f46fe9bf0bcb..d8efdab45f89 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -130,8 +130,8 @@
reg = <0x40000000 0x20000000>;
interrupts = <11 10>;
clocks = <&clks IMX5_CLK_IPU_GATE>,
- <&clks IMX5_CLK_IPU_DI0_GATE>,
- <&clks IMX5_CLK_IPU_DI1_GATE>;
+ <&clks IMX5_CLK_IPU_DI0_GATE>,
+ <&clks IMX5_CLK_IPU_DI1_GATE>;
clock-names = "bus", "di0", "di1";
resets = <&src 2>;
@@ -169,8 +169,8 @@
reg = <0x70004000 0x4000>;
interrupts = <1>;
clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
- <&clks IMX5_CLK_DUMMY>,
- <&clks IMX5_CLK_ESDHC1_PER_GATE>;
+ <&clks IMX5_CLK_DUMMY>,
+ <&clks IMX5_CLK_ESDHC1_PER_GATE>;
clock-names = "ipg", "ahb", "per";
status = "disabled";
};
@@ -180,8 +180,8 @@
reg = <0x70008000 0x4000>;
interrupts = <2>;
clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
- <&clks IMX5_CLK_DUMMY>,
- <&clks IMX5_CLK_ESDHC2_PER_GATE>;
+ <&clks IMX5_CLK_DUMMY>,
+ <&clks IMX5_CLK_ESDHC2_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@@ -192,7 +192,7 @@
reg = <0x7000c000 0x4000>;
interrupts = <33>;
clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
- <&clks IMX5_CLK_UART3_PER_GATE>;
+ <&clks IMX5_CLK_UART3_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -204,7 +204,7 @@
reg = <0x70010000 0x4000>;
interrupts = <36>;
clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
- <&clks IMX5_CLK_ECSPI1_PER_GATE>;
+ <&clks IMX5_CLK_ECSPI1_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -229,8 +229,8 @@
reg = <0x70020000 0x4000>;
interrupts = <3>;
clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
- <&clks IMX5_CLK_DUMMY>,
- <&clks IMX5_CLK_ESDHC3_PER_GATE>;
+ <&clks IMX5_CLK_DUMMY>,
+ <&clks IMX5_CLK_ESDHC3_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@@ -241,8 +241,8 @@
reg = <0x70024000 0x4000>;
interrupts = <4>;
clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
- <&clks IMX5_CLK_DUMMY>,
- <&clks IMX5_CLK_ESDHC4_PER_GATE>;
+ <&clks IMX5_CLK_DUMMY>,
+ <&clks IMX5_CLK_ESDHC4_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@@ -364,7 +364,7 @@
reg = <0x73fa0000 0x4000>;
interrupts = <39>;
clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
- <&clks IMX5_CLK_GPT_HF_GATE>;
+ <&clks IMX5_CLK_GPT_HF_GATE>;
clock-names = "ipg", "per";
};
@@ -378,7 +378,7 @@
compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
reg = <0x73fb4000 0x4000>;
clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
- <&clks IMX5_CLK_PWM1_HF_GATE>;
+ <&clks IMX5_CLK_PWM1_HF_GATE>;
clock-names = "ipg", "per";
interrupts = <61>;
};
@@ -388,7 +388,7 @@
compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
reg = <0x73fb8000 0x4000>;
clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
- <&clks IMX5_CLK_PWM2_HF_GATE>;
+ <&clks IMX5_CLK_PWM2_HF_GATE>;
clock-names = "ipg", "per";
interrupts = <94>;
};
@@ -398,7 +398,7 @@
reg = <0x73fbc000 0x4000>;
interrupts = <31>;
clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
- <&clks IMX5_CLK_UART1_PER_GATE>;
+ <&clks IMX5_CLK_UART1_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -408,7 +408,7 @@
reg = <0x73fc0000 0x4000>;
interrupts = <32>;
clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
- <&clks IMX5_CLK_UART2_PER_GATE>;
+ <&clks IMX5_CLK_UART2_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -456,7 +456,7 @@
reg = <0x83fac000 0x4000>;
interrupts = <37>;
clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
- <&clks IMX5_CLK_ECSPI2_PER_GATE>;
+ <&clks IMX5_CLK_ECSPI2_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -466,7 +466,7 @@
reg = <0x83fb0000 0x4000>;
interrupts = <6>;
clocks = <&clks IMX5_CLK_SDMA_GATE>,
- <&clks IMX5_CLK_SDMA_GATE>;
+ <&clks IMX5_CLK_SDMA_GATE>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
@@ -479,7 +479,7 @@
reg = <0x83fc0000 0x4000>;
interrupts = <38>;
clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
- <&clks IMX5_CLK_CSPI_IPG_GATE>;
+ <&clks IMX5_CLK_CSPI_IPG_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -582,8 +582,8 @@
reg = <0x83fec000 0x4000>;
interrupts = <87>;
clocks = <&clks IMX5_CLK_FEC_GATE>,
- <&clks IMX5_CLK_FEC_GATE>,
- <&clks IMX5_CLK_FEC_GATE>;
+ <&clks IMX5_CLK_FEC_GATE>,
+ <&clks IMX5_CLK_FEC_GATE>;
clock-names = "ipg", "ahb", "ptp";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 0777b41cdfe8..88f9e09effdc 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -131,8 +131,8 @@
reg = <0x18000000 0x08000000>;
interrupts = <11 10>;
clocks = <&clks IMX5_CLK_IPU_GATE>,
- <&clks IMX5_CLK_IPU_DI0_GATE>,
- <&clks IMX5_CLK_IPU_DI1_GATE>;
+ <&clks IMX5_CLK_IPU_DI0_GATE>,
+ <&clks IMX5_CLK_IPU_DI1_GATE>;
clock-names = "bus", "di0", "di1";
resets = <&src 2>;
@@ -199,8 +199,8 @@
reg = <0x50004000 0x4000>;
interrupts = <1>;
clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
- <&clks IMX5_CLK_DUMMY>,
- <&clks IMX5_CLK_ESDHC1_PER_GATE>;
+ <&clks IMX5_CLK_DUMMY>,
+ <&clks IMX5_CLK_ESDHC1_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@@ -211,8 +211,8 @@
reg = <0x50008000 0x4000>;
interrupts = <2>;
clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
- <&clks IMX5_CLK_DUMMY>,
- <&clks IMX5_CLK_ESDHC2_PER_GATE>;
+ <&clks IMX5_CLK_DUMMY>,
+ <&clks IMX5_CLK_ESDHC2_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@@ -223,7 +223,7 @@
reg = <0x5000c000 0x4000>;
interrupts = <33>;
clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
- <&clks IMX5_CLK_UART3_PER_GATE>;
+ <&clks IMX5_CLK_UART3_PER_GATE>;
clock-names = "ipg", "per";
dmas = <&sdma 42 4 0>, <&sdma 43 4 0>;
dma-names = "rx", "tx";
@@ -237,7 +237,7 @@
reg = <0x50010000 0x4000>;
interrupts = <36>;
clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
- <&clks IMX5_CLK_ECSPI1_PER_GATE>;
+ <&clks IMX5_CLK_ECSPI1_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -264,8 +264,8 @@
reg = <0x50020000 0x4000>;
interrupts = <3>;
clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
- <&clks IMX5_CLK_DUMMY>,
- <&clks IMX5_CLK_ESDHC3_PER_GATE>;
+ <&clks IMX5_CLK_DUMMY>,
+ <&clks IMX5_CLK_ESDHC3_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@@ -276,8 +276,8 @@
reg = <0x50024000 0x4000>;
interrupts = <4>;
clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
- <&clks IMX5_CLK_DUMMY>,
- <&clks IMX5_CLK_ESDHC4_PER_GATE>;
+ <&clks IMX5_CLK_DUMMY>,
+ <&clks IMX5_CLK_ESDHC4_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@@ -419,7 +419,7 @@
reg = <0x53fa0000 0x4000>;
interrupts = <39>;
clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
- <&clks IMX5_CLK_GPT_HF_GATE>;
+ <&clks IMX5_CLK_GPT_HF_GATE>;
clock-names = "ipg", "per";
};
@@ -440,11 +440,11 @@
reg = <0x53fa8008 0x4>;
gpr = <&gpr>;
clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
- <&clks IMX5_CLK_LDB_DI1_SEL>,
- <&clks IMX5_CLK_IPU_DI0_SEL>,
- <&clks IMX5_CLK_IPU_DI1_SEL>,
- <&clks IMX5_CLK_LDB_DI0_GATE>,
- <&clks IMX5_CLK_LDB_DI1_GATE>;
+ <&clks IMX5_CLK_LDB_DI1_SEL>,
+ <&clks IMX5_CLK_IPU_DI0_SEL>,
+ <&clks IMX5_CLK_IPU_DI1_SEL>,
+ <&clks IMX5_CLK_LDB_DI0_GATE>,
+ <&clks IMX5_CLK_LDB_DI1_GATE>;
clock-names = "di0_pll", "di1_pll",
"di0_sel", "di1_sel",
"di0", "di1";
@@ -486,7 +486,7 @@
compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
reg = <0x53fb4000 0x4000>;
clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
- <&clks IMX5_CLK_PWM1_HF_GATE>;
+ <&clks IMX5_CLK_PWM1_HF_GATE>;
clock-names = "ipg", "per";
interrupts = <61>;
};
@@ -496,7 +496,7 @@
compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
reg = <0x53fb8000 0x4000>;
clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
- <&clks IMX5_CLK_PWM2_HF_GATE>;
+ <&clks IMX5_CLK_PWM2_HF_GATE>;
clock-names = "ipg", "per";
interrupts = <94>;
};
@@ -506,7 +506,7 @@
reg = <0x53fbc000 0x4000>;
interrupts = <31>;
clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
- <&clks IMX5_CLK_UART1_PER_GATE>;
+ <&clks IMX5_CLK_UART1_PER_GATE>;
clock-names = "ipg", "per";
dmas = <&sdma 18 4 0>, <&sdma 19 4 0>;
dma-names = "rx", "tx";
@@ -518,7 +518,7 @@
reg = <0x53fc0000 0x4000>;
interrupts = <32>;
clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
- <&clks IMX5_CLK_UART2_PER_GATE>;
+ <&clks IMX5_CLK_UART2_PER_GATE>;
clock-names = "ipg", "per";
dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
dma-names = "rx", "tx";
@@ -530,7 +530,7 @@
reg = <0x53fc8000 0x4000>;
interrupts = <82>;
clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
- <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
+ <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -540,7 +540,7 @@
reg = <0x53fcc000 0x4000>;
interrupts = <83>;
clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
- <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
+ <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -603,7 +603,7 @@
reg = <0x53ff0000 0x4000>;
interrupts = <13>;
clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
- <&clks IMX5_CLK_UART4_PER_GATE>;
+ <&clks IMX5_CLK_UART4_PER_GATE>;
clock-names = "ipg", "per";
dmas = <&sdma 2 4 0>, <&sdma 3 4 0>;
dma-names = "rx", "tx";
@@ -635,7 +635,7 @@
reg = <0x63f90000 0x4000>;
interrupts = <86>;
clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
- <&clks IMX5_CLK_UART5_PER_GATE>;
+ <&clks IMX5_CLK_UART5_PER_GATE>;
clock-names = "ipg", "per";
dmas = <&sdma 16 4 0>, <&sdma 17 4 0>;
dma-names = "rx", "tx";
@@ -656,7 +656,7 @@
reg = <0x63fac000 0x4000>;
interrupts = <37>;
clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
- <&clks IMX5_CLK_ECSPI2_PER_GATE>;
+ <&clks IMX5_CLK_ECSPI2_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -666,7 +666,7 @@
reg = <0x63fb0000 0x4000>;
interrupts = <6>;
clocks = <&clks IMX5_CLK_SDMA_GATE>,
- <&clks IMX5_CLK_SDMA_GATE>;
+ <&clks IMX5_CLK_SDMA_GATE>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
@@ -679,7 +679,7 @@
reg = <0x63fc0000 0x4000>;
interrupts = <38>;
clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
- <&clks IMX5_CLK_CSPI_IPG_GATE>;
+ <&clks IMX5_CLK_CSPI_IPG_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -755,8 +755,8 @@
reg = <0x63fec000 0x4000>;
interrupts = <87>;
clocks = <&clks IMX5_CLK_FEC_GATE>,
- <&clks IMX5_CLK_FEC_GATE>,
- <&clks IMX5_CLK_FEC_GATE>;
+ <&clks IMX5_CLK_FEC_GATE>,
+ <&clks IMX5_CLK_FEC_GATE>;
clock-names = "ipg", "ahb", "ptp";
status = "disabled";
};
@@ -766,7 +766,7 @@
reg = <0x63ff0000 0x1000>;
interrupts = <92>;
clocks = <&clks IMX5_CLK_TVE_GATE>,
- <&clks IMX5_CLK_IPU_DI1_SEL>;
+ <&clks IMX5_CLK_IPU_DI1_SEL>;
clock-names = "tve", "di_sel";
status = "disabled";
@@ -782,7 +782,7 @@
reg = <0x63ff4000 0x1000>;
interrupts = <9>;
clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
- <&clks IMX5_CLK_VPU_GATE>;
+ <&clks IMX5_CLK_VPU_GATE>;
clock-names = "per", "ahb";
resets = <&src 1>;
iram = <&ocram>;
@@ -793,7 +793,7 @@
reg = <0x63ff8000 0x4000>;
interrupts = <19 20>;
clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
- <&clks IMX5_CLK_SAHARA_IPG_GATE>;
+ <&clks IMX5_CLK_SAHARA_IPG_GATE>;
clock-names = "ipg", "ahb";
};
};
diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts
index 75d73437adf7..2cb72824e800 100644
--- a/arch/arm/boot/dts/imx6dl-riotboard.dts
+++ b/arch/arm/boot/dts/imx6dl-riotboard.dts
@@ -390,7 +390,7 @@
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 /* AR8035 pin strapping: MODE#3: pull up */
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* GPIO16 -> AR8035 25MHz */
- MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */
+ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x180b0 /* AR8035 interrupt */
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
diff --git a/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts b/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts
index 063fe7510da5..aac42ac465b6 100644
--- a/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts
+++ b/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts
@@ -105,7 +105,7 @@
pixelclk-active = <1>;
};
};
- };
+ };
};
&can1 {
diff --git a/arch/arm/boot/dts/imx6dl-tx6u-801x.dts b/arch/arm/boot/dts/imx6dl-tx6u-801x.dts
index b7a72840b7f0..d1f1298ec55a 100644
--- a/arch/arm/boot/dts/imx6dl-tx6u-801x.dts
+++ b/arch/arm/boot/dts/imx6dl-tx6u-801x.dts
@@ -199,7 +199,7 @@
pixelclk-active = <0>;
};
};
- };
+ };
};
&ipu1_di0_disp0 {
diff --git a/arch/arm/boot/dts/imx6q-phytec-pbab01.dts b/arch/arm/boot/dts/imx6q-phytec-pbab01.dts
index c139ac0ebe15..1f4771304da8 100644
--- a/arch/arm/boot/dts/imx6q-phytec-pbab01.dts
+++ b/arch/arm/boot/dts/imx6q-phytec-pbab01.dts
@@ -23,5 +23,5 @@
};
&sata {
- status = "okay";
+ status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts b/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts
index 65e95ae7509a..71746edc2ee9 100644
--- a/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts
+++ b/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts
@@ -105,7 +105,7 @@
pixelclk-active = <1>;
};
};
- };
+ };
};
&can1 {
diff --git a/arch/arm/boot/dts/imx6q-tx6q-1010.dts b/arch/arm/boot/dts/imx6q-tx6q-1010.dts
index 20cd0e7b3e21..f9cd21a41a79 100644
--- a/arch/arm/boot/dts/imx6q-tx6q-1010.dts
+++ b/arch/arm/boot/dts/imx6q-tx6q-1010.dts
@@ -199,7 +199,7 @@
pixelclk-active = <0>;
};
};
- };
+ };
};
&ipu1_di0_disp0 {
diff --git a/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts b/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts
index 9ed243b704ff..959ff3fb7304 100644
--- a/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts
+++ b/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts
@@ -105,7 +105,7 @@
pixelclk-active = <1>;
};
};
- };
+ };
};
&can1 {
diff --git a/arch/arm/boot/dts/imx6q-tx6q-1020.dts b/arch/arm/boot/dts/imx6q-tx6q-1020.dts
index 347b531d3763..b49133d25d80 100644
--- a/arch/arm/boot/dts/imx6q-tx6q-1020.dts
+++ b/arch/arm/boot/dts/imx6q-tx6q-1020.dts
@@ -199,7 +199,7 @@
pixelclk-active = <0>;
};
};
- };
+ };
};
&ds1339 {
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi
index 9d70cfd40aff..7327bcde843f 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dtsi
+++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi
@@ -192,10 +192,10 @@
};
&i2c4 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c4>;
- status = "okay";
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
codec: wm8962@1a {
compatible = "wlf,wm8962";
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 9526c3854b28..bd9fe6745601 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -858,7 +858,7 @@
fsl,num-tx-queues=<3>;
fsl,num-rx-queues=<3>;
status = "disabled";
- };
+ };
mlb: mlb@0218c000 {
reg = <0x0218c000 0x4000>;
@@ -1181,7 +1181,7 @@
fsl,adck-max-frequency = <30000000>, <40000000>,
<20000000>;
status = "disabled";
- };
+ };
adc2: adc@02284000 {
compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
@@ -1192,7 +1192,7 @@
fsl,adck-max-frequency = <30000000>, <40000000>,
<20000000>;
status = "disabled";
- };
+ };
wdog3: wdog@02288000 {
compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
--
cgit
From 46dcf0ff0de35da881dcf69d86de3f61ebc2393f Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzk@kernel.org>
Date: Fri, 21 Oct 2016 17:15:31 +0300
Subject: ARM: dts: exynos: Remove exynos4415.dtsi
There are no boards in mainline using exynos4415.dtsi. These DTSIs
were not tested for long. I am also not aware of any popular out-of-tree
boards using this (except consumer devices released by Samsung but those
cannot use mainline).
Keeping Exynos4415 costs some useless effort so remove it.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
---
arch/arm/boot/dts/exynos4415-pinctrl.dtsi | 575 --------------------------
arch/arm/boot/dts/exynos4415.dtsi | 650 ------------------------------
2 files changed, 1225 deletions(-)
delete mode 100644 arch/arm/boot/dts/exynos4415-pinctrl.dtsi
delete mode 100644 arch/arm/boot/dts/exynos4415.dtsi
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/exynos4415-pinctrl.dtsi b/arch/arm/boot/dts/exynos4415-pinctrl.dtsi
deleted file mode 100644
index 76cfd872ead3..000000000000
--- a/arch/arm/boot/dts/exynos4415-pinctrl.dtsi
+++ /dev/null
@@ -1,575 +0,0 @@
-/*
- * Samsung's Exynos4415 SoCs pin-mux and pin-config device tree source
- *
- * Copyright (c) 2014 Samsung Electronics Co., Ltd.
- *
- * Samsung's Exynos4415 SoCs pin-mux and pin-config optiosn are listed as device
- * tree nodes are listed in this file.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <dt-bindings/pinctrl/samsung.h>
-
-&pinctrl_0 {
- gpa0: gpa0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpa1: gpa1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpb: gpb {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpc0: gpc0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpc1: gpc1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpd0: gpd0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpd1: gpd1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpf0: gpf0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpf1: gpf1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpf2: gpf2 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- uart0_data: uart0-data {
- samsung,pins = "gpa0-0", "gpa0-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- uart0_fctl: uart0-fctl {
- samsung,pins = "gpa0-2", "gpa0-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- uart1_data: uart1-data {
- samsung,pins = "gpa0-4", "gpa0-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- uart1_fctl: uart1-fctl {
- samsung,pins = "gpa0-6", "gpa0-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- uart2_data: uart2-data {
- samsung,pins = "gpa1-0", "gpa1-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- uart2_fctl: uart2-fctl {
- samsung,pins = "gpa1-2", "gpa1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- uart3_data: uart3-data {
- samsung,pins = "gpa1-4", "gpa1-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c2_bus: i2c2-bus {
- samsung,pins = "gpa0-6", "gpa0-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c3_bus: i2c3-bus {
- samsung,pins = "gpa1-2", "gpa1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- spi0_bus: spi0-bus {
- samsung,pins = "gpb-0", "gpb-2", "gpb-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c4_bus: i2c4-bus {
- samsung,pins = "gpb-0", "gpb-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- spi1_bus: spi1-bus {
- samsung,pins = "gpb-4", "gpb-6", "gpb-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c5_bus: i2c5-bus {
- samsung,pins = "gpb-2", "gpb-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2s1_bus: i2s1-bus {
- samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
- "gpc0-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2s2_bus: i2s2-bus {
- samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
- "gpc1-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- pcm2_bus: pcm2-bus {
- samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
- "gpc1-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c6_bus: i2c6-bus {
- samsung,pins = "gpc1-3", "gpc1-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- spi2_bus: spi2-bus {
- samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_5>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- pwm0_out: pwm0-out {
- samsung,pins = "gpd0-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- pwm1_out: pwm1-out {
- samsung,pins = "gpd0-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- pwm2_out: pwm2-out {
- samsung,pins = "gpd0-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- pwm3_out: pwm3-out {
- samsung,pins = "gpd0-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c7_bus: i2c7-bus {
- samsung,pins = "gpd0-2", "gpd0-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c0_bus: i2c0-bus {
- samsung,pins = "gpd1-0", "gpd1-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c1_bus: i2c1-bus {
- samsung,pins = "gpd1-2", "gpd1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-};
-
-&pinctrl_1 {
- gpk0: gpk0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpk1: gpk1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpk2: gpk2 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpk3: gpk3 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpl0: gpl0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpm0: gpm0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpm1: gpm1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpm2: gpm2 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpm3: gpm3 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpm4: gpm4 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpx0: gpx0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- interrupt-parent = <&gic>;
- interrupts = <0 32 0>, <0 33 0>, <0 34 0>, <0 35 0>,
- <0 36 0>, <0 37 0>, <0 38 0>, <0 39 0>;
- #interrupt-cells = <2>;
- };
-
- gpx1: gpx1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- interrupt-parent = <&gic>;
- interrupts = <0 40 0>, <0 41 0>, <0 42 0>, <0 43 0>,
- <0 44 0>, <0 45 0>, <0 46 0>, <0 47 0>;
- #interrupt-cells = <2>;
- };
-
- gpx2: gpx2 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpx3: gpx3 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- sd0_clk: sd0-clk {
- samsung,pins = "gpk0-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd0_cmd: sd0-cmd {
- samsung,pins = "gpk0-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd0_cd: sd0-cd {
- samsung,pins = "gpk0-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd0_rdqs: sd0-rdqs {
- samsung,pins = "gpk0-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd0_bus1: sd0-bus-width1 {
- samsung,pins = "gpk0-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd0_bus4: sd0-bus-width4 {
- samsung,pins = "gpk0-4", "gpk0-5", "gpk0-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd0_bus8: sd0-bus-width8 {
- samsung,pins = "gpl0-0", "gpl0-1", "gpl0-2", "gpl0-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd1_clk: sd1-clk {
- samsung,pins = "gpk1-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd1_cmd: sd1-cmd {
- samsung,pins = "gpk1-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd1_cd: sd1-cd {
- samsung,pins = "gpk1-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd1_bus1: sd1-bus-width1 {
- samsung,pins = "gpk1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd1_bus4: sd1-bus-width4 {
- samsung,pins = "gpk1-4", "gpk1-5", "gpk1-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd2_clk: sd2-clk {
- samsung,pins = "gpk2-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd2_cmd: sd2-cmd {
- samsung,pins = "gpk2-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd2_cd: sd2-cd {
- samsung,pins = "gpk2-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd2_bus1: sd2-bus-width1 {
- samsung,pins = "gpk2-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd2_bus4: sd2-bus-width4 {
- samsung,pins = "gpk2-4", "gpk2-5", "gpk2-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- cam_port_b_io: cam-port-b-io {
- samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3",
- "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7",
- "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- cam_port_b_clk_active: cam-port-b-clk-active {
- samsung,pins = "gpm2-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- cam_port_b_clk_idle: cam-port-b-clk-idle {
- samsung,pins = "gpm2-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- fimc_is_i2c0: fimc-is-i2c0 {
- samsung,pins = "gpm4-0", "gpm4-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- fimc_is_i2c1: fimc-is-i2c1 {
- samsung,pins = "gpm4-2", "gpm4-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- fimc_is_uart: fimc-is-uart {
- samsung,pins = "gpm3-5", "gpm3-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-};
-
-&pinctrl_2 {
- gpz: gpz {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- i2s0_bus: i2s0-bus {
- samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
- "gpz-4", "gpz-5", "gpz-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-};
diff --git a/arch/arm/boot/dts/exynos4415.dtsi b/arch/arm/boot/dts/exynos4415.dtsi
deleted file mode 100644
index 3c40f8a956dd..000000000000
--- a/arch/arm/boot/dts/exynos4415.dtsi
+++ /dev/null
@@ -1,650 +0,0 @@
-/*
- * Samsung's Exynos4415 SoC device tree source
- *
- * Copyright (c) 2014 Samsung Electronics Co., Ltd.
- *
- * Samsung's Exynos4415 SoC device nodes are listed in this file. Exynos4415
- * based board files can include this file and provide values for board
- * specific bindings.
- *
- * Note: This file does not include device nodes for all the controllers in
- * Exynos4415 SoC. As device tree coverage for Exynos4415 increases, additional
- * nodes can be added to this file.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <dt-bindings/clock/exynos4415.h>
-#include <dt-bindings/clock/exynos-audss-clk.h>
-
-/ {
- compatible = "samsung,exynos4415";
- interrupt-parent = <&gic>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- aliases {
- pinctrl0 = &pinctrl_0;
- pinctrl1 = &pinctrl_1;
- pinctrl2 = &pinctrl_2;
- mshc0 = &mshc_0;
- mshc1 = &mshc_1;
- mshc2 = &mshc_2;
- spi0 = &spi_0;
- spi1 = &spi_1;
- spi2 = &spi_2;
- i2c0 = &i2c_0;
- i2c1 = &i2c_1;
- i2c2 = &i2c_2;
- i2c3 = &i2c_3;
- i2c4 = &i2c_4;
- i2c5 = &i2c_5;
- i2c6 = &i2c_6;
- i2c7 = &i2c_7;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@a00 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0xa00>;
- clock-frequency = <1600000000>;
- };
-
- cpu1: cpu@a01 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0xa01>;
- clock-frequency = <1600000000>;
- };
-
- cpu2: cpu@a02 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0xa02>;
- clock-frequency = <1600000000>;
- };
-
- cpu3: cpu@a03 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0xa03>;
- clock-frequency = <1600000000>;
- };
- };
-
- soc: soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- sysram@02020000 {
- compatible = "mmio-sram";
- reg = <0x02020000 0x50000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x02020000 0x50000>;
-
- smp-sysram@0 {
- compatible = "samsung,exynos4210-sysram";
- reg = <0x0 0x1000>;
- };
-
- smp-sysram@4f000 {
- compatible = "samsung,exynos4210-sysram-ns";
- reg = <0x4f000 0x1000>;
- };
- };
-
- pinctrl_2: pinctrl@03860000 {
- compatible = "samsung,exynos4415-pinctrl";
- reg = <0x03860000 0x1000>;
- interrupts = <0 242 0>;
- };
-
- chipid@10000000 {
- compatible = "samsung,exynos4210-chipid";
- reg = <0x10000000 0x100>;
- };
-
- sysreg_system_controller: syscon@10010000 {
- compatible = "samsung,exynos4-sysreg", "syscon";
- reg = <0x10010000 0x400>;
- };
-
- pmu_system_controller: system-controller@10020000 {
- compatible = "samsung,exynos4415-pmu", "syscon";
- reg = <0x10020000 0x4000>;
- };
-
- mipi_phy: video-phy@10020710 {
- compatible = "samsung,s5pv210-mipi-video-phy";
- #phy-cells = <1>;
- syscon = <&pmu_system_controller>;
- };
-
- pd_cam: cam-power-domain@10024000 {
- compatible = "samsung,exynos4210-pd";
- reg = <0x10024000 0x20>;
- #power-domain-cells = <0>;
- };
-
- pd_tv: tv-power-domain@10024020 {
- compatible = "samsung,exynos4210-pd";
- reg = <0x10024020 0x20>;
- #power-domain-cells = <0>;
- };
-
- pd_mfc: mfc-power-domain@10024040 {
- compatible = "samsung,exynos4210-pd";
- reg = <0x10024040 0x20>;
- #power-domain-cells = <0>;
- };
-
- pd_g3d: g3d-power-domain@10024060 {
- compatible = "samsung,exynos4210-pd";
- reg = <0x10024060 0x20>;
- #power-domain-cells = <0>;
- };
-
- pd_lcd0: lcd0-power-domain@10024080 {
- compatible = "samsung,exynos4210-pd";
- reg = <0x10024080 0x20>;
- #power-domain-cells = <0>;
- };
-
- pd_isp0: isp0-power-domain@100240A0 {
- compatible = "samsung,exynos4210-pd";
- reg = <0x100240A0 0x20>;
- #power-domain-cells = <0>;
- };
-
- pd_isp1: isp1-power-domain@100240E0 {
- compatible = "samsung,exynos4210-pd";
- reg = <0x100240E0 0x20>;
- #power-domain-cells = <0>;
- };
-
- cmu: clock-controller@10030000 {
- compatible = "samsung,exynos4415-cmu";
- reg = <0x10030000 0x18000>;
- #clock-cells = <1>;
- };
-
- rtc: rtc@10070000 {
- compatible = "samsung,s3c6410-rtc";
- reg = <0x10070000 0x100>;
- interrupts = <0 73 0>, <0 74 0>;
- status = "disabled";
- };
-
- mct@10050000 {
- compatible = "samsung,exynos4210-mct";
- reg = <0x10050000 0x800>;
- interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
- <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
- clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
- clock-names = "fin_pll", "mct";
- };
-
- gic: interrupt-controller@10481000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x10481000 0x1000>,
- <0x10482000 0x1000>,
- <0x10484000 0x2000>,
- <0x10486000 0x2000>;
- interrupts = <1 9 0xf04>;
- };
-
- l2c: l2-cache-controller@10502000 {
- compatible = "arm,pl310-cache";
- reg = <0x10502000 0x1000>;
- cache-unified;
- cache-level = <2>;
- arm,tag-latency = <2 2 1>;
- arm,data-latency = <3 2 1>;
- arm,double-linefill = <1>;
- arm,double-linefill-incr = <0>;
- arm,double-linefill-wrap = <1>;
- arm,prefetch-drop = <1>;
- arm,prefetch-offset = <7>;
- };
-
- cmu_dmc: clock-controller@105C0000 {
- compatible = "samsung,exynos4415-cmu-dmc";
- reg = <0x105C0000 0x3000>;
- #clock-cells = <1>;
- };
-
- pinctrl_1: pinctrl@11000000 {
- compatible = "samsung,exynos4415-pinctrl";
- reg = <0x11000000 0x1000>;
- interrupts = <0 225 0>;
-
- wakeup-interrupt-controller {
- compatible = "samsung,exynos4210-wakeup-eint";
- interrupt-parent = <&gic>;
- interrupts = <0 48 0>;
- };
- };
-
- pinctrl_0: pinctrl@11400000 {
- compatible = "samsung,exynos4415-pinctrl";
- reg = <0x11400000 0x1000>;
- interrupts = <0 240 0>;
- };
-
- fimd: fimd@11C00000 {
- compatible = "samsung,exynos4415-fimd";
- reg = <0x11C00000 0x30000>;
- interrupt-names = "fifo", "vsync", "lcd_sys";
- interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
- clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
- clock-names = "sclk_fimd", "fimd";
- samsung,power-domain = <&pd_lcd0>;
- iommus = <&sysmmu_fimd0>;
- samsung,sysreg = <&sysreg_system_controller>;
- status = "disabled";
- };
-
- dsi_0: dsi@11C80000 {
- compatible = "samsung,exynos4415-mipi-dsi";
- reg = <0x11C80000 0x10000>;
- interrupts = <0 83 0>;
- samsung,phy-type = <0>;
- samsung,power-domain = <&pd_lcd0>;
- phys = <&mipi_phy 1>;
- phy-names = "dsim";
- clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
- clock-names = "bus_clk", "pll_clk";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- sysmmu_fimd0: sysmmu@11E20000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x11e20000 0x1000>;
- interrupts = <0 80 0>, <0 81 0>;
- clock-names = "sysmmu", "master";
- clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
- power-domains = <&pd_lcd0>;
- #iommu-cells = <0>;
- };
-
- hsotg: hsotg@12480000 {
- compatible = "samsung,s3c6400-hsotg";
- reg = <0x12480000 0x20000>;
- interrupts = <0 141 0>;
- clocks = <&cmu CLK_USBDEVICE>;
- clock-names = "otg";
- phys = <&exynos_usbphy 0>;
- phy-names = "usb2-phy";
- status = "disabled";
- };
-
- mshc_0: mshc@12510000 {
- compatible = "samsung,exynos5250-dw-mshc";
- reg = <0x12510000 0x1000>;
- interrupts = <0 142 0>;
- clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
- clock-names = "biu", "ciu";
- fifo-depth = <0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- mshc_1: mshc@12520000 {
- compatible = "samsung,exynos5250-dw-mshc";
- reg = <0x12520000 0x1000>;
- interrupts = <0 143 0>;
- clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
- clock-names = "biu", "ciu";
- fifo-depth = <0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- mshc_2: mshc@12530000 {
- compatible = "samsung,exynos5250-dw-mshc";
- reg = <0x12530000 0x1000>;
- interrupts = <0 144 0>;
- clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
- clock-names = "biu", "ciu";
- fifo-depth = <0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- ehci: ehci@12580000 {
- compatible = "samsung,exynos4210-ehci";
- reg = <0x12580000 0x100>;
- interrupts = <0 140 0>;
- clocks = <&cmu CLK_USBHOST>;
- clock-names = "usbhost";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- phys = <&exynos_usbphy 1>;
- status = "disabled";
- };
- port@1 {
- reg = <1>;
- phys = <&exynos_usbphy 2>;
- status = "disabled";
- };
- port@2 {
- reg = <2>;
- phys = <&exynos_usbphy 3>;
- status = "disabled";
- };
- };
-
- ohci: ohci@12590000 {
- compatible = "samsung,exynos4210-ohci";
- reg = <0x12590000 0x100>;
- interrupts = <0 140 0>;
- clocks = <&cmu CLK_USBHOST>;
- clock-names = "usbhost";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- phys = <&exynos_usbphy 1>;
- status = "disabled";
- };
- };
-
- exynos_usbphy: exynos-usbphy@125B0000 {
- compatible = "samsung,exynos4x12-usb2-phy";
- reg = <0x125B0000 0x100>;
- samsung,pmureg-phandle = <&pmu_system_controller>;
- samsung,sysreg-phandle = <&sysreg_system_controller>;
- clocks = <&cmu CLK_USBDEVICE>, <&xusbxti>;
- clock-names = "phy", "ref";
- #phy-cells = <1>;
- status = "disabled";
- };
-
- amba {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&gic>;
- ranges;
-
- pdma0: pdma@12680000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x12680000 0x1000>;
- interrupts = <0 138 0>;
- clocks = <&cmu CLK_PDMA0>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
- };
-
- pdma1: pdma@12690000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x12690000 0x1000>;
- interrupts = <0 139 0>;
- clocks = <&cmu CLK_PDMA1>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
- };
- };
-
- adc: adc@126C0000 {
- compatible = "samsung,exynos3250-adc",
- "samsung,exynos-adc-v2";
- reg = <0x126C0000 0x100>, <0x10020718 0x4>;
- interrupts = <0 137 0>;
- clock-names = "adc", "sclk";
- clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
- #io-channel-cells = <1>;
- io-channel-ranges;
- status = "disabled";
- };
-
- serial_0: serial@13800000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13800000 0x100>;
- interrupts = <0 109 0>;
- clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
- clock-names = "uart", "clk_uart_baud0";
- status = "disabled";
- };
-
- serial_1: serial@13810000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13810000 0x100>;
- interrupts = <0 110 0>;
- clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
- clock-names = "uart", "clk_uart_baud0";
- status = "disabled";
- };
-
- serial_2: serial@13820000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13820000 0x100>;
- interrupts = <0 111 0>;
- clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
- clock-names = "uart", "clk_uart_baud0";
- status = "disabled";
- };
-
- serial_3: serial@13830000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13830000 0x100>;
- interrupts = <0 112 0>;
- clocks = <&cmu CLK_UART3>, <&cmu CLK_SCLK_UART3>;
- clock-names = "uart", "clk_uart_baud0";
- status = "disabled";
- };
-
- i2c_0: i2c@13860000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,s3c2440-i2c";
- reg = <0x13860000 0x100>;
- interrupts = <0 113 0>;
- clocks = <&cmu CLK_I2C0>;
- clock-names = "i2c";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_bus>;
- status = "disabled";
- };
-
- i2c_1: i2c@13870000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,s3c2440-i2c";
- reg = <0x13870000 0x100>;
- interrupts = <0 114 0>;
- clocks = <&cmu CLK_I2C1>;
- clock-names = "i2c";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_bus>;
- status = "disabled";
- };
-
- i2c_2: i2c@13880000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,s3c2440-i2c";
- reg = <0x13880000 0x100>;
- interrupts = <0 115 0>;
- clocks = <&cmu CLK_I2C2>;
- clock-names = "i2c";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_bus>;
- status = "disabled";
- };
-
- i2c_3: i2c@13890000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,s3c2440-i2c";
- reg = <0x13890000 0x100>;
- interrupts = <0 116 0>;
- clocks = <&cmu CLK_I2C3>;
- clock-names = "i2c";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3_bus>;
- status = "disabled";
- };
-
- i2c_4: i2c@138A0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,s3c2440-i2c";
- reg = <0x138A0000 0x100>;
- interrupts = <0 117 0>;
- clocks = <&cmu CLK_I2C4>;
- clock-names = "i2c";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c4_bus>;
- status = "disabled";
- };
-
- i2c_5: i2c@138B0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,s3c2440-i2c";
- reg = <0x138B0000 0x100>;
- interrupts = <0 118 0>;
- clocks = <&cmu CLK_I2C5>;
- clock-names = "i2c";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c5_bus>;
- status = "disabled";
- };
-
- i2c_6: i2c@138C0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,s3c2440-i2c";
- reg = <0x138C0000 0x100>;
- interrupts = <0 119 0>;
- clocks = <&cmu CLK_I2C6>;
- clock-names = "i2c";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c6_bus>;
- status = "disabled";
- };
-
- i2c_7: i2c@138D0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,s3c2440-i2c";
- reg = <0x138D0000 0x100>;
- interrupts = <0 120 0>;
- clocks = <&cmu CLK_I2C7>;
- clock-names = "i2c";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c7_bus>;
- status = "disabled";
- };
-
- spi_0: spi@13920000 {
- compatible = "samsung,exynos4210-spi";
- reg = <0x13920000 0x100>;
- interrupts = <0 121 0>;
- dmas = <&pdma0 7>, <&pdma0 6>;
- dma-names = "tx", "rx";
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
- clock-names = "spi", "spi_busclk0";
- samsung,spi-src-clk = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&spi0_bus>;
- status = "disabled";
- };
-
- spi_1: spi@13930000 {
- compatible = "samsung,exynos4210-spi";
- reg = <0x13930000 0x100>;
- interrupts = <0 122 0>;
- dmas = <&pdma1 7>, <&pdma1 6>;
- dma-names = "tx", "rx";
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
- clock-names = "spi", "spi_busclk0";
- samsung,spi-src-clk = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&spi1_bus>;
- status = "disabled";
- };
-
- spi_2: spi@13940000 {
- compatible = "samsung,exynos4210-spi";
- reg = <0x13940000 0x100>;
- interrupts = <0 123 0>;
- dmas = <&pdma0 9>, <&pdma0 8>;
- dma-names = "tx", "rx";
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cmu CLK_SPI2>, <&cmu CLK_SCLK_SPI2>;
- clock-names = "spi", "spi_busclk0";
- samsung,spi-src-clk = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&spi2_bus>;
- status = "disabled";
- };
-
- clock_audss: clock-controller@03810000 {
- compatible = "samsung,exynos4210-audss-clock";
- reg = <0x03810000 0x0C>;
- #clock-cells = <1>;
- };
-
- i2s0: i2s@3830000 {
- compatible = "samsung,s5pv210-i2s";
- reg = <0x03830000 0x100>;
- interrupts = <0 124 0>;
- clocks = <&clock_audss EXYNOS_I2S_BUS>,
- <&clock_audss EXYNOS_SCLK_I2S>;
- clock-names = "iis", "i2s_opclk0";
- dmas = <&pdma1 10>, <&pdma1 9>, <&pdma1 8>;
- dma-names = "tx", "rx", "tx-sec";
- pinctrl-names = "default";
- pinctrl-0 = <&i2s0_bus>;
- samsung,idma-addr = <0x03000000>;
- status = "disabled";
- };
-
- pwm: pwm@139D0000 {
- compatible = "samsung,exynos4210-pwm";
- reg = <0x139D0000 0x1000>;
- interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
- <0 107 0>, <0 108 0>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pmu {
- compatible = "arm,cortex-a9-pmu";
- interrupts = <0 18 0>, <0 19 0>, <0 20 0>, <0 21 0>;
- };
- };
-};
-
-#include "exynos4415-pinctrl.dtsi"
--
cgit
From 63aee4fa75be5879f0fd34b031f4d5587e354a81 Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzk@kernel.org>
Date: Fri, 16 Sep 2016 21:42:42 +0200
Subject: ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos4
Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and
generates an error:
genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)
The GIC requires shared interrupts to be edge rising or level high.
Platform declares support for both. Arbitrarily choose level high
everywhere hoping it will work on each platform.
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reported-by: Alban Browaeys <alban.browaeys@gmail.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
---
arch/arm/boot/dts/exynos4.dtsi | 94 ++++++++++++++++++++++--------------------
1 file changed, 50 insertions(+), 44 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 5f034eb5a5e2..e6f4da7f0038 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -21,6 +21,7 @@
#include <dt-bindings/clock/exynos4.h>
#include <dt-bindings/clock/exynos-audss-clk.h>
+#include <dt-bindings/interrupt-controller/irq.h>
#include "exynos-syscon-restart.dtsi"
/ {
@@ -168,7 +169,7 @@
dsi_0: dsi@11C80000 {
compatible = "samsung,exynos4210-mipi-dsi";
reg = <0x11C80000 0x10000>;
- interrupts = <0 79 0>;
+ interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_lcd0>;
phys = <&mipi_phy 1>;
phy-names = "dsim";
@@ -191,7 +192,7 @@
fimc_0: fimc@11800000 {
compatible = "samsung,exynos4210-fimc";
reg = <0x11800000 0x1000>;
- interrupts = <0 84 0>;
+ interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>;
clock-names = "fimc", "sclk_fimc";
power-domains = <&pd_cam>;
@@ -203,7 +204,7 @@
fimc_1: fimc@11810000 {
compatible = "samsung,exynos4210-fimc";
reg = <0x11810000 0x1000>;
- interrupts = <0 85 0>;
+ interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>;
clock-names = "fimc", "sclk_fimc";
power-domains = <&pd_cam>;
@@ -215,7 +216,7 @@
fimc_2: fimc@11820000 {
compatible = "samsung,exynos4210-fimc";
reg = <0x11820000 0x1000>;
- interrupts = <0 86 0>;
+ interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>;
clock-names = "fimc", "sclk_fimc";
power-domains = <&pd_cam>;
@@ -227,7 +228,7 @@
fimc_3: fimc@11830000 {
compatible = "samsung,exynos4210-fimc";
reg = <0x11830000 0x1000>;
- interrupts = <0 87 0>;
+ interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>;
clock-names = "fimc", "sclk_fimc";
power-domains = <&pd_cam>;
@@ -239,7 +240,7 @@
csis_0: csis@11880000 {
compatible = "samsung,exynos4210-csis";
reg = <0x11880000 0x4000>;
- interrupts = <0 78 0>;
+ interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>;
clock-names = "csis", "sclk_csis";
bus-width = <4>;
@@ -254,7 +255,7 @@
csis_1: csis@11890000 {
compatible = "samsung,exynos4210-csis";
reg = <0x11890000 0x4000>;
- interrupts = <0 80 0>;
+ interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>;
clock-names = "csis", "sclk_csis";
bus-width = <2>;
@@ -270,7 +271,7 @@
watchdog: watchdog@10060000 {
compatible = "samsung,s3c2410-wdt";
reg = <0x10060000 0x100>;
- interrupts = <0 43 0>;
+ interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_WDT>;
clock-names = "watchdog";
status = "disabled";
@@ -280,7 +281,8 @@
compatible = "samsung,s3c6410-rtc";
reg = <0x10070000 0x100>;
interrupt-parent = <&pmu_system_controller>;
- interrupts = <0 44 0>, <0 45 0>;
+ interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>,
+ <0 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_RTC>;
clock-names = "rtc";
status = "disabled";
@@ -289,7 +291,7 @@
keypad: keypad@100A0000 {
compatible = "samsung,s5pv210-keypad";
reg = <0x100A0000 0x100>;
- interrupts = <0 109 0>;
+ interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_KEYIF>;
clock-names = "keypad";
status = "disabled";
@@ -298,7 +300,7 @@
sdhci_0: sdhci@12510000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12510000 0x100>;
- interrupts = <0 73 0>;
+ interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
clock-names = "hsmmc", "mmc_busclk.2";
status = "disabled";
@@ -307,7 +309,7 @@
sdhci_1: sdhci@12520000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12520000 0x100>;
- interrupts = <0 74 0>;
+ interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
clock-names = "hsmmc", "mmc_busclk.2";
status = "disabled";
@@ -316,7 +318,7 @@
sdhci_2: sdhci@12530000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12530000 0x100>;
- interrupts = <0 75 0>;
+ interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
clock-names = "hsmmc", "mmc_busclk.2";
status = "disabled";
@@ -325,7 +327,7 @@
sdhci_3: sdhci@12540000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12540000 0x100>;
- interrupts = <0 76 0>;
+ interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
clock-names = "hsmmc", "mmc_busclk.2";
status = "disabled";
@@ -344,7 +346,7 @@
hsotg: hsotg@12480000 {
compatible = "samsung,s3c6400-hsotg";
reg = <0x12480000 0x20000>;
- interrupts = <0 71 0>;
+ interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_USB_DEVICE>;
clock-names = "otg";
phys = <&exynos_usbphy 0>;
@@ -355,7 +357,7 @@
ehci: ehci@12580000 {
compatible = "samsung,exynos4210-ehci";
reg = <0x12580000 0x100>;
- interrupts = <0 70 0>;
+ interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_USB_HOST>;
clock-names = "usbhost";
status = "disabled";
@@ -381,7 +383,7 @@
ohci: ohci@12590000 {
compatible = "samsung,exynos4210-ohci";
reg = <0x12590000 0x100>;
- interrupts = <0 70 0>;
+ interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_USB_HOST>;
clock-names = "usbhost";
status = "disabled";
@@ -423,7 +425,7 @@
mfc: codec@13400000 {
compatible = "samsung,mfc-v5";
reg = <0x13400000 0x10000>;
- interrupts = <0 94 0>;
+ interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_mfc>;
clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
clock-names = "mfc", "sclk_mfc";
@@ -434,7 +436,7 @@
serial_0: serial@13800000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13800000 0x100>;
- interrupts = <0 52 0>;
+ interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
clock-names = "uart", "clk_uart_baud0";
dmas = <&pdma0 15>, <&pdma0 16>;
@@ -445,7 +447,7 @@
serial_1: serial@13810000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13810000 0x100>;
- interrupts = <0 53 0>;
+ interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
clock-names = "uart", "clk_uart_baud0";
dmas = <&pdma1 15>, <&pdma1 16>;
@@ -456,7 +458,7 @@
serial_2: serial@13820000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13820000 0x100>;
- interrupts = <0 54 0>;
+ interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
clock-names = "uart", "clk_uart_baud0";
dmas = <&pdma0 17>, <&pdma0 18>;
@@ -467,7 +469,7 @@
serial_3: serial@13830000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13830000 0x100>;
- interrupts = <0 55 0>;
+ interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
clock-names = "uart", "clk_uart_baud0";
dmas = <&pdma1 17>, <&pdma1 18>;
@@ -480,7 +482,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13860000 0x100>;
- interrupts = <0 58 0>;
+ interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C0>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -493,7 +495,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13870000 0x100>;
- interrupts = <0 59 0>;
+ interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C1>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -506,7 +508,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13880000 0x100>;
- interrupts = <0 60 0>;
+ interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C2>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -519,7 +521,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13890000 0x100>;
- interrupts = <0 61 0>;
+ interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C3>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -532,7 +534,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138A0000 0x100>;
- interrupts = <0 62 0>;
+ interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C4>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -545,7 +547,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138B0000 0x100>;
- interrupts = <0 63 0>;
+ interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C5>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -558,7 +560,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138C0000 0x100>;
- interrupts = <0 64 0>;
+ interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C6>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -571,7 +573,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138D0000 0x100>;
- interrupts = <0 65 0>;
+ interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C7>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -584,7 +586,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-hdmiphy-i2c";
reg = <0x138E0000 0x100>;
- interrupts = <0 93 0>;
+ interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C_HDMI>;
clock-names = "i2c";
status = "disabled";
@@ -598,7 +600,7 @@
spi_0: spi@13920000 {
compatible = "samsung,exynos4210-spi";
reg = <0x13920000 0x100>;
- interrupts = <0 66 0>;
+ interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 7>, <&pdma0 6>;
dma-names = "tx", "rx";
#address-cells = <1>;
@@ -613,7 +615,7 @@
spi_1: spi@13930000 {
compatible = "samsung,exynos4210-spi";
reg = <0x13930000 0x100>;
- interrupts = <0 67 0>;
+ interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma1 7>, <&pdma1 6>;
dma-names = "tx", "rx";
#address-cells = <1>;
@@ -628,7 +630,7 @@
spi_2: spi@13940000 {
compatible = "samsung,exynos4210-spi";
reg = <0x13940000 0x100>;
- interrupts = <0 68 0>;
+ interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 9>, <&pdma0 8>;
dma-names = "tx", "rx";
#address-cells = <1>;
@@ -643,7 +645,11 @@
pwm: pwm@139D0000 {
compatible = "samsung,exynos4210-pwm";
reg = <0x139D0000 0x1000>;
- interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>;
+ interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>,
+ <0 38 IRQ_TYPE_LEVEL_HIGH>,
+ <0 39 IRQ_TYPE_LEVEL_HIGH>,
+ <0 40 IRQ_TYPE_LEVEL_HIGH>,
+ <0 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PWM>;
clock-names = "timers";
#pwm-cells = <3>;
@@ -660,7 +666,7 @@
pdma0: pdma@12680000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12680000 0x1000>;
- interrupts = <0 35 0>;
+ interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -671,7 +677,7 @@
pdma1: pdma@12690000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12690000 0x1000>;
- interrupts = <0 36 0>;
+ interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -682,7 +688,7 @@
mdma1: mdma@12850000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12850000 0x1000>;
- interrupts = <0 34 0>;
+ interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MDMA>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -712,7 +718,7 @@
jpeg_codec: jpeg-codec@11840000 {
compatible = "samsung,exynos4210-jpeg";
reg = <0x11840000 0x1000>;
- interrupts = <0 88 0>;
+ interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_JPEG>;
clock-names = "jpeg";
power-domains = <&pd_cam>;
@@ -722,7 +728,7 @@
rotator: rotator@12810000 {
compatible = "samsung,exynos4210-rotator";
reg = <0x12810000 0x64>;
- interrupts = <0 83 0>;
+ interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_ROTATOR>;
clock-names = "rotator";
iommus = <&sysmmu_rotator>;
@@ -731,7 +737,7 @@
hdmi: hdmi@12D00000 {
compatible = "samsung,exynos4210-hdmi";
reg = <0x12D00000 0x70000>;
- interrupts = <0 92 0>;
+ interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy",
"mout_hdmi";
clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
@@ -746,7 +752,7 @@
hdmicec: cec@100B0000 {
compatible = "samsung,s5p-cec";
reg = <0x100B0000 0x200>;
- interrupts = <0 114 0>;
+ interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_HDMI_CEC>;
clock-names = "hdmicec";
samsung,syscon-phandle = <&pmu_system_controller>;
@@ -757,7 +763,7 @@
mixer: mixer@12C10000 {
compatible = "samsung,exynos4210-mixer";
- interrupts = <0 91 0>;
+ interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x12C10000 0x2100>, <0x12c00000 0x300>;
power-domains = <&pd_tv>;
iommus = <&sysmmu_tv>;
@@ -984,7 +990,7 @@
sss: sss@10830000 {
compatible = "samsung,exynos4210-secss";
reg = <0x10830000 0x300>;
- interrupts = <0 112 0>;
+ interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SSS>;
clock-names = "secss";
};
--
cgit
From 71990ea32f1fd4b7242380e46f0febd5c1b9c61c Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzk@kernel.org>
Date: Fri, 16 Sep 2016 21:42:43 +0200
Subject: ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos4210
Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and
generates an error:
genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)
The GIC requires shared interrupts to be edge rising or level high.
Platform declares support for both. Arbitrarily choose level high
everywhere hoping it will work on each platform.
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reported-by: Alban Browaeys <alban.browaeys@gmail.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
---
arch/arm/boot/dts/exynos4210-pinctrl.dtsi | 20 +++++++++++++----
arch/arm/boot/dts/exynos4210.dtsi | 36 ++++++++++++++++++++-----------
2 files changed, 40 insertions(+), 16 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
index d9b6d25e4abe..264b43228cfd 100644
--- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
@@ -537,8 +537,14 @@
interrupt-controller;
interrupt-parent = <&gic>;
- interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
- <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;
+ interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>,
+ <0 17 IRQ_TYPE_LEVEL_HIGH>,
+ <0 18 IRQ_TYPE_LEVEL_HIGH>,
+ <0 19 IRQ_TYPE_LEVEL_HIGH>,
+ <0 20 IRQ_TYPE_LEVEL_HIGH>,
+ <0 21 IRQ_TYPE_LEVEL_HIGH>,
+ <0 22 IRQ_TYPE_LEVEL_HIGH>,
+ <0 23 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
};
@@ -548,8 +554,14 @@
interrupt-controller;
interrupt-parent = <&gic>;
- interrupts = <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
- <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
+ interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>,
+ <0 25 IRQ_TYPE_LEVEL_HIGH>,
+ <0 26 IRQ_TYPE_LEVEL_HIGH>,
+ <0 27 IRQ_TYPE_LEVEL_HIGH>,
+ <0 28 IRQ_TYPE_LEVEL_HIGH>,
+ <0 29 IRQ_TYPE_LEVEL_HIGH>,
+ <0 30 IRQ_TYPE_LEVEL_HIGH>,
+ <0 31 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
};
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 2d9b02967105..736ab8587ab0 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -109,12 +109,12 @@
#interrupt-cells = <1>;
#address-cells = <0>;
#size-cells = <0>;
- interrupt-map = <0 &gic 0 57 0>,
- <1 &gic 0 69 0>,
+ interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
+ <1 &gic 0 69 IRQ_TYPE_LEVEL_HIGH>,
<2 &combiner 12 6>,
<3 &combiner 12 7>,
- <4 &gic 0 42 0>,
- <5 &gic 0 48 0>;
+ <4 &gic 0 42 IRQ_TYPE_LEVEL_HIGH>,
+ <5 &gic 0 48 IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -127,18 +127,18 @@
pinctrl_0: pinctrl@11400000 {
compatible = "samsung,exynos4210-pinctrl";
reg = <0x11400000 0x1000>;
- interrupts = <0 47 0>;
+ interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_1: pinctrl@11000000 {
compatible = "samsung,exynos4210-pinctrl";
reg = <0x11000000 0x1000>;
- interrupts = <0 46 0>;
+ interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
wakup_eint: wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
interrupt-parent = <&gic>;
- interrupts = <0 32 0>;
+ interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -182,7 +182,7 @@
g2d: g2d@12800000 {
compatible = "samsung,s5pv210-g2d";
reg = <0x12800000 0x1000>;
- interrupts = <0 89 0>;
+ interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
clock-names = "sclk_fimg2d", "fimg2d";
power-domains = <&pd_lcd0>;
@@ -424,10 +424,22 @@
&combiner {
samsung,combiner-nr = <16>;
- interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
- <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
- <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
- <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
+ interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
+ <0 1 IRQ_TYPE_LEVEL_HIGH>,
+ <0 2 IRQ_TYPE_LEVEL_HIGH>,
+ <0 3 IRQ_TYPE_LEVEL_HIGH>,
+ <0 4 IRQ_TYPE_LEVEL_HIGH>,
+ <0 5 IRQ_TYPE_LEVEL_HIGH>,
+ <0 6 IRQ_TYPE_LEVEL_HIGH>,
+ <0 7 IRQ_TYPE_LEVEL_HIGH>,
+ <0 8 IRQ_TYPE_LEVEL_HIGH>,
+ <0 9 IRQ_TYPE_LEVEL_HIGH>,
+ <0 10 IRQ_TYPE_LEVEL_HIGH>,
+ <0 11 IRQ_TYPE_LEVEL_HIGH>,
+ <0 12 IRQ_TYPE_LEVEL_HIGH>,
+ <0 13 IRQ_TYPE_LEVEL_HIGH>,
+ <0 14 IRQ_TYPE_LEVEL_HIGH>,
+ <0 15 IRQ_TYPE_LEVEL_HIGH>;
};
&mdma1 {
--
cgit
From 11ebc47cdebb65e91b02fd42a74a9f2e8da56bb3 Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzk@kernel.org>
Date: Fri, 16 Sep 2016 21:42:44 +0200
Subject: ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos4x12
Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and
generates an error:
genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)
The GIC requires shared interrupts to be edge rising or level high.
Platform declares support for both. Arbitrarily choose level high
everywhere hoping it will work on each platform.
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reported-by: Alban Browaeys <alban.browaeys@gmail.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
---
arch/arm/boot/dts/exynos4x12-pinctrl.dtsi | 20 ++++++++++---
arch/arm/boot/dts/exynos4x12.dtsi | 48 ++++++++++++++++++++-----------
2 files changed, 48 insertions(+), 20 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
index a56bf9b1a412..8d7958ecc8e1 100644
--- a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
@@ -572,8 +572,14 @@
interrupt-controller;
interrupt-parent = <&gic>;
- interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
- <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;
+ interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>,
+ <0 17 IRQ_TYPE_LEVEL_HIGH>,
+ <0 18 IRQ_TYPE_LEVEL_HIGH>,
+ <0 19 IRQ_TYPE_LEVEL_HIGH>,
+ <0 20 IRQ_TYPE_LEVEL_HIGH>,
+ <0 21 IRQ_TYPE_LEVEL_HIGH>,
+ <0 22 IRQ_TYPE_LEVEL_HIGH>,
+ <0 23 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
};
@@ -583,8 +589,14 @@
interrupt-controller;
interrupt-parent = <&gic>;
- interrupts = <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
- <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
+ interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>,
+ <0 25 IRQ_TYPE_LEVEL_HIGH>,
+ <0 26 IRQ_TYPE_LEVEL_HIGH>,
+ <0 27 IRQ_TYPE_LEVEL_HIGH>,
+ <0 28 IRQ_TYPE_LEVEL_HIGH>,
+ <0 29 IRQ_TYPE_LEVEL_HIGH>,
+ <0 30 IRQ_TYPE_LEVEL_HIGH>,
+ <0 31 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
};
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index 3394bdcf10ae..2f52b685daf9 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -88,11 +88,11 @@
#interrupt-cells = <1>;
#address-cells = <0>;
#size-cells = <0>;
- interrupt-map = <0 &gic 0 57 0>,
+ interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
<1 &combiner 12 5>,
<2 &combiner 12 6>,
<3 &combiner 12 7>,
- <4 &gic 1 12 0>;
+ <4 &gic 1 12 IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -112,7 +112,7 @@
g2d: g2d@10800000 {
compatible = "samsung,exynos4212-g2d";
reg = <0x10800000 0x1000>;
- interrupts = <0 89 0>;
+ interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
clock-names = "sclk_fimg2d", "fimg2d";
iommus = <&sysmmu_g2d>;
@@ -127,7 +127,7 @@
fimc_lite_0: fimc-lite@12390000 {
compatible = "samsung,exynos4212-fimc-lite";
reg = <0x12390000 0x1000>;
- interrupts = <0 105 0>;
+ interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_isp>;
clocks = <&clock CLK_FIMC_LITE0>;
clock-names = "flite";
@@ -138,7 +138,7 @@
fimc_lite_1: fimc-lite@123A0000 {
compatible = "samsung,exynos4212-fimc-lite";
reg = <0x123A0000 0x1000>;
- interrupts = <0 106 0>;
+ interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_isp>;
clocks = <&clock CLK_FIMC_LITE1>;
clock-names = "flite";
@@ -149,7 +149,8 @@
fimc_is: fimc-is@12000000 {
compatible = "samsung,exynos4212-fimc-is", "simple-bus";
reg = <0x12000000 0x260000>;
- interrupts = <0 90 0>, <0 95 0>;
+ interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>,
+ <0 95 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_isp>;
clocks = <&clock CLK_FIMC_LITE0>,
<&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>,
@@ -200,7 +201,7 @@
mshc_0: mmc@12550000 {
compatible = "samsung,exynos4412-dw-mshc";
reg = <0x12550000 0x1000>;
- interrupts = <0 77 0>;
+ interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
fifo-depth = <0x80>;
@@ -461,11 +462,26 @@
};
&combiner {
- interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
- <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
- <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
- <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
- <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
+ interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
+ <0 1 IRQ_TYPE_LEVEL_HIGH>,
+ <0 2 IRQ_TYPE_LEVEL_HIGH>,
+ <0 3 IRQ_TYPE_LEVEL_HIGH>,
+ <0 4 IRQ_TYPE_LEVEL_HIGH>,
+ <0 5 IRQ_TYPE_LEVEL_HIGH>,
+ <0 6 IRQ_TYPE_LEVEL_HIGH>,
+ <0 7 IRQ_TYPE_LEVEL_HIGH>,
+ <0 8 IRQ_TYPE_LEVEL_HIGH>,
+ <0 9 IRQ_TYPE_LEVEL_HIGH>,
+ <0 10 IRQ_TYPE_LEVEL_HIGH>,
+ <0 11 IRQ_TYPE_LEVEL_HIGH>,
+ <0 12 IRQ_TYPE_LEVEL_HIGH>,
+ <0 13 IRQ_TYPE_LEVEL_HIGH>,
+ <0 14 IRQ_TYPE_LEVEL_HIGH>,
+ <0 15 IRQ_TYPE_LEVEL_HIGH>,
+ <0 107 IRQ_TYPE_LEVEL_HIGH>,
+ <0 108 IRQ_TYPE_LEVEL_HIGH>,
+ <0 48 IRQ_TYPE_LEVEL_HIGH>,
+ <0 42 IRQ_TYPE_LEVEL_HIGH>;
};
&exynos_usbphy {
@@ -529,18 +545,18 @@
&pinctrl_0 {
compatible = "samsung,exynos4x12-pinctrl";
reg = <0x11400000 0x1000>;
- interrupts = <0 47 0>;
+ interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
};
&pinctrl_1 {
compatible = "samsung,exynos4x12-pinctrl";
reg = <0x11000000 0x1000>;
- interrupts = <0 46 0>;
+ interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
wakup_eint: wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
interrupt-parent = <&gic>;
- interrupts = <0 32 0>;
+ interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -554,7 +570,7 @@
&pinctrl_3 {
compatible = "samsung,exynos4x12-pinctrl";
reg = <0x106E0000 0x1000>;
- interrupts = <0 72 0>;
+ interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
};
&pmu_system_controller {
--
cgit
From 89be851108fa9563d21d2bb5cd5664f76612fca2 Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzk@kernel.org>
Date: Fri, 16 Sep 2016 21:42:46 +0200
Subject: ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos3250
Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and
generates an error:
genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)
The GIC requires shared interrupts to be edge rising or level high.
Platform declares support for both. Arbitrarily choose level high
everywhere hoping it will work on each platform.
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reported-by: Alban Browaeys <alban.browaeys@gmail.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
---
arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 20 +++++--
arch/arm/boot/dts/exynos3250.dtsi | 93 ++++++++++++++++++-------------
2 files changed, 71 insertions(+), 42 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
index ec331169c3d9..450127d46acd 100644
--- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
@@ -362,8 +362,14 @@
interrupt-controller;
interrupt-parent = <&gic>;
- interrupts = <0 32 0>, <0 33 0>, <0 34 0>, <0 35 0>,
- <0 36 0>, <0 37 0>, <0 38 0>, <0 39 0>;
+ interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
+ <0 33 IRQ_TYPE_LEVEL_HIGH>,
+ <0 34 IRQ_TYPE_LEVEL_HIGH>,
+ <0 35 IRQ_TYPE_LEVEL_HIGH>,
+ <0 36 IRQ_TYPE_LEVEL_HIGH>,
+ <0 37 IRQ_TYPE_LEVEL_HIGH>,
+ <0 38 IRQ_TYPE_LEVEL_HIGH>,
+ <0 39 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
};
@@ -373,8 +379,14 @@
interrupt-controller;
interrupt-parent = <&gic>;
- interrupts = <0 40 0>, <0 41 0>, <0 42 0>, <0 43 0>,
- <0 44 0>, <0 45 0>, <0 46 0>, <0 47 0>;
+ interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>,
+ <0 41 IRQ_TYPE_LEVEL_HIGH>,
+ <0 42 IRQ_TYPE_LEVEL_HIGH>,
+ <0 43 IRQ_TYPE_LEVEL_HIGH>,
+ <0 44 IRQ_TYPE_LEVEL_HIGH>,
+ <0 45 IRQ_TYPE_LEVEL_HIGH>,
+ <0 46 IRQ_TYPE_LEVEL_HIGH>,
+ <0 47 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
};
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index e9d2556c0dfd..9703d81d1eb3 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -20,6 +20,7 @@
#include "exynos4-cpu-thermal.dtsi"
#include "exynos-syscon-restart.dtsi"
#include <dt-bindings/clock/exynos3250.h>
+#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "samsung,exynos3250";
@@ -211,7 +212,8 @@
rtc: rtc@10070000 {
compatible = "samsung,s3c6410-rtc";
reg = <0x10070000 0x100>;
- interrupts = <0 73 0>, <0 74 0>;
+ interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>,
+ <0 74 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&pmu_system_controller>;
status = "disabled";
};
@@ -219,7 +221,7 @@
tmu: tmu@100C0000 {
compatible = "samsung,exynos3250-tmu";
reg = <0x100C0000 0x100>;
- interrupts = <0 216 0>;
+ interrupts = <0 216 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_TMU_APBIF>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
@@ -240,8 +242,14 @@
mct@10050000 {
compatible = "samsung,exynos4210-mct";
reg = <0x10050000 0x800>;
- interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
- <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
+ interrupts = <0 218 IRQ_TYPE_LEVEL_HIGH>,
+ <0 219 IRQ_TYPE_LEVEL_HIGH>,
+ <0 220 IRQ_TYPE_LEVEL_HIGH>,
+ <0 221 IRQ_TYPE_LEVEL_HIGH>,
+ <0 223 IRQ_TYPE_LEVEL_HIGH>,
+ <0 226 IRQ_TYPE_LEVEL_HIGH>,
+ <0 227 IRQ_TYPE_LEVEL_HIGH>,
+ <0 228 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
clock-names = "fin_pll", "mct";
};
@@ -249,24 +257,24 @@
pinctrl_1: pinctrl@11000000 {
compatible = "samsung,exynos3250-pinctrl";
reg = <0x11000000 0x1000>;
- interrupts = <0 225 0>;
+ interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
- interrupts = <0 48 0>;
+ interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
};
};
pinctrl_0: pinctrl@11400000 {
compatible = "samsung,exynos3250-pinctrl";
reg = <0x11400000 0x1000>;
- interrupts = <0 240 0>;
+ interrupts = <0 240 IRQ_TYPE_LEVEL_HIGH>;
};
jpeg: codec@11830000 {
compatible = "samsung,exynos3250-jpeg";
reg = <0x11830000 0x1000>;
- interrupts = <0 171 0>;
+ interrupts = <0 171 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
clock-names = "jpeg", "sclk";
power-domains = <&pd_cam>;
@@ -280,7 +288,8 @@
sysmmu_jpeg: sysmmu@11A60000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11a60000 0x1000>;
- interrupts = <0 156 0>, <0 161 0>;
+ interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>,
+ <0 161 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu", "master";
clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
power-domains = <&pd_cam>;
@@ -291,7 +300,9 @@
compatible = "samsung,exynos3250-fimd";
reg = <0x11c00000 0x30000>;
interrupt-names = "fifo", "vsync", "lcd_sys";
- interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
+ interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>,
+ <0 85 IRQ_TYPE_LEVEL_HIGH>,
+ <0 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
clock-names = "sclk_fimd", "fimd";
power-domains = <&pd_lcd0>;
@@ -303,7 +314,7 @@
dsi_0: dsi@11C80000 {
compatible = "samsung,exynos3250-mipi-dsi";
reg = <0x11C80000 0x10000>;
- interrupts = <0 83 0>;
+ interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
samsung,phy-type = <0>;
power-domains = <&pd_lcd0>;
phys = <&mipi_phy 1>;
@@ -318,7 +329,8 @@
sysmmu_fimd0: sysmmu@11E20000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11e20000 0x1000>;
- interrupts = <0 80 0>, <0 81 0>;
+ interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>,
+ <0 81 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu", "master";
clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
power-domains = <&pd_lcd0>;
@@ -328,7 +340,7 @@
hsotg: hsotg@12480000 {
compatible = "snps,dwc2";
reg = <0x12480000 0x20000>;
- interrupts = <0 141 0>;
+ interrupts = <0 141 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_USBOTG>;
clock-names = "otg";
phys = <&exynos_usbphy 0>;
@@ -339,7 +351,7 @@
mshc_0: mshc@12510000 {
compatible = "samsung,exynos5420-dw-mshc";
reg = <0x12510000 0x1000>;
- interrupts = <0 142 0>;
+ interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
clock-names = "biu", "ciu";
fifo-depth = <0x80>;
@@ -351,7 +363,7 @@
mshc_1: mshc@12520000 {
compatible = "samsung,exynos5420-dw-mshc";
reg = <0x12520000 0x1000>;
- interrupts = <0 143 0>;
+ interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
clock-names = "biu", "ciu";
fifo-depth = <0x80>;
@@ -363,7 +375,7 @@
mshc_2: mshc@12530000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12530000 0x1000>;
- interrupts = <0 144 0>;
+ interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
clock-names = "biu", "ciu";
fifo-depth = <0x80>;
@@ -391,7 +403,7 @@
pdma0: pdma@12680000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12680000 0x1000>;
- interrupts = <0 138 0>;
+ interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -402,7 +414,7 @@
pdma1: pdma@12690000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12690000 0x1000>;
- interrupts = <0 139 0>;
+ interrupts = <0 139 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -415,7 +427,7 @@
compatible = "samsung,exynos3250-adc",
"samsung,exynos-adc-v2";
reg = <0x126C0000 0x100>;
- interrupts = <0 137 0>;
+ interrupts = <0 137 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "adc", "sclk";
clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
#io-channel-cells = <1>;
@@ -427,7 +439,7 @@
mfc: codec@13400000 {
compatible = "samsung,mfc-v7";
reg = <0x13400000 0x10000>;
- interrupts = <0 102 0>;
+ interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "mfc", "sclk_mfc";
clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
power-domains = <&pd_mfc>;
@@ -437,7 +449,8 @@
sysmmu_mfc: sysmmu@13620000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13620000 0x1000>;
- interrupts = <0 96 0>, <0 98 0>;
+ interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>,
+ <0 98 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu", "master";
clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
power-domains = <&pd_mfc>;
@@ -447,7 +460,7 @@
serial_0: serial@13800000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13800000 0x100>;
- interrupts = <0 109 0>;
+ interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
clock-names = "uart", "clk_uart_baud0";
pinctrl-names = "default";
@@ -458,7 +471,7 @@
serial_1: serial@13810000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13810000 0x100>;
- interrupts = <0 110 0>;
+ interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
clock-names = "uart", "clk_uart_baud0";
pinctrl-names = "default";
@@ -469,7 +482,7 @@
serial_2: serial@13820000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13820000 0x100>;
- interrupts = <0 111 0>;
+ interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
clock-names = "uart", "clk_uart_baud0";
pinctrl-names = "default";
@@ -482,7 +495,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13860000 0x100>;
- interrupts = <0 113 0>;
+ interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C0>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -495,7 +508,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13870000 0x100>;
- interrupts = <0 114 0>;
+ interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C1>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -508,7 +521,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13880000 0x100>;
- interrupts = <0 115 0>;
+ interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C2>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -521,7 +534,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13890000 0x100>;
- interrupts = <0 116 0>;
+ interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C3>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -534,7 +547,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138A0000 0x100>;
- interrupts = <0 117 0>;
+ interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C4>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -547,7 +560,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138B0000 0x100>;
- interrupts = <0 118 0>;
+ interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C5>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -560,7 +573,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138C0000 0x100>;
- interrupts = <0 119 0>;
+ interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C6>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -573,7 +586,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138D0000 0x100>;
- interrupts = <0 120 0>;
+ interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C7>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -584,7 +597,7 @@
spi_0: spi@13920000 {
compatible = "samsung,exynos4210-spi";
reg = <0x13920000 0x100>;
- interrupts = <0 121 0>;
+ interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 7>, <&pdma0 6>;
dma-names = "tx", "rx";
#address-cells = <1>;
@@ -600,7 +613,7 @@
spi_1: spi@13930000 {
compatible = "samsung,exynos4210-spi";
reg = <0x13930000 0x100>;
- interrupts = <0 122 0>;
+ interrupts = <0 122 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma1 7>, <&pdma1 6>;
dma-names = "tx", "rx";
#address-cells = <1>;
@@ -616,7 +629,7 @@
i2s2: i2s@13970000 {
compatible = "samsung,s3c6410-i2s";
reg = <0x13970000 0x100>;
- interrupts = <0 126 0>;
+ interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
clock-names = "iis", "i2s_opclk0";
dmas = <&pdma0 14>, <&pdma0 13>;
@@ -629,15 +642,19 @@
pwm: pwm@139D0000 {
compatible = "samsung,exynos4210-pwm";
reg = <0x139D0000 0x1000>;
- interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
- <0 107 0>, <0 108 0>;
+ interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>,
+ <0 105 IRQ_TYPE_LEVEL_HIGH>,
+ <0 106 IRQ_TYPE_LEVEL_HIGH>,
+ <0 107 IRQ_TYPE_LEVEL_HIGH>,
+ <0 108 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
status = "disabled";
};
pmu {
compatible = "arm,cortex-a7-pmu";
- interrupts = <0 18 0>, <0 19 0>;
+ interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>,
+ <0 19 IRQ_TYPE_LEVEL_HIGH>;
};
ppmu_dmc0: ppmu_dmc0@106a0000 {
--
cgit
From 12a5e2b17f9b3f7d997ea13ceb26969ec5d66342 Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzk@kernel.org>
Date: Fri, 16 Sep 2016 21:42:47 +0200
Subject: ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos5
Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and
generates an error:
genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)
The GIC requires shared interrupts to be edge rising or level high.
Platform declares support for both. Arbitrarily choose level high
everywhere hoping it will work on each platform.
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reported-by: Alban Browaeys <alban.browaeys@gmail.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Tested-by: Alim Akhtar <alim.akhtar@samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
---
arch/arm/boot/dts/exynos5.dtsi | 60 ++++++++++++++++++++++++++++++------------
1 file changed, 43 insertions(+), 17 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 8f06609879f5..d9b1607db5ad 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -13,6 +13,7 @@
* published by the Free Software Foundation.
*/
+#include <dt-bindings/interrupt-controller/irq.h>
#include "exynos-syscon-restart.dtsi"
/ {
@@ -53,14 +54,38 @@
interrupt-controller;
samsung,combiner-nr = <32>;
reg = <0x10440000 0x1000>;
- interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
- <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
- <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
- <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
- <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
- <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
- <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
- <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
+ interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
+ <0 1 IRQ_TYPE_LEVEL_HIGH>,
+ <0 2 IRQ_TYPE_LEVEL_HIGH>,
+ <0 3 IRQ_TYPE_LEVEL_HIGH>,
+ <0 4 IRQ_TYPE_LEVEL_HIGH>,
+ <0 5 IRQ_TYPE_LEVEL_HIGH>,
+ <0 6 IRQ_TYPE_LEVEL_HIGH>,
+ <0 7 IRQ_TYPE_LEVEL_HIGH>,
+ <0 8 IRQ_TYPE_LEVEL_HIGH>,
+ <0 9 IRQ_TYPE_LEVEL_HIGH>,
+ <0 10 IRQ_TYPE_LEVEL_HIGH>,
+ <0 11 IRQ_TYPE_LEVEL_HIGH>,
+ <0 12 IRQ_TYPE_LEVEL_HIGH>,
+ <0 13 IRQ_TYPE_LEVEL_HIGH>,
+ <0 14 IRQ_TYPE_LEVEL_HIGH>,
+ <0 15 IRQ_TYPE_LEVEL_HIGH>,
+ <0 16 IRQ_TYPE_LEVEL_HIGH>,
+ <0 17 IRQ_TYPE_LEVEL_HIGH>,
+ <0 18 IRQ_TYPE_LEVEL_HIGH>,
+ <0 19 IRQ_TYPE_LEVEL_HIGH>,
+ <0 20 IRQ_TYPE_LEVEL_HIGH>,
+ <0 21 IRQ_TYPE_LEVEL_HIGH>,
+ <0 22 IRQ_TYPE_LEVEL_HIGH>,
+ <0 23 IRQ_TYPE_LEVEL_HIGH>,
+ <0 24 IRQ_TYPE_LEVEL_HIGH>,
+ <0 25 IRQ_TYPE_LEVEL_HIGH>,
+ <0 26 IRQ_TYPE_LEVEL_HIGH>,
+ <0 27 IRQ_TYPE_LEVEL_HIGH>,
+ <0 28 IRQ_TYPE_LEVEL_HIGH>,
+ <0 29 IRQ_TYPE_LEVEL_HIGH>,
+ <0 30 IRQ_TYPE_LEVEL_HIGH>,
+ <0 31 IRQ_TYPE_LEVEL_HIGH>;
};
gic: interrupt-controller@10481000 {
@@ -82,31 +107,31 @@
serial_0: serial@12C00000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C00000 0x100>;
- interrupts = <0 51 0>;
+ interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
};
serial_1: serial@12C10000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C10000 0x100>;
- interrupts = <0 52 0>;
+ interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
};
serial_2: serial@12C20000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C20000 0x100>;
- interrupts = <0 53 0>;
+ interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>;
};
serial_3: serial@12C30000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C30000 0x100>;
- interrupts = <0 54 0>;
+ interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
};
i2c_0: i2c@12C60000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C60000 0x100>;
- interrupts = <0 56 0>;
+ interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
samsung,sysreg-phandle = <&sysreg_system_controller>;
@@ -116,7 +141,7 @@
i2c_1: i2c@12C70000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C70000 0x100>;
- interrupts = <0 57 0>;
+ interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
samsung,sysreg-phandle = <&sysreg_system_controller>;
@@ -126,7 +151,7 @@
i2c_2: i2c@12C80000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C80000 0x100>;
- interrupts = <0 58 0>;
+ interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
samsung,sysreg-phandle = <&sysreg_system_controller>;
@@ -136,7 +161,7 @@
i2c_3: i2c@12C90000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C90000 0x100>;
- interrupts = <0 59 0>;
+ interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
samsung,sysreg-phandle = <&sysreg_system_controller>;
@@ -153,7 +178,8 @@
rtc: rtc@101E0000 {
compatible = "samsung,s3c6410-rtc";
reg = <0x101E0000 0x100>;
- interrupts = <0 43 0>, <0 44 0>;
+ interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>,
+ <0 44 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
--
cgit
From 27e64b27b688cae59fdcf339a90b29f6d14809d5 Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzk@kernel.org>
Date: Fri, 16 Sep 2016 21:42:48 +0200
Subject: ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos5250
Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and
generates an error:
genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)
The GIC requires shared interrupts to be edge rising or level high.
Platform declares support for both. Arbitrarily choose level high
everywhere hoping it will work on each platform.
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reported-by: Alban Browaeys <alban.browaeys@gmail.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
---
arch/arm/boot/dts/exynos5250.dtsi | 80 +++++++++++++++++++--------------------
1 file changed, 40 insertions(+), 40 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index f7357d99b47c..4e00c0d06c67 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -181,8 +181,8 @@
<0x1 0 &combiner 23 4>,
<0x2 0 &combiner 25 2>,
<0x3 0 &combiner 25 3>,
- <0x4 0 &gic 0 120 0>,
- <0x5 0 &gic 0 121 0>;
+ <0x4 0 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>,
+ <0x5 0 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -195,31 +195,31 @@
pinctrl_0: pinctrl@11400000 {
compatible = "samsung,exynos5250-pinctrl";
reg = <0x11400000 0x1000>;
- interrupts = <0 46 0>;
+ interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
wakup_eint: wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
interrupt-parent = <&gic>;
- interrupts = <0 32 0>;
+ interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
};
};
pinctrl_1: pinctrl@13400000 {
compatible = "samsung,exynos5250-pinctrl";
reg = <0x13400000 0x1000>;
- interrupts = <0 45 0>;
+ interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_2: pinctrl@10d10000 {
compatible = "samsung,exynos5250-pinctrl";
reg = <0x10d10000 0x1000>;
- interrupts = <0 50 0>;
+ interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_3: pinctrl@03860000 {
compatible = "samsung,exynos5250-pinctrl";
reg = <0x03860000 0x1000>;
- interrupts = <0 47 0>;
+ interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
};
pmu_system_controller: system-controller@10040000 {
@@ -236,7 +236,7 @@
watchdog@101D0000 {
compatible = "samsung,exynos5250-wdt";
reg = <0x101D0000 0x100>;
- interrupts = <0 42 0>;
+ interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_WDT>;
clock-names = "watchdog";
samsung,syscon-phandle = <&pmu_system_controller>;
@@ -245,7 +245,7 @@
g2d@10850000 {
compatible = "samsung,exynos5250-g2d";
reg = <0x10850000 0x1000>;
- interrupts = <0 91 0>;
+ interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_G2D>;
clock-names = "fimg2d";
iommus = <&sysmmu_g2d>;
@@ -254,7 +254,7 @@
mfc: codec@11000000 {
compatible = "samsung,mfc-v6";
reg = <0x11000000 0x10000>;
- interrupts = <0 96 0>;
+ interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_mfc>;
clocks = <&clock CLK_MFC>;
clock-names = "mfc";
@@ -265,7 +265,7 @@
rotator: rotator@11C00000 {
compatible = "samsung,exynos5250-rotator";
reg = <0x11C00000 0x64>;
- interrupts = <0 84 0>;
+ interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_ROTATOR>;
clock-names = "rotator";
iommus = <&sysmmu_rotator>;
@@ -274,7 +274,7 @@
tmu: tmu@10060000 {
compatible = "samsung,exynos5250-tmu";
reg = <0x10060000 0x100>;
- interrupts = <0 65 0>;
+ interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
@@ -284,7 +284,7 @@
compatible = "snps,dwc-ahci";
samsung,sata-freq = <66>;
reg = <0x122F0000 0x1ff>;
- interrupts = <0 115 0>;
+ interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
clock-names = "sata", "sclk_sata";
phys = <&sata_phy>;
@@ -306,7 +306,7 @@
i2c_4: i2c@12CA0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CA0000 0x100>;
- interrupts = <0 60 0>;
+ interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_I2C4>;
@@ -319,7 +319,7 @@
i2c_5: i2c@12CB0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CB0000 0x100>;
- interrupts = <0 61 0>;
+ interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_I2C5>;
@@ -332,7 +332,7 @@
i2c_6: i2c@12CC0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CC0000 0x100>;
- interrupts = <0 62 0>;
+ interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_I2C6>;
@@ -345,7 +345,7 @@
i2c_7: i2c@12CD0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CD0000 0x100>;
- interrupts = <0 63 0>;
+ interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_I2C7>;
@@ -358,7 +358,7 @@
i2c_8: i2c@12CE0000 {
compatible = "samsung,s3c2440-hdmiphy-i2c";
reg = <0x12CE0000 0x1000>;
- interrupts = <0 64 0>;
+ interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_I2C_HDMI>;
@@ -380,7 +380,7 @@
compatible = "samsung,exynos4210-spi";
status = "disabled";
reg = <0x12d20000 0x100>;
- interrupts = <0 66 0>;
+ interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 5
&pdma0 4>;
dma-names = "tx", "rx";
@@ -396,7 +396,7 @@
compatible = "samsung,exynos4210-spi";
status = "disabled";
reg = <0x12d30000 0x100>;
- interrupts = <0 67 0>;
+ interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma1 5
&pdma1 4>;
dma-names = "tx", "rx";
@@ -412,7 +412,7 @@
compatible = "samsung,exynos4210-spi";
status = "disabled";
reg = <0x12d40000 0x100>;
- interrupts = <0 68 0>;
+ interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 7
&pdma0 6>;
dma-names = "tx", "rx";
@@ -426,7 +426,7 @@
mmc_0: mmc@12200000 {
compatible = "samsung,exynos5250-dw-mshc";
- interrupts = <0 75 0>;
+ interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x12200000 0x1000>;
@@ -438,7 +438,7 @@
mmc_1: mmc@12210000 {
compatible = "samsung,exynos5250-dw-mshc";
- interrupts = <0 76 0>;
+ interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x12210000 0x1000>;
@@ -450,7 +450,7 @@
mmc_2: mmc@12220000 {
compatible = "samsung,exynos5250-dw-mshc";
- interrupts = <0 77 0>;
+ interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x12220000 0x1000>;
@@ -463,7 +463,7 @@
mmc_3: mmc@12230000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12230000 0x1000>;
- interrupts = <0 78 0>;
+ interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
@@ -526,7 +526,7 @@
usbdrd_dwc3: dwc3@12000000 {
compatible = "synopsys,dwc3";
reg = <0x12000000 0x10000>;
- interrupts = <0 72 0>;
+ interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
phy-names = "usb2-phy", "usb3-phy";
};
@@ -544,7 +544,7 @@
ehci: usb@12110000 {
compatible = "samsung,exynos4210-ehci";
reg = <0x12110000 0x100>;
- interrupts = <0 71 0>;
+ interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_USB2>;
clock-names = "usbhost";
@@ -559,7 +559,7 @@
ohci: usb@12120000 {
compatible = "samsung,exynos4210-ohci";
reg = <0x12120000 0x100>;
- interrupts = <0 71 0>;
+ interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_USB2>;
clock-names = "usbhost";
@@ -591,7 +591,7 @@
pdma0: pdma@121A0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x121A0000 0x1000>;
- interrupts = <0 34 0>;
+ interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -602,7 +602,7 @@
pdma1: pdma@121B0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x121B0000 0x1000>;
- interrupts = <0 35 0>;
+ interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -613,7 +613,7 @@
mdma0: mdma@10800000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x10800000 0x1000>;
- interrupts = <0 33 0>;
+ interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -624,7 +624,7 @@
mdma1: mdma@11C10000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x11C10000 0x1000>;
- interrupts = <0 124 0>;
+ interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -636,7 +636,7 @@
gsc_0: gsc@13e00000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e00000 0x1000>;
- interrupts = <0 85 0>;
+ interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_gsc>;
clocks = <&clock CLK_GSCL0>;
clock-names = "gscl";
@@ -646,7 +646,7 @@
gsc_1: gsc@13e10000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e10000 0x1000>;
- interrupts = <0 86 0>;
+ interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_gsc>;
clocks = <&clock CLK_GSCL1>;
clock-names = "gscl";
@@ -656,7 +656,7 @@
gsc_2: gsc@13e20000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e20000 0x1000>;
- interrupts = <0 87 0>;
+ interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_gsc>;
clocks = <&clock CLK_GSCL2>;
clock-names = "gscl";
@@ -666,7 +666,7 @@
gsc_3: gsc@13e30000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e30000 0x1000>;
- interrupts = <0 88 0>;
+ interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_gsc>;
clocks = <&clock CLK_GSCL3>;
clock-names = "gscl";
@@ -677,7 +677,7 @@
compatible = "samsung,exynos4212-hdmi";
reg = <0x14530000 0x70000>;
power-domains = <&pd_disp1>;
- interrupts = <0 95 0>;
+ interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
<&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
<&clock CLK_MOUT_HDMI>;
@@ -690,7 +690,7 @@
compatible = "samsung,exynos5250-mixer";
reg = <0x14450000 0x10000>;
power-domains = <&pd_disp1>;
- interrupts = <0 94 0>;
+ interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
<&clock CLK_SCLK_HDMI>;
clock-names = "mixer", "hdmi", "sclk_hdmi";
@@ -706,7 +706,7 @@
adc: adc@12D10000 {
compatible = "samsung,exynos-adc-v1";
reg = <0x12D10000 0x100>;
- interrupts = <0 106 0>;
+ interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_ADC>;
clock-names = "adc";
#io-channel-cells = <1>;
@@ -718,7 +718,7 @@
sss@10830000 {
compatible = "samsung,exynos4210-secss";
reg = <0x10830000 0x300>;
- interrupts = <0 112 0>;
+ interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SSS>;
clock-names = "secss";
};
--
cgit
From 6abdf8d135b77693e6f3f4ad8212bcbc6434eb2b Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzk@kernel.org>
Date: Fri, 16 Sep 2016 21:42:49 +0200
Subject: ARM: dts: exynos: Fix invalid GIC interrupt flags in
exynos5410/exynos542x
Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and
generates an error:
genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)
The GIC requires shared interrupts to be edge rising or level high.
Platform declares support for both. Arbitrarily choose level high
everywhere hoping it will work on each platform.
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reported-by: Alban Browaeys <alban.browaeys@gmail.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
---
arch/arm/boot/dts/exynos5410.dtsi | 26 ++++++-------
arch/arm/boot/dts/exynos5420.dtsi | 78 +++++++++++++++++++--------------------
arch/arm/boot/dts/exynos54xx.dtsi | 34 ++++++++---------
3 files changed, 69 insertions(+), 69 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
index 137f48464f8b..dae5715b41b9 100644
--- a/arch/arm/boot/dts/exynos5410.dtsi
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -85,7 +85,7 @@
tmu_cpu0: tmu@10060000 {
compatible = "samsung,exynos5420-tmu";
reg = <0x10060000 0x100>;
- interrupts = <GIC_SPI 65 0>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
@@ -94,7 +94,7 @@
tmu_cpu1: tmu@10064000 {
compatible = "samsung,exynos5420-tmu";
reg = <0x10064000 0x100>;
- interrupts = <GIC_SPI 183 0>;
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
@@ -103,7 +103,7 @@
tmu_cpu2: tmu@10068000 {
compatible = "samsung,exynos5420-tmu";
reg = <0x10068000 0x100>;
- interrupts = <GIC_SPI 184 0>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
@@ -112,7 +112,7 @@
tmu_cpu3: tmu@1006c000 {
compatible = "samsung,exynos5420-tmu";
reg = <0x1006c000 0x100>;
- interrupts = <GIC_SPI 185 0>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
@@ -121,7 +121,7 @@
mmc_0: mmc@12200000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12200000 0x1000>;
- interrupts = <0 75 0>;
+ interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
@@ -133,7 +133,7 @@
mmc_1: mmc@12210000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12210000 0x1000>;
- interrupts = <0 76 0>;
+ interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
@@ -145,7 +145,7 @@
mmc_2: mmc@12220000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12220000 0x1000>;
- interrupts = <0 77 0>;
+ interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
@@ -157,31 +157,31 @@
pinctrl_0: pinctrl@13400000 {
compatible = "samsung,exynos5410-pinctrl";
reg = <0x13400000 0x1000>;
- interrupts = <0 45 0>;
+ interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
interrupt-parent = <&gic>;
- interrupts = <0 32 0>;
+ interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
};
};
pinctrl_1: pinctrl@14000000 {
compatible = "samsung,exynos5410-pinctrl";
reg = <0x14000000 0x1000>;
- interrupts = <0 46 0>;
+ interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_2: pinctrl@10d10000 {
compatible = "samsung,exynos5410-pinctrl";
reg = <0x10d10000 0x1000>;
- interrupts = <0 50 0>;
+ interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_3: pinctrl@03860000 {
compatible = "samsung,exynos5410-pinctrl";
reg = <0x03860000 0x1000>;
- interrupts = <0 47 0>;
+ interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -329,7 +329,7 @@
};
&usbdrd_dwc3_1 {
- interrupts = <GIC_SPI 200 0>;
+ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
};
&usbdrd_phy1 {
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 00c4cfa54839..906a1a42a7ea 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -193,7 +193,7 @@
mfc: codec@11000000 {
compatible = "samsung,mfc-v7";
reg = <0x11000000 0x10000>;
- interrupts = <0 96 0>;
+ interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MFC>;
clock-names = "mfc";
power-domains = <&mfc_pd>;
@@ -203,7 +203,7 @@
mmc_0: mmc@12200000 {
compatible = "samsung,exynos5420-dw-mshc-smu";
- interrupts = <0 75 0>;
+ interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x12200000 0x2000>;
@@ -215,7 +215,7 @@
mmc_1: mmc@12210000 {
compatible = "samsung,exynos5420-dw-mshc-smu";
- interrupts = <0 76 0>;
+ interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x12210000 0x2000>;
@@ -227,7 +227,7 @@
mmc_2: mmc@12220000 {
compatible = "samsung,exynos5420-dw-mshc";
- interrupts = <0 77 0>;
+ interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x12220000 0x1000>;
@@ -320,37 +320,37 @@
pinctrl_0: pinctrl@13400000 {
compatible = "samsung,exynos5420-pinctrl";
reg = <0x13400000 0x1000>;
- interrupts = <0 45 0>;
+ interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
interrupt-parent = <&gic>;
- interrupts = <0 32 0>;
+ interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
};
};
pinctrl_1: pinctrl@13410000 {
compatible = "samsung,exynos5420-pinctrl";
reg = <0x13410000 0x1000>;
- interrupts = <0 78 0>;
+ interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_2: pinctrl@14000000 {
compatible = "samsung,exynos5420-pinctrl";
reg = <0x14000000 0x1000>;
- interrupts = <0 46 0>;
+ interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_3: pinctrl@14010000 {
compatible = "samsung,exynos5420-pinctrl";
reg = <0x14010000 0x1000>;
- interrupts = <0 50 0>;
+ interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_4: pinctrl@03860000 {
compatible = "samsung,exynos5420-pinctrl";
reg = <0x03860000 0x1000>;
- interrupts = <0 47 0>;
+ interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
};
amba {
@@ -363,7 +363,7 @@
adma: adma@03880000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x03880000 0x1000>;
- interrupts = <0 110 0>;
+ interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_audss EXYNOS_ADMA>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -374,7 +374,7 @@
pdma0: pdma@121A0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x121A0000 0x1000>;
- interrupts = <0 34 0>;
+ interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -385,7 +385,7 @@
pdma1: pdma@121B0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x121B0000 0x1000>;
- interrupts = <0 35 0>;
+ interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -396,7 +396,7 @@
mdma0: mdma@10800000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x10800000 0x1000>;
- interrupts = <0 33 0>;
+ interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -407,7 +407,7 @@
mdma1: mdma@11C10000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x11C10000 0x1000>;
- interrupts = <0 124 0>;
+ interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -479,7 +479,7 @@
spi_0: spi@12d20000 {
compatible = "samsung,exynos4210-spi";
reg = <0x12d20000 0x100>;
- interrupts = <0 68 0>;
+ interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 5
&pdma0 4>;
dma-names = "tx", "rx";
@@ -495,7 +495,7 @@
spi_1: spi@12d30000 {
compatible = "samsung,exynos4210-spi";
reg = <0x12d30000 0x100>;
- interrupts = <0 69 0>;
+ interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma1 5
&pdma1 4>;
dma-names = "tx", "rx";
@@ -511,7 +511,7 @@
spi_2: spi@12d40000 {
compatible = "samsung,exynos4210-spi";
reg = <0x12d40000 0x100>;
- interrupts = <0 70 0>;
+ interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 7
&pdma0 6>;
dma-names = "tx", "rx";
@@ -539,7 +539,7 @@
dsi@14500000 {
compatible = "samsung,exynos5410-mipi-dsi";
reg = <0x14500000 0x10000>;
- interrupts = <0 82 0>;
+ interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
phys = <&mipi_phy 1>;
phy-names = "dsim";
clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
@@ -552,7 +552,7 @@
adc: adc@12D10000 {
compatible = "samsung,exynos-adc-v2";
reg = <0x12D10000 0x100>;
- interrupts = <0 106 0>;
+ interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TSADC>;
clock-names = "adc";
#io-channel-cells = <1>;
@@ -564,7 +564,7 @@
hsi2c_8: i2c@12E00000 {
compatible = "samsung,exynos5250-hsi2c";
reg = <0x12E00000 0x1000>;
- interrupts = <0 87 0>;
+ interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
@@ -577,7 +577,7 @@
hsi2c_9: i2c@12E10000 {
compatible = "samsung,exynos5250-hsi2c";
reg = <0x12E10000 0x1000>;
- interrupts = <0 88 0>;
+ interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
@@ -590,7 +590,7 @@
hsi2c_10: i2c@12E20000 {
compatible = "samsung,exynos5250-hsi2c";
reg = <0x12E20000 0x1000>;
- interrupts = <0 203 0>;
+ interrupts = <0 203 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
@@ -603,7 +603,7 @@
hdmi: hdmi@14530000 {
compatible = "samsung,exynos5420-hdmi";
reg = <0x14530000 0x70000>;
- interrupts = <0 95 0>;
+ interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
<&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
<&clock CLK_MOUT_HDMI>;
@@ -622,7 +622,7 @@
mixer: mixer@14450000 {
compatible = "samsung,exynos5420-mixer";
reg = <0x14450000 0x10000>;
- interrupts = <0 94 0>;
+ interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
<&clock CLK_SCLK_HDMI>;
clock-names = "mixer", "hdmi", "sclk_hdmi";
@@ -633,7 +633,7 @@
rotator: rotator@11C00000 {
compatible = "samsung,exynos5250-rotator";
reg = <0x11C00000 0x64>;
- interrupts = <0 84 0>;
+ interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_ROTATOR>;
clock-names = "rotator";
iommus = <&sysmmu_rotator>;
@@ -642,7 +642,7 @@
gsc_0: video-scaler@13e00000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e00000 0x1000>;
- interrupts = <0 85 0>;
+ interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_GSCL0>;
clock-names = "gscl";
power-domains = <&gsc_pd>;
@@ -652,7 +652,7 @@
gsc_1: video-scaler@13e10000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e10000 0x1000>;
- interrupts = <0 86 0>;
+ interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_GSCL1>;
clock-names = "gscl";
power-domains = <&gsc_pd>;
@@ -662,7 +662,7 @@
jpeg_0: jpeg@11F50000 {
compatible = "samsung,exynos5420-jpeg";
reg = <0x11F50000 0x1000>;
- interrupts = <0 89 0>;
+ interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "jpeg";
clocks = <&clock CLK_JPEG>;
iommus = <&sysmmu_jpeg0>;
@@ -671,7 +671,7 @@
jpeg_1: jpeg@11F60000 {
compatible = "samsung,exynos5420-jpeg";
reg = <0x11F60000 0x1000>;
- interrupts = <0 168 0>;
+ interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "jpeg";
clocks = <&clock CLK_JPEG2>;
iommus = <&sysmmu_jpeg1>;
@@ -691,7 +691,7 @@
tmu_cpu0: tmu@10060000 {
compatible = "samsung,exynos5420-tmu";
reg = <0x10060000 0x100>;
- interrupts = <0 65 0>;
+ interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
@@ -700,7 +700,7 @@
tmu_cpu1: tmu@10064000 {
compatible = "samsung,exynos5420-tmu";
reg = <0x10064000 0x100>;
- interrupts = <0 183 0>;
+ interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
@@ -709,7 +709,7 @@
tmu_cpu2: tmu@10068000 {
compatible = "samsung,exynos5420-tmu-ext-triminfo";
reg = <0x10068000 0x100>, <0x1006c000 0x4>;
- interrupts = <0 184 0>;
+ interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
@@ -718,7 +718,7 @@
tmu_cpu3: tmu@1006c000 {
compatible = "samsung,exynos5420-tmu-ext-triminfo";
reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
- interrupts = <0 185 0>;
+ interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
@@ -727,7 +727,7 @@
tmu_gpu: tmu@100a0000 {
compatible = "samsung,exynos5420-tmu-ext-triminfo";
reg = <0x100a0000 0x100>, <0x10068000 0x4>;
- interrupts = <0 215 0>;
+ interrupts = <0 215 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
@@ -799,7 +799,7 @@
sysmmu_scaler1r: sysmmu@0x12890000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x12890000 0x1000>;
- interrupts = <0 186 0>;
+ interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
#iommu-cells = <0>;
@@ -808,7 +808,7 @@
sysmmu_scaler2r: sysmmu@0x128A0000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x128A0000 0x1000>;
- interrupts = <0 188 0>;
+ interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
#iommu-cells = <0>;
@@ -867,7 +867,7 @@
sysmmu_jpeg1: sysmmu@0x11F20000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11F20000 0x1000>;
- interrupts = <0 169 0>;
+ interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
#iommu-cells = <0>;
@@ -1445,7 +1445,7 @@
};
&usbdrd_dwc3_1 {
- interrupts = <GIC_SPI 73 0>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
};
&usbdrd_phy1 {
diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi
index 9d31cdce1959..8640b01f1c94 100644
--- a/arch/arm/boot/dts/exynos54xx.dtsi
+++ b/arch/arm/boot/dts/exynos54xx.dtsi
@@ -62,34 +62,34 @@
<1 &combiner 23 4>,
<2 &combiner 25 2>,
<3 &combiner 25 3>,
- <4 &gic 0 120 0>,
- <5 &gic 0 121 0>,
- <6 &gic 0 122 0>,
- <7 &gic 0 123 0>,
- <8 &gic 0 128 0>,
- <9 &gic 0 129 0>,
- <10 &gic 0 130 0>,
- <11 &gic 0 131 0>;
+ <4 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>,
+ <5 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>,
+ <6 &gic 0 122 IRQ_TYPE_LEVEL_HIGH>,
+ <7 &gic 0 123 IRQ_TYPE_LEVEL_HIGH>,
+ <8 &gic 0 128 IRQ_TYPE_LEVEL_HIGH>,
+ <9 &gic 0 129 IRQ_TYPE_LEVEL_HIGH>,
+ <10 &gic 0 130 IRQ_TYPE_LEVEL_HIGH>,
+ <11 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>;
};
};
watchdog: watchdog@101d0000 {
compatible = "samsung,exynos5420-wdt";
reg = <0x101d0000 0x100>;
- interrupts = <0 42 0>;
+ interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
};
sss: sss@10830000 {
compatible = "samsung,exynos4210-secss";
reg = <0x10830000 0x300>;
- interrupts = <0 112 0>;
+ interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
};
/* i2c_0-3 are defined in exynos5.dtsi */
hsi2c_4: i2c@12ca0000 {
compatible = "samsung,exynos5250-hsi2c";
reg = <0x12ca0000 0x1000>;
- interrupts = <0 60 0>;
+ interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -98,7 +98,7 @@
hsi2c_5: i2c@12cb0000 {
compatible = "samsung,exynos5250-hsi2c";
reg = <0x12cb0000 0x1000>;
- interrupts = <0 61 0>;
+ interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -107,7 +107,7 @@
hsi2c_6: i2c@12cc0000 {
compatible = "samsung,exynos5250-hsi2c";
reg = <0x12cc0000 0x1000>;
- interrupts = <0 62 0>;
+ interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -116,7 +116,7 @@
hsi2c_7: i2c@12cd0000 {
compatible = "samsung,exynos5250-hsi2c";
reg = <0x12cd0000 0x1000>;
- interrupts = <0 63 0>;
+ interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -131,7 +131,7 @@
usbdrd_dwc3_0: dwc3@12000000 {
compatible = "snps,dwc3";
reg = <0x12000000 0x10000>;
- interrupts = <0 72 0>;
+ interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
phy-names = "usb2-phy", "usb3-phy";
};
@@ -166,7 +166,7 @@
usbhost2: usb@12110000 {
compatible = "samsung,exynos4210-ehci";
reg = <0x12110000 0x100>;
- interrupts = <0 71 0>;
+ interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -179,7 +179,7 @@
usbhost1: usb@12120000 {
compatible = "samsung,exynos4210-ohci";
reg = <0x12120000 0x100>;
- interrupts = <0 71 0>;
+ interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
--
cgit
From eb87868a28ebc1f050987e7df2c428834eab4a3d Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzk@kernel.org>
Date: Fri, 16 Sep 2016 21:42:50 +0200
Subject: ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos5260
Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and
generates an error:
genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)
The GIC requires shared interrupts to be edge rising or level high.
Platform declares support for both. Arbitrarily choose level high
everywhere hoping it will work on each platform.
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reported-by: Alban Browaeys <alban.browaeys@gmail.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
---
arch/arm/boot/dts/exynos5260.dtsi | 39 ++++++++++++++++++++++++---------------
1 file changed, 24 insertions(+), 15 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi
index a86a4898d077..b0848a3d3d88 100644
--- a/arch/arm/boot/dts/exynos5260.dtsi
+++ b/arch/arm/boot/dts/exynos5260.dtsi
@@ -10,6 +10,7 @@
*/
#include <dt-bindings/clock/exynos5260-clk.h>
+#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "samsung,exynos5260", "samsung,exynos5";
@@ -181,10 +182,18 @@
reg = <0x100B0000 0x1000>;
clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>;
clock-names = "fin_pll", "mct";
- interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
- <0 107 0>, <0 122 0>, <0 123 0>,
- <0 124 0>, <0 125 0>, <0 126 0>,
- <0 127 0>, <0 128 0>, <0 129 0>;
+ interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>,
+ <0 105 IRQ_TYPE_LEVEL_HIGH>,
+ <0 106 IRQ_TYPE_LEVEL_HIGH>,
+ <0 107 IRQ_TYPE_LEVEL_HIGH>,
+ <0 122 IRQ_TYPE_LEVEL_HIGH>,
+ <0 123 IRQ_TYPE_LEVEL_HIGH>,
+ <0 124 IRQ_TYPE_LEVEL_HIGH>,
+ <0 125 IRQ_TYPE_LEVEL_HIGH>,
+ <0 126 IRQ_TYPE_LEVEL_HIGH>,
+ <0 127 IRQ_TYPE_LEVEL_HIGH>,
+ <0 128 IRQ_TYPE_LEVEL_HIGH>,
+ <0 129 IRQ_TYPE_LEVEL_HIGH>;
};
cci: cci@10F00000 {
@@ -210,25 +219,25 @@
pinctrl_0: pinctrl@11600000 {
compatible = "samsung,exynos5260-pinctrl";
reg = <0x11600000 0x1000>;
- interrupts = <0 79 0>;
+ interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
interrupt-parent = <&gic>;
- interrupts = <0 32 0>;
+ interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
};
};
pinctrl_1: pinctrl@12290000 {
compatible = "samsung,exynos5260-pinctrl";
reg = <0x12290000 0x1000>;
- interrupts = <0 157 0>;
+ interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_2: pinctrl@128B0000 {
compatible = "samsung,exynos5260-pinctrl";
reg = <0x128B0000 0x1000>;
- interrupts = <0 243 0>;
+ interrupts = <0 243 IRQ_TYPE_LEVEL_HIGH>;
};
pmu_system_controller: system-controller@10D50000 {
@@ -239,7 +248,7 @@
uart0: serial@12C00000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C00000 0x100>;
- interrupts = <0 146 0>;
+ interrupts = <0 146 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_peri PERI_CLK_UART0>, <&clock_peri PERI_SCLK_UART0>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
@@ -248,7 +257,7 @@
uart1: serial@12C10000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C10000 0x100>;
- interrupts = <0 147 0>;
+ interrupts = <0 147 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_peri PERI_CLK_UART1>, <&clock_peri PERI_SCLK_UART1>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
@@ -257,7 +266,7 @@
uart2: serial@12C20000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C20000 0x100>;
- interrupts = <0 148 0>;
+ interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_peri PERI_CLK_UART2>, <&clock_peri PERI_SCLK_UART2>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
@@ -266,7 +275,7 @@
uart3: serial@12860000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12860000 0x100>;
- interrupts = <0 145 0>;
+ interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_aud AUD_CLK_AUD_UART>, <&clock_aud AUD_SCLK_AUD_UART>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
@@ -275,7 +284,7 @@
mmc_0: mmc@12140000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12140000 0x2000>;
- interrupts = <0 156 0>;
+ interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>;
@@ -287,7 +296,7 @@
mmc_1: mmc@12150000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12150000 0x2000>;
- interrupts = <0 158 0>;
+ interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>;
@@ -299,7 +308,7 @@
mmc_2: mmc@12160000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12160000 0x2000>;
- interrupts = <0 159 0>;
+ interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>;
--
cgit
From c473c9a180446385c3e70e79deb1fb4d559fc5da Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzk@kernel.org>
Date: Fri, 16 Sep 2016 21:42:51 +0200
Subject: ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos5440
Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and
generates an error:
genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)
The GIC requires shared interrupts to be edge rising or level high.
Platform declares support for both. Arbitrarily choose level high
everywhere hoping it will work on each platform.
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reported-by: Alban Browaeys <alban.browaeys@gmail.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
---
arch/arm/boot/dts/exynos5440.dtsi | 48 ++++++++++++++++++++++++---------------
1 file changed, 30 insertions(+), 18 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index e6bffd13cedd..20f600225121 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -10,6 +10,7 @@
*/
#include <dt-bindings/clock/exynos5440.h>
+#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "samsung,exynos5440", "samsung,exynos5";
@@ -91,7 +92,7 @@
cpufreq@160000 {
compatible = "samsung,exynos5440-cpufreq";
reg = <0x160000 0x1000>;
- interrupts = <0 57 0>;
+ interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
operating-points = <
/* KHz uV */
1500000 1100000
@@ -108,7 +109,7 @@
serial_0: serial@B0000 {
compatible = "samsung,exynos4210-uart";
reg = <0xB0000 0x1000>;
- interrupts = <0 2 0>;
+ interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
clock-names = "uart", "clk_uart_baud0";
};
@@ -116,7 +117,7 @@
serial_1: serial@C0000 {
compatible = "samsung,exynos4210-uart";
reg = <0xC0000 0x1000>;
- interrupts = <0 3 0>;
+ interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
clock-names = "uart", "clk_uart_baud0";
};
@@ -124,7 +125,7 @@
spi_0: spi@D0000 {
compatible = "samsung,exynos5440-spi";
reg = <0xD0000 0x100>;
- interrupts = <0 4 0>;
+ interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
samsung,spi-src-clk = <0>;
@@ -136,8 +137,14 @@
pin_ctrl: pinctrl@E0000 {
compatible = "samsung,exynos5440-pinctrl";
reg = <0xE0000 0x1000>;
- interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>,
- <0 41 0>, <0 42 0>, <0 43 0>, <0 44 0>;
+ interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>,
+ <0 38 IRQ_TYPE_LEVEL_HIGH>,
+ <0 39 IRQ_TYPE_LEVEL_HIGH>,
+ <0 40 IRQ_TYPE_LEVEL_HIGH>,
+ <0 41 IRQ_TYPE_LEVEL_HIGH>,
+ <0 42 IRQ_TYPE_LEVEL_HIGH>,
+ <0 43 IRQ_TYPE_LEVEL_HIGH>,
+ <0 44 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
#gpio-cells = <2>;
@@ -162,7 +169,7 @@
i2c@F0000 {
compatible = "samsung,exynos5440-i2c";
reg = <0xF0000 0x1000>;
- interrupts = <0 5 0>;
+ interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_B_125>;
@@ -172,7 +179,7 @@
i2c@100000 {
compatible = "samsung,exynos5440-i2c";
reg = <0x100000 0x1000>;
- interrupts = <0 6 0>;
+ interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_B_125>;
@@ -182,7 +189,7 @@
watchdog@110000 {
compatible = "samsung,s3c2410-wdt";
reg = <0x110000 0x1000>;
- interrupts = <0 1 0>;
+ interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_B_125>;
clock-names = "watchdog";
};
@@ -209,7 +216,8 @@
rtc@130000 {
compatible = "samsung,s3c6410-rtc";
reg = <0x130000 0x1000>;
- interrupts = <0 17 0>, <0 16 0>;
+ interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
+ <0 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_B_125>;
clock-names = "rtc";
};
@@ -217,7 +225,7 @@
tmuctrl_0: tmuctrl@160118 {
compatible = "samsung,exynos5440-tmu";
reg = <0x160118 0x230>, <0x160368 0x10>;
- interrupts = <0 58 0>;
+ interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_B_125>;
clock-names = "tmu_apbif";
#include "exynos5440-tmu-sensor-conf.dtsi"
@@ -226,7 +234,7 @@
tmuctrl_1: tmuctrl@16011C {
compatible = "samsung,exynos5440-tmu";
reg = <0x16011C 0x230>, <0x160368 0x10>;
- interrupts = <0 58 0>;
+ interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_B_125>;
clock-names = "tmu_apbif";
#include "exynos5440-tmu-sensor-conf.dtsi"
@@ -235,7 +243,7 @@
tmuctrl_2: tmuctrl@160120 {
compatible = "samsung,exynos5440-tmu";
reg = <0x160120 0x230>, <0x160368 0x10>;
- interrupts = <0 58 0>;
+ interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_B_125>;
clock-names = "tmu_apbif";
#include "exynos5440-tmu-sensor-conf.dtsi"
@@ -259,7 +267,7 @@
sata@210000 {
compatible = "snps,exynos5440-ahci";
reg = <0x210000 0x10000>;
- interrupts = <0 30 0>;
+ interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SATA>;
clock-names = "sata";
};
@@ -267,7 +275,7 @@
ohci@220000 {
compatible = "samsung,exynos5440-ohci";
reg = <0x220000 0x1000>;
- interrupts = <0 29 0>;
+ interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_USB>;
clock-names = "usbhost";
};
@@ -275,7 +283,7 @@
ehci@221000 {
compatible = "samsung,exynos5440-ehci";
reg = <0x221000 0x1000>;
- interrupts = <0 29 0>;
+ interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_USB>;
clock-names = "usbhost";
};
@@ -285,7 +293,9 @@
reg = <0x290000 0x1000
0x270000 0x1000
0x271000 0x40>;
- interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
+ interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>,
+ <0 21 IRQ_TYPE_LEVEL_HIGH>,
+ <0 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>;
clock-names = "pcie", "pcie_bus";
#address-cells = <3>;
@@ -306,7 +316,9 @@
reg = <0x2a0000 0x1000
0x272000 0x1000
0x271040 0x40>;
- interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
+ interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>,
+ <0 24 IRQ_TYPE_LEVEL_HIGH>,
+ <0 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>;
clock-names = "pcie", "pcie_bus";
#address-cells = <3>;
--
cgit
From 9645ab2cbc1a619a3456a28041a207b37cb5100d Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzk@kernel.org>
Date: Fri, 16 Sep 2016 23:41:57 +0200
Subject: ARM: dts: exynos: Use human-friendly symbols for interrupt properties
in exynos3250
Replace hard-coded values of type of GIC interrupt and its flags with
respective macros from header to increase code readability.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 32 ++++-----
arch/arm/boot/dts/exynos3250.dtsi | 112 +++++++++++++++---------------
2 files changed, 73 insertions(+), 71 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
index 450127d46acd..a149f148e659 100644
--- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
@@ -362,14 +362,14 @@
interrupt-controller;
interrupt-parent = <&gic>;
- interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
- <0 33 IRQ_TYPE_LEVEL_HIGH>,
- <0 34 IRQ_TYPE_LEVEL_HIGH>,
- <0 35 IRQ_TYPE_LEVEL_HIGH>,
- <0 36 IRQ_TYPE_LEVEL_HIGH>,
- <0 37 IRQ_TYPE_LEVEL_HIGH>,
- <0 38 IRQ_TYPE_LEVEL_HIGH>,
- <0 39 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
};
@@ -379,14 +379,14 @@
interrupt-controller;
interrupt-parent = <&gic>;
- interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>,
- <0 41 IRQ_TYPE_LEVEL_HIGH>,
- <0 42 IRQ_TYPE_LEVEL_HIGH>,
- <0 43 IRQ_TYPE_LEVEL_HIGH>,
- <0 44 IRQ_TYPE_LEVEL_HIGH>,
- <0 45 IRQ_TYPE_LEVEL_HIGH>,
- <0 46 IRQ_TYPE_LEVEL_HIGH>,
- <0 47 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
};
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 9703d81d1eb3..ba17ee1eb749 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -20,6 +20,7 @@
#include "exynos4-cpu-thermal.dtsi"
#include "exynos-syscon-restart.dtsi"
#include <dt-bindings/clock/exynos3250.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
@@ -212,8 +213,8 @@
rtc: rtc@10070000 {
compatible = "samsung,s3c6410-rtc";
reg = <0x10070000 0x100>;
- interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>,
- <0 74 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&pmu_system_controller>;
status = "disabled";
};
@@ -221,7 +222,7 @@
tmu: tmu@100C0000 {
compatible = "samsung,exynos3250-tmu";
reg = <0x100C0000 0x100>;
- interrupts = <0 216 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_TMU_APBIF>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
@@ -236,20 +237,21 @@
<0x10482000 0x1000>,
<0x10484000 0x2000>,
<0x10486000 0x2000>;
- interrupts = <1 9 0xf04>;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
mct@10050000 {
compatible = "samsung,exynos4210-mct";
reg = <0x10050000 0x800>;
- interrupts = <0 218 IRQ_TYPE_LEVEL_HIGH>,
- <0 219 IRQ_TYPE_LEVEL_HIGH>,
- <0 220 IRQ_TYPE_LEVEL_HIGH>,
- <0 221 IRQ_TYPE_LEVEL_HIGH>,
- <0 223 IRQ_TYPE_LEVEL_HIGH>,
- <0 226 IRQ_TYPE_LEVEL_HIGH>,
- <0 227 IRQ_TYPE_LEVEL_HIGH>,
- <0 228 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
clock-names = "fin_pll", "mct";
};
@@ -257,24 +259,24 @@
pinctrl_1: pinctrl@11000000 {
compatible = "samsung,exynos3250-pinctrl";
reg = <0x11000000 0x1000>;
- interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
- interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
};
};
pinctrl_0: pinctrl@11400000 {
compatible = "samsung,exynos3250-pinctrl";
reg = <0x11400000 0x1000>;
- interrupts = <0 240 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
};
jpeg: codec@11830000 {
compatible = "samsung,exynos3250-jpeg";
reg = <0x11830000 0x1000>;
- interrupts = <0 171 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
clock-names = "jpeg", "sclk";
power-domains = <&pd_cam>;
@@ -288,8 +290,8 @@
sysmmu_jpeg: sysmmu@11A60000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11a60000 0x1000>;
- interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>,
- <0 161 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu", "master";
clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
power-domains = <&pd_cam>;
@@ -300,9 +302,9 @@
compatible = "samsung,exynos3250-fimd";
reg = <0x11c00000 0x30000>;
interrupt-names = "fifo", "vsync", "lcd_sys";
- interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>,
- <0 85 IRQ_TYPE_LEVEL_HIGH>,
- <0 86 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
clock-names = "sclk_fimd", "fimd";
power-domains = <&pd_lcd0>;
@@ -314,7 +316,7 @@
dsi_0: dsi@11C80000 {
compatible = "samsung,exynos3250-mipi-dsi";
reg = <0x11C80000 0x10000>;
- interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
samsung,phy-type = <0>;
power-domains = <&pd_lcd0>;
phys = <&mipi_phy 1>;
@@ -329,8 +331,8 @@
sysmmu_fimd0: sysmmu@11E20000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11e20000 0x1000>;
- interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>,
- <0 81 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu", "master";
clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
power-domains = <&pd_lcd0>;
@@ -340,7 +342,7 @@
hsotg: hsotg@12480000 {
compatible = "snps,dwc2";
reg = <0x12480000 0x20000>;
- interrupts = <0 141 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_USBOTG>;
clock-names = "otg";
phys = <&exynos_usbphy 0>;
@@ -351,7 +353,7 @@
mshc_0: mshc@12510000 {
compatible = "samsung,exynos5420-dw-mshc";
reg = <0x12510000 0x1000>;
- interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
clock-names = "biu", "ciu";
fifo-depth = <0x80>;
@@ -363,7 +365,7 @@
mshc_1: mshc@12520000 {
compatible = "samsung,exynos5420-dw-mshc";
reg = <0x12520000 0x1000>;
- interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
clock-names = "biu", "ciu";
fifo-depth = <0x80>;
@@ -375,7 +377,7 @@
mshc_2: mshc@12530000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12530000 0x1000>;
- interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
clock-names = "biu", "ciu";
fifo-depth = <0x80>;
@@ -403,7 +405,7 @@
pdma0: pdma@12680000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12680000 0x1000>;
- interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -414,7 +416,7 @@
pdma1: pdma@12690000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12690000 0x1000>;
- interrupts = <0 139 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -427,7 +429,7 @@
compatible = "samsung,exynos3250-adc",
"samsung,exynos-adc-v2";
reg = <0x126C0000 0x100>;
- interrupts = <0 137 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "adc", "sclk";
clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
#io-channel-cells = <1>;
@@ -439,7 +441,7 @@
mfc: codec@13400000 {
compatible = "samsung,mfc-v7";
reg = <0x13400000 0x10000>;
- interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "mfc", "sclk_mfc";
clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
power-domains = <&pd_mfc>;
@@ -449,8 +451,8 @@
sysmmu_mfc: sysmmu@13620000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13620000 0x1000>;
- interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>,
- <0 98 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu", "master";
clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
power-domains = <&pd_mfc>;
@@ -460,7 +462,7 @@
serial_0: serial@13800000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13800000 0x100>;
- interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
clock-names = "uart", "clk_uart_baud0";
pinctrl-names = "default";
@@ -471,7 +473,7 @@
serial_1: serial@13810000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13810000 0x100>;
- interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
clock-names = "uart", "clk_uart_baud0";
pinctrl-names = "default";
@@ -482,7 +484,7 @@
serial_2: serial@13820000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13820000 0x100>;
- interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
clock-names = "uart", "clk_uart_baud0";
pinctrl-names = "default";
@@ -495,7 +497,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13860000 0x100>;
- interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C0>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -508,7 +510,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13870000 0x100>;
- interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C1>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -521,7 +523,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13880000 0x100>;
- interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C2>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -534,7 +536,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13890000 0x100>;
- interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C3>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -547,7 +549,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138A0000 0x100>;
- interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C4>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -560,7 +562,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138B0000 0x100>;
- interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C5>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -573,7 +575,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138C0000 0x100>;
- interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C6>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -586,7 +588,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138D0000 0x100>;
- interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C7>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -597,7 +599,7 @@
spi_0: spi@13920000 {
compatible = "samsung,exynos4210-spi";
reg = <0x13920000 0x100>;
- interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 7>, <&pdma0 6>;
dma-names = "tx", "rx";
#address-cells = <1>;
@@ -613,7 +615,7 @@
spi_1: spi@13930000 {
compatible = "samsung,exynos4210-spi";
reg = <0x13930000 0x100>;
- interrupts = <0 122 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma1 7>, <&pdma1 6>;
dma-names = "tx", "rx";
#address-cells = <1>;
@@ -629,7 +631,7 @@
i2s2: i2s@13970000 {
compatible = "samsung,s3c6410-i2s";
reg = <0x13970000 0x100>;
- interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
clock-names = "iis", "i2s_opclk0";
dmas = <&pdma0 14>, <&pdma0 13>;
@@ -642,19 +644,19 @@
pwm: pwm@139D0000 {
compatible = "samsung,exynos4210-pwm";
reg = <0x139D0000 0x1000>;
- interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>,
- <0 105 IRQ_TYPE_LEVEL_HIGH>,
- <0 106 IRQ_TYPE_LEVEL_HIGH>,
- <0 107 IRQ_TYPE_LEVEL_HIGH>,
- <0 108 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
status = "disabled";
};
pmu {
compatible = "arm,cortex-a7-pmu";
- interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>,
- <0 19 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
};
ppmu_dmc0: ppmu_dmc0@106a0000 {
--
cgit
From 74e2c9586b2577247eda8e120dc60ef9aecaf5aa Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzk@kernel.org>
Date: Fri, 16 Sep 2016 23:41:58 +0200
Subject: ARM: dts: exynos: Use human-friendly symbols for interrupt properties
in exynos4
Replace hard-coded values of type of GIC interrupt and its flags with
respective macros from header to increase code readability.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/boot/dts/exynos4.dtsi | 99 ++++++++++++++++---------------
arch/arm/boot/dts/exynos4210-pinctrl.dtsi | 32 +++++-----
arch/arm/boot/dts/exynos4210.dtsi | 40 ++++++-------
arch/arm/boot/dts/exynos4x12-pinctrl.dtsi | 32 +++++-----
arch/arm/boot/dts/exynos4x12.dtsi | 60 +++++++++----------
5 files changed, 132 insertions(+), 131 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index e6f4da7f0038..3cbfc14b6b02 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -21,6 +21,7 @@
#include <dt-bindings/clock/exynos4.h>
#include <dt-bindings/clock/exynos-audss-clk.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "exynos-syscon-restart.dtsi"
@@ -169,7 +170,7 @@
dsi_0: dsi@11C80000 {
compatible = "samsung,exynos4210-mipi-dsi";
reg = <0x11C80000 0x10000>;
- interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_lcd0>;
phys = <&mipi_phy 1>;
phy-names = "dsim";
@@ -192,7 +193,7 @@
fimc_0: fimc@11800000 {
compatible = "samsung,exynos4210-fimc";
reg = <0x11800000 0x1000>;
- interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>;
clock-names = "fimc", "sclk_fimc";
power-domains = <&pd_cam>;
@@ -204,7 +205,7 @@
fimc_1: fimc@11810000 {
compatible = "samsung,exynos4210-fimc";
reg = <0x11810000 0x1000>;
- interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>;
clock-names = "fimc", "sclk_fimc";
power-domains = <&pd_cam>;
@@ -216,7 +217,7 @@
fimc_2: fimc@11820000 {
compatible = "samsung,exynos4210-fimc";
reg = <0x11820000 0x1000>;
- interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>;
clock-names = "fimc", "sclk_fimc";
power-domains = <&pd_cam>;
@@ -228,7 +229,7 @@
fimc_3: fimc@11830000 {
compatible = "samsung,exynos4210-fimc";
reg = <0x11830000 0x1000>;
- interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>;
clock-names = "fimc", "sclk_fimc";
power-domains = <&pd_cam>;
@@ -240,7 +241,7 @@
csis_0: csis@11880000 {
compatible = "samsung,exynos4210-csis";
reg = <0x11880000 0x4000>;
- interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>;
clock-names = "csis", "sclk_csis";
bus-width = <4>;
@@ -255,7 +256,7 @@
csis_1: csis@11890000 {
compatible = "samsung,exynos4210-csis";
reg = <0x11890000 0x4000>;
- interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>;
clock-names = "csis", "sclk_csis";
bus-width = <2>;
@@ -271,7 +272,7 @@
watchdog: watchdog@10060000 {
compatible = "samsung,s3c2410-wdt";
reg = <0x10060000 0x100>;
- interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_WDT>;
clock-names = "watchdog";
status = "disabled";
@@ -281,8 +282,8 @@
compatible = "samsung,s3c6410-rtc";
reg = <0x10070000 0x100>;
interrupt-parent = <&pmu_system_controller>;
- interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>,
- <0 45 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_RTC>;
clock-names = "rtc";
status = "disabled";
@@ -291,7 +292,7 @@
keypad: keypad@100A0000 {
compatible = "samsung,s5pv210-keypad";
reg = <0x100A0000 0x100>;
- interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_KEYIF>;
clock-names = "keypad";
status = "disabled";
@@ -300,7 +301,7 @@
sdhci_0: sdhci@12510000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12510000 0x100>;
- interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
clock-names = "hsmmc", "mmc_busclk.2";
status = "disabled";
@@ -309,7 +310,7 @@
sdhci_1: sdhci@12520000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12520000 0x100>;
- interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
clock-names = "hsmmc", "mmc_busclk.2";
status = "disabled";
@@ -318,7 +319,7 @@
sdhci_2: sdhci@12530000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12530000 0x100>;
- interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
clock-names = "hsmmc", "mmc_busclk.2";
status = "disabled";
@@ -327,7 +328,7 @@
sdhci_3: sdhci@12540000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12540000 0x100>;
- interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
clock-names = "hsmmc", "mmc_busclk.2";
status = "disabled";
@@ -346,7 +347,7 @@
hsotg: hsotg@12480000 {
compatible = "samsung,s3c6400-hsotg";
reg = <0x12480000 0x20000>;
- interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_USB_DEVICE>;
clock-names = "otg";
phys = <&exynos_usbphy 0>;
@@ -357,7 +358,7 @@
ehci: ehci@12580000 {
compatible = "samsung,exynos4210-ehci";
reg = <0x12580000 0x100>;
- interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_USB_HOST>;
clock-names = "usbhost";
status = "disabled";
@@ -383,7 +384,7 @@
ohci: ohci@12590000 {
compatible = "samsung,exynos4210-ohci";
reg = <0x12590000 0x100>;
- interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_USB_HOST>;
clock-names = "usbhost";
status = "disabled";
@@ -425,7 +426,7 @@
mfc: codec@13400000 {
compatible = "samsung,mfc-v5";
reg = <0x13400000 0x10000>;
- interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_mfc>;
clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
clock-names = "mfc", "sclk_mfc";
@@ -436,7 +437,7 @@
serial_0: serial@13800000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13800000 0x100>;
- interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
clock-names = "uart", "clk_uart_baud0";
dmas = <&pdma0 15>, <&pdma0 16>;
@@ -447,7 +448,7 @@
serial_1: serial@13810000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13810000 0x100>;
- interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
clock-names = "uart", "clk_uart_baud0";
dmas = <&pdma1 15>, <&pdma1 16>;
@@ -458,7 +459,7 @@
serial_2: serial@13820000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13820000 0x100>;
- interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
clock-names = "uart", "clk_uart_baud0";
dmas = <&pdma0 17>, <&pdma0 18>;
@@ -469,7 +470,7 @@
serial_3: serial@13830000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13830000 0x100>;
- interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
clock-names = "uart", "clk_uart_baud0";
dmas = <&pdma1 17>, <&pdma1 18>;
@@ -482,7 +483,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13860000 0x100>;
- interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C0>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -495,7 +496,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13870000 0x100>;
- interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C1>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -508,7 +509,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13880000 0x100>;
- interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C2>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -521,7 +522,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13890000 0x100>;
- interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C3>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -534,7 +535,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138A0000 0x100>;
- interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C4>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -547,7 +548,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138B0000 0x100>;
- interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C5>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -560,7 +561,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138C0000 0x100>;
- interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C6>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -573,7 +574,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138D0000 0x100>;
- interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C7>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -586,7 +587,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-hdmiphy-i2c";
reg = <0x138E0000 0x100>;
- interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C_HDMI>;
clock-names = "i2c";
status = "disabled";
@@ -600,7 +601,7 @@
spi_0: spi@13920000 {
compatible = "samsung,exynos4210-spi";
reg = <0x13920000 0x100>;
- interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 7>, <&pdma0 6>;
dma-names = "tx", "rx";
#address-cells = <1>;
@@ -615,7 +616,7 @@
spi_1: spi@13930000 {
compatible = "samsung,exynos4210-spi";
reg = <0x13930000 0x100>;
- interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma1 7>, <&pdma1 6>;
dma-names = "tx", "rx";
#address-cells = <1>;
@@ -630,7 +631,7 @@
spi_2: spi@13940000 {
compatible = "samsung,exynos4210-spi";
reg = <0x13940000 0x100>;
- interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 9>, <&pdma0 8>;
dma-names = "tx", "rx";
#address-cells = <1>;
@@ -645,11 +646,11 @@
pwm: pwm@139D0000 {
compatible = "samsung,exynos4210-pwm";
reg = <0x139D0000 0x1000>;
- interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>,
- <0 38 IRQ_TYPE_LEVEL_HIGH>,
- <0 39 IRQ_TYPE_LEVEL_HIGH>,
- <0 40 IRQ_TYPE_LEVEL_HIGH>,
- <0 41 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PWM>;
clock-names = "timers";
#pwm-cells = <3>;
@@ -666,7 +667,7 @@
pdma0: pdma@12680000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12680000 0x1000>;
- interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -677,7 +678,7 @@
pdma1: pdma@12690000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12690000 0x1000>;
- interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -688,7 +689,7 @@
mdma1: mdma@12850000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12850000 0x1000>;
- interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MDMA>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -718,7 +719,7 @@
jpeg_codec: jpeg-codec@11840000 {
compatible = "samsung,exynos4210-jpeg";
reg = <0x11840000 0x1000>;
- interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_JPEG>;
clock-names = "jpeg";
power-domains = <&pd_cam>;
@@ -728,7 +729,7 @@
rotator: rotator@12810000 {
compatible = "samsung,exynos4210-rotator";
reg = <0x12810000 0x64>;
- interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_ROTATOR>;
clock-names = "rotator";
iommus = <&sysmmu_rotator>;
@@ -737,7 +738,7 @@
hdmi: hdmi@12D00000 {
compatible = "samsung,exynos4210-hdmi";
reg = <0x12D00000 0x70000>;
- interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy",
"mout_hdmi";
clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
@@ -752,7 +753,7 @@
hdmicec: cec@100B0000 {
compatible = "samsung,s5p-cec";
reg = <0x100B0000 0x200>;
- interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_HDMI_CEC>;
clock-names = "hdmicec";
samsung,syscon-phandle = <&pmu_system_controller>;
@@ -763,7 +764,7 @@
mixer: mixer@12C10000 {
compatible = "samsung,exynos4210-mixer";
- interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x12C10000 0x2100>, <0x12c00000 0x300>;
power-domains = <&pd_tv>;
iommus = <&sysmmu_tv>;
@@ -990,7 +991,7 @@
sss: sss@10830000 {
compatible = "samsung,exynos4210-secss";
reg = <0x10830000 0x300>;
- interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SSS>;
clock-names = "secss";
};
diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
index 264b43228cfd..f280954b260a 100644
--- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
@@ -537,14 +537,14 @@
interrupt-controller;
interrupt-parent = <&gic>;
- interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>,
- <0 17 IRQ_TYPE_LEVEL_HIGH>,
- <0 18 IRQ_TYPE_LEVEL_HIGH>,
- <0 19 IRQ_TYPE_LEVEL_HIGH>,
- <0 20 IRQ_TYPE_LEVEL_HIGH>,
- <0 21 IRQ_TYPE_LEVEL_HIGH>,
- <0 22 IRQ_TYPE_LEVEL_HIGH>,
- <0 23 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
};
@@ -554,14 +554,14 @@
interrupt-controller;
interrupt-parent = <&gic>;
- interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>,
- <0 25 IRQ_TYPE_LEVEL_HIGH>,
- <0 26 IRQ_TYPE_LEVEL_HIGH>,
- <0 27 IRQ_TYPE_LEVEL_HIGH>,
- <0 28 IRQ_TYPE_LEVEL_HIGH>,
- <0 29 IRQ_TYPE_LEVEL_HIGH>,
- <0 30 IRQ_TYPE_LEVEL_HIGH>,
- <0 31 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
};
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 736ab8587ab0..7f3a18c8f60f 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -127,18 +127,18 @@
pinctrl_0: pinctrl@11400000 {
compatible = "samsung,exynos4210-pinctrl";
reg = <0x11400000 0x1000>;
- interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_1: pinctrl@11000000 {
compatible = "samsung,exynos4210-pinctrl";
reg = <0x11000000 0x1000>;
- interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
wakup_eint: wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
interrupt-parent = <&gic>;
- interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -182,7 +182,7 @@
g2d: g2d@12800000 {
compatible = "samsung,s5pv210-g2d";
reg = <0x12800000 0x1000>;
- interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
clock-names = "sclk_fimg2d", "fimg2d";
power-domains = <&pd_lcd0>;
@@ -424,22 +424,22 @@
&combiner {
samsung,combiner-nr = <16>;
- interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
- <0 1 IRQ_TYPE_LEVEL_HIGH>,
- <0 2 IRQ_TYPE_LEVEL_HIGH>,
- <0 3 IRQ_TYPE_LEVEL_HIGH>,
- <0 4 IRQ_TYPE_LEVEL_HIGH>,
- <0 5 IRQ_TYPE_LEVEL_HIGH>,
- <0 6 IRQ_TYPE_LEVEL_HIGH>,
- <0 7 IRQ_TYPE_LEVEL_HIGH>,
- <0 8 IRQ_TYPE_LEVEL_HIGH>,
- <0 9 IRQ_TYPE_LEVEL_HIGH>,
- <0 10 IRQ_TYPE_LEVEL_HIGH>,
- <0 11 IRQ_TYPE_LEVEL_HIGH>,
- <0 12 IRQ_TYPE_LEVEL_HIGH>,
- <0 13 IRQ_TYPE_LEVEL_HIGH>,
- <0 14 IRQ_TYPE_LEVEL_HIGH>,
- <0 15 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
&mdma1 {
diff --git a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
index 8d7958ecc8e1..2f866f6e5838 100644
--- a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
@@ -572,14 +572,14 @@
interrupt-controller;
interrupt-parent = <&gic>;
- interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>,
- <0 17 IRQ_TYPE_LEVEL_HIGH>,
- <0 18 IRQ_TYPE_LEVEL_HIGH>,
- <0 19 IRQ_TYPE_LEVEL_HIGH>,
- <0 20 IRQ_TYPE_LEVEL_HIGH>,
- <0 21 IRQ_TYPE_LEVEL_HIGH>,
- <0 22 IRQ_TYPE_LEVEL_HIGH>,
- <0 23 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
};
@@ -589,14 +589,14 @@
interrupt-controller;
interrupt-parent = <&gic>;
- interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>,
- <0 25 IRQ_TYPE_LEVEL_HIGH>,
- <0 26 IRQ_TYPE_LEVEL_HIGH>,
- <0 27 IRQ_TYPE_LEVEL_HIGH>,
- <0 28 IRQ_TYPE_LEVEL_HIGH>,
- <0 29 IRQ_TYPE_LEVEL_HIGH>,
- <0 30 IRQ_TYPE_LEVEL_HIGH>,
- <0 31 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
};
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index 2f52b685daf9..505f047e81c6 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -112,7 +112,7 @@
g2d: g2d@10800000 {
compatible = "samsung,exynos4212-g2d";
reg = <0x10800000 0x1000>;
- interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
clock-names = "sclk_fimg2d", "fimg2d";
iommus = <&sysmmu_g2d>;
@@ -127,7 +127,7 @@
fimc_lite_0: fimc-lite@12390000 {
compatible = "samsung,exynos4212-fimc-lite";
reg = <0x12390000 0x1000>;
- interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_isp>;
clocks = <&clock CLK_FIMC_LITE0>;
clock-names = "flite";
@@ -138,7 +138,7 @@
fimc_lite_1: fimc-lite@123A0000 {
compatible = "samsung,exynos4212-fimc-lite";
reg = <0x123A0000 0x1000>;
- interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_isp>;
clocks = <&clock CLK_FIMC_LITE1>;
clock-names = "flite";
@@ -149,8 +149,8 @@
fimc_is: fimc-is@12000000 {
compatible = "samsung,exynos4212-fimc-is", "simple-bus";
reg = <0x12000000 0x260000>;
- interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>,
- <0 95 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_isp>;
clocks = <&clock CLK_FIMC_LITE0>,
<&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>,
@@ -201,7 +201,7 @@
mshc_0: mmc@12550000 {
compatible = "samsung,exynos4412-dw-mshc";
reg = <0x12550000 0x1000>;
- interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
fifo-depth = <0x80>;
@@ -462,26 +462,26 @@
};
&combiner {
- interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
- <0 1 IRQ_TYPE_LEVEL_HIGH>,
- <0 2 IRQ_TYPE_LEVEL_HIGH>,
- <0 3 IRQ_TYPE_LEVEL_HIGH>,
- <0 4 IRQ_TYPE_LEVEL_HIGH>,
- <0 5 IRQ_TYPE_LEVEL_HIGH>,
- <0 6 IRQ_TYPE_LEVEL_HIGH>,
- <0 7 IRQ_TYPE_LEVEL_HIGH>,
- <0 8 IRQ_TYPE_LEVEL_HIGH>,
- <0 9 IRQ_TYPE_LEVEL_HIGH>,
- <0 10 IRQ_TYPE_LEVEL_HIGH>,
- <0 11 IRQ_TYPE_LEVEL_HIGH>,
- <0 12 IRQ_TYPE_LEVEL_HIGH>,
- <0 13 IRQ_TYPE_LEVEL_HIGH>,
- <0 14 IRQ_TYPE_LEVEL_HIGH>,
- <0 15 IRQ_TYPE_LEVEL_HIGH>,
- <0 107 IRQ_TYPE_LEVEL_HIGH>,
- <0 108 IRQ_TYPE_LEVEL_HIGH>,
- <0 48 IRQ_TYPE_LEVEL_HIGH>,
- <0 42 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
};
&exynos_usbphy {
@@ -545,18 +545,18 @@
&pinctrl_0 {
compatible = "samsung,exynos4x12-pinctrl";
reg = <0x11400000 0x1000>;
- interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
};
&pinctrl_1 {
compatible = "samsung,exynos4x12-pinctrl";
reg = <0x11000000 0x1000>;
- interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
wakup_eint: wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
interrupt-parent = <&gic>;
- interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -570,7 +570,7 @@
&pinctrl_3 {
compatible = "samsung,exynos4x12-pinctrl";
reg = <0x106E0000 0x1000>;
- interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
};
&pmu_system_controller {
--
cgit
From 888950b0cb4949266509788b1c64c0c689b79972 Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzk@kernel.org>
Date: Fri, 16 Sep 2016 23:41:59 +0200
Subject: ARM: dts: exynos: Use human-friendly symbols for interrupt properties
in exynos5
Replace hard-coded values of type of GIC interrupt and its flags with
respective macros from header to increase code readability.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
---
arch/arm/boot/dts/exynos5.dtsi | 4 ++-
arch/arm/boot/dts/exynos5250.dtsi | 76 +++++++++++++++++++--------------------
arch/arm/boot/dts/exynos5410.dtsi | 16 ++++-----
arch/arm/boot/dts/exynos54xx.dtsi | 18 +++++-----
4 files changed, 58 insertions(+), 56 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index d9b1607db5ad..7fd870ee5093 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -13,6 +13,7 @@
* published by the Free Software Foundation.
*/
+#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "exynos-syscon-restart.dtsi"
@@ -96,7 +97,8 @@
<0x10482000 0x1000>,
<0x10484000 0x2000>,
<0x10486000 0x2000>;
- interrupts = <1 9 0xf04>;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
sysreg_system_controller: syscon@10050000 {
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 4e00c0d06c67..b6d7444d8585 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -195,31 +195,31 @@
pinctrl_0: pinctrl@11400000 {
compatible = "samsung,exynos5250-pinctrl";
reg = <0x11400000 0x1000>;
- interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
wakup_eint: wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
interrupt-parent = <&gic>;
- interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
};
};
pinctrl_1: pinctrl@13400000 {
compatible = "samsung,exynos5250-pinctrl";
reg = <0x13400000 0x1000>;
- interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_2: pinctrl@10d10000 {
compatible = "samsung,exynos5250-pinctrl";
reg = <0x10d10000 0x1000>;
- interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_3: pinctrl@03860000 {
compatible = "samsung,exynos5250-pinctrl";
reg = <0x03860000 0x1000>;
- interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
};
pmu_system_controller: system-controller@10040000 {
@@ -236,7 +236,7 @@
watchdog@101D0000 {
compatible = "samsung,exynos5250-wdt";
reg = <0x101D0000 0x100>;
- interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_WDT>;
clock-names = "watchdog";
samsung,syscon-phandle = <&pmu_system_controller>;
@@ -245,7 +245,7 @@
g2d@10850000 {
compatible = "samsung,exynos5250-g2d";
reg = <0x10850000 0x1000>;
- interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_G2D>;
clock-names = "fimg2d";
iommus = <&sysmmu_g2d>;
@@ -254,7 +254,7 @@
mfc: codec@11000000 {
compatible = "samsung,mfc-v6";
reg = <0x11000000 0x10000>;
- interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_mfc>;
clocks = <&clock CLK_MFC>;
clock-names = "mfc";
@@ -265,7 +265,7 @@
rotator: rotator@11C00000 {
compatible = "samsung,exynos5250-rotator";
reg = <0x11C00000 0x64>;
- interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_ROTATOR>;
clock-names = "rotator";
iommus = <&sysmmu_rotator>;
@@ -274,7 +274,7 @@
tmu: tmu@10060000 {
compatible = "samsung,exynos5250-tmu";
reg = <0x10060000 0x100>;
- interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
@@ -284,7 +284,7 @@
compatible = "snps,dwc-ahci";
samsung,sata-freq = <66>;
reg = <0x122F0000 0x1ff>;
- interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
clock-names = "sata", "sclk_sata";
phys = <&sata_phy>;
@@ -306,7 +306,7 @@
i2c_4: i2c@12CA0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CA0000 0x100>;
- interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_I2C4>;
@@ -319,7 +319,7 @@
i2c_5: i2c@12CB0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CB0000 0x100>;
- interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_I2C5>;
@@ -332,7 +332,7 @@
i2c_6: i2c@12CC0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CC0000 0x100>;
- interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_I2C6>;
@@ -345,7 +345,7 @@
i2c_7: i2c@12CD0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CD0000 0x100>;
- interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_I2C7>;
@@ -358,7 +358,7 @@
i2c_8: i2c@12CE0000 {
compatible = "samsung,s3c2440-hdmiphy-i2c";
reg = <0x12CE0000 0x1000>;
- interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_I2C_HDMI>;
@@ -380,7 +380,7 @@
compatible = "samsung,exynos4210-spi";
status = "disabled";
reg = <0x12d20000 0x100>;
- interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 5
&pdma0 4>;
dma-names = "tx", "rx";
@@ -396,7 +396,7 @@
compatible = "samsung,exynos4210-spi";
status = "disabled";
reg = <0x12d30000 0x100>;
- interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma1 5
&pdma1 4>;
dma-names = "tx", "rx";
@@ -412,7 +412,7 @@
compatible = "samsung,exynos4210-spi";
status = "disabled";
reg = <0x12d40000 0x100>;
- interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 7
&pdma0 6>;
dma-names = "tx", "rx";
@@ -426,7 +426,7 @@
mmc_0: mmc@12200000 {
compatible = "samsung,exynos5250-dw-mshc";
- interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x12200000 0x1000>;
@@ -438,7 +438,7 @@
mmc_1: mmc@12210000 {
compatible = "samsung,exynos5250-dw-mshc";
- interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x12210000 0x1000>;
@@ -450,7 +450,7 @@
mmc_2: mmc@12220000 {
compatible = "samsung,exynos5250-dw-mshc";
- interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x12220000 0x1000>;
@@ -463,7 +463,7 @@
mmc_3: mmc@12230000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12230000 0x1000>;
- interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
@@ -526,7 +526,7 @@
usbdrd_dwc3: dwc3@12000000 {
compatible = "synopsys,dwc3";
reg = <0x12000000 0x10000>;
- interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
phy-names = "usb2-phy", "usb3-phy";
};
@@ -544,7 +544,7 @@
ehci: usb@12110000 {
compatible = "samsung,exynos4210-ehci";
reg = <0x12110000 0x100>;
- interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_USB2>;
clock-names = "usbhost";
@@ -559,7 +559,7 @@
ohci: usb@12120000 {
compatible = "samsung,exynos4210-ohci";
reg = <0x12120000 0x100>;
- interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_USB2>;
clock-names = "usbhost";
@@ -591,7 +591,7 @@
pdma0: pdma@121A0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x121A0000 0x1000>;
- interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -602,7 +602,7 @@
pdma1: pdma@121B0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x121B0000 0x1000>;
- interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -613,7 +613,7 @@
mdma0: mdma@10800000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x10800000 0x1000>;
- interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -624,7 +624,7 @@
mdma1: mdma@11C10000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x11C10000 0x1000>;
- interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -636,7 +636,7 @@
gsc_0: gsc@13e00000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e00000 0x1000>;
- interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_gsc>;
clocks = <&clock CLK_GSCL0>;
clock-names = "gscl";
@@ -646,7 +646,7 @@
gsc_1: gsc@13e10000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e10000 0x1000>;
- interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_gsc>;
clocks = <&clock CLK_GSCL1>;
clock-names = "gscl";
@@ -656,7 +656,7 @@
gsc_2: gsc@13e20000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e20000 0x1000>;
- interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_gsc>;
clocks = <&clock CLK_GSCL2>;
clock-names = "gscl";
@@ -666,7 +666,7 @@
gsc_3: gsc@13e30000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e30000 0x1000>;
- interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_gsc>;
clocks = <&clock CLK_GSCL3>;
clock-names = "gscl";
@@ -677,7 +677,7 @@
compatible = "samsung,exynos4212-hdmi";
reg = <0x14530000 0x70000>;
power-domains = <&pd_disp1>;
- interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
<&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
<&clock CLK_MOUT_HDMI>;
@@ -690,7 +690,7 @@
compatible = "samsung,exynos5250-mixer";
reg = <0x14450000 0x10000>;
power-domains = <&pd_disp1>;
- interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
<&clock CLK_SCLK_HDMI>;
clock-names = "mixer", "hdmi", "sclk_hdmi";
@@ -706,7 +706,7 @@
adc: adc@12D10000 {
compatible = "samsung,exynos-adc-v1";
reg = <0x12D10000 0x100>;
- interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_ADC>;
clock-names = "adc";
#io-channel-cells = <1>;
@@ -718,7 +718,7 @@
sss@10830000 {
compatible = "samsung,exynos4210-secss";
reg = <0x10830000 0x300>;
- interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SSS>;
clock-names = "secss";
};
diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
index dae5715b41b9..2501249d97aa 100644
--- a/arch/arm/boot/dts/exynos5410.dtsi
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -121,7 +121,7 @@
mmc_0: mmc@12200000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12200000 0x1000>;
- interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
@@ -133,7 +133,7 @@
mmc_1: mmc@12210000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12210000 0x1000>;
- interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
@@ -145,7 +145,7 @@
mmc_2: mmc@12220000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12220000 0x1000>;
- interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
@@ -157,31 +157,31 @@
pinctrl_0: pinctrl@13400000 {
compatible = "samsung,exynos5410-pinctrl";
reg = <0x13400000 0x1000>;
- interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
interrupt-parent = <&gic>;
- interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
};
};
pinctrl_1: pinctrl@14000000 {
compatible = "samsung,exynos5410-pinctrl";
reg = <0x14000000 0x1000>;
- interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_2: pinctrl@10d10000 {
compatible = "samsung,exynos5410-pinctrl";
reg = <0x10d10000 0x1000>;
- interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_3: pinctrl@03860000 {
compatible = "samsung,exynos5410-pinctrl";
reg = <0x03860000 0x1000>;
- interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
};
};
diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi
index 8640b01f1c94..0389e8a10d0b 100644
--- a/arch/arm/boot/dts/exynos54xx.dtsi
+++ b/arch/arm/boot/dts/exynos54xx.dtsi
@@ -76,20 +76,20 @@
watchdog: watchdog@101d0000 {
compatible = "samsung,exynos5420-wdt";
reg = <0x101d0000 0x100>;
- interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
};
sss: sss@10830000 {
compatible = "samsung,exynos4210-secss";
reg = <0x10830000 0x300>;
- interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
};
/* i2c_0-3 are defined in exynos5.dtsi */
hsi2c_4: i2c@12ca0000 {
compatible = "samsung,exynos5250-hsi2c";
reg = <0x12ca0000 0x1000>;
- interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -98,7 +98,7 @@
hsi2c_5: i2c@12cb0000 {
compatible = "samsung,exynos5250-hsi2c";
reg = <0x12cb0000 0x1000>;
- interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -107,7 +107,7 @@
hsi2c_6: i2c@12cc0000 {
compatible = "samsung,exynos5250-hsi2c";
reg = <0x12cc0000 0x1000>;
- interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -116,7 +116,7 @@
hsi2c_7: i2c@12cd0000 {
compatible = "samsung,exynos5250-hsi2c";
reg = <0x12cd0000 0x1000>;
- interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -131,7 +131,7 @@
usbdrd_dwc3_0: dwc3@12000000 {
compatible = "snps,dwc3";
reg = <0x12000000 0x10000>;
- interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
phy-names = "usb2-phy", "usb3-phy";
};
@@ -166,7 +166,7 @@
usbhost2: usb@12110000 {
compatible = "samsung,exynos4210-ehci";
reg = <0x12110000 0x100>;
- interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -179,7 +179,7 @@
usbhost1: usb@12120000 {
compatible = "samsung,exynos4210-ohci";
reg = <0x12120000 0x100>;
- interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
--
cgit
From 7184c42c57124c176f6429cb16228b7a03d6537f Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzk@kernel.org>
Date: Fri, 16 Sep 2016 23:42:01 +0200
Subject: ARM: dts: exynos: Use human-friendly symbols for interrupt properties
in exynos5260
Replace hard-coded values of type of GIC interrupt and its flags with
respective macros from header to increase code readability.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/boot/dts/exynos5260.dtsi | 50 ++++++++++++++++++++-------------------
1 file changed, 26 insertions(+), 24 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi
index b0848a3d3d88..5818718618b1 100644
--- a/arch/arm/boot/dts/exynos5260.dtsi
+++ b/arch/arm/boot/dts/exynos5260.dtsi
@@ -10,6 +10,7 @@
*/
#include <dt-bindings/clock/exynos5260-clk.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
@@ -169,7 +170,8 @@
<0x10482000 0x1000>,
<0x10484000 0x2000>,
<0x10486000 0x2000>;
- interrupts = <1 9 0xf04>;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
chipid: chipid@10000000 {
@@ -182,18 +184,18 @@
reg = <0x100B0000 0x1000>;
clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>;
clock-names = "fin_pll", "mct";
- interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>,
- <0 105 IRQ_TYPE_LEVEL_HIGH>,
- <0 106 IRQ_TYPE_LEVEL_HIGH>,
- <0 107 IRQ_TYPE_LEVEL_HIGH>,
- <0 122 IRQ_TYPE_LEVEL_HIGH>,
- <0 123 IRQ_TYPE_LEVEL_HIGH>,
- <0 124 IRQ_TYPE_LEVEL_HIGH>,
- <0 125 IRQ_TYPE_LEVEL_HIGH>,
- <0 126 IRQ_TYPE_LEVEL_HIGH>,
- <0 127 IRQ_TYPE_LEVEL_HIGH>,
- <0 128 IRQ_TYPE_LEVEL_HIGH>,
- <0 129 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
};
cci: cci@10F00000 {
@@ -219,25 +221,25 @@
pinctrl_0: pinctrl@11600000 {
compatible = "samsung,exynos5260-pinctrl";
reg = <0x11600000 0x1000>;
- interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
interrupt-parent = <&gic>;
- interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
};
};
pinctrl_1: pinctrl@12290000 {
compatible = "samsung,exynos5260-pinctrl";
reg = <0x12290000 0x1000>;
- interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_2: pinctrl@128B0000 {
compatible = "samsung,exynos5260-pinctrl";
reg = <0x128B0000 0x1000>;
- interrupts = <0 243 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
};
pmu_system_controller: system-controller@10D50000 {
@@ -248,7 +250,7 @@
uart0: serial@12C00000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C00000 0x100>;
- interrupts = <0 146 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_peri PERI_CLK_UART0>, <&clock_peri PERI_SCLK_UART0>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
@@ -257,7 +259,7 @@
uart1: serial@12C10000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C10000 0x100>;
- interrupts = <0 147 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_peri PERI_CLK_UART1>, <&clock_peri PERI_SCLK_UART1>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
@@ -266,7 +268,7 @@
uart2: serial@12C20000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C20000 0x100>;
- interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_peri PERI_CLK_UART2>, <&clock_peri PERI_SCLK_UART2>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
@@ -275,7 +277,7 @@
uart3: serial@12860000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12860000 0x100>;
- interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_aud AUD_CLK_AUD_UART>, <&clock_aud AUD_SCLK_AUD_UART>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
@@ -284,7 +286,7 @@
mmc_0: mmc@12140000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12140000 0x2000>;
- interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>;
@@ -296,7 +298,7 @@
mmc_1: mmc@12150000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12150000 0x2000>;
- interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>;
@@ -308,7 +310,7 @@
mmc_2: mmc@12160000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12160000 0x2000>;
- interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>;
--
cgit
From 04a886727ca7e841afa2fbc5d87aff81ae256dbf Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzk@kernel.org>
Date: Fri, 16 Sep 2016 23:42:02 +0200
Subject: ARM: dts: exynos: Use human-friendly symbols for interrupt properties
in exynos5440
Replace hard-coded values of type of GIC interrupt and its flags with
respective macros from header to increase code readability.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/boot/dts/exynos5440.dtsi | 80 ++++++++++++++++++++-------------------
1 file changed, 41 insertions(+), 39 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index 20f600225121..97c9f0e38526 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -10,6 +10,7 @@
*/
#include <dt-bindings/clock/exynos5440.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
@@ -42,7 +43,8 @@
<0x2E2000 0x1000>,
<0x2E4000 0x2000>,
<0x2E6000 0x2000>;
- interrupts = <1 9 0xf04>;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
cpus {
@@ -73,26 +75,26 @@
arm-pmu {
compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
- interrupts = <0 52 4>,
- <0 53 4>,
- <0 54 4>,
- <0 55 4>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
};
timer {
compatible = "arm,cortex-a15-timer",
"arm,armv7-timer";
- interrupts = <1 13 0xf08>,
- <1 14 0xf08>,
- <1 11 0xf08>,
- <1 10 0xf08>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <50000000>;
};
cpufreq@160000 {
compatible = "samsung,exynos5440-cpufreq";
reg = <0x160000 0x1000>;
- interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
operating-points = <
/* KHz uV */
1500000 1100000
@@ -109,7 +111,7 @@
serial_0: serial@B0000 {
compatible = "samsung,exynos4210-uart";
reg = <0xB0000 0x1000>;
- interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
clock-names = "uart", "clk_uart_baud0";
};
@@ -117,7 +119,7 @@
serial_1: serial@C0000 {
compatible = "samsung,exynos4210-uart";
reg = <0xC0000 0x1000>;
- interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
clock-names = "uart", "clk_uart_baud0";
};
@@ -125,7 +127,7 @@
spi_0: spi@D0000 {
compatible = "samsung,exynos5440-spi";
reg = <0xD0000 0x100>;
- interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
samsung,spi-src-clk = <0>;
@@ -137,14 +139,14 @@
pin_ctrl: pinctrl@E0000 {
compatible = "samsung,exynos5440-pinctrl";
reg = <0xE0000 0x1000>;
- interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>,
- <0 38 IRQ_TYPE_LEVEL_HIGH>,
- <0 39 IRQ_TYPE_LEVEL_HIGH>,
- <0 40 IRQ_TYPE_LEVEL_HIGH>,
- <0 41 IRQ_TYPE_LEVEL_HIGH>,
- <0 42 IRQ_TYPE_LEVEL_HIGH>,
- <0 43 IRQ_TYPE_LEVEL_HIGH>,
- <0 44 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
#gpio-cells = <2>;
@@ -169,7 +171,7 @@
i2c@F0000 {
compatible = "samsung,exynos5440-i2c";
reg = <0xF0000 0x1000>;
- interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_B_125>;
@@ -179,7 +181,7 @@
i2c@100000 {
compatible = "samsung,exynos5440-i2c";
reg = <0x100000 0x1000>;
- interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_B_125>;
@@ -189,7 +191,7 @@
watchdog@110000 {
compatible = "samsung,s3c2410-wdt";
reg = <0x110000 0x1000>;
- interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_B_125>;
clock-names = "watchdog";
};
@@ -198,7 +200,7 @@
compatible = "snps,dwmac-3.70a";
reg = <0x00230000 0x8000>;
interrupt-parent = <&gic>;
- interrupts = <0 31 4>;
+ interrupts = <GIC_SPI 31 4>;
interrupt-names = "macirq";
phy-mode = "sgmii";
clocks = <&clock CLK_GMAC0>;
@@ -216,8 +218,8 @@
rtc@130000 {
compatible = "samsung,s3c6410-rtc";
reg = <0x130000 0x1000>;
- interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
- <0 16 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_B_125>;
clock-names = "rtc";
};
@@ -225,7 +227,7 @@
tmuctrl_0: tmuctrl@160118 {
compatible = "samsung,exynos5440-tmu";
reg = <0x160118 0x230>, <0x160368 0x10>;
- interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_B_125>;
clock-names = "tmu_apbif";
#include "exynos5440-tmu-sensor-conf.dtsi"
@@ -234,7 +236,7 @@
tmuctrl_1: tmuctrl@16011C {
compatible = "samsung,exynos5440-tmu";
reg = <0x16011C 0x230>, <0x160368 0x10>;
- interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_B_125>;
clock-names = "tmu_apbif";
#include "exynos5440-tmu-sensor-conf.dtsi"
@@ -243,7 +245,7 @@
tmuctrl_2: tmuctrl@160120 {
compatible = "samsung,exynos5440-tmu";
reg = <0x160120 0x230>, <0x160368 0x10>;
- interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_B_125>;
clock-names = "tmu_apbif";
#include "exynos5440-tmu-sensor-conf.dtsi"
@@ -267,7 +269,7 @@
sata@210000 {
compatible = "snps,exynos5440-ahci";
reg = <0x210000 0x10000>;
- interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SATA>;
clock-names = "sata";
};
@@ -275,7 +277,7 @@
ohci@220000 {
compatible = "samsung,exynos5440-ohci";
reg = <0x220000 0x1000>;
- interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_USB>;
clock-names = "usbhost";
};
@@ -283,7 +285,7 @@
ehci@221000 {
compatible = "samsung,exynos5440-ehci";
reg = <0x221000 0x1000>;
- interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_USB>;
clock-names = "usbhost";
};
@@ -293,9 +295,9 @@
reg = <0x290000 0x1000
0x270000 0x1000
0x271000 0x40>;
- interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>,
- <0 21 IRQ_TYPE_LEVEL_HIGH>,
- <0 22 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>;
clock-names = "pcie", "pcie_bus";
#address-cells = <3>;
@@ -316,9 +318,9 @@
reg = <0x2a0000 0x1000
0x272000 0x1000
0x271040 0x40>;
- interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>,
- <0 24 IRQ_TYPE_LEVEL_HIGH>,
- <0 25 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>;
clock-names = "pcie", "pcie_bus";
#address-cells = <3>;
--
cgit
From d3cec922fe2030235588aa6fe53d6470b4e7496f Mon Sep 17 00:00:00 2001
From: Simon Horman <horms+renesas@verge.net.au>
Date: Tue, 13 Sep 2016 12:57:02 +0200
Subject: ARM: dts: koelsch: enable UHS for SDHI 0, 1 & 3
Add the "1v8" pinctrl state and sd-uhs-sdr50 property to SDHI{0,1,2}.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
arch/arm/boot/dts/r8a7791-koelsch.dts | 33 ++++++++++++++++++++++++++++++---
1 file changed, 30 insertions(+), 3 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index f8a7d090fd01..f17bfa000f73 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -360,16 +360,37 @@
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
+ power-source = <3300>;
+ };
+
+ sdhi0_pins_uhs: sd0_uhs {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ power-source = <1800>;
};
sdhi1_pins: sd1 {
groups = "sdhi1_data4", "sdhi1_ctrl";
function = "sdhi1";
+ power-source = <3300>;
+ };
+
+ sdhi1_pins_uhs: sd1_uhs {
+ groups = "sdhi1_data4", "sdhi1_ctrl";
+ function = "sdhi1";
+ power-source = <1800>;
};
sdhi2_pins: sd2 {
groups = "sdhi2_data4", "sdhi2_ctrl";
function = "sdhi2";
+ power-source = <3300>;
+ };
+
+ sdhi2_pins_uhs: sd2_uhs {
+ groups = "sdhi2_data4", "sdhi2_ctrl";
+ function = "sdhi2";
+ power-source = <1800>;
};
qspi_pins: qspi {
@@ -454,33 +475,39 @@
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
- pinctrl-names = "default";
+ pinctrl-1 = <&sdhi0_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
+ sd-uhs-sdr50;
status = "okay";
};
&sdhi1 {
pinctrl-0 = <&sdhi1_pins>;
- pinctrl-names = "default";
+ pinctrl-1 = <&sdhi1_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi1>;
vqmmc-supply = <&vccq_sdhi1>;
cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
+ sd-uhs-sdr50;
status = "okay";
};
&sdhi2 {
pinctrl-0 = <&sdhi2_pins>;
- pinctrl-names = "default";
+ pinctrl-1 = <&sdhi2_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi2>;
vqmmc-supply = <&vccq_sdhi2>;
cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
+ sd-uhs-sdr50;
status = "okay";
};
--
cgit
From 5babb5d46413ac8af5ae4f3b9cc93616b3ee2bd1 Mon Sep 17 00:00:00 2001
From: Simon Horman <horms+renesas@verge.net.au>
Date: Tue, 13 Sep 2016 12:57:03 +0200
Subject: ARM: dts: r8a7794: set maximum frequency for SDHI clocks
Define the upper limit otherwise the driver cannot utilize max speeds.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
arch/arm/boot/dts/r8a7794.dtsi | 3 +++
1 file changed, 3 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 9365580a194f..57e0d27cb82e 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -731,6 +731,7 @@
dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
<&dmac1 0xcd>, <&dmac1 0xce>;
dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <195000000>;
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
status = "disabled";
};
@@ -743,6 +744,7 @@
dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
<&dmac1 0xc1>, <&dmac1 0xc2>;
dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
status = "disabled";
};
@@ -755,6 +757,7 @@
dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
<&dmac1 0xd3>, <&dmac1 0xd4>;
dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
status = "disabled";
};
--
cgit
From 9510f3492589866a1aa738951bd30e68b2aae7a7 Mon Sep 17 00:00:00 2001
From: Simon Horman <horms+renesas@verge.net.au>
Date: Tue, 13 Sep 2016 12:57:04 +0200
Subject: ARM: dts: alt: enable UHS for SDHI 0 & 1
Add the "1v8" pinctrl state and sd-uhs-sdr50 property to SDHI{0,1}.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
arch/arm/boot/dts/r8a7794-alt.dts | 22 ++++++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index 8d1b35afaf82..325d3f972c57 100644
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -207,11 +207,25 @@
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
+ power-source = <3300>;
+ };
+
+ sdhi0_pins_uhs: sd0_uhs {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ power-source = <1800>;
};
sdhi1_pins: sd1 {
groups = "sdhi1_data4", "sdhi1_ctrl";
function = "sdhi1";
+ power-source = <3300>;
+ };
+
+ sdhi1_pins_uhs: sd1_uhs {
+ groups = "sdhi1_data4", "sdhi1_ctrl";
+ function = "sdhi1";
+ power-source = <1800>;
};
};
@@ -255,23 +269,27 @@
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
- pinctrl-names = "default";
+ pinctrl-1 = <&sdhi0_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>;
+ sd-uhs-sdr50;
status = "okay";
};
&sdhi1 {
pinctrl-0 = <&sdhi1_pins>;
- pinctrl-names = "default";
+ pinctrl-1 = <&sdhi1_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi1>;
vqmmc-supply = <&vccq_sdhi1>;
cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
+ sd-uhs-sdr50;
status = "okay";
};
--
cgit
From f31fbe837b4213b7371d78e2b48786853faadd31 Mon Sep 17 00:00:00 2001
From: Geert Uytterhoeven <geert+renesas@glider.be>
Date: Mon, 19 Sep 2016 16:18:53 +0200
Subject: ARM: dts: r8a7790: Correct SCIFB reg properties to cover all
registers
Several SCIFB registers reside outside the reported register ranges.
Fortunately this works (on Linux), due to the PAGE_SIZE granularity of
ioremap().
Extend the sizes from 64 to 0x100 bytes to fix this, like is done on
SH/R-Mobile SoCs.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7790.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 351fcc2f87df..a946474be9cf 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -711,7 +711,7 @@
scifb0: serial@e6c20000 {
compatible = "renesas,scifb-r8a7790",
"renesas,rcar-gen2-scifb", "renesas,scifb";
- reg = <0 0xe6c20000 0 64>;
+ reg = <0 0xe6c20000 0 0x100>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
clock-names = "fck";
@@ -725,7 +725,7 @@
scifb1: serial@e6c30000 {
compatible = "renesas,scifb-r8a7790",
"renesas,rcar-gen2-scifb", "renesas,scifb";
- reg = <0 0xe6c30000 0 64>;
+ reg = <0 0xe6c30000 0 0x100>;
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
clock-names = "fck";
@@ -739,7 +739,7 @@
scifb2: serial@e6ce0000 {
compatible = "renesas,scifb-r8a7790",
"renesas,rcar-gen2-scifb", "renesas,scifb";
- reg = <0 0xe6ce0000 0 64>;
+ reg = <0 0xe6ce0000 0 0x100>;
interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
clock-names = "fck";
--
cgit
From 5f25f9f52e1954d3ccec43976e10ea1a8075e536 Mon Sep 17 00:00:00 2001
From: Geert Uytterhoeven <geert+renesas@glider.be>
Date: Mon, 19 Sep 2016 16:18:54 +0200
Subject: ARM: dts: r8a7791: Correct SCIFB reg properties to cover all
registers
Several SCIFB registers reside outside the reported register ranges.
Fortunately this works (on Linux), due to the PAGE_SIZE granularity of
ioremap().
Extend the sizes from 64 to 0x100 bytes to fix this, like is done on
SH/R-Mobile SoCs.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7791.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index b07c799f72f2..091d7fb6ee7d 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -702,7 +702,7 @@
scifb0: serial@e6c20000 {
compatible = "renesas,scifb-r8a7791",
"renesas,rcar-gen2-scifb", "renesas,scifb";
- reg = <0 0xe6c20000 0 64>;
+ reg = <0 0xe6c20000 0 0x100>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
clock-names = "fck";
@@ -716,7 +716,7 @@
scifb1: serial@e6c30000 {
compatible = "renesas,scifb-r8a7791",
"renesas,rcar-gen2-scifb", "renesas,scifb";
- reg = <0 0xe6c30000 0 64>;
+ reg = <0 0xe6c30000 0 0x100>;
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
clock-names = "fck";
@@ -730,7 +730,7 @@
scifb2: serial@e6ce0000 {
compatible = "renesas,scifb-r8a7791",
"renesas,rcar-gen2-scifb", "renesas,scifb";
- reg = <0 0xe6ce0000 0 64>;
+ reg = <0 0xe6ce0000 0 0x100>;
interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
clock-names = "fck";
--
cgit
From 88b8596ba95599fefa5a5f1a709c70796a0e8163 Mon Sep 17 00:00:00 2001
From: Geert Uytterhoeven <geert+renesas@glider.be>
Date: Mon, 19 Sep 2016 16:18:55 +0200
Subject: ARM: dts: r8a7793: Correct SCIFB reg properties to cover all
registers
Several SCIFB registers reside outside the reported register ranges.
Fortunately this works (on Linux), due to the PAGE_SIZE granularity of
ioremap().
Extend the sizes from 64 to 0x100 bytes to fix this, like is done on
SH/R-Mobile SoCs.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7793.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 8d02aacf2892..a7d11b9f3555 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -666,7 +666,7 @@
scifb0: serial@e6c20000 {
compatible = "renesas,scifb-r8a7793",
"renesas,rcar-gen2-scifb", "renesas,scifb";
- reg = <0 0xe6c20000 0 64>;
+ reg = <0 0xe6c20000 0 0x100>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7793_CLK_SCIFB0>;
clock-names = "fck";
@@ -680,7 +680,7 @@
scifb1: serial@e6c30000 {
compatible = "renesas,scifb-r8a7793",
"renesas,rcar-gen2-scifb", "renesas,scifb";
- reg = <0 0xe6c30000 0 64>;
+ reg = <0 0xe6c30000 0 0x100>;
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7793_CLK_SCIFB1>;
clock-names = "fck";
@@ -694,7 +694,7 @@
scifb2: serial@e6ce0000 {
compatible = "renesas,scifb-r8a7793",
"renesas,rcar-gen2-scifb", "renesas,scifb";
- reg = <0 0xe6ce0000 0 64>;
+ reg = <0 0xe6ce0000 0 0x100>;
interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7793_CLK_SCIFB2>;
clock-names = "fck";
--
cgit
From 655ea555064251e0b094848d378d4a67e8ebb0ed Mon Sep 17 00:00:00 2001
From: Geert Uytterhoeven <geert+renesas@glider.be>
Date: Mon, 19 Sep 2016 16:18:56 +0200
Subject: ARM: dts: r8a7794: Correct SCIFB reg properties to cover all
registers
Several SCIFB registers reside outside the reported register ranges.
Fortunately this works (on Linux), due to the PAGE_SIZE granularity of
ioremap().
Extend the sizes from 64 to 0x100 bytes to fix this, like is done on
SH/R-Mobile SoCs.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7794.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 57e0d27cb82e..8cfc1385f58a 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -411,7 +411,7 @@
scifb0: serial@e6c20000 {
compatible = "renesas,scifb-r8a7794",
"renesas,rcar-gen2-scifb", "renesas,scifb";
- reg = <0 0xe6c20000 0 64>;
+ reg = <0 0xe6c20000 0 0x100>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>;
clock-names = "fck";
@@ -425,7 +425,7 @@
scifb1: serial@e6c30000 {
compatible = "renesas,scifb-r8a7794",
"renesas,rcar-gen2-scifb", "renesas,scifb";
- reg = <0 0xe6c30000 0 64>;
+ reg = <0 0xe6c30000 0 0x100>;
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>;
clock-names = "fck";
@@ -439,7 +439,7 @@
scifb2: serial@e6ce0000 {
compatible = "renesas,scifb-r8a7794",
"renesas,rcar-gen2-scifb", "renesas,scifb";
- reg = <0 0xe6ce0000 0 64>;
+ reg = <0 0xe6ce0000 0 0x100>;
interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>;
clock-names = "fck";
--
cgit
From f6eea82a87db2753e2f7c0454f078fb630eb72cd Mon Sep 17 00:00:00 2001
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Date: Fri, 23 Sep 2016 00:06:43 +0300
Subject: ARM: dts: wheat: add DU support
Define the Wheat board dependent part of the DU device node.
Add the device nodes for the Analog Devices ADV7513 HDMI transmitters
connected to DU0/1. Add the necessary subnodes to interconnect DU with
HDMI transmitters/connectors.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7792-wheat.dts | 126 ++++++++++++++++++++++++++++++++++++
1 file changed, 126 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7792-wheat.dts b/arch/arm/boot/dts/r8a7792-wheat.dts
index 6dbb94114a93..c24f26fdab1f 100644
--- a/arch/arm/boot/dts/r8a7792-wheat.dts
+++ b/arch/arm/boot/dts/r8a7792-wheat.dts
@@ -86,6 +86,34 @@
gpio = <&gpio11 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
+
+ hdmi-out0 {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con0: endpoint {
+ remote-endpoint = <&adv7513_0_out>;
+ };
+ };
+ };
+
+ hdmi-out1 {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con1: endpoint {
+ remote-endpoint = <&adv7513_1_out>;
+ };
+ };
+ };
+
+ osc2_clk: osc2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <74250000>;
+ };
};
&extal_clk {
@@ -128,6 +156,16 @@
groups = "qspi_ctrl", "qspi_data4";
function = "qspi";
};
+
+ du0_pins: du0 {
+ groups = "du0_rgb888", "du0_sync", "du0_disp";
+ function = "du0";
+ };
+
+ du1_pins: du1 {
+ groups = "du1_rgb666", "du1_sync", "du1_disp";
+ function = "du1";
+ };
};
&scif0 {
@@ -197,3 +235,91 @@
};
};
};
+
+&i2c4 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ hdmi@3d {
+ compatible = "adi,adv7513";
+ reg = <0x3d>;
+
+ adi,input-depth = <8>;
+ adi,input-colorspace = "rgb";
+ adi,input-clock = "1x";
+ adi,input-style = <1>;
+ adi,input-justification = "evenly";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7513_0_in: endpoint {
+ remote-endpoint = <&du_out_rgb0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ adv7513_0_out: endpoint {
+ remote-endpoint = <&hdmi_con0>;
+ };
+ };
+ };
+ };
+
+ hdmi@39 {
+ compatible = "adi,adv7513";
+ reg = <0x39>;
+
+ adi,input-depth = <8>;
+ adi,input-colorspace = "rgb";
+ adi,input-clock = "1x";
+ adi,input-style = <1>;
+ adi,input-justification = "evenly";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7513_1_in: endpoint {
+ remote-endpoint = <&du_out_rgb1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ adv7513_1_out: endpoint {
+ remote-endpoint = <&hdmi_con1>;
+ };
+ };
+ };
+ };
+};
+
+&du {
+ pinctrl-0 = <&du0_pins &du1_pins>;
+ pinctrl-names = "default";
+
+ clocks = <&mstp7_clks R8A7792_CLK_DU0>, <&mstp7_clks R8A7792_CLK_DU1>,
+ <&osc2_clk>;
+ clock-names = "du.0", "du.1", "dclkin.0";
+ status = "okay";
+
+ ports {
+ port@0 {
+ endpoint {
+ remote-endpoint = <&adv7513_0_in>;
+ };
+ };
+ port@1 {
+ endpoint {
+ remote-endpoint = <&adv7513_1_in>;
+ };
+ };
+ };
+};
--
cgit
From 5cef452bf895cc38af3a4e20f85c20c1a4d41001 Mon Sep 17 00:00:00 2001
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Date: Mon, 5 Sep 2016 23:55:01 +0300
Subject: ARM: dts: r8a7792: add MSIOF clocks
Describe the MSIOF0/1 clocks and their parent, MP clock in the R8A7792
device tree.
Based on the original (and large) patch by Vladimir Barinov
<vladimir.barinov@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7792.dtsi | 21 +++++++++++++++++++--
1 file changed, 19 insertions(+), 2 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
index 713141d38b3e..839cd70c4c75 100644
--- a/arch/arm/boot/dts/r8a7792.dtsi
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -763,6 +763,13 @@
clock-div = <48>;
clock-mult = <1>;
};
+ mp_clk: mp {
+ compatible = "fixed-factor-clock";
+ clocks = <&pll1_div2_clk>;
+ #clock-cells = <0>;
+ clock-div = <15>;
+ clock-mult = <1>;
+ };
m2_clk: m2 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
@@ -793,6 +800,15 @@
};
/* Gate clocks */
+ mstp0_clks: mstp0_clks@e6150130 {
+ compatible = "renesas,r8a7792-mstp-clocks",
+ "renesas,cpg-mstp-clocks";
+ reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
+ clocks = <&mp_clk>;
+ #clock-cells = <1>;
+ clock-indices = <R8A7792_CLK_MSIOF0>;
+ clock-output-names = "msiof0";
+ };
mstp1_clks: mstp1_clks@e6150134 {
compatible = "renesas,r8a7792-mstp-clocks",
"renesas,cpg-mstp-clocks";
@@ -811,12 +827,13 @@
compatible = "renesas,r8a7792-mstp-clocks",
"renesas,cpg-mstp-clocks";
reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
- clocks = <&zs_clk>, <&zs_clk>;
+ clocks = <&mp_clk>, <&zs_clk>, <&zs_clk>;
#clock-cells = <1>;
clock-indices = <
+ R8A7792_CLK_MSIOF1
R8A7792_CLK_SYS_DMAC1 R8A7792_CLK_SYS_DMAC0
>;
- clock-output-names = "sys-dmac1", "sys-dmac0";
+ clock-output-names = "msiof1", "sys-dmac1", "sys-dmac0";
};
mstp3_clks: mstp3_clks@e615013c {
compatible = "renesas,r8a7792-mstp-clocks",
--
cgit
From b0663cd4211a26eb7fcaed98a26b3d117dc34926 Mon Sep 17 00:00:00 2001
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Date: Mon, 5 Sep 2016 23:55:57 +0300
Subject: ARM: dts: r8a7792: add MSIOF support
Define the generic R8A7792 parts of the MSIOF0/1 device nodes.
Based on the original (and large) patch by Vladimir Barinov
<vladimir.barinov@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7792.dtsi | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
index 839cd70c4c75..a75e0cd312c5 100644
--- a/arch/arm/boot/dts/r8a7792.dtsi
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -26,6 +26,8 @@
i2c4 = &i2c4;
i2c5 = &i2c5;
spi0 = &qspi;
+ spi1 = &msiof0;
+ spi2 = &msiof1;
vin0 = &vin0;
vin1 = &vin1;
vin2 = &vin2;
@@ -572,6 +574,34 @@
status = "disabled";
};
+ msiof0: spi@e6e20000 {
+ compatible = "renesas,msiof-r8a7792";
+ reg = <0 0xe6e20000 0 0x0064>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp0_clks R8A7792_CLK_MSIOF0>;
+ dmas = <&dmac0 0x51>, <&dmac0 0x52>,
+ <&dmac1 0x51>, <&dmac1 0x52>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof1: spi@e6e10000 {
+ compatible = "renesas,msiof-r8a7792";
+ reg = <0 0xe6e10000 0 0x0064>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp2_clks R8A7792_CLK_MSIOF1>;
+ dmas = <&dmac0 0x55>, <&dmac0 0x56>,
+ <&dmac1 0x55>, <&dmac1 0x56>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
du: display@feb00000 {
compatible = "renesas,du-r8a7792";
reg = <0 0xfeb00000 0 0x40000>;
--
cgit
From 887862227ba397bc6b22147284cdccc60a87f72f Mon Sep 17 00:00:00 2001
From: Chris Brandt <chris.brandt@renesas.com>
Date: Tue, 20 Sep 2016 11:46:18 -0400
Subject: ARM: dts: r7s72100: add mmcif to device tree
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r7s72100.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index e18d4e645d6e..50f9f3bc109d 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -450,4 +450,16 @@
#size-cells = <0>;
status = "disabled";
};
+
+ mmcif: mmc@e804c800 {
+ compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";
+ reg = <0xe804c800 0x80>;
+ interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
+ reg-io-width = <4>;
+ bus-width = <8>;
+ status = "disabled";
+ };
};
--
cgit
From 7c8522b7047c77ef598e8b5f9ff6e349c22e0622 Mon Sep 17 00:00:00 2001
From: Chris Brandt <chris.brandt@renesas.com>
Date: Thu, 22 Sep 2016 17:32:09 -0400
Subject: ARM: dts: r7s72100: add sdhi clock to device tree
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r7s72100.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index 50f9f3bc109d..eab06701ef11 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -149,6 +149,14 @@
>;
clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4";
};
+ mstp12_clks: mstp12_clks@fcfe0444 {
+ #clock-cells = <1>;
+ compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+ reg = <0xfcfe0444 4>;
+ clocks = <&p1_clk>, <&p1_clk>;
+ clock-indices = <R7S72100_CLK_SDHI1 R7S72100_CLK_SDHI0>;
+ clock-output-names = "sdhi1", "sdhi0";
+ };
};
cpus {
--
cgit
From af897250ea54c6f21bd50c350c68e8340556b93b Mon Sep 17 00:00:00 2001
From: Simon Horman <horms+renesas@verge.net.au>
Date: Fri, 16 Sep 2016 12:04:54 +0200
Subject: ARM: dts: gose: use generic pinctrl properties in SDHI nodes
Since 16ccaf5bb5a5 ("pinctrl: sh-pfc: Accept standard function, pins and
groups properties") renesas pfc drivers accept generic "function", "pins"
and "groups" properties.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7793-gose.dts | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts
index 90af18600124..dc311eba4444 100644
--- a/arch/arm/boot/dts/r8a7793-gose.dts
+++ b/arch/arm/boot/dts/r8a7793-gose.dts
@@ -346,18 +346,18 @@
};
sdhi0_pins: sd0 {
- renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
- renesas,function = "sdhi0";
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
};
sdhi1_pins: sd1 {
- renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
- renesas,function = "sdhi1";
+ groups = "sdhi1_data4", "sdhi1_ctrl";
+ function = "sdhi1";
};
sdhi2_pins: sd2 {
- renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
- renesas,function = "sdhi2";
+ groups = "sdhi2_data4", "sdhi2_ctrl";
+ function = "sdhi2";
};
qspi_pins: qspi {
--
cgit
From 0f4eebb63eb779b50e05bde0f46ea21213f4c465 Mon Sep 17 00:00:00 2001
From: Geert Uytterhoeven <geert+renesas@glider.be>
Date: Tue, 4 Oct 2016 15:31:48 +0200
Subject: ARM: dts: r8a7794: Fix W=1 dtc warnings
Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,dvc/dvc@0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,dvc/dvc@1 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,mix/mix@0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,mix/mix@1 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@1 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@2 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@3 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@4 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@5 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@6 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@7 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@1 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@2 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@3 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@4 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@5 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@6 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@1 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@2 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@3 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@4 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@5 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@6 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@7 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@8 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@9 has a unit name, but no reg property
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7794.dtsi | 58 +++++++++++++++++++++---------------------
1 file changed, 29 insertions(+), 29 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 8cfc1385f58a..44ce62938417 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -1491,62 +1491,62 @@
status = "disabled";
rcar_sound,dvc {
- dvc0: dvc@0 {
+ dvc0: dvc-0 {
dmas = <&audma0 0xbc>;
dma-names = "tx";
};
- dvc1: dvc@1 {
+ dvc1: dvc-1 {
dmas = <&audma0 0xbe>;
dma-names = "tx";
};
};
rcar_sound,mix {
- mix0: mix@0 { };
- mix1: mix@1 { };
+ mix0: mix-0 { };
+ mix1: mix-1 { };
};
rcar_sound,ctu {
- ctu00: ctu@0 { };
- ctu01: ctu@1 { };
- ctu02: ctu@2 { };
- ctu03: ctu@3 { };
- ctu10: ctu@4 { };
- ctu11: ctu@5 { };
- ctu12: ctu@6 { };
- ctu13: ctu@7 { };
+ ctu00: ctu-0 { };
+ ctu01: ctu-1 { };
+ ctu02: ctu-2 { };
+ ctu03: ctu-3 { };
+ ctu10: ctu-4 { };
+ ctu11: ctu-5 { };
+ ctu12: ctu-6 { };
+ ctu13: ctu-7 { };
};
rcar_sound,src {
- src@0 {
+ src-0 {
status = "disabled";
};
- src1: src@1 {
+ src1: src-1 {
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x87>, <&audma0 0x9c>;
dma-names = "rx", "tx";
};
- src2: src@2 {
+ src2: src-2 {
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x89>, <&audma0 0x9e>;
dma-names = "rx", "tx";
};
- src3: src@3 {
+ src3: src-3 {
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x8b>, <&audma0 0xa0>;
dma-names = "rx", "tx";
};
- src4: src@4 {
+ src4: src-4 {
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x8d>, <&audma0 0xb0>;
dma-names = "rx", "tx";
};
- src5: src@5 {
+ src5: src-5 {
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x8f>, <&audma0 0xb2>;
dma-names = "rx", "tx";
};
- src6: src@6 {
+ src6: src-6 {
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x91>, <&audma0 0xb4>;
dma-names = "rx", "tx";
@@ -1554,61 +1554,61 @@
};
rcar_sound,ssi {
- ssi0: ssi@0 {
+ ssi0: ssi-0 {
interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x01>, <&audma0 0x02>,
<&audma0 0x15>, <&audma0 0x16>;
dma-names = "rx", "tx", "rxu", "txu";
};
- ssi1: ssi@1 {
+ ssi1: ssi-1 {
interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x03>, <&audma0 0x04>,
<&audma0 0x49>, <&audma0 0x4a>;
dma-names = "rx", "tx", "rxu", "txu";
};
- ssi2: ssi@2 {
+ ssi2: ssi-2 {
interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x05>, <&audma0 0x06>,
<&audma0 0x63>, <&audma0 0x64>;
dma-names = "rx", "tx", "rxu", "txu";
};
- ssi3: ssi@3 {
+ ssi3: ssi-3 {
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x07>, <&audma0 0x08>,
<&audma0 0x6f>, <&audma0 0x70>;
dma-names = "rx", "tx", "rxu", "txu";
};
- ssi4: ssi@4 {
+ ssi4: ssi-4 {
interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x09>, <&audma0 0x0a>,
<&audma0 0x71>, <&audma0 0x72>;
dma-names = "rx", "tx", "rxu", "txu";
};
- ssi5: ssi@5 {
+ ssi5: ssi-5 {
interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x0b>, <&audma0 0x0c>,
<&audma0 0x73>, <&audma0 0x74>;
dma-names = "rx", "tx", "rxu", "txu";
};
- ssi6: ssi@6 {
+ ssi6: ssi-6 {
interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x0d>, <&audma0 0x0e>,
<&audma0 0x75>, <&audma0 0x76>;
dma-names = "rx", "tx", "rxu", "txu";
};
- ssi7: ssi@7 {
+ ssi7: ssi-7 {
interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x0f>, <&audma0 0x10>,
<&audma0 0x79>, <&audma0 0x7a>;
dma-names = "rx", "tx", "rxu", "txu";
};
- ssi8: ssi@8 {
+ ssi8: ssi-8 {
interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x11>, <&audma0 0x12>,
<&audma0 0x7b>, <&audma0 0x7c>;
dma-names = "rx", "tx", "rxu", "txu";
};
- ssi9: ssi@9 {
+ ssi9: ssi-9 {
interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x13>, <&audma0 0x14>,
<&audma0 0x7d>, <&audma0 0x7e>;
--
cgit
From 66474697923cd166567b06b492e52adce12393eb Mon Sep 17 00:00:00 2001
From: Chris Brandt <chris.brandt@renesas.com>
Date: Mon, 26 Sep 2016 16:40:31 -0400
Subject: ARM: dts: r7s72100: add sdhi to device tree
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r7s72100.dtsi | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index eab06701ef11..3dd427d68c83 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -470,4 +470,30 @@
bus-width = <8>;
status = "disabled";
};
+
+ sdhi0: sd@e804e000 {
+ compatible = "renesas,sdhi-r7s72100";
+ reg = <0xe804e000 0x100>;
+ interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&mstp12_clks R7S72100_CLK_SDHI0>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ status = "disabled";
+ };
+
+ sdhi1: sd@e804e800 {
+ compatible = "renesas,sdhi-r7s72100";
+ reg = <0xe804e800 0x100>;
+ interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&mstp12_clks R7S72100_CLK_SDHI1>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ status = "disabled";
+ };
};
--
cgit
From bba1b7ea9a1cfb1478df2c1cbd8ed6736a5f4f98 Mon Sep 17 00:00:00 2001
From: Chris Brandt <chris.brandt@renesas.com>
Date: Mon, 26 Sep 2016 16:40:32 -0400
Subject: ARM: dts: rskrza1: add sdhi1 DT support
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r7s72100-rskrza1.dts | 5 +++++
1 file changed, 5 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts b/arch/arm/boot/dts/r7s72100-rskrza1.dts
index e5dea5bb4032..dd4418195ca6 100644
--- a/arch/arm/boot/dts/r7s72100-rskrza1.dts
+++ b/arch/arm/boot/dts/r7s72100-rskrza1.dts
@@ -56,6 +56,11 @@
};
};
+&sdhi1 {
+ bus-width = <4>;
+ status = "okay";
+};
+
&scif2 {
status = "okay";
};
--
cgit
From 56548d0c5aead2a1f7df43fcb29f93575ff713b4 Mon Sep 17 00:00:00 2001
From: William Towle <william.towle@codethink.co.uk>
Date: Tue, 18 Oct 2016 17:01:33 +0200
Subject: ARM: dts: lager: Add entries for VIN HDMI input support
Add DT entries for vin0, vin0_pins, and adv7612.
Sets the 'default-input' property for ADV7612, enabling image and video
capture without the need to have userspace specifying routing.
Signed-off-by: William Towle <william.towle@codethink.co.uk>
Signed-off-by: Rob Taylor <rob.taylor@codethink.co.uk>
[uli: added interrupt, renamed endpoint, merged default-input]
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7790-lager.dts | 66 +++++++++++++++++++++++++++++++++++--
1 file changed, 64 insertions(+), 2 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 52b56fcaddf2..434268262d88 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -231,12 +231,23 @@
};
};
+ hdmi-in {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&adv7612_in>;
+ };
+ };
+ };
+
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
- hdmi_con: endpoint {
+ hdmi_con_out: endpoint {
remote-endpoint = <&adv7511_out>;
};
};
@@ -427,6 +438,11 @@
function = "usb2";
};
+ vin0_pins: vin0 {
+ groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk";
+ function = "vin0";
+ };
+
vin1_pins: vin1 {
groups = "vin1_data8", "vin1_clk";
function = "vin1";
@@ -646,7 +662,34 @@
port@1 {
reg = <1>;
adv7511_out: endpoint {
- remote-endpoint = <&hdmi_con>;
+ remote-endpoint = <&hdmi_con_out>;
+ };
+ };
+ };
+ };
+
+ hdmi-in@4c {
+ compatible = "adi,adv7612";
+ reg = <0x4c>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
+ default-input = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7612_in: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ adv7612_out: endpoint {
+ remote-endpoint = <&vin0ep2>;
};
};
};
@@ -722,6 +765,25 @@
status = "okay";
};
+/* HDMI video input */
+&vin0 {
+ pinctrl-0 = <&vin0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ port {
+ vin0ep2: endpoint {
+ remote-endpoint = <&adv7612_out>;
+ bus-width = <24>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pclk-sample = <1>;
+ data-active = <1>;
+ };
+ };
+};
+
/* composite video input */
&vin1 {
pinctrl-0 = <&vin1_pins>;
--
cgit
From 84e3a74664c52b58cd7f5b6fa381f7f1cd1956e0 Mon Sep 17 00:00:00 2001
From: Hans Verkuil <hverkuil@xs4all.nl>
Date: Tue, 18 Oct 2016 17:01:34 +0200
Subject: ARM: dts: koelsch: add HDMI input
Add support in the dts for the HDMI input. Based on the Lager dts
patch from Ulrich Hecht.
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
[uli: removed "renesas," prefixes from pfc nodes]
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7791-koelsch.dts | 68 +++++++++++++++++++++++++++++++++--
1 file changed, 66 insertions(+), 2 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index f17bfa000f73..c457b43deb7d 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -265,12 +265,23 @@
};
};
+ hdmi-in {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&adv7612_in>;
+ };
+ };
+ };
+
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
- hdmi_con: endpoint {
+ hdmi_con_out: endpoint {
remote-endpoint = <&adv7511_out>;
};
};
@@ -414,6 +425,11 @@
function = "usb1";
};
+ vin0_pins: vin0 {
+ groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk";
+ function = "vin0";
+ };
+
vin1_pins: vin1 {
groups = "vin1_data8", "vin1_clk";
function = "vin1";
@@ -617,7 +633,34 @@
port@1 {
reg = <1>;
adv7511_out: endpoint {
- remote-endpoint = <&hdmi_con>;
+ remote-endpoint = <&hdmi_con_out>;
+ };
+ };
+ };
+ };
+
+ hdmi-in@4c {
+ compatible = "adi,adv7612";
+ reg = <0x4c>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+ default-input = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7612_in: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ adv7612_out: endpoint {
+ remote-endpoint = <&vin0ep2>;
};
};
};
@@ -699,6 +742,27 @@
cpu0-supply = <&vdd_dvfs>;
};
+/* HDMI video input */
+&vin0 {
+ status = "okay";
+ pinctrl-0 = <&vin0_pins>;
+ pinctrl-names = "default";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vin0ep2: endpoint {
+ remote-endpoint = <&adv7612_out>;
+ bus-width = <24>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pclk-sample = <1>;
+ data-active = <1>;
+ };
+ };
+};
+
/* composite video input */
&vin1 {
status = "okay";
--
cgit
From 06b64afa6e981b332dccadcf0b5d52139525b4f6 Mon Sep 17 00:00:00 2001
From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Date: Tue, 18 Oct 2016 17:02:21 +0200
Subject: ARM: dts: r8a7793: Enable VIN0-VIN2
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7793.dtsi | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index a7d11b9f3555..629d3d60d1cd 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -852,6 +852,33 @@
status = "disabled";
};
+ vin0: video@e6ef0000 {
+ compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef0000 0 0x1000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R8A7793_CLK_VIN0>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ vin1: video@e6ef1000 {
+ compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef1000 0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R8A7793_CLK_VIN1>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ vin2: video@e6ef2000 {
+ compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef2000 0 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R8A7793_CLK_VIN2>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
qspi: spi@e6b10000 {
compatible = "renesas,qspi-r8a7793", "renesas,qspi";
reg = <0 0xe6b10000 0 0x2c>;
--
cgit
From 30524edfae10d4af08cb2daed786ae4713ba3fd6 Mon Sep 17 00:00:00 2001
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Date: Wed, 19 Oct 2016 01:23:02 +0300
Subject: ARM: dts: r8a7779: Fix DU reg property
The system uses one address cell and one size cell, not two. Fix the DU
DT node.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7779.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index b9bbcce69dfb..9d5b8fa3da8b 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -420,7 +420,7 @@
du: display@fff80000 {
compatible = "renesas,du-r8a7779";
- reg = <0 0xfff80000 0 0x40000>;
+ reg = <0xfff80000 0x40000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7779_CLK_DU>;
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
--
cgit
From 51b884d0e1d881d7b2f4f79d806375cd2b03c50d Mon Sep 17 00:00:00 2001
From: Geert Uytterhoeven <geert+renesas@glider.be>
Date: Fri, 21 Oct 2016 11:16:06 +0200
Subject: ARM: dts: emev2: Remove skeleton.dtsi inclusion
As of commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark skeleton.dtsi
as deprecated"), including skeleton.dtsi is deprecated.
This fixes the following warning with W=1:
Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/emev2.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi
index cd119400f440..0124faf175c8 100644
--- a/arch/arm/boot/dts/emev2.dtsi
+++ b/arch/arm/boot/dts/emev2.dtsi
@@ -8,13 +8,14 @@
* kind, whether express or implied.
*/
-#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "renesas,emev2";
interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
aliases {
gpio0 = &gpio0;
--
cgit
From 3bc313022dbdc96457add1d2c29d81280d6a2b60 Mon Sep 17 00:00:00 2001
From: Geert Uytterhoeven <geert+renesas@glider.be>
Date: Fri, 21 Oct 2016 11:16:07 +0200
Subject: ARM: dts: r8a7778: Remove skeleton.dtsi inclusion
As of commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark skeleton.dtsi
as deprecated"), including skeleton.dtsi is deprecated.
This fixes the following warning with W=1:
Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7778.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index e571d66ea0fe..f3ffe1d31544 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -14,8 +14,6 @@
* kind, whether express or implied.
*/
-/include/ "skeleton.dtsi"
-
#include <dt-bindings/clock/r8a7778-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
@@ -23,6 +21,8 @@
/ {
compatible = "renesas,r8a7778";
interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
cpus {
#address-cells = <1>;
--
cgit
From 1cfc0c03602b8e876672ba895377f0ba1445a2d8 Mon Sep 17 00:00:00 2001
From: Geert Uytterhoeven <geert+renesas@glider.be>
Date: Fri, 21 Oct 2016 11:16:08 +0200
Subject: ARM: dts: r8a7779: Remove skeleton.dtsi inclusion
As of commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark skeleton.dtsi
as deprecated"), including skeleton.dtsi is deprecated.
This fixes the following warning with W=1:
Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7779.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index 9d5b8fa3da8b..3005308a1807 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -9,8 +9,6 @@
* kind, whether express or implied.
*/
-/include/ "skeleton.dtsi"
-
#include <dt-bindings/clock/r8a7779-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
@@ -19,6 +17,8 @@
/ {
compatible = "renesas,r8a7779";
interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
cpus {
#address-cells = <1>;
--
cgit
From d0b54c54f1a2257017c2501a56df936c6d921585 Mon Sep 17 00:00:00 2001
From: Geert Uytterhoeven <geert+renesas@glider.be>
Date: Fri, 21 Oct 2016 11:16:09 +0200
Subject: ARM: dts: r8a7740: Remove skeleton.dtsi inclusion
As of commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark skeleton.dtsi
as deprecated"), including skeleton.dtsi is deprecated.
This fixes the following warning with W=1:
Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7740.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index 159e04eb1b9e..34159a8349de 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -8,8 +8,6 @@
* kind, whether express or implied.
*/
-/include/ "skeleton.dtsi"
-
#include <dt-bindings/clock/r8a7740-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
@@ -17,6 +15,8 @@
/ {
compatible = "renesas,r8a7740";
interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
cpus {
#address-cells = <1>;
--
cgit
From cbdcf396fc862882516d8feeb9af4d8b33a4c7dd Mon Sep 17 00:00:00 2001
From: Geert Uytterhoeven <geert+renesas@glider.be>
Date: Fri, 21 Oct 2016 11:16:10 +0200
Subject: ARM: dts: sh73a0: Remove skeleton.dtsi inclusion
As of commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark skeleton.dtsi
as deprecated"), including skeleton.dtsi is deprecated.
This fixes the following warning with W=1:
Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/sh73a0.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 032fe2f14b16..e1267590b575 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -8,8 +8,6 @@
* kind, whether express or implied.
*/
-/include/ "skeleton.dtsi"
-
#include <dt-bindings/clock/sh73a0-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
@@ -17,6 +15,8 @@
/ {
compatible = "renesas,sh73a0";
interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
cpus {
#address-cells = <1>;
--
cgit
From 8698d83dcf1b348eb54bcd1d52b8c636d8d7d494 Mon Sep 17 00:00:00 2001
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Date: Fri, 21 Oct 2016 15:27:43 +0300
Subject: ARM: dts: r8a7779: marzen: Configure pinmuxing for the DU0 input
clock
DU0 uses an externally provided clock, but the corresponding pin isn't
correctly muxed. Fix it.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7779-marzen.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index 541678df90a9..676151b70185 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -170,7 +170,7 @@
du_pins: du {
du0 {
- groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0";
+ groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0", "du0_clk_in";
function = "du0";
};
du1 {
--
cgit
From 68cc085a4daaa32f7138de1e918331c05165a484 Mon Sep 17 00:00:00 2001
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Date: Sun, 30 Oct 2016 00:31:27 +0300
Subject: ARM: dts: r8a7794: remove Z clock
R8A7794 doesn't have Cortex-A15 CPUs, thus there's no Z clock...
Fixes: 0dce5454d5c2 ("ARM: shmobile: Initial r8a7794 SoC device tree")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7794.dtsi | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 44ce62938417..01816ac775a8 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -1028,8 +1028,7 @@
clocks = <&extal_clk &usb_extal_clk>;
#clock-cells = <1>;
clock-output-names = "main", "pll0", "pll1", "pll3",
- "lb", "qspi", "sdh", "sd0", "z",
- "rcan";
+ "lb", "qspi", "sdh", "sd0", "rcan";
#power-domain-cells = <0>;
};
/* Variable factor clocks */
--
cgit
From 38d4a53733f50bcca72c3bc89a555d96c7fc441d Mon Sep 17 00:00:00 2001
From: Neil Armstrong <narmstrong@baylibre.com>
Date: Fri, 9 Sep 2016 12:24:38 +0200
Subject: ARM: dts: Add support for OX820 and Pogoplug V3
Add device tree for the Oxford Seminconductor OX820 SoC and the
Cloud Engines PogoPlug v3 board.
Add the SoC and board compatible strings to oxnas bindings.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
arch/arm/boot/dts/Makefile | 3 +-
.../boot/dts/cloudengines-pogoplug-series-3.dts | 94 +++++++
arch/arm/boot/dts/ox820.dtsi | 296 +++++++++++++++++++++
3 files changed, 392 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/cloudengines-pogoplug-series-3.dts
create mode 100644 arch/arm/boot/dts/ox820.dtsi
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index befcd2619902..3b0c74f6940d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -604,7 +604,8 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
dtb-$(CONFIG_ARCH_PRIMA2) += \
prima2-evb.dtb
dtb-$(CONFIG_ARCH_OXNAS) += \
- wd-mbwe.dtb
+ wd-mbwe.dtb \
+ cloudengines-pogoplug-series-3.dtb
dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8060-dragonboard.dtb \
qcom-apq8064-arrow-sd-600eval.dtb \
diff --git a/arch/arm/boot/dts/cloudengines-pogoplug-series-3.dts b/arch/arm/boot/dts/cloudengines-pogoplug-series-3.dts
new file mode 100644
index 000000000000..bfde32e37123
--- /dev/null
+++ b/arch/arm/boot/dts/cloudengines-pogoplug-series-3.dts
@@ -0,0 +1,94 @@
+/*
+ * cloudengines-pogoplug-series-3.dtsi - Device tree file for Cloud Engines PogoPlug Series 3
+ *
+ * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/dts-v1/;
+#include "ox820.dtsi"
+
+/ {
+ model = "Cloud Engines PogoPlug Series 3";
+
+ compatible = "cloudengines,pogoplugv3", "oxsemi,ox820";
+
+ chosen {
+ bootargs = "earlyprintk";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ /* 128Mbytes DDR */
+ reg = <0x60000000 0x8000000>;
+ };
+
+ aliases {
+ serial0 = &uart0;
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ blue {
+ label = "pogoplug:blue";
+ gpios = <&gpio0 2 0>;
+ default-state = "keep";
+ };
+
+ orange {
+ label = "pogoplug:orange";
+ gpios = <&gpio1 16 1>;
+ default-state = "keep";
+ };
+
+ green {
+ label = "pogoplug:green";
+ gpios = <&gpio1 17 1>;
+ default-state = "keep";
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
+};
+
+&nandc {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand>;
+
+ nand@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ nand-ecc-mode = "soft";
+ nand-ecc-algo = "hamming";
+
+ partition@0 {
+ label = "boot";
+ reg = <0x00000000 0x00e00000>;
+ read-only;
+ };
+
+ partition@e00000 {
+ label = "ubi";
+ reg = <0x00e00000 0x07200000>;
+ };
+ };
+};
+
+ða {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_etha_mdio>;
+};
diff --git a/arch/arm/boot/dts/ox820.dtsi b/arch/arm/boot/dts/ox820.dtsi
new file mode 100644
index 000000000000..e40f282a023a
--- /dev/null
+++ b/arch/arm/boot/dts/ox820.dtsi
@@ -0,0 +1,296 @@
+/*
+ * ox820.dtsi - Device tree file for Oxford Semiconductor OX820 SoC
+ *
+ * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/include/ "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "oxsemi,ox820";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "oxsemi,ox820-smp";
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,arm11mpcore";
+ clocks = <&armclk>;
+ reg = <0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,arm11mpcore";
+ clocks = <&armclk>;
+ reg = <1>;
+ };
+ };
+
+ memory {
+ /* Max 512MB @ 0x60000000 */
+ reg = <0x60000000 0x20000000>;
+ };
+
+ clocks {
+ osc: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ gmacclk: gmacclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ sysclk: sysclk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ clocks = <&osc>;
+ };
+
+ plla: plla {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <850000000>;
+ };
+
+ armclk: armclk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ clocks = <&plla>;
+ };
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges;
+ interrupt-parent = <&gic>;
+
+ nandc: nand-controller@41000000 {
+ compatible = "oxsemi,ox820-nand";
+ reg = <0x41000000 0x100000>;
+ clocks = <&stdclk 11>;
+ resets = <&reset 15>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ etha: ethernet@40400000 {
+ compatible = "oxsemi,ox820-dwmac", "snps,dwmac";
+ reg = <0x40400000 0x2000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ mac-address = [000000000000]; /* Filled in by U-Boot */
+ phy-mode = "rgmii";
+
+ clocks = <&stdclk 9>, <&gmacclk>;
+ clock-names = "gmac", "stmmaceth";
+ resets = <&reset 6>;
+
+ /* Regmap for sys registers */
+ oxsemi,sys-ctrl = <&sys>;
+
+ status = "disabled";
+ };
+
+ apb-bridge@44000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0 0x44000000 0x1000000>;
+
+ pinctrl: pinctrl {
+ compatible = "oxsemi,ox820-pinctrl";
+
+ /* Regmap for sys registers */
+ oxsemi,sys-ctrl = <&sys>;
+
+ pinctrl_uart0: uart0 {
+ uart0 {
+ pins = "gpio30", "gpio31";
+ function = "fct5";
+ };
+ };
+
+ pinctrl_uart0_modem: uart0_modem {
+ uart0_modem_a {
+ pins = "gpio24", "gpio24", "gpio26", "gpio27";
+ function = "fct4";
+ };
+ uart0_modem_b {
+ pins = "gpio28", "gpio29";
+ function = "fct5";
+ };
+ };
+
+ pinctrl_uart1: uart1 {
+ uart1 {
+ pins = "gpio7", "gpio8";
+ function = "fct4";
+ };
+ };
+
+ pinctrl_uart1_modem: uart1_modem {
+ uart1_modem {
+ pins = "gpio5", "gpio6", "gpio40", "gpio41", "gpio42", "gpio43";
+ function = "fct4";
+ };
+ };
+
+ pinctrl_etha_mdio: etha_mdio {
+ etha_mdio {
+ pins = "gpio3", "gpio4";
+ function = "fct1";
+ };
+ };
+
+ pinctrl_nand: nand {
+ nand {
+ pins = "gpio12", "gpio13", "gpio14", "gpio15",
+ "gpio16", "gpio17", "gpio18", "gpio19",
+ "gpio20", "gpio21", "gpio22", "gpio23",
+ "gpio24";
+ function = "fct1";
+ };
+ };
+ };
+
+ gpio0: gpio@000000 {
+ compatible = "oxsemi,ox820-gpio";
+ reg = <0x000000 0x100000>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ngpios = <32>;
+ oxsemi,gpio-bank = <0>;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ };
+
+ gpio1: gpio@100000 {
+ compatible = "oxsemi,ox820-gpio";
+ reg = <0x100000 0x100000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ngpios = <18>;
+ oxsemi,gpio-bank = <1>;
+ gpio-ranges = <&pinctrl 0 32 18>;
+ };
+
+ uart0: serial@200000 {
+ compatible = "ns16550a";
+ reg = <0x200000 0x100000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <0>;
+ fifo-size = <16>;
+ reg-io-width = <1>;
+ current-speed = <115200>;
+ no-loopback-test;
+ status = "disabled";
+ clocks = <&sysclk>;
+ resets = <&reset 17>;
+ };
+
+ uart1: serial@300000 {
+ compatible = "ns16550a";
+ reg = <0x200000 0x100000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <0>;
+ fifo-size = <16>;
+ reg-io-width = <1>;
+ current-speed = <115200>;
+ no-loopback-test;
+ status = "disabled";
+ clocks = <&sysclk>;
+ resets = <&reset 18>;
+ };
+
+ rps@400000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0 0x400000 0x100000>;
+
+ intc: interrupt-controller@0 {
+ compatible = "oxsemi,ox820-rps-irq", "oxsemi,ox810se-rps-irq";
+ interrupt-controller;
+ reg = <0 0x200>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ valid-mask = <0xFFFFFFFF>;
+ clear-mask = <0>;
+ };
+
+ timer0: timer@200 {
+ compatible = "oxsemi,ox820-rps-timer";
+ reg = <0x200 0x40>;
+ clocks = <&sysclk>;
+ interrupt-parent = <&intc>;
+ interrupts = <4>;
+ };
+ };
+
+ sys: sys-ctrl@e00000 {
+ compatible = "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd";
+ reg = <0xe00000 0x200000>;
+
+ reset: reset-controller {
+ compatible = "oxsemi,ox820-reset", "oxsemi,ox810se-reset";
+ #reset-cells = <1>;
+ };
+
+ stdclk: stdclk {
+ compatible = "oxsemi,ox820-stdclk", "oxsemi,ox810se-stdclk";
+ #clock-cells = <1>;
+ };
+ };
+ };
+
+ apb-bridge@47000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0 0x47000000 0x1000000>;
+
+ scu: scu@0 {
+ compatible = "arm,arm11mp-scu";
+ reg = <0x0 0x100>;
+ };
+
+ local-timer@600 {
+ compatible = "arm,arm11mp-twd-timer";
+ reg = <0x600 0x20>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3)|IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&armclk>;
+ };
+
+ gic: gic@1000 {
+ compatible = "arm,arm11mp-gic";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x1000 0x1000>,
+ <0x100 0x500>;
+ };
+ };
+ };
+};
--
cgit
From 3f1b13f4e118378bb3c0bf533b8f89e70d4fb665 Mon Sep 17 00:00:00 2001
From: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Date: Thu, 20 Oct 2016 21:15:27 +0200
Subject: ARM: dts: armada-370-rn102: drop specification of compatible for i2c0
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
The compatible string is already provided by armada-370.dtsi.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm/boot/dts/armada-370-netgear-rn102.dts | 1 -
1 file changed, 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
index 39181b3fa90d..3ca6330a1752 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
@@ -120,7 +120,6 @@
};
i2c@11000 {
- compatible = "marvell,mv64xxx-i2c";
clock-frequency = <100000>;
status = "okay";
--
cgit
From ebbd9896a692316cf52a822d78abbace454d6bc3 Mon Sep 17 00:00:00 2001
From: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Date: Thu, 20 Oct 2016 21:19:42 +0200
Subject: ARM: dts: armada-370-rn102: add pinmuxing for i2c0
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Up to now a working i2c bus depended on the bootloader to configure the
pinmuxing. Make it explicit.
As a side effect this change makes i2c work in barebox.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm/boot/dts/armada-370-netgear-rn102.dts | 4 ++++
1 file changed, 4 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
index 3ca6330a1752..a9e3810aea65 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
@@ -121,6 +121,10 @@
i2c@11000 {
clock-frequency = <100000>;
+
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+
status = "okay";
isl12057: isl12057@68 {
--
cgit
From ed01154fe7dd1b199279892fde426ba7f7b6cd59 Mon Sep 17 00:00:00 2001
From: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Date: Fri, 4 Nov 2016 15:06:55 +0100
Subject: ARM: dts: Add GPIO irq support to STM32F429
Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
---
arch/arm/boot/dts/stm32f429.dtsi | 2 ++
1 file changed, 2 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 336ee4fb587d..3dd47ebe680b 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -190,6 +190,8 @@
#size-cells = <1>;
compatible = "st,stm32f429-pinctrl";
ranges = <0 0x40020000 0x3000>;
+ interrupt-parent = <&exti>;
+ st,syscfg = <&syscfg 0x8>;
pins-are-numbered;
gpioa: gpio@40020000 {
--
cgit
From 5670501c996955af681cfb674ce1fcdc3de10fc1 Mon Sep 17 00:00:00 2001
From: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Date: Fri, 2 Sep 2016 15:45:53 +0200
Subject: ARM: dts: Declare push button as GPIO key on stm32f429 boards
Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
---
arch/arm/boot/dts/stm32429i-eval.dts | 18 ++++++++++++++++++
arch/arm/boot/dts/stm32f429-disco.dts | 13 +++++++++++++
2 files changed, 31 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts
index 6bfc5959dac3..0fd78e4e8a45 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -47,6 +47,7 @@
/dts-v1/;
#include "stm32f429.dtsi"
+#include <dt-bindings/input/input.h>
/ {
model = "STMicroelectronics STM32429i-EVAL board";
@@ -82,6 +83,23 @@
};
};
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+ button@0 {
+ label = "Wake up";
+ linux,code = <KEY_WAKEUP>;
+ gpios = <&gpioa 0 0>;
+ };
+ button@1 {
+ label = "Tamper";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpioc 13 0>;
+ };
+ };
+
usbotg_hs_phy: usbphy {
#phy-cells = <0>;
compatible = "usb-nop-xceiv";
diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts
index 01408073dd53..7d0415e80668 100644
--- a/arch/arm/boot/dts/stm32f429-disco.dts
+++ b/arch/arm/boot/dts/stm32f429-disco.dts
@@ -47,6 +47,7 @@
/dts-v1/;
#include "stm32f429.dtsi"
+#include <dt-bindings/input/input.h>
/ {
model = "STMicroelectronics STM32F429i-DISCO board";
@@ -75,6 +76,18 @@
linux,default-trigger = "heartbeat";
};
};
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+ button@0 {
+ label = "User";
+ linux,code = <KEY_HOME>;
+ gpios = <&gpioa 0 0>;
+ };
+ };
};
&clk_hse {
--
cgit
From 73767f19a01872279fe63ac01598ea8dc240097f Mon Sep 17 00:00:00 2001
From: Gerald Baeza <gerald.baeza@st.com>
Date: Thu, 3 Nov 2016 15:08:43 +0100
Subject: ARM: DT: STM32: add dma for usart1 on F429
Tested-by: Bruno Herrera <bruherrera@gmail.com>
Signed-off-by: Gerald Baeza <gerald.baeza@st.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
---
arch/arm/boot/dts/stm32f429.dtsi | 3 +++
1 file changed, 3 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 3dd47ebe680b..f5ebad826374 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -162,6 +162,9 @@
interrupts = <37>;
clocks = <&rcc 0 164>;
status = "disabled";
+ dmas = <&dma2 2 4 0x400 0x0>,
+ <&dma2 7 4 0x400 0x0>;
+ dma-names = "rx", "tx";
};
usart6: serial@40011400 {
--
cgit
From f113438990550e5bf8fe757a50e0ced0e710e379 Mon Sep 17 00:00:00 2001
From: Alexandre TORGUE <alexandre.torgue@st.com>
Date: Mon, 24 Oct 2016 15:22:43 +0200
Subject: ARM: DT: STM32: add dma for usart3 on F429
Add DMA support for USART3 on STM32F429 MCU.
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
---
arch/arm/boot/dts/stm32f429.dtsi | 3 +++
1 file changed, 3 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index f5ebad826374..1c54f9e68723 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -122,6 +122,9 @@
interrupts = <39>;
clocks = <&rcc 0 146>;
status = "disabled";
+ dmas = <&dma1 1 4 0x400 0x0>,
+ <&dma1 3 4 0x400 0x0>;
+ dma-names = "rx", "tx";
};
usart4: serial@40004c00 {
--
cgit
From 626e7ea0021501dc6e35ef89a936cd1e25f30b26 Mon Sep 17 00:00:00 2001
From: Alexandre TORGUE <alexandre.torgue@st.com>
Date: Thu, 3 Nov 2016 15:16:38 +0100
Subject: ARM: DT: stm32: move dma translation to board files
stm32f469-disco and stm32f429-eval boards use SDRAM start address remapping
(to @0) to boost performances. A DMA translation through "dma-ranges"
property was needed for other masters than the M4 CPU.
stm32f429-disco doesn't use remapping so doesn't need this DMA translation.
This patches moves this DMA translation definition from stm32f429 soc file
to board files.
Tested-by: Bruno Herrera <bruherrera@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
---
arch/arm/boot/dts/stm32429i-eval.dts | 4 ++++
arch/arm/boot/dts/stm32f429.dtsi | 4 ----
arch/arm/boot/dts/stm32f469-disco.dts | 4 ++++
3 files changed, 8 insertions(+), 4 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts
index 0fd78e4e8a45..7d2f84df1a03 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -66,6 +66,10 @@
serial0 = &usart1;
};
+ soc {
+ dma-ranges = <0xc0000000 0x0 0x10000000>;
+ };
+
leds {
compatible = "gpio-leds";
green {
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 1c54f9e68723..8af8ac9d94e1 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -59,8 +59,6 @@
};
soc {
- dma-ranges = <0xc0000000 0x0 0x10000000>;
-
timer2: timer@40000000 {
compatible = "st,stm32-timer";
reg = <0x40000000 0x400>;
@@ -392,13 +390,11 @@
st,syscon = <&syscfg 0x4>;
snps,pbl = <8>;
snps,mixed-burst;
- dma-ranges;
status = "disabled";
};
usbotg_hs: usb@40040000 {
compatible = "snps,dwc2";
- dma-ranges;
reg = <0x40040000 0x40000>;
interrupts = <77>;
clocks = <&rcc 0 29>;
diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts
index e911af836471..b766511357de 100644
--- a/arch/arm/boot/dts/stm32f469-disco.dts
+++ b/arch/arm/boot/dts/stm32f469-disco.dts
@@ -64,6 +64,10 @@
aliases {
serial0 = &usart3;
};
+
+ soc {
+ dma-ranges = <0xc0000000 0x0 0x10000000>;
+ };
};
&clk_hse {
--
cgit
From d9b296b91a1216bfd0a1ecf7242ecd4c53566ef1 Mon Sep 17 00:00:00 2001
From: Alexandre TORGUE <alexandre.torgue@st.com>
Date: Mon, 24 Oct 2016 09:57:08 +0200
Subject: ARM: dts: stm32f429: Align Ethernet node with new bindings properties
This patch aligns clocks names and node reference according to new
stm32-dwmac glue binding. It also renames Ethernet pinctrl phandle
(indeed there is no need to add 0 as Ethernet instance as there is only
one IP in SOC).
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
---
arch/arm/boot/dts/stm32429i-eval.dts | 7 ++++---
arch/arm/boot/dts/stm32f429.dtsi | 6 +++---
2 files changed, 7 insertions(+), 6 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts
index 7d2f84df1a03..380a002829d6 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -116,11 +116,12 @@
clock-frequency = <25000000>;
};
-ðernet0 {
+&mac {
status = "okay";
- pinctrl-0 = <ðernet0_mii>;
+ pinctrl-0 = <ðernet_mii>;
pinctrl-names = "default";
- phy-mode = "mii-id";
+ phy-mode = "mii";
+
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 8af8ac9d94e1..b9286607e9f9 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -319,7 +319,7 @@
};
};
- ethernet0_mii: mii@0 {
+ ethernet_mii: mii@0 {
pins {
pinmux = <STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
<STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
@@ -379,13 +379,13 @@
st,mem2mem;
};
- ethernet0: dwmac@40028000 {
+ mac: ethernet@40028000 {
compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
reg = <0x40028000 0x8000>;
reg-names = "stmmaceth";
interrupts = <61>, <62>;
interrupt-names = "macirq", "eth_wake_irq";
- clock-names = "stmmaceth", "tx-clk", "rx-clk";
+ clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
st,syscon = <&syscfg 0x4>;
snps,pbl = <8>;
--
cgit
From 682d77cf0a9be04515c802c707749862ce3ef8b7 Mon Sep 17 00:00:00 2001
From: Alexandre TORGUE <alexandre.torgue@st.com>
Date: Wed, 7 Sep 2016 12:28:17 +0200
Subject: ARM: dts: stm32f429: Fix Ethernet node on Eval Board
"phy-handle" entry is mandatory when mdio subnode is used in
Ethernet node.
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
---
arch/arm/boot/dts/stm32429i-eval.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts
index 380a002829d6..5436e880e28f 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -121,7 +121,7 @@
pinctrl-0 = <ðernet_mii>;
pinctrl-names = "default";
phy-mode = "mii";
-
+ phy-handle = <&phy1>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
--
cgit
From ed75bf3380bb5810d67a96cc8b61ec9ea95dea70 Mon Sep 17 00:00:00 2001
From: Alexandre TORGUE <alexandre.torgue@st.com>
Date: Thu, 20 Oct 2016 16:58:26 +0200
Subject: ARM: dts: stm32f429: remove Ethernet wake on Lan support
This patch removes WoL (Wake on Lan) support as it is not yet
fully supported and tested.
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
---
arch/arm/boot/dts/stm32f429.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index b9286607e9f9..b02a31edd0b2 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -383,8 +383,8 @@
compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
reg = <0x40028000 0x8000>;
reg-names = "stmmaceth";
- interrupts = <61>, <62>;
- interrupt-names = "macirq", "eth_wake_irq";
+ interrupts = <61>;
+ interrupt-names = "macirq";
clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
st,syscon = <&syscfg 0x4>;
--
cgit
From f6dbbff4f0af1a5c0d6eaf414572b5eff7a73a8b Mon Sep 17 00:00:00 2001
From: Gabriel Fernandez <gabriel.fernandez@st.com>
Date: Fri, 14 Oct 2016 11:18:00 +0200
Subject: ARM: dts: stm32f429: add LSI and LSE clocks
This patch adds lsi / lse oscillators. These clocks can be use by
RTC clocks.
The clock drivers needs to disable the power domain write protection using
syscon / regmap to enable these clocks.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
---
arch/arm/boot/dts/stm32f429.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index b02a31edd0b2..e4dae0eda3cd 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -56,6 +56,18 @@
compatible = "fixed-clock";
clock-frequency = <0>;
};
+
+ clk-lse {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ clk-lsi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ };
};
soc {
@@ -189,6 +201,11 @@
interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
};
+ pwrcfg: power-config@40007000 {
+ compatible = "syscon";
+ reg = <0x40007000 0x400>;
+ };
+
pin-controller {
#address-cells = <1>;
#size-cells = <1>;
@@ -346,6 +363,7 @@
compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
reg = <0x40023800 0x400>;
clocks = <&clk_hse>;
+ st,syscfg = <&pwrcfg>;
};
dma1: dma-controller@40026000 {
--
cgit
From 6c0dceaae604cff7b54c9a90409b28990645c103 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Mon, 17 Oct 2016 00:42:43 +0900
Subject: ARM: dts: uniphier: increase register region size of sysctrl node
The System Control node has 0x10000 byte of registers. The current
reg size must be expanded to use the cpufreq driver because the
registers controlling CPU frequency are located at offset 0x8000.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
arch/arm/boot/dts/uniphier-common32.dtsi | 2 +-
arch/arm/boot/dts/uniphier-sld3.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/uniphier-common32.dtsi b/arch/arm/boot/dts/uniphier-common32.dtsi
index 8c8a85176b64..d067f38fa21d 100644
--- a/arch/arm/boot/dts/uniphier-common32.dtsi
+++ b/arch/arm/boot/dts/uniphier-common32.dtsi
@@ -183,7 +183,7 @@
sysctrl@61840000 {
compatible = "socionext,uniphier-sysctrl",
"simple-mfd", "syscon";
- reg = <0x61840000 0x4000>;
+ reg = <0x61840000 0x10000>;
sys_clk: clock {
#clock-cells = <1>;
diff --git a/arch/arm/boot/dts/uniphier-sld3.dtsi b/arch/arm/boot/dts/uniphier-sld3.dtsi
index 5fa96c939b5c..35c18197d94f 100644
--- a/arch/arm/boot/dts/uniphier-sld3.dtsi
+++ b/arch/arm/boot/dts/uniphier-sld3.dtsi
@@ -271,7 +271,7 @@
sysctrl@f1840000 {
compatible = "socionext,uniphier-sysctrl",
"simple-mfd", "syscon";
- reg = <0xf1840000 0x4000>;
+ reg = <0xf1840000 0x10000>;
sys_clk: clock {
compatible = "socionext,uniphier-sld3-clock";
--
cgit
From 35167e27f2b7f50538dfb81f144ccb8dd89adcac Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 27 Oct 2016 01:37:38 +0900
Subject: ARM: dts: uniphier: add CPU clocks and OPP table for Pro5 SoC
Add a CPU clock to every CPU node and a CPU OPP table to use the
generic cpufreq driver.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
---
arch/arm/boot/dts/uniphier-pro5.dtsi | 74 ++++++++++++++++++++++++++++++++++++
1 file changed, 74 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi
index 5357ea9c14b1..5bd6068ac14b 100644
--- a/arch/arm/boot/dts/uniphier-pro5.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro5.dtsi
@@ -56,16 +56,90 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
+ clocks = <&sys_clk 32>;
enable-method = "psci";
next-level-cache = <&l2>;
+ operating-points-v2 = <&cpu_opp>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
+ clocks = <&sys_clk 32>;
enable-method = "psci";
next-level-cache = <&l2>;
+ operating-points-v2 = <&cpu_opp>;
+ };
+ };
+
+ cpu_opp: opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@116667000 {
+ opp-hz = /bits/ 64 <116667000>;
+ clock-latency-ns = <300>;
+ };
+ opp@150000000 {
+ opp-hz = /bits/ 64 <150000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@175000000 {
+ opp-hz = /bits/ 64 <175000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@233334000 {
+ opp-hz = /bits/ 64 <233334000>;
+ clock-latency-ns = <300>;
+ };
+ opp@300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@350000000 {
+ opp-hz = /bits/ 64 <350000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@466667000 {
+ opp-hz = /bits/ 64 <466667000>;
+ clock-latency-ns = <300>;
+ };
+ opp@600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@700000000 {
+ opp-hz = /bits/ 64 <700000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@933334000 {
+ opp-hz = /bits/ 64 <933334000>;
+ clock-latency-ns = <300>;
+ };
+ opp@1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ clock-latency-ns = <300>;
};
};
--
cgit
From 7a8a6588219dba5b47ebd4fa74ec2c1d81f0ee9f Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 27 Oct 2016 01:37:39 +0900
Subject: ARM: dts: uniphier: add CPU clocks and OPP table for PXs2 SoC
Add a CPU clock to every CPU node and a CPU OPP table to use the
generic cpufreq driver.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
---
arch/arm/boot/dts/uniphier-pxs2.dtsi | 46 ++++++++++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi
index 950f07ba0337..83ba3e60b4bd 100644
--- a/arch/arm/boot/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi
@@ -56,32 +56,78 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
+ clocks = <&sys_clk 32>;
enable-method = "psci";
next-level-cache = <&l2>;
+ operating-points-v2 = <&cpu_opp>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
+ clocks = <&sys_clk 32>;
enable-method = "psci";
next-level-cache = <&l2>;
+ operating-points-v2 = <&cpu_opp>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <2>;
+ clocks = <&sys_clk 32>;
enable-method = "psci";
next-level-cache = <&l2>;
+ operating-points-v2 = <&cpu_opp>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <3>;
+ clocks = <&sys_clk 32>;
enable-method = "psci";
next-level-cache = <&l2>;
+ operating-points-v2 = <&cpu_opp>;
+ };
+ };
+
+ cpu_opp: opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@150000000 {
+ opp-hz = /bits/ 64 <150000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ clock-latency-ns = <300>;
};
};
--
cgit
From 1be81ea5860744520e06d0dfb9e3490b45902dbb Mon Sep 17 00:00:00 2001
From: Joshua Clayton <stillcompiling@gmail.com>
Date: Tue, 1 Nov 2016 16:51:45 -0700
Subject: ARM: dts: imx6: Add imx-weim parameters to dtsi's
imx-weim should always set address-cells to 2,
and size_cells to 1.
On imx6, fsl,weim-cs-gpr will always be &gpr
Set these common parameters in the dtsi file,
rather than in a downstream dts.
Signed-off-by: Joshua Clayton <stillcompiling@gmail.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/imx6q-evi.dts | 3 ---
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 2 --
arch/arm/boot/dts/imx6qdl.dtsi | 3 +++
arch/arm/boot/dts/imx6sl.dtsi | 3 +++
arch/arm/boot/dts/imx6sx.dtsi | 3 +++
5 files changed, 9 insertions(+), 5 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts
index 6de21ff47c3a..7c7c1a855ece 100644
--- a/arch/arm/boot/dts/imx6q-evi.dts
+++ b/arch/arm/boot/dts/imx6q-evi.dts
@@ -232,10 +232,7 @@
};
&weim {
- #address-cells = <2>;
- #size-cells = <1>;
ranges = <0 0 0x08000000 0x08000000>;
- fsl,weim-cs-gpr = <&gpr>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_weimfpga &pinctrl_weimcs>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 80064678ba3c..52390ba83e81 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -613,8 +613,6 @@
&weim {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
- #address-cells = <2>;
- #size-cells = <1>;
ranges = <0 0 0x08000000 0x08000000>;
status = "disabled"; /* pin conflict with SPI NOR */
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 1bbd36f40424..d7bed1f8ff1d 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1092,10 +1092,13 @@
};
weim: weim@021b8000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
compatible = "fsl,imx6q-weim";
reg = <0x021b8000 0x4000>;
interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
+ fsl,weim-cs-gpr = <&gpr>;
};
ocotp: ocotp@021bc000 {
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 02378db3f5fc..c2b28c06e50d 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -893,8 +893,11 @@
};
weim: weim@021b8000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
reg = <0x021b8000 0x4000>;
interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,weim-cs-gpr = <&gpr>;
};
ocotp: ocotp@021bc000 {
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index bd9fe6745601..dbc540f5fec5 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -968,10 +968,13 @@
};
weim: weim@021b8000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
reg = <0x021b8000 0x4000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
+ fsl,weim-cs-gpr = <&gpr>;
};
ocotp: ocotp@021bc000 {
--
cgit
From 2752bcaa1a9495573ed799c208309a8fba135f3d Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Mon, 31 Oct 2016 16:29:24 +0900
Subject: ARM: dts: uniphier: make 32bit SoC DTSI linear
I notice some mistakes in the SoC DTSI; wrong interrupts properties
of timer nodes, mismatch between the node name and the compatible
for sdctrl block. Given those problems fixed, the common parts
among SoCs are less than I had first expected. The more and more
property overrides are making the SoC DTSI unreadable.
Stretch out the SoC DTSI files and fix the following:
- Fix the 3rd cell of the interrupts property of the timer nodes
for Pro4, Pro5, PXs2
- Fix the node name mioctrl to sdctrl for Pro5, PXs2
- Fix the second region of l2 node for PXs2
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
arch/arm/boot/dts/uniphier-common32.dtsi | 199 ----------------
arch/arm/boot/dts/uniphier-ld4.dtsi | 358 +++++++++++++++++++----------
arch/arm/boot/dts/uniphier-pro4.dtsi | 378 ++++++++++++++++++++-----------
arch/arm/boot/dts/uniphier-pro5.dtsi | 358 +++++++++++++++++++----------
arch/arm/boot/dts/uniphier-pxs2.dtsi | 353 +++++++++++++++++++----------
arch/arm/boot/dts/uniphier-sld8.dtsi | 359 +++++++++++++++++++----------
6 files changed, 1209 insertions(+), 796 deletions(-)
delete mode 100644 arch/arm/boot/dts/uniphier-common32.dtsi
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/uniphier-common32.dtsi b/arch/arm/boot/dts/uniphier-common32.dtsi
deleted file mode 100644
index d067f38fa21d..000000000000
--- a/arch/arm/boot/dts/uniphier-common32.dtsi
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
- * Device Tree Source commonly used by UniPhier ARM SoCs
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/include/ "skeleton.dtsi"
-
-/ {
- psci {
- compatible = "arm,psci-0.2";
- method = "smc";
- };
-
- clocks {
- refclk: ref {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- };
- };
-
- soc: soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- interrupt-parent = <&intc>;
-
- serial0: serial@54006800 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006800 0x40>;
- interrupts = <0 33 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart0>;
- clocks = <&peri_clk 0>;
- };
-
- serial1: serial@54006900 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006900 0x40>;
- interrupts = <0 35 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- clocks = <&peri_clk 1>;
- };
-
- serial2: serial@54006a00 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006a00 0x40>;
- interrupts = <0 37 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- clocks = <&peri_clk 2>;
- };
-
- serial3: serial@54006b00 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006b00 0x40>;
- interrupts = <0 177 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- clocks = <&peri_clk 3>;
- };
-
- system_bus: system-bus@58c00000 {
- compatible = "socionext,uniphier-system-bus";
- status = "disabled";
- reg = <0x58c00000 0x400>;
- #address-cells = <2>;
- #size-cells = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_system_bus>;
- };
-
- smpctrl@59800000 {
- compatible = "socionext,uniphier-smpctrl";
- reg = <0x59801000 0x400>;
- };
-
- mioctrl@59810000 {
- compatible = "socionext,uniphier-mioctrl",
- "simple-mfd", "syscon";
- reg = <0x59810000 0x800>;
-
- mio_clk: clock {
- #clock-cells = <1>;
- };
-
- mio_rst: reset {
- #reset-cells = <1>;
- };
- };
-
- perictrl@59820000 {
- compatible = "socionext,uniphier-perictrl",
- "simple-mfd", "syscon";
- reg = <0x59820000 0x200>;
-
- peri_clk: clock {
- #clock-cells = <1>;
- };
-
- peri_rst: reset {
- #reset-cells = <1>;
- };
- };
-
- timer@60000200 {
- compatible = "arm,cortex-a9-global-timer";
- reg = <0x60000200 0x20>;
- interrupts = <1 11 0x104>;
- clocks = <&arm_timer_clk>;
- };
-
- timer@60000600 {
- compatible = "arm,cortex-a9-twd-timer";
- reg = <0x60000600 0x20>;
- interrupts = <1 13 0x104>;
- clocks = <&arm_timer_clk>;
- };
-
- intc: interrupt-controller@60001000 {
- compatible = "arm,cortex-a9-gic";
- reg = <0x60001000 0x1000>,
- <0x60000100 0x100>;
- #interrupt-cells = <3>;
- interrupt-controller;
- };
-
- soc-glue@5f800000 {
- compatible = "socionext,uniphier-soc-glue",
- "simple-mfd", "syscon";
- reg = <0x5f800000 0x2000>;
-
- pinctrl: pinctrl {
- /* specify compatible in each SoC DTSI */
- };
- };
-
- sysctrl@61840000 {
- compatible = "socionext,uniphier-sysctrl",
- "simple-mfd", "syscon";
- reg = <0x61840000 0x10000>;
-
- sys_clk: clock {
- #clock-cells = <1>;
- };
-
- sys_rst: reset {
- #reset-cells = <1>;
- };
- };
- };
-};
-
-/include/ "uniphier-pinctrl.dtsi"
diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi
index 95f342c9d9c1..a7c494d7c43a 100644
--- a/arch/arm/boot/dts/uniphier-ld4.dtsi
+++ b/arch/arm/boot/dts/uniphier-ld4.dtsi
@@ -43,7 +43,7 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-/include/ "uniphier-common32.dtsi"
+/include/ "skeleton.dtsi"
/ {
compatible = "socionext,uniphier-ld4";
@@ -61,147 +61,267 @@
};
};
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
clocks {
+ refclk: ref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24576000>;
+ };
+
arm_timer_clk: arm_timer_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
};
-};
-
-&soc {
- l2: l2-cache@500c0000 {
- compatible = "socionext,uniphier-system-cache";
- reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
- interrupts = <0 174 4>, <0 175 4>;
- cache-unified;
- cache-size = <(512 * 1024)>;
- cache-sets = <256>;
- cache-line-size = <128>;
- cache-level = <2>;
- };
- i2c0: i2c@58400000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58400000 0x40>;
+ soc {
+ compatible = "simple-bus";
#address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 41 1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0>;
- clocks = <&peri_clk 4>;
- clock-frequency = <100000>;
- };
+ #size-cells = <1>;
+ ranges;
+ interrupt-parent = <&intc>;
- i2c1: i2c@58480000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58480000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 42 1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- clocks = <&peri_clk 5>;
- clock-frequency = <100000>;
- };
+ l2: l2-cache@500c0000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
+ <0x506c0000 0x400>;
+ interrupts = <0 174 4>, <0 175 4>;
+ cache-unified;
+ cache-size = <(512 * 1024)>;
+ cache-sets = <256>;
+ cache-line-size = <128>;
+ cache-level = <2>;
+ };
- /* chip-internal connection for DMD */
- i2c2: i2c@58500000 {
- compatible = "socionext,uniphier-i2c";
- reg = <0x58500000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 43 1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- clocks = <&peri_clk 6>;
- clock-frequency = <400000>;
- };
+ serial0: serial@54006800 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006800 0x40>;
+ interrupts = <0 33 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
+ clocks = <&peri_clk 0>;
+ };
- i2c3: i2c@58580000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58580000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 44 1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- clocks = <&peri_clk 7>;
- clock-frequency = <100000>;
- };
+ serial1: serial@54006900 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006900 0x40>;
+ interrupts = <0 35 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ clocks = <&peri_clk 1>;
+ };
- usb0: usb@5a800100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a800100 0x100>;
- interrupts = <0 80 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0>;
- clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
- resets = <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>, <&sys_rst 8>;
- };
+ serial2: serial@54006a00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006a00 0x40>;
+ interrupts = <0 37 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ clocks = <&peri_clk 2>;
+ };
- usb1: usb@5a810100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a810100 0x100>;
- interrupts = <0 81 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1>;
- clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
- resets = <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>, <&sys_rst 8>;
- };
+ serial3: serial@54006b00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006b00 0x40>;
+ interrupts = <0 29 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ clocks = <&peri_clk 3>;
+ };
- usb2: usb@5a820100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a820100 0x100>;
- interrupts = <0 82 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb2>;
- clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
- resets = <&mio_rst 7>, <&mio_rst 10>, <&mio_rst 14>, <&sys_rst 8>;
- };
+ i2c0: i2c@58400000 {
+ compatible = "socionext,uniphier-i2c";
+ status = "disabled";
+ reg = <0x58400000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ clocks = <&peri_clk 4>;
+ clock-frequency = <100000>;
+ };
-};
+ i2c1: i2c@58480000 {
+ compatible = "socionext,uniphier-i2c";
+ status = "disabled";
+ reg = <0x58480000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 42 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clocks = <&peri_clk 5>;
+ clock-frequency = <100000>;
+ };
-&refclk {
- clock-frequency = <24576000>;
-};
+ /* chip-internal connection for DMD */
+ i2c2: i2c@58500000 {
+ compatible = "socionext,uniphier-i2c";
+ reg = <0x58500000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 43 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clocks = <&peri_clk 6>;
+ clock-frequency = <400000>;
+ };
-&serial3 {
- interrupts = <0 29 4>;
-};
+ i2c3: i2c@58580000 {
+ compatible = "socionext,uniphier-i2c";
+ status = "disabled";
+ reg = <0x58580000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 44 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clocks = <&peri_clk 7>;
+ clock-frequency = <100000>;
+ };
-&mio_clk {
- compatible = "socionext,uniphier-ld4-mio-clock";
-};
+ system_bus: system-bus@58c00000 {
+ compatible = "socionext,uniphier-system-bus";
+ status = "disabled";
+ reg = <0x58c00000 0x400>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_system_bus>;
+ };
-&mio_rst {
- compatible = "socionext,uniphier-ld4-mio-reset";
- resets = <&sys_rst 7>;
-};
+ smpctrl@59800000 {
+ compatible = "socionext,uniphier-smpctrl";
+ reg = <0x59801000 0x400>;
+ };
-&peri_clk {
- compatible = "socionext,uniphier-ld4-peri-clock";
-};
+ mioctrl@59810000 {
+ compatible = "socionext,uniphier-ld4-mioctrl",
+ "simple-mfd", "syscon";
+ reg = <0x59810000 0x800>;
-&peri_rst {
- compatible = "socionext,uniphier-ld4-peri-reset";
-};
+ mio_clk: clock {
+ compatible = "socionext,uniphier-ld4-mio-clock";
+ #clock-cells = <1>;
+ };
-&pinctrl {
- compatible = "socionext,uniphier-ld4-pinctrl";
-};
+ mio_rst: reset {
+ compatible = "socionext,uniphier-ld4-mio-reset";
+ #reset-cells = <1>;
+ };
+ };
-&sys_clk {
- compatible = "socionext,uniphier-ld4-clock";
-};
+ perictrl@59820000 {
+ compatible = "socionext,uniphier-ld4-perictrl",
+ "simple-mfd", "syscon";
+ reg = <0x59820000 0x200>;
+
+ peri_clk: clock {
+ compatible = "socionext,uniphier-ld4-peri-clock";
+ #clock-cells = <1>;
+ };
+
+ peri_rst: reset {
+ compatible = "socionext,uniphier-ld4-peri-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ usb0: usb@5a800100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a800100 0x100>;
+ interrupts = <0 80 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>;
+ clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
+ <&mio_rst 12>;
+ };
+
+ usb1: usb@5a810100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a810100 0x100>;
+ interrupts = <0 81 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>;
+ clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
+ <&mio_rst 13>;
+ };
-&sys_rst {
- compatible = "socionext,uniphier-ld4-reset";
+ usb2: usb@5a820100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a820100 0x100>;
+ interrupts = <0 82 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb2>;
+ clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
+ <&mio_rst 14>;
+ };
+
+ soc-glue@5f800000 {
+ compatible = "socionext,uniphier-ld4-soc-glue",
+ "simple-mfd", "syscon";
+ reg = <0x5f800000 0x2000>;
+
+ pinctrl: pinctrl {
+ compatible = "socionext,uniphier-ld4-pinctrl";
+ };
+ };
+
+ timer@60000200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0x60000200 0x20>;
+ interrupts = <1 11 0x104>;
+ clocks = <&arm_timer_clk>;
+ };
+
+ timer@60000600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x60000600 0x20>;
+ interrupts = <1 13 0x104>;
+ clocks = <&arm_timer_clk>;
+ };
+
+ intc: interrupt-controller@60001000 {
+ compatible = "arm,cortex-a9-gic";
+ reg = <0x60001000 0x1000>,
+ <0x60000100 0x100>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ };
+
+ sysctrl@61840000 {
+ compatible = "socionext,uniphier-ld4-sysctrl",
+ "simple-mfd", "syscon";
+ reg = <0x61840000 0x10000>;
+
+ sys_clk: clock {
+ compatible = "socionext,uniphier-ld4-clock";
+ #clock-cells = <1>;
+ };
+
+ sys_rst: reset {
+ compatible = "socionext,uniphier-ld4-reset";
+ #reset-cells = <1>;
+ };
+ };
+ };
};
+
+/include/ "uniphier-pinctrl.dtsi"
diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi
index ba700267ad66..e960b09ff01c 100644
--- a/arch/arm/boot/dts/uniphier-pro4.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro4.dtsi
@@ -43,7 +43,7 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-/include/ "uniphier-common32.dtsi"
+/include/ "skeleton.dtsi"
/ {
compatible = "socionext,uniphier-pro4";
@@ -69,155 +69,279 @@
};
};
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
clocks {
+ refclk: ref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
arm_timer_clk: arm_timer_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
};
-};
-&soc {
- l2: l2-cache@500c0000 {
- compatible = "socionext,uniphier-system-cache";
- reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
- interrupts = <0 174 4>, <0 175 4>;
- cache-unified;
- cache-size = <(768 * 1024)>;
- cache-sets = <256>;
- cache-line-size = <128>;
- cache-level = <2>;
- };
-
- i2c0: i2c@58780000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58780000 0x80>;
+ soc {
+ compatible = "simple-bus";
#address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 41 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0>;
- clocks = <&peri_clk 4>;
- clock-frequency = <100000>;
- };
+ #size-cells = <1>;
+ ranges;
+ interrupt-parent = <&intc>;
- i2c1: i2c@58781000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58781000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 42 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- clocks = <&peri_clk 5>;
- clock-frequency = <100000>;
- };
+ l2: l2-cache@500c0000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
+ <0x506c0000 0x400>;
+ interrupts = <0 174 4>, <0 175 4>;
+ cache-unified;
+ cache-size = <(768 * 1024)>;
+ cache-sets = <256>;
+ cache-line-size = <128>;
+ cache-level = <2>;
+ };
- i2c2: i2c@58782000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58782000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 43 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- clocks = <&peri_clk 6>;
- clock-frequency = <100000>;
- };
+ serial0: serial@54006800 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006800 0x40>;
+ interrupts = <0 33 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
+ clocks = <&peri_clk 0>;
+ };
- i2c3: i2c@58783000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58783000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 44 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- clocks = <&peri_clk 7>;
- clock-frequency = <100000>;
- };
+ serial1: serial@54006900 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006900 0x40>;
+ interrupts = <0 35 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ clocks = <&peri_clk 1>;
+ };
- /* i2c4 does not exist */
+ serial2: serial@54006a00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006a00 0x40>;
+ interrupts = <0 37 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ clocks = <&peri_clk 2>;
+ };
- /* chip-internal connection for DMD */
- i2c5: i2c@58785000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58785000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 25 4>;
- clocks = <&peri_clk 9>;
- clock-frequency = <400000>;
- };
+ serial3: serial@54006b00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006b00 0x40>;
+ interrupts = <0 177 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ clocks = <&peri_clk 3>;
+ };
- /* chip-internal connection for HDMI */
- i2c6: i2c@58786000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58786000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 26 4>;
- clocks = <&peri_clk 10>;
- clock-frequency = <400000>;
- };
+ i2c0: i2c@58780000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58780000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ clocks = <&peri_clk 4>;
+ clock-frequency = <100000>;
+ };
- usb2: usb@5a800100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a800100 0x100>;
- interrupts = <0 80 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb2>;
- clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
- resets = <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>, <&sys_rst 8>;
- };
+ i2c1: i2c@58781000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58781000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 42 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clocks = <&peri_clk 5>;
+ clock-frequency = <100000>;
+ };
- usb3: usb@5a810100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a810100 0x100>;
- interrupts = <0 81 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb3>;
- clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
- resets = <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>, <&sys_rst 8>;
- };
-};
+ i2c2: i2c@58782000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58782000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 43 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clocks = <&peri_clk 6>;
+ clock-frequency = <100000>;
+ };
-&refclk {
- clock-frequency = <25000000>;
-};
+ i2c3: i2c@58783000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58783000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 44 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clocks = <&peri_clk 7>;
+ clock-frequency = <100000>;
+ };
-&mio_clk {
- compatible = "socionext,uniphier-pro4-mio-clock";
-};
+ /* i2c4 does not exist */
-&mio_rst {
- compatible = "socionext,uniphier-pro4-mio-reset";
- resets = <&sys_rst 7>;
-};
+ /* chip-internal connection for DMD */
+ i2c5: i2c@58785000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58785000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 25 4>;
+ clocks = <&peri_clk 9>;
+ clock-frequency = <400000>;
+ };
-&peri_clk {
- compatible = "socionext,uniphier-pro4-peri-clock";
-};
+ /* chip-internal connection for HDMI */
+ i2c6: i2c@58786000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58786000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 26 4>;
+ clocks = <&peri_clk 10>;
+ clock-frequency = <400000>;
+ };
-&peri_rst {
- compatible = "socionext,uniphier-pro4-peri-reset";
-};
+ system_bus: system-bus@58c00000 {
+ compatible = "socionext,uniphier-system-bus";
+ status = "disabled";
+ reg = <0x58c00000 0x400>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_system_bus>;
+ };
-&pinctrl {
- compatible = "socionext,uniphier-pro4-pinctrl";
-};
+ smpctrl@59800000 {
+ compatible = "socionext,uniphier-smpctrl";
+ reg = <0x59801000 0x400>;
+ };
-&sys_clk {
- compatible = "socionext,uniphier-pro4-clock";
-};
+ mioctrl@59810000 {
+ compatible = "socionext,uniphier-pro4-mioctrl",
+ "simple-mfd", "syscon";
+ reg = <0x59810000 0x800>;
+
+ mio_clk: clock {
+ compatible = "socionext,uniphier-pro4-mio-clock";
+ #clock-cells = <1>;
+ };
+
+ mio_rst: reset {
+ compatible = "socionext,uniphier-pro4-mio-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ perictrl@59820000 {
+ compatible = "socionext,uniphier-pro4-perictrl",
+ "simple-mfd", "syscon";
+ reg = <0x59820000 0x200>;
+
+ peri_clk: clock {
+ compatible = "socionext,uniphier-pro4-peri-clock";
+ #clock-cells = <1>;
+ };
+
+ peri_rst: reset {
+ compatible = "socionext,uniphier-pro4-peri-reset";
+ #reset-cells = <1>;
+ };
+ };
-&sys_rst {
- compatible = "socionext,uniphier-pro4-reset";
+ usb2: usb@5a800100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a800100 0x100>;
+ interrupts = <0 80 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb2>;
+ clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
+ <&mio_rst 12>;
+ };
+
+ usb3: usb@5a810100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a810100 0x100>;
+ interrupts = <0 81 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb3>;
+ clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
+ <&mio_rst 13>;
+ };
+
+ soc-glue@5f800000 {
+ compatible = "socionext,uniphier-pro4-soc-glue",
+ "simple-mfd", "syscon";
+ reg = <0x5f800000 0x2000>;
+
+ pinctrl: pinctrl {
+ compatible = "socionext,uniphier-pro4-pinctrl";
+ };
+ };
+
+ timer@60000200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0x60000200 0x20>;
+ interrupts = <1 11 0x304>;
+ clocks = <&arm_timer_clk>;
+ };
+
+ timer@60000600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x60000600 0x20>;
+ interrupts = <1 13 0x304>;
+ clocks = <&arm_timer_clk>;
+ };
+
+ intc: interrupt-controller@60001000 {
+ compatible = "arm,cortex-a9-gic";
+ reg = <0x60001000 0x1000>,
+ <0x60000100 0x100>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ };
+
+ sysctrl@61840000 {
+ compatible = "socionext,uniphier-pro4-sysctrl",
+ "simple-mfd", "syscon";
+ reg = <0x61840000 0x10000>;
+
+ sys_clk: clock {
+ compatible = "socionext,uniphier-pro4-clock";
+ #clock-cells = <1>;
+ };
+
+ sys_rst: reset {
+ compatible = "socionext,uniphier-pro4-reset";
+ #reset-cells = <1>;
+ };
+ };
+ };
};
+
+/include/ "uniphier-pinctrl.dtsi"
diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi
index 5bd6068ac14b..dbc5e5333163 100644
--- a/arch/arm/boot/dts/uniphier-pro5.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro5.dtsi
@@ -43,7 +43,7 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-/include/ "uniphier-common32.dtsi"
+/include/ "skeleton.dtsi"
/ {
compatible = "socionext,uniphier-pro5";
@@ -143,144 +143,268 @@
};
};
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
clocks {
+ refclk: ref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <20000000>;
+ };
+
arm_timer_clk: arm_timer_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
};
-};
-&soc {
- l2: l2-cache@500c0000 {
- compatible = "socionext,uniphier-system-cache";
- reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;
- interrupts = <0 190 4>, <0 191 4>;
- cache-unified;
- cache-size = <(2 * 1024 * 1024)>;
- cache-sets = <512>;
- cache-line-size = <128>;
- cache-level = <2>;
- next-level-cache = <&l3>;
- };
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ interrupt-parent = <&intc>;
- l3: l3-cache@500c8000 {
- compatible = "socionext,uniphier-system-cache";
- reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;
- interrupts = <0 174 4>, <0 175 4>;
- cache-unified;
- cache-size = <(2 * 1024 * 1024)>;
- cache-sets = <512>;
- cache-line-size = <256>;
- cache-level = <3>;
- };
+ l2: l2-cache@500c0000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
+ <0x506c0000 0x400>;
+ interrupts = <0 190 4>, <0 191 4>;
+ cache-unified;
+ cache-size = <(2 * 1024 * 1024)>;
+ cache-sets = <512>;
+ cache-line-size = <128>;
+ cache-level = <2>;
+ next-level-cache = <&l3>;
+ };
- i2c0: i2c@58780000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58780000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 41 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0>;
- clocks = <&peri_clk 4>;
- clock-frequency = <100000>;
- };
+ l3: l3-cache@500c8000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
+ <0x506c8000 0x400>;
+ interrupts = <0 174 4>, <0 175 4>;
+ cache-unified;
+ cache-size = <(2 * 1024 * 1024)>;
+ cache-sets = <512>;
+ cache-line-size = <256>;
+ cache-level = <3>;
+ };
- i2c1: i2c@58781000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58781000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 42 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- clocks = <&peri_clk 5>;
- clock-frequency = <100000>;
- };
+ serial0: serial@54006800 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006800 0x40>;
+ interrupts = <0 33 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
+ clocks = <&peri_clk 0>;
+ };
- i2c2: i2c@58782000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58782000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 43 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- clocks = <&peri_clk 6>;
- clock-frequency = <100000>;
- };
+ serial1: serial@54006900 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006900 0x40>;
+ interrupts = <0 35 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ clocks = <&peri_clk 1>;
+ };
- i2c3: i2c@58783000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58783000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 44 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- clocks = <&peri_clk 7>;
- clock-frequency = <100000>;
- };
+ serial2: serial@54006a00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006a00 0x40>;
+ interrupts = <0 37 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ clocks = <&peri_clk 2>;
+ };
- /* i2c4 does not exist */
+ serial3: serial@54006b00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006b00 0x40>;
+ interrupts = <0 177 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ clocks = <&peri_clk 3>;
+ };
- /* chip-internal connection for DMD */
- i2c5: i2c@58785000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58785000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 25 4>;
- clocks = <&peri_clk 9>;
- clock-frequency = <400000>;
- };
+ i2c0: i2c@58780000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58780000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ clocks = <&peri_clk 4>;
+ clock-frequency = <100000>;
+ };
- /* chip-internal connection for HDMI */
- i2c6: i2c@58786000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58786000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 26 4>;
- clocks = <&peri_clk 10>;
- clock-frequency = <400000>;
- };
-};
+ i2c1: i2c@58781000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58781000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 42 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clocks = <&peri_clk 5>;
+ clock-frequency = <100000>;
+ };
-&refclk {
- clock-frequency = <20000000>;
-};
+ i2c2: i2c@58782000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58782000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 43 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clocks = <&peri_clk 6>;
+ clock-frequency = <100000>;
+ };
-&mio_clk {
- compatible = "socionext,uniphier-pro5-sd-clock";
-};
+ i2c3: i2c@58783000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58783000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 44 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clocks = <&peri_clk 7>;
+ clock-frequency = <100000>;
+ };
-&mio_rst {
- compatible = "socionext,uniphier-pro5-sd-reset";
-};
+ /* i2c4 does not exist */
-&peri_clk {
- compatible = "socionext,uniphier-pro5-peri-clock";
-};
+ /* chip-internal connection for DMD */
+ i2c5: i2c@58785000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58785000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 25 4>;
+ clocks = <&peri_clk 9>;
+ clock-frequency = <400000>;
+ };
-&peri_rst {
- compatible = "socionext,uniphier-pro5-peri-reset";
-};
+ /* chip-internal connection for HDMI */
+ i2c6: i2c@58786000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58786000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 26 4>;
+ clocks = <&peri_clk 10>;
+ clock-frequency = <400000>;
+ };
-&pinctrl {
- compatible = "socionext,uniphier-pro5-pinctrl";
-};
+ system_bus: system-bus@58c00000 {
+ compatible = "socionext,uniphier-system-bus";
+ status = "disabled";
+ reg = <0x58c00000 0x400>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_system_bus>;
+ };
-&sys_clk {
- compatible = "socionext,uniphier-pro5-clock";
-};
+ smpctrl@59800000 {
+ compatible = "socionext,uniphier-smpctrl";
+ reg = <0x59801000 0x400>;
+ };
+
+ sdctrl@59810000 {
+ compatible = "socionext,uniphier-pro5-sdctrl",
+ "simple-mfd", "syscon";
+ reg = <0x59810000 0x800>;
+
+ sd_clk: clock {
+ compatible = "socionext,uniphier-pro5-sd-clock";
+ #clock-cells = <1>;
+ };
+
+ sd_rst: reset {
+ compatible = "socionext,uniphier-pro5-sd-reset";
+ #reset-cells = <1>;
+ };
+ };
-&sys_rst {
- compatible = "socionext,uniphier-pro5-reset";
+ perictrl@59820000 {
+ compatible = "socionext,uniphier-pro5-perictrl",
+ "simple-mfd", "syscon";
+ reg = <0x59820000 0x200>;
+
+ peri_clk: clock {
+ compatible = "socionext,uniphier-pro5-peri-clock";
+ #clock-cells = <1>;
+ };
+
+ peri_rst: reset {
+ compatible = "socionext,uniphier-pro5-peri-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ soc-glue@5f800000 {
+ compatible = "socionext,uniphier-pro5-soc-glue",
+ "simple-mfd", "syscon";
+ reg = <0x5f800000 0x2000>;
+
+ pinctrl: pinctrl {
+ compatible = "socionext,uniphier-pro5-pinctrl";
+ };
+ };
+
+ timer@60000200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0x60000200 0x20>;
+ interrupts = <1 11 0x304>;
+ clocks = <&arm_timer_clk>;
+ };
+
+ timer@60000600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x60000600 0x20>;
+ interrupts = <1 13 0x304>;
+ clocks = <&arm_timer_clk>;
+ };
+
+ intc: interrupt-controller@60001000 {
+ compatible = "arm,cortex-a9-gic";
+ reg = <0x60001000 0x1000>,
+ <0x60000100 0x100>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ };
+
+ sysctrl@61840000 {
+ compatible = "socionext,uniphier-pro5-sysctrl",
+ "simple-mfd", "syscon";
+ reg = <0x61840000 0x10000>;
+
+ sys_clk: clock {
+ compatible = "socionext,uniphier-pro5-clock";
+ #clock-cells = <1>;
+ };
+
+ sys_rst: reset {
+ compatible = "socionext,uniphier-pro5-reset";
+ #reset-cells = <1>;
+ };
+ };
+ };
};
+
+/include/ "uniphier-pinctrl.dtsi"
diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi
index 83ba3e60b4bd..e9e031d63c1a 100644
--- a/arch/arm/boot/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi
@@ -43,7 +43,7 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-/include/ "uniphier-common32.dtsi"
+/include/ "skeleton.dtsi"
/ {
compatible = "socionext,uniphier-pxs2";
@@ -131,141 +131,264 @@
};
};
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
clocks {
+ refclk: ref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
arm_timer_clk: arm_timer_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
};
-};
-&soc {
- l2: l2-cache@500c0000 {
- compatible = "socionext,uniphier-system-cache";
- reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
- interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
- cache-unified;
- cache-size = <(1280 * 1024)>;
- cache-sets = <512>;
- cache-line-size = <128>;
- cache-level = <2>;
- };
-
- i2c0: i2c@58780000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58780000 0x80>;
+ soc {
+ compatible = "simple-bus";
#address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 41 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0>;
- clocks = <&peri_clk 4>;
- clock-frequency = <100000>;
- };
+ #size-cells = <1>;
+ ranges;
+ interrupt-parent = <&intc>;
- i2c1: i2c@58781000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58781000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 42 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- clocks = <&peri_clk 5>;
- clock-frequency = <100000>;
- };
+ l2: l2-cache@500c0000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
+ <0x506c0000 0x400>;
+ interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
+ cache-unified;
+ cache-size = <(1280 * 1024)>;
+ cache-sets = <512>;
+ cache-line-size = <128>;
+ cache-level = <2>;
+ };
- i2c2: i2c@58782000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58782000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- interrupts = <0 43 4>;
- clocks = <&peri_clk 6>;
- clock-frequency = <100000>;
- };
+ serial0: serial@54006800 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006800 0x40>;
+ interrupts = <0 33 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
+ clocks = <&peri_clk 0>;
+ };
- i2c3: i2c@58783000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58783000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 44 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- clocks = <&peri_clk 7>;
- clock-frequency = <100000>;
- };
+ serial1: serial@54006900 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006900 0x40>;
+ interrupts = <0 35 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ clocks = <&peri_clk 1>;
+ };
- /* chip-internal connection for DMD */
- i2c4: i2c@58784000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58784000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 45 4>;
- clocks = <&peri_clk 8>;
- clock-frequency = <400000>;
- };
+ serial2: serial@54006a00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006a00 0x40>;
+ interrupts = <0 37 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ clocks = <&peri_clk 2>;
+ };
- /* chip-internal connection for STM */
- i2c5: i2c@58785000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58785000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 25 4>;
- clocks = <&peri_clk 9>;
- clock-frequency = <400000>;
- };
+ serial3: serial@54006b00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006b00 0x40>;
+ interrupts = <0 177 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ clocks = <&peri_clk 3>;
+ };
- /* chip-internal connection for HDMI */
- i2c6: i2c@58786000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58786000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 26 4>;
- clocks = <&peri_clk 10>;
- clock-frequency = <400000>;
- };
-};
+ i2c0: i2c@58780000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58780000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ clocks = <&peri_clk 4>;
+ clock-frequency = <100000>;
+ };
-&refclk {
- clock-frequency = <25000000>;
-};
+ i2c1: i2c@58781000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58781000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 42 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clocks = <&peri_clk 5>;
+ clock-frequency = <100000>;
+ };
-&mio_clk {
- compatible = "socionext,uniphier-pxs2-sd-clock";
-};
+ i2c2: i2c@58782000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58782000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 43 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clocks = <&peri_clk 6>;
+ clock-frequency = <100000>;
+ };
-&mio_rst {
- compatible = "socionext,uniphier-pxs2-sd-reset";
-};
+ i2c3: i2c@58783000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58783000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 44 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clocks = <&peri_clk 7>;
+ clock-frequency = <100000>;
+ };
-&peri_clk {
- compatible = "socionext,uniphier-pxs2-peri-clock";
-};
+ /* chip-internal connection for DMD */
+ i2c4: i2c@58784000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58784000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 45 4>;
+ clocks = <&peri_clk 8>;
+ clock-frequency = <400000>;
+ };
-&peri_rst {
- compatible = "socionext,uniphier-pxs2-peri-reset";
-};
+ /* chip-internal connection for STM */
+ i2c5: i2c@58785000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58785000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 25 4>;
+ clocks = <&peri_clk 9>;
+ clock-frequency = <400000>;
+ };
-&pinctrl {
- compatible = "socionext,uniphier-pxs2-pinctrl";
-};
+ /* chip-internal connection for HDMI */
+ i2c6: i2c@58786000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58786000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 26 4>;
+ clocks = <&peri_clk 10>;
+ clock-frequency = <400000>;
+ };
-&sys_clk {
- compatible = "socionext,uniphier-pxs2-clock";
-};
+ system_bus: system-bus@58c00000 {
+ compatible = "socionext,uniphier-system-bus";
+ status = "disabled";
+ reg = <0x58c00000 0x400>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_system_bus>;
+ };
+
+ smpctrl@59800000 {
+ compatible = "socionext,uniphier-smpctrl";
+ reg = <0x59801000 0x400>;
+ };
+
+ sdctrl@59810000 {
+ compatible = "socionext,uniphier-pxs2-sdctrl",
+ "simple-mfd", "syscon";
+ reg = <0x59810000 0x800>;
+
+ sd_clk: clock {
+ compatible = "socionext,uniphier-pxs2-sd-clock";
+ #clock-cells = <1>;
+ };
+
+ sd_rst: reset {
+ compatible = "socionext,uniphier-pxs2-sd-reset";
+ #reset-cells = <1>;
+ };
+ };
-&sys_rst {
- compatible = "socionext,uniphier-pxs2-reset";
+ perictrl@59820000 {
+ compatible = "socionext,uniphier-pxs2-perictrl",
+ "simple-mfd", "syscon";
+ reg = <0x59820000 0x200>;
+
+ peri_clk: clock {
+ compatible = "socionext,uniphier-pxs2-peri-clock";
+ #clock-cells = <1>;
+ };
+
+ peri_rst: reset {
+ compatible = "socionext,uniphier-pxs2-peri-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ soc-glue@5f800000 {
+ compatible = "socionext,uniphier-pxs2-soc-glue",
+ "simple-mfd", "syscon";
+ reg = <0x5f800000 0x2000>;
+
+ pinctrl: pinctrl {
+ compatible = "socionext,uniphier-pxs2-pinctrl";
+ };
+ };
+
+ timer@60000200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0x60000200 0x20>;
+ interrupts = <1 11 0xf04>;
+ clocks = <&arm_timer_clk>;
+ };
+
+ timer@60000600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x60000600 0x20>;
+ interrupts = <1 13 0xf04>;
+ clocks = <&arm_timer_clk>;
+ };
+
+ intc: interrupt-controller@60001000 {
+ compatible = "arm,cortex-a9-gic";
+ reg = <0x60001000 0x1000>,
+ <0x60000100 0x100>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ };
+
+ sysctrl@61840000 {
+ compatible = "socionext,uniphier-pxs2-sysctrl",
+ "simple-mfd", "syscon";
+ reg = <0x61840000 0x10000>;
+
+ sys_clk: clock {
+ compatible = "socionext,uniphier-pxs2-clock";
+ #clock-cells = <1>;
+ };
+
+ sys_rst: reset {
+ compatible = "socionext,uniphier-pxs2-reset";
+ #reset-cells = <1>;
+ };
+ };
+ };
};
+
+/include/ "uniphier-pinctrl.dtsi"
diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi
index d8cf0e7e11ea..b2c980ead7f0 100644
--- a/arch/arm/boot/dts/uniphier-sld8.dtsi
+++ b/arch/arm/boot/dts/uniphier-sld8.dtsi
@@ -43,7 +43,7 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-/include/ "uniphier-common32.dtsi"
+/include/ "skeleton.dtsi"
/ {
compatible = "socionext,uniphier-sld8";
@@ -61,146 +61,267 @@
};
};
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
clocks {
+ refclk: ref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
arm_timer_clk: arm_timer_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
};
-};
-
-&soc {
- l2: l2-cache@500c0000 {
- compatible = "socionext,uniphier-system-cache";
- reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
- interrupts = <0 174 4>, <0 175 4>;
- cache-unified;
- cache-size = <(256 * 1024)>;
- cache-sets = <256>;
- cache-line-size = <128>;
- cache-level = <2>;
- };
- i2c0: i2c@58400000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58400000 0x40>;
+ soc {
+ compatible = "simple-bus";
#address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 41 1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0>;
- clocks = <&peri_clk 4>;
- clock-frequency = <100000>;
- };
+ #size-cells = <1>;
+ ranges;
+ interrupt-parent = <&intc>;
- i2c1: i2c@58480000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58480000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 42 1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- clocks = <&peri_clk 5>;
- clock-frequency = <100000>;
- };
+ l2: l2-cache@500c0000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
+ <0x506c0000 0x400>;
+ interrupts = <0 174 4>, <0 175 4>;
+ cache-unified;
+ cache-size = <(256 * 1024)>;
+ cache-sets = <256>;
+ cache-line-size = <128>;
+ cache-level = <2>;
+ };
- /* chip-internal connection for DMD */
- i2c2: i2c@58500000 {
- compatible = "socionext,uniphier-i2c";
- reg = <0x58500000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 43 1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- clocks = <&peri_clk 6>;
- clock-frequency = <400000>;
- };
+ serial0: serial@54006800 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006800 0x40>;
+ interrupts = <0 33 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
+ clocks = <&peri_clk 0>;
+ };
- i2c3: i2c@58580000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58580000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 44 1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- clocks = <&peri_clk 7>;
- clock-frequency = <100000>;
- };
+ serial1: serial@54006900 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006900 0x40>;
+ interrupts = <0 35 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ clocks = <&peri_clk 1>;
+ };
- usb0: usb@5a800100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a800100 0x100>;
- interrupts = <0 80 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0>;
- clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
- resets = <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>, <&sys_rst 8>;
- };
+ serial2: serial@54006a00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006a00 0x40>;
+ interrupts = <0 37 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ clocks = <&peri_clk 2>;
+ };
- usb1: usb@5a810100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a810100 0x100>;
- interrupts = <0 81 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1>;
- clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
- resets = <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>, <&sys_rst 8>;
- };
+ serial3: serial@54006b00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006b00 0x40>;
+ interrupts = <0 29 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ clocks = <&peri_clk 3>;
+ };
- usb2: usb@5a820100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a820100 0x100>;
- interrupts = <0 82 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb2>;
- clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
- resets = <&mio_rst 7>, <&mio_rst 10>, <&mio_rst 14>, <&sys_rst 8>;
- };
-};
+ i2c0: i2c@58400000 {
+ compatible = "socionext,uniphier-i2c";
+ status = "disabled";
+ reg = <0x58400000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ clocks = <&peri_clk 4>;
+ clock-frequency = <100000>;
+ };
-&refclk {
- clock-frequency = <25000000>;
-};
+ i2c1: i2c@58480000 {
+ compatible = "socionext,uniphier-i2c";
+ status = "disabled";
+ reg = <0x58480000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 42 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clocks = <&peri_clk 5>;
+ clock-frequency = <100000>;
+ };
-&serial3 {
- interrupts = <0 29 4>;
-};
+ /* chip-internal connection for DMD */
+ i2c2: i2c@58500000 {
+ compatible = "socionext,uniphier-i2c";
+ reg = <0x58500000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 43 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clocks = <&peri_clk 6>;
+ clock-frequency = <400000>;
+ };
-&mio_clk {
- compatible = "socionext,uniphier-sld8-mio-clock";
-};
+ i2c3: i2c@58580000 {
+ compatible = "socionext,uniphier-i2c";
+ status = "disabled";
+ reg = <0x58580000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 44 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clocks = <&peri_clk 7>;
+ clock-frequency = <100000>;
+ };
-&mio_rst {
- compatible = "socionext,uniphier-sld8-mio-reset";
- resets = <&sys_rst 7>;
-};
+ system_bus: system-bus@58c00000 {
+ compatible = "socionext,uniphier-system-bus";
+ status = "disabled";
+ reg = <0x58c00000 0x400>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_system_bus>;
+ };
-&peri_clk {
- compatible = "socionext,uniphier-sld8-peri-clock";
-};
+ smpctrl@59800000 {
+ compatible = "socionext,uniphier-smpctrl";
+ reg = <0x59801000 0x400>;
+ };
-&peri_rst {
- compatible = "socionext,uniphier-sld8-peri-reset";
-};
+ mioctrl@59810000 {
+ compatible = "socionext,uniphier-sld8-mioctrl",
+ "simple-mfd", "syscon";
+ reg = <0x59810000 0x800>;
-&pinctrl {
- compatible = "socionext,uniphier-sld8-pinctrl";
-};
+ mio_clk: clock {
+ compatible = "socionext,uniphier-sld8-mio-clock";
+ #clock-cells = <1>;
+ };
-&sys_clk {
- compatible = "socionext,uniphier-sld8-clock";
-};
+ mio_rst: reset {
+ compatible = "socionext,uniphier-sld8-mio-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ perictrl@59820000 {
+ compatible = "socionext,uniphier-sld8-perictrl",
+ "simple-mfd", "syscon";
+ reg = <0x59820000 0x200>;
+
+ peri_clk: clock {
+ compatible = "socionext,uniphier-sld8-peri-clock";
+ #clock-cells = <1>;
+ };
+
+ peri_rst: reset {
+ compatible = "socionext,uniphier-sld8-peri-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ usb0: usb@5a800100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a800100 0x100>;
+ interrupts = <0 80 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>;
+ clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
+ <&mio_rst 12>;
+ };
+
+ usb1: usb@5a810100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a810100 0x100>;
+ interrupts = <0 81 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>;
+ clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
+ <&mio_rst 13>;
+ };
+
+ usb2: usb@5a820100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a820100 0x100>;
+ interrupts = <0 82 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb2>;
+ clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
+ <&mio_rst 14>;
+ };
-&sys_rst {
- compatible = "socionext,uniphier-sld8-reset";
+ soc-glue@5f800000 {
+ compatible = "socionext,uniphier-sld8-soc-glue",
+ "simple-mfd", "syscon";
+ reg = <0x5f800000 0x2000>;
+
+ pinctrl: pinctrl {
+ compatible = "socionext,uniphier-sld8-pinctrl";
+ };
+ };
+
+ timer@60000200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0x60000200 0x20>;
+ interrupts = <1 11 0x104>;
+ clocks = <&arm_timer_clk>;
+ };
+
+ timer@60000600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x60000600 0x20>;
+ interrupts = <1 13 0x104>;
+ clocks = <&arm_timer_clk>;
+ };
+
+ intc: interrupt-controller@60001000 {
+ compatible = "arm,cortex-a9-gic";
+ reg = <0x60001000 0x1000>,
+ <0x60000100 0x100>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ };
+
+ sysctrl@61840000 {
+ compatible = "socionext,uniphier-sld8-sysctrl",
+ "simple-mfd", "syscon";
+ reg = <0x61840000 0x10000>;
+
+ sys_clk: clock {
+ compatible = "socionext,uniphier-sld8-clock";
+ #clock-cells = <1>;
+ };
+
+ sys_rst: reset {
+ compatible = "socionext,uniphier-sld8-reset";
+ #reset-cells = <1>;
+ };
+ };
+ };
};
+
+/include/ "uniphier-pinctrl.dtsi"
--
cgit
From 29ad7f49628eee53cda9319eeabbffaf39598a75 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Fri, 4 Nov 2016 09:53:53 +0900
Subject: ARM: dts: uniphier: remove redundant serial fifo-size properties
These are the default of the optional property. No need to describe
them explicitly.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
arch/arm/boot/dts/uniphier-sld3.dtsi | 3 ---
1 file changed, 3 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/uniphier-sld3.dtsi b/arch/arm/boot/dts/uniphier-sld3.dtsi
index 35c18197d94f..5f57a96e4e13 100644
--- a/arch/arm/boot/dts/uniphier-sld3.dtsi
+++ b/arch/arm/boot/dts/uniphier-sld3.dtsi
@@ -135,7 +135,6 @@
reg = <0x54006800 0x40>;
interrupts = <0 33 4>;
clocks = <&sys_clk 0>;
- fifo-size = <64>;
};
serial1: serial@54006900 {
@@ -144,7 +143,6 @@
reg = <0x54006900 0x40>;
interrupts = <0 35 4>;
clocks = <&sys_clk 0>;
- fifo-size = <64>;
};
serial2: serial@54006a00 {
@@ -153,7 +151,6 @@
reg = <0x54006a00 0x40>;
interrupts = <0 37 4>;
clocks = <&sys_clk 0>;
- fifo-size = <64>;
};
i2c0: i2c@58400000 {
--
cgit
From 64f4896592b5ac830bc0c7daf91ea21100eb54be Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 11 Oct 2016 15:26:06 +0900
Subject: ARM: dts: uniphier: add clocks/resets to EHCI nodes of sLD3 SoC
Now, the clock/reset controller driver is available for this SoC.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
arch/arm/boot/dts/uniphier-sld3.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/uniphier-sld3.dtsi b/arch/arm/boot/dts/uniphier-sld3.dtsi
index 5f57a96e4e13..a75189f7d8fe 100644
--- a/arch/arm/boot/dts/uniphier-sld3.dtsi
+++ b/arch/arm/boot/dts/uniphier-sld3.dtsi
@@ -242,6 +242,9 @@
status = "disabled";
reg = <0x5a800100 0x100>;
interrupts = <0 80 4>;
+ clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
+ <&mio_rst 12>;
};
usb1: usb@5a810100 {
@@ -249,6 +252,9 @@
status = "disabled";
reg = <0x5a810100 0x100>;
interrupts = <0 81 4>;
+ clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
+ <&mio_rst 13>;
};
usb2: usb@5a820100 {
@@ -256,6 +262,9 @@
status = "disabled";
reg = <0x5a820100 0x100>;
interrupts = <0 82 4>;
+ clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
+ <&mio_rst 14>;
};
usb3: usb@5a830100 {
@@ -263,6 +272,9 @@
status = "disabled";
reg = <0x5a830100 0x100>;
interrupts = <0 83 4>;
+ clocks = <&mio_clk 7>, <&mio_clk 11>, <&mio_clk 15>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 11>,
+ <&mio_rst 15>;
};
sysctrl@f1840000 {
--
cgit
From 13b4a6190b25c7bf69239bbc212d256656ada7b9 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Sat, 5 Nov 2016 16:28:26 +0900
Subject: ARM: dts: uniphier: make compatible of syscon nodes SoC-specific
These hardware blocks are SoC-specific, so their compatible strings
should be SoC-specific as well. This change has no impact on the
actual behavior since it is controlled by the generic "simple-mfd",
"syscon" compatible strings.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
arch/arm/boot/dts/uniphier-sld3.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/uniphier-sld3.dtsi b/arch/arm/boot/dts/uniphier-sld3.dtsi
index a75189f7d8fe..9fad6bd2db8a 100644
--- a/arch/arm/boot/dts/uniphier-sld3.dtsi
+++ b/arch/arm/boot/dts/uniphier-sld3.dtsi
@@ -222,7 +222,7 @@
};
mioctrl@59810000 {
- compatible = "socionext,uniphier-mioctrl",
+ compatible = "socionext,uniphier-sld3-mioctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
@@ -278,7 +278,7 @@
};
sysctrl@f1840000 {
- compatible = "socionext,uniphier-sysctrl",
+ compatible = "socionext,uniphier-sld3-sysctrl",
"simple-mfd", "syscon";
reg = <0xf1840000 0x10000>;
--
cgit
From 05a3589f46f913fbe91704f12fdca46a0eb0a27b Mon Sep 17 00:00:00 2001
From: Pankaj Dubey <pankaj.dubey@samsung.com>
Date: Fri, 4 Nov 2016 09:09:22 +0530
Subject: ARM: dts: exynos: Add SCU device node to exynos4.dtsi
Exynos4 like other Cortex-A9 SoC's has a Snoop Control Unit(SCU)
and its SFR are used during SMP boot and S2R. Add SCU node to the device tree.
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/boot/dts/exynos4.dtsi | 5 +++++
1 file changed, 5 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 5f034eb5a5e2..6865ca99932e 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -78,6 +78,11 @@
reg = <0x10000000 0x100>;
};
+ scu: snoop-control-unit@10500000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0x10500000 0x2000>;
+ };
+
memory-controller@12570000 {
compatible = "samsung,exynos4210-srom";
reg = <0x12570000 0x14>;
--
cgit
From 04a6e5e83a37cdcc45bf53970b03f6a8e58e3462 Mon Sep 17 00:00:00 2001
From: Paweł Jarosz <paweljarosz3691@gmail.com>
Date: Fri, 4 Nov 2016 19:07:31 +0100
Subject: ARM: dts: rockchip: Set sdmmc frequency at boot time for rk3066a
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Currently driver leaves sdmmc frequency at its default.
So lets set this to 50MHz.
This gives us performance boost in mmc transfers.
Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/boot/dts/rk3066a.dtsi | 2 ++
1 file changed, 2 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index f3a51099f5e0..fc8dcc72b16f 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -636,6 +636,8 @@
};
&mmc0 {
+ clock-frequency = <50000000>;
+ max-frequency = <50000000>;
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
};
--
cgit
From 67cb5d52ea2c3ae35d637ab79a46cd452d1c7d41 Mon Sep 17 00:00:00 2001
From: Peter Chen <peter.chen@nxp.com>
Date: Mon, 31 Oct 2016 10:58:28 +0800
Subject: ARM: dts: imx6sx-sdb: update TX D_CAL for USBPHY
We need to change trimming value (as a percentage) of the 17.78mA TX
reference current for better signal quality. With this change, we
can pass the eye-diagram test on this board.
Signed-off-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/imx6sx-sdb.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi
index 7327bcde843f..da815527a7f8 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dtsi
+++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi
@@ -290,6 +290,14 @@
status = "okay";
};
+&usbphy1 {
+ fsl,tx-d-cal = <106>;
+};
+
+&usbphy2 {
+ fsl,tx-d-cal = <106>;
+};
+
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
--
cgit
From 901725b7902eb776df0b4d83e5210e2bcd1bd9ce Mon Sep 17 00:00:00 2001
From: Peter Chen <peter.chen@nxp.com>
Date: Mon, 31 Oct 2016 10:58:29 +0800
Subject: ARM: dts: imx6ul-14x14-evk: update TX D_CAL for USBPHY
We need to change trimming value (as a percentage) of the 17.78mA TX
reference current for better signal quality. With this change, we
can pass the eye-diagram test on this board.
Signed-off-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/imx6ul-14x14-evk.dts | 8 ++++++++
1 file changed, 8 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dts b/arch/arm/boot/dts/imx6ul-14x14-evk.dts
index c5cf9424ae35..00f98e5bfcaf 100644
--- a/arch/arm/boot/dts/imx6ul-14x14-evk.dts
+++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dts
@@ -235,6 +235,14 @@
status = "okay";
};
+&usbphy1 {
+ fsl,tx-d-cal = <106>;
+};
+
+&usbphy2 {
+ fsl,tx-d-cal = <106>;
+};
+
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
--
cgit
From c1700644dd38c01015d025d84cc88898216b954d Mon Sep 17 00:00:00 2001
From: Mirza Krak <mirza.krak@gmail.com>
Date: Mon, 7 Nov 2016 09:30:04 +0100
Subject: ARM: tegra: Add Tegra20 GMI support
Add a device node for the GMI controller found on Tegra20.
Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm/boot/dts/tegra20.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 2207c08e3fa3..e8807503f87c 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -376,6 +376,19 @@
status = "disabled";
};
+ gmi@70009000 {
+ compatible = "nvidia,tegra20-gmi";
+ reg = <0x70009000 0x1000>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0 0xd0000000 0xfffffff>;
+ clocks = <&tegra_car TEGRA20_CLK_NOR>;
+ clock-names = "gmi";
+ resets = <&tegra_car 42>;
+ reset-names = "gmi";
+ status = "disabled";
+ };
+
pwm: pwm@7000a000 {
compatible = "nvidia,tegra20-pwm";
reg = <0x7000a000 0x100>;
--
cgit
From 5e35c1f037ce9d4c89fb22c05c7192ae0e615f0e Mon Sep 17 00:00:00 2001
From: Mirza Krak <mirza.krak@gmail.com>
Date: Mon, 7 Nov 2016 09:30:03 +0100
Subject: ARM: tegra: Add Tegra30 GMI support
Add a device node for the GMI controller found on Tegra30.
Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm/boot/dts/tegra30.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 5030065cbdfe..bbb1c002e7f1 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -439,6 +439,19 @@
status = "disabled";
};
+ gmi@70009000 {
+ compatible = "nvidia,tegra30-gmi";
+ reg = <0x70009000 0x1000>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0 0x48000000 0x7ffffff>;
+ clocks = <&tegra_car TEGRA30_CLK_NOR>;
+ clock-names = "gmi";
+ resets = <&tegra_car 42>;
+ reset-names = "gmi";
+ status = "disabled";
+ };
+
pwm: pwm@7000a000 {
compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
reg = <0x7000a000 0x100>;
--
cgit
From 5d831dd5e2ee49847359bfe6ccc7d36d1ef054fc Mon Sep 17 00:00:00 2001
From: Paul Kocialkowski <contact@paulk.fr>
Date: Sun, 18 Sep 2016 16:13:11 +0200
Subject: ARM: tegra: nyan: Enable GPU node and related supply
This enables the GPU node for tegra124 nyan boards, which is required to
get graphics acceleration with nouveau on these devices.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Acked-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm/boot/dts/tegra124-nyan.dtsi | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi
index 271505e0715f..eabfa655a3cd 100644
--- a/arch/arm/boot/dts/tegra124-nyan.dtsi
+++ b/arch/arm/boot/dts/tegra124-nyan.dtsi
@@ -42,6 +42,12 @@
};
};
+ gpu@0,57000000 {
+ status = "okay";
+
+ vdd-supply = <&vdd_gpu>;
+ };
+
serial@70006000 {
/* Debug connector on the bottom of the board near SD card. */
status = "okay";
@@ -214,7 +220,7 @@
regulator-always-on;
};
- sd6 {
+ vdd_gpu: sd6 {
regulator-name = "+VDD_GPU_AP";
regulator-min-microvolt = <650000>;
regulator-max-microvolt = <1200000>;
--
cgit
From 8948e7468ab9cbf0beb88cfc806fda37948ab9ff Mon Sep 17 00:00:00 2001
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Date: Sun, 19 Jun 2016 03:00:01 +0200
Subject: ARM: tegra: apalis/colibri t30: Integrate audio
Integrate Freescale SGTL5000 analogue audio codec support.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
[treding@nvidia.com: remove leading 0 from unit-address]
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm/boot/dts/tegra30-apalis.dtsi | 49 ++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/tegra30-colibri.dtsi | 49 ++++++++++++++++++++++++++++++++++
2 files changed, 98 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi
index 192b95177aac..f6c7c3e958ac 100644
--- a/arch/arm/boot/dts/tegra30-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
@@ -48,6 +48,24 @@
pinctrl-0 = <&state_default>;
state_default: pinmux {
+ /* Analogue Audio (On-module) */
+ clk1_out_pw4 {
+ nvidia,pins = "clk1_out_pw4";
+ nvidia,function = "extperiph1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap3_fs_pp0 {
+ nvidia,pins = "dap3_fs_pp0",
+ "dap3_sclk_pp3",
+ "dap3_din_pp1",
+ "dap3_dout_pp2";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
/* Apalis BKL1_ON */
pv2 {
nvidia,pins = "pv2";
@@ -429,6 +447,15 @@
status = "okay";
clock-frequency = <100000>;
+ /* SGTL5000 audio codec */
+ sgtl5000: codec@a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ VDDA-supply = <&sys_3v3_reg>;
+ VDDIO-supply = <&sys_3v3_reg>;
+ clocks = <&tegra_car TEGRA30_CLK_EXTERN1>;
+ };
+
pmic: tps65911@2d {
compatible = "ti,tps65911";
reg = <0x2d>;
@@ -660,6 +687,12 @@
nvidia,sys-clock-req-active-high;
};
+ ahub@70080000 {
+ i2s@70080500 {
+ status = "okay";
+ };
+ };
+
/* eMMC */
sdhci@78000600 {
status = "okay";
@@ -733,4 +766,20 @@
regulator-always-on;
};
};
+
+ sound {
+ compatible = "toradex,tegra-audio-sgtl5000-apalis_t30",
+ "nvidia,tegra-audio-sgtl5000";
+ nvidia,model = "Toradex Apalis T30";
+ nvidia,audio-routing =
+ "Headphone Jack", "HP_OUT",
+ "LINE_IN", "Line In Jack",
+ "MIC_IN", "Mic Jack";
+ nvidia,i2s-controller = <&tegra_i2s2>;
+ nvidia,audio-codec = <&sgtl5000>;
+ clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
+ <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA30_CLK_EXTERN1>;
+ clock-names = "pll_a", "pll_a_out0", "mclk";
+ };
};
diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi
index a265534cd314..5360d638eedc 100644
--- a/arch/arm/boot/dts/tegra30-colibri.dtsi
+++ b/arch/arm/boot/dts/tegra30-colibri.dtsi
@@ -29,6 +29,24 @@
pinctrl-0 = <&state_default>;
state_default: pinmux {
+ /* Analogue Audio (On-module) */
+ clk1_out_pw4 {
+ nvidia,pins = "clk1_out_pw4";
+ nvidia,function = "extperiph1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap3_fs_pp0 {
+ nvidia,pins = "dap3_fs_pp0",
+ "dap3_sclk_pp3",
+ "dap3_din_pp1",
+ "dap3_dout_pp2";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
/* Colibri BL_ON */
pv2 {
nvidia,pins = "pv2";
@@ -207,6 +225,15 @@
status = "okay";
clock-frequency = <100000>;
+ /* SGTL5000 audio codec */
+ sgtl5000: codec@a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ VDDA-supply = <&sys_3v3_reg>;
+ VDDIO-supply = <&sys_3v3_reg>;
+ clocks = <&tegra_car TEGRA30_CLK_EXTERN1>;
+ };
+
pmic: tps65911@2d {
compatible = "ti,tps65911";
reg = <0x2d>;
@@ -396,6 +423,12 @@
nvidia,sys-clock-req-active-high;
};
+ ahub@70080000 {
+ i2s@70080500 {
+ status = "okay";
+ };
+ };
+
/* eMMC */
sdhci@78000600 {
status = "okay";
@@ -471,4 +504,20 @@
regulator-always-on;
};
};
+
+ sound {
+ compatible = "toradex,tegra-audio-sgtl5000-colibri_t30",
+ "nvidia,tegra-audio-sgtl5000";
+ nvidia,model = "Toradex Colibri T30";
+ nvidia,audio-routing =
+ "Headphone Jack", "HP_OUT",
+ "LINE_IN", "Line In Jack",
+ "MIC_IN", "Mic Jack";
+ nvidia,i2s-controller = <&tegra_i2s2>;
+ nvidia,audio-codec = <&sgtl5000>;
+ clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
+ <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA30_CLK_EXTERN1>;
+ clock-names = "pll_a", "pll_a_out0", "mclk";
+ };
};
--
cgit
From be76fd3197df608e1b010bf5ab90377205f54344 Mon Sep 17 00:00:00 2001
From: Tony Lindgren <tony@atomide.com>
Date: Mon, 7 Nov 2016 08:27:49 -0700
Subject: ARM: dts: Add #pinctrl-cells for pinctrl-single instances
Drivers using pinctrl-single,pins have #pinctrl-cells = <1>, while
pinctrl-single,bits need #pinctrl-cells = <2>.
Note that this patch can be optionally applied separately from the
driver changes as the driver supports also the legacy binding without
#pinctrl-cells.
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/am33xx.dtsi | 2 ++
arch/arm/boot/dts/am3517.dtsi | 1 +
arch/arm/boot/dts/am4372.dtsi | 1 +
arch/arm/boot/dts/da850.dtsi | 1 +
arch/arm/boot/dts/dm814x.dtsi | 1 +
arch/arm/boot/dts/dm816x.dtsi | 2 ++
arch/arm/boot/dts/dra7.dtsi | 1 +
arch/arm/boot/dts/hi3620.dtsi | 2 ++
arch/arm/boot/dts/keystone-k2g.dtsi | 1 +
arch/arm/boot/dts/keystone-k2l.dtsi | 1 +
arch/arm/boot/dts/omap2420.dtsi | 2 ++
arch/arm/boot/dts/omap2430.dtsi | 2 ++
arch/arm/boot/dts/omap3.dtsi | 2 ++
arch/arm/boot/dts/omap34xx.dtsi | 1 +
arch/arm/boot/dts/omap36xx.dtsi | 1 +
arch/arm/boot/dts/omap4.dtsi | 2 ++
arch/arm/boot/dts/omap5.dtsi | 2 ++
arch/arm/boot/dts/pxa3xx.dtsi | 1 +
18 files changed, 26 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 194d884c9de1..3a3fde1f84c7 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -130,6 +130,7 @@
reg = <0x210000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
+ #pinctrl-cells = <1>;
ranges = <0 0x210000 0x2000>;
am33xx_pinmux: pinmux@800 {
@@ -137,6 +138,7 @@
reg = <0x800 0x238>;
#address-cells = <1>;
#size-cells = <0>;
+ #pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x7f>;
};
diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
index 0db19d39d24c..9fe545dbfa89 100644
--- a/arch/arm/boot/dts/am3517.dtsi
+++ b/arch/arm/boot/dts/am3517.dtsi
@@ -66,6 +66,7 @@
reg = <0x480025d8 0x24>;
#address-cells = <1>;
#size-cells = <0>;
+ #pinctrl-cells = <1>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index a275fa956813..7b5ca1bbc6a9 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -189,6 +189,7 @@
reg = <0x800 0x31c>;
#address-cells = <1>;
#size-cells = <0>;
+ #pinctrl-cells = <1>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <32>;
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index f79e1b91c680..a25a55387db3 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -36,6 +36,7 @@
reg = <0x14120 0x50>;
#address-cells = <1>;
#size-cells = <0>;
+ #pinctrl-cells = <2>;
pinctrl-single,bit-per-mux;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xf>;
diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi
index ff90a6ce6bdc..1facc5f12cef 100644
--- a/arch/arm/boot/dts/dm814x.dtsi
+++ b/arch/arm/boot/dts/dm814x.dtsi
@@ -373,6 +373,7 @@
reg = <0x800 0x438>;
#address-cells = <1>;
#size-cells = <0>;
+ #pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x307ff>;
};
diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi
index f1e0f771ff29..61dd2f6b02bc 100644
--- a/arch/arm/boot/dts/dm816x.dtsi
+++ b/arch/arm/boot/dts/dm816x.dtsi
@@ -83,6 +83,7 @@
reg = <0x48140000 0x21000>;
#address-cells = <1>;
#size-cells = <1>;
+ #pinctrl-cells = <1>;
ranges = <0 0x48140000 0x21000>;
dm816x_pinmux: pinmux@800 {
@@ -90,6 +91,7 @@
reg = <0x800 0x50a>;
#address-cells = <1>;
#size-cells = <0>;
+ #pinctrl-cells = <1>;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0xf>;
};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index d4fcd68f6349..addb7530cfbe 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -171,6 +171,7 @@
reg = <0x1400 0x0468>;
#address-cells = <1>;
#size-cells = <0>;
+ #pinctrl-cells = <1>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <32>;
diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi
index c85d07e6db61..45eea81678c0 100644
--- a/arch/arm/boot/dts/hi3620.dtsi
+++ b/arch/arm/boot/dts/hi3620.dtsi
@@ -537,6 +537,7 @@
reg = <0x803000 0x188>;
#address-cells = <1>;
#size-cells = <1>;
+ #pinctrl-cells = <1>;
#gpio-range-cells = <3>;
ranges;
@@ -558,6 +559,7 @@
reg = <0x803800 0x2dc>;
#address-cells = <1>;
#size-cells = <1>;
+ #pinctrl-cells = <1>;
ranges;
pinctrl-single,register-width = <32>;
diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi
index 2919c5190653..63c7cf0c6b6d 100644
--- a/arch/arm/boot/dts/keystone-k2g.dtsi
+++ b/arch/arm/boot/dts/keystone-k2g.dtsi
@@ -72,6 +72,7 @@
soc {
#address-cells = <1>;
#size-cells = <1>;
+ #pinctrl-cells = <1>;
compatible = "ti,keystone","simple-bus";
ranges = <0x0 0x0 0x0 0xc0000000>;
dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>;
diff --git a/arch/arm/boot/dts/keystone-k2l.dtsi b/arch/arm/boot/dts/keystone-k2l.dtsi
index 2ee3d0ac2816..0c5e74e79ba2 100644
--- a/arch/arm/boot/dts/keystone-k2l.dtsi
+++ b/arch/arm/boot/dts/keystone-k2l.dtsi
@@ -59,6 +59,7 @@
reg = <0x02620690 0xc>;
#address-cells = <1>;
#size-cells = <0>;
+ #pinctrl-cells = <2>;
pinctrl-single,bit-per-mux;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x1>;
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index fb712b9aa874..aba542d63d6d 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -38,6 +38,7 @@
reg = <0x0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
+ #pinctrl-cells = <1>;
ranges = <0 0x0 0x1000>;
omap2420_pmx: pinmux@30 {
@@ -46,6 +47,7 @@
reg = <0x30 0x0113>;
#address-cells = <1>;
#size-cells = <0>;
+ #pinctrl-cells = <1>;
pinctrl-single,register-width = <8>;
pinctrl-single,function-mask = <0x3f>;
};
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index 455aaea407dd..84635eeb99cd 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -38,6 +38,7 @@
reg = <0x2000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
+ #pinctrl-cells = <1>;
ranges = <0 0x2000 0x1000>;
omap2430_pmx: pinmux@30 {
@@ -46,6 +47,7 @@
reg = <0x30 0x0154>;
#address-cells = <1>;
#size-cells = <0>;
+ #pinctrl-cells = <1>;
pinctrl-single,register-width = <8>;
pinctrl-single,function-mask = <0x3f>;
};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 353d818ce5a6..ecf5eb584c75 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -106,6 +106,7 @@
reg = <0x30 0x238>;
#address-cells = <1>;
#size-cells = <0>;
+ #pinctrl-cells = <1>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
@@ -145,6 +146,7 @@
reg = <0xa00 0x5c>;
#address-cells = <1>;
#size-cells = <0>;
+ #pinctrl-cells = <1>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
index e41c52d3b113..834fdf13601f 100644
--- a/arch/arm/boot/dts/omap34xx.dtsi
+++ b/arch/arm/boot/dts/omap34xx.dtsi
@@ -34,6 +34,7 @@
reg = <0x480025d8 0x24>;
#address-cells = <1>;
#size-cells = <0>;
+ #pinctrl-cells = <1>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index 718fa88407cd..d1a3e56b50ce 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -66,6 +66,7 @@
reg = <0x480025a0 0x5c>;
#address-cells = <1>;
#size-cells = <0>;
+ #pinctrl-cells = <1>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 0ced079b7ae3..8087456b5fbe 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -184,6 +184,7 @@
reg = <0x40 0x0196>;
#address-cells = <1>;
#size-cells = <0>;
+ #pinctrl-cells = <1>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
@@ -256,6 +257,7 @@
reg = <0x1e040 0x0038>;
#address-cells = <1>;
#size-cells = <0>;
+ #pinctrl-cells = <1>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 25262118ec3d..968c67a49dbd 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -171,6 +171,7 @@
reg = <0x40 0x01b6>;
#address-cells = <1>;
#size-cells = <0>;
+ #pinctrl-cells = <1>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
@@ -270,6 +271,7 @@
reg = <0xc840 0x003c>;
#address-cells = <1>;
#size-cells = <0>;
+ #pinctrl-cells = <1>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi
index 9d6f3aacedb7..7a0cc4ea819a 100644
--- a/arch/arm/boot/dts/pxa3xx.dtsi
+++ b/arch/arm/boot/dts/pxa3xx.dtsi
@@ -138,6 +138,7 @@
reg = <0x40e10000 0xffff>;
#address-cells = <1>;
#size-cells = <0>;
+ #pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x7>;
};
--
cgit
From ad0de58bfec943cca10f808d5ddbde5e9fc24d44 Mon Sep 17 00:00:00 2001
From: Chris Packham <chris.packham@alliedtelesis.co.nz>
Date: Wed, 26 Oct 2016 12:52:42 +1300
Subject: ARM: dts: mvebu: Update comment for main PLL frequency
The actual frequency was updated in commit ae142bd99765 ("ARM: mvebu:
Fix the main PLL frequency on Armada 375, 38x and 39x SoCs") but the
comment was not updated. Update it now.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm/boot/dts/armada-375.dtsi | 2 +-
arch/arm/boot/dts/armada-38x.dtsi | 2 +-
arch/arm/boot/dts/armada-39x.dtsi | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi
index cc952cf8ec30..45fa92f9cf5c 100644
--- a/arch/arm/boot/dts/armada-375.dtsi
+++ b/arch/arm/boot/dts/armada-375.dtsi
@@ -65,7 +65,7 @@
};
clocks {
- /* 2 GHz fixed main PLL */
+ /* 1 GHz fixed main PLL */
mainpll: mainpll {
compatible = "fixed-clock";
#clock-cells = <0>;
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index 2d7668848c5a..7450e9fea45d 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -661,7 +661,7 @@
};
clocks {
- /* 2 GHz fixed main PLL */
+ /* 1 GHz fixed main PLL */
mainpll: mainpll {
compatible = "fixed-clock";
#clock-cells = <0>;
diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi
index 34cba87f9200..de171baffcf6 100644
--- a/arch/arm/boot/dts/armada-39x.dtsi
+++ b/arch/arm/boot/dts/armada-39x.dtsi
@@ -573,7 +573,7 @@
};
clocks {
- /* 2 GHz fixed main PLL */
+ /* 1 GHz fixed main PLL */
mainpll: mainpll {
compatible = "fixed-clock";
#clock-cells = <0>;
--
cgit
From da32081ffa0feec3deed6bd526a7f3c1d44342cb Mon Sep 17 00:00:00 2001
From: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Date: Tue, 20 Sep 2016 22:58:32 +0200
Subject: ARM: dts: at91: sama5d4: use proper sckc compatible
Now that there is support for the sama5d4 slow clock controller, use its
driver.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/boot/dts/sama5d4.dtsi | 27 ++++-----------------------
1 file changed, 4 insertions(+), 23 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
index f7bfc6229285..4f60c1b7b137 100644
--- a/arch/arm/boot/dts/sama5d4.dtsi
+++ b/arch/arm/boot/dts/sama5d4.dtsi
@@ -1314,30 +1314,11 @@
status = "disabled";
};
- sckc@fc068650 {
- compatible = "atmel,at91sam9x5-sckc";
+ clk32k: sckc@fc068650 {
+ compatible = "atmel,sama5d4-sckc";
reg = <0xfc068650 0x4>;
-
- slow_rc_osc: slow_rc_osc {
- compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-accuracy = <250000000>;
- atmel,startup-time-usec = <75>;
- };
-
- slow_osc: slow_osc {
- compatible = "atmel,at91sam9x5-clk-slow-osc";
- #clock-cells = <0>;
- clocks = <&slow_xtal>;
- atmel,startup-time-usec = <1200000>;
- };
-
- clk32k: slowck {
- compatible = "atmel,at91sam9x5-clk-slow";
- #clock-cells = <0>;
- clocks = <&slow_rc_osc &slow_osc>;
- };
+ #clock-cells = <0>;
+ clocks = <&slow_xtal>;
};
rtc@fc0686b0 {
--
cgit
From 58c016e09cd2bc1bddc76b9d33961e4dfa79b6be Mon Sep 17 00:00:00 2001
From: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Date: Tue, 20 Sep 2016 22:58:33 +0200
Subject: ARM: dts: at91: sama5d2: use correct sckc compatible
the sama5d2 sckc is actually sama5d4 compatible
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/boot/dts/sama5d2.dtsi | 26 ++++----------------------
1 file changed, 4 insertions(+), 22 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
index a0dd649db455..fb8b496267ed 100644
--- a/arch/arm/boot/dts/sama5d2.dtsi
+++ b/arch/arm/boot/dts/sama5d2.dtsi
@@ -1089,30 +1089,12 @@
status = "disabled";
};
- sckc@f8048050 {
- compatible = "atmel,at91sam9x5-sckc";
+ clk32k: sckc@f8048050 {
+ compatible = "atmel,sama5d4-sckc";
reg = <0xf8048050 0x4>;
- slow_rc_osc: slow_rc_osc {
- compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-accuracy = <250000000>;
- atmel,startup-time-usec = <75>;
- };
-
- slow_osc: slow_osc {
- compatible = "atmel,at91sam9x5-clk-slow-osc";
- #clock-cells = <0>;
- clocks = <&slow_xtal>;
- atmel,startup-time-usec = <1200000>;
- };
-
- clk32k: slowck {
- compatible = "atmel,at91sam9x5-clk-slow";
- #clock-cells = <0>;
- clocks = <&slow_rc_osc &slow_osc>;
- };
+ clocks = <&slow_xtal>;
+ #clock-cells = <0>;
};
rtc@f80480b0 {
--
cgit
From d44432dfc4b2d8c23bbfef518725315a5ce34ee2 Mon Sep 17 00:00:00 2001
From: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Date: Thu, 22 Sep 2016 00:09:36 +0200
Subject: ARM: dts: at91: sama5d2: Add secumod node
The sama5d2 has a security module, add its node.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/boot/dts/sama5d2.dtsi | 5 +++++
1 file changed, 5 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
index fb8b496267ed..2390b58c3528 100644
--- a/arch/arm/boot/dts/sama5d2.dtsi
+++ b/arch/arm/boot/dts/sama5d2.dtsi
@@ -1244,6 +1244,11 @@
clocks = <&pioA_clk>;
};
+ secumod@fc040000 {
+ compatible = "atmel,sama5d2-secumod", "syscon";
+ reg = <0xfc040000 0x100>;
+ };
+
tdes@fc044000 {
compatible = "atmel,at91sam9g46-tdes";
reg = <0xfc044000 0x100>;
--
cgit
From d4ce5f44d44091d26f484f7028ce94ff6851ab4c Mon Sep 17 00:00:00 2001
From: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Date: Thu, 22 Sep 2016 00:09:39 +0200
Subject: ARM: dts: at91: sama5d2: Add securam node
The sama5d2 has some static RAM that can be erased by the security module,
add its node
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/boot/dts/sama5d2.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
index 2390b58c3528..ceb9783ff7e1 100644
--- a/arch/arm/boot/dts/sama5d2.dtsi
+++ b/arch/arm/boot/dts/sama5d2.dtsi
@@ -735,6 +735,11 @@
atmel,clk-output-range = <0 83000000>;
};
+ securam_clk: securam_clk {
+ #clock-cells = <0>;
+ reg = <51>;
+ };
+
i2s0_clk: i2s0_clk {
#clock-cells = <0>;
reg = <54>;
@@ -1059,6 +1064,15 @@
status = "disabled";
};
+ securam: sram@f8044000 {
+ compatible = "atmel,sama5d2-securam", "mmio-sram";
+ reg = <0xf8044000 0x1420>;
+ clocks = <&securam_clk>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xf8044000 0x1420>;
+ };
+
rstc@f8048000 {
compatible = "atmel,sama5d3-rstc";
reg = <0xf8048000 0x10>;
--
cgit
From 5e8a724d143308f3195375951b0c8f01b2ca59fe Mon Sep 17 00:00:00 2001
From: Thierry Reding <treding@nvidia.com>
Date: Mon, 7 Nov 2016 14:46:59 +0100
Subject: ARM: tegra: apalis-tk1: Drop leading 0 from unit-address
According to the latest best practices, unit-addresses should be
represented without any leading zeroes.
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm/boot/dts/tegra124-apalis.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi
index e7a73db17613..0819721dda59 100644
--- a/arch/arm/boot/dts/tegra124-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis.dtsi
@@ -1595,7 +1595,7 @@
clock-frequency = <400000>;
/* SGTL5000 audio codec */
- sgtl5000: codec@0a {
+ sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
VDDA-supply = <®_3v3>;
--
cgit
From d1da66351749d82e4c82ef2251e95f6294847a85 Mon Sep 17 00:00:00 2001
From: Dinh Nguyen <dinguyen@kernel.org>
Date: Tue, 1 Nov 2016 09:57:06 -0500
Subject: ARM: dts: socfpga: add specific compatible strings for boards
Add a more specific board compatible entry for all of the SOCFPGA
Cyclone 5 based boards.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v3: Be a bit more specific with the c5 dk and sockit, use
"altr,socfpga-cyclone5-socdk" and "terasic,socfpga-cyclone5-sockit"
v2: remove extra space and add a comma between compatible entries
---
arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts | 2 +-
arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts | 2 +-
arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 2 +-
arch/arm/boot/dts/socfpga_cyclone5_sockit.dts | 2 +-
arch/arm/boot/dts/socfpga_cyclone5_sodia.dts | 2 +-
arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts | 2 +-
6 files changed, 6 insertions(+), 6 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts
index afea3645ada4..5ecd2ef405e3 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts
@@ -18,7 +18,7 @@
/ {
model = "Terasic DE-0(Atlas)";
- compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+ compatible = "terasic,de0-atlas", "altr,socfpga-cyclone5", "altr,socfpga";
chosen {
bootargs = "earlyprintk";
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts b/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts
index 424523b0d381..e5a98e5696ca 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts
@@ -19,7 +19,7 @@
/ {
model = "Aries/DENX MCV EVK";
- compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+ compatible = "denx,mcvevk", "altr,socfpga-cyclone5", "altr,socfpga";
aliases {
ethernet0 = &gmac0;
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
index 15e43f43f244..7a5f42dba12e 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
@@ -19,7 +19,7 @@
/ {
model = "Altera SOCFPGA Cyclone V SoC Development Kit";
- compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+ compatible = "altr,socfpga-cyclone5-socdk", "altr,socfpga-cyclone5", "altr,socfpga";
chosen {
bootargs = "earlyprintk";
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
index 02e22f554ef0..fcacaf7b2c83 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
@@ -19,7 +19,7 @@
/ {
model = "Terasic SoCkit";
- compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+ compatible = "terasic,socfpga-cyclone5-sockit", "altr,socfpga-cyclone5", "altr,socfpga";
chosen {
bootargs = "earlyprintk";
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
index 9aaf413b80de..5b7e3c27e6e9 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
@@ -21,7 +21,7 @@
/ {
model = "Altera SOCFPGA Cyclone V SoC Macnica Sodia board";
- compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+ compatible = "macnica,sodia", "altr,socfpga-cyclone5", "altr,socfpga";
chosen {
bootargs = "earlyprintk";
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
index b844473601d2..363ee62457fe 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
@@ -51,7 +51,7 @@
/ {
model = "samtec VIN|ING FPGA";
- compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+ compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga";
chosen {
bootargs = "console=ttyS0,115200";
--
cgit
From e8f0ff58330b76342359986a0321520106e80ad3 Mon Sep 17 00:00:00 2001
From: Dinh Nguyen <dinguyen@opensource.altera.com>
Date: Tue, 18 Oct 2016 22:51:42 -0500
Subject: ARM: dts: socfpga: enable qspi on the Cyclone5 devkit
Enable the qspi controller on the devkit and add the flash chip.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 33 ++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
index 7a5f42dba12e..6306d008f01b 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
@@ -87,6 +87,39 @@
status = "okay";
};
+&qspi {
+ status = "okay";
+
+ flash0: n25q00@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q00";
+ reg = <0>; /* chip select */
+ spi-max-frequency = <100000000>;
+
+ m25p,fast-read;
+ cdns,page-size = <256>;
+ cdns,block-size = <16>;
+ cdns,read-delay = <4>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+
+ partition@qspi-boot {
+ /* 8MB for raw data. */
+ label = "Flash 0 Raw Data";
+ reg = <0x0 0x800000>;
+ };
+
+ partition@qspi-rootfs {
+ /* 120MB for jffs2 data. */
+ label = "Flash 0 jffs2 Filesystem";
+ reg = <0x800000 0x7800000>;
+ };
+ };
+};
+
&usb1 {
status = "okay";
};
--
cgit
From 5d662bf15dcb35c79c8b80db468e1cb4a43cc066 Mon Sep 17 00:00:00 2001
From: Dinh Nguyen <dinguyen@opensource.altera.com>
Date: Wed, 19 Oct 2016 10:56:33 -0500
Subject: ARM: dts: socfpga: Add QSPI node for the Arria10
Add the QSPI device node for Arria10 SOC.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 1149216c78c5..551c636a4f01 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -675,6 +675,20 @@
};
};
+ qspi: spi@ff809000 {
+ compatible = "cdns,qspi-nor";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xff809000 0x100>,
+ <0xffa00000 0x100000>;
+ interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
+ cdns,fifo-depth = <128>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x00000000>;
+ clocks = <&qspi_clk>;
+ status = "disabled";
+ };
+
rst: rstmgr@ffd05000 {
#reset-cells = <1>;
compatible = "altr,rst-mgr";
--
cgit
From 1df99da8953afd4aef75f2dee77b61fc07e918e1 Mon Sep 17 00:00:00 2001
From: Dinh Nguyen <dinguyen@opensource.altera.com>
Date: Wed, 19 Oct 2016 10:07:48 -0500
Subject: ARM: dts: socfpga: Enable QSPI in Arria10 devkit
Enable the QSPI node and add the flash chip.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts | 49 ++++++++++++++++++++++++
2 files changed, 50 insertions(+)
create mode 100644 arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7c5f0c31b6f6..081fd94eb183 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -690,6 +690,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
sh73a0-kzm9g.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_arria5_socdk.dtb \
+ socfpga_arria10_socdk_qspi.dtb \
socfpga_arria10_socdk_sdmmc.dtb \
socfpga_cyclone5_mcvevk.dtb \
socfpga_cyclone5_socdk.dtb \
diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts
new file mode 100644
index 000000000000..beb2fc6b9eb6
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2016 Intel. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/dts-v1/;
+#include "socfpga_arria10_socdk.dtsi"
+
+&qspi {
+ status = "okay";
+
+ flash0: n25q00@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q00aa";
+ reg = <0>;
+ spi-max-frequency = <100000000>;
+
+ m25p,fast-read;
+ cdns,page-size = <256>;
+ cdns,block-size = <16>;
+ cdns,read-delay = <4>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+
+ partition@qspi-boot {
+ label = "Boot and fpga data";
+ reg = <0x0 0x2720000>;
+ };
+
+ partition@qspi-rootfs {
+ label = "Root Filesystem - JFFS2";
+ reg = <0x2720000 0x58E0000>;
+ };
+ };
+};
--
cgit
From 466e90ca2138c92b1e47d919237488b445b44d73 Mon Sep 17 00:00:00 2001
From: Dinh Nguyen <dinguyen@opensource.altera.com>
Date: Wed, 19 Oct 2016 14:55:54 -0500
Subject: ARM: dts: socfpga: Enable QSPI on the Cyclone5 sockit
Enable the QSPI node and add the flash chip.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v3: Use n25q00 for the compatible entry for the flash part and
tested on SoCKit
v2: Remove partition entries for the SoCKIT
---
arch/arm/boot/dts/socfpga_cyclone5_sockit.dts | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
index fcacaf7b2c83..a0c90b3bdfd1 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
@@ -175,6 +175,27 @@
status = "okay";
};
+&qspi {
+ status = "okay";
+
+ flash: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q00";
+ reg = <0>;
+ spi-max-frequency = <100000000>;
+
+ m25p,fast-read;
+ cdns,page-size = <256>;
+ cdns,block-size = <16>;
+ cdns,read-delay = <4>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+ };
+};
+
&usb1 {
status = "okay";
};
--
cgit
From 47d5c5ffa33d67990c93be14ceb754a89849a3dc Mon Sep 17 00:00:00 2001
From: Dinh Nguyen <dinguyen@opensource.altera.com>
Date: Wed, 19 Oct 2016 15:48:07 -0500
Subject: ARM: dts: socfpga: Enable QSPI on the Arria5 devkit
Enable the QSPI node and add the flash chip.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
arch/arm/boot/dts/socfpga_arria5_socdk.dts | 33 ++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
index 3c8867862b0d..f739ead074a2 100644
--- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
@@ -82,6 +82,39 @@
status = "okay";
};
+&qspi {
+ status = "okay";
+
+ flash: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q256a";
+ reg = <0>;
+ spi-max-frequency = <100000000>;
+
+ m25p,fast-read;
+ cdns,page-size = <256>;
+ cdns,block-size = <16>;
+ cdns,read-delay = <4>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+
+ partition@qspi-boot {
+ /* 8MB for raw data. */
+ label = "Flash 0 Raw Data";
+ reg = <0x0 0x800000>;
+ };
+
+ partition@qspi-rootfs {
+ /* 120MB for jffs2 data. */
+ label = "Flash 0 jffs2 Filesystem";
+ reg = <0x800000 0x7800000>;
+ };
+ };
+};
+
&usb1 {
status = "okay";
};
--
cgit
From 6a8883d614c7bede1075a4850139daa9723c291e Mon Sep 17 00:00:00 2001
From: Jaehoon Chung <jh80.chung@samsung.com>
Date: Thu, 3 Nov 2016 15:21:33 +0900
Subject: ARM: dts: rockchip: replace to "max-frequency" instead of
"clock-freq-min-max"
In drivers/mmc/core/host.c, there is "max-frequency" property.
It should be same behavior. So use the "max-frequency" instead of
"clock-freq-min-max".
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/boot/dts/rk3036.dtsi | 6 +++---
arch/arm/boot/dts/rk322x.dtsi | 2 +-
arch/arm/boot/dts/rk3288.dtsi | 8 ++++----
3 files changed, 8 insertions(+), 8 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index 81691ae50199..3279c996a300 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -246,7 +246,7 @@
compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x10214000 0x4000>;
clock-frequency = <37500000>;
- clock-freq-min-max = <400000 37500000>;
+ max-frequency = <37500000>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
clock-names = "biu", "ciu";
fifo-depth = <0x100>;
@@ -257,7 +257,7 @@
sdio: dwmmc@10218000 {
compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x10218000 0x4000>;
- clock-freq-min-max = <400000 37500000>;
+ max-frequency = <37500000>;
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
@@ -273,7 +273,7 @@
bus-width = <8>;
cap-mmc-highspeed;
clock-frequency = <37500000>;
- clock-freq-min-max = <400000 37500000>;
+ max-frequency = <37500000>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index 6ea8126d7a5f..9d3aee5abc15 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -404,7 +404,7 @@
reg = <0x30020000 0x4000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <37500000>;
- clock-freq-min-max = <400000 37500000>;
+ max-frequency = <37500000>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 2f814ffeb605..73590e47f4fb 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -229,7 +229,7 @@
sdmmc: dwmmc@ff0c0000 {
compatible = "rockchip,rk3288-dw-mshc";
- clock-freq-min-max = <400000 150000000>;
+ max-frequency = <150000000>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
@@ -241,7 +241,7 @@
sdio0: dwmmc@ff0d0000 {
compatible = "rockchip,rk3288-dw-mshc";
- clock-freq-min-max = <400000 150000000>;
+ max-frequency = <150000000>;
clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
<&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
@@ -253,7 +253,7 @@
sdio1: dwmmc@ff0e0000 {
compatible = "rockchip,rk3288-dw-mshc";
- clock-freq-min-max = <400000 150000000>;
+ max-frequency = <150000000>;
clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
<&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
@@ -265,7 +265,7 @@
emmc: dwmmc@ff0f0000 {
compatible = "rockchip,rk3288-dw-mshc";
- clock-freq-min-max = <400000 150000000>;
+ max-frequency = <150000000>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
--
cgit
From d837a80d19505d74ee5941eebf9dd53fed6f36a6 Mon Sep 17 00:00:00 2001
From: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Date: Wed, 9 Nov 2016 12:39:33 -0600
Subject: ARM: dts: socfpga: add nand controller nodes
Add the denali nand controller to the socfpga dtsi.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
arch/arm/boot/dts/socfpga.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index dda6b4500b9a..27c1d46127cf 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -701,6 +701,19 @@
status = "disabled";
};
+ nand0: nand@ff900000 {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "denali,denali-nand-dt";
+ reg = <0xff900000 0x100000>,
+ <0xffb80000 0x10000>;
+ reg-names = "nand_data", "denali_reg";
+ interrupts = <0x0 0x90 0x4>;
+ dma-mask = <0xffffffff>;
+ clocks = <&nand_clk>;
+ status = "disabled";
+ };
+
ocram: sram@ffff0000 {
compatible = "mmio-sram";
reg = <0xffff0000 0x10000>;
--
cgit
From 9adce7a44138e22c6d9169d7b0b239cd48a4f449 Mon Sep 17 00:00:00 2001
From: Jaehoon Chung <jh80.chung@samsung.com>
Date: Thu, 3 Nov 2016 15:21:32 +0900
Subject: ARM: dts: exynos: Replace "clock-freq-min-max" with "max-frequency"
In drivers/mmc/core/host.c, there is a "max-frequency" property.
Behavior should not change, so use the "max-frequency" instead of
"clock-freq-min-max".
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/boot/dts/exynos3250-artik5-eval.dts | 2 +-
arch/arm/boot/dts/exynos3250-artik5.dtsi | 2 +-
arch/arm/boot/dts/exynos3250-monk.dts | 2 +-
arch/arm/boot/dts/exynos3250-rinato.dts | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/exynos3250-artik5-eval.dts b/arch/arm/boot/dts/exynos3250-artik5-eval.dts
index be4d6aa379f3..4bd2ee87124e 100644
--- a/arch/arm/boot/dts/exynos3250-artik5-eval.dts
+++ b/arch/arm/boot/dts/exynos3250-artik5-eval.dts
@@ -28,7 +28,7 @@
vqmmc-supply = <&ldo3_reg>;
card-detect-delay = <200>;
clock-frequency = <100000000>;
- clock-freq-min-max = <400000 100000000>;
+ max-frequency = <100000000>;
samsung,dw-mshc-ciu-div = <1>;
samsung,dw-mshc-sdr-timing = <0 1>;
samsung,dw-mshc-ddr-timing = <1 2>;
diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi
index a70819b1b739..59c89d7662a8 100644
--- a/arch/arm/boot/dts/exynos3250-artik5.dtsi
+++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi
@@ -310,7 +310,7 @@
card-detect-delay = <200>;
vmmc-supply = <&ldo12_reg>;
clock-frequency = <100000000>;
- clock-freq-min-max = <400000 100000000>;
+ max-frequency = <100000000>;
samsung,dw-mshc-ciu-div = <1>;
samsung,dw-mshc-sdr-timing = <0 1>;
samsung,dw-mshc-ddr-timing = <1 2>;
diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts
index 66f04f6ba6bb..cccfe4b791d1 100644
--- a/arch/arm/boot/dts/exynos3250-monk.dts
+++ b/arch/arm/boot/dts/exynos3250-monk.dts
@@ -435,7 +435,7 @@
card-detect-delay = <200>;
vmmc-supply = <&vemmc_reg>;
clock-frequency = <100000000>;
- clock-freq-min-max = <400000 100000000>;
+ max-frequency = <100000000>;
samsung,dw-mshc-ciu-div = <1>;
samsung,dw-mshc-sdr-timing = <0 1>;
samsung,dw-mshc-ddr-timing = <1 2>;
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts
index 3967ee5f7752..548413e23c47 100644
--- a/arch/arm/boot/dts/exynos3250-rinato.dts
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -649,7 +649,7 @@
card-detect-delay = <200>;
vmmc-supply = <&ldo12_reg>;
clock-frequency = <100000000>;
- clock-freq-min-max = <400000 100000000>;
+ max-frequency = <100000000>;
samsung,dw-mshc-ciu-div = <1>;
samsung,dw-mshc-sdr-timing = <0 1>;
samsung,dw-mshc-ddr-timing = <1 2>;
--
cgit
From bd0fdb4cbdbcb96754eafadff6fd0a980e957287 Mon Sep 17 00:00:00 2001
From: Milo Kim <woogyom.kim@gmail.com>
Date: Fri, 28 Oct 2016 21:36:55 +0900
Subject: ARM: dts: tps65217: Specify the interrupt controller
TPS65217 MFD driver supports the IRQ domain to handle the charger input
interrupts and push button status event. The interrupt controller enables
corresponding IRQ handling in the charger[*] and power button driver[**].
[*] drivers/power/supply/tps65217_charger.c
[**] drivers/input/misc/tps65218-pwrbutton.c
Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/tps65217.dtsi | 2 ++
1 file changed, 2 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/tps65217.dtsi b/arch/arm/boot/dts/tps65217.dtsi
index a63272422d76..27935f8f080a 100644
--- a/arch/arm/boot/dts/tps65217.dtsi
+++ b/arch/arm/boot/dts/tps65217.dtsi
@@ -13,6 +13,8 @@
&tps {
compatible = "ti,tps65217";
+ interrupt-controller;
+ #interrupt-cells = <1>;
regulators {
#address-cells = <1>;
--
cgit
From 9ec0a6585f63513b7c55dedb16ee60837d9e6806 Mon Sep 17 00:00:00 2001
From: Milo Kim <woogyom.kim@gmail.com>
Date: Fri, 28 Oct 2016 21:36:56 +0900
Subject: ARM: dts: tps65217: Add the charger device
Support the charger driver and disable it by default.
Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/tps65217.dtsi | 5 +++++
1 file changed, 5 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/tps65217.dtsi b/arch/arm/boot/dts/tps65217.dtsi
index 27935f8f080a..8f77d0da05ea 100644
--- a/arch/arm/boot/dts/tps65217.dtsi
+++ b/arch/arm/boot/dts/tps65217.dtsi
@@ -16,6 +16,11 @@
interrupt-controller;
#interrupt-cells = <1>;
+ charger {
+ compatible = "ti,tps65217-charger";
+ status = "disabled";
+ };
+
regulators {
#address-cells = <1>;
#size-cells = <0>;
--
cgit
From e598c4418097fd39198a2e1259d0074880fdf9f9 Mon Sep 17 00:00:00 2001
From: Milo Kim <woogyom.kim@gmail.com>
Date: Fri, 28 Oct 2016 21:36:57 +0900
Subject: ARM: dts: tps65217: Add the power button device
Support the power button driver and disable it by default.
Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/tps65217.dtsi | 5 +++++
1 file changed, 5 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/tps65217.dtsi b/arch/arm/boot/dts/tps65217.dtsi
index 8f77d0da05ea..02de56b55823 100644
--- a/arch/arm/boot/dts/tps65217.dtsi
+++ b/arch/arm/boot/dts/tps65217.dtsi
@@ -21,6 +21,11 @@
status = "disabled";
};
+ pwrbutton {
+ compatible = "ti,tps65217-pwrbutton";
+ status = "disabled";
+ };
+
regulators {
#address-cells = <1>;
#size-cells = <0>;
--
cgit
From 2d63b9ce21363e9f545463221a94262ec6ab8430 Mon Sep 17 00:00:00 2001
From: Milo Kim <woogyom.kim@gmail.com>
Date: Fri, 28 Oct 2016 21:36:58 +0900
Subject: ARM: dts: am335x: Support the PMIC interrupt
AM335x bone based boards have the PMIC interrupt named NMI which is
connected to TPS65217 device. AM335x main interrupt controller provides it
and the number is 7.
Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/am335x-bone-common.dtsi | 4 ++++
1 file changed, 4 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi
index 007b5e5a51a9..25303d98b1b6 100644
--- a/arch/arm/boot/dts/am335x-bone-common.dtsi
+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
@@ -310,6 +310,10 @@
* by the hardware problems. (Tip: double-check by performing a current
* measurement after shutdown: it should be less than 1 mA.)
*/
+
+ interrupts = <7>; /* NMI */
+ interrupt-parent = <&intc>;
+
ti,pmic-shutdown-controller;
regulators {
--
cgit
From 1934e89a769b9da761f38e1c7b5e46ffa468f4c2 Mon Sep 17 00:00:00 2001
From: Milo Kim <woogyom.kim@gmail.com>
Date: Fri, 28 Oct 2016 21:37:00 +0900
Subject: ARM: dts: am335x: Add the charger interrupt
This enables the charger driver gets corresponding IRQ number by using
platform_get_irq_byname() helper.
Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/am335x-bone-common.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi
index 25303d98b1b6..cec9d91dc296 100644
--- a/arch/arm/boot/dts/am335x-bone-common.dtsi
+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
@@ -6,6 +6,8 @@
* published by the Free Software Foundation.
*/
+#include <dt-bindings/mfd/tps65217.h>
+
/ {
cpus {
cpu@0 {
@@ -316,6 +318,12 @@
ti,pmic-shutdown-controller;
+ charger {
+ interrupts = <TPS65217_IRQ_AC>, <TPS65217_IRQ_USB>;
+ interrupts-names = "AC", "USB";
+ status = "okay";
+ };
+
regulators {
dcdc1_reg: regulator@0 {
regulator-name = "vdds_dpr";
--
cgit
From eb3e4bbebac41946cf3001ebe11bd4c135b61f29 Mon Sep 17 00:00:00 2001
From: Milo Kim <woogyom.kim@gmail.com>
Date: Fri, 28 Oct 2016 21:37:01 +0900
Subject: ARM: dts: am335x: Add the power button interrupt
This enables the power button driver gets corresponding IRQ number by
using platform_get_irq().
Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/am335x-bone-common.dtsi | 5 +++++
1 file changed, 5 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi
index cec9d91dc296..0c0a90c30afa 100644
--- a/arch/arm/boot/dts/am335x-bone-common.dtsi
+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
@@ -324,6 +324,11 @@
status = "okay";
};
+ pwrbutton {
+ interrupts = <TPS65217_IRQ_PB>;
+ status = "okay";
+ };
+
regulators {
dcdc1_reg: regulator@0 {
regulator-name = "vdds_dpr";
--
cgit
From 3559fe7bd8b35fcda683d442597f68b176268621 Mon Sep 17 00:00:00 2001
From: "H. Nikolaus Schaller" <hns@goldelico.com>
Date: Thu, 29 Sep 2016 07:25:36 +0200
Subject: ARM: dts: omap5 uevm: add EEPROM
Add EEPROM.
Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/omap5-uevm.dts | 7 +++++++
1 file changed, 7 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
index 53d31a87b44b..577e33885f4f 100644
--- a/arch/arm/boot/dts/omap5-uevm.dts
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -33,6 +33,13 @@
vdda-supply = <&ldo4_reg>;
};
+&i2c1 {
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ };
+};
+
&i2c5 {
pinctrl-names = "default";
pinctrl-0 = <&i2c5_pins>;
--
cgit
From b14b0eb0b892ccd8953dc4b5908eb161b5e77d1d Mon Sep 17 00:00:00 2001
From: "H. Nikolaus Schaller" <hns@goldelico.com>
Date: Thu, 29 Sep 2016 07:25:37 +0200
Subject: ARM: dts: omap5 uevm: add LEDs
Add LEDs.
Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/omap5-uevm.dts | 60 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 60 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
index 577e33885f4f..c8ab6275f1d8 100644
--- a/arch/arm/boot/dts/omap5-uevm.dts
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -27,6 +27,66 @@
default-state = "off";
};
};
+
+ evm_leds {
+ compatible = "gpio-leds";
+
+ led1 {
+ label = "omap5:red:led";
+ gpios = <&gpio9 17 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ default-state = "off";
+ };
+
+ led2 {
+ label = "omap5:green:led";
+ gpios = <&gpio9 18 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc1";
+ default-state = "off";
+ };
+
+ led3 {
+ label = "omap5:blue:led";
+ gpios = <&gpio9 19 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc2";
+ default-state = "off";
+ };
+
+ led4 {
+ label = "omap5:green:led1";
+ gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+
+ led5 {
+ label = "omap5:green:led2";
+ gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ default-state = "off";
+ };
+
+ led6 {
+ label = "omap5:green:led3";
+ gpios = <&gpio9 4 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+
+ led7 {
+ label = "omap5:green:led4";
+ gpios = <&gpio9 5 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ default-state = "off";
+ };
+
+ led8 {
+ label = "omap5:green:led5";
+ gpios = <&gpio9 6 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+ };
};
&hdmi {
--
cgit
From 2d46c0c607255716758f95eac570c890abc56c45 Mon Sep 17 00:00:00 2001
From: "H. Nikolaus Schaller" <hns@goldelico.com>
Date: Thu, 29 Sep 2016 07:25:38 +0200
Subject: ARM: dts: omap5 uevm: add USR1 button
Add USR1 button.
Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/omap5-uevm.dts | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
index c8ab6275f1d8..2fcdc516da45 100644
--- a/arch/arm/boot/dts/omap5-uevm.dts
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -28,6 +28,25 @@
};
};
+ evm_keys {
+ compatible = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&evm_keys_pins>;
+
+ #address-cells = <7>;
+ #size-cells = <0>;
+
+ btn1 {
+ label = "BTN1";
+ linux,code = <169>;
+ gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; /* gpio3_83 */
+ gpio-key,wakeup;
+ autorepeat;
+ debounce_interval = <50>;
+ };
+ };
+
evm_leds {
compatible = "gpio-leds";
@@ -115,6 +134,12 @@
};
&omap5_pmx_core {
+ evm_keys_pins: pinmux_evm_keys_gpio_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x0b6, PIN_INPUT | MUX_MODE6) /* gpio3_83 */
+ >;
+ };
+
i2c5_pins: pinmux_i2c5_pins {
pinctrl-single,pins = <
OMAP5_IOPAD(0x1c6, PIN_INPUT | MUX_MODE0) /* i2c5_scl */
--
cgit
From 55e871fc19ca9e98b0c8e33f12d2996f363debbb Mon Sep 17 00:00:00 2001
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Wed, 5 Oct 2016 14:34:42 +0530
Subject: ARM: dts: am33xx: add DMA properties for tscadc
Add DMA properties for tscadc
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/am33xx.dtsi | 2 ++
1 file changed, 2 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 194d884c9de1..348ed77a355a 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -855,6 +855,8 @@
interrupts = <16>;
ti,hwmods = "adc_tsc";
status = "disabled";
+ dmas = <&edma 53 0>, <&edma 57 0>;
+ dma-names = "fifo0", "fifo1";
tsc {
compatible = "ti,am3359-tsc";
--
cgit
From b6a4280a59f00db1d8732e1eafa0808abea1af06 Mon Sep 17 00:00:00 2001
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Wed, 5 Oct 2016 14:34:43 +0530
Subject: ARM: dts: am4372: add DMA properties for tscadc
Add DMA properties for tscadc
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/am4372.dtsi | 2 ++
1 file changed, 2 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index a275fa956813..c58345739360 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -871,6 +871,8 @@
clocks = <&adc_tsc_fck>;
clock-names = "fck";
status = "disabled";
+ dmas = <&edma 53 0>, <&edma 57 0>;
+ dma-names = "fifo0", "fifo1";
tsc {
compatible = "ti,am3359-tsc";
--
cgit
From eae3339f23f41162fc9600dd3caa9d3049c572d2 Mon Sep 17 00:00:00 2001
From: Yegor Yefremov <yegorslists@googlemail.com>
Date: Wed, 19 Oct 2016 09:09:03 +0200
Subject: ARM: dts: am335x-baltos-ir5221: use both musb channels in host mode
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/am335x-baltos-ir5221.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/am335x-baltos-ir5221.dts b/arch/arm/boot/dts/am335x-baltos-ir5221.dts
index d0faa7b8c5da..f599350dd305 100644
--- a/arch/arm/boot/dts/am335x-baltos-ir5221.dts
+++ b/arch/arm/boot/dts/am335x-baltos-ir5221.dts
@@ -114,7 +114,7 @@
&usb1 {
status = "okay";
- dr_mode = "otg";
+ dr_mode = "host";
};
&cpsw_emac0 {
--
cgit
From 17fad5f3ab61210fb9a7b43decae275e01968a63 Mon Sep 17 00:00:00 2001
From: Keerthy <j-keerthy@ti.com>
Date: Thu, 27 Oct 2016 11:18:06 +0530
Subject: ARM: dts: AM335X-bone-common: Add the internal and external clock
nodes for rtc
rtc can either be supplied from internal 32k clock or external crystal
generated 32k clock. Internal clock is SoC specific and the external
clock is board dependent. Assigning the corresponding clocks.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/am335x-bone-common.dtsi | 5 +++++
arch/arm/boot/dts/am33xx.dtsi | 2 ++
2 files changed, 7 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi
index 0c0a90c30afa..dc561d505bbe 100644
--- a/arch/arm/boot/dts/am335x-bone-common.dtsi
+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
@@ -410,3 +410,8 @@
&sham {
status = "okay";
};
+
+&rtc {
+ clocks = <&clk_32768_ck>, <&clkdiv32k_ick>;
+ clock-names = "ext-clk", "int-clk";
+};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 348ed77a355a..104bea434e81 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -505,6 +505,8 @@
interrupts = <75
76>;
ti,hwmods = "rtc";
+ clocks = <&clkdiv32k_ick>;
+ clock-names = "int-clk";
};
spi0: spi@48030000 {
--
cgit
From 542a7707ce8c153872ccfbbfe288176552664276 Mon Sep 17 00:00:00 2001
From: Keerthy <j-keerthy@ti.com>
Date: Thu, 27 Oct 2016 11:18:07 +0530
Subject: ARM: dts: AM335X-evm: Add the internal and external clock nodes for
rtc
rtc can either be supplied from internal 32k clock or external crystal
generated 32k clock. Internal clock is SoC specific and the external
clock is board dependent. Assigning the corresponding clocks.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/am335x-evm.dts | 5 +++++
1 file changed, 5 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index e82432c79f85..c2186ec2834b 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -783,3 +783,8 @@
pinctrl-names = "default";
pinctrl-0 = <&dcan1_pins_default>;
};
+
+&rtc {
+ clocks = <&clk_32768_ck>, <&clkdiv32k_ick>;
+ clock-names = "ext-clk", "int-clk";
+};
--
cgit
From 3fb5c894f6db642d970403fe55055c0425f9fac9 Mon Sep 17 00:00:00 2001
From: Keerthy <j-keerthy@ti.com>
Date: Thu, 27 Oct 2016 11:18:08 +0530
Subject: ARM: dts: AM335X-evmsk: Add the internal and external clock nodes for
rtc
rtc can either be supplied from internal 32k clock or external crystal
generated 32k clock. Internal clock is SoC specific and the external
clock is board dependent. Assigning the corresponding clocks.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/am335x-evmsk.dts | 5 +++++
1 file changed, 5 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index 975c36e332a2..e2548d1ce753 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -715,3 +715,8 @@
blue-and-red-wiring = "crossed";
};
+
+&rtc {
+ clocks = <&clk_32768_ck>, <&clkdiv32k_ick>;
+ clock-names = "ext-clk", "int-clk";
+};
--
cgit
From 5ce93ff601614c17197eeebfa53aacddccb67225 Mon Sep 17 00:00:00 2001
From: Yegor Yefremov <yegorslists@googlemail.com>
Date: Wed, 2 Nov 2016 10:08:16 +0100
Subject: ARM: dts: am335x-baltos: don't reset gpio3 block
This change is needed in order to enable some hardware components
from bootloader.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/am335x-baltos.dtsi | 4 ++++
1 file changed, 4 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/am335x-baltos.dtsi b/arch/arm/boot/dts/am335x-baltos.dtsi
index dd45d172a892..09b954154e6b 100644
--- a/arch/arm/boot/dts/am335x-baltos.dtsi
+++ b/arch/arm/boot/dts/am335x-baltos.dtsi
@@ -406,3 +406,7 @@
&gpio0 {
ti,no-reset-on-init;
};
+
+&gpio3 {
+ ti,no-reset-on-init;
+};
--
cgit
From 46cfc8945887d379630dc7da47c2e546ee65152f Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Fri, 21 Oct 2016 16:08:33 +0530
Subject: ARM: dts: dra72-evm: Remove pinmux configurations for erratum i869
Pinmuxing for DRA7x/AM57x family of processors need to be done in IO
isolation as part of initial bootloader executed from SRAM. This is
done as part of iodelay configuration sequence and is required due
to the limitations introduced by erratum ID: i869[1] (IO Glitches
can occur when changing IO settings) and elaborated in the Technical
Reference Manual[2] 18.4.6.1.7 Isolation Requirements.
Only peripheral that is permitted for dynamic pin mux configuration
is MMC and DCAN. MMC is permitted to change to accommodate the
requirements for varied speeds (which require IO-delay support in
kernel as well). DCAN is a result of i893[1] (DCAN initialization
sequence). With the exception of DCAN and MMC, all other pin mux
configurations are removed from the dts.
[1] http://www.ti.com/lit/er/sprz436a/sprz436a.pdf
[2] http://www.ti.com/lit/ug/spruhz7c/spruhz7c.pdf
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/dra72-evm-common.dtsi | 192 --------------------------------
1 file changed, 192 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi
index c94d8d64710d..3c02612216c0 100644
--- a/arch/arm/boot/dts/dra72-evm-common.dtsi
+++ b/arch/arm/boot/dts/dra72-evm-common.dtsi
@@ -69,9 +69,6 @@
tpd12s015: encoder {
compatible = "ti,tpd12s015";
- pinctrl-names = "default";
- pinctrl-0 = <&tpd12s015_pins>;
-
gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
<&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
<&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
@@ -134,72 +131,6 @@
};
&dra7_pmx_core {
- i2c1_pins: pinmux_i2c1_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
- DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
- >;
- };
-
- i2c5_pins: pinmux_i2c5_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
- DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
- >;
- };
-
- i2c5_pins: pinmux_i2c5_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
- DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
- >;
- };
-
- nand_default: nand_default {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
- DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
- DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
- DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
- DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
- DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
- DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
- DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
- DRA7XX_CORE_IOPAD(0x3420, PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
- DRA7XX_CORE_IOPAD(0x3424, PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
- DRA7XX_CORE_IOPAD(0x3428, PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
- DRA7XX_CORE_IOPAD(0x342c, PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
- DRA7XX_CORE_IOPAD(0x3430, PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
- DRA7XX_CORE_IOPAD(0x3434, PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
- DRA7XX_CORE_IOPAD(0x3438, PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
- DRA7XX_CORE_IOPAD(0x343c, PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
- DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
- DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
- DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
- DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
- DRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
- DRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */
- >;
- };
-
- usb1_pins: pinmux_usb1_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
- >;
- };
-
- usb2_pins: pinmux_usb2_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
- >;
- };
-
- tps65917_pins_default: tps65917_pins_default {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3824, PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
- >;
- };
-
mmc1_pins_default: mmc1_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
@@ -240,59 +171,16 @@
DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
>;
};
-
- hdmi_pins: pinmux_hdmi_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
- DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
- >;
- };
-
- tpd12s015_pins: pinmux_tpd12s015_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */
- >;
- };
-
- atl_pins: pinmux_atl_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */
- DRA7XX_CORE_IOPAD(0x369c, PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */
- >;
- };
-
- mcasp3_pins: pinmux_mcasp3_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3724, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */
- DRA7XX_CORE_IOPAD(0x3728, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */
- DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */
- DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */
- >;
- };
-
- mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT_PULLDOWN | MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x372c, PIN_INPUT_PULLDOWN | MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE15)
- >;
- };
};
&i2c1 {
status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
tps65917: tps65917@58 {
compatible = "ti,tps65917";
reg = <0x58>;
- pinctrl-names = "default";
- pinctrl-0 = <&tps65917_pins_default>;
-
interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
interrupt-controller;
#interrupt-cells = <2>;
@@ -423,8 +311,6 @@
&i2c5 {
status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c5_pins>;
clock-frequency = <400000>;
pcf_hdmi: pcf8575@26 {
@@ -462,8 +348,6 @@
&gpmc {
status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&nand_default>;
ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
nand@0,0 {
/* To use NAND, DIP switch SW5 must be set like so:
@@ -566,14 +450,10 @@
&usb1 {
dr_mode = "peripheral";
- pinctrl-names = "default";
- pinctrl-0 = <&usb1_pins>;
};
&usb2 {
dr_mode = "host";
- pinctrl-names = "default";
- pinctrl-0 = <&usb2_pins>;
};
&mmc1 {
@@ -603,71 +483,8 @@
max-frequency = <192000000>;
};
-&dra7_pmx_core {
- cpsw_default: cpsw_default {
- pinctrl-single,pins = <
- /* Slave 2 */
- DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
- DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
- DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
- DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
- DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
- DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
- DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
- DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
- DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
- DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
- DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
- DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
- >;
-
- };
-
- cpsw_sleep: cpsw_sleep {
- pinctrl-single,pins = <
- /* Slave 2 */
- DRA7XX_CORE_IOPAD(0x3598, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x359c, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35a0, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35a4, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35a8, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35ac, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35b0, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35b4, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35b8, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35bc, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35c0, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35c4, MUX_MODE15)
- >;
- };
-
- davinci_mdio_default: davinci_mdio_default {
- pinctrl-single,pins = <
- /* MDIO */
- DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
- DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
- >;
- };
-
- davinci_mdio_sleep: davinci_mdio_sleep {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x363c, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x3640, MUX_MODE15)
- >;
- };
-};
-
&mac {
status = "okay";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&cpsw_default>;
- pinctrl-1 = <&cpsw_sleep>;
-};
-
-&davinci_mdio {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&davinci_mdio_default>;
- pinctrl-1 = <&davinci_mdio_sleep>;
};
&dcan1 {
@@ -748,9 +565,6 @@
&hdmi {
status = "ok";
- pinctrl-names = "default";
- pinctrl-0 = <&hdmi_pins>;
-
port {
hdmi_out: endpoint {
remote-endpoint = <&tpd12s015_in>;
@@ -759,9 +573,6 @@
};
&atl {
- pinctrl-names = "default";
- pinctrl-0 = <&atl_pins>;
-
assigned-clocks = <&abe_dpll_sys_clk_mux>,
<&atl_gfclk_mux>,
<&dpll_abe_ck>,
@@ -780,9 +591,6 @@
&mcasp3 {
#sound-dai-cells = <0>;
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&mcasp3_pins>;
- pinctrl-1 = <&mcasp3_sleep_pins>;
assigned-clocks = <&mcasp3_ahclkx_mux>;
assigned-clock-parents = <&atl_clkin2_ck>;
--
cgit
From e9a05fbd21deae4b32e590850587f3e76abcd1e6 Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Fri, 21 Oct 2016 16:08:34 +0530
Subject: ARM: dts: dra72-evm: Fix modelling of regulators
Add proper description of input voltage regulators and update the voltage
rail map for all the regulators.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/dra72-evm-common.dtsi | 48 +++++++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi
index 3c02612216c0..8537b6a9e5dc 100644
--- a/arch/arm/boot/dts/dra72-evm-common.dtsi
+++ b/arch/arm/boot/dts/dra72-evm-common.dtsi
@@ -18,11 +18,47 @@
display0 = &hdmi0;
};
+ evm_12v0: fixedregulator-evm12v0 {
+ /* main supply */
+ compatible = "regulator-fixed";
+ regulator-name = "evm_12v0";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ evm_5v0: fixedregulator-evm5v0 {
+ /* Output 1 of TPS43351QDAPRQ1 */
+ compatible = "regulator-fixed";
+ regulator-name = "evm_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&evm_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_3v3: fixedregulator-vsys3v3 {
+ /* Output 2 of TPS43351QDAPRQ1 */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&evm_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
evm_3v3_sw: fixedregulator-evm_3v3 {
+ /* TPS22965DSG */
compatible = "regulator-fixed";
regulator-name = "evm_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
+ vin-supply = <&vsys_3v3>;
+ regulator-always-on;
+ regulator-boot-on;
};
aic_dvdd: fixedregulator-aic_dvdd {
@@ -39,6 +75,7 @@
regulator-name = "evm_3v3_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
+ vin-supply = <&evm_3v3_sw>;
enable-active-high;
gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
};
@@ -190,6 +227,17 @@
tps65917_pmic {
compatible = "ti,tps65917-pmic";
+ smps1-in-supply = <&vsys_3v3>;
+ smps2-in-supply = <&vsys_3v3>;
+ smps3-in-supply = <&vsys_3v3>;
+ smps4-in-supply = <&vsys_3v3>;
+ smps5-in-supply = <&vsys_3v3>;
+ ldo1-in-supply = <&vsys_3v3>;
+ ldo2-in-supply = <&vsys_3v3>;
+ ldo3-in-supply = <&vsys_3v3>;
+ ldo4-in-supply = <&evm_5v0>;
+ ldo5-in-supply = <&vsys_3v3>;
+
tps65917_regulators: regulators {
smps1_reg: smps1 {
/* VDD_MPU */
--
cgit
From 5d080aa3068128e71b92c351db9afb187ad6bcc7 Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Fri, 21 Oct 2016 16:08:35 +0530
Subject: ARM: dts: dra72: Add separate dtsi for tps65917
dra72-evm-common.dtsi consolidates dra72-evm.dts and dra72-evm-revc.dts
which also include tps65917 pmic support as both the evms uses the same
pmic. But, dra71-evm has mostly similar features with a different pmic.
In order to exploit dra72-evm-common.dtsi, creating a separate dtsi
for tps65915 support and including it in respective board files.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/dra72-evm-common.dtsi | 128 ----------------------------
arch/arm/boot/dts/dra72-evm-revc.dts | 21 +++--
arch/arm/boot/dts/dra72-evm-tps65917.dtsi | 134 ++++++++++++++++++++++++++++++
arch/arm/boot/dts/dra72-evm.dts | 14 ++--
4 files changed, 154 insertions(+), 143 deletions(-)
create mode 100644 arch/arm/boot/dts/dra72-evm-tps65917.dtsi
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi
index 8537b6a9e5dc..9903ac774242 100644
--- a/arch/arm/boot/dts/dra72-evm-common.dtsi
+++ b/arch/arm/boot/dts/dra72-evm-common.dtsi
@@ -214,123 +214,6 @@
status = "okay";
clock-frequency = <400000>;
- tps65917: tps65917@58 {
- compatible = "ti,tps65917";
- reg = <0x58>;
-
- interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
- interrupt-controller;
- #interrupt-cells = <2>;
-
- ti,system-power-controller;
-
- tps65917_pmic {
- compatible = "ti,tps65917-pmic";
-
- smps1-in-supply = <&vsys_3v3>;
- smps2-in-supply = <&vsys_3v3>;
- smps3-in-supply = <&vsys_3v3>;
- smps4-in-supply = <&vsys_3v3>;
- smps5-in-supply = <&vsys_3v3>;
- ldo1-in-supply = <&vsys_3v3>;
- ldo2-in-supply = <&vsys_3v3>;
- ldo3-in-supply = <&vsys_3v3>;
- ldo4-in-supply = <&evm_5v0>;
- ldo5-in-supply = <&vsys_3v3>;
-
- tps65917_regulators: regulators {
- smps1_reg: smps1 {
- /* VDD_MPU */
- regulator-name = "smps1";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1250000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- smps2_reg: smps2 {
- /* VDD_CORE */
- regulator-name = "smps2";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1150000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- smps3_reg: smps3 {
- /* VDD_GPU IVA DSPEVE */
- regulator-name = "smps3";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1250000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- smps4_reg: smps4 {
- /* VDDS1V8 */
- regulator-name = "smps4";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- smps5_reg: smps5 {
- /* VDD_DDR */
- regulator-name = "smps5";
- regulator-min-microvolt = <1350000>;
- regulator-max-microvolt = <1350000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo1_reg: ldo1 {
- /* LDO1_OUT --> SDIO */
- regulator-name = "ldo1";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-allow-bypass;
- };
-
- ldo3_reg: ldo3 {
- /* VDDA_1V8_PHY */
- regulator-name = "ldo3";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo5_reg: ldo5 {
- /* VDDA_1V8_PLL */
- regulator-name = "ldo5";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldo4_reg: ldo4 {
- /* VDDA_3V_USB: VDDA_USBHS33 */
- regulator-name = "ldo4";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- };
- };
- };
-
- tps65917_power_button {
- compatible = "ti,palmas-pwrbutton";
- interrupt-parent = <&tps65917>;
- interrupts = <1 IRQ_TYPE_NONE>;
- wakeup-source;
- ti,palmas-long-press-seconds = <6>;
- };
- };
-
pcf_gpio_21: gpio@21 {
compatible = "ti,pcf8575", "nxp,pcf8575";
reg = <0x21>;
@@ -480,14 +363,6 @@
};
};
-&usb2_phy1 {
- phy-supply = <&ldo4_reg>;
-};
-
-&usb2_phy2 {
- phy-supply = <&ldo4_reg>;
-};
-
&omap_dwc3_1 {
extcon = <&extcon_usb1>;
};
@@ -509,7 +384,6 @@
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins_default>;
vmmc-supply = <&evm_3v3_sd>;
- vmmc_aux-supply = <&ldo1_reg>;
bus-width = <4>;
/*
* SDCD signal is not being used here - using the fact that GPIO mode
@@ -606,8 +480,6 @@
&dss {
status = "ok";
-
- vdda_video-supply = <&ldo5_reg>;
};
&hdmi {
diff --git a/arch/arm/boot/dts/dra72-evm-revc.dts b/arch/arm/boot/dts/dra72-evm-revc.dts
index 064b322a7a04..4ea2a0c7819e 100644
--- a/arch/arm/boot/dts/dra72-evm-revc.dts
+++ b/arch/arm/boot/dts/dra72-evm-revc.dts
@@ -17,17 +17,22 @@
};
};
-&tps65917_regulators {
- ldo2_reg: ldo2 {
- /* LDO2_OUT --> VDDA_1V8_PHY2 */
- regulator-name = "ldo2";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
+&i2c1 {
+ tps65917: tps65917@58 {
+ reg = <0x58>;
+
+ interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
};
};
+#include "dra72-evm-tps65917.dtsi"
+
+&ldo2_reg {
+ /* LDO2_OUT --> VDDA_1V8_PHY2 */
+ regulator-always-on;
+ regulator-boot-on;
+};
+
&hdmi {
vdda-supply = <&ldo2_reg>;
};
diff --git a/arch/arm/boot/dts/dra72-evm-tps65917.dtsi b/arch/arm/boot/dts/dra72-evm-tps65917.dtsi
new file mode 100644
index 000000000000..ee6dac44edf1
--- /dev/null
+++ b/arch/arm/boot/dts/dra72-evm-tps65917.dtsi
@@ -0,0 +1,134 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Integrated Power Management Chip
+ * http://www.ti.com/lit/ds/symlink/tps65917-q1.pdf
+ */
+
+&tps65917 {
+ compatible = "ti,tps65917";
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ ti,system-power-controller;
+
+ tps65917_pmic {
+ compatible = "ti,tps65917-pmic";
+
+ smps1-in-supply = <&vsys_3v3>;
+ smps2-in-supply = <&vsys_3v3>;
+ smps3-in-supply = <&vsys_3v3>;
+ smps4-in-supply = <&vsys_3v3>;
+ smps5-in-supply = <&vsys_3v3>;
+ ldo1-in-supply = <&vsys_3v3>;
+ ldo2-in-supply = <&vsys_3v3>;
+ ldo3-in-supply = <&vsys_3v3>;
+ ldo4-in-supply = <&evm_5v0>;
+ ldo5-in-supply = <&vsys_3v3>;
+
+ tps65917_regulators: regulators {
+ smps1_reg: smps1 {
+ /* VDD_MPU */
+ regulator-name = "smps1";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps2_reg: smps2 {
+ /* VDD_CORE */
+ regulator-name = "smps2";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ smps3_reg: smps3 {
+ /* VDD_GPU IVA DSPEVE */
+ regulator-name = "smps3";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ smps4_reg: smps4 {
+ /* VDDS1V8 */
+ regulator-name = "smps4";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps5_reg: smps5 {
+ /* VDD_DDR */
+ regulator-name = "smps5";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1_reg: ldo1 {
+ /* LDO1_OUT --> SDIO */
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-allow-bypass;
+ };
+
+ ldo2_reg: ldo2 {
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-allow-bypass;
+ };
+
+ ldo3_reg: ldo3 {
+ /* VDDA_1V8_PHY */
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo5_reg: ldo5 {
+ /* VDDA_1V8_PLL */
+ regulator-name = "ldo5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo4_reg: ldo4 {
+ /* VDDA_3V_USB: VDDA_USBHS33 */
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ };
+ };
+ };
+
+ tps65917_power_button {
+ compatible = "ti,palmas-pwrbutton";
+ interrupt-parent = <&tps65917>;
+ interrupts = <1 IRQ_TYPE_NONE>;
+ wakeup-source;
+ ti,palmas-long-press-seconds = <6>;
+ };
+};
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index e3a9b6985693..cd9c4ff12654 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -15,16 +15,16 @@
};
};
-&tps65917_regulators {
- ldo2_reg: ldo2 {
- /* LDO2_OUT --> TP1017 (UNUSED) */
- regulator-name = "ldo2";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-allow-bypass;
+&i2c1 {
+ tps65917: tps65917@58 {
+ reg = <0x58>;
+
+ interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
};
};
+#include "dra72-evm-tps65917.dtsi"
+
&hdmi {
vdda-supply = <&ldo3_reg>;
};
--
cgit
From 6eebfeb9cf0dd0e6057a57b12f647cfc55f4f58d Mon Sep 17 00:00:00 2001
From: Nishanth Menon <nm@ti.com>
Date: Fri, 21 Oct 2016 16:08:39 +0530
Subject: ARM: dts: Add support for dra718-evm
The DRA718-evm is a board based on TI's DRA718 processor targeting
BOM-optimized entry infotainment systems and is a reduced pin and
software compatible derivative of the DRA72 ES2.0 processor.
This platform features:
- 2GB of DDR3L
- Dual 1Gbps Ethernet
- HDMI,
- uSD
- 8GB eMMC
- CAN
- PCIe
- USB3.0
- Video Input Port
- LP873x PMIC
More information can be found here[1].
Adding support for this board while reusing the data available in
dra72-evm-common.dtsi.
[1] http://www.ti.com/product/dra718
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/dra71-evm.dts | 230 ++++++++++++++++++++++++++++++++
arch/arm/boot/dts/dra72-evm-common.dtsi | 6 +-
3 files changed, 236 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/boot/dts/dra71-evm.dts
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index befcd2619902..b92d5016bf00 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -590,7 +590,8 @@ dtb-$(CONFIG_SOC_DRA7XX) += \
am572x-idk.dtb \
dra7-evm.dtb \
dra72-evm.dtb \
- dra72-evm-revc.dtb
+ dra72-evm-revc.dtb \
+ dra71-evm.dtb
dtb-$(CONFIG_ARCH_ORION5X) += \
orion5x-kuroboxpro.dtb \
orion5x-lacie-d2-network.dtb \
diff --git a/arch/arm/boot/dts/dra71-evm.dts b/arch/arm/boot/dts/dra71-evm.dts
new file mode 100644
index 000000000000..2b9a5a8d69ad
--- /dev/null
+++ b/arch/arm/boot/dts/dra71-evm.dts
@@ -0,0 +1,230 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "dra72-evm-common.dtsi"
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+ compatible = "ti,dra718-evm", "ti,dra718", "ti,dra722", "ti,dra72", "ti,dra7";
+ model = "TI DRA718 EVM";
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */
+ };
+
+ vpo_sd_1v8_3v3: gpio-regulator-TPS74801 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "vddshv8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ vin-supply = <&evm_5v0>;
+
+ gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x0
+ 3000000 0x1>;
+ };
+
+ poweroff: gpio-poweroff {
+ compatible = "gpio-poweroff";
+ gpios = <&gpio7 30 GPIO_ACTIVE_HIGH>;
+ input;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ lp8733: lp8733@60 {
+ compatible = "ti,lp8733";
+ reg = <0x60>;
+
+ buck0-in-supply =<&vsys_3v3>;
+ buck1-in-supply =<&vsys_3v3>;
+ ldo0-in-supply =<&evm_5v0>;
+ ldo1-in-supply =<&evm_5v0>;
+
+ lp8733_regulators: regulators {
+ lp8733_buck0_reg: buck0 {
+ /* FB_B0 -> LP8733-BUCK1 - VPO_S1_AVS - VDD_CORE_AVS (core, mpu, gpu) */
+ regulator-name = "lp8733-buck0";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ lp8733_buck1_reg: buck1 {
+ /* FB_B1 -> LP8733-BUCK2 - VPO_S2_AVS - VDD_DSP_AVS (DSP/eve/iva) */
+ regulator-name = "lp8733-buck1";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ lp8733_ldo0_reg: ldo0 {
+ /* LDO0 -> LP8733-LDO1 - VPO_L1_3V3 - VDDSHV8 (optional) */
+ regulator-name = "lp8733-ldo0";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ lp8733_ldo1_reg: ldo1 {
+ /* LDO1 -> LP8733-LDO2 - VPO_L2_3V3 - VDDA_USB3V3 */
+ regulator-name = "lp8733-ldo1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+
+ lp8732: lp8732@61 {
+ compatible = "ti,lp8732";
+ reg = <0x61>;
+
+ buck0-in-supply =<&vsys_3v3>;
+ buck1-in-supply =<&vsys_3v3>;
+ ldo0-in-supply =<&vsys_3v3>;
+ ldo1-in-supply =<&vsys_3v3>;
+
+ lp8732_regulators: regulators {
+ lp8732_buck0_reg: buck0 {
+ /* FB_B0 -> LP8732-BUCK1 - VPO_S3_1V8 - VDDS_1V8 */
+ regulator-name = "lp8732-buck0";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ lp8732_buck1_reg: buck1 {
+ /* FB_B1 -> LP8732-BUCK2 - VPO_S4_DDR - VDD_DDR_1V35 */
+ regulator-name = "lp8732-buck1";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ lp8732_ldo0_reg: ldo0 {
+ /* LDO0 -> LP8732-LDO1 - VPO_L3_1V8 - VDA_1V8_PLL */
+ regulator-name = "lp8732-ldo0";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ lp8732_ldo1_reg: ldo1 {
+ /* LDO1 -> LP8732-LDO2 - VPO_L4_1V8 - VDA_1V8_PHY */
+ regulator-name = "lp8732-ldo1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+};
+
+&pcf_gpio_21 {
+ interrupt-parent = <&gpio7>;
+ interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
+};
+
+&pcf_hdmi {
+ p0 {
+ /*
+ * PM_OEn to High: Disable routing I2C3 to PM_I2C
+ * With this PM_SEL(p3) should not matter
+ */
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_LOW>;
+ output-high;
+ line-name = "pm_oe_n";
+ };
+};
+
+&mmc1 {
+ vmmc_aux-supply = <&vpo_sd_1v8_3v3>;
+};
+
+&mac {
+ mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>,
+ <&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */
+ <&pcf_hdmi 10 GPIO_ACTIVE_LOW>; /* P12 */
+ dual_emac;
+};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <2>;
+ phy-mode = "rgmii-id";
+ dual_emac_res_vlan = <1>;
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <3>;
+ phy-mode = "rgmii-id";
+ dual_emac_res_vlan = <2>;
+};
+
+&davinci_mdio {
+ dp83867_0: ethernet-phy@2 {
+ reg = <2>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
+ ti,impedance-control = <0x1f>;
+ };
+
+ dp83867_1: ethernet-phy@3 {
+ reg = <3>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
+ ti,impedance-control = <0x1f>;
+ };
+};
+
+/* No Sata on this device */
+&sata_phy {
+ status = "disabled";
+};
+
+&sata {
+ status = "disabled";
+};
+
+/* No RTC on this device */
+&rtc {
+ status = "disabled";
+};
+
+&usb2_phy1 {
+ phy-supply = <&lp8733_ldo1_reg>;
+};
+
+&usb2_phy2 {
+ phy-supply = <&lp8733_ldo1_reg>;
+};
+
+&dss {
+ /* Supplied by VDA_1V8_PLL */
+ vdda_video-supply = <&lp8732_ldo0_reg>;
+};
+
+&hdmi {
+ /* Supplied by VDA_1V8_PHY */
+ vdda_video-supply = <&lp8732_ldo1_reg>;
+};
diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi
index 9903ac774242..e50fbeea96e0 100644
--- a/arch/arm/boot/dts/dra72-evm-common.dtsi
+++ b/arch/arm/boot/dts/dra72-evm-common.dtsi
@@ -29,7 +29,8 @@
};
evm_5v0: fixedregulator-evm5v0 {
- /* Output 1 of TPS43351QDAPRQ1 */
+ /* Output 1 of TPS43351QDAPRQ1 on dra72-evm */
+ /* Output 1 of LM5140QRWGTQ1 on dra71-evm */
compatible = "regulator-fixed";
regulator-name = "evm_5v0";
regulator-min-microvolt = <5000000>;
@@ -40,7 +41,8 @@
};
vsys_3v3: fixedregulator-vsys3v3 {
- /* Output 2 of TPS43351QDAPRQ1 */
+ /* Output 2 of TPS43351QDAPRQ1 on dra72-evm */
+ /* Output 2 of LM5140QRWGTQ1 on dra71-evm */
compatible = "regulator-fixed";
regulator-name = "vsys_3v3";
regulator-min-microvolt = <3300000>;
--
cgit
From e614a121c43446f15e603c4a177031b48338cc77 Mon Sep 17 00:00:00 2001
From: Peter Griffin <peter.griffin@linaro.org>
Date: Fri, 21 Oct 2016 11:08:00 +0200
Subject: ARM: dts: stih407-clocks: Identify critical clocks
Lots of platforms contain clocks which if turned off would prove fatal.
The only way to recover is to restart the board(s). This driver takes
references to clocks which are required to be always-on. The Common
Clk Framework will then take references to them. This way they will
not be turned off during the clk_disabled_unused() procedure.
In this patch we are identifying clocks, which if gated would render
the STiH407 development board unserviceable.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stih407-clock.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi
index 13029c03d7c6..34c119a66f14 100644
--- a/arch/arm/boot/dts/stih407-clock.dtsi
+++ b/arch/arm/boot/dts/stih407-clock.dtsi
@@ -101,6 +101,7 @@
clocks = <&clk_sysin>;
clock-output-names = "clk-s-a0-pll-ofd-0";
+ clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
};
clk_s_a0_flexgen: clk-s-a0-flexgen {
@@ -112,6 +113,7 @@
<&clk_sysin>;
clock-output-names = "clk-ic-lmi0";
+ clock-critical = <CLK_IC_LMI0>;
};
};
@@ -126,6 +128,7 @@
"clk-s-c0-fs0-ch1",
"clk-s-c0-fs0-ch2",
"clk-s-c0-fs0-ch3";
+ clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
};
clk_s_c0: clockgen-c@09103000 {
@@ -139,6 +142,7 @@
clocks = <&clk_sysin>;
clock-output-names = "clk-s-c0-pll0-odf-0";
+ clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
};
clk_s_c0_pll1: clk-s-c0-pll1 {
@@ -194,6 +198,12 @@
"clk-main-disp",
"clk-aux-disp",
"clk-compo-dvp";
+ clock-critical = <CLK_PROC_STFE>,
+ <CLK_ICN_CPU>,
+ <CLK_TX_ICN_DMU>,
+ <CLK_EXT2F_A9>,
+ <CLK_ICN_LMI>,
+ <CLK_ICN_SBC>;
};
};
--
cgit
From 486d379cc3740f9f882b9035035a4d1616ec30f6 Mon Sep 17 00:00:00 2001
From: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Date: Fri, 4 Nov 2016 11:12:00 +0100
Subject: ARM: dts: STiH410-B2260: enable sound card
Enable simple card with HDMI device.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
---
arch/arm/boot/dts/stih410-b2260.dts | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/stih410-b2260.dts b/arch/arm/boot/dts/stih410-b2260.dts
index 511a1098741e..d50242eabae8 100644
--- a/arch/arm/boot/dts/stih410-b2260.dts
+++ b/arch/arm/boot/dts/stih410-b2260.dts
@@ -165,6 +165,9 @@
status = "okay";
};
+ sti_uni_player0: sti-uni-player@8d80000 {
+ status = "okay";
+ };
/* SSC11 to HDMI */
hdmiddc: i2c@9541000 {
/* HDMI V1.3a supports Standard mode only */
@@ -174,6 +177,25 @@
status = "okay";
};
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "STI-B2260";
+ status = "okay";
+
+ simple-audio-card,dai-link@0 {
+ /* DAC */
+ format = "i2s";
+ mclk-fs = <128>;
+ cpu {
+ sound-dai = <&sti_uni_player0>;
+ };
+
+ codec {
+ sound-dai = <&sti_hdmi>;
+ };
+ };
+ };
+
miphy28lp_phy: miphy28lp@9b22000 {
phy_port1: port@9b2a000 {
--
cgit
From 64783ea7de0bff3de77cfdff1ed76428c288faac Mon Sep 17 00:00:00 2001
From: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Date: Fri, 4 Nov 2016 11:44:00 +0100
Subject: ARM: dts: STiHxxx-b2120: change sound card name
Rename sound card to differentiate B2120 and B2260 sound card.
Sound card name is used by alsa-lib to load associated card
configuration file.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
---
arch/arm/boot/dts/stihxxx-b2120.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi
index 313c1f8686d4..4b8f62f89664 100644
--- a/arch/arm/boot/dts/stihxxx-b2120.dtsi
+++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi
@@ -155,7 +155,7 @@
sound {
compatible = "simple-audio-card";
- simple-audio-card,name = "sti audio card";
+ simple-audio-card,name = "STI-B2120";
status = "okay";
simple-audio-card,dai-link@0 {
--
cgit
From adf6eb7774a90bd75e1284710d5a83cd7b707228 Mon Sep 17 00:00:00 2001
From: James Liao <jamesjj.liao@mediatek.com>
Date: Fri, 4 Nov 2016 15:43:07 +0800
Subject: arm: dts: mt2701: Add clock controller device nodes
Add clock controller nodes for MT2701, include topckgen, infracfg,
pericfg and apmixedsys. This patch also add two oscillators that
provide clocks for MT2701.
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
---
arch/arm/boot/dts/mt2701.dtsi | 42 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 18596a2c58a1..c9a8dbf415ff 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -12,8 +12,10 @@
* GNU General Public License for more details.
*/
+#include <dt-bindings/clock/mt2701-clk.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/mt2701-resets.h>
#include "skeleton64.dtsi"
#include "mt2701-pinfunc.h"
@@ -77,6 +79,20 @@
#clock-cells = <0>;
};
+ clk26m: oscillator@0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "clk26m";
+ };
+
+ rtc32k: oscillator@1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32000>;
+ clock-output-names = "rtc32k";
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupt-parent = <&gic>;
@@ -104,6 +120,26 @@
reg = <0 0x10005000 0 0x1000>;
};
+ topckgen: syscon@10000000 {
+ compatible = "mediatek,mt2701-topckgen", "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg: syscon@10001000 {
+ compatible = "mediatek,mt2701-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ pericfg: syscon@10003000 {
+ compatible = "mediatek,mt2701-pericfg", "syscon";
+ reg = <0 0x10003000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
watchdog: watchdog@10007000 {
compatible = "mediatek,mt2701-wdt",
"mediatek,mt6589-wdt";
@@ -128,6 +164,12 @@
reg = <0 0x10200100 0 0x1c>;
};
+ apmixedsys: syscon@10209000 {
+ compatible = "mediatek,mt2701-apmixedsys", "syscon";
+ reg = <0 0x10209000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
gic: interrupt-controller@10211000 {
compatible = "arm,cortex-a7-gic";
interrupt-controller;
--
cgit
From 28d6e3647bd7c869bfc251f9a7e283d78cef5fc5 Mon Sep 17 00:00:00 2001
From: Erin Lo <erin.lo@mediatek.com>
Date: Fri, 4 Nov 2016 15:43:08 +0800
Subject: arm: dts: mt2701: Use real clock for UARTs
We used to use a fixed rate clock for the UARTs. Now that we have clock
support we can associate the correct clocks to the UARTs and drop the
26MHz fixed rate UART clock.
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
---
arch/arm/boot/dts/mt2701.dtsi | 18 ++++++++----------
1 file changed, 8 insertions(+), 10 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index c9a8dbf415ff..7eab6f4c4665 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -73,12 +73,6 @@
#clock-cells = <0>;
};
- uart_clk: dummy26m {
- compatible = "fixed-clock";
- clock-frequency = <26000000>;
- #clock-cells = <0>;
- };
-
clk26m: oscillator@0 {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -186,7 +180,8 @@
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&uart_clk>;
+ clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
+ clock-names = "baud", "bus";
status = "disabled";
};
@@ -195,7 +190,8 @@
"mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x400>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&uart_clk>;
+ clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
+ clock-names = "baud", "bus";
status = "disabled";
};
@@ -204,7 +200,8 @@
"mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x400>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&uart_clk>;
+ clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
+ clock-names = "baud", "bus";
status = "disabled";
};
@@ -213,7 +210,8 @@
"mediatek,mt6577-uart";
reg = <0 0x11005000 0 0x400>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&uart_clk>;
+ clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
+ clock-names = "baud", "bus";
status = "disabled";
};
};
--
cgit
From 43bac4133f405b67857e4c985aecc44a57233bfe Mon Sep 17 00:00:00 2001
From: Martin Sperl <kernel@martin.sperl.org>
Date: Wed, 2 Nov 2016 10:18:23 +0000
Subject: ARM: bcm2835: dts: add thermal node to device-tree of bcm283x
Add the node for the thermal sensor of the bcm2835-soc
to the device tree.
Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
Changelog:
V1 -> V5: generic settings is shared in bcm283x.dtsi, but disabled
moved the compatible string to the SOC specific dtsi
for arm and arm64
V5 -> V6: fix remove 0x prefix from thermal@0x7e212000
Note: there is no arm/boot/dts/bcm2837.dtsi as of now,
so the 32-bit rpi3 dt is not modified.
Signed-off-by: Eric Anholt <eric@anholt.net>
---
arch/arm/boot/dts/bcm2835.dtsi | 6 ++++++
arch/arm/boot/dts/bcm2836.dtsi | 6 ++++++
arch/arm/boot/dts/bcm283x.dtsi | 7 +++++++
3 files changed, 19 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
index a78759e73710..0890d97e674d 100644
--- a/arch/arm/boot/dts/bcm2835.dtsi
+++ b/arch/arm/boot/dts/bcm2835.dtsi
@@ -23,3 +23,9 @@
};
};
};
+
+/* enable thermal sensor with the correct compatible property set */
+&thermal {
+ compatible = "brcm,bcm2835-thermal";
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm2836.dtsi b/arch/arm/boot/dts/bcm2836.dtsi
index 9d0651d8f373..519a44f5d25a 100644
--- a/arch/arm/boot/dts/bcm2836.dtsi
+++ b/arch/arm/boot/dts/bcm2836.dtsi
@@ -76,3 +76,9 @@
interrupt-parent = <&local_intc>;
interrupts = <8>;
};
+
+/* enable thermal sensor with the correct compatible property set */
+&thermal {
+ compatible = "brcm,bcm2836-thermal";
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi
index eae6ab88d1a6..9a44da190897 100644
--- a/arch/arm/boot/dts/bcm283x.dtsi
+++ b/arch/arm/boot/dts/bcm283x.dtsi
@@ -390,6 +390,13 @@
interrupts = <2 14>; /* pwa1 */
};
+ thermal: thermal@7e212000 {
+ compatible = "brcm,bcm2835-thermal";
+ reg = <0x7e212000 0x8>;
+ clocks = <&clocks BCM2835_CLOCK_TSENS>;
+ status = "disabled";
+ };
+
aux: aux@0x7e215000 {
compatible = "brcm,bcm2835-aux";
#clock-cells = <1>;
--
cgit
From 731b26a6ac17f24057c559361c6d0cb7cb79baed Mon Sep 17 00:00:00 2001
From: Linus Walleij <linus.walleij@linaro.org>
Date: Thu, 6 Oct 2016 13:15:02 +0200
Subject: ARM: bcm2835: Add names for the Raspberry Pi GPIO lines
The idea is to give useful names to GPIO lines that an implementer
will be using from userspace, e.g. for maker type projects. These are
user-visible using tools/gpio/lsgpio.c
v2: Major rewrite by anholt: Flatten each GPIO line to a line in the
file for better diffing, prefix all expansion header pins with
"P<number>" or "P5HEADER_P<number>" and drop the mostly-unused
GPIO_GEN<smallnumber> names in favor of GPIO<socgpionumber>, fix
extra '[]' on a couple of lines, fix locations of SD_CARD_DETECT,
CAM_GPIO and STATUS_LED, fix HDMI_HPD polarities, rewrite A+ using
unreleased schematics.
v3: More changes by anholt: Drop P<number> / P5HEADER<number>
prefixes. I had been skeptical about adding them, and was
convinced to drop them by Gottfried (who probably has more
experience with GPIOs in educational contexts than the rest of
us). Also drop [] brackets for "is pinmuxed", which didn't seem
to clarify, and were ambiguous for things like the SPI_*-labeled
pins which may or may not actually be pinmuxed to SPI.
v4: Rename B+'s SDA0/SCL0 to match the other boards, despite the
naming on its schematic.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
---
arch/arm/boot/dts/bcm2835-rpi-a-plus.dts | 65 +++++++++++++++++++++++++++++++
arch/arm/boot/dts/bcm2835-rpi-a.dts | 67 ++++++++++++++++++++++++++++++++
arch/arm/boot/dts/bcm2835-rpi-b-plus.dts | 66 +++++++++++++++++++++++++++++++
arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts | 66 +++++++++++++++++++++++++++++++
arch/arm/boot/dts/bcm2835-rpi-b.dts | 67 ++++++++++++++++++++++++++++++++
5 files changed, 331 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
index 21507c922783..5a22c7965f34 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
@@ -22,6 +22,71 @@
};
&gpio {
+ /*
+ * This is based on the unreleased schematic for the Model A+.
+ *
+ * Legend:
+ * "NC" = not connected (no rail from the SoC)
+ * "FOO" = GPIO line named "FOO" on the schematic
+ * "FOO_N" = GPIO line named "FOO" on schematic, active low
+ */
+ gpio-line-names = "SDA0",
+ "SCL0",
+ "SDA1",
+ "SCL1",
+ "GPIO_GCLK",
+ "GPIO5",
+ "GPIO6",
+ "SPI_CE1_N",
+ "SPI_CE0_N",
+ "SPI_MISO",
+ "SPI_MOSI",
+ "SPI_SCLK",
+ "GPIO12",
+ "GPIO13",
+ /* Serial port */
+ "TXD0",
+ "RXD0",
+ "GPIO16",
+ "GPIO17",
+ "GPIO18",
+ "GPIO19",
+ "GPIO20",
+ "GPIO21",
+ "GPIO22",
+ "GPIO23",
+ "GPIO24",
+ "GPIO25",
+ "GPIO26",
+ "GPIO27",
+ "SDA0",
+ "SCL0",
+ "NC", /* GPIO30 */
+ "NC", /* GPIO31 */
+ "NC", /* GPIO32 */
+ "NC", /* GPIO33 */
+ "NC", /* GPIO34 */
+ "PWR_LOW_N", /* GPIO35 */
+ "NC", /* GPIO36 */
+ "NC", /* GPIO37 */
+ "NC", /* GPIO38 */
+ "NC", /* GPIO39 */
+ "PWM0_OUT", /* GPIO40 */
+ "CAM_GPIO0", /* GPIO41 */
+ "NC", /* GPIO42 */
+ "NC", /* GPIO43 */
+ "NC", /* GPIO44 */
+ "PWM1_OUT", /* GPIO45 */
+ "HDMI_HPD_N",
+ "STATUS_LED",
+ /* Used by SD Card */
+ "SD_CLK_R",
+ "SD_CMD_R",
+ "SD_DATA0_R",
+ "SD_DATA1_R",
+ "SD_DATA2_R",
+ "SD_DATA3_R";
+
pinctrl-0 = <&gpioout &alt0 &i2s_alt0>;
/* I2S interface */
diff --git a/arch/arm/boot/dts/bcm2835-rpi-a.dts b/arch/arm/boot/dts/bcm2835-rpi-a.dts
index 5afba0900449..54f98c59a75d 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-a.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-a.dts
@@ -15,6 +15,73 @@
};
&gpio {
+ /*
+ * Taken from Raspberry-Pi-Rev-1.0-Model-AB-Schematics.pdf
+ * RPI00021 sheet 02
+ *
+ * Legend:
+ * "NC" = not connected (no rail from the SoC)
+ * "FOO" = GPIO line named "FOO" on the schematic
+ * "FOO_N" = GPIO line named "FOO" on schematic, active low
+ */
+ gpio-line-names = "SDA0",
+ "SCL0",
+ "SDA1",
+ "SCL1",
+ "GPIO_GCLK",
+ "CAM_CLK",
+ "LAN_RUN",
+ "SPI_CE1_N",
+ "SPI_CE0_N",
+ "SPI_MISO",
+ "SPI_MOSI",
+ "SPI_SCLK",
+ "NC", /* GPIO12 */
+ "NC", /* GPIO13 */
+ /* Serial port */
+ "TXD0",
+ "RXD0",
+ "STATUS_LED_N",
+ "GPIO17",
+ "GPIO18",
+ "NC", /* GPIO19 */
+ "NC", /* GPIO20 */
+ "GPIO21",
+ "GPIO22",
+ "GPIO23",
+ "GPIO24",
+ "GPIO25",
+ "NC", /* GPIO26 */
+ "CAM_GPIO",
+ /* Binary number representing build/revision */
+ "CONFIG0",
+ "CONFIG1",
+ "CONFIG2",
+ "CONFIG3",
+ "NC", /* GPIO32 */
+ "NC", /* GPIO33 */
+ "NC", /* GPIO34 */
+ "NC", /* GPIO35 */
+ "NC", /* GPIO36 */
+ "NC", /* GPIO37 */
+ "NC", /* GPIO38 */
+ "NC", /* GPIO39 */
+ "PWM0_OUT",
+ "NC", /* GPIO41 */
+ "NC", /* GPIO42 */
+ "NC", /* GPIO43 */
+ "NC", /* GPIO44 */
+ "PWM1_OUT",
+ "HDMI_HPD_P",
+ "SD_CARD_DET",
+ /* Used by SD Card */
+ "SD_CLK_R",
+ "SD_CMD_R",
+ "SD_DATA0_R",
+ "SD_DATA1_R",
+ "SD_DATA2_R",
+ "SD_DATA3_R";
+
pinctrl-0 = <&gpioout &alt0 &i2s_alt2>;
/* I2S interface */
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
index 38f66aa244fe..b67587e6cbef 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
@@ -23,6 +23,72 @@
};
&gpio {
+ /*
+ * Taken from Raspberry-Pi-B-Plus-V1.2-Schematics.pdf
+ * RPI-BPLUS sheet 1
+ *
+ * Legend:
+ * "NC" = not connected (no rail from the SoC)
+ * "FOO" = GPIO line named "FOO" on the schematic
+ * "FOO_N" = GPIO line named "FOO" on schematic, active low
+ */
+ gpio-line-names = "SDA0",
+ "SCL0",
+ "SDA1",
+ "SCL1",
+ "GPIO_GCLK",
+ "GPIO5",
+ "GPIO6",
+ "SPI_CE1_N",
+ "SPI_CE0_N",
+ "SPI_MISO",
+ "SPI_MOSI",
+ "SPI_SCLK",
+ "GPIO12",
+ "GPIO13",
+ /* Serial port */
+ "TXD0",
+ "RXD0",
+ "GPIO16",
+ "GPIO17",
+ "GPIO18",
+ "GPIO19",
+ "GPIO20",
+ "GPIO21",
+ "GPIO22",
+ "GPIO23",
+ "GPIO24",
+ "GPIO25",
+ "GPIO26",
+ "GPIO27",
+ "SDA0",
+ "SCL0",
+ "NC", /* GPIO30 */
+ "LAN_RUN", /* GPIO31 */
+ "CAM_GPIO1", /* GPIO32 */
+ "NC", /* GPIO33 */
+ "NC", /* GPIO34 */
+ "PWR_LOW_N", /* GPIO35 */
+ "NC", /* GPIO36 */
+ "NC", /* GPIO37 */
+ "NC", /* GPIO38 */
+ "NC", /* GPIO39 */
+ "PWM0_OUT", /* GPIO40 */
+ "CAM_GPIO0", /* GPIO41 */
+ "NC", /* GPIO42 */
+ "NC", /* GPIO43 */
+ "ETHCLK", /* GPIO44 */
+ "PWM1_OUT", /* GPIO45 */
+ "HDMI_HPD_N",
+ "STATUS_LED",
+ /* Used by SD Card */
+ "SD_CLK_R",
+ "SD_CMD_R",
+ "SD_DATA0_R",
+ "SD_DATA1_R",
+ "SD_DATA2_R",
+ "SD_DATA3_R";
+
pinctrl-0 = <&gpioout &alt0 &i2s_alt0>;
/* I2S interface */
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts
index 75e045aba7ce..4133bc2cd9be 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts
@@ -16,6 +16,72 @@
};
&gpio {
+ /*
+ * Taken from Raspberry-Pi-Rev-2.0-Model-AB-Schematics.pdf
+ * RPI00022 sheet 02
+ *
+ * Legend:
+ * "NC" = not connected (no rail from the SoC)
+ * "FOO" = GPIO line named "FOO" on the schematic
+ * "FOO_N" = GPIO line named "FOO" on schematic, active low
+ */
+ gpio-line-names = "SDA0",
+ "SCL0",
+ "SDA1",
+ "SCL1",
+ "GPIO_GCLK",
+ "CAM_CLK",
+ "LAN_RUN",
+ "SPI_CE1_N",
+ "SPI_CE0_N",
+ "SPI_MISO",
+ "SPI_MOSI",
+ "SPI_SCLK",
+ "NC", /* GPIO12 */
+ "NC", /* GPIO13 */
+ /* Serial port */
+ "TXD0",
+ "RXD0",
+ "STATUS_LED_N",
+ "GPIO17",
+ "GPIO18",
+ "NC", /* GPIO19 */
+ "NC", /* GPIO20 */
+ "CAM_GPIO",
+ "GPIO22",
+ "GPIO23",
+ "GPIO24",
+ "GPIO25",
+ "NC", /* GPIO26 */
+ "GPIO27",
+ "GPIO28",
+ "GPIO29",
+ "GPIO30",
+ "GPIO31",
+ "NC", /* GPIO32 */
+ "NC", /* GPIO33 */
+ "NC", /* GPIO34 */
+ "NC", /* GPIO35 */
+ "NC", /* GPIO36 */
+ "NC", /* GPIO37 */
+ "NC", /* GPIO38 */
+ "NC", /* GPIO39 */
+ "PWM0_OUT",
+ "NC", /* GPIO41 */
+ "NC", /* GPIO42 */
+ "NC", /* GPIO43 */
+ "NC", /* GPIO44 */
+ "PWM1_OUT",
+ "HDMI_HPD_P",
+ "SD_CARD_DET",
+ /* Used by SD Card */
+ "SD_CLK_R",
+ "SD_CMD_R",
+ "SD_DATA0_R",
+ "SD_DATA1_R",
+ "SD_DATA2_R",
+ "SD_DATA3_R";
+
pinctrl-0 = <&gpioout &alt0 &i2s_alt2>;
/* I2S interface */
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts
index 76a254b3219a..71f50e16c646 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts
@@ -16,6 +16,73 @@
};
&gpio {
+ /*
+ * Taken from Raspberry-Pi-Rev-1.0-Model-AB-Schematics.pdf
+ * RPI00021 sheet 02
+ *
+ * Legend:
+ * "NC" = not connected (no rail from the SoC)
+ * "FOO" = GPIO line named "FOO" on the schematic
+ * "FOO_N" = GPIO line named "FOO" on schematic, active low
+ */
+ gpio-line-names = "SDA0",
+ "SCL0",
+ "SDA1",
+ "SCL1",
+ "GPIO_GCLK",
+ "CAM_CLK",
+ "LAN_RUN",
+ "SPI_CE1_N",
+ "SPI_CE0_N",
+ "SPI_MISO",
+ "SPI_MOSI",
+ "SPI_SCLK",
+ "NC", /* GPIO12 */
+ "NC", /* GPIO13 */
+ /* Serial port */
+ "TXD0",
+ "RXD0",
+ "STATUS_LED_N",
+ "GPIO17",
+ "GPIO18",
+ "NC", /* GPIO19 */
+ "NC", /* GPIO20 */
+ "GPIO21",
+ "GPIO22",
+ "GPIO23",
+ "GPIO24",
+ "GPIO25",
+ "NC", /* GPIO26 */
+ "CAM_GPIO",
+ /* Binary number representing build/revision */
+ "CONFIG0",
+ "CONFIG1",
+ "CONFIG2",
+ "CONFIG3",
+ "NC", /* GPIO32 */
+ "NC", /* GPIO33 */
+ "NC", /* GPIO34 */
+ "NC", /* GPIO35 */
+ "NC", /* GPIO36 */
+ "NC", /* GPIO37 */
+ "NC", /* GPIO38 */
+ "NC", /* GPIO39 */
+ "PWM0_OUT",
+ "NC", /* GPIO41 */
+ "NC", /* GPIO42 */
+ "NC", /* GPIO43 */
+ "NC", /* GPIO44 */
+ "PWM1_OUT",
+ "HDMI_HPD_P",
+ "SD_CARD_DET",
+ /* Used by SD Card */
+ "SD_CLK_R",
+ "SD_CMD_R",
+ "SD_DATA0_R",
+ "SD_DATA1_R",
+ "SD_DATA2_R",
+ "SD_DATA3_R";
+
pinctrl-0 = <&gpioout &alt0>;
};
--
cgit
From 8df0547fb11f1f74e8e33905033d7ecae333d6e2 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Mon, 19 Sep 2016 23:40:41 +0200
Subject: ARM: dts: mxs: Add new M28EVK manufacturer compat
The board is now manufactured by Aries Embedded GmbH, update compat string.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/imx28-m28.dtsi | 4 ++--
arch/arm/boot/dts/imx28-m28evk.dts | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/imx28-m28.dtsi b/arch/arm/boot/dts/imx28-m28.dtsi
index 214bb1506b53..a69856e41ba4 100644
--- a/arch/arm/boot/dts/imx28-m28.dtsi
+++ b/arch/arm/boot/dts/imx28-m28.dtsi
@@ -12,8 +12,8 @@
#include "imx28.dtsi"
/ {
- model = "DENX M28";
- compatible = "denx,m28", "fsl,imx28";
+ model = "Aries/DENX M28";
+ compatible = "aries,m28", "denx,m28", "fsl,imx28";
memory {
reg = <0x40000000 0x08000000>;
diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts
index 8d04e57039bc..dbfb8aab505f 100644
--- a/arch/arm/boot/dts/imx28-m28evk.dts
+++ b/arch/arm/boot/dts/imx28-m28evk.dts
@@ -13,8 +13,8 @@
#include "imx28-m28.dtsi"
/ {
- model = "DENX M28EVK";
- compatible = "denx,m28evk", "fsl,imx28";
+ model = "Aries/DENX M28EVK";
+ compatible = "aries,m28evk", "denx,m28evk", "fsl,imx28";
apb@80000000 {
apbh@80000000 {
--
cgit
From 9827429132752d8e18fd062f594dfd7d1e1a6312 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Mon, 19 Sep 2016 23:40:42 +0200
Subject: ARM: dts: mx5: Add new M53EVK manufacturer compat
The board is now manufactured by Aries Embedded GmbH, update compat string.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/imx53-m53.dtsi | 4 ++--
arch/arm/boot/dts/imx53-m53evk.dts | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/imx53-m53.dtsi b/arch/arm/boot/dts/imx53-m53.dtsi
index d259f57bfd98..ec390aa562c3 100644
--- a/arch/arm/boot/dts/imx53-m53.dtsi
+++ b/arch/arm/boot/dts/imx53-m53.dtsi
@@ -12,8 +12,8 @@
#include "imx53.dtsi"
/ {
- model = "DENX M53";
- compatible = "denx,imx53-m53", "fsl,imx53";
+ model = "Aries/DENX M53";
+ compatible = "aries,imx53-m53", "denx,imx53-m53", "fsl,imx53";
memory {
reg = <0x70000000 0x20000000>,
diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts
index dcee1e0f968f..4347a321c782 100644
--- a/arch/arm/boot/dts/imx53-m53evk.dts
+++ b/arch/arm/boot/dts/imx53-m53evk.dts
@@ -13,8 +13,8 @@
#include "imx53-m53.dtsi"
/ {
- model = "DENX M53EVK";
- compatible = "denx,imx53-m53evk", "fsl,imx53";
+ model = "Aries/DENX M53EVK";
+ compatible = "aries,imx53-m53evk", "denx,imx53-m53evk", "fsl,imx53";
display1: display@di1 {
compatible = "fsl,imx-parallel-display";
--
cgit
From 841310d00a76800a8407ee214eb7242541aac178 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@nxp.com>
Date: Tue, 1 Nov 2016 15:38:12 -0200
Subject: ARM: dts: imx6sx-udoo: Add board specific compatible strings
Add a compatible entry for the specific board versions.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts | 2 +-
arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts | 2 +-
arch/arm/boot/dts/imx6sx-udoo-neo-full.dts | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts b/arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts
index 0b888789efc6..0c1fc1a8f913 100644
--- a/arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts
+++ b/arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts
@@ -46,7 +46,7 @@
/ {
model = "UDOO Neo Basic";
- compatible = "fsl,imx6sx";
+ compatible = "udoo,neobasic", "fsl,imx6sx";
memory {
reg = <0x80000000 0x20000000>;
diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts b/arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts
index d6fdd17cd3ac..5d6c2274ee2b 100644
--- a/arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts
+++ b/arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts
@@ -46,7 +46,7 @@
/ {
model = "UDOO Neo Extended";
- compatible = "fsl,imx6sx";
+ compatible = "udoo,neoextended", "fsl,imx6sx";
memory {
reg = <0x80000000 0x40000000>;
diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo-full.dts b/arch/arm/boot/dts/imx6sx-udoo-neo-full.dts
index d8c3577c9dd5..653ceb29e28b 100644
--- a/arch/arm/boot/dts/imx6sx-udoo-neo-full.dts
+++ b/arch/arm/boot/dts/imx6sx-udoo-neo-full.dts
@@ -46,7 +46,7 @@
/ {
model = "UDOO Neo Full";
- compatible = "fsl,imx6sx";
+ compatible = "udoo,neofull", "fsl,imx6sx";
memory {
reg = <0x80000000 0x40000000>;
--
cgit
From c4479f6f57a0821aae4f6ab6a91a23625d6b35a0 Mon Sep 17 00:00:00 2001
From: Frank Li <Frank.Li@nxp.com>
Date: Mon, 7 Nov 2016 11:30:49 -0600
Subject: ARM: dts: add new compatible string for i.MX6QP mmdc
MMDC has a slightly different programming model between imx6q and imx6qp
in terms of perf support, it's exactly same for suspend support, so we
have fsl,imx6q-mmdc here to save patching suspend driver with the new
compatible.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/imx6qp.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/imx6qp.dtsi b/arch/arm/boot/dts/imx6qp.dtsi
index 886dbf2eca49..e0fdd0fda361 100644
--- a/arch/arm/boot/dts/imx6qp.dtsi
+++ b/arch/arm/boot/dts/imx6qp.dtsi
@@ -85,5 +85,12 @@
pcie: pcie@0x01000000 {
compatible = "fsl,imx6qp-pcie", "snps,dw-pcie";
};
+
+ aips-bus@02100000 {
+ mmdc0: mmdc@021b0000 { /* MMDC0 */
+ compatible = "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc";
+ reg = <0x021b0000 0x4000>;
+ };
+ };
};
};
--
cgit
From 425dd2773ed07d1ba21d4ada0f9a9abc85b75151 Mon Sep 17 00:00:00 2001
From: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Date: Fri, 11 Nov 2016 16:59:39 +0100
Subject: ARM: dts: imx6q-utilite-pro: i2c1 is muxed
It turns out that the i2c1 adapter is connected to a multiplexer
controlled by a gpio line. The first (default) mux option connects
i2c1 to a bus connected to the already known peripherals. The other
one connects the adapter to the ddc pins of the DVI port.
Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/imx6q-utilite-pro.dts | 51 ++++++++++++++++++++++++++-------
1 file changed, 40 insertions(+), 11 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/imx6q-utilite-pro.dts b/arch/arm/boot/dts/imx6q-utilite-pro.dts
index 61990630a748..246979a388a4 100644
--- a/arch/arm/boot/dts/imx6q-utilite-pro.dts
+++ b/arch/arm/boot/dts/imx6q-utilite-pro.dts
@@ -71,6 +71,40 @@
gpio-key,wakeup;
};
};
+
+ i2cmux {
+ compatible = "i2c-mux-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1mux>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mux-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+ i2c-parent = <&i2c1>;
+
+ i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@50 {
+ compatible = "at24,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+
+ em3027: rtc@56 {
+ compatible = "emmicro,em3027";
+ reg = <0x56>;
+ };
+ };
+
+ i2c_dvi_ddc: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
};
&hdmi {
@@ -82,17 +116,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
-
- eeprom@50 {
- compatible = "at24,24c02";
- reg = <0x50>;
- pagesize = <16>;
- };
-
- em3027: rtc@56 {
- compatible = "emmicro,em3027";
- reg = <0x56>;
- };
};
&i2c2 {
@@ -115,6 +138,12 @@
>;
};
+ pinctrl_i2c1mux: i2c1muxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
+ >;
+ };
+
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
--
cgit
From 7f107887d1995c819389f292828097cac4ec4396 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@nxp.com>
Date: Sat, 12 Nov 2016 13:30:35 -0200
Subject: ARM: dts: imx: Remove skeleton.dtsi
As explained by commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark
skeleton.dtsi as deprecated"), including skeleton.dtsi is deprecated.
This fixes the following warning with W=1:
Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/imx1.dtsi | 4 +++-
arch/arm/boot/dts/imx23.dtsi | 4 +++-
arch/arm/boot/dts/imx25.dtsi | 4 +++-
arch/arm/boot/dts/imx27.dtsi | 4 +++-
arch/arm/boot/dts/imx28.dtsi | 4 +++-
arch/arm/boot/dts/imx31.dtsi | 5 +++--
arch/arm/boot/dts/imx35.dtsi | 4 +++-
arch/arm/boot/dts/imx50.dtsi | 4 +++-
arch/arm/boot/dts/imx51.dtsi | 4 +++-
arch/arm/boot/dts/imx53.dtsi | 4 +++-
arch/arm/boot/dts/imx6qdl.dtsi | 5 +++--
arch/arm/boot/dts/imx6sl.dtsi | 4 +++-
arch/arm/boot/dts/imx6sx.dtsi | 4 +++-
arch/arm/boot/dts/imx6ul.dtsi | 4 +++-
arch/arm/boot/dts/imx7s.dtsi | 4 +++-
15 files changed, 45 insertions(+), 17 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/imx1.dtsi b/arch/arm/boot/dts/imx1.dtsi
index 22f5d1db5b31..b792eee3899b 100644
--- a/arch/arm/boot/dts/imx1.dtsi
+++ b/arch/arm/boot/dts/imx1.dtsi
@@ -9,7 +9,6 @@
* http://www.gnu.org/copyleft/gpl.html
*/
-#include "skeleton.dtsi"
#include "imx1-pinfunc.h"
#include <dt-bindings/clock/imx1-clock.h>
@@ -17,6 +16,9 @@
#include <dt-bindings/interrupt-controller/irq.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
gpio0 = &gpio1;
gpio1 = &gpio2;
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 8e1543f7aea7..ac2a9da62b6c 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -9,10 +9,12 @@
* http://www.gnu.org/copyleft/gpl.html
*/
-#include "skeleton.dtsi"
#include "imx23-pinfunc.h"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
interrupt-parent = <&icoll>;
aliases {
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index af6af8741fe5..831d09a28155 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -9,10 +9,12 @@
* http://www.gnu.org/copyleft/gpl.html
*/
-#include "skeleton.dtsi"
#include "imx25-pinfunc.h"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
ethernet0 = &fec;
gpio0 = &gpio1;
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index f818ea483aeb..9d8b5969ee3b 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -9,7 +9,6 @@
* http://www.gnu.org/copyleft/gpl.html
*/
-#include "skeleton.dtsi"
#include "imx27-pinfunc.h"
#include <dt-bindings/clock/imx27-clock.h>
@@ -18,6 +17,9 @@
#include <dt-bindings/interrupt-controller/irq.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
ethernet0 = &fec;
gpio0 = &gpio1;
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 0ad893bf5f43..3aabf65a6a52 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -10,10 +10,12 @@
*/
#include <dt-bindings/gpio/gpio.h>
-#include "skeleton.dtsi"
#include "imx28-pinfunc.h"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
interrupt-parent = <&icoll>;
aliases {
diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi
index 1ce7ae94e7ad..c534c1fd185a 100644
--- a/arch/arm/boot/dts/imx31.dtsi
+++ b/arch/arm/boot/dts/imx31.dtsi
@@ -9,9 +9,10 @@
* http://www.gnu.org/copyleft/gpl.html
*/
-#include "skeleton.dtsi"
-
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
serial0 = &uart1;
serial1 = &uart2;
diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi
index f812d586c5ce..9f40e6229189 100644
--- a/arch/arm/boot/dts/imx35.dtsi
+++ b/arch/arm/boot/dts/imx35.dtsi
@@ -8,10 +8,12 @@
* Free Software Foundation.
*/
-#include "skeleton.dtsi"
#include "imx35-pinfunc.h"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
ethernet0 = &fec;
gpio0 = &gpio1;
diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi
index 92a03bc54f75..fe0221e4cbf7 100644
--- a/arch/arm/boot/dts/imx50.dtsi
+++ b/arch/arm/boot/dts/imx50.dtsi
@@ -11,11 +11,13 @@
* http://www.gnu.org/copyleft/gpl.html
*/
-#include "skeleton.dtsi"
#include "imx50-pinfunc.h"
#include <dt-bindings/clock/imx5-clock.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
ethernet0 = &fec;
gpio0 = &gpio1;
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index d8efdab45f89..33526cade735 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -10,7 +10,6 @@
* http://www.gnu.org/copyleft/gpl.html
*/
-#include "skeleton.dtsi"
#include "imx51-pinfunc.h"
#include <dt-bindings/clock/imx5-clock.h>
#include <dt-bindings/gpio/gpio.h>
@@ -18,6 +17,9 @@
#include <dt-bindings/interrupt-controller/irq.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
ethernet0 = &fec;
gpio0 = &gpio1;
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 88f9e09effdc..ca51dc03e327 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -10,7 +10,6 @@
* http://www.gnu.org/copyleft/gpl.html
*/
-#include "skeleton.dtsi"
#include "imx53-pinfunc.h"
#include <dt-bindings/clock/imx5-clock.h>
#include <dt-bindings/gpio/gpio.h>
@@ -18,6 +17,9 @@
#include <dt-bindings/interrupt-controller/irq.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
ethernet0 = &fec;
gpio0 = &gpio1;
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index d7bed1f8ff1d..53e6e63cbb02 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -13,9 +13,10 @@
#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include "skeleton.dtsi"
-
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
ethernet0 = &fec;
can0 = &can1;
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index c2b28c06e50d..4fd6de29f07d 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -8,11 +8,13 @@
*/
#include <dt-bindings/interrupt-controller/irq.h>
-#include "skeleton.dtsi"
#include "imx6sl-pinfunc.h"
#include <dt-bindings/clock/imx6sl-clock.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
ethernet0 = &fec;
gpio0 = &gpio1;
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index dbc540f5fec5..076a30f9bcae 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -11,9 +11,11 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "imx6sx-pinfunc.h"
-#include "skeleton.dtsi"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
can0 = &flexcan1;
can1 = &flexcan2;
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index c5c05fdccc78..39845a7e0463 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -11,9 +11,11 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "imx6ul-pinfunc.h"
-#include "skeleton.dtsi"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
ethernet0 = &fec1;
ethernet1 = &fec2;
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index 0d7d5ac6257b..51dfcc16e4b8 100644
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -46,9 +46,11 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "imx7d-pinfunc.h"
-#include "skeleton.dtsi"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
gpio0 = &gpio1;
gpio1 = &gpio2;
--
cgit
From e5a31718d69cc5484100beedbfcee13554aa7140 Mon Sep 17 00:00:00 2001
From: Paweł Jarosz <paweljarosz3691@gmail.com>
Date: Mon, 14 Nov 2016 07:54:00 +0100
Subject: ARM: dts: rockchip: fix TSADC reset node for rk3066a
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
This patch fixes incorectly assigned rk3066a TSADC node
Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/boot/dts/rk3066a.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index fc8dcc72b16f..ac46109041d0 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -205,7 +205,7 @@
clock-names = "saradc", "apb_pclk";
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
#io-channel-cells = <1>;
- resets = <&cru SRST_SARADC>;
+ resets = <&cru SRST_TSADC>;
reset-names = "saradc-apb";
status = "disabled";
};
--
cgit
From 8ce0eda30aea4a31de0b39f036d894346ea249ae Mon Sep 17 00:00:00 2001
From: Paweł Jarosz <paweljarosz3691@gmail.com>
Date: Mon, 14 Nov 2016 07:52:06 +0100
Subject: ARM: dts: rockchip: enable dma for uart and mmc on rk3066a
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
DMA controller driver is in good shape these days on rockchip platforms.
So lets enable DMA for uart and mmc.
Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/boot/dts/rk3066a.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index ac46109041d0..e498c362b9e7 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -637,16 +637,25 @@
&mmc0 {
clock-frequency = <50000000>;
+ dmas = <&dmac2 1>;
+ dma-names = "rx-tx";
max-frequency = <50000000>;
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
};
&mmc1 {
+ dmas = <&dmac2 3>;
+ dma-names = "rx-tx";
pinctrl-names = "default";
pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
};
+&emmc {
+ dmas = <&dmac2 4>;
+ dma-names = "rx-tx";
+};
+
&pwm0 {
pinctrl-names = "default";
pinctrl-0 = <&pwm0_out>;
@@ -678,21 +687,29 @@
};
&uart0 {
+ dmas = <&dmac1_s 0>, <&dmac1_s 1>;
+ dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer>;
};
&uart1 {
+ dmas = <&dmac1_s 2>, <&dmac1_s 3>;
+ dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart1_xfer>;
};
&uart2 {
+ dmas = <&dmac2 6>, <&dmac2 7>;
+ dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart2_xfer>;
};
&uart3 {
+ dmas = <&dmac2 8>, <&dmac2 9>;
+ dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart3_xfer>;
};
--
cgit
From 4743ced991308d473f0d87f626c833b8731a7290 Mon Sep 17 00:00:00 2001
From: Sanchayan Maity <maitysanchayan@gmail.com>
Date: Mon, 14 Nov 2016 18:07:01 +0530
Subject: ARM: dts: vfxxx: Enable DMA for DSPI2 and DSPI3
Enable DMA for DSPI2 and DSPI3 on Vybrid.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/vfxxx.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
index 000550f7b9dd..e9d28474c26a 100644
--- a/arch/arm/boot/dts/vfxxx.dtsi
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -573,6 +573,9 @@
clocks = <&clks VF610_CLK_DSPI2>;
clock-names = "dspi";
spi-num-chipselects = <2>;
+ dmas = <&edma1 0 10>,
+ <&edma1 0 11>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -585,6 +588,9 @@
clocks = <&clks VF610_CLK_DSPI3>;
clock-names = "dspi";
spi-num-chipselects = <2>;
+ dmas = <&edma1 0 12>,
+ <&edma1 0 13>;
+ dma-names = "rx", "tx";
status = "disabled";
};
--
cgit
From b662a9dd8a1a03e6e2d61e74d3e7a08400edefb7 Mon Sep 17 00:00:00 2001
From: Sudeep Holla <sudeep.holla@arm.com>
Date: Mon, 14 Nov 2016 15:44:08 +0000
Subject: ARM: dts: at91: replace gpio-key,wakeup with wakeup-source for
sam9260ek
Though the keyboard driver for GPIO buttons(gpio-keys) will continue to
check for/support the legacy "gpio-key,wakeup" boolean property to
enable gpio buttons as wakeup source, "wakeup-source" is the new
standard binding.
This patch replaces the legacy "gpio-key,wakeup" with the unified
"wakeup-source" property in order to avoid any further copy-paste
duplication.
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/boot/dts/at91sam9260ek.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/at91sam9260ek.dts b/arch/arm/boot/dts/at91sam9260ek.dts
index 2c87f58448e7..b2578feceb08 100644
--- a/arch/arm/boot/dts/at91sam9260ek.dts
+++ b/arch/arm/boot/dts/at91sam9260ek.dts
@@ -174,14 +174,14 @@
label = "Button 3";
gpios = <&pioA 30 GPIO_ACTIVE_LOW>;
linux,code = <0x103>;
- gpio-key,wakeup;
+ wakeup-source;
};
btn4 {
label = "Button 4";
gpios = <&pioA 31 GPIO_ACTIVE_LOW>;
linux,code = <0x104>;
- gpio-key,wakeup;
+ wakeup-source;
};
};
--
cgit
From 70e105ad35ac4b9445b5d66ef8a44273f8868084 Mon Sep 17 00:00:00 2001
From: Sudeep Holla <sudeep.holla@arm.com>
Date: Mon, 14 Nov 2016 15:44:09 +0000
Subject: ARM: dts: imx6q: replace gpio-key,wakeup with wakeup-source for
Utilite Pro
Though the keyboard driver for GPIO buttons(gpio-keys) will continue to
check for/support the legacy "gpio-key,wakeup" boolean property to
enable gpio buttons as wakeup source, "wakeup-source" is the new
standard binding.
This patch replaces the legacy "gpio-key,wakeup" with the unified
"wakeup-source" property in order to avoid any further copy-paste
duplication.
Cc: Sascha Hauer <kernel@pengutronix.de>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/imx6q-utilite-pro.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/imx6q-utilite-pro.dts b/arch/arm/boot/dts/imx6q-utilite-pro.dts
index 246979a388a4..22009947cebc 100644
--- a/arch/arm/boot/dts/imx6q-utilite-pro.dts
+++ b/arch/arm/boot/dts/imx6q-utilite-pro.dts
@@ -68,7 +68,7 @@
label = "Power Button";
gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
- gpio-key,wakeup;
+ wakeup-source;
};
};
--
cgit
From c201369d4aa5f05b8a37d6d1eeabf248c7086454 Mon Sep 17 00:00:00 2001
From: Peter Chen <peter.chen@nxp.com>
Date: Mon, 14 Nov 2016 15:04:20 +0800
Subject: ARM: dts: imx6ull: add imx6ull support
It is the 10th processor in the well-known imx6 series, and derived
from imx6ul but cost optimized. The more information about imx6ull
can be found at:
http://www.nxp.com/products/microcontrollers-and-processors/
arm-processors/i.mx-applications-processors/i.mx-6-processors
/i.mx6qp/i.mx-6ull-single-core-processor-with-arm-cortex-a7-core
:i.MX6ULL
imx6ul.dtsi is the SoC common stuff for both imx6ul and imx6ull;
imx6ul-14x14-evk.dts is the board common stuff for both imx6ul
and imx6ull 14x14 evk. In this patch, for SoC part, the
imx6ull.dtsi includes imx6ul.dtsi; for board part, imx6ull-14x14-evk.dts
includes imx6ul-14x14-evk.dts.
Signed-off-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/imx6ull-14x14-evk.dts | 52 ++++++++++++++++++++++++++++++
arch/arm/boot/dts/imx6ull-pinfunc.h | 56 +++++++++++++++++++++++++++++++++
arch/arm/boot/dts/imx6ull.dtsi | 43 +++++++++++++++++++++++++
4 files changed, 153 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/imx6ull-14x14-evk.dts
create mode 100644 arch/arm/boot/dts/imx6ull-pinfunc.h
create mode 100644 arch/arm/boot/dts/imx6ull.dtsi
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5363b994f513..cb5e36e4b3dd 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -431,7 +431,8 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-pico-hobbit.dtb \
imx6ul-tx6ul-0010.dtb \
imx6ul-tx6ul-0011.dtb \
- imx6ul-tx6ul-mainboard.dtb
+ imx6ul-tx6ul-mainboard.dtb \
+ imx6ull-14x14-evk.dtb
dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-cl-som-imx7.dtb \
imx7d-colibri-eval-v3.dtb \
diff --git a/arch/arm/boot/dts/imx6ull-14x14-evk.dts b/arch/arm/boot/dts/imx6ull-14x14-evk.dts
new file mode 100644
index 000000000000..db5bc076e1cc
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-14x14-evk.dts
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "imx6ul-14x14-evk.dts"
+
+/ {
+ model = "Freescale i.MX6 UlltraLite 14x14 EVK Board";
+ compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
+};
+
+&clks {
+ assigned-clocks = <&clks IMX6UL_CLK_PLL3_PFD2>;
+ assigned-clock-rates = <320000000>;
+};
diff --git a/arch/arm/boot/dts/imx6ull-pinfunc.h b/arch/arm/boot/dts/imx6ull-pinfunc.h
new file mode 100644
index 000000000000..118202336691
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-pinfunc.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __DTS_IMX6ULL_PINFUNC_H
+#define __DTS_IMX6ULL_PINFUNC_H
+
+#include "imx6ul-pinfunc.h"
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX6ULL_PAD_ENET2_RX_DATA0__EPDC_SDDO08 0x00E4 0x0370 0x0000 0x9 0x0
+#define MX6ULL_PAD_ENET2_RX_DATA1__EPDC_SDDO09 0x00E8 0x0374 0x0000 0x9 0x0
+#define MX6ULL_PAD_ENET2_RX_EN__EPDC_SDDO10 0x00EC 0x0378 0x0000 0x9 0x0
+#define MX6ULL_PAD_ENET2_TX_DATA0__EPDC_SDDO11 0x00F0 0x037C 0x0000 0x9 0x0
+#define MX6ULL_PAD_ENET2_TX_DATA1__EPDC_SDDO12 0x00F4 0x0380 0x0000 0x9 0x0
+#define MX6ULL_PAD_ENET2_TX_EN__EPDC_SDDO13 0x00F8 0x0384 0x0000 0x9 0x0
+#define MX6ULL_PAD_ENET2_TX_CLK__EPDC_SDDO14 0x00FC 0x0388 0x0000 0x9 0x0
+#define MX6ULL_PAD_ENET2_RX_ER__EPDC_SDDO15 0x0100 0x038C 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_CLK__EPDC_SDCLK 0x0104 0x0390 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_ENABLE__EPDC_SDLE 0x0108 0x0394 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_HSYNC__EPDC_SDOE 0x010C 0x0398 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_VSYNC__EPDC_SDCE0 0x0110 0x039C 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_RESET__EPDC_GDOE 0x0114 0x03A0 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_DATA00__EPDC_SDDO00 0x0118 0x03A4 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_DATA01__EPDC_SDDO01 0x011C 0x03A8 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_DATA02__EPDC_SDDO02 0x0120 0x03AC 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_DATA03__EPDC_SDDO03 0x0124 0x03B0 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_DATA04__EPDC_SDDO04 0x0128 0x03B4 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_DATA05__EPDC_SDDO05 0x012C 0x03B8 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_DATA06__EPDC_SDDO06 0x0130 0x03BC 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_DATA07__EPDC_SDDO07 0x0134 0x03C0 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_DATA14__EPDC_SDSHR 0x0150 0x03DC 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_DATA15__EPDC_GDRL 0x0154 0x03E0 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_DATA16__EPDC_GDCLK 0x0158 0x03E4 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_DATA17__EPDC_GDSP 0x015C 0x03E8 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_DATA21__EPDC_SDCE1 0x016C 0x03F8 0x0000 0x9 0x0
+#define MX6ULL_PAD_CSI_MCLK__ESAI_TX3_RX2 0x01D4 0x0460 0x0000 0x9 0x0
+#define MX6ULL_PAD_CSI_PIXCLK__ESAI_TX2_RX3 0x01D8 0x0464 0x0000 0x9 0x0
+#define MX6ULL_PAD_CSI_VSYNC__ESAI_TX4_RX1 0x01DC 0x0468 0x0000 0x9 0x0
+#define MX6ULL_PAD_CSI_HSYNC__ESAI_TX1 0x01E0 0x046C 0x0000 0x9 0x0
+#define MX6ULL_PAD_CSI_DATA00__ESAI_TX_HF_CLK 0x01E4 0x0470 0x0000 0x9 0x0
+#define MX6ULL_PAD_CSI_DATA01__ESAI_RX_HF_CLK 0x01E8 0x0474 0x0000 0x9 0x0
+#define MX6ULL_PAD_CSI_DATA02__ESAI_RX_FS 0x01EC 0x0478 0x0000 0x9 0x0
+#define MX6ULL_PAD_CSI_DATA03__ESAI_RX_CLK 0x01F0 0x047C 0x0000 0x9 0x0
+#define MX6ULL_PAD_CSI_DATA04__ESAI_TX_FS 0x01F4 0x0480 0x0000 0x9 0x0
+#define MX6ULL_PAD_CSI_DATA05__ESAI_TX_CLK 0x01F8 0x0484 0x0000 0x9 0x0
+#define MX6ULL_PAD_CSI_DATA06__ESAI_TX5_RX0 0x01FC 0x0488 0x0000 0x9 0x0
+#define MX6ULL_PAD_CSI_DATA07__ESAI_T0 0x0200 0x048C 0x0000 0x9 0x0
+
+#endif /* __DTS_IMX6ULL_PINFUNC_H */
diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi
new file mode 100644
index 000000000000..dee8ab8135e1
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull.dtsi
@@ -0,0 +1,43 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "imx6ul.dtsi"
+#include "imx6ull-pinfunc.h"
--
cgit
From ca34ab20255d0f5addf64ed2082a2c61a84563db Mon Sep 17 00:00:00 2001
From: Kefeng Wang <wangkefeng.wang@huawei.com>
Date: Mon, 24 Oct 2016 16:31:28 +0800
Subject: ARM: dts: hip01: Remove skeleton.dtsi inclusion
Since commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark skeleton.dtsi
as deprecated"), remove deprecated skeleton.dtsi.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
---
arch/arm/boot/dts/hip01.dtsi | 2 --
1 file changed, 2 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/hip01.dtsi b/arch/arm/boot/dts/hip01.dtsi
index 4e9562f806a2..9d5fd5cfefa6 100644
--- a/arch/arm/boot/dts/hip01.dtsi
+++ b/arch/arm/boot/dts/hip01.dtsi
@@ -11,8 +11,6 @@
* published by the Free Software Foundation.
*/
-#include "skeleton.dtsi"
-
/ {
interrupt-parent = <&gic>;
#address-cells = <1>;
--
cgit
From 4899138fa77269ed4b397b4305fd1b04c0bbb695 Mon Sep 17 00:00:00 2001
From: Kefeng Wang <wangkefeng.wang@huawei.com>
Date: Mon, 24 Oct 2016 16:31:29 +0800
Subject: ARM: dts: hi3620: Remove skeleton.dtsi inclusion
Since commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark skeleton.dtsi
as deprecated"), remove deprecated skeleton.dtsi.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
---
arch/arm/boot/dts/hi3620.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi
index c85d07e6db61..d18a9156b38e 100644
--- a/arch/arm/boot/dts/hi3620.dtsi
+++ b/arch/arm/boot/dts/hi3620.dtsi
@@ -11,10 +11,12 @@
* publishhed by the Free Software Foundation.
*/
-#include "skeleton.dtsi"
#include <dt-bindings/clock/hi3620-clock.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
serial0 = &uart0;
serial1 = &uart1;
--
cgit
From 3b23aabfcd48988179f7c6c2dde01f3356f68213 Mon Sep 17 00:00:00 2001
From: Kefeng Wang <wangkefeng.wang@huawei.com>
Date: Mon, 24 Oct 2016 16:31:30 +0800
Subject: ARM: dts: hisi-x5hd2: Remove skeleton.dtsi inclusion
Since commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark skeleton.dtsi
as deprecated"), remove deprecated skeleton.dtsi.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
---
arch/arm/boot/dts/hisi-x5hd2.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi
index fdcc23d203e5..506fdc10706d 100644
--- a/arch/arm/boot/dts/hisi-x5hd2.dtsi
+++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi
@@ -7,10 +7,12 @@
* publishhed by the Free Software Foundation.
*/
-#include "skeleton.dtsi"
#include <dt-bindings/clock/hix5hd2-clock.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
serial0 = &uart0;
};
--
cgit
From ec2f9b10f33fc7eb8357246feeb6f2bf5fd065d0 Mon Sep 17 00:00:00 2001
From: Alexandre TORGUE <alexandre.torgue@st.com>
Date: Tue, 15 Nov 2016 12:01:57 +0100
Subject: ARM: dts: Add STM32F746 MCU and STM32746g-EVAL board
The STMicrolectornics's STM32F746 MCU has the following main features:
- Cortex-M7 core running up to @216MHz
- 1MB internal flash, 320KBytes internal RAM (+4KB of backup SRAM)
- FMC controller to connect SDRAM, NOR and NAND memories
- Dual mode QSPI
- SD/MMC/SDIO support
- Ethernet controller
- USB OTFG FS & HS controllers
- I2C, SPI, CAN busses support
- Several 16 & 32 bits general purpose timers
- Serial Audio interface
- LCD controller
- HDMI-CEC
- SPDIFRX
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/stm32746g-eval.dts | 96 +++++++++++
arch/arm/boot/dts/stm32f746.dtsi | 304 +++++++++++++++++++++++++++++++++++
3 files changed, 402 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/stm32746g-eval.dts
create mode 100644 arch/arm/boot/dts/stm32f746.dtsi
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index befcd2619902..343dda264403 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -721,7 +721,8 @@ dtb-$(CONFIG_ARCH_STI) += \
dtb-$(CONFIG_ARCH_STM32)+= \
stm32f429-disco.dtb \
stm32f469-disco.dtb \
- stm32429i-eval.dtb
+ stm32429i-eval.dtb \
+ stm32746g-eval.dtb
dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-a1000.dtb \
sun4i-a10-ba10-tvbox.dtb \
diff --git a/arch/arm/boot/dts/stm32746g-eval.dts b/arch/arm/boot/dts/stm32746g-eval.dts
new file mode 100644
index 000000000000..aa03fac1ec55
--- /dev/null
+++ b/arch/arm/boot/dts/stm32746g-eval.dts
@@ -0,0 +1,96 @@
+/*
+ * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "stm32f746.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "STMicroelectronics STM32746g-EVAL board";
+ compatible = "st,stm32746g-eval", "st,stm32f746";
+
+ chosen {
+ bootargs = "root=/dev/ram";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ reg = <0xc0000000 0x2000000>;
+ };
+
+ aliases {
+ serial0 = &usart1;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ green {
+ gpios = <&gpiof 10 1>;
+ linux,default-trigger = "heartbeat";
+ };
+ red {
+ gpios = <&gpiob 7 1>;
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+ button@0 {
+ label = "Wake up";
+ linux,code = <KEY_WAKEUP>;
+ gpios = <&gpioc 13 0>;
+ };
+ };
+};
+
+&clk_hse {
+ clock-frequency = <25000000>;
+};
+
+&usart1 {
+ pinctrl-0 = <&usart1_pins_a>;
+ pinctrl-names = "default";
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi
new file mode 100644
index 000000000000..f321ffe87144
--- /dev/null
+++ b/arch/arm/boot/dts/stm32f746.dtsi
@@ -0,0 +1,304 @@
+/*
+ * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "skeleton.dtsi"
+#include "armv7-m.dtsi"
+#include <dt-bindings/pinctrl/stm32f746-pinfunc.h>
+
+/ {
+ clocks {
+ clk_hse: clk-hse {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+ };
+
+ soc {
+ timer2: timer@40000000 {
+ compatible = "st,stm32-timer";
+ reg = <0x40000000 0x400>;
+ interrupts = <28>;
+ clocks = <&rcc 0 128>;
+ status = "disabled";
+ };
+
+ timer3: timer@40000400 {
+ compatible = "st,stm32-timer";
+ reg = <0x40000400 0x400>;
+ interrupts = <29>;
+ clocks = <&rcc 0 129>;
+ status = "disabled";
+ };
+
+ timer4: timer@40000800 {
+ compatible = "st,stm32-timer";
+ reg = <0x40000800 0x400>;
+ interrupts = <30>;
+ clocks = <&rcc 0 130>;
+ status = "disabled";
+ };
+
+ timer5: timer@40000c00 {
+ compatible = "st,stm32-timer";
+ reg = <0x40000c00 0x400>;
+ interrupts = <50>;
+ clocks = <&rcc 0 131>;
+ };
+
+ timer6: timer@40001000 {
+ compatible = "st,stm32-timer";
+ reg = <0x40001000 0x400>;
+ interrupts = <54>;
+ clocks = <&rcc 0 132>;
+ status = "disabled";
+ };
+
+ timer7: timer@40001400 {
+ compatible = "st,stm32-timer";
+ reg = <0x40001400 0x400>;
+ interrupts = <55>;
+ clocks = <&rcc 0 133>;
+ status = "disabled";
+ };
+
+ usart2: serial@40004400 {
+ compatible = "st,stm32f7-usart", "st,stm32f7-uart";
+ reg = <0x40004400 0x400>;
+ interrupts = <38>;
+ clocks = <&rcc 0 145>;
+ status = "disabled";
+ };
+
+ usart3: serial@40004800 {
+ compatible = "st,stm32f7-usart", "st,stm32f7-uart";
+ reg = <0x40004800 0x400>;
+ interrupts = <39>;
+ clocks = <&rcc 0 146>;
+ status = "disabled";
+ };
+
+ usart4: serial@40004c00 {
+ compatible = "st,stm32f7-uart";
+ reg = <0x40004c00 0x400>;
+ interrupts = <52>;
+ clocks = <&rcc 0 147>;
+ status = "disabled";
+ };
+
+ usart5: serial@40005000 {
+ compatible = "st,stm32f7-uart";
+ reg = <0x40005000 0x400>;
+ interrupts = <53>;
+ clocks = <&rcc 0 148>;
+ status = "disabled";
+ };
+
+ usart7: serial@40007800 {
+ compatible = "st,stm32f7-usart", "st,stm32f7-uart";
+ reg = <0x40007800 0x400>;
+ interrupts = <82>;
+ clocks = <&rcc 0 158>;
+ status = "disabled";
+ };
+
+ usart8: serial@40007c00 {
+ compatible = "st,stm32f7-usart", "st,stm32f7-uart";
+ reg = <0x40007c00 0x400>;
+ interrupts = <83>;
+ clocks = <&rcc 0 159>;
+ status = "disabled";
+ };
+
+ usart1: serial@40011000 {
+ compatible = "st,stm32f7-usart", "st,stm32f7-uart";
+ reg = <0x40011000 0x400>;
+ interrupts = <37>;
+ clocks = <&rcc 0 164>;
+ status = "disabled";
+ };
+
+ usart6: serial@40011400 {
+ compatible = "st,stm32f7-usart", "st,stm32f7-uart";
+ reg = <0x40011400 0x400>;
+ interrupts = <71>;
+ clocks = <&rcc 0 165>;
+ status = "disabled";
+ };
+
+ syscfg: system-config@40013800 {
+ compatible = "syscon";
+ reg = <0x40013800 0x400>;
+ };
+
+ exti: interrupt-controller@40013c00 {
+ compatible = "st,stm32-exti";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x40013C00 0x400>;
+ interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
+ };
+
+ pin-controller {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stm32f746-pinctrl";
+ ranges = <0 0x40020000 0x3000>;
+ interrupt-parent = <&exti>;
+ st,syscfg = <&syscfg 0x8>;
+ pins-are-numbered;
+
+ gpioa: gpio@40020000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x0 0x400>;
+ clocks = <&rcc 0 256>;
+ st,bank-name = "GPIOA";
+ };
+
+ gpiob: gpio@40020400 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x400 0x400>;
+ clocks = <&rcc 0 257>;
+ st,bank-name = "GPIOB";
+ };
+
+ gpioc: gpio@40020800 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x800 0x400>;
+ clocks = <&rcc 0 258>;
+ st,bank-name = "GPIOC";
+ };
+
+ gpiod: gpio@40020c00 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0xc00 0x400>;
+ clocks = <&rcc 0 259>;
+ st,bank-name = "GPIOD";
+ };
+
+ gpioe: gpio@40021000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x1000 0x400>;
+ clocks = <&rcc 0 260>;
+ st,bank-name = "GPIOE";
+ };
+
+ gpiof: gpio@40021400 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x1400 0x400>;
+ clocks = <&rcc 0 261>;
+ st,bank-name = "GPIOF";
+ };
+
+ gpiog: gpio@40021800 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x1800 0x400>;
+ clocks = <&rcc 0 262>;
+ st,bank-name = "GPIOG";
+ };
+
+ gpioh: gpio@40021c00 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x1c00 0x400>;
+ clocks = <&rcc 0 263>;
+ st,bank-name = "GPIOH";
+ };
+
+ gpioi: gpio@40022000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x2000 0x400>;
+ clocks = <&rcc 0 264>;
+ st,bank-name = "GPIOI";
+ };
+
+ gpioj: gpio@40022400 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x2400 0x400>;
+ clocks = <&rcc 0 265>;
+ st,bank-name = "GPIOJ";
+ };
+
+ gpiok: gpio@40022800 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x2800 0x400>;
+ clocks = <&rcc 0 266>;
+ st,bank-name = "GPIOK";
+ };
+
+ usart1_pins_a: usart1@0 {
+ pins1 {
+ pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32F746_PA10_FUNC_USART1_RX>;
+ bias-disable;
+ };
+ };
+ };
+
+ rcc: rcc@40023800 {
+ #clock-cells = <2>;
+ compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
+ reg = <0x40023800 0x400>;
+ clocks = <&clk_hse>;
+ };
+ };
+};
+
+&systick {
+ clocks = <&rcc 1 0>;
+ status = "okay";
+};
--
cgit
From 2ecaa477b404d707bac93c56f09a0a6162e04ed7 Mon Sep 17 00:00:00 2001
From: Gabriel Fernandez <gabriel.fernandez@st.com>
Date: Fri, 4 Nov 2016 09:52:00 +0100
Subject: ARM: dts: stm32f429: Add QSPI clock
This patch adds the QSPI clock for stm32f469 discovery board.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
---
arch/arm/boot/dts/stm32f469-disco.dts | 4 ++++
1 file changed, 4 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts
index b766511357de..8877c00ce8e8 100644
--- a/arch/arm/boot/dts/stm32f469-disco.dts
+++ b/arch/arm/boot/dts/stm32f469-disco.dts
@@ -70,6 +70,10 @@
};
};
+&rcc {
+ compatible = "st,stm32f469-rcc", "st,stm32f42xx-rcc", "st,stm32-rcc";
+};
+
&clk_hse {
clock-frequency = <8000000>;
};
--
cgit
From f3d47fc99157d9bc6bc7c52d6107ccdbeeade113 Mon Sep 17 00:00:00 2001
From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Date: Tue, 15 Nov 2016 12:00:11 +0100
Subject: ARM: dts: da850: add the mstpri and ddrctl nodes
Add the nodes for the MSTPRI configuration and DDR2/mDDR memory
controller drivers to da850.dtsi.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
arch/arm/boot/dts/da850.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 2534aab851e1..36066fab2e57 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -209,6 +209,10 @@
};
};
+ prictrl: priority-controller@14110 {
+ compatible = "ti,da850-mstpri";
+ reg = <0x14110 0x0c>;
+ };
cfgchip: chip-controller@1417c {
compatible = "ti,da830-cfgchip", "syscon", "simple-mfd";
reg = <0x1417c 0x14>;
@@ -450,4 +454,8 @@
1 0 0x68000000 0x00008000>;
status = "disabled";
};
+ memctrl: memory-controller@b0000000 {
+ compatible = "ti,da850-ddr-controller";
+ reg = <0xb0000000 0xe8>;
+ };
};
--
cgit
From 7e2f8c0ae670327cbe0348ad2f3df7d9a55a8e5d Mon Sep 17 00:00:00 2001
From: Tony Lindgren <tony@atomide.com>
Date: Sat, 12 Nov 2016 08:57:59 -0800
Subject: ARM: dts: Add minimal support for motorola droid 4 xt894
Let's add minimal support for droid 4 with MMC and WLAN working.
It can be booted with appended dtb using kexec to a state where
MMC and WLAN work with currently no support for it's PMIC or
display.
Note that we are currently using fixed regulators as we don't
have support for it's cpcap PMIC. I'll be posting regmap_spi
based minimal cpcap patches later on for USB and the debug
UART on droid 4 multiplexed with the USB connector.
Cc: Marcel Partap <mpartap@gmx.net>
Cc: Michael Scott <michael.scott@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/omap4-droid4-xt894.dts | 188 +++++++++++++++++++++++++++++++
2 files changed, 189 insertions(+)
create mode 100644 arch/arm/boot/dts/omap4-droid4-xt894.dts
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b92d5016bf00..28df93f92701 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -561,6 +561,7 @@ dtb-$(CONFIG_SOC_AM33XX) += \
am335x-sl50.dtb \
am335x-wega-rdk.dtb
dtb-$(CONFIG_ARCH_OMAP4) += \
+ omap4-droid4-xt894.dtb \
omap4-duovero-parlor.dtb \
omap4-kc1.dtb \
omap4-panda.dtb \
diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts
new file mode 100644
index 000000000000..f3ccb4ceed9e
--- /dev/null
+++ b/arch/arm/boot/dts/omap4-droid4-xt894.dts
@@ -0,0 +1,188 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "omap443x.dtsi"
+
+/ {
+ model = "Motorola Droid 4 XT894";
+ compatible = "motorola,droid4", "ti,omap4430", "ti,omap4";
+
+ chosen {
+ stdout-path = &uart3;
+ };
+
+ /*
+ * We seem to have only 1021 MB accessible, 1021 - 1022 is locked,
+ * then 1023 - 1024 seems to contain mbm. For SRAM, see the notes
+ * below about SRAM and L3_ICLK2 being unused by default,
+ */
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x3fd00000>; /* 1021 MB */
+ };
+
+ /* CPCAP really supports 1650000 to 3400000 range */
+ vmmc: regulator-mmc {
+ compatible = "regulator-fixed";
+ regulator-name = "vmmc";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ };
+
+ /* CPCAP really supports 3000000 to 3100000 range */
+ vemmc: regulator-emmc {
+ compatible = "regulator-fixed";
+ regulator-name = "vemmc";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ };
+
+ /* CPCAP really supports 1650000 to 1950000 range */
+ wl12xx_vmmc: regulator-wl12xx {
+ compatible = "regulator-fixed";
+ regulator-name = "vwl1271";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <1650000>;
+ gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; /* gpio94 */
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
+};
+
+/* L3_2 interconnect is unused, SRAM, GPMC and L3_ICLK2 disabled */
+&gpmc {
+ status = "disabled";
+};
+
+&mmc1 {
+ vmmc-supply = <&vmmc>;
+ bus-width = <4>;
+ cd-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; /* gpio106 */
+};
+
+&mmc2 {
+ vmmc-supply = <&vemmc>;
+ bus-width = <8>;
+ non-removable;
+};
+
+&mmc3 {
+ vmmc-supply = <&wl12xx_vmmc>;
+ interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH
+ &omap4_pmx_core 0xde>;
+
+ non-removable;
+ bus-width = <4>;
+ cap-power-off-card;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wlcore: wlcore@2 {
+ compatible = "ti,wl1283";
+ reg = <2>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; /* gpio100 */
+ ref-clock-frequency = <26000000>;
+ tcxo-clock-frequency = <26000000>;
+ };
+};
+
+/* L3_2 interconnect is unused, SRAM, GPMC and L3_ICLK2 disabled */
+&ocmcram {
+ status = "disabled";
+};
+
+&omap4_pmx_core {
+ usb_gpio_mux_sel1: pinmux_usb_gpio_mux_sel1_pins {
+ /* gpio_60 */
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x088, PIN_OUTPUT | MUX_MODE3)
+ >;
+ };
+
+ usb_ulpi_pins: pinmux_usb_ulpi_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x196, MUX_MODE7)
+ OMAP4_IOPAD(0x198, MUX_MODE7)
+ OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1ba, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1bc, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE0)
+ >;
+ };
+
+ /* usb0_otg_dp and usb0_otg_dm */
+ usb_utmi_pins: pinmux_usb_utmi_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x196, PIN_INPUT | MUX_MODE0)
+ OMAP4_IOPAD(0x198, PIN_INPUT | MUX_MODE0)
+ OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1ba, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1bc, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE7)
+ >;
+ };
+
+ /* uart3_tx_irtx and uart3_rx_irrx */
+ uart3_pins: pinmux_uart3_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x196, MUX_MODE7)
+ OMAP4_IOPAD(0x198, MUX_MODE7)
+ OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1ba, MUX_MODE2)
+ OMAP4_IOPAD(0x1bc, PIN_INPUT | MUX_MODE2)
+ OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE7)
+ >;
+ };
+};
+
+&omap4_pmx_wkup {
+ usb_gpio_mux_sel2: pinmux_usb_gpio_mux_sel2_pins {
+ /* gpio_wk0 */
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x040, PIN_OUTPUT_PULLDOWN | MUX_MODE3)
+ >;
+ };
+};
+
+&uart3 {
+ interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
+ &omap4_pmx_core 0x17c>;
+};
+
+/* Internal UTMI+ PHY used for OTG, CPCAP ULPI PHY for detection and charger */
+&usb_otg_hs {
+ interface-type = <1>;
+ mode = <3>;
+ power = <50>;
+};
--
cgit
From 7fe91fccc49f147e7f4e1f8eefbe97d014763a79 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Tue, 15 Nov 2016 14:50:38 +0100
Subject: ARM: zynq: Remove skeleton.dtsi
Based on
"ARM: dts: explicitly mark skeleton.dtsi as deprecated"
(sha1: 9c0da3cc61f1233c2782e2d3d91e3d0707dd4ba5)
skeleton.dtsi is deprecated.
Move address and size-cells directly to zynq-7000.dtsi.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Julia Cartwright <julia@ni.com>
---
arch/arm/boot/dts/zynq-7000.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index f283ff08381c..f47a6c1cc752 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -10,9 +10,10 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
-/include/ "skeleton.dtsi"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
compatible = "xlnx,zynq-7000";
cpus {
--
cgit
From da457d57594b2f954b4b3eed29affafbd7288733 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Tue, 15 Nov 2016 15:02:18 +0100
Subject: ARM: zynq: Fix W=1 dtc 1.4 warnings
The patch removes these warnings reported by dtc 1.4:
Warning (unit_address_vs_reg): Node /pmu has a reg or ranges property,
but no unit name
Warning (unit_address_vs_reg): Node /fixedregulator@0 has a unit name,
but no reg property
Warning (unit_address_vs_reg): Node /memory has a reg or ranges
property, but no unit name
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Julia Cartwright <julia@ni.com>
Series-to: arm-soc
---
arch/arm/boot/dts/zynq-7000.dtsi | 4 ++--
arch/arm/boot/dts/zynq-parallella.dts | 2 +-
arch/arm/boot/dts/zynq-zc702.dts | 2 +-
arch/arm/boot/dts/zynq-zc706.dts | 2 +-
arch/arm/boot/dts/zynq-zed.dts | 2 +-
arch/arm/boot/dts/zynq-zybo.dts | 2 +-
6 files changed, 7 insertions(+), 7 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index f47a6c1cc752..402b5bbe3b5b 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -42,14 +42,14 @@
};
};
- pmu {
+ pmu@f8891000 {
compatible = "arm,cortex-a9-pmu";
interrupts = <0 5 4>, <0 6 4>;
interrupt-parent = <&intc>;
reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
};
- regulator_vccpint: fixedregulator@0 {
+ regulator_vccpint: fixedregulator {
compatible = "regulator-fixed";
regulator-name = "VCCPINT";
regulator-min-microvolt = <1000000>;
diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts
index 307ed201d658..64a6390fc501 100644
--- a/arch/arm/boot/dts/zynq-parallella.dts
+++ b/arch/arm/boot/dts/zynq-parallella.dts
@@ -28,7 +28,7 @@
serial0 = &uart1;
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x0 0x40000000>;
};
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
index e96959b2e67a..0cdad2cc8b78 100644
--- a/arch/arm/boot/dts/zynq-zc702.dts
+++ b/arch/arm/boot/dts/zynq-zc702.dts
@@ -24,7 +24,7 @@
serial0 = &uart1;
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x0 0x40000000>;
};
diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts
index be6a986bbbd8..ad4bb06dba25 100644
--- a/arch/arm/boot/dts/zynq-zc706.dts
+++ b/arch/arm/boot/dts/zynq-zc706.dts
@@ -24,7 +24,7 @@
serial0 = &uart1;
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x0 0x40000000>;
};
diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/zynq-zed.dts
index 7250c1eac7f9..325379f7983c 100644
--- a/arch/arm/boot/dts/zynq-zed.dts
+++ b/arch/arm/boot/dts/zynq-zed.dts
@@ -23,7 +23,7 @@
serial0 = &uart1;
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x0 0x20000000>;
};
diff --git a/arch/arm/boot/dts/zynq-zybo.dts b/arch/arm/boot/dts/zynq-zybo.dts
index d9e0f3e70671..590ec24b8749 100644
--- a/arch/arm/boot/dts/zynq-zybo.dts
+++ b/arch/arm/boot/dts/zynq-zybo.dts
@@ -23,7 +23,7 @@
serial0 = &uart1;
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x0 0x20000000>;
};
--
cgit
From 995966ccde55b52646b929a98180d68322cb6bea Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Wed, 16 Nov 2016 09:29:57 +0100
Subject: ARM: zynq: Fix pmu register description coding style
Drop the space before/after '<' and '>'; and
separate the entries to be a bit more readable.
Reported-by: Julia Cartwright <julia@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Series-to: arm-soc
Series-cc: julia@ni.com
---
arch/arm/boot/dts/zynq-7000.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 402b5bbe3b5b..f3ac9bfe580e 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -46,7 +46,8 @@
compatible = "arm,cortex-a9-pmu";
interrupts = <0 5 4>, <0 6 4>;
interrupt-parent = <&intc>;
- reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
+ reg = <0xf8891000 0x1000>,
+ <0xf8893000 0x1000>;
};
regulator_vccpint: fixedregulator {
--
cgit
From 601018167fcb2624f374aa3d5a1b7f264c2ae97e Mon Sep 17 00:00:00 2001
From: Andy Yan <andy.yan@rock-chips.com>
Date: Mon, 14 Nov 2016 20:14:48 +0800
Subject: ARM: dts: rockchip: add basic support for RK1108 SOC
RK1108 is embedded with an ARM Cortex-A7 single core and a DSP core.
It is designed for varies application scenario such as car DVR, sports
DV, secure camera and UAV camera.
This patch add basic support for it with DMAC / UART / CRU / pinctrl / MMC
enabled.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Tested-by: Jacob Chen <jacob2.chen@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/boot/dts/rk1108.dtsi | 427 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 427 insertions(+)
create mode 100644 arch/arm/boot/dts/rk1108.dtsi
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/rk1108.dtsi b/arch/arm/boot/dts/rk1108.dtsi
new file mode 100644
index 000000000000..37634ace1222
--- /dev/null
+++ b/arch/arm/boot/dts/rk1108.dtsi
@@ -0,0 +1,427 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/rk1108-cru.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ compatible = "rockchip,rk1108";
+
+ interrupt-parent = <&gic>;
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@f00 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf00>;
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+ clock-frequency = <24000000>;
+ };
+
+ xin24m: oscillator {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xin24m";
+ #clock-cells = <0>;
+ };
+
+ amba {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ pdma: pdma@102a0000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x102a0000 0x4000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ arm,pl330-broken-no-flushp;
+ clocks = <&cru ACLK_DMAC>;
+ clock-names = "apb_pclk";
+ };
+ };
+
+ bus_intmem@10080000 {
+ compatible = "mmio-sram";
+ reg = <0x10080000 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x10080000 0x2000>;
+ };
+
+ uart2: serial@10210000 {
+ compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";
+ reg = <0x10210000 0x100>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2m0_xfer>;
+ status = "disabled";
+ };
+
+ uart1: serial@10220000 {
+ compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";
+ reg = <0x10220000 0x100>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_xfer>;
+ status = "disabled";
+ };
+
+ uart0: serial@10230000 {
+ compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";
+ reg = <0x10230000 0x100>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+ status = "disabled";
+ };
+
+ grf: syscon@10300000 {
+ compatible = "rockchip,rk1108-grf", "syscon";
+ reg = <0x10300000 0x1000>;
+ };
+
+ pmugrf: syscon@20060000 {
+ compatible = "rockchip,rk1108-pmugrf", "syscon";
+ reg = <0x20060000 0x1000>;
+ };
+
+ cru: clock-controller@20200000 {
+ compatible = "rockchip,rk1108-cru";
+ reg = <0x20200000 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ emmc: dwmmc@30110000 {
+ compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";
+ clock-freq-min-max = <400000 150000000>;
+ clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
+ <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x30110000 0x4000>;
+ status = "disabled";
+ };
+
+ sdio: dwmmc@30120000 {
+ compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";
+ clock-freq-min-max = <400000 150000000>;
+ clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
+ <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x30120000 0x4000>;
+ status = "disabled";
+ };
+
+ sdmmc: dwmmc@30130000 {
+ compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";
+ clock-freq-min-max = <400000 100000000>;
+ clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
+ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x30130000 0x4000>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@32010000 {
+ compatible = "arm,gic-400";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+
+ reg = <0x32011000 0x1000>,
+ <0x32012000 0x1000>,
+ <0x32014000 0x2000>,
+ <0x32016000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk1108-pinctrl";
+ rockchip,grf = <&grf>;
+ rockchip,pmu = <&pmugrf>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gpio0: gpio0@20030000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x20030000 0x100>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&xin24m>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio1@10310000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x10310000 0x100>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&xin24m>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio2@10320000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x10320000 0x100>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&xin24m>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio3@10330000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x10330000 0x100>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&xin24m>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pcfg_pull_up: pcfg-pull-up {
+ bias-pull-up;
+ };
+
+ pcfg_pull_down: pcfg-pull-down {
+ bias-pull-down;
+ };
+
+ pcfg_pull_none: pcfg-pull-none {
+ bias-disable;
+ };
+
+ pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
+ drive-strength = <8>;
+ };
+
+ pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
+ drive-strength = <12>;
+ };
+
+ pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
+ bias-pull-up;
+ drive-strength = <8>;
+ };
+
+ pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
+ drive-strength = <4>;
+ };
+
+ pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
+ bias-pull-up;
+ drive-strength = <4>;
+ };
+
+ pcfg_output_high: pcfg-output-high {
+ output-high;
+ };
+
+ pcfg_output_low: pcfg-output-low {
+ output-low;
+ };
+
+ pcfg_input_high: pcfg-input-high {
+ bias-pull-up;
+ input-enable;
+ };
+
+ i2c1 {
+ i2c1_xfer: i2c1-xfer {
+ rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
+ <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
+ };
+ };
+
+ i2c2m1 {
+ i2c2m1_xfer: i2c2m1-xfer {
+ rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
+ <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>;
+ };
+
+ i2c2m1_gpio: i2c2m1-gpio {
+ rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
+ <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ i2c2m05v {
+ i2c2m05v_xfer: i2c2m05v-xfer {
+ rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,
+ <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ i2c2m05v_gpio: i2c2m05v-gpio {
+ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
+ <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ i2c3 {
+ i2c3_xfer: i2c3-xfer {
+ rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
+ <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ uart0 {
+ uart0_xfer: uart0-xfer {
+ rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>,
+ <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart0_cts: uart0-cts {
+ rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart0_rts: uart0-rts {
+ rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart0_rts_gpio: uart0-rts-gpio {
+ rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ uart1 {
+ uart1_xfer: uart1-xfer {
+ rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
+ <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart1_cts: uart1-cts {
+ rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart1_rts: uart1-rts {
+ rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ uart2m0 {
+ uart2m0_xfer: uart2m0-xfer {
+ rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>,
+ <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ uart2m1 {
+ uart2m1_xfer: uart2m1-xfer {
+ rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>,
+ <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ uart2_5v {
+ uart2_5v_cts: uart2_5v-cts {
+ rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart2_5v_rts: uart2_5v-rts {
+ rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+ };
+};
--
cgit
From f35597ac4906d34797a6f344e6cded426d891f52 Mon Sep 17 00:00:00 2001
From: Andy Yan <andy.yan@rock-chips.com>
Date: Mon, 14 Nov 2016 20:17:43 +0800
Subject: ARM: dts: rockchip: add rockchip RK1108 Evaluation board
RK1108 EVB is designed by Rockchip for CVR field.
This patch add basic support for it, which can boot with
initramfs into shell.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/rk1108-evb.dts | 69 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 70 insertions(+)
create mode 100644 arch/arm/boot/dts/rk1108-evb.dts
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index e49476a78250..249dca960cdd 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -635,6 +635,7 @@ dtb-$(CONFIG_ARCH_REALVIEW) += \
arm-realview-pba8.dtb \
arm-realview-pbx-a9.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += \
+ rk1108-evb.dtb \
rk3036-evb.dtb \
rk3036-kylin.dtb \
rk3066a-bqcurie2.dtb \
diff --git a/arch/arm/boot/dts/rk1108-evb.dts b/arch/arm/boot/dts/rk1108-evb.dts
new file mode 100644
index 000000000000..3956cff4ca79
--- /dev/null
+++ b/arch/arm/boot/dts/rk1108-evb.dts
@@ -0,0 +1,69 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "rk1108.dtsi"
+
+/ {
+ model = "Rockchip RK1108 Evaluation board";
+ compatible = "rockchip,rk1108-evb", "rockchip,rk1108";
+
+ memory@60000000 {
+ device_type = "memory";
+ reg = <0x60000000 0x08000000>;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
--
cgit
From c458e1b504a6a8c817fc56b4d4704273f2c459bb Mon Sep 17 00:00:00 2001
From: Jacob Chen <jacob2.chen@rock-chips.com>
Date: Sun, 13 Nov 2016 16:13:18 +0800
Subject: ARM: dts: rockchip: add the sdmmc pinctrl for rk1108
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/boot/dts/rk1108.dtsi | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/rk1108.dtsi b/arch/arm/boot/dts/rk1108.dtsi
index 37634ace1222..d7700235e0f5 100644
--- a/arch/arm/boot/dts/rk1108.dtsi
+++ b/arch/arm/boot/dts/rk1108.dtsi
@@ -366,6 +366,31 @@
};
};
+ sdmmc {
+ sdmmc_clk: sdmmc-clk {
+ rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
+ };
+
+ sdmmc_cmd: sdmmc-cmd {
+ rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
+ };
+
+ sdmmc_cd: sdmmc-cd {
+ rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
+ };
+
+ sdmmc_bus1: sdmmc-bus1 {
+ rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
+ };
+
+ sdmmc_bus4: sdmmc-bus4 {
+ rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
+ <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
+ <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
+ <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
+ };
+ };
+
uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>,
--
cgit
From 77f923cb141bdc77b61a9296581ef86b34e134e5 Mon Sep 17 00:00:00 2001
From: Jonathan Richardson <jonathan.richardson@broadcom.com>
Date: Tue, 18 Oct 2016 12:00:37 -0700
Subject: ARM: dts: Enable Broadcom iProc mailbox controller
Reviewed-by: Jonathan Richardson <jonathan.richardson@broadcom.com>
Reviewed-by: Shreesha Rajashekar <shreesha.rajashekar@broadcom.com>
Reviewed-by: Ray Jui <ray.jui@broadcom.com>
Tested-by: Jonathan Richardson <jonathan.richardson@broadcom.com>
Reviewed-by: Vikram Prakash <vikram.prakash@broadcom.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
Signed-off-by: Jonathan Richardson <jonathan.richardson@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/bcm-cygnus.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi
index 539c58f12f51..4b741f67ec6a 100644
--- a/arch/arm/boot/dts/bcm-cygnus.dtsi
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -114,6 +114,15 @@
<0x0301d24c 0x2c>;
};
+ mailbox: mailbox@03024024 {
+ compatible = "brcm,iproc-mailbox";
+ reg = <0x03024024 0x40>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ #mbox-cells = <1>;
+ };
+
gpio_crmu: gpio@03024800 {
compatible = "brcm,cygnus-crmu-gpio";
reg = <0x03024800 0x50>,
--
cgit
From 2c42d0f060801caad669290d337a12b26560fac9 Mon Sep 17 00:00:00 2001
From: Jonathan Richardson <jonathan.richardson@broadcom.com>
Date: Tue, 18 Oct 2016 12:00:38 -0700
Subject: ARM: dts: Enable interrupt support for cygnus crmu gpio driver
The M0 processor handles interrupts for the always-on CRMU GPIO
controller. Setting the CRMU GPIO driver with the mailbox controller as
the interrupt parent allows the mailbox controller to forward interrupts
from the M0 to the GPIO driver for processing.
Reviewed-by: Jonathan Richardson <jonathan.richardson@broadcom.com>
Tested-by: Jonathan Richardson <jonathan.richardson@broadcom.com>
Reviewed-by: Vikram Prakash <vikram.prakash@broadcom.com>
Reviewed-by: Shreesha Rajashekar <shreesha.rajashekar@broadcom.com>
Reviewed-by: Ray Jui <ray.jui@broadcom.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
Signed-off-by: Jonathan Richardson <jonathan.richardson@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/bcm-cygnus.dtsi | 3 +++
1 file changed, 3 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi
index 4b741f67ec6a..c592f6d82685 100644
--- a/arch/arm/boot/dts/bcm-cygnus.dtsi
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -130,6 +130,9 @@
ngpios = <6>;
#gpio-cells = <2>;
gpio-controller;
+ interrupt-controller;
+ interrupt-parent = <&mailbox>;
+ interrupts = <0>;
};
i2c0: i2c@18008000 {
--
cgit
From 7fa8b51b5d2aff3cf8e932310eb43882f06a751c Mon Sep 17 00:00:00 2001
From: Jonathan Richardson <jonathar@broadcom.com>
Date: Mon, 24 Oct 2016 12:12:04 -0700
Subject: ARM: dts: Add node for Broadcom OTP controller driver
Reviewed-by: Ray Jui <ray.jui@broadcom.com>
Tested-by: Jonathan Richardson <jonathan.richardson@broadcom.com>
Signed-off-by: Scott Branden <scott.branden@broadcom.com>
Signed-off-by: Oza Pawandeep <oza@broadcom.com>
Signed-off-by: Jonathan Richardson <jonathan.richardson@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/bcm-cygnus.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi
index c592f6d82685..8833a4c3cd96 100644
--- a/arch/arm/boot/dts/bcm-cygnus.dtsi
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -91,6 +91,13 @@
#address-cells = <1>;
#size-cells = <1>;
+ otp: otp@0301c800 {
+ compatible = "brcm,ocotp";
+ reg = <0x0301c800 0x2c>;
+ brcm,ocotp-size = <2048>;
+ status = "disabled";
+ };
+
pcie_phy: phy@0301d0a0 {
compatible = "brcm,cygnus-pcie-phy";
reg = <0x0301d0a0 0x14>;
--
cgit
From 41182beb217c47cfbaaf26a60f22a8b3943faa61 Mon Sep 17 00:00:00 2001
From: Rafał Miłecki <rafal@milecki.pl>
Date: Sun, 13 Nov 2016 11:12:09 +0100
Subject: ARM: BCM5301X: Add DT for TP-LINK Archer C9 V1
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
It's BCM4709A0 based device with 16 MiB flash, 128 MiB of RAM and two
PCIe based on-PCB BCM4360 chipsets.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts | 114 ++++++++++++++++++++++
2 files changed, 115 insertions(+)
create mode 100644 arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 837703ac79e8..7a52a9f8d5a7 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -87,6 +87,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
bcm4709-buffalo-wxr-1900dhp.dtb \
bcm4709-netgear-r7000.dtb \
bcm4709-netgear-r8000.dtb \
+ bcm4709-tplink-archer-c9-v1.dtb \
bcm47094-dlink-dir-885l.dtb \
bcm47094-luxul-xwr-3100.dtb \
bcm47094-netgear-r8500.dtb \
diff --git a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts
new file mode 100644
index 000000000000..9a92c24ac2d8
--- /dev/null
+++ b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts
@@ -0,0 +1,114 @@
+/*
+ * Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
+ *
+ * Licensed under the ISC license.
+ */
+
+/dts-v1/;
+
+#include "bcm4709.dtsi"
+
+/ {
+ compatible = "tplink,archer-c9-v1", "brcm,bcm4709", "brcm,bcm4708";
+ model = "TP-LINK Archer C9 V1";
+
+ chosen {
+ bootargs = "console=ttyS0,115200 earlycon";
+ };
+
+ memory {
+ reg = <0x00000000 0x08000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ lan {
+ label = "bcm53xx:blue:lan";
+ gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-off";
+ };
+
+ wps {
+ label = "bcm53xx:blue:wps";
+ gpios = <&chipcommon 2 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-off";
+ };
+
+ 2ghz {
+ label = "bcm53xx:blue:2ghz";
+ gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-off";
+ };
+
+ 5ghz {
+ label = "bcm53xx:blue:5ghz";
+ gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-off";
+ };
+
+ usb3 {
+ label = "bcm53xx:blue:usb3";
+ gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-off";
+ };
+
+ usb2 {
+ label = "bcm53xx:blue:usb2";
+ gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-off";
+ };
+
+ wan-blue {
+ label = "bcm53xx:blue:wan";
+ gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-off";
+ };
+
+ wan-amber {
+ label = "bcm53xx:amber:wan";
+ gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-off";
+ };
+
+ power {
+ label = "bcm53xx:blue:power";
+ gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-on";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ wps {
+ label = "WPS";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
+ };
+
+ restart {
+ label = "Reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&usb2 {
+ vcc-gpio = <&chipcommon 13 GPIO_ACTIVE_HIGH>;
+};
+
+&usb3 {
+ vcc-gpio = <&chipcommon 12 GPIO_ACTIVE_HIGH>;
+};
+
+&spi_nor {
+ status = "okay";
+};
--
cgit
From 1480986d68ce32706ff08586e111dcb769dd3962 Mon Sep 17 00:00:00 2001
From: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
Date: Mon, 14 Nov 2016 08:30:19 -0500
Subject: ARM: dts: enable GPIO-b for Broadcom NSP
This enables the GPIO-b support for Broadcom NSP SoC
Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/bcm-nsp.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 7502556143f0..b6142bda661e 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -241,6 +241,16 @@
brcm,nand-has-wp;
};
+ gpiob: gpio@30000 {
+ compatible = "brcm,iproc-nsp-gpio", "brcm,iproc-gpio";
+ reg = <0x30000 0x50>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ ngpios = <4>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
pwm: pwm@31000 {
compatible = "brcm,iproc-pwm";
reg = <0x31000 0x28>;
--
cgit
From 6b9170887e1b912b657dab4597f8b44ae4dbdf50 Mon Sep 17 00:00:00 2001
From: Stefan Wahren <stefan.wahren@i2se.com>
Date: Wed, 16 Nov 2016 17:52:06 +0000
Subject: ARM: bcm2835: Fix names for the Raspberry Pi GPIO lines
There are some differences between the schematics and the official firmware
DTS [1]. So based on these additional information the following has been
changed:
* use consistent "CAM_GPIO1" for camera LED
* use consistent "CAM_GPIO0" for camera shutdown
* add "USB_LIMIT" for USB current limit (0=600mA, 1=1200mA)
[1] - https://github.com/raspberrypi/firmware/blob/master/extra/dt-blob.dts
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
---
arch/arm/boot/dts/bcm2835-rpi-a-plus.dts | 4 ++--
arch/arm/boot/dts/bcm2835-rpi-a.dts | 4 ++--
arch/arm/boot/dts/bcm2835-rpi-b-plus.dts | 2 +-
arch/arm/boot/dts/bcm2835-rpi-b.dts | 4 ++--
4 files changed, 7 insertions(+), 7 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
index 5a22c7965f34..d0704540db6b 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
@@ -63,13 +63,13 @@
"SCL0",
"NC", /* GPIO30 */
"NC", /* GPIO31 */
- "NC", /* GPIO32 */
+ "CAM_GPIO1", /* GPIO32 */
"NC", /* GPIO33 */
"NC", /* GPIO34 */
"PWR_LOW_N", /* GPIO35 */
"NC", /* GPIO36 */
"NC", /* GPIO37 */
- "NC", /* GPIO38 */
+ "USB_LIMIT", /* GPIO38 */
"NC", /* GPIO39 */
"PWM0_OUT", /* GPIO40 */
"CAM_GPIO0", /* GPIO41 */
diff --git a/arch/arm/boot/dts/bcm2835-rpi-a.dts b/arch/arm/boot/dts/bcm2835-rpi-a.dts
index 54f98c59a75d..46d078e29017 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-a.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-a.dts
@@ -29,7 +29,7 @@
"SDA1",
"SCL1",
"GPIO_GCLK",
- "CAM_CLK",
+ "CAM_GPIO1",
"LAN_RUN",
"SPI_CE1_N",
"SPI_CE0_N",
@@ -52,7 +52,7 @@
"GPIO24",
"GPIO25",
"NC", /* GPIO26 */
- "CAM_GPIO",
+ "CAM_GPIO0",
/* Binary number representing build/revision */
"CONFIG0",
"CONFIG1",
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
index b67587e6cbef..432088ebb0a1 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
@@ -71,7 +71,7 @@
"PWR_LOW_N", /* GPIO35 */
"NC", /* GPIO36 */
"NC", /* GPIO37 */
- "NC", /* GPIO38 */
+ "USB_LIMIT", /* GPIO38 */
"NC", /* GPIO39 */
"PWM0_OUT", /* GPIO40 */
"CAM_GPIO0", /* GPIO41 */
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts
index 71f50e16c646..4d56fe3006b0 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts
@@ -30,7 +30,7 @@
"SDA1",
"SCL1",
"GPIO_GCLK",
- "CAM_CLK",
+ "CAM_GPIO1",
"LAN_RUN",
"SPI_CE1_N",
"SPI_CE0_N",
@@ -53,7 +53,7 @@
"GPIO24",
"GPIO25",
"NC", /* GPIO26 */
- "CAM_GPIO",
+ "CAM_GPIO0",
/* Binary number representing build/revision */
"CONFIG0",
"CONFIG1",
--
cgit
From 3a1689ea752436917c5ce4487527ed6c444630ee Mon Sep 17 00:00:00 2001
From: Stefan Wahren <stefan.wahren@i2se.com>
Date: Wed, 16 Nov 2016 17:52:07 +0000
Subject: ARM: bcm2835: Add names for the RPi Zero GPIO lines
This adds the GPIO names for the Raspberry Pi Zero. The GPIO lines
of the RPi Zero are almost identical to the Model A+ except:
* GPIO 35, 38, 40 and 45 are not connected
* Status LED is active low
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
---
arch/arm/boot/dts/bcm2835-rpi-zero.dts | 65 ++++++++++++++++++++++++++++++++++
1 file changed, 65 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero.dts b/arch/arm/boot/dts/bcm2835-rpi-zero.dts
index 7c1c18048948..cc8b832c4c78 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-zero.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-zero.dts
@@ -26,6 +26,71 @@
};
&gpio {
+ /*
+ * This is based on the official GPU firmware DT blob.
+ *
+ * Legend:
+ * "NC" = not connected (no rail from the SoC)
+ * "FOO" = GPIO line named "FOO" on the schematic
+ * "FOO_N" = GPIO line named "FOO" on schematic, active low
+ */
+ gpio-line-names = "SDA0",
+ "SCL0",
+ "SDA1",
+ "SCL1",
+ "GPIO_GCLK",
+ "GPIO5",
+ "GPIO6",
+ "SPI_CE1_N",
+ "SPI_CE0_N",
+ "SPI_MISO",
+ "SPI_MOSI",
+ "SPI_SCLK",
+ "GPIO12",
+ "GPIO13",
+ /* Serial port */
+ "TXD0",
+ "RXD0",
+ "GPIO16",
+ "GPIO17",
+ "GPIO18",
+ "GPIO19",
+ "GPIO20",
+ "GPIO21",
+ "GPIO22",
+ "GPIO23",
+ "GPIO24",
+ "GPIO25",
+ "GPIO26",
+ "GPIO27",
+ "SDA0",
+ "SCL0",
+ "NC", /* GPIO30 */
+ "NC", /* GPIO31 */
+ "CAM_GPIO1", /* GPIO32 */
+ "NC", /* GPIO33 */
+ "NC", /* GPIO34 */
+ "NC", /* GPIO35 */
+ "NC", /* GPIO36 */
+ "NC", /* GPIO37 */
+ "NC", /* GPIO38 */
+ "NC", /* GPIO39 */
+ "NC", /* GPIO40 */
+ "CAM_GPIO0", /* GPIO41 */
+ "NC", /* GPIO42 */
+ "NC", /* GPIO43 */
+ "NC", /* GPIO44 */
+ "NC", /* GPIO45 */
+ "HDMI_HPD_N",
+ "STATUS_LED_N",
+ /* Used by SD Card */
+ "SD_CLK_R",
+ "SD_CMD_R",
+ "SD_DATA0_R",
+ "SD_DATA1_R",
+ "SD_DATA2_R",
+ "SD_DATA3_R";
+
pinctrl-0 = <&gpioout &alt0 &i2s_alt0>;
/* I2S interface */
--
cgit
From 66579e29f7aba7c72146e608efe08c08ea1dc934 Mon Sep 17 00:00:00 2001
From: Sudeep Holla <sudeep.holla@arm.com>
Date: Mon, 14 Nov 2016 15:44:07 +0000
Subject: ARM: dts: omap5: replace gpio-key,wakeup with wakeup-source property
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Though the keyboard driver for GPIO buttons(gpio-keys) will continue to
check for/support the legacy "gpio-key,wakeup" boolean property to
enable gpio buttons as wakeup source, "wakeup-source" is the new
standard binding.
This patch replaces the legacy "gpio-key,wakeup" with the unified
"wakeup-source" property in order to avoid any further copy-paste
duplication.
Cc: "Benoît Cousson" <bcousson@baylibre.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/omap5-uevm.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
index 2fcdc516da45..a8c72611fbe3 100644
--- a/arch/arm/boot/dts/omap5-uevm.dts
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -41,7 +41,7 @@
label = "BTN1";
linux,code = <169>;
gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; /* gpio3_83 */
- gpio-key,wakeup;
+ wakeup-source;
autorepeat;
debounce_interval = <50>;
};
--
cgit
From a291b6b3d287592da72d463e5e141a2a60e8ee04 Mon Sep 17 00:00:00 2001
From: Jyri Sarha <jsarha@ti.com>
Date: Thu, 17 Nov 2016 22:13:42 +0200
Subject: ARM: dts: am335x-boneblack: Add blue-and-red-wiring -property to LCDC
node
Add blue-and-red-wiring -property to LCDC node. Also adds comments on
how to get support 24 bit RGB mode. After this patch am335x-boneblack
support RGB565, BGR888, and XBGR8888 color formats. See details in
Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt.
The BBB has straight color wiring from am335x to tda19988, however the
tda19988 can be configured to cross the blue and red wires. The
comments show how to do that with video-ports property of tda19988
node and how to tell LCDC that blue and red wires are crossed, with
blue-and-red-wiring LCDC node property. This changes supported color
formats from 16 bit RGB and 24 bit BGR to 16 bit BGR and 24 bit RGB.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/am335x-boneblack.dts | 11 +++++++++++
1 file changed, 11 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts
index 6bbb1fee0868..db00d8ef7b19 100644
--- a/arch/arm/boot/dts/am335x-boneblack.dts
+++ b/arch/arm/boot/dts/am335x-boneblack.dts
@@ -79,6 +79,14 @@
&lcdc {
status = "okay";
+
+ /* If you want to get 24 bit RGB and 16 BGR mode instead of
+ * current 16 bit RGB and 24 BGR modes, set the propety
+ * below to "crossed" and uncomment the video-ports -property
+ * in tda19988 node.
+ */
+ blue-and-red-wiring = "straight";
+
port {
lcdc_0: endpoint@0 {
remote-endpoint = <&hdmi_0>;
@@ -95,6 +103,9 @@
pinctrl-0 = <&nxp_hdmi_bonelt_pins>;
pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>;
+ /* Convert 24bit BGR to RGB, e.g. cross red and blue wiring */
+ /* video-ports = <0x234501>; */
+
#sound-dai-cells = <0>;
audio-ports = < TDA998x_I2S 0x03>;
--
cgit
From c9a865bd47150db0cd3d93e30744783e26c22f6c Mon Sep 17 00:00:00 2001
From: Markus Reichl <m.reichl@fivetechno.de>
Date: Fri, 18 Nov 2016 10:55:04 +0100
Subject: ARM: dts: exynos: Add ADCs on 4412 and 5422 based odroid boards.
Odroid-X, -X2, -XU3 and -XU4 have SOC-ADC routed to an external connector.
Enable the ADC for use as iio-device.
Signed-off-by: Markus Reichl <m.reichl@fivetechno.de>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/boot/dts/exynos4412-odroidx.dts | 5 +++++
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 11 +++++++++++
2 files changed, 16 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 61906b35ea7a..153a75fe6e24 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -64,6 +64,11 @@
};
};
+&adc {
+ vdd-supply = <&ldo10_reg>;
+ status = "okay";
+};
+
/* VDDQ for MSHC (eMMC card) */
&buck8_reg {
regulator-name = "BUCK8_VDDQ_MMC4_2.8V";
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
index 246d298557f5..9e63328b961f 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
@@ -147,6 +147,11 @@
};
};
+&adc {
+ vdd-supply = <&ldo4_reg>;
+ status = "okay";
+};
+
&bus_wcore {
devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>,
<&nocp_mem1_0>, <&nocp_mem1_1>;
@@ -293,6 +298,12 @@
regulator-max-microvolt = <1800000>;
};
+ ldo4_reg: LDO4 {
+ regulator-name = "vdd_adc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
ldo5_reg: LDO5 {
regulator-name = "vdd_ldo5";
regulator-min-microvolt = <1800000>;
--
cgit
From 3c558b3289e83a2010de99b60df3d36b93609c99 Mon Sep 17 00:00:00 2001
From: "Andrew F. Davis" <afd@ti.com>
Date: Fri, 7 Oct 2016 09:44:22 -0500
Subject: ARM: dts: am335x-icev2: Add Industrial input support
The SN65HVS882 is available on the AM335x-ICEv2 and is attached to SPI0.
Input is attached to the I/O header.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/am335x-icev2.dts | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/am335x-icev2.dts
index 85e04c205542..d46efc6a0772 100644
--- a/arch/arm/boot/dts/am335x-icev2.dts
+++ b/arch/arm/boot/dts/am335x-icev2.dts
@@ -187,6 +187,8 @@
AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */
AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */
AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */
+ AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE0) /* (C15) spi0_cs1.spi0_cs1 */
+ AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7) /* (B12) mcasp0_aclkr.gpio3[18] */
>;
};
@@ -224,6 +226,24 @@
};
};
+&spi0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins_default>;
+
+ sn65hvs882@1 {
+ compatible = "pisosr-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ load-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
+
+ reg = <1>;
+ spi-max-frequency = <1000000>;
+ spi-cpol;
+ };
+};
+
#include "tps65910.dtsi"
&tps {
--
cgit
From 722cb0fa07918bf0c77cb05b9cf52d7ee0ca8b5c Mon Sep 17 00:00:00 2001
From: "Andrew F. Davis" <afd@ti.com>
Date: Fri, 7 Oct 2016 09:44:23 -0500
Subject: ARM: dts: am335x-icev2: Disable Industrial I/O LEDs and fix naming
The LEDs tied to the Industrial I/O output pins are meant for providing
status feed-back and are not the primary use for the pins. Disable
this use by default. Also unify the LED naming across IDK platforms.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/am335x-icev2.dts | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/am335x-icev2.dts
index d46efc6a0772..fa3f5dc4ffa0 100644
--- a/arch/arm/boot/dts/am335x-icev2.dts
+++ b/arch/arm/boot/dts/am335x-icev2.dts
@@ -43,52 +43,52 @@
enable-active-high;
};
- leds0 {
+ leds-iio {
+ status = "disabled";
compatible = "gpio-leds";
-
- led0 {
+ led-out0 {
label = "out0";
gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
- led1 {
+ led-out1 {
label = "out1";
gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
- led2 {
+ led-out2 {
label = "out2";
gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
- led3 {
+ led-out3 {
label = "out3";
gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
- led4 {
+ led-out4 {
label = "out4";
gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
- led5 {
+ led-out5 {
label = "out5";
gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
- led6 {
+ led-out6 {
label = "out6";
gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
- led7 {
+ led-out7 {
label = "out7";
gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>;
default-state = "off";
--
cgit
From a59c2238d62b079c7ba9b072dcc258f274950542 Mon Sep 17 00:00:00 2001
From: "Andrew F. Davis" <afd@ti.com>
Date: Fri, 7 Oct 2016 09:44:24 -0500
Subject: ARM: dts: am335x-icev2: Add ADC support
7 of the 8 ADC inputs on the am335x are connected to the Industrial I/O
header, add this here.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/am335x-icev2.dts | 7 +++++++
1 file changed, 7 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/am335x-icev2.dts
index fa3f5dc4ffa0..1463df3b5b19 100644
--- a/arch/arm/boot/dts/am335x-icev2.dts
+++ b/arch/arm/boot/dts/am335x-icev2.dts
@@ -244,6 +244,13 @@
};
};
+&tscadc {
+ status = "okay";
+ adc {
+ ti,adc-channels = <1 2 3 4 5 6 7>;
+ };
+};
+
#include "tps65910.dtsi"
&tps {
--
cgit
From a2f8ad59881f26625478027074ec24f0af1525d2 Mon Sep 17 00:00:00 2001
From: "Andrew F. Davis" <afd@ti.com>
Date: Fri, 7 Oct 2016 09:44:25 -0500
Subject: ARM: dts: am437x-idk: Add Industrial input support
The SN65HVS882 is available on the AM437x IDK and is attached to SPI1.
Input is attached to the I/O header.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/am437x-idk-evm.dts | 42 ++++++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts b/arch/arm/boot/dts/am437x-idk-evm.dts
index 25ce611c6568..fff7ef6661a7 100644
--- a/arch/arm/boot/dts/am437x-idk-evm.dts
+++ b/arch/arm/boot/dts/am437x-idk-evm.dts
@@ -178,6 +178,24 @@
>;
};
+ spi1_pins_default: spi1_pins_default {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x908, PIN_INPUT | MUX_MODE2) /* mii1_col.spi1_sclk */
+ AM4372_IOPAD(0x910, PIN_INPUT | MUX_MODE2) /* mii1_rx_er.spi1_d1 */
+ AM4372_IOPAD(0x944, PIN_OUTPUT | MUX_MODE2) /* rmii1_ref_clk.spi1_cs0 */
+ AM4372_IOPAD(0x90c, PIN_OUTPUT | MUX_MODE7) /* mii1_crs.gpio3_1 */
+ >;
+ };
+
+ spi1_pins_sleep: spi1_pins_sleep {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
ecap0_pins_default: backlight_pins_default {
pinctrl-single,pins = <
AM4372_IOPAD(0x964, PIN_OUTPUT | MUX_MODE0) /* ecap0_in_pwm0_out.ecap0_in_pwm0_out */
@@ -292,6 +310,26 @@
clock-frequency = <100000>;
};
+&spi1 {
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&spi1_pins_default>;
+ pinctrl-1 = <&spi1_pins_sleep>;
+ ti,pindir-d0-out-d1-in;
+
+ sn65hvs882: sn65hvs882@0 {
+ compatible = "pisosr-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ load-gpios = <&gpio3 1 GPIO_ACTIVE_LOW>;
+
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ spi-cpol;
+ };
+};
+
&epwmss0 {
status = "okay";
};
@@ -310,6 +348,10 @@
status = "okay";
};
+&gpio3 {
+ status = "okay";
+};
+
&gpio4 {
status = "okay";
};
--
cgit
From c0a0ee4693511643a4ebab949a97d6e79508b06d Mon Sep 17 00:00:00 2001
From: "Andrew F. Davis" <afd@ti.com>
Date: Fri, 7 Oct 2016 09:44:26 -0500
Subject: ARM: dts: am437x-idk: Add Industrial output support
The TPIC2810 is available on the AM437x IDK and is attached to I2C1.
Output is attached to the I/O header and 10 LEDs.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/am437x-idk-evm.dts | 59 ++++++++++++++++++++++++++++++++++++
1 file changed, 59 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts b/arch/arm/boot/dts/am437x-idk-evm.dts
index fff7ef6661a7..b76a7c0264a5 100644
--- a/arch/arm/boot/dts/am437x-idk-evm.dts
+++ b/arch/arm/boot/dts/am437x-idk-evm.dts
@@ -117,6 +117,58 @@
compatible = "fixed-clock";
clock-frequency = <32768>;
};
+
+ leds-iio {
+ status = "disabled";
+ compatible = "gpio-leds";
+ led-out0 {
+ label = "out0";
+ gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-out1 {
+ label = "out1";
+ gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-out2 {
+ label = "out2";
+ gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-out3 {
+ label = "out3";
+ gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-out4 {
+ label = "out4";
+ gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-out5 {
+ label = "out5";
+ gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-out6 {
+ label = "out6";
+ gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-out7 {
+ label = "out7";
+ gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
};
&am43xx_pinmux {
@@ -308,6 +360,13 @@
pinctrl-0 = <&i2c2_pins_default>;
pinctrl-1 = <&i2c2_pins_sleep>;
clock-frequency = <100000>;
+
+ tpic2810: tpic2810@60 {
+ compatible = "ti,tpic2810";
+ reg = <0x60>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
};
&spi1 {
--
cgit
From 8b43764f5d6859c6da9ee140b8b6f0d8c378064e Mon Sep 17 00:00:00 2001
From: "Andrew F. Davis" <afd@ti.com>
Date: Fri, 7 Oct 2016 09:44:27 -0500
Subject: ARM: dts: am57xx-idk: Add Industrial input support
The SN65HVS882 is available on both the AM572x and AM571x IDKs and is
attached to SPI1. Input is attached to the I/O header. The load trigger
is attached to GPIO3_19 on the AM572x IDK.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/am572x-idk.dts | 4 ++++
arch/arm/boot/dts/am57xx-idk-common.dtsi | 15 +++++++++++++++
2 files changed, 19 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/am572x-idk.dts b/arch/arm/boot/dts/am572x-idk.dts
index 87bbc66f0f21..27d9149cedba 100644
--- a/arch/arm/boot/dts/am572x-idk.dts
+++ b/arch/arm/boot/dts/am572x-idk.dts
@@ -83,3 +83,7 @@
bus-width = <4>;
cd-gpios = <&gpio6 27 0>; /* gpio 219 */
};
+
+&sn65hvs882 {
+ load-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
+};
diff --git a/arch/arm/boot/dts/am57xx-idk-common.dtsi b/arch/arm/boot/dts/am57xx-idk-common.dtsi
index 03cec62260e1..438076e23a55 100644
--- a/arch/arm/boot/dts/am57xx-idk-common.dtsi
+++ b/arch/arm/boot/dts/am57xx-idk-common.dtsi
@@ -253,6 +253,21 @@
};
};
+&mcspi3 {
+ status = "okay";
+ ti,pindir-d0-out-d1-in;
+
+ sn65hvs882: sn65hvs882@0 {
+ compatible = "pisosr-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ spi-cpol;
+ };
+};
+
&uart3 {
status = "okay";
interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH
--
cgit
From 50e95b6b854cf4c996d3b91ef3f19d779a2a7020 Mon Sep 17 00:00:00 2001
From: "Andrew F. Davis" <afd@ti.com>
Date: Fri, 7 Oct 2016 09:44:28 -0500
Subject: ARM: dts: am57xx-idk: Add Industrial output support
The TPIC2810 is available on both the AM571x and the AM572x IDKs and
is attached to I2C1. Output is attached to the I/O header and 10 LEDs.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/am57xx-idk-common.dtsi | 59 ++++++++++++++++++++++++++++++++
1 file changed, 59 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/am57xx-idk-common.dtsi b/arch/arm/boot/dts/am57xx-idk-common.dtsi
index 438076e23a55..35e210ce68a1 100644
--- a/arch/arm/boot/dts/am57xx-idk-common.dtsi
+++ b/arch/arm/boot/dts/am57xx-idk-common.dtsi
@@ -43,6 +43,58 @@
regulator-always-on;
regulator-boot-on;
};
+
+ leds-iio {
+ status = "disabled";
+ compatible = "gpio-leds";
+ led-out0 {
+ label = "out0";
+ gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-out1 {
+ label = "out1";
+ gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-out2 {
+ label = "out2";
+ gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-out3 {
+ label = "out3";
+ gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-out4 {
+ label = "out4";
+ gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-out5 {
+ label = "out5";
+ gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-out6 {
+ label = "out6";
+ gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-out7 {
+ label = "out7";
+ gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
};
&i2c1 {
@@ -266,6 +318,13 @@
spi-max-frequency = <1000000>;
spi-cpol;
};
+
+ tpic2810: tpic2810@60 {
+ compatible = "ti,tpic2810";
+ reg = <0x60>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
};
&uart3 {
--
cgit
From 209f4d7a3d50ae6e162e6d61765d722bb26a686b Mon Sep 17 00:00:00 2001
From: Robert Jarzmik <robert.jarzmik@free.fr>
Date: Sun, 10 Apr 2016 21:30:00 +0200
Subject: ARM: dts: pxa: add pxa25x .dtsi file
This file describes pxa25x SoCs. Not all devices are listed yet, only
the subset which was already tested with a lubbock board.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
---
arch/arm/boot/dts/pxa25x.dtsi | 92 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 92 insertions(+)
create mode 100644 arch/arm/boot/dts/pxa25x.dtsi
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/pxa25x.dtsi b/arch/arm/boot/dts/pxa25x.dtsi
new file mode 100644
index 000000000000..0d1e012178c4
--- /dev/null
+++ b/arch/arm/boot/dts/pxa25x.dtsi
@@ -0,0 +1,92 @@
+/*
+ * Copyright (C) 2016 Robert Jarzmik <robert.jarzmik@free.fr>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include "pxa2xx.dtsi"
+#include "dt-bindings/clock/pxa-clock.h"
+
+/ {
+ model = "Marvell PXA25x family SoC";
+ compatible = "marvell,pxa250";
+
+ clocks {
+ /*
+ * The muxing of external clocks/internal dividers for osc* clock
+ * sources has been hidden under the carpet by now.
+ */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clks: pxa2xx_clks@41300004 {
+ compatible = "marvell,pxa250-core-clocks";
+ #clock-cells = <1>;
+ status = "okay";
+ };
+
+ /* timer oscillator */
+ clktimer: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <3686400>;
+ clock-output-names = "ostimer";
+ };
+ };
+
+ pxabus {
+ pdma: dma-controller@40000000 {
+ compatible = "marvell,pdma-1.0";
+ reg = <0x40000000 0x10000>;
+ interrupts = <25>;
+ #dma-channels = <16>;
+ #dma-cells = <2>;
+ #dma-requests = <40>;
+ status = "okay";
+ };
+
+ pxairq: interrupt-controller@40d00000 {
+ marvell,intc-priority;
+ marvell,intc-nr-irqs = <32>;
+ };
+
+ pinctrl: pinctrl@40e00000 {
+ reg = <0x40e00054 0x20 0x40e0000c 0xc 0x40e0010c 4
+ 0x40f00020 0x10>;
+ compatible = "marvell,pxa25x-pinctrl";
+ };
+
+ gpio: gpio@40e00000 {
+ compatible = "intel,pxa25x-gpio";
+ gpio-ranges = <&pinctrl 0 0 84>;
+ clocks = <&clks CLK_NONE>;
+ };
+
+ pwm0: pwm@40b00000 {
+ compatible = "marvell,pxa250-pwm";
+ reg = <0x40b00000 0x10>;
+ #pwm-cells = <1>;
+ clocks = <&clks CLK_PWM0>;
+ };
+
+ pwm1: pwm@40b00010 {
+ compatible = "marvell,pxa250-pwm";
+ reg = <0x40b00010 0x10>;
+ #pwm-cells = <1>;
+ clocks = <&clks CLK_PWM1>;
+ };
+ };
+
+ timer@40a00000 {
+ compatible = "marvell,pxa-timer";
+ reg = <0x40a00000 0x20>;
+ interrupts = <26>;
+ clocks = <&clktimer>;
+ status = "okay";
+ };
+};
--
cgit
From 4852a25eab45f375d6e8563aa3192a0a8064011a Mon Sep 17 00:00:00 2001
From: Robert Jarzmik <robert.jarzmik@free.fr>
Date: Mon, 26 Sep 2016 09:22:11 +0200
Subject: ARM: dts: pxa: fix gpio0 and gpio1 interrupts
Since gpio-pxa was redesigned to differenciate gpio0, gpio1 and the
gpio-mux interrupt as in the hardware IP, the device-tree description
should be amended so that interrupts from gpio0 and gpio1 can be mapped
to consumers.
This is especially true on lubbock and mainstone devices where gpio0 is
multiplexed on pxa_cplds for ethernet, sa1111, usb udc, and other
devices.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
---
arch/arm/boot/dts/pxa2xx.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi
index 3ff077ca4400..e4ebcde17837 100644
--- a/arch/arm/boot/dts/pxa2xx.dtsi
+++ b/arch/arm/boot/dts/pxa2xx.dtsi
@@ -54,8 +54,8 @@
reg = <0x40e00000 0x10000>;
gpio-controller;
#gpio-cells = <0x2>;
- interrupts = <10>;
- interrupt-names = "gpio_mux";
+ interrupts = <8>, <9>, <10>;
+ interrupt-names = "gpio0", "gpio1", "gpio_mux";
interrupt-controller;
#interrupt-cells = <0x2>;
ranges;
--
cgit
From 93ab7c84863e31f58d896174a19793cab7bda8de Mon Sep 17 00:00:00 2001
From: Robert Jarzmik <robert.jarzmik@free.fr>
Date: Mon, 31 Oct 2016 20:54:54 +0100
Subject: ARM: dts: pxa: add pxa25x cpu operating points
Add the relevant data taken from the PXA 25x Electrical, Mechanical, and
Thermal Specfication. This will be input data for cpufreq-dt driver.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
---
arch/arm/boot/dts/pxa25x.dtsi | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/pxa25x.dtsi b/arch/arm/boot/dts/pxa25x.dtsi
index 0d1e012178c4..f9f4726396a0 100644
--- a/arch/arm/boot/dts/pxa25x.dtsi
+++ b/arch/arm/boot/dts/pxa25x.dtsi
@@ -89,4 +89,29 @@
clocks = <&clktimer>;
status = "okay";
};
+
+ pxa250_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+
+ opp@99532800 {
+ opp-hz = /bits/ 64 <99532800>;
+ opp-microvolt = <1000000 950000 1650000>;
+ clock-latency-ns = <20>;
+ };
+ opp@199065600 {
+ opp-hz = /bits/ 64 <199065600>;
+ opp-microvolt = <1000000 950000 1650000>;
+ clock-latency-ns = <20>;
+ };
+ opp@298598400 {
+ opp-hz = /bits/ 64 <298598400>;
+ opp-microvolt = <1100000 1045000 1650000>;
+ clock-latency-ns = <20>;
+ };
+ opp@398131200 {
+ opp-hz = /bits/ 64 <398131200>;
+ opp-microvolt = <1300000 1235000 1650000>;
+ clock-latency-ns = <20>;
+ };
+ };
};
--
cgit
From 74e382b870caf297f4e1a727010c9a26cce6b6af Mon Sep 17 00:00:00 2001
From: Robert Jarzmik <robert.jarzmik@free.fr>
Date: Mon, 31 Oct 2016 20:54:55 +0100
Subject: ARM: dts: pxa: add pxa27x cpu operating points
Add the relevant data taken from the PXA27x Electrical, Mechanical, and
Thermal Specfication. This will be input data for cpufreq-dt driver.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
---
arch/arm/boot/dts/pxa27x.dtsi | 40 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/pxa27x.dtsi b/arch/arm/boot/dts/pxa27x.dtsi
index 9e73dc6b3ed3..e0fab48ba6fa 100644
--- a/arch/arm/boot/dts/pxa27x.dtsi
+++ b/arch/arm/boot/dts/pxa27x.dtsi
@@ -137,4 +137,44 @@
clocks = <&clks CLK_OSTIMER>;
status = "okay";
};
+
+ pxa270_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+
+ opp@104000000 {
+ opp-hz = /bits/ 64 <104000000>;
+ opp-microvolt = <900000 900000 1705000>;
+ clock-latency-ns = <20>;
+ };
+ opp@156000000 {
+ opp-hz = /bits/ 64 <156000000>;
+ opp-microvolt = <1000000 1000000 1705000>;
+ clock-latency-ns = <20>;
+ };
+ opp@208000000 {
+ opp-hz = /bits/ 64 <208000000>;
+ opp-microvolt = <1180000 1180000 1705000>;
+ clock-latency-ns = <20>;
+ };
+ opp@312000000 {
+ opp-hz = /bits/ 64 <312000000>;
+ opp-microvolt = <1250000 1250000 1705000>;
+ clock-latency-ns = <20>;
+ };
+ opp@416000000 {
+ opp-hz = /bits/ 64 <416000000>;
+ opp-microvolt = <1350000 1350000 1705000>;
+ clock-latency-ns = <20>;
+ };
+ opp@520000000 {
+ opp-hz = /bits/ 64 <520000000>;
+ opp-microvolt = <1450000 1450000 1705000>;
+ clock-latency-ns = <20>;
+ };
+ opp@624000000 {
+ opp-hz = /bits/ 64 <624000000>;
+ opp-microvolt = <1550000 1550000 1705000>;
+ clock-latency-ns = <20>;
+ };
+ };
};
--
cgit
From 426610dd8cc550ffd947b35c06d3c242cf390008 Mon Sep 17 00:00:00 2001
From: Linus Walleij <linus.walleij@linaro.org>
Date: Wed, 10 Aug 2016 10:38:27 +0200
Subject: ARM: dts: Add Integrator/CP cpus node and operating points
This adds the cpus node to the Integrator/CP device tree so
that we have a proper placeholder to put in the DT-defined
operating points for the generic DT/OPP cpufreq driver,
along with two working operating points.
I have only put in 48 and 50 MHz because going to e.g. 36
MHz hangs the system when CLCD graphics are active.
Presumably the memory bus gets to slow to feed the display
and the systems hangs for this reason. The ideal solution
would be for the display controller to put constraints on
the memory bus frequency, but that need to be a separate
longer-term project.
We define a CPU node since this is required for cpufreq-dt,
however we do not define any compatible string for the CPU
since this architecture has pluggable CPU modules and we
do not know which one will be used. If necessary, the CPU
compatible can be filled in by the boot loader, but for
just cpufreq-dt it is not required.
Cc: Rafael J. Wysocki <rjw@rjwysocki.net>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Russell King <linux@armlinux.org.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
---
arch/arm/boot/dts/integratorcp.dts | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts
index 1b5e4b006b72..97f38b57a702 100644
--- a/arch/arm/boot/dts/integratorcp.dts
+++ b/arch/arm/boot/dts/integratorcp.dts
@@ -13,6 +13,32 @@
bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk";
};
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ /*
+ * Since the board has pluggable CPU modules, we
+ * cannot define a proper compatible here. Let the
+ * boot loader fill in the apropriate compatible
+ * string if necessary.
+ */
+ /* compatible = "arm,arm920t"; */
+ reg = <0>;
+ /*
+ * TBD comment.
+ */
+ /* kHz uV */
+ operating-points = <50000 0
+ 48000 0>;
+ clocks = <&cmcore>;
+ clock-names = "cpu";
+ clock-latency = <1000000>; /* 1 ms */
+ };
+ };
+
/*
* The Integrator/CP overall clocking architecture can be found in
* ARM DUI 0184B page 7-28 "Integrator/CP922T system clocks" which
--
cgit
From 964971c8a3ef34d7d9c5d0be0941e08012e2b784 Mon Sep 17 00:00:00 2001
From: Linus Walleij <linus.walleij@linaro.org>
Date: Thu, 4 Aug 2016 16:21:57 +0200
Subject: ARM: dts: Add Integrator/AP cpus node and operating points
This adds the cpus node to the Integrator/AP device tree so
that we have a proper placeholder to put in the DT-defined
operating points for the generic DT/OPP cpufreq driver,
along with the proper operating points.
The old Integrator cpufreq driver would resolve the max
frequency to 71MHz, and the min frequency to 12 MHz, but
the clock driver can actually handle any frequency inbetween
so I picked a few select frequencies as OPPs. The cpufreq
framework doesn't seem to deal with sliding frequency scales,
only fixed points so 7 OPPs is better than 2 atleast.
We define a CPU node since this is required for cpufreq-dt,
however we do not define any compatible string for the CPU
since this architecture has pluggable CPU modules and we
do not know which one will be used. If necessary, the CPU
compatible can be filled in by the boot loader, but for
just cpufreq-dt it is not required.
Cc: Rafael J. Wysocki <rjw@rjwysocki.net>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Russell King <linux@armlinux.org.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
---
arch/arm/boot/dts/integratorap.dts | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts
index 6f16d09dc5a4..e8b249f92fb3 100644
--- a/arch/arm/boot/dts/integratorap.dts
+++ b/arch/arm/boot/dts/integratorap.dts
@@ -10,6 +10,41 @@
compatible = "arm,integrator-ap";
dma-ranges = <0x80000000 0x0 0x80000000>;
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ /*
+ * Since the board has pluggable CPU modules, we
+ * cannot define a proper compatible here. Let the
+ * boot loader fill in the apropriate compatible
+ * string if necessary.
+ */
+ /* compatible = "arm,arm926ej-s"; */
+ reg = <0>;
+ /*
+ * The documentation in ARM DUI 0138E page 3-12 states
+ * that the maximum frequency for this clock is 200 MHz
+ * but painful trial-and-error has proved to me that it
+ * is actually just hanging the system above 71 MHz.
+ * Sad but true.
+ */
+ /* kHz uV */
+ operating-points = <71000 0
+ 66000 0
+ 60000 0
+ 48000 0
+ 36000 0
+ 24000 0
+ 12000 0>;
+ clocks = <&cmosc>;
+ clock-names = "cpu";
+ clock-latency = <1000000>; /* 1 ms */
+ };
+ };
+
aliases {
arm,timer-primary = &timer2;
arm,timer-secondary = &timer1;
--
cgit
From 8e35c48e70d2a6da915673e8b00db1824931d034 Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzk@kernel.org>
Date: Fri, 18 Nov 2016 14:59:24 +0200
Subject: ARM: dts: exynos: Fix invalid GIC interrupt flags in audio block of
Exynos5410
Recently added audio block of Exynos5410 missed global fixup of GIC
interrupt flags. Interrupt of type IRQ_TYPE_NONE is not allowed for GIC
interrupts so use level high.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
---
arch/arm/boot/dts/exynos5410.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
index 9a91685d8890..081d22bdaa84 100644
--- a/arch/arm/boot/dts/exynos5410.dtsi
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -203,7 +203,7 @@
pdma0: pdma@12680000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x121A0000 0x1000>;
- interrupts = <GIC_SPI 34 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -214,7 +214,7 @@
pdma1: pdma@12690000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x121B0000 0x1000>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
--
cgit
From 3106dba69640cf7003ca8b9de41e6d655ac408c9 Mon Sep 17 00:00:00 2001
From: Neil Armstrong <narmstrong@baylibre.com>
Date: Tue, 23 Aug 2016 13:39:05 +0200
Subject: ARM: dts: Add Sierra Wireless WP8548 dtsi
In order to support the Sierra Wireless WP8548 module based on the
Qualcomm MDM9615 SoC, add a dtsi file.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
---
arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi | 170 +++++++++++++++++++++++++++++
1 file changed, 170 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi b/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi
new file mode 100644
index 000000000000..7869898e392d
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi
@@ -0,0 +1,170 @@
+/*
+ * Device Tree Source for Sierra Wireless WP8548 Module
+ *
+ * Copyright (C) 2016 BayLibre, SAS.
+ * Author : Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "qcom-mdm9615.dtsi"
+
+/ {
+ model = "Sierra Wireless WP8548 Module";
+ compatible = "swir,wp8548", "qcom,mdm9615";
+
+ memory {
+ reg = <0x48000000 0x7F00000>;
+ };
+};
+
+&msmgpio {
+ pinctrl-0 = <&reset_out_pins>;
+ pinctrl-names = "default";
+
+ gsbi3_pins: gsbi3_pins {
+ mux {
+ pins = "gpio8", "gpio9", "gpio10", "gpio11";
+ function = "gsbi3";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
+
+ gsbi4_pins: gsbi4_pins {
+ mux {
+ pins = "gpio12", "gpio13", "gpio14", "gpio15";
+ function = "gsbi4";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
+
+ gsbi5_i2c_pins: gsbi5_i2c_pins {
+ pin16 {
+ pins = "gpio16";
+ function = "gsbi5_i2c";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ pin17 {
+ pins = "gpio17";
+ function = "gsbi5_i2c";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ gsbi5_uart_pins: gsbi5_uart_pins {
+ mux {
+ pins = "gpio18", "gpio19";
+ function = "gsbi5_uart";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
+
+ reset_out_pins: reset_out_pins {
+ pins {
+ pins = "gpio66";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ output-high;
+ };
+ };
+};
+
+&pmicgpio {
+ usb_vbus_5v_pins: usb_vbus_5v_pins {
+ pins = "gpio4";
+ function = "normal";
+ output-high;
+ bias-disable;
+ qcom,drive-strength = <1>;
+ power-source = <2>;
+ };
+};
+
+&gsbi3 {
+ status = "ok";
+ qcom,mode = <GSBI_PROT_SPI>;
+};
+
+&gsbi3_spi {
+ status = "ok";
+ pinctrl-0 = <&gsbi3_pins>;
+ pinctrl-names = "default";
+ assigned-clocks = <&gcc GSBI3_QUP_CLK>;
+ assigned-clock-rates = <24000000>;
+};
+
+&gsbi4 {
+ status = "ok";
+ qcom,mode = <GSBI_PROT_UART_W_FC>;
+};
+
+&gsbi4_serial {
+ status = "ok";
+ pinctrl-0 = <&gsbi4_pins>;
+ pinctrl-names = "default";
+};
+
+&gsbi5 {
+ status = "ok";
+ qcom,mode = <GSBI_PROT_I2C_UART>;
+};
+
+&gsbi5_i2c {
+ status = "ok";
+ clock-frequency = <200000>;
+ pinctrl-0 = <&gsbi5_i2c_pins>;
+ pinctrl-names = "default";
+};
+
+&gsbi5_serial {
+ status = "ok";
+ pinctrl-0 = <&gsbi5_uart_pins>;
+ pinctrl-names = "default";
+};
+
+&sdcc1 {
+ status = "ok";
+};
--
cgit
From 8ab8a8c3945baef7d0c69501590c2bed0cab95d8 Mon Sep 17 00:00:00 2001
From: Neil Armstrong <narmstrong@baylibre.com>
Date: Tue, 23 Aug 2016 13:39:06 +0200
Subject: ARM: dts: Add WP8548 based MangOH Green board DTS
Add support for the Sierra Wireless MangOH Green board with the
Sierra Wireless WP8548 Module.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
---
arch/arm/boot/dts/Makefile | 3 +-
.../boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts | 281 +++++++++++++++++++++
2 files changed, 283 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index befcd2619902..c7f482d634f0 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -620,7 +620,8 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
qcom-msm8974-lge-nexus5-hammerhead.dtb \
- qcom-msm8974-sony-xperia-honami.dtb
+ qcom-msm8974-sony-xperia-honami.dtb \
+ qcom-mdm9615-wp8548-mangoh-green.dtb
dtb-$(CONFIG_ARCH_REALVIEW) += \
arm-realview-pb1176.dtb \
arm-realview-pb11mp.dtb \
diff --git a/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts b/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts
new file mode 100644
index 000000000000..26160c324802
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts
@@ -0,0 +1,281 @@
+/*
+ * Device Tree Source for mangOH Green Board with WP8548 Module
+ *
+ * Copyright (C) 2016 BayLibre, SAS.
+ * Author : Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/input/input.h>
+
+#include "qcom-mdm9615-wp8548.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "MangOH Green with WP8548 Module";
+ compatible = "swir,mangoh-green-wp8548", "swir,wp8548", "qcom,mdm9615";
+
+ aliases {
+ spi0 = &gsbi3_spi;
+ serial0 = &gsbi4_serial;
+ serial1 = &gsbi5_serial;
+ i2c0 = &gsbi5_i2c;
+ mmc0 = &sdcc1;
+ };
+
+ chosen {
+ stdout-path = "serial1:115200n8";
+ };
+};
+
+&msmgpio {
+ /* MangOH GPIO Mapping :
+ * - 2 : GPIOEXP_INT2
+ * - 7 : IOT1_GPIO2
+ * - 8 : IOT0_GPIO4
+ * - 13: IOT0_GPIO3
+ * - 21: IOT1_GPIO4
+ * - 22: IOT2_GPIO1
+ * - 23: IOT2_GPIO2
+ * - 24: IOT2_GPIO3
+ * - 25: IOT1_GPIO1
+ * - 32: IOT1_GPIO3
+ * - 33: IOT0_GPIO2
+ * - 42: IOT0_GPIO1 and SD Card Detect
+ */
+
+ gpioext1_pins: gpioext1_pins {
+ pins {
+ pins = "gpio2";
+ function = "gpio";
+ input-enable;
+ bias-disable;
+ };
+ };
+
+ sdc_cd_pins: sdc_cd_pins {
+ pins {
+ pins = "gpio42";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+};
+
+&gsbi3_spi {
+ spi@0 {
+ compatible = "swir,mangoh-iotport-spi", "spidev";
+ spi-max-frequency = <24000000>;
+ reg = <0>;
+ };
+};
+
+&gsbi5_i2c {
+ mux@71 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x71>;
+
+ i2c_iot0: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c_iot1: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ i2c_iot2: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+
+ usbhub: hub@8 {
+ compatible = "smsc,usb3503a";
+ reg = <0x8>;
+ connect-gpios = <&gpioext2 1 GPIO_ACTIVE_HIGH>;
+ intn-gpios = <&gpioext2 0 GPIO_ACTIVE_LOW>;
+ initial-mode = <1>;
+ };
+ };
+
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+
+ gpioext0: gpio@3e {
+ /* GPIO Expander 0 Mapping :
+ * - 0: ARDUINO_RESET_Level shift
+ * - 1: BattChrgr_PG_N
+ * - 2: BattGauge_GPIO
+ * - 3: LED_ON (out active high)
+ * - 4: ATmega_reset_GPIO
+ * - 5: X
+ * - 6: PCM_ANALOG_SELECT (out active high)
+ * - 7: X
+ * - 8: Board_rev_res1 (in)
+ * - 9: Board_rev_res2 (in)
+ * - 10: UART_EXP1_ENn (out active low / pull-down)
+ * - 11: UART_EXP1_IN (out pull-down)
+ * - 12: UART_EXP2_IN (out pull-down)
+ * - 13: SDIO_SEL (out pull-down)
+ * - 14: SPI_EXP1_ENn (out active low / pull-down)
+ * - 15: SPI_EXP1_IN (out pull-down)
+ */
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ compatible = "semtech,sx1509q";
+ reg = <0x3e>;
+ interrupt-parent = <&gpioext1>;
+ interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
+
+ probe-reset;
+
+ gpio-controller;
+ interrupt-controller;
+ };
+ };
+
+ i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+
+ gpioext1: gpio@3f {
+ /* GPIO Expander 1 Mapping :
+ * - 0: GPIOEXP_INT1
+ * - 1: Battery detect
+ * - 2: GPIO_SCF3_RESET
+ * - 3: LED_CARD_DETECT_IOT0 (in)
+ * - 4: LED_CARD_DETECT_IOT1 (in)
+ * - 5: LED_CARD_DETECT_IOT2 (in)
+ * - 6: UIM2_PWM_SELECT
+ * - 7: UIM2_M2_S_SELECT
+ * - 8: TP900
+ * - 9: SENSOR_INT1 (in)
+ * - 10: SENSOR_INT2 (in)
+ * - 11: CARD_DETECT_IOT0 (in pull-up)
+ * - 12: CARD_DETECT_IOT2 (in pull-up)
+ * - 13: CARD_DETECT_IOT1 (in pull-up)
+ * - 14: GPIOEXP_INT3 (in active low / pull-up)
+ * - 15: BattChrgr_INT_N
+ */
+ pinctrl-0 = <&gpioext1_pins>;
+ pinctrl-names = "default";
+
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ compatible = "semtech,sx1509q";
+ reg = <0x3f>;
+ interrupt-parent = <&msmgpio>;
+ interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
+
+ probe-reset;
+
+ gpio-controller;
+ interrupt-controller;
+ };
+ };
+
+ i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+
+ gpioext2: gpio@70 {
+ /* GPIO Expander 2 Mapping :
+ * - 0: USB_HUB_INTn
+ * - 1: HUB_CONNECT
+ * - 2: GPIO_IOT2_RESET (out active low / pull-up)
+ * - 3: GPIO_IOT1_RESET (out active low / pull-up)
+ * - 4: GPIO_IOT0_RESET (out active low / pull-up)
+ * - 5: TP901
+ * - 6: TP902
+ * - 7: TP903
+ * - 8: UART_EXP2_ENn (out active low / pull-down)
+ * - 9: PCM_EXP1_ENn (out active low)
+ * - 10: PCM_EXP1_SEL (out)
+ * - 11: ARD_FTDI
+ * - 12: TP904
+ * - 13: TP905
+ * - 14: TP906
+ * - 15: RS232_Enable (out active high / pull-up)
+ */
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ compatible = "semtech,sx1509q";
+ reg = <0x70>;
+ interrupt-parent = <&gpioext1>;
+ interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
+
+ probe-reset;
+
+ gpio-controller;
+ interrupt-controller;
+ };
+ };
+
+ i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+ };
+};
+
+&sdcc1 {
+ pinctrl-0 = <&sdc_cd_pins>;
+ pinctrl-names = "default";
+ disable-wp;
+ cd-gpios = <&msmgpio 42 GPIO_ACTIVE_LOW>; /* Active low CD */
+};
--
cgit
From a511e97c495f70bdcc9459d23e259f22c985896a Mon Sep 17 00:00:00 2001
From: Bhushan Shah <bshah@kde.org>
Date: Wed, 20 Jul 2016 11:56:10 +0530
Subject: ARM: dts: qcom: msm8974-hammerhead: Add sdhci1 node
This introduces the eMMC sdhci node and its pinctrl state
Signed-off-by: Bhushan Shah <bshah@kde.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
---
.../dts/qcom-msm8974-lge-nexus5-hammerhead.dts | 29 ++++++++++++++++++++++
1 file changed, 29 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts
index c0fb4a698c56..382bcc3231a9 100644
--- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts
+++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts
@@ -224,6 +224,35 @@
status = "ok";
};
+ pinctrl@fd510000 {
+ sdhc1_pin_a: sdhc1-pin-active {
+ clk {
+ pins = "sdc1_clk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ cmd-data {
+ pins = "sdc1_cmd", "sdc1_data";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ sdhci@f9824900 {
+ status = "ok";
+
+ vmmc-supply = <&pm8941_l20>;
+ vqmmc-supply = <&pm8941_s3>;
+
+ bus-width = <8>;
+ non-removable;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhc1_pin_a>;
+ };
+
gpio-keys {
compatible = "gpio-keys";
input-name = "gpio-keys";
--
cgit
From e77a3a7841f58cae5249e69db8521a04d8be6f25 Mon Sep 17 00:00:00 2001
From: Archit Taneja <architt@codeaurora.org>
Date: Fri, 23 Sep 2016 12:03:06 +0530
Subject: arm: dts: qcom: apq8064: Add display DT nodes
APQ8064 contains a MDP4 based display controller. It contains a HDMI, LVDS
and 2 DSI outputs.
Add display DT nodes for MDP4, HDMI TX and HDMI PHY. MDP4 based display
blocks have a flat device hierarchy.
Nodes for other outputs will be added later.
Cc: devicetree@vger.kernel.org
Tested-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 91 +++++++++++++++++++++++++++++++++++++
1 file changed, 91 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 1dbe697b2e90..5b3aaaa7a588 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -1095,6 +1095,97 @@
reset-names = "axi", "ahb", "por", "pci", "phy";
status = "disabled";
};
+
+ hdmi: hdmi-tx@4a00000 {
+ compatible = "qcom,hdmi-tx-8960";
+ reg = <0x04a00000 0x2f0>;
+ reg-names = "core_physical";
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mmcc HDMI_APP_CLK>,
+ <&mmcc HDMI_M_AHB_CLK>,
+ <&mmcc HDMI_S_AHB_CLK>;
+ clock-names = "core_clk",
+ "master_iface_clk",
+ "slave_iface_clk";
+
+ phys = <&hdmi_phy>;
+ phy-names = "hdmi-phy";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ hdmi_in: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ hdmi_out: endpoint {
+ };
+ };
+ };
+ };
+
+ hdmi_phy: hdmi-phy@4a00400 {
+ compatible = "qcom,hdmi-phy-8960";
+ reg = <0x4a00400 0x60>,
+ <0x4a00500 0x100>;
+ reg-names = "hdmi_phy",
+ "hdmi_pll";
+
+ clocks = <&mmcc HDMI_S_AHB_CLK>;
+ clock-names = "slave_iface_clk";
+ };
+
+ mdp: mdp@5100000 {
+ compatible = "qcom,mdp4";
+ reg = <0x05100000 0xf0000>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mmcc MDP_CLK>,
+ <&mmcc MDP_AHB_CLK>,
+ <&mmcc MDP_AXI_CLK>,
+ <&mmcc MDP_LUT_CLK>,
+ <&mmcc HDMI_TV_CLK>,
+ <&mmcc MDP_TV_CLK>;
+ clock-names = "core_clk",
+ "iface_clk",
+ "bus_clk",
+ "lut_clk",
+ "hdmi_clk",
+ "tv_clk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdp_lvds_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ mdp_dsi1_out: endpoint {
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ mdp_dsi2_out: endpoint {
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ mdp_dtv_out: endpoint {
+ };
+ };
+ };
+ };
};
};
#include "qcom-apq8064-pins.dtsi"
--
cgit
From c809801d4ceb5185b1c670562a94aef6defe9a70 Mon Sep 17 00:00:00 2001
From: Archit Taneja <architt@codeaurora.org>
Date: Fri, 23 Sep 2016 12:03:07 +0530
Subject: arm: dts: qcom: apq8064-ifc6410: Add HDMI support
Add HDMI support on IFC6410. Populate the regulators required by HDMI-TX
and PHY. Establish the link between the MDP4 DTV encoder and HDMI. Create
a generic micro HDMI connector DT node. The msm drm driver doesn't parse
for HDMI connectors in DT, but it will do so later.
Cc: devicetree@vger.kernel.org
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
---
arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 74 ++++++++++++++++++++++++++++++
1 file changed, 74 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
index 2eeb0904eaa7..3d37cab3b9a9 100644
--- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
@@ -43,6 +43,17 @@
};
};
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "d";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <&hdmi_out>;
+ };
+ };
+ };
+
soc {
pinctrl@800000 {
card_detect: card_detect {
@@ -64,6 +75,25 @@
bias-disable;
};
};
+
+ hdmi_pinctrl: hdmi-pinctrl {
+ mux {
+ pins = "gpio70", "gpio71", "gpio72";
+ function = "hdmi";
+ };
+
+ pinconf_ddc {
+ pins = "gpio70", "gpio71";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ pinconf_hpd {
+ pins = "gpio72";
+ bias-pull-down;
+ drive-strength = <16>;
+ };
+ };
};
rpm@108000 {
@@ -329,5 +359,49 @@
mmc-pwrseq = <&sdcc4_pwrseq>;
};
};
+
+ hdmi-tx@4a00000 {
+ status = "okay";
+
+ core-vdda-supply = <&pm8921_hdmi_switch>;
+ hdmi-mux-supply = <&ext_3p3v>;
+
+ hpd-gpios = <&tlmm_pinmux 72 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pinctrl>;
+
+ ports {
+ port@0 {
+ endpoint {
+ remote-endpoint = <&mdp_dtv_out>;
+ };
+ };
+
+ port@1 {
+ endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+ };
+ };
+
+ hdmi-phy@4a00400 {
+ status = "okay";
+
+ core-vdda-supply = <&pm8921_hdmi_switch>;
+ };
+
+ mdp@5100000 {
+ status = "okay";
+
+ ports {
+ port@3 {
+ endpoint {
+ remote-endpoint = <&hdmi_in>;
+ };
+ };
+ };
+ };
};
};
--
cgit
From f078eac68e8da3689385d96262caa10ca1ff0e0a Mon Sep 17 00:00:00 2001
From: John Stultz <john.stultz@linaro.org>
Date: Fri, 23 Sep 2016 17:01:04 -0700
Subject: arm: dts: qcom: apq8064: Add dsi, gpu and iommu nodes
Adds the core gpu, and dsi nodes for the apq8064 needed
to get graphics working on the nexus7 and other devices.
These apply on top of Archit's patch set that enables HDMI for IFC6410
Feedback would be greatly appreciated!
Cc: Archit Taneja <architt@codeaurora.org>
Cc: vinay simha <vinaysimha@inforcecomputing.com>
Cc: andy.gross@linaro.org
Cc: robdclark@gmail.com
Cc: linux-arm-msm@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 230 ++++++++++++++++++++++++++++++++++++
1 file changed, 230 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 5b3aaaa7a588..268bd470c865 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -1060,6 +1060,231 @@
reg = <0x1a400000 0x100>;
};
+ gpu: adreno-3xx@4300000 {
+ compatible = "qcom,adreno-3xx";
+ reg = <0x04300000 0x20000>;
+ reg-names = "kgsl_3d0_reg_memory";
+ interrupts = <GIC_SPI 80 0>;
+ interrupt-names = "kgsl_3d0_irq";
+ clock-names =
+ "core_clk",
+ "iface_clk",
+ "mem_clk",
+ "mem_iface_clk";
+ clocks =
+ <&mmcc GFX3D_CLK>,
+ <&mmcc GFX3D_AHB_CLK>,
+ <&mmcc GFX3D_AXI_CLK>,
+ <&mmcc MMSS_IMEM_AHB_CLK>;
+ qcom,chipid = <0x03020002>;
+
+ iommus = <&gfx3d 0
+ &gfx3d 1
+ &gfx3d 2
+ &gfx3d 3
+ &gfx3d 4
+ &gfx3d 5
+ &gfx3d 6
+ &gfx3d 7
+ &gfx3d 8
+ &gfx3d 9
+ &gfx3d 10
+ &gfx3d 11
+ &gfx3d 12
+ &gfx3d 13
+ &gfx3d 14
+ &gfx3d 15
+ &gfx3d 16
+ &gfx3d 17
+ &gfx3d 18
+ &gfx3d 19
+ &gfx3d 20
+ &gfx3d 21
+ &gfx3d 22
+ &gfx3d 23
+ &gfx3d 24
+ &gfx3d 25
+ &gfx3d 26
+ &gfx3d 27
+ &gfx3d 28
+ &gfx3d 29
+ &gfx3d 30
+ &gfx3d 31
+ &gfx3d1 0
+ &gfx3d1 1
+ &gfx3d1 2
+ &gfx3d1 3
+ &gfx3d1 4
+ &gfx3d1 5
+ &gfx3d1 6
+ &gfx3d1 7
+ &gfx3d1 8
+ &gfx3d1 9
+ &gfx3d1 10
+ &gfx3d1 11
+ &gfx3d1 12
+ &gfx3d1 13
+ &gfx3d1 14
+ &gfx3d1 15
+ &gfx3d1 16
+ &gfx3d1 17
+ &gfx3d1 18
+ &gfx3d1 19
+ &gfx3d1 20
+ &gfx3d1 21
+ &gfx3d1 22
+ &gfx3d1 23
+ &gfx3d1 24
+ &gfx3d1 25
+ &gfx3d1 26
+ &gfx3d1 27
+ &gfx3d1 28
+ &gfx3d1 29
+ &gfx3d1 30
+ &gfx3d1 31>;
+
+ qcom,gpu-pwrlevels {
+ compatible = "qcom,gpu-pwrlevels";
+ qcom,gpu-pwrlevel@0 {
+ qcom,gpu-freq = <450000000>;
+ };
+ qcom,gpu-pwrlevel@1 {
+ qcom,gpu-freq = <27000000>;
+ };
+ };
+ };
+
+ mmss_sfpb: syscon@5700000 {
+ compatible = "syscon";
+ reg = <0x5700000 0x70>;
+ };
+
+ dsi0: mdss_dsi@4700000 {
+ compatible = "qcom,mdss-dsi-ctrl";
+ label = "MDSS DSI CTRL->0";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 82 0>;
+ reg = <0x04700000 0x200>;
+ reg-names = "dsi_ctrl";
+
+ clocks = <&mmcc DSI_M_AHB_CLK>,
+ <&mmcc DSI_S_AHB_CLK>,
+ <&mmcc AMP_AHB_CLK>,
+ <&mmcc DSI_CLK>,
+ <&mmcc DSI1_BYTE_CLK>,
+ <&mmcc DSI_PIXEL_CLK>,
+ <&mmcc DSI1_ESC_CLK>;
+ clock-names = "iface_clk", "bus_clk", "core_mmss_clk",
+ "src_clk", "byte_clk", "pixel_clk",
+ "core_clk";
+
+ assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
+ <&mmcc DSI1_ESC_SRC>,
+ <&mmcc DSI_SRC>,
+ <&mmcc DSI_PIXEL_SRC>;
+ assigned-clock-parents = <&dsi0_phy 0>,
+ <&dsi0_phy 0>,
+ <&dsi0_phy 1>,
+ <&dsi0_phy 1>;
+ syscon-sfpb = <&mmss_sfpb>;
+ phys = <&dsi0_phy>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ };
+ };
+ };
+ };
+
+
+ dsi0_phy: dsi-phy@4700200 {
+ compatible = "qcom,dsi-phy-28nm-8960";
+ #clock-cells = <1>;
+
+ reg = <0x04700200 0x100>,
+ <0x04700300 0x200>,
+ <0x04700500 0x5c>;
+ reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
+ clock-names = "iface_clk";
+ clocks = <&mmcc DSI_M_AHB_CLK>;
+ };
+
+
+ mdp_port0: iommu@7500000 {
+ compatible = "qcom,apq8064-iommu";
+ #iommu-cells = <1>;
+ clock-names =
+ "smmu_pclk",
+ "iommu_clk";
+ clocks =
+ <&mmcc SMMU_AHB_CLK>,
+ <&mmcc MDP_AXI_CLK>;
+ reg = <0x07500000 0x100000>;
+ interrupts =
+ <GIC_SPI 63 0>,
+ <GIC_SPI 64 0>;
+ qcom,ncb = <2>;
+ };
+
+ mdp_port1: iommu@7600000 {
+ compatible = "qcom,apq8064-iommu";
+ #iommu-cells = <1>;
+ clock-names =
+ "smmu_pclk",
+ "iommu_clk";
+ clocks =
+ <&mmcc SMMU_AHB_CLK>,
+ <&mmcc MDP_AXI_CLK>;
+ reg = <0x07600000 0x100000>;
+ interrupts =
+ <GIC_SPI 61 0>,
+ <GIC_SPI 62 0>;
+ qcom,ncb = <2>;
+ };
+
+ gfx3d: iommu@7c00000 {
+ compatible = "qcom,apq8064-iommu";
+ #iommu-cells = <1>;
+ clock-names =
+ "smmu_pclk",
+ "iommu_clk";
+ clocks =
+ <&mmcc SMMU_AHB_CLK>,
+ <&mmcc GFX3D_AXI_CLK>;
+ reg = <0x07c00000 0x100000>;
+ interrupts =
+ <GIC_SPI 69 0>,
+ <GIC_SPI 70 0>;
+ qcom,ncb = <3>;
+ };
+
+ gfx3d1: iommu@7d00000 {
+ compatible = "qcom,apq8064-iommu";
+ #iommu-cells = <1>;
+ clock-names =
+ "smmu_pclk",
+ "iommu_clk";
+ clocks =
+ <&mmcc SMMU_AHB_CLK>,
+ <&mmcc GFX3D_AXI_CLK>;
+ reg = <0x07d00000 0x100000>;
+ interrupts =
+ <GIC_SPI 210 0>,
+ <GIC_SPI 211 0>;
+ qcom,ncb = <3>;
+ };
+
pcie: pci@1b500000 {
compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
reg = <0x1b500000 0x1000
@@ -1157,6 +1382,11 @@
"hdmi_clk",
"tv_clk";
+ iommus = <&mdp_port0 0
+ &mdp_port0 2
+ &mdp_port1 0
+ &mdp_port1 2>;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
--
cgit
From a3e6e13addee8335926e4e5ea4e8f5caf98e783c Mon Sep 17 00:00:00 2001
From: John Stultz <john.stultz@linaro.org>
Date: Fri, 23 Sep 2016 17:01:05 -0700
Subject: arm: dts: qcom: apq8064-nexus7: Add DSI and panel nodes
Add DSI and panel nodes to get graphics up and running
on the Nexus7.
This still depends on the panel driver being present
along with the rpmclk code.
Feedback would be greatly appreciated!
Cc: Archit Taneja <architt@codeaurora.org>
Cc: vinay simha <vinaysimha@inforcecomputing.com>
Cc: andy.gross@linaro.org
Cc: robdclark@gmail.com
Cc: linux-arm-msm@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
---
arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts | 63 +++++++++++++++++++++-
1 file changed, 61 insertions(+), 2 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts
index b72e09506448..4225652aa880 100644
--- a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts
@@ -99,6 +99,7 @@
l2 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
+ regulator-always-on;
};
/* msm_otg-HSUSB_3p3 */
@@ -133,13 +134,14 @@
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
bias-pull-down;
+ regulator-always-on;
};
/* pwm_power for backlight */
l17 {
regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3600000>;
- bias-pull-down;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
};
/* camera, qdsp6 */
@@ -184,6 +186,63 @@
};
};
+ mdp@5100000 {
+ status = "okay";
+ ports {
+ port@1 {
+ mdp_dsi1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+ };
+ };
+
+ dsi0: mdss_dsi@4700000 {
+ status = "okay";
+ vdda-supply = <&pm8921_l2>;/*VDD_MIPI1 to 4*/
+ vdd-supply = <&pm8921_l8>;
+ vddio-supply = <&pm8921_lvs7>;
+ avdd-supply = <&pm8921_l11>;
+ vcss-supply = <&ext_3p3v>;
+
+ panel@0 {
+ reg = <0>;
+ compatible = "jdi,lt070me05000";
+
+ vddp-supply = <&pm8921_l17>;
+ iovcc-supply = <&pm8921_lvs7>;
+
+ enable-gpios = <&pm8921_gpio 36 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&tlmm_pinmux 54 GPIO_ACTIVE_LOW>;
+ dcdc-en-gpios = <&pm8921_gpio 23 GPIO_ACTIVE_HIGH>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+ };
+ ports {
+ port@0 {
+ dsi0_in: endpoint {
+ remote-endpoint = <&mdp_dsi1_out>;
+ };
+ };
+
+ port@1 {
+ dsi0_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ data-lanes = <0 1 2 3>;
+ };
+ };
+ };
+ };
+
+ dsi-phy@4700200 {
+ status = "okay";
+ vddio-supply = <&pm8921_lvs7>;/*VDD_PLL2_1 to 7*/
+ };
+
gsbi@16200000 {
status = "okay";
qcom,mode = <GSBI_PROT_I2C>;
--
cgit
From 663286e7e63caaed74718d1919500646fd2ceb1b Mon Sep 17 00:00:00 2001
From: John Stultz <john.stultz@linaro.org>
Date: Fri, 23 Sep 2016 17:13:33 -0700
Subject: arm: dts: qcom: apq8064-nexus7: Add pstore support to nexus7
Add pstore support for the nexus7. This was useful in debugging
a crash where the cpus were getting stuck with irqs off and
serial output wasn't reliably working.
Cc: Kees Cook <keescook@chromium.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Clark <robdclark@gmail.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Andy Gross <andy.gross@linaro.org>
Cc: Vinay Simha <vinaysimha@inforcecomputing.com>
Cc: Archit Taneja <architt@codeaurora.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
---
arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts | 14 ++++++++++++++
1 file changed, 14 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts
index 4225652aa880..e39440a86739 100644
--- a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts
@@ -15,6 +15,20 @@
stdout-path = "serial0:115200n8";
};
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ ramoops@88d00000{
+ compatible = "ramoops";
+ reg = <0x88d00000 0x100000>;
+ record-size = <0x00020000>;
+ console-size = <0x00020000>;
+ ftrace-size = <0x00020000>;
+ };
+ };
+
ext_3p3v: regulator-fixed@1 {
compatible = "regulator-fixed";
regulator-min-microvolt = <3300000>;
--
cgit
From e3770594c4c8db041b1d385234aaa911734dd0b8 Mon Sep 17 00:00:00 2001
From: Linus Walleij <linus.walleij@linaro.org>
Date: Tue, 25 Oct 2016 00:22:12 +0200
Subject: ARM: dts: add EBI2 to the Qualcomm MSM8660 DTSI
This adds the external bus interface EBI2 to the MSM8660 device
tree, albeit with status = "disabled" so that devices actually
using EBI2 can turn it on if needed.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
---
arch/arm/boot/dts/qcom-msm8660.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi
index 8c65e0d82559..4d828f810746 100644
--- a/arch/arm/boot/dts/qcom-msm8660.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
@@ -141,6 +141,23 @@
};
};
+ external-bus@1a100000 {
+ compatible = "qcom,msm8660-ebi2";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x1a800000 0x00800000>,
+ <1 0x0 0x1b000000 0x00800000>,
+ <2 0x0 0x1b800000 0x00800000>,
+ <3 0x0 0x1d000000 0x08000000>,
+ <4 0x0 0x1c800000 0x00800000>,
+ <5 0x0 0x1c000000 0x00800000>;
+ reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
+ reg-names = "ebi2", "xmem";
+ clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
+ clock-names = "ebi2x", "ebi2";
+ status = "disabled";
+ };
+
qcom,ssbi@500000 {
compatible = "qcom,ssbi";
reg = <0x500000 0x1000>;
--
cgit
From 4c52ffc708c90b2985f941db5490145530e4df69 Mon Sep 17 00:00:00 2001
From: Linus Walleij <linus.walleij@linaro.org>
Date: Tue, 25 Oct 2016 00:22:20 +0200
Subject: ARM: dts: add SMSC ethernet on the APQ8060 Dragonboard
The SMSC9112 ethernet controller is connected to chip select 2
on the EBI2 bus on the APQ8060 Dragonboard. We set this up by
activating EBI2, creating a chipselect entry as a subnode, and then
putting the ethernet controller in a subnode of the chipselect.
After the chipselect is configured, the SMSC device will be
instantiated.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
---
arch/arm/boot/dts/qcom-apq8060-dragonboard.dts | 119 +++++++++++++++++++++++++
1 file changed, 119 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts
index 6c0038398ef2..4b8872cc8bf9 100644
--- a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts
+++ b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts
@@ -51,6 +51,29 @@
regulator-boot-on;
};
+ /* GPIO controlled ethernet power regulator */
+ dragon_veth: xc622a331mrg {
+ compatible = "regulator-fixed";
+ regulator-name = "XC6222A331MR-G";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vph>;
+ gpio = <&pm8058_gpio 40 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ pinctrl-names = "default";
+ pinctrl-0 = <&dragon_veth_gpios>;
+ regulator-always-on;
+ };
+
+ /* VDDvario fixed regulator */
+ dragon_vario: nds332p {
+ compatible = "regulator-fixed";
+ regulator-name = "NDS332P";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&pm8058_s3>;
+ };
+
/* This is a levelshifter for SDCC5 */
dragon_vio_txb: txb0104rgyr {
compatible = "regulator-fixed";
@@ -167,6 +190,36 @@
bias-pull-up;
};
};
+
+ dragon_ebi2_pins: ebi2 {
+ /*
+ * Pins used by EBI2 on the Dragonboard, actually only
+ * CS2 is used by a real peripheral. CS0 is just
+ * routed to a test point.
+ */
+ mux0 {
+ pins =
+ /* "gpio39", CS1A_N this is not good to mux */
+ "gpio40", /* CS2A_N */
+ "gpio134"; /* CS0_N testpoint TP29 */
+ function = "ebi2cs";
+ };
+ mux1 {
+ pins =
+ /* EBI2_ADDR_7 downto EBI2_ADDR_0 address bus */
+ "gpio123", "gpio124", "gpio125", "gpio126",
+ "gpio127", "gpio128", "gpio129", "gpio130",
+ /* EBI2_DATA_15 downto EBI2_DATA_0 data bus */
+ "gpio135", "gpio136", "gpio137", "gpio138",
+ "gpio139", "gpio140", "gpio141", "gpio142",
+ "gpio143", "gpio144", "gpio145", "gpio146",
+ "gpio147", "gpio148", "gpio149", "gpio150",
+ "gpio151", /* EBI2_OE_N */
+ "gpio153", /* EBI2_ADV */
+ "gpio157"; /* EBI2_WE_N */
+ function = "ebi2";
+ };
+ };
};
qcom,ssbi@500000 {
@@ -201,6 +254,15 @@
};
gpio@150 {
+ dragon_ethernet_gpios: ethernet-gpios {
+ pinconf {
+ pins = "gpio7";
+ function = "normal";
+ input-enable;
+ bias-disable;
+ power-source = <PM8058_GPIO_S3>;
+ };
+ };
dragon_bmp085_gpios: bmp085-gpios {
pinconf {
pins = "gpio16";
@@ -238,6 +300,14 @@
power-source = <PM8058_GPIO_S3>;
};
};
+ dragon_veth_gpios: veth-gpios {
+ pinconf {
+ pins = "gpio40";
+ function = "normal";
+ bias-disable;
+ drive-push-pull;
+ };
+ };
};
led@48 {
@@ -322,6 +392,55 @@
};
};
+ external-bus@1a100000 {
+ /* The EBI2 will instantiate first, then populate its children */
+ status = "ok";
+ pinctrl-names = "default";
+ pinctrl-0 = <&dragon_ebi2_pins>;
+
+ /*
+ * An on-board SMSC LAN9221 chip for "debug ethernet",
+ * which is actually just an ordinary ethernet on the
+ * EBI2. This has a 25MHz chrystal next to it, so no
+ * clocking is needed.
+ */
+ ethernet-ebi2@2,0 {
+ compatible = "smsc,lan9221", "smsc,lan9115";
+ reg = <2 0x0 0x100>;
+ /*
+ * GPIO7 has interrupt 198 on the PM8058
+ * The second interrupt is the PME interrupt
+ * for network wakeup, connected to the TLMM.
+ */
+ interrupts-extended = <&pmicintc 198 IRQ_TYPE_EDGE_FALLING>,
+ <&tlmm 29 IRQ_TYPE_EDGE_RISING>;
+ reset-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
+ vdd33a-supply = <&dragon_veth>;
+ vddvario-supply = <&dragon_vario>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&dragon_ethernet_gpios>;
+ phy-mode = "mii";
+ reg-io-width = <2>;
+ smsc,force-external-phy;
+ /* IRQ on edge falling = active low */
+ smsc,irq-active-low;
+ smsc,irq-push-pull;
+
+ /*
+ * SLOW chipselect config
+ * Delay 9 cycles (140ns@64MHz) between SMSC
+ * LAN9221 Ethernet controller reads and writes
+ * on CS2.
+ */
+ qcom,xmem-recovery-cycles = <0>;
+ qcom,xmem-write-hold-cycles = <3>;
+ qcom,xmem-write-delta-cycles = <31>;
+ qcom,xmem-read-delta-cycles = <28>;
+ qcom,xmem-write-wait-cycles = <9>;
+ qcom,xmem-read-wait-cycles = <9>;
+ };
+ };
+
rpm@104000 {
/*
* Set up of the PMIC RPM regulators for this board
--
cgit
From f94f268979a2aaeb5842c5b24ed7d44497f7753c Mon Sep 17 00:00:00 2001
From: Ashley Hughes <ashley.hughes@blueyonder.co.uk>
Date: Sat, 19 Nov 2016 08:10:27 +0100
Subject: ARM: dts: orion5x: convert ls-chl to FDT
This patch converts my orion5x ls-chl Linkstation device to device tree.
[gregory.clement@free-electrons.com: fix title, add back the commit log,
move the removal of the platform in an other patch]
Signed-off-by: Ashley Hughes <ashley.hughes@blueyonder.co.uk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/orion5x-lschl.dts | 171 ++++++++++++++++++++++++++++++++++++
2 files changed, 172 insertions(+)
create mode 100644 arch/arm/boot/dts/orion5x-lschl.dts
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index befcd2619902..485304914916 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -597,6 +597,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
orion5x-lacie-ethernet-disk-mini-v2.dtb \
orion5x-linkstation-lsgl.dtb \
orion5x-linkstation-lswtgl.dtb \
+ orion5x-lschl.dtb \
orion5x-lswsgl.dtb \
orion5x-maxtor-shared-storage-2.dtb \
orion5x-netgear-wnr854t.dtb \
diff --git a/arch/arm/boot/dts/orion5x-lschl.dts b/arch/arm/boot/dts/orion5x-lschl.dts
new file mode 100644
index 000000000000..947409252845
--- /dev/null
+++ b/arch/arm/boot/dts/orion5x-lschl.dts
@@ -0,0 +1,171 @@
+/*
+ * Device Tree file for Buffalo Linkstation LS-CHLv3
+ *
+ * Copyright (C) 2016 Ash Hughes <ashley.hughes@blueyonder.co.uk>
+ * Copyright (C) 2015, 2016
+ * Roger Shimizu <rogershimizu@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "orion5x-linkstation.dtsi"
+#include "mvebu-linkstation-gpio-simple.dtsi"
+#include "mvebu-linkstation-fan.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Buffalo Linkstation Live v3 (LS-CHL)";
+ compatible = "buffalo,lschl", "marvell,orion5x-88f5182", "marvell,orion5x";
+
+ memory { /* 128 MB */
+ device_type = "memory";
+ reg = <0x00000000 0x8000000>;
+ };
+
+ gpio_keys {
+ func {
+ label = "Function Button";
+ linux,code = <KEY_OPTION>;
+ gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
+ };
+
+ power-on-switch {
+ gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
+ };
+
+ power-auto-switch {
+ gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio_leds {
+ pinctrl-0 = <&pmx_led_power &pmx_led_alarm &pmx_led_info &pmx_led_func>;
+ blue-power-led {
+ gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
+ };
+
+ red-alarm-led {
+ gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+ };
+
+ amber-info-led {
+ gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
+ };
+
+ func {
+ label = "lschl:func:blue:top";
+ gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio_fan {
+ gpios = <&gpio0 14 GPIO_ACTIVE_LOW
+ &gpio0 16 GPIO_ACTIVE_LOW>;
+
+ alarm-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&pinctrl {
+ pmx_led_power: pmx-leds {
+ marvell,pins = "mpp0";
+ marvell,function = "gpio";
+ };
+
+ pmx_power_hdd: pmx-power-hdd {
+ marvell,pins = "mpp1";
+ marvell,function = "gpio";
+ };
+
+ pmx_led_alarm: pmx-leds {
+ marvell,pins = "mpp2";
+ marvell,function = "gpio";
+ };
+
+ pmx_led_info: pmx-leds {
+ marvell,pins = "mpp3";
+ marvell,function = "gpio";
+ };
+
+ pmx_fan_lock: pmx-fan-lock {
+ marvell,pins = "mpp6";
+ marvell,function = "gpio";
+ };
+
+ pmx_power_switch: pmx-power-switch {
+ marvell,pins = "mpp8", "mpp10", "mpp15";
+ marvell,function = "gpio";
+ };
+
+ pmx_power_usb: pmx-power-usb {
+ marvell,pins = "mpp9";
+ marvell,function = "gpio";
+ };
+
+ pmx_fan_high: pmx-fan-high {
+ marvell,pins = "mpp14";
+ marvell,function = "gpio";
+ };
+
+ pmx_fan_low: pmx-fan-low {
+ marvell,pins = "mpp16";
+ marvell,function = "gpio";
+ };
+
+ pmx_led_func: pmx-leds {
+ marvell,pins = "mpp17";
+ marvell,function = "gpio";
+ };
+
+ pmx_sw_init: pmx-sw-init {
+ marvell,pins = "mpp7";
+ marvell,function = "gpio";
+ };
+};
+
+&hdd_power {
+ gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
+};
+
+&usb_power {
+ gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+};
+
--
cgit
From 95430414c7edaa434bb7840a2ab1a1ef640a943c Mon Sep 17 00:00:00 2001
From: Paul Wassi <p.wassi@gmx.at>
Date: Thu, 17 Nov 2016 21:29:47 +0100
Subject: ARM: dts: kirkwood: fix spelling mistake
Fix a spelling mistake in arch/arm/boot/dts/kirkwood-topkick.dts.
The manufacturer's name is Univer*s*al Scientific Industrial...
Compare with footer of page here:
http://www.usish.com/english/products_topkick1281p2.php
Signed-off-by: Paul Wassi <p.wassi@gmx.at>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm/boot/dts/kirkwood-topkick.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts
index 1e9a72100a45..330aada6d33f 100644
--- a/arch/arm/boot/dts/kirkwood-topkick.dts
+++ b/arch/arm/boot/dts/kirkwood-topkick.dts
@@ -4,7 +4,7 @@
#include "kirkwood-6282.dtsi"
/ {
- model = "Univeral Scientific Industrial Co. Topkick-1281P2";
+ model = "Universal Scientific Industrial Co. Topkick-1281P2";
compatible = "usi,topkick-1281P2", "usi,topkick", "marvell,kirkwood-88f6282", "marvell,kirkwood";
memory {
--
cgit
From 1a9cd8f36d0617630b4f0ae2601fe5600edff109 Mon Sep 17 00:00:00 2001
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
Date: Sun, 6 Nov 2016 22:52:39 +0100
Subject: ARM: dts: armada-xp-matrix: Fix the location of the pcie-controller
node
In the dts for the Marvell Armada XP Matrix board the pcie-controller was
located under the internal-regs node whereas it belongs to the soc node.
It means that, until this fix, the pcie could not work for this board
because it didn't match the definition of the pcie-controller node in the
dtsi file. If we had a look on the decompiled dtb file we saw two
different instances of the pcie-controller node: one with the all the
resource set but disabled and the other without any resource but enabled.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm/boot/dts/armada-xp-matrix.dts | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/armada-xp-matrix.dts b/arch/arm/boot/dts/armada-xp-matrix.dts
index 6522b04f4a8e..e1509f4c5114 100644
--- a/arch/arm/boot/dts/armada-xp-matrix.dts
+++ b/arch/arm/boot/dts/armada-xp-matrix.dts
@@ -71,6 +71,15 @@
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
+ pcie-controller {
+ status = "okay";
+
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+ };
+
internal-regs {
serial@12000 {
status = "okay";
@@ -99,15 +108,6 @@
};
};
- pcie-controller {
- status = "okay";
-
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
- };
-
usb@50000 {
status = "okay";
};
--
cgit
From e72996b80d53b9b7616c8b68304ce4c422b4ddd1 Mon Sep 17 00:00:00 2001
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
Date: Fri, 4 Nov 2016 15:50:33 +0100
Subject: ARM: dts: armada-370-xp: move the cpurst node in the common file
The cpurst nodes are identical in armada-370.dtsi and armada-xp.dtsi
files, so move it in the common armada-370-xp.dtsi file.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm/boot/dts/armada-370-xp.dtsi | 5 +++++
arch/arm/boot/dts/armada-370.dtsi | 5 -----
arch/arm/boot/dts/armada-xp.dtsi | 1 -
3 files changed, 5 insertions(+), 6 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 3ccedc9dffb2..1d8171380fa0 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -228,6 +228,11 @@
reg = <0x20300 0x34>, <0x20704 0x4>;
};
+ cpurst@20800 {
+ compatible = "marvell,armada-370-cpu-reset";
+ reg = <0x20800 0x8>;
+ };
+
pmsu@22000 {
compatible = "marvell,armada-370-pmsu";
reg = <0x22000 0x1000>;
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index b4258105e91f..79b5463209aa 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -233,11 +233,6 @@
clocks = <&coreclk 2>;
};
- cpurst@20800 {
- compatible = "marvell,armada-370-cpu-reset";
- reg = <0x20800 0x8>;
- };
-
cpu-config@21000 {
compatible = "marvell,armada-370-cpu-config";
reg = <0x21000 0x8>;
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 4a5f99e65b51..e141de2a4a1c 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -167,7 +167,6 @@
};
cpurst@20800 {
- compatible = "marvell,armada-370-cpu-reset";
reg = <0x20800 0x20>;
};
--
cgit
From 11f7135bb9dbe7ae3bb9a125e6123d4096a7e69e Mon Sep 17 00:00:00 2001
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
Date: Fri, 4 Nov 2016 16:27:03 +0100
Subject: ARM: dts: armada-370-xp: add node labels
As it was previously done for kirkwood, this adds missing node labels to
Armada 370 and XP common and SoC specific nodes to allow to reference
them more easily.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm/boot/dts/armada-370-xp.dtsi | 32 ++++++++++++++++----------------
arch/arm/boot/dts/armada-370.dtsi | 20 ++++++++++----------
arch/arm/boot/dts/armada-xp-mv78230.dtsi | 12 ++++++------
arch/arm/boot/dts/armada-xp-mv78260.dtsi | 20 ++++++++++----------
arch/arm/boot/dts/armada-xp-mv78460.dtsi | 22 +++++++++++-----------
arch/arm/boot/dts/armada-xp.dtsi | 12 ++++++------
6 files changed, 59 insertions(+), 59 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 1d8171380fa0..54359896b76c 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -86,7 +86,7 @@
pcie-mem-aperture = <0xf8000000 0x7e00000>;
pcie-io-aperture = <0xffe00000 0x100000>;
- devbus-bootcs {
+ devbus_bootcs: devbus-bootcs {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
@@ -96,7 +96,7 @@
status = "disabled";
};
- devbus-cs0 {
+ devbus_cs0: devbus-cs0 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
@@ -106,7 +106,7 @@
status = "disabled";
};
- devbus-cs1 {
+ devbus_cs1: devbus-cs1 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
@@ -116,7 +116,7 @@
status = "disabled";
};
- devbus-cs2 {
+ devbus_cs2: devbus-cs2 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
@@ -126,7 +126,7 @@
status = "disabled";
};
- devbus-cs3 {
+ devbus_cs3: devbus-cs3 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
@@ -142,7 +142,7 @@
#size-cells = <1>;
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
- rtc@10300 {
+ rtc: rtc@10300 {
compatible = "marvell,orion-rtc";
reg = <0x10300 0x20>;
interrupts = <50>;
@@ -214,38 +214,38 @@
msi-controller;
};
- coherency-fabric@20200 {
+ coherencyfab: coherency-fabric@20200 {
compatible = "marvell,coherency-fabric";
reg = <0x20200 0xb0>, <0x21010 0x1c>;
};
- timer@20300 {
+ timer: timer@20300 {
reg = <0x20300 0x30>, <0x21040 0x30>;
interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
};
- watchdog@20300 {
+ watchdog: watchdog@20300 {
reg = <0x20300 0x34>, <0x20704 0x4>;
};
- cpurst@20800 {
+ cpurst: cpurst@20800 {
compatible = "marvell,armada-370-cpu-reset";
reg = <0x20800 0x8>;
};
- pmsu@22000 {
+ pmsu: pmsu@22000 {
compatible = "marvell,armada-370-pmsu";
reg = <0x22000 0x1000>;
};
- usb@50000 {
+ usb0: usb@50000 {
compatible = "marvell,orion-ehci";
reg = <0x50000 0x500>;
interrupts = <45>;
status = "disabled";
};
- usb@51000 {
+ usb1: usb@51000 {
compatible = "marvell,orion-ehci";
reg = <0x51000 0x500>;
interrupts = <46>;
@@ -274,7 +274,7 @@
status = "disabled";
};
- sata@a0000 {
+ sata: sata@a0000 {
compatible = "marvell,armada-370-sata";
reg = <0xa0000 0x5000>;
interrupts = <55>;
@@ -283,7 +283,7 @@
status = "disabled";
};
- nand@d0000 {
+ nand: nand@d0000 {
compatible = "marvell,armada370-nand";
reg = <0xd0000 0x54>;
#address-cells = <1>;
@@ -293,7 +293,7 @@
status = "disabled";
};
- mvsdio@d4000 {
+ sdio: mvsdio@d4000 {
compatible = "marvell,orion-sdio";
reg = <0xd4000 0x200>;
interrupts = <54>;
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 79b5463209aa..5ed086da1e51 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -70,7 +70,7 @@
reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
};
- pcie-controller {
+ pciec: pcie-controller {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci";
@@ -89,7 +89,7 @@
0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
- pcie@1,0 {
+ pcie0: pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
@@ -106,7 +106,7 @@
status = "disabled";
};
- pcie@2,0 {
+ pcie2: pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
@@ -190,7 +190,7 @@
pinctrl-names = "default";
};
- system-controller@18200 {
+ systemc: system-controller@18200 {
compatible = "marvell,armada-370-xp-system-controller";
reg = <0x18200 0x100>;
};
@@ -208,14 +208,14 @@
#clock-cells = <1>;
};
- thermal@18300 {
+ thermal: thermal@18300 {
compatible = "marvell,armada370-thermal";
reg = <0x18300 0x4
0x18304 0x4>;
status = "okay";
};
- sscg@18330 {
+ sscg: sscg@18330 {
reg = <0x18330 0x4>;
};
@@ -233,7 +233,7 @@
clocks = <&coreclk 2>;
};
- cpu-config@21000 {
+ cpuconf: cpu-config@21000 {
compatible = "marvell,armada-370-cpu-config";
reg = <0x21000 0x8>;
};
@@ -256,7 +256,7 @@
clocks = <&coreclk 0>;
};
- xor@60800 {
+ xor0: xor@60800 {
compatible = "marvell,orion-xor";
reg = <0x60800 0x100
0x60A00 0x100>;
@@ -275,7 +275,7 @@
};
};
- xor@60900 {
+ xor1: xor@60900 {
compatible = "marvell,orion-xor";
reg = <0x60900 0x100
0x60b00 0x100>;
@@ -302,7 +302,7 @@
compatible = "marvell,armada-370-neta";
};
- crypto@90000 {
+ cesa: crypto@90000 {
compatible = "marvell,armada-370-crypto";
reg = <0x90000 0x10000>;
reg-names = "regs";
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index 6e6d0f04bf2b..ebf79d6de1a1 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -86,7 +86,7 @@
* configured as x4 or quad x1 lanes. One unit is
* x1 only.
*/
- pcie-controller {
+ pciec: pcie-controller {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
device_type = "pci";
@@ -114,7 +114,7 @@
0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
- pcie@1,0 {
+ pcie1: pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
@@ -131,7 +131,7 @@
status = "disabled";
};
- pcie@2,0 {
+ pcie2: pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
@@ -148,7 +148,7 @@
status = "disabled";
};
- pcie@3,0 {
+ pcie3: pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
@@ -165,7 +165,7 @@
status = "disabled";
};
- pcie@4,0 {
+ pcie4: pcie@4,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
@@ -182,7 +182,7 @@
status = "disabled";
};
- pcie@5,0 {
+ pcie5: pcie@5,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
reg = <0x2800 0 0 0 0>;
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index c5fdc99f0dbe..34e78a568460 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -87,7 +87,7 @@
* configured as x4 or quad x1 lanes. One unit is
* x4 only.
*/
- pcie-controller {
+ pciec: pcie-controller {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
device_type = "pci";
@@ -129,7 +129,7 @@
0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
- pcie@1,0 {
+ pcie1: pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
@@ -146,7 +146,7 @@
status = "disabled";
};
- pcie@2,0 {
+ pcie2: pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
@@ -163,7 +163,7 @@
status = "disabled";
};
- pcie@3,0 {
+ pcie3: pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
@@ -180,7 +180,7 @@
status = "disabled";
};
- pcie@4,0 {
+ pcie4: pcie@4,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
@@ -197,7 +197,7 @@
status = "disabled";
};
- pcie@5,0 {
+ pcie5: pcie@5,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
reg = <0x2800 0 0 0 0>;
@@ -214,7 +214,7 @@
status = "disabled";
};
- pcie@6,0 {
+ pcie6: pcie@6,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
reg = <0x3000 0 0 0 0>;
@@ -231,7 +231,7 @@
status = "disabled";
};
- pcie@7,0 {
+ pcie7: pcie@7,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
reg = <0x3800 0 0 0 0>;
@@ -248,7 +248,7 @@
status = "disabled";
};
- pcie@8,0 {
+ pcie8: pcie@8,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
reg = <0x4000 0 0 0 0>;
@@ -265,7 +265,7 @@
status = "disabled";
};
- pcie@9,0 {
+ pcie9: pcie@9,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
reg = <0x4800 0 0 0 0>;
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index 0e24f1a38540..5148827ed934 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -104,7 +104,7 @@
* configured as x4 or quad x1 lanes. Two units are
* x4/x1.
*/
- pcie-controller {
+ pciec: pcie-controller {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
device_type = "pci";
@@ -150,7 +150,7 @@
0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
- pcie@1,0 {
+ pcie1: pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
@@ -167,7 +167,7 @@
status = "disabled";
};
- pcie@2,0 {
+ pcie2: pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
@@ -184,7 +184,7 @@
status = "disabled";
};
- pcie@3,0 {
+ pcie3: pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
@@ -201,7 +201,7 @@
status = "disabled";
};
- pcie@4,0 {
+ pcie4: pcie@4,0 {
device_type = "pci";
assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
@@ -218,7 +218,7 @@
status = "disabled";
};
- pcie@5,0 {
+ pcie5: pcie@5,0 {
device_type = "pci";
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
reg = <0x2800 0 0 0 0>;
@@ -235,7 +235,7 @@
status = "disabled";
};
- pcie@6,0 {
+ pcie6: pcie@6,0 {
device_type = "pci";
assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
reg = <0x3000 0 0 0 0>;
@@ -252,7 +252,7 @@
status = "disabled";
};
- pcie@7,0 {
+ pcie7: pcie@7,0 {
device_type = "pci";
assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
reg = <0x3800 0 0 0 0>;
@@ -269,7 +269,7 @@
status = "disabled";
};
- pcie@8,0 {
+ pcie8: pcie@8,0 {
device_type = "pci";
assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
reg = <0x4000 0 0 0 0>;
@@ -286,7 +286,7 @@
status = "disabled";
};
- pcie@9,0 {
+ pcie9: pcie@9,0 {
device_type = "pci";
assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
reg = <0x4800 0 0 0 0>;
@@ -303,7 +303,7 @@
status = "disabled";
};
- pcie@10,0 {
+ pcie10: pcie@10,0 {
device_type = "pci";
assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
reg = <0x5000 0 0 0 0>;
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index e141de2a4a1c..654a61e525b4 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -118,7 +118,7 @@
status = "disabled";
};
- system-controller@18200 {
+ systemc: system-controller@18200 {
compatible = "marvell,armada-370-xp-system-controller";
reg = <0x18200 0x500>;
};
@@ -136,7 +136,7 @@
#clock-cells = <1>;
};
- thermal@182b0 {
+ thermal: thermal@182b0 {
compatible = "marvell,armadaxp-thermal";
reg = <0x182b0 0x4
0x184d0 0x4>;
@@ -191,7 +191,7 @@
clocks = <&gateclk 19>;
};
- usb@52000 {
+ usb2: usb@52000 {
compatible = "marvell,orion-ehci";
reg = <0x52000 0x500>;
interrupts = <47>;
@@ -199,7 +199,7 @@
status = "disabled";
};
- xor@60900 {
+ xor1: xor@60900 {
compatible = "marvell,orion-xor";
reg = <0x60900 0x100
0x60b00 0x100>;
@@ -227,7 +227,7 @@
compatible = "marvell,armada-xp-neta";
};
- crypto@90000 {
+ cesa: crypto@90000 {
compatible = "marvell,armada-xp-crypto";
reg = <0x90000 0x10000>;
reg-names = "regs";
@@ -247,7 +247,7 @@
status = "disabled";
};
- xor@f0900 {
+ xor0: xor@f0900 {
compatible = "marvell,orion-xor";
reg = <0xF0900 0x100
0xF0B00 0x100>;
--
cgit
From f60f913986accc9337409331ea0038b028ee17ab Mon Sep 17 00:00:00 2001
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
Date: Fri, 4 Nov 2016 17:47:37 +0100
Subject: ARM: dts: armada-370-xp: Use the node labels
Use the node label when possible. As a result it flattens the device tree
and it makes more visible the IP blocks specific to each SoC variant.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm/boot/dts/armada-370.dtsi | 105 +++++++++++++++++++-------------------
arch/arm/boot/dts/armada-xp.dtsi | 76 +++++++++++++--------------
2 files changed, 91 insertions(+), 90 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 5ed086da1e51..079494e52554 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -134,14 +134,6 @@
wt-override;
};
- i2c0: i2c@11000 {
- reg = <0x11000 0x20>;
- };
-
- i2c1: i2c@11100 {
- reg = <0x11100 0x20>;
- };
-
gpio0: gpio@18100 {
compatible = "marvell,orion-gpio";
reg = <0x18100 0x40>;
@@ -175,20 +167,6 @@
interrupts = <91>;
};
- /*
- * Default UART pinctrl setting without RTS/CTS, can
- * be overwritten on board level if a different
- * configuration is used.
- */
- uart0: serial@12000 {
- pinctrl-0 = <&uart0_pins>;
- pinctrl-names = "default";
- };
-
- uart1: serial@12100 {
- pinctrl-0 = <&uart1_pins>;
- pinctrl-names = "default";
- };
systemc: system-controller@18200 {
compatible = "marvell,armada-370-xp-system-controller";
@@ -219,20 +197,6 @@
reg = <0x18330 0x4>;
};
- interrupt-controller@20a00 {
- reg = <0x20a00 0x1d0>, <0x21870 0x58>;
- };
-
- timer@20300 {
- compatible = "marvell,armada-370-timer";
- clocks = <&coreclk 2>;
- };
-
- watchdog@20300 {
- compatible = "marvell,armada-370-wdt";
- clocks = <&coreclk 2>;
- };
-
cpuconf: cpu-config@21000 {
compatible = "marvell,armada-370-cpu-config";
reg = <0x21000 0x8>;
@@ -248,14 +212,6 @@
status = "disabled";
};
- usb@50000 {
- clocks = <&coreclk 0>;
- };
-
- usb@51000 {
- clocks = <&coreclk 0>;
- };
-
xor0: xor@60800 {
compatible = "marvell,orion-xor";
reg = <0x60800 0x100
@@ -294,14 +250,6 @@
};
};
- ethernet@70000 {
- compatible = "marvell,armada-370-neta";
- };
-
- ethernet@74000 {
- compatible = "marvell,armada-370-neta";
- };
-
cesa: crypto@90000 {
compatible = "marvell,armada-370-crypto";
reg = <0x90000 0x10000>;
@@ -337,6 +285,59 @@
};
};
+/*
+ * Default UART pinctrl setting without RTS/CTS, can be overwritten on
+ * board level if a different configuration is used.
+ */
+
+&uart0 {
+ pinctrl-0 = <&uart0_pins>;
+ pinctrl-names = "default";
+};
+
+&uart1 {
+ pinctrl-0 = <&uart1_pins>;
+ pinctrl-names = "default";
+};
+
+&i2c0 {
+ reg = <0x11000 0x20>;
+};
+
+&i2c1 {
+ reg = <0x11100 0x20>;
+};
+
+&mpic {
+ reg = <0x20a00 0x1d0>, <0x21870 0x58>;
+};
+
+&timer {
+ compatible = "marvell,armada-370-timer";
+ clocks = <&coreclk 2>;
+};
+
+&watchdog {
+ compatible = "marvell,armada-370-wdt";
+ clocks = <&coreclk 2>;
+};
+
+&usb0 {
+ clocks = <&coreclk 0>;
+};
+
+&usb1 {
+ clocks = <&coreclk 0>;
+};
+
+ð0 {
+ compatible = "marvell,armada-370-neta";
+};
+
+ð1 {
+ compatible = "marvell,armada-370-neta";
+};
+
&pinctrl {
compatible = "marvell,mv88f6710-pinctrl";
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 654a61e525b4..bb8f7dcaf656 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -84,16 +84,6 @@
wt-override;
};
- i2c0: i2c@11000 {
- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
- reg = <0x11000 0x100>;
- };
-
- i2c1: i2c@11100 {
- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
- reg = <0x11100 0x100>;
- };
-
uart2: serial@12200 {
compatible = "snps,dw-apb-uart";
pinctrl-0 = <&uart2_pins>;
@@ -150,26 +140,6 @@
clocks = <&coreclk 1>;
};
- interrupt-controller@20a00 {
- reg = <0x20a00 0x2d0>, <0x21070 0x58>;
- };
-
- timer@20300 {
- compatible = "marvell,armada-xp-timer";
- clocks = <&coreclk 2>, <&refclk>;
- clock-names = "nbclk", "fixed";
- };
-
- watchdog@20300 {
- compatible = "marvell,armada-xp-wdt";
- clocks = <&coreclk 2>, <&refclk>;
- clock-names = "nbclk", "fixed";
- };
-
- cpurst@20800 {
- reg = <0x20800 0x20>;
- };
-
cpu-config@21000 {
compatible = "marvell,armada-xp-cpu-config";
reg = <0x21000 0x8>;
@@ -183,14 +153,6 @@
status = "disabled";
};
- usb@50000 {
- clocks = <&gateclk 18>;
- };
-
- usb@51000 {
- clocks = <&gateclk 19>;
- };
-
usb2: usb@52000 {
compatible = "marvell,orion-ehci";
reg = <0x52000 0x500>;
@@ -308,6 +270,44 @@
};
};
+&i2c0 {
+ compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
+ reg = <0x11000 0x100>;
+};
+
+&i2c1 {
+ compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
+ reg = <0x11100 0x100>;
+};
+
+&mpic {
+ reg = <0x20a00 0x2d0>, <0x21070 0x58>;
+};
+
+&timer {
+ compatible = "marvell,armada-xp-timer";
+ clocks = <&coreclk 2>, <&refclk>;
+ clock-names = "nbclk", "fixed";
+};
+
+&watchdog {
+ compatible = "marvell,armada-xp-wdt";
+ clocks = <&coreclk 2>, <&refclk>;
+ clock-names = "nbclk", "fixed";
+};
+
+&cpurst {
+ reg = <0x20800 0x20>;
+};
+
+&usb0 {
+ clocks = <&gateclk 18>;
+};
+
+&usb1 {
+ clocks = <&gateclk 19>;
+};
+
&pinctrl {
ge0_gmii_pins: ge0-gmii-pins {
marvell,pins =
--
cgit
From 1fc2129553c5a387be786c4b302e3a253a7d01a8 Mon Sep 17 00:00:00 2001
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
Date: Fri, 4 Nov 2016 17:54:54 +0100
Subject: ARM: dts: armada-370-xp: Fixup mdio DT warning
MDIO has a reg property so the unit name should contain an address.
Take the opportunity to use the node label instead of the full name.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm/boot/dts/armada-370-db.dts | 24 +++++++--------
arch/arm/boot/dts/armada-370-mirabox.dts | 23 +++++++-------
arch/arm/boot/dts/armada-370-netgear-rn102.dts | 16 +++++-----
arch/arm/boot/dts/armada-370-netgear-rn104.dts | 24 +++++++--------
arch/arm/boot/dts/armada-370-rd.dts | 19 ++++++------
arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts | 13 ++++----
arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi | 18 +++++------
.../dts/armada-370-seagate-personal-cloud.dtsi | 18 +++++------
arch/arm/boot/dts/armada-370-synology-ds213j.dts | 12 ++++----
arch/arm/boot/dts/armada-370-xp.dtsi | 2 +-
arch/arm/boot/dts/armada-xp-axpwifiap.dts | 20 ++++++------
arch/arm/boot/dts/armada-xp-db.dts | 36 +++++++++++-----------
arch/arm/boot/dts/armada-xp-gp.dts | 36 +++++++++++-----------
arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts | 20 ++++++------
arch/arm/boot/dts/armada-xp-netgear-rn2120.dts | 21 +++++++------
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 36 +++++++++++-----------
arch/arm/boot/dts/armada-xp-synology-ds414.dts | 20 ++++++------
17 files changed, 181 insertions(+), 177 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index 033fa63544f7..d26115085ea1 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -86,18 +86,6 @@
status = "okay";
};
- mdio {
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
- };
-
ethernet@70000 {
pinctrl-0 = <&ge0_rgmii_pins>;
pinctrl-names = "default";
@@ -260,6 +248,18 @@
compatible = "linux,spdif-dir";
};
};
+&mdio {
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
&spi0 {
pinctrl-0 = <&spi0_pins2>;
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index d5e19cd4d256..3e1ef56b6319 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -113,17 +113,6 @@
};
};
- mdio {
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
- };
ethernet@70000 {
pinctrl-0 = <&ge0_rgmii_pins>;
pinctrl-names = "default";
@@ -197,6 +186,18 @@
};
};
+&mdio {
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
&pinctrl {
pwr_led_pin: pwr-led-pin {
marvell,pins = "mpp63";
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
index a9e3810aea65..a6409853db6d 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
@@ -99,14 +99,6 @@
status = "okay";
};
- mdio {
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- phy0: ethernet-phy@0 { /* Marvell 88E1318 */
- reg = <0>;
- };
- };
-
ethernet@74000 {
pinctrl-0 = <&ge1_rgmii_pins>;
pinctrl-names = "default";
@@ -260,6 +252,14 @@
};
};
+&mdio {
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ phy0: ethernet-phy@0 { /* Marvell 88E1318 */
+ reg = <0>;
+ };
+};
+
&pinctrl {
power_led_pin: power-led-pin {
marvell,pins = "mpp57";
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
index 14c379699350..fd5f1d9a434a 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
@@ -93,18 +93,6 @@
status = "okay";
};
- mdio {
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- phy0: ethernet-phy@0 { /* Marvell 88E1318 */
- reg = <0>;
- };
-
- phy1: ethernet-phy@1 { /* Marvell 88E1318 */
- reg = <1>;
- };
- };
-
ethernet@70000 {
pinctrl-0 = <&ge0_rgmii_pins>;
pinctrl-names = "default";
@@ -282,6 +270,18 @@
};
};
+&mdio {
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ phy0: ethernet-phy@0 { /* Marvell 88E1318 */
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 { /* Marvell 88E1318 */
+ reg = <1>;
+ };
+};
+
&pinctrl {
poweroff: poweroff {
marvell,pins = "mpp60";
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index fbef730e8d37..621add7e12d5 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -102,14 +102,6 @@
status = "okay";
};
- mdio {
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
- };
-
ethernet@70000 {
status = "okay";
phy = <&phy0>;
@@ -235,7 +227,16 @@
};
};
};
- };
+};
+
+&mdio {
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
&pinctrl {
fan_pins: fan-pins {
diff --git a/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts b/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts
index ae2e1fe50ef6..82ce5ec6467b 100644
--- a/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts
+++ b/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts
@@ -36,12 +36,6 @@
};
internal-regs {
- mdio {
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
- };
-
ethernet@74000 {
status = "okay";
pinctrl-0 = <&ge1_rgmii_pins>;
@@ -131,3 +125,10 @@
1300 0>;
};
};
+
+&mdio {
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
diff --git a/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi b/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi
index 3036e25c5992..724a47908e3f 100644
--- a/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi
+++ b/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi
@@ -51,15 +51,6 @@
status = "okay";
};
- mdio {
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
-
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
- };
-
ethernet@70000 {
status = "okay";
pinctrl-0 = <&ge0_rgmii_pins>;
@@ -208,6 +199,15 @@
};
};
+&mdio {
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
&pinctrl {
pinctrl-0 = <&hdd0_led_sata_pin>, <&hdd1_led_sata_pin>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi b/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi
index 01cded310cbc..fb52a34f0a35 100644
--- a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi
+++ b/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi
@@ -51,15 +51,6 @@
status = "okay";
};
- mdio {
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
-
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
- };
-
ethernet@74000 {
status = "okay";
pinctrl-0 = <&ge1_rgmii_pins>;
@@ -143,6 +134,15 @@
};
};
+&mdio {
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
&pinctrl {
pinctrl-0 = <&sata_led_pin>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/armada-370-synology-ds213j.dts b/arch/arm/boot/dts/armada-370-synology-ds213j.dts
index a9cc42776874..a696bbf0f703 100644
--- a/arch/arm/boot/dts/armada-370-synology-ds213j.dts
+++ b/arch/arm/boot/dts/armada-370-synology-ds213j.dts
@@ -127,12 +127,6 @@
status = "okay";
};
- mdio {
- phy1: ethernet-phy@1 { /* Marvell 88E1512 */
- reg = <1>;
- };
- };
-
ethernet@70000 {
status = "okay";
phy = <&phy1>;
@@ -220,6 +214,12 @@
};
};
+&mdio {
+ phy1: ethernet-phy@1 { /* Marvell 88E1512 */
+ reg = <1>;
+ };
+};
+
&pinctrl {
disk1_led_pin: disk1-led-pin {
marvell,pins = "mpp31";
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 54359896b76c..a4f9684def1c 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -259,7 +259,7 @@
status = "disabled";
};
- mdio: mdio {
+ mdio: mdio@72004 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "marvell,orion-mdio";
diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
index ce152719bc28..7038c8625ac5 100644
--- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts
+++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
@@ -111,16 +111,6 @@
status = "okay";
};
- mdio {
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
- };
-
ethernet@70000 {
pinctrl-0 = <&ge0_rgmii_pins>;
pinctrl-names = "default";
@@ -153,6 +143,16 @@
};
};
+&mdio {
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
&pinctrl {
pinctrl-0 = <&phy_int_pin>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index 075120bc3ec4..665c81ff98db 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -160,24 +160,6 @@
status = "okay";
};
- mdio {
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
-
- phy2: ethernet-phy@2 {
- reg = <25>;
- };
-
- phy3: ethernet-phy@3 {
- reg = <27>;
- };
- };
-
ethernet@70000 {
status = "okay";
phy = <&phy0>;
@@ -266,6 +248,24 @@
};
};
+&mdio {
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+
+ phy2: ethernet-phy@2 {
+ reg = <25>;
+ };
+
+ phy3: ethernet-phy@3 {
+ reg = <27>;
+ };
+};
+
&spi0 {
status = "okay";
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 190e4eccb180..09c9cabdf67a 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -175,24 +175,6 @@
status = "okay";
};
- mdio {
- phy0: ethernet-phy@0 {
- reg = <16>;
- };
-
- phy1: ethernet-phy@1 {
- reg = <17>;
- };
-
- phy2: ethernet-phy@2 {
- reg = <18>;
- };
-
- phy3: ethernet-phy@3 {
- reg = <19>;
- };
- };
-
ethernet@70000 {
status = "okay";
phy = <&phy0>;
@@ -251,6 +233,24 @@
};
};
+&mdio {
+ phy0: ethernet-phy@0 {
+ reg = <16>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <17>;
+ };
+
+ phy2: ethernet-phy@2 {
+ reg = <18>;
+ };
+
+ phy3: ethernet-phy@3 {
+ reg = <19>;
+ };
+};
+
&spi0 {
status = "okay";
diff --git a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
index 8af463f26ea1..0a6a43692620 100644
--- a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
+++ b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
@@ -89,16 +89,6 @@
status = "okay";
};
- mdio {
- phy0: ethernet-phy@0 { /* Marvell 88E1318 */
- reg = <0>;
- };
-
- phy1: ethernet-phy@1 { /* Marvell 88E1318 */
- reg = <1>;
- };
- };
-
ethernet@70000 {
pinctrl-0 = <&ge0_rgmii_pins>;
pinctrl-names = "default";
@@ -296,6 +286,16 @@
};
};
+&mdio {
+ phy0: ethernet-phy@0 { /* Marvell 88E1318 */
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 { /* Marvell 88E1318 */
+ reg = <1>;
+ };
+};
+
&pinctrl {
poweroff_pin: poweroff-pin {
marvell,pins = "mpp24";
diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
index b6bf5344fbbe..c4685cb86f06 100644
--- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
+++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
@@ -153,16 +153,6 @@
status = "okay";
};
- mdio {
- phy0: ethernet-phy@0 { /* Marvell 88E1318 */
- reg = <0>;
- };
-
- phy1: ethernet-phy@1 { /* Marvell 88E1318 */
- reg = <1>;
- };
- };
-
ethernet@70000 {
pinctrl-0 = <&ge0_rgmii_pins>;
pinctrl-names = "default";
@@ -300,6 +290,17 @@
};
};
+&mdio {
+ phy0: ethernet-phy@0 { /* Marvell 88E1318 */
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 { /* Marvell 88E1318 */
+ reg = <1>;
+ };
+};
+
+
&pinctrl {
poweroff: poweroff {
marvell,pins = "mpp42";
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index ed3b889d16ce..2e2cd9353761 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -155,24 +155,6 @@
};
};
- mdio {
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
-
- phy2: ethernet-phy@2 {
- reg = <2>;
- };
-
- phy3: ethernet-phy@3 {
- reg = <3>;
- };
- };
-
ethernet@70000 {
status = "okay";
phy = <&phy0>;
@@ -240,6 +222,24 @@
};
};
+&mdio {
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+
+ phy2: ethernet-phy@2 {
+ reg = <2>;
+ };
+
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ };
+};
+
&pinctrl {
led_pins: led-pins-0 {
marvell,pins = "mpp49", "mpp51", "mpp53";
diff --git a/arch/arm/boot/dts/armada-xp-synology-ds414.dts b/arch/arm/boot/dts/armada-xp-synology-ds414.dts
index ae286736b90a..189ec7f4667c 100644
--- a/arch/arm/boot/dts/armada-xp-synology-ds414.dts
+++ b/arch/arm/boot/dts/armada-xp-synology-ds414.dts
@@ -150,16 +150,6 @@
status = "okay";
};
- mdio {
- phy0: ethernet-phy@0 { /* Marvell 88E1512 */
- reg = <0>;
- };
-
- phy1: ethernet-phy@1 { /* Marvell 88E1512 */
- reg = <1>;
- };
- };
-
ethernet@70000 {
status = "okay";
pinctrl-0 = <&ge0_rgmii_pins>;
@@ -240,6 +230,16 @@
};
};
+&mdio {
+ phy0: ethernet-phy@0 { /* Marvell 88E1512 */
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 { /* Marvell 88E1512 */
+ reg = <1>;
+ };
+};
+
&pinctrl {
sata1_pwr_pin: sata1-pwr-pin {
marvell,pins = "mpp42";
--
cgit
From 007d05d898050ffc70fd2737896528c5069f7269 Mon Sep 17 00:00:00 2001
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
Date: Sat, 5 Nov 2016 19:03:50 +0100
Subject: ARM: dts: armada-xp: Fixup pcie DT warnings
PCIe has a range property, so the unit name should contain an address.
Take the opportunity to use the node label instead of the full name.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm/boot/dts/armada-xp-axpwifiap.dts | 44 ++++++++--------
arch/arm/boot/dts/armada-xp-db.dts | 66 ++++++++++++------------
arch/arm/boot/dts/armada-xp-gp.dts | 42 +++++++--------
arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts | 31 ++++++-----
arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 44 ++++++++--------
arch/arm/boot/dts/armada-xp-matrix.dts | 18 +++----
arch/arm/boot/dts/armada-xp-mv78230.dtsi | 2 +-
arch/arm/boot/dts/armada-xp-mv78260.dtsi | 2 +-
arch/arm/boot/dts/armada-xp-mv78460.dtsi | 2 +-
arch/arm/boot/dts/armada-xp-netgear-rn2120.dts | 44 ++++++++--------
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 18 +++----
arch/arm/boot/dts/armada-xp-synology-ds414.dts | 45 ++++++++--------
12 files changed, 179 insertions(+), 179 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
index 7038c8625ac5..d12b06bf0d60 100644
--- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts
+++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
@@ -73,28 +73,6 @@
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
- pcie-controller {
- status = "okay";
-
- /* First mini-PCIe port */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
-
- /* Second mini-PCIe port */
- pcie@2,0 {
- /* Port 0, Lane 1 */
- status = "okay";
- };
-
- /* Renesas uPD720202 USB 3.0 controller */
- pcie@3,0 {
- /* Port 0, Lane 3 */
- status = "okay";
- };
- };
-
internal-regs {
/* UART0 */
serial@12000 {
@@ -153,6 +131,28 @@
};
};
+&pciec {
+ status = "okay";
+
+ /* First mini-PCIe port */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+
+ /* Second mini-PCIe port */
+ pcie@2,0 {
+ /* Port 0, Lane 1 */
+ status = "okay";
+ };
+
+ /* Renesas uPD720202 USB 3.0 controller */
+ pcie@3,0 {
+ /* Port 0, Lane 3 */
+ status = "okay";
+ };
+};
+
&pinctrl {
pinctrl-0 = <&phy_int_pin>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index 665c81ff98db..8b9c606bfbc6 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -108,39 +108,6 @@
};
};
- pcie-controller {
- status = "okay";
-
- /*
- * All 6 slots are physically present as
- * standard PCIe slots on the board.
- */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
- pcie@2,0 {
- /* Port 0, Lane 1 */
- status = "okay";
- };
- pcie@3,0 {
- /* Port 0, Lane 2 */
- status = "okay";
- };
- pcie@4,0 {
- /* Port 0, Lane 3 */
- status = "okay";
- };
- pcie@9,0 {
- /* Port 2, Lane 0 */
- status = "okay";
- };
- pcie@10,0 {
- /* Port 3, Lane 0 */
- status = "okay";
- };
- };
-
internal-regs {
serial@12000 {
status = "okay";
@@ -248,6 +215,39 @@
};
};
+&pciec {
+ status = "okay";
+
+ /*
+ * All 6 slots are physically present as
+ * standard PCIe slots on the board.
+ */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+ pcie@2,0 {
+ /* Port 0, Lane 1 */
+ status = "okay";
+ };
+ pcie@3,0 {
+ /* Port 0, Lane 2 */
+ status = "okay";
+ };
+ pcie@4,0 {
+ /* Port 0, Lane 3 */
+ status = "okay";
+ };
+ pcie@9,0 {
+ /* Port 2, Lane 0 */
+ status = "okay";
+ };
+ pcie@10,0 {
+ /* Port 3, Lane 0 */
+ status = "okay";
+ };
+};
+
&mdio {
phy0: ethernet-phy@0 {
reg = <0>;
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 09c9cabdf67a..fca37e92b96a 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -127,27 +127,6 @@
};
};
- pcie-controller {
- status = "okay";
-
- /*
- * The 3 slots are physically present as
- * standard PCIe slots on the board.
- */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
- pcie@9,0 {
- /* Port 2, Lane 0 */
- status = "okay";
- };
- pcie@10,0 {
- /* Port 3, Lane 0 */
- status = "okay";
- };
- };
-
internal-regs {
serial@12000 {
status = "okay";
@@ -233,6 +212,27 @@
};
};
+&pciec {
+ status = "okay";
+
+ /*
+ * The 3 slots are physically present as
+ * standard PCIe slots on the board.
+ */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+ pcie@9,0 {
+ /* Port 2, Lane 0 */
+ status = "okay";
+ };
+ pcie@10,0 {
+ /* Port 3, Lane 0 */
+ status = "okay";
+ };
+};
+
&mdio {
phy0: ethernet-phy@0 {
reg = <16>;
diff --git a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
index 0a6a43692620..1dce74d9b616 100644
--- a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
+++ b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
@@ -68,22 +68,6 @@
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
- pcie-controller {
- status = "okay";
-
- /* Quad port sata: Marvell 88SX7042 */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
-
- /* USB 3.0 xHCI controller: NEC D720200F1 */
- pcie@5,0 {
- /* Port 1, Lane 0 */
- status = "okay";
- };
- };
-
internal-regs {
serial@12000 {
status = "okay";
@@ -285,6 +269,21 @@
gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
};
};
+&pciec {
+ status = "okay";
+
+ /* Quad port sata: Marvell 88SX7042 */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+
+ /* USB 3.0 xHCI controller: NEC D720200F1 */
+ pcie@5,0 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+ };
+};
&mdio {
phy0: ethernet-phy@0 { /* Marvell 88E1318 */
diff --git a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
index 076f27f22c3b..488a047481d4 100644
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
@@ -73,28 +73,6 @@
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
- pcie-controller {
- status = "okay";
-
- /* Etron EJ168 USB 3.0 controller */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
-
- /* First mini-PCIe port */
- pcie@2,0 {
- /* Port 0, Lane 1 */
- status = "okay";
- };
-
- /* Second mini-PCIe port */
- pcie@3,0 {
- /* Port 0, Lane 3 */
- status = "okay";
- };
- };
-
internal-regs {
rtc@10300 {
@@ -369,6 +347,28 @@
};
};
+&pciec {
+ status = "okay";
+
+ /* Etron EJ168 USB 3.0 controller */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+
+ /* First mini-PCIe port */
+ pcie@2,0 {
+ /* Port 0, Lane 1 */
+ status = "okay";
+ };
+
+ /* Second mini-PCIe port */
+ pcie@3,0 {
+ /* Port 0, Lane 3 */
+ status = "okay";
+ };
+};
+
&pinctrl {
keys_pin: keys-pin {
diff --git a/arch/arm/boot/dts/armada-xp-matrix.dts b/arch/arm/boot/dts/armada-xp-matrix.dts
index e1509f4c5114..8b5a4e79d26b 100644
--- a/arch/arm/boot/dts/armada-xp-matrix.dts
+++ b/arch/arm/boot/dts/armada-xp-matrix.dts
@@ -71,15 +71,6 @@
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
- pcie-controller {
- status = "okay";
-
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
- };
-
internal-regs {
serial@12000 {
status = "okay";
@@ -114,3 +105,12 @@
};
};
};
+
+&pciec {
+ status = "okay";
+
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+};
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index ebf79d6de1a1..05c164b5786d 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -86,7 +86,7 @@
* configured as x4 or quad x1 lanes. One unit is
* x1 only.
*/
- pciec: pcie-controller {
+ pciec: pcie-controller@82000000 {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
device_type = "pci";
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 34e78a568460..07894b0d3e59 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -87,7 +87,7 @@
* configured as x4 or quad x1 lanes. One unit is
* x4 only.
*/
- pciec: pcie-controller {
+ pciec: pcie-controller@82000000 {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
device_type = "pci";
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index 5148827ed934..775bee53ce86 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -104,7 +104,7 @@
* configured as x4 or quad x1 lanes. Two units are
* x4/x1.
*/
- pciec: pcie-controller {
+ pciec: pcie-controller@82000000 {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
device_type = "pci";
diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
index c4685cb86f06..5aaaf0fb2330 100644
--- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
+++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
@@ -67,28 +67,6 @@
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
- pcie-controller {
- status = "okay";
-
- /* Connected to first Marvell 88SE9170 SATA controller */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
-
- /* Connected to second Marvell 88SE9170 SATA controller */
- pcie@2,0 {
- /* Port 0, Lane 1 */
- status = "okay";
- };
-
- /* Connected to Fresco Logic FL1009 USB 3.0 controller */
- pcie@5,0 {
- /* Port 1, Lane 0 */
- status = "okay";
- };
- };
-
internal-regs {
/* RTC is provided by Intersil ISL12057 I2C RTC chip */
@@ -290,6 +268,28 @@
};
};
+&pciec {
+ status = "okay";
+
+ /* Connected to first Marvell 88SE9170 SATA controller */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+
+ /* Connected to second Marvell 88SE9170 SATA controller */
+ pcie@2,0 {
+ /* Port 0, Lane 1 */
+ status = "okay";
+ };
+
+ /* Connected to Fresco Logic FL1009 USB 3.0 controller */
+ pcie@5,0 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+ };
+};
+
&mdio {
phy0: ethernet-phy@0 { /* Marvell 88E1318 */
reg = <0>;
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 2e2cd9353761..a0e36e166b02 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -98,15 +98,6 @@
};
};
- pcie-controller {
- status = "okay";
- /* Internal mini-PCIe connector */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
- };
-
internal-regs {
rtc@10300 {
/* No crystal connected to the internal RTC */
@@ -222,6 +213,15 @@
};
};
+&pciec {
+ status = "okay";
+ /* Internal mini-PCIe connector */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+};
+
&mdio {
phy0: ethernet-phy@0 {
reg = <0>;
diff --git a/arch/arm/boot/dts/armada-xp-synology-ds414.dts b/arch/arm/boot/dts/armada-xp-synology-ds414.dts
index 189ec7f4667c..d5630a7b4b18 100644
--- a/arch/arm/boot/dts/armada-xp-synology-ds414.dts
+++ b/arch/arm/boot/dts/armada-xp-synology-ds414.dts
@@ -81,28 +81,6 @@
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
- pcie-controller {
- status = "okay";
-
- /*
- * Connected to Marvell 88SX7042 SATA-II controller
- * handling the four disks.
- */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
-
- /*
- * Connected to EtronTech EJ168A XHCI controller
- * providing the two rear USB 3.0 ports.
- */
- pcie@5,0 {
- /* Port 1, Lane 0 */
- status = "okay";
- };
- };
-
internal-regs {
/* RTC is provided by Seiko S-35390A below */
@@ -230,6 +208,29 @@
};
};
+&pciec {
+ status = "okay";
+
+ /*
+ * Connected to Marvell 88SX7042 SATA-II controller
+ * handling the four disks.
+ */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+
+ /*
+ * Connected to EtronTech EJ168A XHCI controller
+ * providing the two rear USB 3.0 ports.
+ */
+ pcie@5,0 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+ };
+};
+
+
&mdio {
phy0: ethernet-phy@0 { /* Marvell 88E1512 */
reg = <0>;
--
cgit
From 8d977093bf54422a42927722f93360d6fc240751 Mon Sep 17 00:00:00 2001
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
Date: Sat, 5 Nov 2016 19:20:09 +0100
Subject: ARM: dts: armada-370: Fixup pcie DT warnings
PCIe has a ranges property, so the unit name should contain an address.
Take the opportunity to use the node label instead of the full name.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm/boot/dts/armada-370-db.dts | 37 +++++++++++-----------
arch/arm/boot/dts/armada-370-dlink-dns327l.dts | 28 ++++++++--------
arch/arm/boot/dts/armada-370-mirabox.dts | 32 +++++++++----------
arch/arm/boot/dts/armada-370-netgear-rn102.dts | 32 +++++++++----------
arch/arm/boot/dts/armada-370-netgear-rn104.dts | 32 +++++++++----------
arch/arm/boot/dts/armada-370-rd.dts | 32 +++++++++----------
arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts | 14 ++++----
arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi | 19 +++++------
.../dts/armada-370-seagate-personal-cloud.dtsi | 18 +++++------
arch/arm/boot/dts/armada-370.dtsi | 2 +-
10 files changed, 124 insertions(+), 122 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index d26115085ea1..f3adc187c6a5 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -170,24 +170,6 @@
};
};
};
-
- pcie-controller {
- status = "okay";
- /*
- * The two PCIe units are accessible through
- * both standard PCIe slots and mini-PCIe
- * slots on the board.
- */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
-
- pcie@2,0 {
- /* Port 1, Lane 0 */
- status = "okay";
- };
- };
};
sound {
@@ -248,6 +230,25 @@
compatible = "linux,spdif-dir";
};
};
+
+&pciec {
+ status = "okay";
+ /*
+ * The two PCIe units are accessible through
+ * both standard PCIe slots and mini-PCIe
+ * slots on the board.
+ */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+
+ pcie@2,0 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+ };
+};
+
&mdio {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/armada-370-dlink-dns327l.dts b/arch/arm/boot/dts/armada-370-dlink-dns327l.dts
index e2a363b1dd8a..9e499eeede4b 100644
--- a/arch/arm/boot/dts/armada-370-dlink-dns327l.dts
+++ b/arch/arm/boot/dts/armada-370-dlink-dns327l.dts
@@ -72,20 +72,6 @@
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
- pcie-controller {
- status = "okay";
-
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
-
- pcie@2,0 {
- /* Port 1, Lane 0 */
- status = "okay";
- };
- };
-
internal-regs {
sata@a0000 {
nr-ports = <2>;
@@ -262,6 +248,20 @@
};
};
+&pciec {
+ status = "okay";
+
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+
+ pcie@2,0 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+ };
+};
+
&pinctrl {
sata_l_white_pin: sata-l-white-pin {
marvell,pins = "mpp57";
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index 3e1ef56b6319..c4dded0cd0c1 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -64,22 +64,6 @@
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
- pcie-controller {
- status = "okay";
-
- /* Internal mini-PCIe connector */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
-
- /* Connected on the PCB to a USB 3.0 XHCI controller */
- pcie@2,0 {
- /* Port 1, Lane 0 */
- status = "okay";
- };
- };
-
internal-regs {
serial@12000 {
status = "okay";
@@ -186,6 +170,22 @@
};
};
+&pciec {
+ status = "okay";
+
+ /* Internal mini-PCIe connector */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+
+ /* Connected on the PCB to a USB 3.0 XHCI controller */
+ pcie@2,0 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+ };
+};
+
&mdio {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
index a6409853db6d..99b9d73ebbaf 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
@@ -66,22 +66,6 @@
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
- pcie-controller {
- status = "okay";
-
- /* Connected to Marvell 88SE9170 SATA controller */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
-
- /* Connected to FL1009 USB 3.0 controller */
- pcie@2,0 {
- /* Port 1, Lane 0 */
- status = "okay";
- };
- };
-
internal-regs {
/* RTC is provided by Intersil ISL12057 I2C RTC chip */
@@ -252,6 +236,22 @@
};
};
+&pciec {
+ status = "okay";
+
+ /* Connected to Marvell 88SE9170 SATA controller */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+
+ /* Connected to FL1009 USB 3.0 controller */
+ pcie@2,0 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+ };
+};
+
&mdio {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
index fd5f1d9a434a..b5dd30178725 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
@@ -66,22 +66,6 @@
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
- pcie-controller {
- status = "okay";
-
- /* Connected to FL1009 USB 3.0 controller */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
-
- /* Connected to Marvell 88SE9215 SATA controller */
- pcie@2,0 {
- /* Port 1, Lane 0 */
- status = "okay";
- };
- };
-
internal-regs {
/* RTC is provided by Intersil ISL12057 I2C RTC chip */
@@ -270,6 +254,22 @@
};
};
+&pciec {
+ status = "okay";
+
+ /* Connected to FL1009 USB 3.0 controller */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+
+ /* Connected to Marvell 88SE9215 SATA controller */
+ pcie@2,0 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+ };
+};
+
&mdio {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index 621add7e12d5..29722b9f288e 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -77,22 +77,6 @@
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
- pcie-controller {
- status = "okay";
-
- /* Internal mini-PCIe connector */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
-
- /* Internal mini-PCIe connector */
- pcie@2,0 {
- /* Port 1, Lane 0 */
- status = "okay";
- };
- };
-
internal-regs {
serial@12000 {
status = "okay";
@@ -229,6 +213,22 @@
};
};
+&pciec {
+ status = "okay";
+
+ /* Internal mini-PCIe connector */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+
+ /* Internal mini-PCIe connector */
+ pcie@2,0 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+ };
+};
+
&mdio {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts b/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts
index 82ce5ec6467b..eb6af53b4954 100644
--- a/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts
+++ b/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts
@@ -28,13 +28,6 @@
compatible = "seagate,dart-4", "marvell,armada370", "marvell,armada-370-xp";
soc {
- pcie-controller {
- /* SATA AHCI controller 88SE9170 */
- pcie@1,0 {
- status = "okay";
- };
- };
-
internal-regs {
ethernet@74000 {
status = "okay";
@@ -126,6 +119,13 @@
};
};
+&pciec {
+ /* SATA AHCI controller 88SE9170 */
+ pcie@1,0 {
+ status = "okay";
+ };
+};
+
&mdio {
phy1: ethernet-phy@1 {
reg = <1>;
diff --git a/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi b/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi
index 724a47908e3f..9b582c47f10c 100644
--- a/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi
+++ b/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi
@@ -32,15 +32,6 @@
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
- pcie-controller {
- status = "okay";
-
- /* USB 3.0 bridge ASM1042A */
- pcie@2,0 {
- status = "okay";
- };
- };
-
internal-regs {
serial@12000 {
status = "okay";
@@ -199,6 +190,16 @@
};
};
+&pciec {
+ status = "okay";
+
+ /* USB 3.0 bridge ASM1042A */
+ pcie@2,0 {
+ status = "okay";
+ };
+};
+
+
&mdio {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi b/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi
index fb52a34f0a35..bb678a45ac8e 100644
--- a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi
+++ b/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi
@@ -33,15 +33,6 @@
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
- pcie-controller {
- status = "okay";
-
- /* USB 3.0 Bridge ASM1042A */
- pcie@1,0 {
- status = "okay";
- };
- };
-
internal-regs {
coherency-fabric@20200 {
broken-idle;
@@ -134,6 +125,15 @@
};
};
+&pciec {
+ status = "okay";
+
+ /* USB 3.0 Bridge ASM1042A */
+ pcie@1,0 {
+ status = "okay";
+ };
+};
+
&mdio {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 079494e52554..60cdeb35f117 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -70,7 +70,7 @@
reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
};
- pciec: pcie-controller {
+ pciec: pcie-controller@82000000 {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci";
--
cgit
From 1cb92a98a1a57c5e71f69985451ff6f0c1534af5 Mon Sep 17 00:00:00 2001
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
Date: Sat, 5 Nov 2016 19:35:12 +0100
Subject: ARM: dts: armada-370-xp: Remove skeleton.dtsi
The skeleton.dtsi file was removed in ARM64 for different reasons as
explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi").
These also applies to ARM and it will also allow to get rid of the
following DTC warnings in the future:
"Node /memory has a reg or ranges property, but no unit name"
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm/boot/dts/armada-370-xp.dtsi | 2 --
arch/arm/boot/dts/armada-370.dtsi | 4 +++-
arch/arm/boot/dts/armada-xp.dtsi | 3 +++
3 files changed, 6 insertions(+), 3 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index a4f9684def1c..b0520bdeea27 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -50,8 +50,6 @@
* 370 and Armada XP SoC.
*/
-/include/ "skeleton64.dtsi"
-
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
/ {
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 60cdeb35f117..a65bc4d3b810 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -50,9 +50,11 @@
*/
#include "armada-370-xp.dtsi"
-/include/ "skeleton.dtsi"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
model = "Marvell Armada 370 family SoC";
compatible = "marvell,armada370", "marvell,armada-370-xp";
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index bb8f7dcaf656..097ea70736e2 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -53,6 +53,9 @@
#include "armada-370-xp.dtsi"
/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
model = "Marvell Armada XP family SoC";
compatible = "marvell,armadaxp", "marvell,armada-370-xp";
--
cgit
From 3a729d7ccfb582c345e1d20fe443c079134c50d3 Mon Sep 17 00:00:00 2001
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
Date: Sat, 5 Nov 2016 19:40:45 +0100
Subject: ARM: dts: armada-370-xp: Fixup l2-cache DT warning
l2-cache which is either an aurora-outer-cache or an aurora-system-cache
has a reg property so the unit name should contain an address.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm/boot/dts/armada-370.dtsi | 2 +-
arch/arm/boot/dts/armada-xp.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index a65bc4d3b810..b704bcc597f7 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -127,7 +127,7 @@
};
internal-regs {
- L2: l2-cache {
+ L2: l2-cache@8000 {
compatible = "marvell,aurora-outer-cache";
reg = <0x08000 0x1000>;
cache-id-part = <0x100>;
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 097ea70736e2..5274e4ff5d62 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -78,7 +78,7 @@
reg = <0x1400 0x500>;
};
- L2: l2-cache {
+ L2: l2-cache@8000 {
compatible = "marvell,aurora-system-cache";
reg = <0x08000 0x1000>;
cache-id-part = <0x100>;
--
cgit
From 6f477f43f9de0a2e57d4ed3493021e0b0f7a477e Mon Sep 17 00:00:00 2001
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
Date: Sun, 6 Nov 2016 09:29:35 +0100
Subject: ARM: dts: armada-370-xp: Fixup memory DT warning
memory has a reg property so the unit name should contain an address.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm/boot/dts/armada-370-db.dts | 2 +-
arch/arm/boot/dts/armada-370-dlink-dns327l.dts | 2 +-
arch/arm/boot/dts/armada-370-mirabox.dts | 2 +-
arch/arm/boot/dts/armada-370-netgear-rn102.dts | 2 +-
arch/arm/boot/dts/armada-370-netgear-rn104.dts | 2 +-
arch/arm/boot/dts/armada-370-rd.dts | 2 +-
arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi | 2 +-
arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi | 2 +-
arch/arm/boot/dts/armada-370-synology-ds213j.dts | 2 +-
arch/arm/boot/dts/armada-xp-axpwifiap.dts | 2 +-
arch/arm/boot/dts/armada-xp-db.dts | 2 +-
arch/arm/boot/dts/armada-xp-gp.dts | 2 +-
arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts | 2 +-
arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 2 +-
arch/arm/boot/dts/armada-xp-matrix.dts | 2 +-
arch/arm/boot/dts/armada-xp-netgear-rn2120.dts | 2 +-
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 2 +-
arch/arm/boot/dts/armada-xp-synology-ds414.dts | 2 +-
18 files changed, 18 insertions(+), 18 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index f3adc187c6a5..a9419f8e17e8 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -67,7 +67,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x40000000>; /* 1 GB */
};
diff --git a/arch/arm/boot/dts/armada-370-dlink-dns327l.dts b/arch/arm/boot/dts/armada-370-dlink-dns327l.dts
index 9e499eeede4b..aeedc463daa6 100644
--- a/arch/arm/boot/dts/armada-370-dlink-dns327l.dts
+++ b/arch/arm/boot/dts/armada-370-dlink-dns327l.dts
@@ -62,7 +62,7 @@
stdout-path = &uart0;
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MiB */
};
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index c4dded0cd0c1..a1425409e570 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -54,7 +54,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
};
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
index 99b9d73ebbaf..6bd9265f1062 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
@@ -56,7 +56,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
};
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
index b5dd30178725..c84ab5bf1e18 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
@@ -56,7 +56,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
};
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index 29722b9f288e..023eeda7cfec 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -67,7 +67,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
};
diff --git a/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi b/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi
index 9b582c47f10c..4aec32c9b6df 100644
--- a/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi
+++ b/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi
@@ -23,7 +23,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
};
diff --git a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi b/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi
index bb678a45ac8e..75ad77b26a47 100644
--- a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi
+++ b/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi
@@ -24,7 +24,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
};
diff --git a/arch/arm/boot/dts/armada-370-synology-ds213j.dts b/arch/arm/boot/dts/armada-370-synology-ds213j.dts
index a696bbf0f703..1a7a9497fbc5 100644
--- a/arch/arm/boot/dts/armada-370-synology-ds213j.dts
+++ b/arch/arm/boot/dts/armada-370-synology-ds213j.dts
@@ -70,7 +70,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
};
diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
index d12b06bf0d60..e7b306ad84e8 100644
--- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts
+++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
@@ -62,7 +62,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000 0x40000000>; /* 1GB */
};
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index 8b9c606bfbc6..44a724d39dbe 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -67,7 +67,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0 0x00000000 0 0x80000000>; /* 2 GB */
};
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index fca37e92b96a..72cb8fa377e3 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -68,7 +68,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
/*
* 8 GB of plug-in RAM modules by default.The amount
diff --git a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
index 1dce74d9b616..d848ae9007db 100644
--- a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
+++ b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
@@ -57,7 +57,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0 0x00000000 0 0x20000000>; /* 512MB */
};
diff --git a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
index 488a047481d4..4f2b8aae397c 100644
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
@@ -62,7 +62,7 @@
stdout-path = &uart0;
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000 0x10000000>; /* 256MB */
};
diff --git a/arch/arm/boot/dts/armada-xp-matrix.dts b/arch/arm/boot/dts/armada-xp-matrix.dts
index 8b5a4e79d26b..16277380e714 100644
--- a/arch/arm/boot/dts/armada-xp-matrix.dts
+++ b/arch/arm/boot/dts/armada-xp-matrix.dts
@@ -55,7 +55,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
/*
* This board has 4 GB of RAM, but the last 256 MB of
diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
index 5aaaf0fb2330..a2f0e789465d 100644
--- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
+++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
@@ -56,7 +56,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0 0x00000000 0 0x80000000>; /* 2GB */
};
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index a0e36e166b02..8a14b32c70e1 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -57,7 +57,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0 0x00000000 0 0x40000000>; /* 1 GB soldered on */
};
diff --git a/arch/arm/boot/dts/armada-xp-synology-ds414.dts b/arch/arm/boot/dts/armada-xp-synology-ds414.dts
index d5630a7b4b18..0524b1b0c039 100644
--- a/arch/arm/boot/dts/armada-xp-synology-ds414.dts
+++ b/arch/arm/boot/dts/armada-xp-synology-ds414.dts
@@ -70,7 +70,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0 0x00000000 0 0x40000000>; /* 1GB */
};
--
cgit
From eb94ec6423ad3bc2d9c0d9e40da245b422b003e4 Mon Sep 17 00:00:00 2001
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
Date: Sun, 6 Nov 2016 10:35:41 +0100
Subject: ARM: dts: armada-370-xp: Remove address from dsa unit name
The dsa node does not have a reg property, so remove the address from the
unit name.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm/boot/dts/armada-370-rd.dts | 2 +-
arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index 023eeda7cfec..e2ba4bd52ecf 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -172,7 +172,7 @@
};
};
- dsa@0 {
+ dsa {
compatible = "marvell,dsa";
#address-cells = <2>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
index 4f2b8aae397c..7c8cd7b450e5 100644
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
@@ -301,7 +301,7 @@
4500 1>;
};
- dsa@0 {
+ dsa {
compatible = "marvell,dsa";
#address-cells = <2>;
#size-cells = <0>;
--
cgit
From 9e622af05c2e206c37db0f0d2ea20c3200daf8d1 Mon Sep 17 00:00:00 2001
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
Date: Sun, 6 Nov 2016 10:59:19 +0100
Subject: ARM: dts: armada-370-xp: Remove button address and fixup names
The gpio-key nodes do not have a reg property, so remove the address from
the unit name.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm/boot/dts/armada-370-rd.dts | 2 +-
arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi | 6 +++---
arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi | 6 +++---
arch/arm/boot/dts/armada-xp-axpwifiap.dts | 2 +-
arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 4 ++--
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 2 +-
6 files changed, 11 insertions(+), 11 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index e2ba4bd52ecf..c3fd6e49212f 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -122,7 +122,7 @@
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
- button@1 {
+ button {
label = "Software Button";
linux,code = <KEY_POWER>;
gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi b/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi
index 4aec32c9b6df..e9a5b952afc0 100644
--- a/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi
+++ b/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi
@@ -141,19 +141,19 @@
#address-cells = <1>;
#size-cells = <0>;
- button@1 {
+ power {
label = "Power button";
linux,code = <KEY_POWER>;
gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
debounce-interval = <100>;
};
- button@2 {
+ backup {
label = "Backup button";
linux,code = <KEY_OPTION>;
gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
debounce-interval = <100>;
};
- button@3 {
+ reset {
label = "Reset Button";
linux,code = <KEY_RESTART>;
gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi b/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi
index 75ad77b26a47..d079a89ee5a2 100644
--- a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi
+++ b/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi
@@ -89,19 +89,19 @@
#address-cells = <1>;
#size-cells = <0>;
- button@1 {
+ power {
label = "Power button";
linux,code = <KEY_POWER>;
gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
debounce-interval = <100>;
};
- button@2 {
+ reset {
label = "Reset Button";
linux,code = <KEY_RESTART>;
gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
debounce-interval = <100>;
};
- button@3 {
+ button {
label = "USB VBUS error";
linux,code = <KEY_UNKNOWN>;
gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
index e7b306ad84e8..1e1fc4fccbad 100644
--- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts
+++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
@@ -113,7 +113,7 @@
pinctrl-0 = <&keys_pin>;
pinctrl-names = "default";
- button@1 {
+ reset {
label = "Factory Reset Button";
linux,code = <KEY_SETUP>;
gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
index 7c8cd7b450e5..83ac884c0f8a 100644
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
@@ -267,13 +267,13 @@
pinctrl-0 = <&keys_pin>;
pinctrl-names = "default";
- button@1 {
+ wps {
label = "WPS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
};
- button@2 {
+ reset {
label = "Factory Reset Button";
linux,code = <KEY_RESTART>;
gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 8a14b32c70e1..b577c9fb03a4 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -139,7 +139,7 @@
#address-cells = <1>;
#size-cells = <0>;
- button@1 {
+ init {
label = "Init Button";
linux,code = <KEY_POWER>;
gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
--
cgit
From baa2f7447e18efabc2b8293bc330c67babbd68e0 Mon Sep 17 00:00:00 2001
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
Date: Sun, 6 Nov 2016 11:05:32 +0100
Subject: ARM: dts: armada-370-xp: Fixup regulator DT warning
regulator has a reg property so the unit name should contain an address.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm/boot/dts/armada-370-synology-ds213j.dts | 4 ++--
arch/arm/boot/dts/armada-xp-synology-ds414.dts | 8 ++++----
2 files changed, 6 insertions(+), 6 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/armada-370-synology-ds213j.dts b/arch/arm/boot/dts/armada-370-synology-ds213j.dts
index 1a7a9497fbc5..99f9de229ea8 100644
--- a/arch/arm/boot/dts/armada-370-synology-ds213j.dts
+++ b/arch/arm/boot/dts/armada-370-synology-ds213j.dts
@@ -186,7 +186,7 @@
pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin>;
pinctrl-names = "default";
- sata1_regulator: sata1-regulator {
+ sata1_regulator: sata1-regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "SATA1 Power";
@@ -199,7 +199,7 @@
gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
};
- sata2_regulator: sata2-regulator {
+ sata2_regulator: sata2-regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "SATA2 Power";
diff --git a/arch/arm/boot/dts/armada-xp-synology-ds414.dts b/arch/arm/boot/dts/armada-xp-synology-ds414.dts
index 0524b1b0c039..e803da03146a 100644
--- a/arch/arm/boot/dts/armada-xp-synology-ds414.dts
+++ b/arch/arm/boot/dts/armada-xp-synology-ds414.dts
@@ -154,7 +154,7 @@
&sata3_pwr_pin &sata4_pwr_pin>;
pinctrl-names = "default";
- sata1_regulator: sata1-regulator {
+ sata1_regulator: sata1-regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "SATA1 Power";
@@ -167,7 +167,7 @@
gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
};
- sata2_regulator: sata2-regulator {
+ sata2_regulator: sata2-regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "SATA2 Power";
@@ -180,7 +180,7 @@
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
};
- sata3_regulator: sata3-regulator {
+ sata3_regulator: sata3-regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "SATA3 Power";
@@ -193,7 +193,7 @@
gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
};
- sata4_regulator: sata4-regulator {
+ sata4_regulator: sata4-regulator@4 {
compatible = "regulator-fixed";
reg = <4>;
regulator-name = "SATA4 Power";
--
cgit
From e4a0709da2d3af10d4ae2e1955a572001b44708f Mon Sep 17 00:00:00 2001
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
Date: Wed, 9 Nov 2016 23:42:22 +0100
Subject: ARM: dts: armada-375: Add node labels
As it was previously done for kirkwood and for aramda 370/XP, this adds
missing node labels to Armada 375 and SoC specific nodes to allow to
reference them more easily.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm/boot/dts/armada-375.dtsi | 62 +++++++++++++++++++--------------------
1 file changed, 31 insertions(+), 31 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi
index 45fa92f9cf5c..e016ff3ed970 100644
--- a/arch/arm/boot/dts/armada-375.dtsi
+++ b/arch/arm/boot/dts/armada-375.dtsi
@@ -84,12 +84,12 @@
#size-cells = <0>;
enable-method = "marvell,armada-375-smp";
- cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
};
- cpu@1 {
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
@@ -115,7 +115,7 @@
reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
};
- devbus-bootcs {
+ devbus_bootcs: devbus-bootcs {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
@@ -125,7 +125,7 @@
status = "disabled";
};
- devbus-cs0 {
+ devbus_cs0: devbus-cs0 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
@@ -135,7 +135,7 @@
status = "disabled";
};
- devbus-cs1 {
+ devbus_cs1: devbus-cs1 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
@@ -145,7 +145,7 @@
status = "disabled";
};
- devbus-cs2 {
+ devbus_cs2: devbus-cs2 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
@@ -155,7 +155,7 @@
status = "disabled";
};
- devbus-cs3 {
+ devbus_cs3: devbus-cs3 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
@@ -182,12 +182,12 @@
prefetch-data = <1>;
};
- scu@c000 {
+ scu: scu@c000 {
compatible = "arm,cortex-a9-scu";
reg = <0xc000 0x58>;
};
- timer@c600 {
+ timer0: timer@c600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xc600 0x20>;
interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
@@ -203,7 +203,7 @@
<0xc100 0x100>;
};
- mdio {
+ mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "marvell,orion-mdio";
@@ -212,7 +212,7 @@
};
/* Network controller */
- ethernet@f0000 {
+ ethernet: ethernet@f0000 {
compatible = "marvell,armada-375-pp2";
reg = <0xf0000 0xa000>, /* Packet Processor regs */
<0xc0000 0x3060>, /* LMS regs */
@@ -235,7 +235,7 @@
};
};
- rtc@10300 {
+ rtc: rtc@10300 {
compatible = "marvell,orion-rtc";
reg = <0x10300 0x20>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
@@ -307,7 +307,7 @@
status = "disabled";
};
- pinctrl {
+ pinctrl: pinctrl {
compatible = "marvell,mv88f6720-pinctrl";
reg = <0x18000 0x24>;
@@ -382,7 +382,7 @@
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
};
- system-controller@18200 {
+ systemc: system-controller@18200 {
compatible = "marvell,armada-375-system-controller";
reg = <0x18200 0x100>;
};
@@ -415,7 +415,7 @@
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
- timer@20300 {
+ timer1: timer@20300 {
compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
reg = <0x20300 0x30>, <0x21040 0x30>;
interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
@@ -428,24 +428,24 @@
clock-names = "nbclk", "fixed";
};
- watchdog@20300 {
+ watchdog: watchdog@20300 {
compatible = "marvell,armada-375-wdt";
reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
clocks = <&coreclk 0>, <&refclk>;
clock-names = "nbclk", "fixed";
};
- cpurst@20800 {
+ cpurst: cpurst@20800 {
compatible = "marvell,armada-370-cpu-reset";
reg = <0x20800 0x10>;
};
- coherency-fabric@21010 {
+ coherencyfab: coherency-fabric@21010 {
compatible = "marvell,armada-375-coherency-fabric";
reg = <0x21010 0x1c>;
};
- usb@50000 {
+ usb0: usb@50000 {
compatible = "marvell,orion-ehci";
reg = <0x50000 0x500>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
@@ -455,7 +455,7 @@
status = "disabled";
};
- usb@54000 {
+ usb1: usb@54000 {
compatible = "marvell,orion-ehci";
reg = <0x54000 0x500>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
@@ -463,7 +463,7 @@
status = "disabled";
};
- usb3@58000 {
+ usb2: usb3@58000 {
compatible = "marvell,armada-375-xhci";
reg = <0x58000 0x20000>,<0x5b880 0x80>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
@@ -473,7 +473,7 @@
status = "disabled";
};
- xor@60800 {
+ xor0: xor@60800 {
compatible = "marvell,orion-xor";
reg = <0x60800 0x100
0x60A00 0x100>;
@@ -493,7 +493,7 @@
};
};
- xor@60900 {
+ xor1: xor@60900 {
compatible = "marvell,orion-xor";
reg = <0x60900 0x100
0x60b00 0x100>;
@@ -513,7 +513,7 @@
};
};
- crypto@90000 {
+ cesa: crypto@90000 {
compatible = "marvell,armada-375-crypto";
reg = <0x90000 0x10000>;
reg-names = "regs";
@@ -528,7 +528,7 @@
marvell,crypto-sram-size = <0x800>;
};
- sata@a0000 {
+ sata: sata@a0000 {
compatible = "marvell,armada-370-sata";
reg = <0xa0000 0x5000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
@@ -537,7 +537,7 @@
status = "disabled";
};
- nand@d0000 {
+ nand: nand@d0000 {
compatible = "marvell,armada370-nand";
reg = <0xd0000 0x54>;
#address-cells = <1>;
@@ -547,7 +547,7 @@
status = "disabled";
};
- mvsdio@d4000 {
+ sdio: mvsdio@d4000 {
compatible = "marvell,orion-sdio";
reg = <0xd4000 0x200>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
@@ -559,7 +559,7 @@
status = "disabled";
};
- thermal@e8078 {
+ thermal: thermal@e8078 {
compatible = "marvell,armada375-thermal";
reg = <0xe8078 0x4>, <0xe807c 0x8>;
status = "okay";
@@ -580,7 +580,7 @@
};
};
- pcie-controller {
+ pciec: pcie-controller {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci";
@@ -599,7 +599,7 @@
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>;
- pcie@1,0 {
+ pcie0: pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
@@ -616,7 +616,7 @@
status = "disabled";
};
- pcie@2,0 {
+ pcie1: pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
--
cgit
From 3a33467f42bf728119533e5f9d376574c48003a9 Mon Sep 17 00:00:00 2001
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
Date: Wed, 9 Nov 2016 23:59:30 +0100
Subject: ARM: dts: armada-375: Use the node labels
Use the node label when possible. As a result it flattens the device tree
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm/boot/dts/armada-375-db.dts | 269 ++++++++++++++++++------------------
1 file changed, 136 insertions(+), 133 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/armada-375-db.dts b/arch/arm/boot/dts/armada-375-db.dts
index cded5f0a262d..b33a674088ed 100644
--- a/arch/arm/boot/dts/armada-375-db.dts
+++ b/arch/arm/boot/dts/armada-375-db.dts
@@ -69,138 +69,141 @@
MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>;
- internal-regs {
- spi@10600 {
- pinctrl-0 = <&spi0_pins>;
- pinctrl-names = "default";
- /*
- * SPI conflicts with NAND, so we disable it
- * here, and select NAND as the enabled device
- * by default.
- */
- status = "disabled";
-
- spi-flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "n25q128a13", "jedec,spi-nor";
- reg = <0>; /* Chip select 0 */
- spi-max-frequency = <108000000>;
- };
- };
-
- i2c@11000 {
- status = "okay";
- clock-frequency = <100000>;
- pinctrl-0 = <&i2c0_pins>;
- pinctrl-names = "default";
- };
-
- i2c@11100 {
- status = "okay";
- clock-frequency = <100000>;
- pinctrl-0 = <&i2c1_pins>;
- pinctrl-names = "default";
- };
-
- serial@12000 {
- status = "okay";
- };
-
- pinctrl {
- sdio_st_pins: sdio-st-pins {
- marvell,pins = "mpp44", "mpp45";
- marvell,function = "gpio";
- };
- };
-
- sata@a0000 {
- status = "okay";
- nr-ports = <2>;
- };
-
- nand: nand@d0000 {
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
- status = "okay";
- num-cs = <1>;
- marvell,nand-keep-config;
- marvell,nand-enable-arbiter;
- nand-on-flash-bbt;
- nand-ecc-strength = <4>;
- nand-ecc-step-size = <512>;
-
- partition@0 {
- label = "U-Boot";
- reg = <0 0x800000>;
- };
- partition@800000 {
- label = "Linux";
- reg = <0x800000 0x800000>;
- };
- partition@1000000 {
- label = "Filesystem";
- reg = <0x1000000 0x3f000000>;
- };
- };
-
- usb@54000 {
- status = "okay";
- };
-
- usb3@58000 {
- status = "okay";
- };
-
- mvsdio@d4000 {
- pinctrl-0 = <&sdio_pins &sdio_st_pins>;
- pinctrl-names = "default";
- status = "okay";
- cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
- wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
- };
-
- mdio {
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
-
- phy3: ethernet-phy@3 {
- reg = <3>;
- };
- };
-
- ethernet@f0000 {
- status = "okay";
-
- eth0@c4000 {
- status = "okay";
- phy = <&phy0>;
- phy-mode = "rgmii-id";
- };
-
- eth1@c5000 {
- status = "okay";
- phy = <&phy3>;
- phy-mode = "gmii";
- };
- };
- };
-
- pcie-controller {
- status = "okay";
- /*
- * The two PCIe units are accessible through
- * standard PCIe slots on the board.
- */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
- pcie@2,0 {
- /* Port 1, Lane 0 */
- status = "okay";
- };
- };
};
};
+&pciec {
+ status = "okay";
+};
+
+/*
+ * The two PCIe units are accessible through
+ * standard PCIe slots on the board.
+ */
+&pcie0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+};
+
+&pcie1 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+};
+
+
+&spi0 {
+ pinctrl-0 = <&spi0_pins>;
+ pinctrl-names = "default";
+
+ /*
+ * SPI conflicts with NAND, so we disable it here, and
+ * select NAND as the enabled device by default.
+ */
+
+ status = "disabled";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q128a13", "jedec,spi-nor";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <108000000>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <100000>;
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <100000>;
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-names = "default";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&pinctrl {
+ sdio_st_pins: sdio-st-pins {
+ marvell,pins = "mpp44", "mpp45";
+ marvell,function = "gpio";
+ };
+};
+
+&sata {
+ status = "okay";
+ nr-ports = <2>;
+};
+
+&nand {
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ num-cs = <1>;
+ marvell,nand-keep-config;
+ marvell,nand-enable-arbiter;
+ nand-on-flash-bbt;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0 0x800000>;
+ };
+ partition@800000 {
+ label = "Linux";
+ reg = <0x800000 0x800000>;
+ };
+ partition@1000000 {
+ label = "Filesystem";
+ reg = <0x1000000 0x3f000000>;
+ };
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
+
+&sdio {
+ pinctrl-0 = <&sdio_pins &sdio_st_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+};
+
+&mdio {
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ };
+};
+
+ðernet {
+ status = "okay";
+};
+
+
+ð0 {
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+};
+
+ð1 {
+ status = "okay";
+ phy = <&phy3>;
+ phy-mode = "gmii";
+};
--
cgit
From 6b15260482db5485a1bd143a024bb0f794cd7a9d Mon Sep 17 00:00:00 2001
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
Date: Thu, 10 Nov 2016 00:05:33 +0100
Subject: ARM: dts: armada-375: Fixup mdio DT warning
MDIO has a reg property so the unit name should contain an address.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm/boot/dts/armada-375.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi
index e016ff3ed970..97b663d83fb6 100644
--- a/arch/arm/boot/dts/armada-375.dtsi
+++ b/arch/arm/boot/dts/armada-375.dtsi
@@ -203,7 +203,7 @@
<0xc100 0x100>;
};
- mdio: mdio {
+ mdio: mdio@c0054 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "marvell,orion-mdio";
--
cgit
From 5eacabfe946b4b4e38f61b1a81195ba782be50ad Mon Sep 17 00:00:00 2001
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
Date: Thu, 10 Nov 2016 00:24:44 +0100
Subject: ARM: dts: armada-375: Fixup pcie DT warnings
PCIe has a range property, so the unit name should contain an address.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm/boot/dts/armada-375.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi
index 97b663d83fb6..8eabcc15cb8a 100644
--- a/arch/arm/boot/dts/armada-375.dtsi
+++ b/arch/arm/boot/dts/armada-375.dtsi
@@ -580,7 +580,7 @@
};
};
- pciec: pcie-controller {
+ pciec: pcie-controller@82000000 {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci";
--
cgit
From 41c2f4e4c619ff2500c404f87a953d1abd8f9b21 Mon Sep 17 00:00:00 2001
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
Date: Thu, 10 Nov 2016 00:37:21 +0100
Subject: ARM: dts: armada-375: Fixup pinctrl DT warnings
pinctrl has a ranges property, so the unit name should contain an
address.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm/boot/dts/armada-375.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi
index 8eabcc15cb8a..cff81da5898a 100644
--- a/arch/arm/boot/dts/armada-375.dtsi
+++ b/arch/arm/boot/dts/armada-375.dtsi
@@ -307,7 +307,7 @@
status = "disabled";
};
- pinctrl: pinctrl {
+ pinctrl: pinctrl@18000 {
compatible = "marvell,mv88f6720-pinctrl";
reg = <0x18000 0x24>;
--
cgit
From 4b91a217d4965faff96883c59659e76297ca5cc2 Mon Sep 17 00:00:00 2001
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
Date: Thu, 10 Nov 2016 00:50:26 +0100
Subject: ARM: dts: armada-375: Remove skeleton.dtsi
The skeleton.dtsi file was removed in ARM64 for different reasons as
explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi").
These also applies to ARM and it will also allow to get rid of the
following DTC warnings in the future:
"Node /memory has a reg or ranges property, but no unit name"
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm/boot/dts/armada-375.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi
index cff81da5898a..e71aeb183da6 100644
--- a/arch/arm/boot/dts/armada-375.dtsi
+++ b/arch/arm/boot/dts/armada-375.dtsi
@@ -45,7 +45,6 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/phy/phy.h>
@@ -53,6 +52,9 @@
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
model = "Marvell Armada 375 family SoC";
compatible = "marvell,armada375";
--
cgit
From 1a15dca330e8d75b7a2f9cfc66c7d782e09fe850 Mon Sep 17 00:00:00 2001
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
Date: Thu, 10 Nov 2016 00:51:54 +0100
Subject: ARM: dts: armada-375: Fixup memory DT warning
memory has a reg property so the unit name should contain an address.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm/boot/dts/armada-375-db.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/armada-375-db.dts b/arch/arm/boot/dts/armada-375-db.dts
index b33a674088ed..ef45cbeb3e7d 100644
--- a/arch/arm/boot/dts/armada-375-db.dts
+++ b/arch/arm/boot/dts/armada-375-db.dts
@@ -58,7 +58,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x40000000>; /* 1 GB */
};
--
cgit
From 2f7132852038deb8e364bee155f51cb477c8d2f4 Mon Sep 17 00:00:00 2001
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
Date: Thu, 10 Nov 2016 00:58:18 +0100
Subject: ARM: dts: armada-375: Fixup ethernet child DT warning
Child of mvpp2 ethernet do not have a reg property so the unit name
should not contain an address: remove them.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm/boot/dts/armada-375.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi
index e71aeb183da6..f515591e8733 100644
--- a/arch/arm/boot/dts/armada-375.dtsi
+++ b/arch/arm/boot/dts/armada-375.dtsi
@@ -224,13 +224,13 @@
clock-names = "pp_clk", "gop_clk";
status = "disabled";
- eth0: eth0@c4000 {
+ eth0: eth0 {
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
port-id = <0>;
status = "disabled";
};
- eth1: eth1@c5000 {
+ eth1: eth1 {
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
port-id = <1>;
status = "disabled";
--
cgit
From 2957e36e76c836b167e5e0c1edb578d8a9bd7af6 Mon Sep 17 00:00:00 2001
From: Alexandre Bailon <abailon@baylibre.com>
Date: Wed, 16 Nov 2016 12:07:35 +0100
Subject: ARM: dts: da850: Add the usb otg device node
This adds the device tree node for the usb otg
controller present in the da850 family of SoC's.
Signed-off-by: Alexandre Bailon <abailon@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
arch/arm/boot/dts/da850.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 36066fab2e57..6205917b4f59 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -387,6 +387,16 @@
dma-names = "rx", "tx";
status = "disabled";
};
+ usb0: usb@200000 {
+ compatible = "ti,da830-musb";
+ reg = <0x200000 0x10000>;
+ interrupts = <58>;
+ interrupt-names = "mc";
+ dr_mode = "otg";
+ phys = <&usb_phy 0>;
+ phy-names = "usb-phy";
+ status = "disabled";
+ };
mdio: mdio@224000 {
compatible = "ti,davinci_mdio";
#address-cells = <1>;
--
cgit
From 83de086cc89410a8d4e0b6345e8a1116797ea703 Mon Sep 17 00:00:00 2001
From: Alexandre Bailon <abailon@baylibre.com>
Date: Wed, 16 Nov 2016 12:07:36 +0100
Subject: ARM: dts: da850-lcdk: Enable the usb otg device node
This enables the usb otg controller for the lcdk board.
Signed-off-by: Alexandre Bailon <abailon@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
arch/arm/boot/dts/da850-lcdk.dts | 8 ++++++++
1 file changed, 8 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/da850-lcdk.dts b/arch/arm/boot/dts/da850-lcdk.dts
index 7b8ab21fed6c..03f9bfda5385 100644
--- a/arch/arm/boot/dts/da850-lcdk.dts
+++ b/arch/arm/boot/dts/da850-lcdk.dts
@@ -158,6 +158,14 @@
rx-num-evt = <32>;
};
+&usb_phy {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
&aemif {
pinctrl-names = "default";
pinctrl-0 = <&nand_pins>;
--
cgit
From 7c38dc624bc49d83d84c185e2ca14adf352c5eaa Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Mon, 21 Nov 2016 09:23:31 -0600
Subject: ARM: dts: socfpga: fine-tune L2 cache configuration
Enable double-linefill and increase prefetch offset, which gives
considerable read performance boost. The following numbers were
obtained using lmbench 3.0 bw_mem tool, for easier comparison, the
numbers are pasted in two columns. The test machine has Cyclone V
SoC running at 800MHz MPU clock and 512MiB 333MHz 16bit DDR3 DRAM.
Without patch | With patch
$ for i in rd wr rdwr cp fwr frd fcp bzero bcopy ; do echo $i ; bw_mem 64M $i ; done
rd | rd
64.00 526.46 | 64.00 1151.06
wr | wr
64.00 329.95 | 64.00 346.14
rdwr | rdwr
64.00 342.07 | 64.00 367.24
cp | cp
64.00 239.79 | 64.00 322.47
fwr | fwr
64.00 1027.90 | 64.00 1025.38
frd | frd
64.00 322.36 | 64.00 641.89
fcp | fcp
64.00 256.99 | 64.00 408.41
bzero | bzero
64.00 1028.43 | 64.00 1025.07
bcopy | bcopy
64.00 294.73 | 64.00 357.19
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
arch/arm/boot/dts/socfpga.dtsi | 5 +++++
1 file changed, 5 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 27c1d46127cf..da689659131f 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -687,6 +687,11 @@
prefetch-data = <1>;
prefetch-instr = <1>;
arm,shared-override;
+ arm,double-linefill = <1>;
+ arm,double-linefill-incr = <0>;
+ arm,double-linefill-wrap = <1>;
+ arm,prefetch-drop = <0>;
+ arm,prefetch-offset = <7>;
};
mmc: dwmmc0@ff704000 {
--
cgit
From a9aa4233b8948ef212dd0b62d0bf4e8ef0b8894b Mon Sep 17 00:00:00 2001
From: Axel Haslam <ahaslam@baylibre.com>
Date: Mon, 21 Nov 2016 16:41:55 +0100
Subject: ARM: dts: da850-lcdk: fix mmc card detect polarity
The polarity of the card detect pin is inverted.
Change it to reflect the right polarity for the board
which is ACTIVE_LOW.
Signed-off-by: Axel Haslam <ahaslam@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
arch/arm/boot/dts/da850-lcdk.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/da850-lcdk.dts b/arch/arm/boot/dts/da850-lcdk.dts
index 03f9bfda5385..8411a91911fd 100644
--- a/arch/arm/boot/dts/da850-lcdk.dts
+++ b/arch/arm/boot/dts/da850-lcdk.dts
@@ -122,7 +122,7 @@
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
- cd-gpios = <&gpio 64 GPIO_ACTIVE_HIGH>;
+ cd-gpios = <&gpio 64 GPIO_ACTIVE_LOW>;
status = "okay";
};
--
cgit
From dc0aea386a62d3ffc85d97ebb3880711cab71e3a Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Fri, 7 Oct 2016 00:06:26 +0800
Subject: ARM: dts: sun6i: Sort pinmux setting nodes
The pinmux setting nodes for the A31 were added out of alphabetical
order. Sort them.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun6i-a31.dtsi | 82 ++++++++++++++++++++--------------------
1 file changed, 41 insertions(+), 41 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index ce1960453a0b..c1b891e75f18 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -434,13 +434,48 @@
#interrupt-cells = <3>;
#gpio-cells = <3>;
- uart0_pins_a: uart0@0 {
- allwinner,pins = "PH20", "PH21";
- allwinner,function = "uart0";
+ gmac_pins_gmii_a: gmac_gmii@0 {
+ allwinner,pins = "PA0", "PA1", "PA2", "PA3",
+ "PA4", "PA5", "PA6", "PA7",
+ "PA8", "PA9", "PA10", "PA11",
+ "PA12", "PA13", "PA14", "PA15",
+ "PA16", "PA17", "PA18", "PA19",
+ "PA20", "PA21", "PA22", "PA23",
+ "PA24", "PA25", "PA26", "PA27";
+ allwinner,function = "gmac";
+ /*
+ * data lines in GMII mode run at 125MHz and
+ * might need a higher signal drive strength
+ */
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ gmac_pins_mii_a: gmac_mii@0 {
+ allwinner,pins = "PA0", "PA1", "PA2", "PA3",
+ "PA8", "PA9", "PA11",
+ "PA12", "PA13", "PA14", "PA19",
+ "PA20", "PA21", "PA22", "PA23",
+ "PA24", "PA26", "PA27";
+ allwinner,function = "gmac";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+ gmac_pins_rgmii_a: gmac_rgmii@0 {
+ allwinner,pins = "PA0", "PA1", "PA2", "PA3",
+ "PA9", "PA10", "PA11",
+ "PA12", "PA13", "PA14", "PA19",
+ "PA20", "PA25", "PA26", "PA27";
+ allwinner,function = "gmac";
+ /*
+ * data lines in RGMII mode use DDR mode
+ * and need a higher signal drive strength
+ */
+ allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
i2c0_pins_a: i2c0@0 {
allwinner,pins = "PH14", "PH15";
allwinner,function = "i2c0";
@@ -506,47 +541,12 @@
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
- gmac_pins_mii_a: gmac_mii@0 {
- allwinner,pins = "PA0", "PA1", "PA2", "PA3",
- "PA8", "PA9", "PA11",
- "PA12", "PA13", "PA14", "PA19",
- "PA20", "PA21", "PA22", "PA23",
- "PA24", "PA26", "PA27";
- allwinner,function = "gmac";
+ uart0_pins_a: uart0@0 {
+ allwinner,pins = "PH20", "PH21";
+ allwinner,function = "uart0";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
-
- gmac_pins_gmii_a: gmac_gmii@0 {
- allwinner,pins = "PA0", "PA1", "PA2", "PA3",
- "PA4", "PA5", "PA6", "PA7",
- "PA8", "PA9", "PA10", "PA11",
- "PA12", "PA13", "PA14", "PA15",
- "PA16", "PA17", "PA18", "PA19",
- "PA20", "PA21", "PA22", "PA23",
- "PA24", "PA25", "PA26", "PA27";
- allwinner,function = "gmac";
- /*
- * data lines in GMII mode run at 125MHz and
- * might need a higher signal drive strength
- */
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- gmac_pins_rgmii_a: gmac_rgmii@0 {
- allwinner,pins = "PA0", "PA1", "PA2", "PA3",
- "PA9", "PA10", "PA11",
- "PA12", "PA13", "PA14", "PA19",
- "PA20", "PA25", "PA26", "PA27";
- allwinner,function = "gmac";
- /*
- * data lines in RGMII mode use DDR mode
- * and need a higher signal drive strength
- */
- allwinner,drive = <SUN4I_PINCTRL_40_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
};
timer@01c20c00 {
--
cgit
From 960eb12dc5c056fe8ceaf6afeab13f28de07409b Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime.ripard@free-electrons.com>
Date: Thu, 12 May 2016 10:23:41 +0200
Subject: ARM: sun5i: a13-olinuxino: Enable VGA bridge
Now that we have support for the VGA bridges using our DRM driver, enable
the display engine for the Olimex A13-Olinuxino.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 54 +++++++++++++++++++++++++++++++
1 file changed, 54 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index b3c234c65ea1..bb7210e0e4a9 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -72,6 +72,47 @@
default-state = "on";
};
};
+
+ bridge {
+ compatible = "dumb-vga-dac";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ vga_bridge_in: endpoint {
+ remote-endpoint = <&tcon0_out_vga>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ vga_bridge_out: endpoint {
+ remote-endpoint = <&vga_con_in>;
+ };
+ };
+ };
+ };
+
+ vga {
+ compatible = "vga-connector";
+
+ port {
+ vga_con_in: endpoint {
+ remote-endpoint = <&vga_bridge_out>;
+ };
+ };
+ };
+};
+
+&be0 {
+ status = "okay";
};
&ehci0 {
@@ -211,6 +252,19 @@
status = "okay";
};
+&tcon0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_rgb666_pins>;
+ status = "okay";
+};
+
+&tcon0_out {
+ tcon0_out_vga: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vga_bridge_in>;
+ };
+};
+
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins_b>;
--
cgit
From f19802bd4dd1596fcae3a8f9577a9d06c6c921b8 Mon Sep 17 00:00:00 2001
From: Emmanuel Vadot <manu@bidouilliste.com>
Date: Sat, 15 Oct 2016 17:23:40 +0200
Subject: ARM: dts: sunxi: Add cpu-supply for Olimex A20 EVB
sun7i-a20-olimex-som-evb.dts doesn't contain cpu-supply needed for
voltage-scaling with cpufreq-dt so define it.
The default voltages are defined in sun7i-a20.dtsi.
Signed-off-by: Emmanuel Vadot <manu@bidouilliste.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts | 4 ++++
1 file changed, 4 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts
index 23aacce4d6c7..134e0c1b129d 100644
--- a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts
@@ -88,6 +88,10 @@
status = "okay";
};
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
&codec {
status = "okay";
};
--
cgit
From 6d0e5b70be13e703974b4fa03e833d5f39519ea9 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Thu, 20 Oct 2016 11:43:42 +0800
Subject: ARM: dts: sun6i: Add device nodes for first display pipeline
The A31 has 2 parallel display pipelines, which can be intermixed.
However the driver currently only supports one of them.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun6i-a31.dtsi | 152 ++++++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/sun6i-a31s.dtsi | 8 ++
2 files changed, 160 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index c1b891e75f18..4d2c7786b92a 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -231,6 +231,11 @@
};
};
+ de: display-engine {
+ compatible = "allwinner,sun6i-a31-display-engine";
+ allwinner,pipelines = <&fe0>;
+ };
+
soc@01c00000 {
compatible = "simple-bus";
#address-cells = <1>;
@@ -246,6 +251,44 @@
#dma-cells = <1>;
};
+ tcon0: lcd-controller@01c0c000 {
+ compatible = "allwinner,sun6i-a31-tcon";
+ reg = <0x01c0c000 0x1000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&ccu RST_AHB1_LCD0>;
+ reset-names = "lcd";
+ clocks = <&ccu CLK_AHB1_LCD0>,
+ <&ccu CLK_LCD0_CH0>,
+ <&ccu CLK_LCD0_CH1>;
+ clock-names = "ahb",
+ "tcon-ch0",
+ "tcon-ch1";
+ clock-output-names = "tcon0-pixel-clock";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon0_in_drc0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&drc0_out_tcon0>;
+ };
+ };
+
+ tcon0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
+ };
+
mmc0: mmc@01c0f000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c0f000 0x1000>;
@@ -799,6 +842,115 @@
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ fe0: display-frontend@01e00000 {
+ compatible = "allwinner,sun6i-a31-display-frontend";
+ reg = <0x01e00000 0x20000>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>,
+ <&ccu CLK_DRAM_FE0>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&ccu RST_AHB1_FE0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fe0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ fe0_out_be0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&be0_in_fe0>;
+ };
+ };
+ };
+ };
+
+ be0: display-backend@01e60000 {
+ compatible = "allwinner,sun6i-a31-display-backend";
+ reg = <0x01e60000 0x10000>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>,
+ <&ccu CLK_DRAM_BE0>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&ccu RST_AHB1_BE0>;
+
+ assigned-clocks = <&ccu CLK_BE0>;
+ assigned-clock-rates = <300000000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ be0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ be0_in_fe0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&fe0_out_be0>;
+ };
+ };
+
+ be0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ be0_out_drc0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&drc0_in_be0>;
+ };
+ };
+ };
+ };
+
+ drc0: drc@01e70000 {
+ compatible = "allwinner,sun6i-a31-drc";
+ reg = <0x01e70000 0x10000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>,
+ <&ccu CLK_DRAM_DRC0>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&ccu RST_AHB1_DRC0>;
+
+ assigned-clocks = <&ccu CLK_IEP_DRC0>;
+ assigned-clock-rates = <300000000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ drc0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ drc0_in_be0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&be0_out_drc0>;
+ };
+ };
+
+ drc0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ drc0_out_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_in_drc0>;
+ };
+ };
+ };
+ };
+
rtc: rtc@01f00000 {
compatible = "allwinner,sun6i-a31-rtc";
reg = <0x01f00000 0x54>;
diff --git a/arch/arm/boot/dts/sun6i-a31s.dtsi b/arch/arm/boot/dts/sun6i-a31s.dtsi
index c17a32771b98..97e2c51d0aea 100644
--- a/arch/arm/boot/dts/sun6i-a31s.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31s.dtsi
@@ -48,6 +48,14 @@
#include "sun6i-a31.dtsi"
+&de {
+ compatible = "allwinner,sun6i-a31s-display-engine";
+};
+
&pio {
compatible = "allwinner,sun6i-a31s-pinctrl";
};
+
+&tcon0 {
+ compatible = "allwinner,sun6i-a31s-tcon";
+};
--
cgit
From 0ff8219fa6dac17a6887b88599873b83ce51a5f2 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Thu, 20 Oct 2016 11:43:43 +0800
Subject: ARM: dts: sun6i: Add A31 LCD0 RGB888 pins
The LCD0 controller on the A31 can do RGB output up to 8 bits per
channel. Add the pins for RGB888 output.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun6i-a31.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 4d2c7786b92a..2e8bf93dcfb2 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -540,6 +540,19 @@
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+ lcd0_rgb888_pins: lcd0_rgb888 {
+ allwinner,pins = "PD0", "PD1", "PD2", "PD3",
+ "PD4", "PD5", "PD6", "PD7",
+ "PD8", "PD9", "PD10", "PD11",
+ "PD12", "PD13", "PD14", "PD15",
+ "PD16", "PD17", "PD18", "PD19",
+ "PD20", "PD21", "PD22", "PD23",
+ "PD24", "PD25", "PD26", "PD27";
+ allwinner,function = "lcd0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
mmc0_pins_a: mmc0@0 {
allwinner,pins = "PF0", "PF1", "PF2",
"PF3", "PF4", "PF5";
--
cgit
From 95f4b4f44414beac97b4221e2c219a1d0b719d1b Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime.ripard@free-electrons.com>
Date: Thu, 20 Oct 2016 08:47:40 +0200
Subject: ARM: gr8: Add the UART3
The GR8 has access to the UART3 controller, which was missing in the
DTSI. Add it.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm/boot/dts/sun5i-gr8.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sun5i-gr8.dtsi b/arch/arm/boot/dts/sun5i-gr8.dtsi
index ca54e03ef366..d7cf6be2549c 100644
--- a/arch/arm/boot/dts/sun5i-gr8.dtsi
+++ b/arch/arm/boot/dts/sun5i-gr8.dtsi
@@ -978,6 +978,16 @@
status = "disabled";
};
+ uart3: serial@01c28c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28c00 0x400>;
+ interrupts = <4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 19>;
+ status = "disabled";
+ };
+
i2c0: i2c@01c2ac00 {
compatible = "allwinner,sun4i-a10-i2c";
reg = <0x01c2ac00 0x400>;
--
cgit
From e900146c2f58385a3b44ab35dee8ad4387d056e2 Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime.ripard@free-electrons.com>
Date: Thu, 20 Oct 2016 09:18:54 +0200
Subject: ARM: gr8: Fix typo in the i2s mclk pin group
There was a dumb copy and paste mistake here, fix it.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm/boot/dts/sun5i-gr8.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sun5i-gr8.dtsi b/arch/arm/boot/dts/sun5i-gr8.dtsi
index d7cf6be2549c..74aff795e723 100644
--- a/arch/arm/boot/dts/sun5i-gr8.dtsi
+++ b/arch/arm/boot/dts/sun5i-gr8.dtsi
@@ -792,7 +792,7 @@
};
i2s0_mclk_pins_a: i2s0-mclk@0 {
- allwinner,pins = "PB6", "PB7", "PB8", "PB9";
+ allwinner,pins = "PB5";
allwinner,function = "i2s0";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
--
cgit
From aade6b90d5846a08254f212de6c5f7757cdf4f6c Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime.ripard@free-electrons.com>
Date: Thu, 20 Oct 2016 08:49:59 +0200
Subject: ARM: gr8: Add missing pwm channel 1 pin
The PWM controller has two different channels, but only the first pin was
exposed in the DTSI. Add the other one.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm/boot/dts/sun5i-gr8.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sun5i-gr8.dtsi b/arch/arm/boot/dts/sun5i-gr8.dtsi
index 74aff795e723..c68439b27ef9 100644
--- a/arch/arm/boot/dts/sun5i-gr8.dtsi
+++ b/arch/arm/boot/dts/sun5i-gr8.dtsi
@@ -854,6 +854,13 @@
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+ pwm1_pins: pwm1 {
+ allwinner,pins = "PG13";
+ allwinner,function = "pwm1";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
spdif_tx_pins_a: spdif@0 {
allwinner,pins = "PB10";
allwinner,function = "spdif";
--
cgit
From 7c432442c883651f8c278da40c058f8bac1c42a1 Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime.ripard@free-electrons.com>
Date: Thu, 20 Oct 2016 09:01:41 +0200
Subject: ARM: gr8: Add UART2 pins
The UART2 pins were missing from the DTSI. Add them.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm/boot/dts/sun5i-gr8.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sun5i-gr8.dtsi b/arch/arm/boot/dts/sun5i-gr8.dtsi
index c68439b27ef9..48e5eea9c3ab 100644
--- a/arch/arm/boot/dts/sun5i-gr8.dtsi
+++ b/arch/arm/boot/dts/sun5i-gr8.dtsi
@@ -881,6 +881,20 @@
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+
+ uart2_pins_a: uart2@1 {
+ allwinner,pins = "PD2", "PD3";
+ allwinner,function = "uart2";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart2_cts_rts_pins_a: uart2-cts-rts@0 {
+ allwinner,pins = "PD4", "PD5";
+ allwinner,function = "uart2";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
};
pwm: pwm@01c20e00 {
--
cgit
From 15df8ad971f4f20cdafe3e8651d64c2a1b8aa5ba Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime.ripard@free-electrons.com>
Date: Thu, 20 Oct 2016 09:01:41 +0200
Subject: ARM: gr8: Add UART3 pins
The UART3 pins were missing from the DTSI. Add them.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm/boot/dts/sun5i-gr8.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sun5i-gr8.dtsi b/arch/arm/boot/dts/sun5i-gr8.dtsi
index 48e5eea9c3ab..ea86d4d58db6 100644
--- a/arch/arm/boot/dts/sun5i-gr8.dtsi
+++ b/arch/arm/boot/dts/sun5i-gr8.dtsi
@@ -895,6 +895,20 @@
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+
+ uart3_pins_a: uart3@1 {
+ allwinner,pins = "PG9", "PG10";
+ allwinner,function = "uart3";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart3_cts_rts_pins_a: uart3-cts-rts@0 {
+ allwinner,pins = "PG11", "PG12";
+ allwinner,function = "uart3";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
};
pwm: pwm@01c20e00 {
--
cgit
From e63604933ec72b268444a59ca357b4e96449480b Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime.ripard@free-electrons.com>
Date: Thu, 1 Sep 2016 18:27:21 +0200
Subject: ARM: gr8: Add CHIP Pro support
The CHIP Pro is a small embeddable board. It features a GR8, an AXP209
PMIC, a 512MB SLC NAND and a WiFi/BT chip.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/sun5i-gr8-chip-pro.dts | 266 +++++++++++++++++++++++++++++++
2 files changed, 267 insertions(+)
create mode 100644 arch/arm/boot/dts/sun5i-gr8-chip-pro.dts
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index c558ba75cbcc..8b4dc8123a66 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -760,6 +760,7 @@ dtb-$(CONFIG_MACH_SUN5I) += \
sun5i-a13-olinuxino-micro.dtb \
sun5i-a13-q8-tablet.dtb \
sun5i-a13-utoo-p66.dtb \
+ sun5i-gr8-chip-pro.dtb \
sun5i-gr8-evb.dtb \
sun5i-r8-chip.dtb
dtb-$(CONFIG_MACH_SUN6I) += \
diff --git a/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts b/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts
new file mode 100644
index 000000000000..92a2dc6250a5
--- /dev/null
+++ b/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts
@@ -0,0 +1,266 @@
+/*
+ * Copyright 2016 Free Electrons
+ * Copyright 2016 NextThing Co
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun5i-gr8.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ model = "NextThing C.H.I.P. Pro";
+ compatible = "nextthing,chip-pro", "nextthing,gr8";
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ status {
+ label = "chip-pro:white:status";
+ gpios = <&axp_gpio 2 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ mmc0_pwrseq: mmc0_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_reg_on_pin_chip_pro>;
+ reset-gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; /* PB10 */
+ };
+};
+
+&codec {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ reg = <0x34>;
+
+ /*
+ * The interrupt is routed through the "External Fast
+ * Interrupt Request" pin (ball G13 of the module)
+ * directly to the main interrupt controller, without
+ * any other controller interfering.
+ */
+ interrupts = <0>;
+ };
+};
+
+#include "axp209.dtsi"
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "disabled";
+};
+
+&i2s0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s0_mclk_pins_a>, <&i2s0_data_pins_a>;
+ status = "disabled";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>;
+ vmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&mmc0_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+};
+
+&nfc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>;
+ status = "okay";
+
+ nand@0 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0>;
+ allwinner,rb = <0>;
+ nand-ecc-mode = "hw";
+ };
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&otg_sram {
+ status = "okay";
+};
+
+&pio {
+ usb0_id_pin_chip_pro: usb0-id-pin@0 {
+ allwinner,pins = "PG2";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ wifi_reg_on_pin_chip_pro: wifi-reg-on-pin@0 {
+ allwinner,pins = "PB10";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pins_a>, <&pwm1_pins>;
+ status = "disabled";
+};
+
+®_dcdc2 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+ regulator-always-on;
+};
+
+®_dcdc3 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-name = "vdd-sys";
+ regulator-always-on;
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "avcc";
+ regulator-always-on;
+};
+
+/*
+ * Both LDO3 and LDO4 are used in parallel to power up the
+ * WiFi/BT chip.
+ */
+®_ldo3 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-1";
+ regulator-always-on;
+};
+
+®_ldo4 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-2";
+ regulator-always-on;
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins_a>, <&uart1_cts_rts_pins_a>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins_a>, <&uart2_cts_rts_pins_a>;
+ status = "disabled";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins_a>, <&uart3_cts_rts_pins_a>;
+ status = "okay";
+};
+
+&usb_otg {
+ /*
+ * The CHIP Pro doesn't have a controllable VBUS, nor does it
+ * have any 5v rail on the board itself.
+ *
+ * If one wants to use it as a true OTG port, it should be
+ * done in the baseboard, and its DT / overlay will add it.
+ */
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usb_power_supply {
+ status = "okay";
+};
+
+&usbphy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_id_pin_chip_pro>;
+ usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
+ usb0_vbus_power-supply = <&usb_power_supply>;
+ usb1_vbus-supply = <®_vcc5v0>;
+ status = "okay";
+};
--
cgit
From bb1ea8bf1bed9048dc51cb0b9ccacd63fcb0a3a0 Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime.ripard@free-electrons.com>
Date: Wed, 22 Jul 2015 16:51:33 +0200
Subject: ARM: sun5i: chip: Enable Wi-Fi SDIO chip
The WiFi chip is powered through a GPIO and two regulators in parallel.
Since that case is not supported yet, just set them as always on before we
rework the regulator framework to deal with those.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm/boot/dts/sun5i-r8-chip.dts | 41 +++++++++++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts
index b68a12374b35..e616084b9495 100644
--- a/arch/arm/boot/dts/sun5i-r8-chip.dts
+++ b/arch/arm/boot/dts/sun5i-r8-chip.dts
@@ -74,6 +74,13 @@
default-state = "on";
};
};
+
+ mmc0_pwrseq: mmc0_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&chip_wifi_reg_on_pin>;
+ reset-gpios = <&pio 2 19 GPIO_ACTIVE_LOW>; /* PC19 */
+ };
};
&be0 {
@@ -131,10 +138,15 @@
};
};
+&mmc0_pins_a {
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&mmc0_pwrseq>;
bus-width = <4>;
non-removable;
status = "okay";
@@ -156,6 +168,13 @@
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+ chip_wifi_reg_on_pin: chip_wifi_reg_on_pin@0 {
+ allwinner,pins = "PC19";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
chip_id_det_pin: chip_id_det_pin@0 {
allwinner,pins = "PG2";
allwinner,function = "gpio_in";
@@ -189,6 +208,28 @@
regulator-always-on;
};
+/*
+ * Both LDO3 and LDO4 are used in parallel to power up the WiFi/BT
+ * Chip.
+ *
+ * If those are not enabled, the SDIO part will not enumerate, and
+ * since there's no way currently to pass DT infos to an SDIO device,
+ * we cannot really do better than this ugly hack for now.
+ */
+®_ldo3 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-1";
+ regulator-always-on;
+};
+
+®_ldo4 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-2";
+ regulator-always-on;
+};
+
®_ldo5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
--
cgit
From 74194620add1fb9984184873a9dbf8a1002a00c2 Mon Sep 17 00:00:00 2001
From: Antoine Tenart <antoine.tenart@free-electrons.com>
Date: Thu, 1 Oct 2015 16:39:43 +0200
Subject: ARM: sun5i: chip: add a node for the w1 gpio controller
The CHIP uses a 1-Wire bus to discover the DIPs. Enable the bus in the DT.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun5i-r8-chip.dts | 14 ++++++++++++++
1 file changed, 14 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts
index e616084b9495..059d86865b73 100644
--- a/arch/arm/boot/dts/sun5i-r8-chip.dts
+++ b/arch/arm/boot/dts/sun5i-r8-chip.dts
@@ -81,6 +81,13 @@
pinctrl-0 = <&chip_wifi_reg_on_pin>;
reset-gpios = <&pio 2 19 GPIO_ACTIVE_LOW>; /* PC19 */
};
+
+ onewire {
+ compatible = "w1-gpio";
+ gpios = <&pio 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&chip_w1_pin>;
+ };
};
&be0 {
@@ -181,6 +188,13 @@
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+
+ chip_w1_pin: chip_w1_pin@0 {
+ allwinner,pins = "PD2";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
};
®_dcdc2 {
--
cgit
From 915688621ba485fe7f232621229cb125e776f407 Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime.ripard@free-electrons.com>
Date: Fri, 14 Oct 2016 16:32:26 +0200
Subject: ARM: sun5i: Rename A10s pins
The SPI2 pins on the sun5i PB bank are only available on the A10s. Rename
the A10s only bank so that it doesn't confuse people on the other SoCs
whose indexing would start at b.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 4 ++--
arch/arm/boot/dts/sun5i-a10s.dtsi | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
index aef91476f9ae..0684d7930d65 100644
--- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
@@ -250,8 +250,8 @@
&spi2 {
pinctrl-names = "default";
- pinctrl-0 = <&spi2_pins_a>,
- <&spi2_cs0_pins_a>;
+ pinctrl-0 = <&spi2_pins_b>,
+ <&spi2_cs0_pins_b>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index c41a2ba34dde..7aa8c7aa0153 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -243,14 +243,14 @@
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
- spi2_pins_a: spi2@0 {
+ spi2_pins_b: spi2@1 {
allwinner,pins = "PB12", "PB13", "PB14";
allwinner,function = "spi2";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
- spi2_cs0_pins_a: spi2_cs0@0 {
+ spi2_cs0_pins_b: spi2_cs0@1 {
allwinner,pins = "PB11";
allwinner,function = "spi2";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
--
cgit
From 9255fb6c7e0c7069832811e81f90e18a1f124500 Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime.ripard@free-electrons.com>
Date: Mon, 18 Jul 2016 20:51:30 +0200
Subject: ARM: sun5i: Add SPI2 pins
All the sun5i have the SPI2 pins exposed on the PE bank. Add them to the
DT.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm/boot/dts/sun5i.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index e374f4fc8073..245cee14cf1d 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -591,6 +591,20 @@
allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
};
+ spi2_pins_a: spi2@0 {
+ allwinner,pins = "PE1", "PE2", "PE3";
+ allwinner,function = "spi2";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ spi2_cs0_pins_a: spi2-cs0@0 {
+ allwinner,pins = "PE0";
+ allwinner,function = "spi2";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
uart3_pins_a: uart3@0 {
allwinner,pins = "PG9", "PG10";
allwinner,function = "uart3";
--
cgit
From 60a47e43436e57a780192eca28ca316aafd6510d Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime.ripard@free-electrons.com>
Date: Thu, 25 Feb 2016 17:15:30 -0800
Subject: ARM: sun5i: Add RGB 565 LCD pins
Some boards use the LCD in RGB565. Enable the pin muxing option.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm/boot/dts/sun5i.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 245cee14cf1d..b4ccee8cfb02 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -574,6 +574,16 @@
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+ lcd_rgb565_pins: lcd_rgb565@0 {
+ allwinner,pins = "PD3", "PD4", "PD5", "PD6", "PD7",
+ "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
+ "PD19", "PD20", "PD21", "PD22", "PD23",
+ "PD24", "PD25", "PD26", "PD27";
+ allwinner,function = "lcd0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
mmc0_pins_a: mmc0@0 {
allwinner,pins = "PF0", "PF1", "PF2", "PF3",
"PF4", "PF5";
--
cgit
From 77df9d66b0b1ad01c685fd6341ce501493899658 Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime.ripard@free-electrons.com>
Date: Fri, 14 Oct 2016 17:39:10 +0200
Subject: ARM: sun5i: chip: Add optional buses
The I2C1 and SPI2 buses are exposed on the CHIP headers, and are not
explicitly dedicated to anything.
Add them to the DTS with the muxing already set, but keep them disabled.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm/boot/dts/sun5i-r8-chip.dts | 14 ++++++++++++++
1 file changed, 14 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts
index 059d86865b73..c6da5ad37152 100644
--- a/arch/arm/boot/dts/sun5i-r8-chip.dts
+++ b/arch/arm/boot/dts/sun5i-r8-chip.dts
@@ -56,9 +56,11 @@
aliases {
i2c0 = &i2c0;
+ i2c1 = &i2c1;
i2c2 = &i2c2;
serial0 = &uart1;
serial1 = &uart3;
+ spi0 = &spi2;
};
chosen {
@@ -126,6 +128,12 @@
#include "axp209.dtsi"
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "disabled";
+};
+
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
@@ -257,6 +265,12 @@
status = "okay";
};
+&spi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pins_a>;
+ status = "disabled";
+};
+
&tcon0 {
status = "okay";
};
--
cgit
From 56b0730157f70dc23d6caff9e7ceb8b377b96b9f Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Fri, 28 Oct 2016 18:11:52 +0800
Subject: ARM: dts: sun9i: Add mmc1 pinmux setting
On the A80, mmc1 is available on pingroup G. Designs mostly use this
to connect to an SDIO WiFi chip.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun9i-a80.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index 3c5214cbe4e6..ab6a221027ef 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -700,6 +700,14 @@
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+ mmc1_pins: mmc1 {
+ allwinner,pins = "PG0", "PG1" ,"PG2", "PG3",
+ "PG4", "PG5";
+ allwinner,function = "mmc1";
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
mmc2_8bit_pins: mmc2_8bit {
allwinner,pins = "PC6", "PC7", "PC8", "PC9",
"PC10", "PC11", "PC12",
--
cgit
From 6cf4eaef12f1ecc47a7d657108f1776dbf57953c Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Fri, 28 Oct 2016 18:11:53 +0800
Subject: ARM: dts: sun9i: a80-optimus: Enable AP6330 WiFi
The board has a Ampak AP6330 WiFi/BT/FM module. Inside it is a Broadcom
BCM4330 WiFi/BT/FM combo IC. The WiFi portion is connected to mmc1, with
the enabling pin connected to PL2. The AC100 RTC provides a low power
clock signal.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun9i-a80-optimus.dts | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts
index ceb6ef15d669..7e036b2be762 100644
--- a/arch/arm/boot/dts/sun9i-a80-optimus.dts
+++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts
@@ -105,6 +105,14 @@
enable-active-high;
gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
};
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&ac100_rtc 1>;
+ clock-names = "ext_clock";
+ /* enables internal regulator and de-asserts reset */
+ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
+ };
};
&ehci0 {
@@ -130,6 +138,21 @@
status = "okay";
};
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>, <&wifi_en_pin_optimus>;
+ vmmc-supply = <®_dldo1>;
+ vqmmc-supply = <®_cldo3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+};
+
+&mmc1_pins {
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+};
+
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_8bit_pins>;
@@ -199,6 +222,13 @@
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+
+ wifi_en_pin_optimus: wifi_en_pin@0 {
+ allwinner,pins = "PL2";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
};
&r_rsb {
--
cgit
From e62c46bcdd533046da364e37b47c8e8f38745be1 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Fri, 28 Oct 2016 18:11:54 +0800
Subject: ARM: dts: sun9i: cubieboard4: Enable AP6330 WiFi
The board has a Ampak AP6330 WiFi/BT/FM module. Inside it is a Broadcom
BCM4330 WiFi/BT/FM combo IC. The WiFi portion is connected to mmc1, with
the enabling pin connected to PL2. The AC100 RTC provides a low power
clock signal.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun9i-a80-cubieboard4.dts | 32 +++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
index 439847acd41e..67b02fe7f11c 100644
--- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
+++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
@@ -76,6 +76,14 @@
gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
};
};
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&ac100_rtc 1>;
+ clock-names = "ext_clock";
+ /* enables internal regulator and de-asserts reset */
+ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
+ };
};
&mmc0 {
@@ -88,6 +96,21 @@
status = "okay";
};
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>, <&wifi_en_pin_cubieboard4>;
+ vmmc-supply = <®_dldo1>;
+ vqmmc-supply = <®_cldo3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+};
+
+&mmc1_pins {
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+};
+
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_8bit_pins>;
@@ -128,6 +151,15 @@
status = "okay";
};
+&r_pio {
+ wifi_en_pin_cubieboard4: wifi_en_pin@0 {
+ allwinner,pins = "PL2";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
&r_rsb {
status = "okay";
--
cgit
From 49f01c9e14b3476cbdf9623c4812c43f6485830b Mon Sep 17 00:00:00 2001
From: Milo Kim <woogyom.kim@gmail.com>
Date: Fri, 28 Oct 2016 15:59:01 +0900
Subject: ARM: dts: sun8i: Add common dtsi file for NanoPi SBCs
This patch provides a common file for NanoPi M1 and Neo SBC.
Those have common features below.
* UART0
* 2 LEDs
* USB host (EHCI3, OHCI3) and PHY
* MicroSD
* GPIO key switch
Cc: James Pettigrew <james@innovum.com.au>
Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun8i-h3-nanopi.dtsi | 144 +++++++++++++++++++++++++++++++++
1 file changed, 144 insertions(+)
create mode 100644 arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
new file mode 100644
index 000000000000..8038aa29a5a7
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2016 James Pettigrew <james@innovum.com.au>
+ * Copyright (C) 2016 Milo Kim <woogyom.kim@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-h3.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&leds_npi>, <&leds_r_npi>;
+
+ status {
+ label = "nanopi:blue:status";
+ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ pwr {
+ label = "nanopi:green:pwr";
+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ r_gpio_keys {
+ compatible = "gpio-keys";
+ input-name = "k1";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sw_r_npi>;
+
+ k1@0 {
+ label = "k1";
+ linux,code = <KEY_POWER>;
+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&mmc0 {
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+ status = "okay";
+ vmmc-supply = <®_vcc3v3>;
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&pio {
+ leds_npi: led_pins@0 {
+ allwinner,pins = "PA10";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+&r_pio {
+ leds_r_npi: led_pins@0 {
+ allwinner,pins = "PL10";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ sw_r_npi: key_pins@0 {
+ allwinner,pins = "PL3";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
--
cgit
From f10239ea378e9afe0a8e0cf141e60e5372d5300b Mon Sep 17 00:00:00 2001
From: Milo Kim <woogyom.kim@gmail.com>
Date: Fri, 28 Oct 2016 15:59:02 +0900
Subject: ARM: dts: sun8i: Use the common file in NanoPi NEO SBC
NanoPi common dtsi supports all components of NEO SBC, so just include it.
Cc: James Pettigrew <james@innovum.com.au>
Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 79 +------------------------------
1 file changed, 1 insertion(+), 78 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
index 3d64cafc1e90..8d2cc6e9a03f 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
@@ -40,86 +40,9 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-/dts-v1/;
-#include "sun8i-h3.dtsi"
-#include "sunxi-common-regulators.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
+#include "sun8i-h3-nanopi.dtsi"
/ {
model = "FriendlyARM NanoPi NEO";
compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3";
-
- aliases {
- serial0 = &uart0;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&leds_opc>, <&leds_r_opc>;
-
- pwr {
- label = "nanopi:green:pwr";
- gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
- default-state = "on";
- };
-
- status {
- label = "nanopi:blue:status";
- gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */
- };
- };
-};
-
-&ehci3 {
- status = "okay";
-};
-
-&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
- vmmc-supply = <®_vcc3v3>;
- bus-width = <4>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
- cd-inverted;
- status = "okay";
-};
-
-&ohci3 {
- status = "okay";
-};
-
-&pio {
- leds_opc: led-pins {
- allwinner,pins = "PA10";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-};
-
-&r_pio {
- leds_r_opc: led-pins {
- allwinner,pins = "PL10";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
- status = "okay";
-};
-
-&usbphy {
- /* USB VBUS is always on */
- status = "okay";
};
--
cgit
From 10efbf5f16336b7540ad6a16aa1cb0b26bab033b Mon Sep 17 00:00:00 2001
From: Milo Kim <woogyom.kim@gmail.com>
Date: Fri, 28 Oct 2016 15:59:03 +0900
Subject: ARM: dts: sun8i: Add dts file for NanoPi M1 SBC
NanoPi M1 is the Allwinner H3 based board.
This patch enables UART for debug console, LEDs, GPIO key switch, 3 USB
host ports, a micro SD slot and related power and pin controls by using
NanoPi common dtsi file.
Cc: James Pettigrew <james@innovum.com.au>
Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts | 64 ++++++++++++++++++++++++++++++++
1 file changed, 64 insertions(+)
create mode 100644 arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts
new file mode 100644
index 000000000000..ec63d104b404
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2016 Milo Kim <woogyom.kim@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "sun8i-h3-nanopi.dtsi"
+
+/ {
+ model = "FriendlyArm NanoPi M1";
+ compatible = "friendlyarm,nanopi-m1", "allwinner,sun8i-h3";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
--
cgit
From eeeb2d64e8d656f879d7e1d54da3931b92962d3e Mon Sep 17 00:00:00 2001
From: Milo Kim <woogyom.kim@gmail.com>
Date: Fri, 28 Oct 2016 15:54:09 +0900
Subject: ARM: dts: sun8i: Add SPI pinctrl node in H3
H3 supports two SPI controllers. Four pins (MOSI, MISO, SCLK, SS) are
configured through the pinctrl subsystem.
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun8i-h3.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 75a865406d3e..8a59d8dbeabd 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -381,6 +381,20 @@
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+ spi0_pins: spi0 {
+ allwinner,pins = "PC0", "PC1", "PC2", "PC3";
+ allwinner,function = "spi0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ spi1_pins: spi1 {
+ allwinner,pins = "PA15", "PA16", "PA14", "PA13";
+ allwinner,function = "spi1";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
uart0_pins_a: uart0@0 {
allwinner,pins = "PA4", "PA5";
allwinner,function = "uart0";
--
cgit
From 8e1ce6c63e0f479ec61333383fae4eeca230ece6 Mon Sep 17 00:00:00 2001
From: Milo Kim <woogyom.kim@gmail.com>
Date: Fri, 28 Oct 2016 15:54:10 +0900
Subject: ARM: dts: sun8i: Add SPI controller node in H3
H3 SPI subsystem is almost same as A31 SPI except buffer size, so those
DT properties are reusable.
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun8i-h3.dtsi | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 8a59d8dbeabd..c38b028cac83 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -439,6 +439,38 @@
clocks = <&osc24M>;
};
+ spi0: spi@01c68000 {
+ compatible = "allwinner,sun8i-h3-spi";
+ reg = <0x01c68000 0x1000>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma 23>, <&dma 23>;
+ dma-names = "rx", "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>;
+ resets = <&ccu RST_BUS_SPI0>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi1: spi@01c69000 {
+ compatible = "allwinner,sun8i-h3-spi";
+ reg = <0x01c69000 0x1000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma 24>, <&dma 24>;
+ dma-names = "rx", "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins>;
+ resets = <&ccu RST_BUS_SPI1>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
wdt0: watchdog@01c20ca0 {
compatible = "allwinner,sun6i-a31-wdt";
reg = <0x01c20ca0 0x20>;
--
cgit
From e7c66334f676a63fd74c52863bbf983c795c788a Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime.ripard@free-electrons.com>
Date: Thu, 3 Nov 2016 13:41:41 +0100
Subject: ARM: gr8: evb: Enable SPDIF
The GR8-EVB has a SPDIF out connector. Enable it.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm/boot/dts/sun5i-gr8-evb.dts | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sun5i-gr8-evb.dts b/arch/arm/boot/dts/sun5i-gr8-evb.dts
index 714381fd64d7..e58c8ea3c692 100644
--- a/arch/arm/boot/dts/sun5i-gr8-evb.dts
+++ b/arch/arm/boot/dts/sun5i-gr8-evb.dts
@@ -75,6 +75,24 @@
brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
default-brightness-level = <8>;
};
+
+ spdif {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "On-board SPDIF";
+
+ simple-audio-card,cpu {
+ sound-dai = <&spdif>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&spdif_out>;
+ };
+ };
+
+ spdif_out: spdif-out {
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dit";
+ };
};
&be0 {
--
cgit
From 94a160c6560404210c25c59de00f9504a03b7af8 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Mon, 7 Nov 2016 18:07:01 +0800
Subject: ARM: dts: sun6i: Add audio codec device node
The A31 SoC includes the Allwinner audio codec, capable of 24-bit
playback up to 192 kHz and 24-bit capture up to 48 kHz.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun6i-a31.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 2e8bf93dcfb2..ef24669234a0 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -784,6 +784,19 @@
reset-names = "ahb";
};
+ codec: codec@01c22c00 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun6i-a31-codec";
+ reg = <0x01c22c00 0x400>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>;
+ clock-names = "apb", "codec";
+ resets = <&ccu RST_APB1_CODEC>;
+ dmas = <&dma 15>, <&dma 15>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
timer@01c60000 {
compatible = "allwinner,sun6i-a31-hstimer",
"allwinner,sun7i-a20-hstimer";
--
cgit
From 77042bec6f341e8086f24c8b9232792b1c2d101e Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Mon, 7 Nov 2016 18:07:02 +0800
Subject: ARM: dts: sun6i: hummingbird: Enable internal audio codec
The Hummingbird A31 has headset and line in audio jacks and an onboard
mic routed to the pins for the SoC's internal codec. The line out pins
are routed to an onboard speaker amp, whose output is available on a
pin header.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 13 +++++++++++++
1 file changed, 13 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
index 9a74637f677f..4e0516026596 100644
--- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
+++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
@@ -69,6 +69,19 @@
};
};
+&codec {
+ allwinner,audio-routing =
+ "Headphone", "HP",
+ "Speaker", "LINEOUT",
+ "LINEIN", "Line In",
+ "MIC1", "Mic",
+ "MIC2", "Headset Mic",
+ "Mic", "MBIAS",
+ "Headset Mic", "HBIAS";
+ allwinner,pa-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
+ status = "okay";
+};
+
&cpu0 {
cpu-supply = <®_dcdc3>;
};
--
cgit
From caed8b581578da50b90d484d85b7e06e437bc999 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Mon, 7 Nov 2016 18:07:03 +0800
Subject: ARM: dts: sun6i: sina31s: Enable internal audio codec
The SinA31s routes the SoC's LINEOUT pins to a line out jack, and MIC1
to a microphone jack, with MBIAS providing phantom power.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun6i-a31s-sina31s.dts | 8 ++++++++
1 file changed, 8 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts
index 6ead2f5c847a..c35ec112f5a0 100644
--- a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts
+++ b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts
@@ -65,6 +65,14 @@
};
};
+&codec {
+ allwinner,audio-routing =
+ "Line Out", "LINEOUT",
+ "MIC1", "Mic",
+ "Mic", "MBIAS";
+ status = "okay";
+};
+
&ehci0 {
/* USB 2.0 4 port hub IC */
status = "okay";
--
cgit
From b9b8daa203d85f50366b4dcfd985f51987daae57 Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime.ripard@free-electrons.com>
Date: Mon, 29 Aug 2016 21:59:46 +0200
Subject: ARM: gr8: evb: Add i2s codec
The GR8-EVB comes with a wm8978 codec connected to the i2s bus.
Add a card in order to have it working
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun5i-gr8-evb.dts | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sun5i-gr8-evb.dts b/arch/arm/boot/dts/sun5i-gr8-evb.dts
index e58c8ea3c692..030605aa8065 100644
--- a/arch/arm/boot/dts/sun5i-gr8-evb.dts
+++ b/arch/arm/boot/dts/sun5i-gr8-evb.dts
@@ -76,7 +76,22 @@
default-brightness-level = <8>;
};
- spdif {
+ sound-analog {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "gr8-evb-wm8978";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <512>;
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s0>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&wm8978>;
+ };
+ };
+
+ sound-spdif {
compatible = "simple-audio-card";
simple-audio-card,name = "On-board SPDIF";
--
cgit
From ff44ded689011fc92e5cb05784dc54d44767765e Mon Sep 17 00:00:00 2001
From: Sudeep Holla <sudeep.holla@arm.com>
Date: Mon, 14 Nov 2016 15:44:10 +0000
Subject: ARM: dts: sun8i: replace enable-sdio-wakeup with wakeup-source for
BananaPi M1+
Though the mmc core driver will continue to support the legacy
"enable-sdio-wakeup" property to enable SDIO as the wakeup source,
"wakeup-source" is the new standard binding.
This patch replaces the legacy "enable-sdio-wakeup" with the unified
"wakeup-source" property in order to avoid any further copy-paste
duplication.
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts
index ba5bca0fe997..1df47aa0a07b 100644
--- a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts
+++ b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts
@@ -167,7 +167,7 @@
mmc-pwrseq = <&mmc3_pwrseq>;
bus-width = <4>;
non-removable;
- enable-sdio-wakeup;
+ wakeup-source;
status = "okay";
brcmf: bcrmf@1 {
--
cgit
From 6a08816d9b7875726c658a42c67e72ad896afc8c Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Sun, 13 Nov 2016 20:22:03 +0100
Subject: ARM: dts: sun8i: reference-design-tablet: ldo_io1 is vcc-touchscreen
On some Q8 and other tablets ldo_io1 is used as vcc-touchscreen,
config at as such in sun8i-reference-design-tablet.dtsi.
Note that it will only be enabled when it us actually referenced by
a foo-supply property in the touchscreen node, so for tablets which
do not use ldo_io1 as vcc-touchscreen, it will be disabled.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts | 7 -------
arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi | 7 +++++++
2 files changed, 7 insertions(+), 7 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts
index a86cbedda34c..21bb291b9568 100644
--- a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts
+++ b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts
@@ -98,13 +98,6 @@
};
};
-®_ldo_io1 {
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-touchscreen";
- status = "okay";
-};
-
&touchscreen {
reg = <0x40>;
compatible = "silead,gsl1680";
diff --git a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
index 08cd00143635..69bc0cd26ca7 100644
--- a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
+++ b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
@@ -209,6 +209,13 @@
status = "okay";
};
+®_ldo_io1 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-touchscreen";
+ status = "okay";
+};
+
®_rtc_ldo {
regulator-name = "vcc-rtc";
};
--
cgit
From daa4c2603aea23227590f7c47af3c4d2c5524444 Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime.ripard@free-electrons.com>
Date: Fri, 4 Nov 2016 15:44:39 +0100
Subject: ARM: sun8i: sina33: Enable USB gadget
The micro-USB on the SinA33 has a somewhat interesting design in the sense
that it has a micro USB connector, but the VBUS is (supposed to be)
controlled through an (unpopulated) jumper.
Obviously, that doesn't work really well, and only the peripheral mode
really works. Still enable it.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 5 +++++
1 file changed, 5 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
index fef6abc0a703..71bb9418c5f9 100644
--- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
+++ b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
@@ -213,6 +213,11 @@
status = "okay";
};
+&usb_otg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
&usbphy {
status = "okay";
usb1_vbus-supply = <®_vcc5v0>; /* USB1 VBUS is always on */
--
cgit
From 0cff18cbab4f55581d9da86e4286655d9723d7d2 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Tue, 15 Nov 2016 21:51:04 +0800
Subject: ARM: dts: sun7i: bananapi-m1-plus: Enable USB PHY for USB host
support
The 2 USB host ports are directly tied to the 2 USB hosts in the SoC.
The 2 host pairs were already enabled, but the USB PHY wasn't.
VBUS on the 2 ports are always on.
Enable the USB PHY.
Fixes: 04c85ecad32a ("ARM: dts: sun7i: Add dts file for Bananapi M1 Plus
board")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts | 5 +++++
1 file changed, 5 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts
index 1df47aa0a07b..c88b48ab2836 100644
--- a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts
+++ b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts
@@ -227,3 +227,8 @@
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
+
+&usbphy {
+ /* VBUS on usb host ports are tied to DC5V and therefore always on */
+ status = "okay";
+};
--
cgit
From e57904eb69442af86108143019dd9f4336830664 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Tue, 15 Nov 2016 21:51:05 +0800
Subject: ARM: dts: sun7i: bananapi-m1-plus: Add PMIC regulators
The Bananapi M1+, like other Allwinner A20 based boards, uses the
AXP209 PMIC to supply its power.
Add the AXP209 regulators.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts | 35 +++++++++++++++++++++---
1 file changed, 31 insertions(+), 4 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts
index c88b48ab2836..f9b85fc8046e 100644
--- a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts
+++ b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts
@@ -105,6 +105,10 @@
status = "okay";
};
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
&ehci0 {
status = "okay";
};
@@ -132,16 +136,14 @@
status = "okay";
axp209: pmic@34 {
- compatible = "x-powers,axp209";
reg = <0x34>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
-
- interrupt-controller;
- #interrupt-cells = <1>;
};
};
+#include "axp209.dtsi"
+
&ir0 {
pinctrl-names = "default";
pinctrl-0 = <&ir0_rx_pins_a>;
@@ -222,6 +224,31 @@
};
};
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-int-dll";
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
--
cgit
From 82f2e1884eba4ad04af0a04dc0247cde631d451a Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Tue, 15 Nov 2016 21:51:06 +0800
Subject: ARM: dts: sun7i: bananapi-m1-plus: Enable USB OTG
The Bananapi M1+ supports USB OTG, with the PMIC doing VBUS sensing.
Enable the USB OTG related functions.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts
index f9b85fc8046e..532f1a160560 100644
--- a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts
+++ b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts
@@ -194,6 +194,10 @@
status = "okay";
};
+&otg_sram {
+ status = "okay";
+};
+
&pio {
gmac_power_pin_bpi_m1p: gmac_power_pin@0 {
allwinner,pins = "PH23";
@@ -249,13 +253,29 @@
regulator-name = "avcc";
};
+®_usb0_vbus {
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usb_power_supply {
+ status = "okay";
+};
+
&usbphy {
+ usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ usb0_vbus_power-supply = <&usb_power_supply>;
+ usb0_vbus-supply = <®_usb0_vbus>;
/* VBUS on usb host ports are tied to DC5V and therefore always on */
status = "okay";
};
--
cgit
From be7bc6b98781451d9ec55fa9267ac895f060d172 Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime.ripard@free-electrons.com>
Date: Wed, 19 Oct 2016 11:15:27 +0200
Subject: ARM: sunxi: Add the missing clocks to the pinctrl nodes
The pin controllers also use the two oscillators for debouncing. Add them
to the DTs.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm/boot/dts/sun4i-a10.dtsi | 3 ++-
arch/arm/boot/dts/sun5i.dtsi | 3 ++-
arch/arm/boot/dts/sun6i-a31.dtsi | 6 ++++--
arch/arm/boot/dts/sun7i-a20.dtsi | 3 ++-
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 6 ++++--
arch/arm/boot/dts/sun8i-h3.dtsi | 6 ++++--
arch/arm/boot/dts/sun9i-a80.dtsi | 6 ++++--
7 files changed, 22 insertions(+), 11 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 7e7dfc2b43db..b14a4281058d 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -967,7 +967,8 @@
compatible = "allwinner,sun4i-a10-pinctrl";
reg = <0x01c20800 0x400>;
interrupts = <28>;
- clocks = <&apb0_gates 5>;
+ clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index b4ccee8cfb02..b0fca4ef4dae 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -547,7 +547,8 @@
pio: pinctrl@01c20800 {
reg = <0x01c20800 0x400>;
interrupts = <28>;
- clocks = <&apb0_gates 5>;
+ clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index ef24669234a0..2b26175d55d1 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -471,7 +471,8 @@
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_APB1_PIO>;
+ clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;
@@ -1064,7 +1065,8 @@
reg = <0x01f02c00 0x400>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb0_gates 0>;
+ clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
resets = <&apb0_rst 0>;
gpio-controller;
interrupt-controller;
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 94cf5a1c7172..f7db067b0de0 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -1085,7 +1085,8 @@
compatible = "allwinner,sun7i-a20-pinctrl";
reg = <0x01c20800 0x400>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb0_gates 5>;
+ clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index 300a1bd5a6ec..e4991a78ad73 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -266,7 +266,8 @@
/* compatible gets set in SoC specific dtsi file */
reg = <0x01c20800 0x400>;
/* interrupts get set in SoC specific dtsi file */
- clocks = <&ccu CLK_BUS_PIO>;
+ clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;
@@ -575,7 +576,8 @@
compatible = "allwinner,sun8i-a23-r-pinctrl";
reg = <0x01f02c00 0x400>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb0_gates 0>;
+ clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
resets = <&apb0_rst 0>;
gpio-controller;
interrupt-controller;
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index c38b028cac83..3c6596f06ebc 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -321,7 +321,8 @@
reg = <0x01c20800 0x400>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_PIO>;
+ clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;
interrupt-controller;
@@ -614,7 +615,8 @@
compatible = "allwinner,sun8i-h3-r-pinctrl";
reg = <0x01f02c00 0x400>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb0_gates 0>;
+ clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
resets = <&apb0_reset 0>;
gpio-controller;
#gpio-cells = <3>;
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index ab6a221027ef..979ad1aacfb1 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -678,7 +678,8 @@
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb0_gates 5>;
+ clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;
@@ -902,7 +903,8 @@
reg = <0x08002c00 0x400>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apbs_gates 0>;
+ clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
resets = <&apbs_rst 0>;
gpio-controller;
interrupt-controller;
--
cgit
From 9bfe7c8d1af5a8a55a21b5407e1a35ed3c1b98eb Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Wed, 16 Nov 2016 14:15:08 +0100
Subject: ARM: dts: sun5i: Add touchscreen node to reference-design-tablet.dtsi
Just like on sun8i all sun5i tablets use the same interrupt and power
gpios for their touchscreens. I've checked all known a13 fex files and
only the UTOO P66 uses a different gpio for the interrupt.
Add a touchscreen node to sun5i-reference-design-tablet.dtsi, which
fills in the necessary gpios to avoid duplication in the tablet dts files,
just like we do in sun8i-reference-design-tablet.dtsi.
This will make future patches adding touchscreen nodes to a13 tablets
simpler.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun5i-a13-utoo-p66.dts | 38 ++++++++--------------
.../boot/dts/sun5i-reference-design-tablet.dtsi | 25 ++++++++++++++
2 files changed, 39 insertions(+), 24 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts
index a8b0bcc04514..3d7ff10a48e9 100644
--- a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts
+++ b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts
@@ -83,22 +83,6 @@
allwinner,pins = "PG3";
};
-&i2c1 {
- icn8318: touchscreen@40 {
- compatible = "chipone,icn8318";
- reg = <0x40>;
- interrupt-parent = <&pio>;
- interrupts = <6 9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */
- pinctrl-names = "default";
- pinctrl-0 = <&ts_wake_pin_p66>;
- wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
- touchscreen-size-x = <800>;
- touchscreen-size-y = <480>;
- touchscreen-inverted-x;
- touchscreen-swapped-x-y;
- };
-};
-
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins_a>;
@@ -121,20 +105,26 @@
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
};
-
- ts_wake_pin_p66: ts_wake_pin@0 {
- allwinner,pins = "PB3";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
};
®_usb0_vbus {
gpio = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
};
+&touchscreen {
+ compatible = "chipone,icn8318";
+ reg = <0x40>;
+ /* The P66 uses a different EINT then the reference design */
+ interrupts = <6 9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */
+ /* The icn8318 binding expects wake-gpios instead of power-gpios */
+ wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
+ touchscreen-size-x = <800>;
+ touchscreen-size-y = <480>;
+ touchscreen-inverted-x;
+ touchscreen-swapped-x-y;
+ status = "okay";
+};
+
&uart1 {
/* The P66 uses the uart pins as gpios */
status = "disabled";
diff --git a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi
index 20cc940f5f91..82f87cdcd164 100644
--- a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi
+++ b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi
@@ -41,6 +41,7 @@
*/
#include "sunxi-reference-design-tablet.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pwm/pwm.h>
/ {
@@ -84,6 +85,23 @@
};
&i2c1 {
+ /*
+ * The gsl1680 is rated at 400KHz and it will not work reliable at
+ * 100KHz, this has been confirmed on multiple different q8 tablets.
+ * All other devices on this bus are also rated for 400KHz.
+ */
+ clock-frequency = <400000>;
+
+ touchscreen: touchscreen {
+ interrupt-parent = <&pio>;
+ interrupts = <6 11 IRQ_TYPE_EDGE_FALLING>; /* EINT11 (PG11) */
+ pinctrl-names = "default";
+ pinctrl-0 = <&ts_power_pin>;
+ power-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
+ /* Tablet dts must provide reg and compatible */
+ status = "disabled";
+ };
+
pcf8563: rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
@@ -125,6 +143,13 @@
allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
};
+ ts_power_pin: ts_power_pin {
+ pins = "PB3";
+ function = "gpio_out";
+ drive-strength = <10>;
+ bias-disable;
+ };
+
usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
allwinner,pins = "PG1";
allwinner,function = "gpio_in";
--
cgit
From 0fa1c17c162f9a5f5ca8b244f7bad7fd0aa7bc60 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Wed, 16 Nov 2016 23:42:32 +0800
Subject: ARM: dts: sun6i: hummingbird-a31: Enable display output through VGA
bridge
The Hummingbird A31 board has a VGA DAC which converts RGB output
from the LCD interface to VGA analog signals.
Add nodes for the VGA DAC, its power supply, and enable this part
of the display pipeline.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 67 +++++++++++++++++++++++++++++
1 file changed, 67 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
index 4e0516026596..735914f6ae44 100644
--- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
+++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
@@ -63,6 +63,60 @@
stdout-path = "serial0:115200n8";
};
+ vga-connector {
+ compatible = "vga-connector";
+
+ port {
+ vga_con_in: endpoint {
+ remote-endpoint = <&vga_dac_out>;
+ };
+ };
+ };
+
+ vga-dac {
+ compatible = "dumb-vga-dac";
+ vdd-supply = <®_vga_3v3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ vga_dac_in: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_out_vga>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ vga_dac_out: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vga_con_in>;
+ };
+ };
+ };
+ };
+
+ reg_vga_3v3: vga_3v3_regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vga-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&pio 7 25 GPIO_ACTIVE_HIGH>; /* PH25 */
+ };
+
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 */
@@ -258,6 +312,19 @@
status = "okay";
};
+&tcon0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd0_rgb888_pins>;
+ status = "okay";
+};
+
+&tcon0_out {
+ tcon0_out_vga: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vga_dac_in>;
+ };
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
--
cgit
From 1f166499ce006b3770a3166122eda64e160736ab Mon Sep 17 00:00:00 2001
From: Keerthy <j-keerthy@ti.com>
Date: Thu, 10 Nov 2016 10:39:19 +0530
Subject: ARM: dts: am57xx-beagle-x15-common: Add overide powerhold property
The PMICs have POWERHOLD set by default which prevents PMIC shutdown
even on DEV_CTRL On bit set to 0 as the Powerhold has higher priority.
So to enable pmic power off this property lets one over ride the default
value and enable pmic power off.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi | 1 +
1 file changed, 1 insertion(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
index 6df7829a2c15..78bee26361f1 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
+++ b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
@@ -204,6 +204,7 @@
interrupt-controller;
ti,system-power-controller;
+ ti,palmas-override-powerhold;
tps659038_pmic {
compatible = "ti,tps659038-pmic";
--
cgit
From 8804755bfb1f3cbc003e4ebe99eac491672f354c Mon Sep 17 00:00:00 2001
From: Keerthy <j-keerthy@ti.com>
Date: Thu, 10 Nov 2016 10:39:20 +0530
Subject: ARM: dts: am57xx-idk-common: Add overide powerhold property
The PMICs have POWERHOLD set by default which prevents PMIC shutdown
even on DEV_CTRL On bit set to 0 as the Powerhold has higher priority.
So to enable pmic power off this property lets one over ride the default
value and enable pmic power off.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/am57xx-idk-common.dtsi | 1 +
1 file changed, 1 insertion(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/am57xx-idk-common.dtsi b/arch/arm/boot/dts/am57xx-idk-common.dtsi
index 35e210ce68a1..555ae21f2b9a 100644
--- a/arch/arm/boot/dts/am57xx-idk-common.dtsi
+++ b/arch/arm/boot/dts/am57xx-idk-common.dtsi
@@ -109,6 +109,7 @@
#interrupt-cells = <2>;
interrupt-controller;
ti,system-power-controller;
+ ti,palmas-override-powerhold;
tps659038_pmic {
compatible = "ti,tps659038-pmic";
--
cgit
From f5c59d165af1238d097f23f458b2c5d96a5e7d66 Mon Sep 17 00:00:00 2001
From: Yegor Yefremov <yegorslists@googlemail.com>
Date: Wed, 23 Nov 2016 16:49:26 +0100
Subject: ARM: dts: am335x-baltos: use phy-phandle declarations
phy-phandle is now a preferred method to reference a PHY device.
Especially in regards to cpsw it enables PHY specific settings like
max-speed etc. being specified in DTS.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/am335x-baltos-ir2110.dts | 10 ++++++++--
arch/arm/boot/dts/am335x-baltos-ir3220.dts | 2 +-
arch/arm/boot/dts/am335x-baltos-ir5221.dts | 2 +-
arch/arm/boot/dts/am335x-baltos.dtsi | 5 ++++-
4 files changed, 14 insertions(+), 5 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/am335x-baltos-ir2110.dts b/arch/arm/boot/dts/am335x-baltos-ir2110.dts
index a9a97307d66c..501c7527121b 100644
--- a/arch/arm/boot/dts/am335x-baltos-ir2110.dts
+++ b/arch/arm/boot/dts/am335x-baltos-ir2110.dts
@@ -54,16 +54,22 @@
dr_mode = "host";
};
+&davinci_mdio {
+ phy0: ethernet-phy@0 {
+ reg = <1>;
+ };
+};
+
&cpsw_emac0 {
- phy_id = <&davinci_mdio>, <1>;
phy-mode = "rmii";
dual_emac_res_vlan = <1>;
+ phy-handle = <&phy0>;
};
&cpsw_emac1 {
- phy_id = <&davinci_mdio>, <7>;
phy-mode = "rgmii-txid";
dual_emac_res_vlan = <2>;
+ phy-handle = <&phy1>;
};
&phy_sel {
diff --git a/arch/arm/boot/dts/am335x-baltos-ir3220.dts b/arch/arm/boot/dts/am335x-baltos-ir3220.dts
index fe002a17c04b..19f53b8569e1 100644
--- a/arch/arm/boot/dts/am335x-baltos-ir3220.dts
+++ b/arch/arm/boot/dts/am335x-baltos-ir3220.dts
@@ -109,9 +109,9 @@
};
&cpsw_emac1 {
- phy_id = <&davinci_mdio>, <7>;
phy-mode = "rgmii-txid";
dual_emac_res_vlan = <2>;
+ phy-handle = <&phy1>;
};
&phy_sel {
diff --git a/arch/arm/boot/dts/am335x-baltos-ir5221.dts b/arch/arm/boot/dts/am335x-baltos-ir5221.dts
index f599350dd305..2b9d7f4db23f 100644
--- a/arch/arm/boot/dts/am335x-baltos-ir5221.dts
+++ b/arch/arm/boot/dts/am335x-baltos-ir5221.dts
@@ -127,9 +127,9 @@
};
&cpsw_emac1 {
- phy_id = <&davinci_mdio>, <7>;
phy-mode = "rgmii-txid";
dual_emac_res_vlan = <2>;
+ phy-handle = <&phy1>;
};
&phy_sel {
diff --git a/arch/arm/boot/dts/am335x-baltos.dtsi b/arch/arm/boot/dts/am335x-baltos.dtsi
index 09b954154e6b..efb5eae290a8 100644
--- a/arch/arm/boot/dts/am335x-baltos.dtsi
+++ b/arch/arm/boot/dts/am335x-baltos.dtsi
@@ -364,11 +364,14 @@
};
&davinci_mdio {
+ status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
- status = "okay";
+ phy1: ethernet-phy@1 {
+ reg = <7>;
+ };
};
&mmc1 {
--
cgit
From 5817430ba7250cfc5a9c4a397935b07da16c9762 Mon Sep 17 00:00:00 2001
From: Schuyler Patton <spatton@ti.com>
Date: Tue, 22 Nov 2016 09:47:32 +0530
Subject: ARM: dts: AM571x-IDK Initial Support
The AM571x-IDK board is a board based on TI's AM5718 SOC
which has a single core 1.5GHz A15 processor. This board is a
development platform for the Industrial market with:
- 1GB of DDR3L
- Dual 1Gbps Ethernet
- HDMI,
- PRU-ICSS
- uSD
- 16GB eMMC
- CAN
- RS-485
- PCIe
- USB3.0
- Video Input Port
- Industrial IO port and expansion connector
The link to the data sheet and TRM can be found here:
http://www.ti.com/product/AM5718
Initial support is only for basic peripherals.
Signed-off-by: Schuyler Patton <spatton@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/am571x-idk.dts | 81 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 82 insertions(+)
create mode 100644 arch/arm/boot/dts/am571x-idk.dts
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 28df93f92701..02a0b1d01d95 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -589,6 +589,7 @@ dtb-$(CONFIG_SOC_DRA7XX) += \
am57xx-cl-som-am57x.dtb \
am57xx-sbc-am57x.dtb \
am572x-idk.dtb \
+ am571x-idk.dtb \
dra7-evm.dtb \
dra72-evm.dtb \
dra72-evm-revc.dtb \
diff --git a/arch/arm/boot/dts/am571x-idk.dts b/arch/arm/boot/dts/am571x-idk.dts
new file mode 100644
index 000000000000..d6e43e5184c1
--- /dev/null
+++ b/arch/arm/boot/dts/am571x-idk.dts
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "dra72x.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "am57xx-idk-common.dtsi"
+
+/ {
+ model = "TI AM5718 IDK";
+ compatible = "ti,am5718-idk", "ti,am5718", "ti,dra7";
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x40000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ cpu0-led {
+ label = "status0:red:cpu0";
+ gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "cpu0";
+ };
+
+ usr0-led {
+ label = "status0:green:usr";
+ gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ heartbeat-led {
+ label = "status0:blue:heartbeat";
+ gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "heartbeat";
+ };
+
+ usr1-led {
+ label = "status1:red:usr";
+ gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ usr2-led {
+ label = "status1:green:usr";
+ gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ mmc0-led {
+ label = "status1:blue:mmc0";
+ gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "mmc0";
+ };
+ };
+
+ extcon_usb2: extcon_usb2 {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&mmc1 {
+ status = "okay";
+ vmmc-supply = <&ldo1_reg>;
+ bus-width = <4>;
+ cd-gpios = <&gpio6 27 0>; /* gpio 219 */
+};
+
+&omap_dwc3_2 {
+ extcon = <&extcon_usb2>;
+};
--
cgit
From 6753c0ad974fc86fef05e0e5022c190e3e498de2 Mon Sep 17 00:00:00 2001
From: Niklas Cassel <niklas.cassel@axis.com>
Date: Wed, 23 Nov 2016 15:24:51 +0100
Subject: ARM: dts: exynos: Specify snps, dwmac in compatible string for gmac
devicetree binding for stmmac states:
- compatible: Should be "snps,dwmac-<ip_version>", "snps,dwmac"
For backwards compatibility: "st,spear600-gmac" is also supported.
No functional change intended.
Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/boot/dts/exynos5440.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index e6bffd13cedd..1012659888f0 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -188,7 +188,7 @@
};
gmac: ethernet@00230000 {
- compatible = "snps,dwmac-3.70a";
+ compatible = "snps,dwmac-3.70a", "snps,dwmac";
reg = <0x00230000 0x8000>;
interrupt-parent = <&gic>;
interrupts = <0 31 4>;
--
cgit
From 79700041b37f0aca5da3ea27858ad6c42f99a474 Mon Sep 17 00:00:00 2001
From: Jaehoon Chung <jh80.chung@samsung.com>
Date: Mon, 21 Nov 2016 16:10:32 +0900
Subject: ARM: dts: exynos: Remove the cd-gpios property for eMMC of Odroid
XU3/4
Odroid XU3/4 didn't need to use the cd-gpios for detecting card.
Because host controller has the CDETECT register through SDx_CDN line.
Host controller can know whether card is inserted or not with this
register.
When I have checked the Odroid XU3/4, they are using CDETECT register
(not using exteranl cd-gpio).
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 1 -
1 file changed, 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
index 9e63328b961f..05b9afdd6757 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
@@ -510,7 +510,6 @@
&mmc_0 {
status = "okay";
mmc-pwrseq = <&emmc_pwrseq>;
- cd-gpios = <&gpc0 2 GPIO_ACTIVE_LOW>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <0 4>;
--
cgit
From 5591aa4249436615b12ed980a457840f886656f9 Mon Sep 17 00:00:00 2001
From: Jacopo Mondi <jacopo@jmondi.org>
Date: Thu, 3 Nov 2016 20:34:46 +0100
Subject: ARM: dts: alt: Fix PFC names for DU
Update the PFC pin groups and function names of DU interface for
r8a7794 ALT board.
The currently specified pin groups and function names prevented PFC and
DU interfaces from being correctly configured:
sh-pfc e6060000.pin-controller: function 'du' not supported
sh-pfc e6060000.pin-controller: invalid function du in map table
sh-pfc e6060000.pin-controller: function 'du' not supported
sh-pfc e6060000.pin-controller: invalid function du in map table
sh-pfc e6060000.pin-controller: function 'du' not supported
sh-pfc e6060000.pin-controller: invalid function du in map table
sh-pfc e6060000.pin-controller: function 'du' not supported
sh-pfc e6060000.pin-controller: invalid function du in map table
rcar-du: probe of feb00000.display failed with error -22
Signed-off-by: Jacopo Mondi <jacopo@jmondi.org>
Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7794-alt.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index 325d3f972c57..a3e74684289b 100644
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -165,8 +165,8 @@
pinctrl-names = "default";
du_pins: du {
- groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_dotclkout0";
- function = "du";
+ groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out";
+ function = "du1";
};
scif2_pins: scif2 {
--
cgit
From dc8ee9dbdba509fb58e23ba79f2e6059fe5d8b3b Mon Sep 17 00:00:00 2001
From: Geert Uytterhoeven <geert+renesas@glider.be>
Date: Mon, 7 Nov 2016 20:07:07 +0100
Subject: ARM: dts: r8a7794: Correct hsusb parent clock
The parent clock of the HSUSB clock is the HP clock, not the MP clock.
Fixes: c7bab9f929e51761 ("ARM: shmobile: r8a7794: Add USB clocks to device tree")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7794.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 01816ac775a8..7d9f0601d3ca 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -1262,7 +1262,7 @@
mstp7_clks: mstp7_clks@e615014c {
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
- clocks = <&mp_clk>, <&mp_clk>,
+ clocks = <&mp_clk>, <&hp_clk>,
<&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
<&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
<&zx_clk>;
--
cgit
From 24b2d930a50662c11918fd0c22931f1448488da4 Mon Sep 17 00:00:00 2001
From: Geert Uytterhoeven <geert+renesas@glider.be>
Date: Mon, 7 Nov 2016 20:10:04 +0100
Subject: ARM: dts: r8a7794: Use SYSC "always-on" PM Domain for sound
Hook up the Audio-DMAC and sound device nodes to the SYSC "always-on" PM
Domain, for a more consistent device-power-area description in DT.
Cfr. commit 0761ff2ad0c581f3 ("ARM: dts: r8a7794: Add SYSC PM Domains").
Fixes: 320d6c5a08a4abd3 ("ARM: dts: r8a7794: add sound support")
Fixes: 298e4ee3d213a076 ("ARM: dts: r8a7794: add Audio-DMAC support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7794.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 7d9f0601d3ca..364b4aa8d1c1 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -319,7 +319,7 @@
"ch12";
clocks = <&mstp5_clks R8A7794_CLK_AUDIO_DMAC0>;
clock-names = "fck";
- power-domains = <&cpg_clocks>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
#dma-cells = <1>;
dma-channels = <13>;
};
@@ -1485,7 +1485,7 @@
"mix.0", "mix.1",
"dvc.0", "dvc.1",
"clk_a", "clk_b", "clk_c", "clk_i";
- power-domains = <&cpg_clocks>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
status = "disabled";
--
cgit
From 1e26fcf31c5c70557689184185913881e4557bc0 Mon Sep 17 00:00:00 2001
From: Simon Horman <horms+renesas@verge.net.au>
Date: Sun, 6 Nov 2016 21:20:19 +0100
Subject: ARM: dts: lager: rename and reindex i2cexio
The rename from i2cexio to i2cexio0 is in preparation for adding
i2cexio1 which will use the demuxer for IIC1/I2C1.
The reindexing from i2c8 to i2c10 is to allow space for grouping of
additional GPIO buses to be added by follow-up patches to support demuxing
of other i2c buses.
Also note that fallback to GPIO is not provided by the hardware for IIC0/I2C0.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
[wsa: rebased, fixed alias and removed typo in commit message]
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
arch/arm/boot/dts/r8a7790-lager.dts | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 434268262d88..5645444cd21a 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -50,7 +50,7 @@
aliases {
serial0 = &scif0;
serial1 = &scifa1;
- i2c8 = "i2cexio";
+ i2c10 = &i2cexio0;
};
chosen {
@@ -273,11 +273,13 @@
* bus with IIC3 on pins 110 (SCL) + 112 (SDA), select I2C0 at runtime, and
* instantiate the slave device at runtime according to the documentation.
* You can then communicate with the slave via IIC3.
+ *
+ * IIC0/I2C0 does not appear to support fallback to GPIO.
*/
- i2cexio: i2c-8 {
+ i2cexio0: i2c-10 {
compatible = "i2c-demux-pinctrl";
i2c-parent = <&iic0>, <&i2c0>;
- i2c-bus-name = "i2c-exio";
+ i2c-bus-name = "i2c-exio0";
#address-cells = <1>;
#size-cells = <0>;
};
@@ -596,12 +598,12 @@
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
- pinctrl-names = "i2c-exio";
+ pinctrl-names = "i2c-exio0";
};
&iic0 {
pinctrl-0 = <&iic0_pins>;
- pinctrl-names = "i2c-exio";
+ pinctrl-names = "i2c-exio0";
};
&iic1 {
--
cgit
From b2f15ca697a11c8df64ac6c8086ababc5c9e6060 Mon Sep 17 00:00:00 2001
From: Simon Horman <horms+renesas@verge.net.au>
Date: Sun, 6 Nov 2016 21:20:20 +0100
Subject: ARM: dts: lager: use demuxer for IIC1/I2C1
Make it possible to select which I2C1 IP core you want to run on the
EXIO-A connector.
This is based on reference work for the I2C0 core of the lager board
by Wolfram Sang.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
[wsa: rebased and fixed aliases]
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
arch/arm/boot/dts/r8a7790-lager.dts | 39 +++++++++++++++++++++++++++++++++++--
1 file changed, 37 insertions(+), 2 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 5645444cd21a..9b9748548702 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -50,7 +50,9 @@
aliases {
serial0 = &scif0;
serial1 = &scifa1;
+ i2c8 = &gpioi2c1;
i2c10 = &i2cexio0;
+ i2c11 = &i2cexio1;
};
chosen {
@@ -265,6 +267,17 @@
clock-frequency = <148500000>;
};
+ gpioi2c1: i2c-8 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "i2c-gpio";
+ status = "disabled";
+ gpios = <&gpio1 17 GPIO_ACTIVE_HIGH /* sda */
+ &gpio1 16 GPIO_ACTIVE_HIGH /* scl */
+ >;
+ i2c-gpio,delay-us = <5>;
+ };
+
/*
* IIC0/I2C0 is routed to EXIO connector A, pins 114 (SCL) + 116 (SDA) only.
* We use the I2C demuxer, so the desired IP core can be selected at runtime
@@ -283,6 +296,19 @@
#address-cells = <1>;
#size-cells = <0>;
};
+
+ /*
+ * IIC1/I2C1 is routed to EXIO connector A, pins 78 (SCL) + 80 (SDA).
+ * This is similar to the arangement described for i2cexio0 (above)
+ * with a fallback to GPIO also provided.
+ */
+ i2cexio1: i2c-11 {
+ compatible = "i2c-demux-pinctrl";
+ i2c-parent = <&iic1>, <&i2c1>, <&gpioi2c1>;
+ i2c-bus-name = "i2c-exio1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
&du {
@@ -405,6 +431,11 @@
function = "iic0";
};
+ i2c1_pins: i2c1 {
+ groups = "i2c1";
+ function = "i2c1";
+ };
+
iic1_pins: iic1 {
groups = "iic1";
function = "iic1";
@@ -606,10 +637,14 @@
pinctrl-names = "i2c-exio0";
};
+&i2c1 {
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-names = "i2c-exio1";
+};
+
&iic1 {
- status = "okay";
pinctrl-0 = <&iic1_pins>;
- pinctrl-names = "default";
+ pinctrl-names = "i2c-exio1";
};
&iic2 {
--
cgit
From 6723438b3b98ba8434655fa13fc6d5153f70ee98 Mon Sep 17 00:00:00 2001
From: Simon Horman <horms+renesas@verge.net.au>
Date: Sun, 6 Nov 2016 21:20:23 +0100
Subject: ARM: dts: koelsch: use demuxer for I2C1
Make it possible to fallback to GPIO for I2C1 on the EXIO-C connector.
This is based on reference work for the I2C0 core of the lager/r8a7790
by Wolfram Sang.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
[wsa: rebased and fixed aliases]
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
arch/arm/boot/dts/r8a7791-koelsch.dts | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index c457b43deb7d..d5c80e6bff22 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -50,6 +50,8 @@
aliases {
serial0 = &scif0;
serial1 = &scif1;
+ i2c9 = &gpioi2c1;
+ i2c12 = &i2cexio1;
};
chosen {
@@ -298,6 +300,29 @@
#clock-cells = <0>;
clock-frequency = <148500000>;
};
+
+ gpioi2c1: i2c-9 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "i2c-gpio";
+ status = "disabled";
+ gpios = <&gpio7 16 GPIO_ACTIVE_HIGH /* sda */
+ &gpio7 15 GPIO_ACTIVE_HIGH /* scl */
+ >;
+ i2c-gpio,delay-us = <5>;
+ };
+
+ /*
+ * I2C1 is routed to EXIO connector B, pins 64 (SCL) + 66 (SDA).
+ * A fallback to GPIO is provided.
+ */
+ i2cexio1: i2c-12 {
+ compatible = "i2c-demux-pinctrl";
+ i2c-parent = <&i2c1>, <&gpioi2c1>;
+ i2c-bus-name = "i2c-exio1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
&du {
@@ -333,6 +358,11 @@
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
+ i2c1_pins: i2c1 {
+ groups = "i2c1";
+ function = "i2c1";
+ };
+
i2c2_pins: i2c2 {
groups = "i2c2";
function = "i2c2";
@@ -581,6 +611,11 @@
};
};
+&i2c1 {
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-names = "i2c-exio1";
+};
+
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
--
cgit
From e60a19f03cdb5a16fdad72d0776a1ede10fd2a57 Mon Sep 17 00:00:00 2001
From: Simon Horman <horms+renesas@verge.net.au>
Date: Sun, 6 Nov 2016 21:20:30 +0100
Subject: ARM: dts: alt: use demuxer for I2C4
Make it possible to fallback to GPIO for I2C4 on the EXIO-B connector.
This is based on reference work for the I2C0 core of the lager/r8a7790
by Wolfram Sang.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
[wsa: rebased and fixed aliases]
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
arch/arm/boot/dts/r8a7794-alt.dts | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index a3e74684289b..7270d4224b1a 100644
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -18,6 +18,8 @@
aliases {
serial0 = &scif2;
+ i2c10 = &gpioi2c4;
+ i2c12 = &i2cexio4;
};
chosen {
@@ -135,6 +137,29 @@
#clock-cells = <0>;
clock-frequency = <148500000>;
};
+
+ gpioi2c4: i2c-10 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "i2c-gpio";
+ status = "disabled";
+ gpios = <&gpio4 9 GPIO_ACTIVE_HIGH /* sda */
+ &gpio4 8 GPIO_ACTIVE_HIGH /* scl */
+ >;
+ i2c-gpio,delay-us = <5>;
+ };
+
+ /*
+ * I2C4 is routed to EXIO connector B, pins 73 (SCL) + 74 (SDA).
+ * A fallback to GPIO is provided.
+ */
+ i2cexio4: i2c-14 {
+ compatible = "i2c-demux-pinctrl";
+ i2c-parent = <&i2c4>, <&gpioi2c4>;
+ i2c-bus-name = "i2c-exio4";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
&du {
@@ -194,6 +219,11 @@
function = "i2c1";
};
+ i2c4_pins: i2c4 {
+ groups = "i2c4";
+ function = "i2c4";
+ };
+
vin0_pins: vin0 {
groups = "vin0_data8", "vin0_clk";
function = "vin0";
@@ -314,6 +344,11 @@
};
};
+&i2c4 {
+ pinctrl-0 = <&i2c4_pins>;
+ pinctrl-names = "i2c-exio4";
+};
+
&vin0 {
status = "okay";
pinctrl-0 = <&vin0_pins>;
--
cgit
From dcc2fe783d5338125214335b7168623a4b81adbb Mon Sep 17 00:00:00 2001
From: Simon Horman <horms+renesas@verge.net.au>
Date: Thu, 3 Nov 2016 16:07:23 +0100
Subject: ARM: dts: lager: Enable UHS-I SDR-104
Add the sd-uhs-sdr104 property to SDHI0.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
arch/arm/boot/dts/r8a7790-lager.dts | 1 +
1 file changed, 1 insertion(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 9b9748548702..bd512c86e852 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -608,6 +608,7 @@
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
sd-uhs-sdr50;
+ sd-uhs-sdr104;
status = "okay";
};
--
cgit
From 0726729a4c6882086fe0db150a4dd0493f15dea3 Mon Sep 17 00:00:00 2001
From: Simon Horman <horms+renesas@verge.net.au>
Date: Thu, 3 Nov 2016 16:07:24 +0100
Subject: ARM: dts: koelsch: Enable UHS-I SDR-104
And the sd-uhs-sdr104 property to SDHI0.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
arch/arm/boot/dts/r8a7791-koelsch.dts | 1 +
1 file changed, 1 insertion(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index d5c80e6bff22..5405d337d744 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -529,6 +529,7 @@
cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
sd-uhs-sdr50;
+ sd-uhs-sdr104;
status = "okay";
};
--
cgit
From f9f2fc0b8d659158cafa95df4ca1d38b1c081d94 Mon Sep 17 00:00:00 2001
From: Simon Horman <horms+renesas@verge.net.au>
Date: Thu, 3 Nov 2016 16:07:25 +0100
Subject: ARM: dts: alt: Enable UHS-I SDR-104
And the sd-uhs-sdr104 property to SDHI0.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
arch/arm/boot/dts/r8a7794-alt.dts | 1 +
1 file changed, 1 insertion(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index 7270d4224b1a..569e3f0e97a5 100644
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -307,6 +307,7 @@
cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>;
sd-uhs-sdr50;
+ sd-uhs-sdr104;
status = "okay";
};
--
cgit
From 34e8d993a68ae459ad98c27afc07647e439deacc Mon Sep 17 00:00:00 2001
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Date: Mon, 31 Oct 2016 22:54:01 +0300
Subject: ARM: dts: r8a7743: initial SoC device tree
The initial R8A7743 SoC device tree including CPU0, GIC, timer, SYSC, RST,
CPG, and the required clock descriptions.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7743.dtsi | 120 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 120 insertions(+)
create mode 100644 arch/arm/boot/dts/r8a7743.dtsi
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
new file mode 100644
index 000000000000..db9cb41be79b
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -0,0 +1,120 @@
+/*
+ * Device Tree Source for the r8a7743 SoC
+ *
+ * Copyright (C) 2016 Cogent Embedded Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/r8a7743-cpg-mssr.h>
+#include <dt-bindings/power/r8a7743-sysc.h>
+
+/ {
+ compatible = "renesas,r8a7743";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ clock-frequency = <1500000000>;
+ clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
+ power-domains = <&sysc R8A7743_PD_CA15_CPU0>;
+ next-level-cache = <&L2_CA15>;
+ };
+
+ L2_CA15: cache-controller@0 {
+ compatible = "cache";
+ reg = <0>;
+ cache-unified;
+ cache-level = <2>;
+ power-domains = <&sysc R8A7743_PD_CA15_SCU>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic: interrupt-controller@f1001000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0xf1001000 0 0x1000>,
+ <0 0xf1002000 0 0x1000>,
+ <0 0xf1004000 0 0x2000>,
+ <0 0xf1006000 0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ cpg: clock-controller@e6150000 {
+ compatible = "renesas,r8a7743-cpg-mssr";
+ reg = <0 0xe6150000 0 0x1000>;
+ clocks = <&extal_clk>, <&usb_extal_clk>;
+ clock-names = "extal", "usb_extal";
+ #clock-cells = <2>;
+ #power-domain-cells = <0>;
+ };
+
+ sysc: system-controller@e6180000 {
+ compatible = "renesas,r8a7743-sysc";
+ reg = <0 0xe6180000 0 0x200>;
+ #power-domain-cells = <1>;
+ };
+
+ rst: reset-controller@e6160000 {
+ compatible = "renesas,r8a7743-rst";
+ reg = <0 0xe6160000 0 0x100>;
+ };
+ };
+
+ /* External root clock */
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ /* External USB clock - can be overridden by the board */
+ usb_extal_clk: usb_extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+
+ /* External SCIF clock */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+};
--
cgit
From 6ed5ed500a5c67eed7b76e5353f7bca3b3daae92 Mon Sep 17 00:00:00 2001
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Date: Mon, 31 Oct 2016 22:54:50 +0300
Subject: ARM: dts: r8a7743: add SYS-DMAC support
Describe SYS-DMAC0/1 in the R8A7743 device tree.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7743.dtsi | 64 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 64 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index db9cb41be79b..4807b08a3541 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -93,6 +93,70 @@
compatible = "renesas,r8a7743-rst";
reg = <0 0xe6160000 0 0x100>;
};
+
+ dmac0: dma-controller@e6700000 {
+ compatible = "renesas,dmac-r8a7743",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6700000 0 0x20000>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 219>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
+
+ dmac1: dma-controller@e6720000 {
+ compatible = "renesas,dmac-r8a7743",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6720000 0 0x20000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 218>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
};
/* External root clock */
--
cgit
From 809c01342691469456489bbe87d2d79ed9638631 Mon Sep 17 00:00:00 2001
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Date: Mon, 31 Oct 2016 22:55:39 +0300
Subject: ARM: dts: r8a7743: add [H]SCIF{A|B} support
Describe [H]SCIF{|A|B} ports in the R8A7743 device tree.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
[simon: consistently use tabs for indentation]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7743.dtsi | 261 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 261 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index 4807b08a3541..874bcf2b4da6 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -157,6 +157,267 @@
#dma-cells = <1>;
dma-channels = <15>;
};
+
+ scifa0: serial@e6c40000 {
+ compatible = "renesas,scifa-r8a7743",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c40000 0 0x40>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 204>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x21>, <&dmac0 0x22>,
+ <&dmac1 0x21>, <&dmac1 0x22>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifa1: serial@e6c50000 {
+ compatible = "renesas,scifa-r8a7743",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c50000 0 0x40>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 203>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x25>, <&dmac0 0x26>,
+ <&dmac1 0x25>, <&dmac1 0x26>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifa2: serial@e6c60000 {
+ compatible = "renesas,scifa-r8a7743",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c60000 0 0x40>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 202>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+ <&dmac1 0x27>, <&dmac1 0x28>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifa3: serial@e6c70000 {
+ compatible = "renesas,scifa-r8a7743",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c70000 0 0x40>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1106>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
+ <&dmac1 0x1b>, <&dmac1 0x1c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifa4: serial@e6c78000 {
+ compatible = "renesas,scifa-r8a7743",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c78000 0 0x40>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1107>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
+ <&dmac1 0x1f>, <&dmac1 0x20>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifa5: serial@e6c80000 {
+ compatible = "renesas,scifa-r8a7743",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c80000 0 0x40>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1108>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x23>, <&dmac0 0x24>,
+ <&dmac1 0x23>, <&dmac1 0x24>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifb0: serial@e6c20000 {
+ compatible = "renesas,scifb-r8a7743",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6c20000 0 0x100>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 206>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
+ <&dmac1 0x3d>, <&dmac1 0x3e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifb1: serial@e6c30000 {
+ compatible = "renesas,scifb-r8a7743",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6c30000 0 0x100>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 207>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
+ <&dmac1 0x19>, <&dmac1 0x1a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifb2: serial@e6ce0000 {
+ compatible = "renesas,scifb-r8a7743",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6ce0000 0 0x100>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 216>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
+ <&dmac1 0x1d>, <&dmac1 0x1e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif0: serial@e6e60000 {
+ compatible = "renesas,scif-r8a7743",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e60000 0 0x40>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 721>,
+ <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+ <&dmac1 0x29>, <&dmac1 0x2a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif1: serial@e6e68000 {
+ compatible = "renesas,scif-r8a7743",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e68000 0 0x40>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 720>,
+ <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+ <&dmac1 0x2d>, <&dmac1 0x2e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif2: serial@e6e58000 {
+ compatible = "renesas,scif-r8a7743",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e58000 0 0x40>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 719>,
+ <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+ <&dmac1 0x2b>, <&dmac1 0x2c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif3: serial@e6ea8000 {
+ compatible = "renesas,scif-r8a7743",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6ea8000 0 0x40>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 718>,
+ <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
+ <&dmac1 0x2f>, <&dmac1 0x30>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif4: serial@e6ee0000 {
+ compatible = "renesas,scif-r8a7743",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6ee0000 0 0x40>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 715>,
+ <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
+ <&dmac1 0xfb>, <&dmac1 0xfc>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif5: serial@e6ee8000 {
+ compatible = "renesas,scif-r8a7743",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6ee8000 0 0x40>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 714>,
+ <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
+ <&dmac1 0xfd>, <&dmac1 0xfe>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ hscif0: serial@e62c0000 {
+ compatible = "renesas,hscif-r8a7743",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62c0000 0 0x60>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 717>,
+ <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+ <&dmac1 0x39>, <&dmac1 0x3a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ hscif1: serial@e62c8000 {
+ compatible = "renesas,hscif-r8a7743",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62c8000 0 0x60>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 716>,
+ <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+ <&dmac1 0x4d>, <&dmac1 0x4e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ hscif2: serial@e62d0000 {
+ compatible = "renesas,hscif-r8a7743",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62d0000 0 0x60>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 713>,
+ <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
+ <&dmac1 0x3b>, <&dmac1 0x3c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
};
/* External root clock */
--
cgit
From 75f97fb45e6297e3fbaf837fc30850cf724c8f83 Mon Sep 17 00:00:00 2001
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Date: Mon, 31 Oct 2016 22:56:36 +0300
Subject: ARM: dts: r8a7743: add Ether support
Define the generic R8A7743 part of the Ether device node.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7743.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index 874bcf2b4da6..87563a5379b5 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -418,6 +418,18 @@
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
status = "disabled";
};
+
+ ether: ethernet@ee700000 {
+ compatible = "renesas,ether-r8a7743";
+ reg = <0 0xee700000 0 0x400>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 813>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ phy-mode = "rmii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
/* External root clock */
--
cgit
From ef0ca50774495c4ca4d1211252c8ee5af5136187 Mon Sep 17 00:00:00 2001
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Date: Mon, 31 Oct 2016 22:58:12 +0300
Subject: ARM: dts: r8a7743: add IRQC support
Describe the IRQC interrupt controller in the R8A7743 device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7743.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index 87563a5379b5..216cb1f37f87 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -62,6 +62,25 @@
IRQ_TYPE_LEVEL_HIGH)>;
};
+ irqc: interrupt-controller@e61c0000 {
+ compatible = "renesas,irqc-r8a7743", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 407>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
--
cgit
From 22e69c4bfce712ab945ce6cd57951e3ba15a8e70 Mon Sep 17 00:00:00 2001
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Date: Mon, 31 Oct 2016 22:59:03 +0300
Subject: ARM: dts: sk-rzg1m: initial device tree
Add the initial device tree for the R8A7743 SoC based SK-RZG1M board.
The board has one debug serial port (SCIF0); include support for it, so
that the serial console can work.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/r8a7743-sk-rzg1m.dts | 44 ++++++++++++++++++++++++++++++++++
2 files changed, 45 insertions(+)
create mode 100644 arch/arm/boot/dts/r8a7743-sk-rzg1m.dts
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index befcd2619902..f83ea57c97f9 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -677,6 +677,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
r7s72100-rskrza1.dtb \
r8a73a4-ape6evm.dtb \
r8a7740-armadillo800eva.dtb \
+ r8a7743-sk-rzg1m.dtb \
r8a7778-bockw.dtb \
r8a7779-marzen.dtb \
r8a7790-lager.dtb \
diff --git a/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts b/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts
new file mode 100644
index 000000000000..ed26961c9434
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts
@@ -0,0 +1,44 @@
+/*
+ * Device Tree Source for the SK-RZG1M board
+ *
+ * Copyright (C) 2016 Cogent Embedded, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "r8a7743.dtsi"
+
+/ {
+ model = "SK-RZG1M";
+ compatible = "renesas,sk-rzg1m", "renesas,r8a7743";
+
+ aliases {
+ serial0 = &scif0;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x40000000>;
+ };
+
+ memory@200000000 {
+ device_type = "memory";
+ reg = <2 0x00000000 0 0x40000000>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <20000000>;
+};
+
+&scif0 {
+ status = "okay";
+};
--
cgit
From d05ab65b1d0b7fdd0f25439a3bf234324a419d94 Mon Sep 17 00:00:00 2001
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Date: Mon, 31 Oct 2016 23:00:03 +0300
Subject: ARM: dts: sk-rzg1m: add Ether support
Define the SK-RZG1M board dependent part of the Ether device node.
Enable DHCP and NFS root for the kernel booting.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7743-sk-rzg1m.dts | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts b/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts
index ed26961c9434..3a22538208f2 100644
--- a/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts
+++ b/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts
@@ -20,7 +20,7 @@
};
chosen {
- bootargs = "ignore_loglevel";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = "serial0:115200n8";
};
@@ -42,3 +42,16 @@
&scif0 {
status = "okay";
};
+
+ðer {
+ phy-handle = <&phy1>;
+ renesas,ether-link-active-low;
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ interrupt-parent = <&irqc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ micrel,led-mode = <1>;
+ };
+};
--
cgit
From c95360247bdd67d39b55f7e743153efa64e4efe3 Mon Sep 17 00:00:00 2001
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Date: Sat, 5 Nov 2016 00:53:38 +0300
Subject: ARM: dts: r8a7745: initial SoC device tree
The initial R8A7745 SoC device tree including CPU0, GIC, timer, SYSC, RST,
CPG, and the required clock descriptions.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7745.dtsi | 120 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 120 insertions(+)
create mode 100644 arch/arm/boot/dts/r8a7745.dtsi
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
new file mode 100644
index 000000000000..fbf72ddd82b7
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -0,0 +1,120 @@
+/*
+ * Device Tree Source for the r8a7745 SoC
+ *
+ * Copyright (C) 2016 Cogent Embedded Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/r8a7745-cpg-mssr.h>
+#include <dt-bindings/power/r8a7745-sysc.h>
+
+/ {
+ compatible = "renesas,r8a7745";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0>;
+ clock-frequency = <1000000000>;
+ clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
+ power-domains = <&sysc R8A7745_PD_CA7_CPU0>;
+ next-level-cache = <&L2_CA7>;
+ };
+
+ L2_CA7: cache-controller@0 {
+ compatible = "cache";
+ reg = <0>;
+ cache-unified;
+ cache-level = <2>;
+ power-domains = <&sysc R8A7745_PD_CA7_SCU>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic: interrupt-controller@f1001000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0xf1001000 0 0x1000>,
+ <0 0xf1002000 0 0x1000>,
+ <0 0xf1004000 0 0x2000>,
+ <0 0xf1006000 0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ cpg: clock-controller@e6150000 {
+ compatible = "renesas,r8a7745-cpg-mssr";
+ reg = <0 0xe6150000 0 0x1000>;
+ clocks = <&extal_clk>, <&usb_extal_clk>;
+ clock-names = "extal", "usb_extal";
+ #clock-cells = <2>;
+ #power-domain-cells = <0>;
+ };
+
+ sysc: system-controller@e6180000 {
+ compatible = "renesas,r8a7745-sysc";
+ reg = <0 0xe6180000 0 0x200>;
+ #power-domain-cells = <1>;
+ };
+
+ rst: reset-controller@e6160000 {
+ compatible = "renesas,r8a7745-rst";
+ reg = <0 0xe6160000 0 0x100>;
+ };
+ };
+
+ /* External root clock */
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ /* External USB clock - can be overridden by the board */
+ usb_extal_clk: usb_extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+
+ /* External SCIF clock */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+};
--
cgit
From 06a80bad04291b6e305ef521550581d62b4656a3 Mon Sep 17 00:00:00 2001
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Date: Sat, 5 Nov 2016 00:54:51 +0300
Subject: ARM: dts: r8a7745: add SYS-DMAC support
Describe SYS-DMAC0/1 in the R8A7745 device tree.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7745.dtsi | 64 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 64 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index fbf72ddd82b7..437c5ad933d1 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -93,6 +93,70 @@
compatible = "renesas,r8a7745-rst";
reg = <0 0xe6160000 0 0x100>;
};
+
+ dmac0: dma-controller@e6700000 {
+ compatible = "renesas,dmac-r8a7745",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6700000 0 0x20000>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 219>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
+
+ dmac1: dma-controller@e6720000 {
+ compatible = "renesas,dmac-r8a7745",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6720000 0 0x20000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 218>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
};
/* External root clock */
--
cgit
From e0d2da54c4d01ba27a4f50c9da94f7a011c6056b Mon Sep 17 00:00:00 2001
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Date: Sat, 5 Nov 2016 00:55:52 +0300
Subject: ARM: dts: r8a7745: add [H]SCIF{|A|B} support
Describe [H]SCIF{|A|B} ports in the R8A7745 device tree.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
[simon: consistently use tabs for indentation]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7745.dtsi | 261 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 261 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index 437c5ad933d1..99ccdd0d3014 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -157,6 +157,267 @@
#dma-cells = <1>;
dma-channels = <15>;
};
+
+ scifa0: serial@e6c40000 {
+ compatible = "renesas,scifa-r8a7745",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c40000 0 0x40>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 204>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x21>, <&dmac0 0x22>,
+ <&dmac1 0x21>, <&dmac1 0x22>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifa1: serial@e6c50000 {
+ compatible = "renesas,scifa-r8a7745",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c50000 0 0x40>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 203>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x25>, <&dmac0 0x26>,
+ <&dmac1 0x25>, <&dmac1 0x26>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifa2: serial@e6c60000 {
+ compatible = "renesas,scifa-r8a7745",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c60000 0 0x40>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 202>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+ <&dmac1 0x27>, <&dmac1 0x28>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifa3: serial@e6c70000 {
+ compatible = "renesas,scifa-r8a7745",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c70000 0 0x40>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1106>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
+ <&dmac1 0x1b>, <&dmac1 0x1c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifa4: serial@e6c78000 {
+ compatible = "renesas,scifa-r8a7745",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c78000 0 0x40>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1107>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
+ <&dmac1 0x1f>, <&dmac1 0x20>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifa5: serial@e6c80000 {
+ compatible = "renesas,scifa-r8a7745",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c80000 0 0x40>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1108>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x23>, <&dmac0 0x24>,
+ <&dmac1 0x23>, <&dmac1 0x24>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifb0: serial@e6c20000 {
+ compatible = "renesas,scifb-r8a7745",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6c20000 0 0x100>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 206>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
+ <&dmac1 0x3d>, <&dmac1 0x3e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifb1: serial@e6c30000 {
+ compatible = "renesas,scifb-r8a7745",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6c30000 0 0x100>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 207>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
+ <&dmac1 0x19>, <&dmac1 0x1a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifb2: serial@e6ce0000 {
+ compatible = "renesas,scifb-r8a7745",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6ce0000 0 0x100>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 216>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
+ <&dmac1 0x1d>, <&dmac1 0x1e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif0: serial@e6e60000 {
+ compatible = "renesas,scif-r8a7745",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e60000 0 0x40>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 721>,
+ <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+ <&dmac1 0x29>, <&dmac1 0x2a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif1: serial@e6e68000 {
+ compatible = "renesas,scif-r8a7745",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e68000 0 0x40>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 720>,
+ <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+ <&dmac1 0x2d>, <&dmac1 0x2e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif2: serial@e6e58000 {
+ compatible = "renesas,scif-r8a7745",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e58000 0 0x40>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 719>,
+ <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+ <&dmac1 0x2b>, <&dmac1 0x2c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif3: serial@e6ea8000 {
+ compatible = "renesas,scif-r8a7745",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6ea8000 0 0x40>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 718>,
+ <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
+ <&dmac1 0x2f>, <&dmac1 0x30>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif4: serial@e6ee0000 {
+ compatible = "renesas,scif-r8a7745",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6ee0000 0 0x40>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 715>,
+ <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
+ <&dmac1 0xfb>, <&dmac1 0xfc>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif5: serial@e6ee8000 {
+ compatible = "renesas,scif-r8a7745",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6ee8000 0 0x40>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 714>,
+ <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
+ <&dmac1 0xfd>, <&dmac1 0xfe>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ hscif0: serial@e62c0000 {
+ compatible = "renesas,hscif-r8a7745",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62c0000 0 0x60>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 717>,
+ <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+ <&dmac1 0x39>, <&dmac1 0x3a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ hscif1: serial@e62c8000 {
+ compatible = "renesas,hscif-r8a7745",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62c8000 0 0x60>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 716>,
+ <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+ <&dmac1 0x4d>, <&dmac1 0x4e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ hscif2: serial@e62d0000 {
+ compatible = "renesas,hscif-r8a7745",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62d0000 0 0x60>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 713>,
+ <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
+ <&dmac1 0x3b>, <&dmac1 0x3c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
};
/* External root clock */
--
cgit
From bed98a59b62d3e121da2d8372425fd4e424b0aa6 Mon Sep 17 00:00:00 2001
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Date: Fri, 4 Nov 2016 14:57:01 -0700
Subject: ARM: dts: r8a7745: add Ether support
Define the generic R8A7745 part of the Ether device node.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7745.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index 99ccdd0d3014..6fe48157f906 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -418,6 +418,18 @@
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
status = "disabled";
};
+
+ ether: ethernet@ee700000 {
+ compatible = "renesas,ether-r8a7745";
+ reg = <0 0xee700000 0 0x400>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 813>;
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ phy-mode = "rmii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
/* External root clock */
--
cgit
From 28c43fbb3ca0a9a8f547aece94dac8d791358444 Mon Sep 17 00:00:00 2001
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Date: Sat, 5 Nov 2016 00:59:37 +0300
Subject: ARM: dts: r8a7745: add IRQC support
Describe the IRQC interrupt controller in the R8A7745 device tree.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7745.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index 6fe48157f906..0b2e2f37150f 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -62,6 +62,25 @@
IRQ_TYPE_LEVEL_HIGH)>;
};
+ irqc: interrupt-controller@e61c0000 {
+ compatible = "renesas,irqc-r8a7745", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 407>;
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
--
cgit
From e9189e66dbdcd9705697c8b283b5b142b87da9aa Mon Sep 17 00:00:00 2001
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Date: Sat, 5 Nov 2016 01:04:32 +0300
Subject: ARM: dts: sk-rzg1e: initial device tree
Add the initial device tree for the R8A7745 SoC based SK-RZG1E board.
The board has 1 debug serial port (SCIF2); include support for it,
so that the serial console can work.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/r8a7745-sk-rzg1e.dts | 39 ++++++++++++++++++++++++++++++++++
2 files changed, 40 insertions(+)
create mode 100644 arch/arm/boot/dts/r8a7745-sk-rzg1e.dts
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f83ea57c97f9..6f8cd1436ee8 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -678,6 +678,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
r8a73a4-ape6evm.dtb \
r8a7740-armadillo800eva.dtb \
r8a7743-sk-rzg1m.dtb \
+ r8a7745-sk-rzg1e.dtb \
r8a7778-bockw.dtb \
r8a7779-marzen.dtb \
r8a7790-lager.dtb \
diff --git a/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts b/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts
new file mode 100644
index 000000000000..667ec4b259d5
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts
@@ -0,0 +1,39 @@
+/*
+ * Device Tree Source for the SK-RZG1E board
+ *
+ * Copyright (C) 2016 Cogent Embedded, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "r8a7745.dtsi"
+
+/ {
+ model = "SK-RZG1E";
+ compatible = "renesas,sk-rzg1e", "renesas,r8a7745";
+
+ aliases {
+ serial0 = &scif2;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x40000000>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <20000000>;
+};
+
+&scif2 {
+ status = "okay";
+};
--
cgit
From 6b334366e63678c777367002eb87c297a10d2751 Mon Sep 17 00:00:00 2001
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Date: Sat, 5 Nov 2016 01:05:28 +0300
Subject: ARM: dts: sk-rzg1e: add Ether support
Define the SK-RZG1E board dependent part of the Ether device node.
Enable DHCP and NFS root for the kernel booting.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7745-sk-rzg1e.dts | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts b/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts
index 667ec4b259d5..97840b340197 100644
--- a/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts
+++ b/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts
@@ -20,7 +20,7 @@
};
chosen {
- bootargs = "ignore_loglevel";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = "serial0:115200n8";
};
@@ -37,3 +37,16 @@
&scif2 {
status = "okay";
};
+
+ðer {
+ phy-handle = <&phy1>;
+ renesas,ether-link-active-low;
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ interrupt-parent = <&irqc>;
+ interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+ micrel,led-mode = <1>;
+ };
+};
--
cgit
From f02703320698bf60c81c8b74aeed1e64442f29c5 Mon Sep 17 00:00:00 2001
From: Geert Uytterhoeven <geert+renesas@glider.be>
Date: Mon, 14 Nov 2016 19:37:09 +0100
Subject: ARM: dts: r8a73a4: Add device node for PRR
Add a device node for the Product Register, which provides SoC product
and revision information.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a73a4.dtsi | 5 +++++
1 file changed, 5 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index ca8672778fe0..53183ffe04c1 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -751,6 +751,11 @@
};
};
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
+
sysc: system-controller@e6180000 {
compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile";
reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>;
--
cgit
From 9ba368e2226e949e42596cc6027854656f6216a2 Mon Sep 17 00:00:00 2001
From: Geert Uytterhoeven <geert+renesas@glider.be>
Date: Mon, 14 Nov 2016 19:37:10 +0100
Subject: ARM: dts: r8a7779: Add device node for PRR
Add a device node for the Product Register, which provides SoC product
and revision information.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7779.dtsi | 5 +++++
1 file changed, 5 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index 3005308a1807..9d3bb74bd3f6 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -590,6 +590,11 @@
};
};
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0xff000044 4>;
+ };
+
sysc: system-controller@ffd85000 {
compatible = "renesas,r8a7779-sysc";
reg = <0xffd85000 0x0200>;
--
cgit
From 328f39b84d4312f3bbc390524f6c6e8be5852500 Mon Sep 17 00:00:00 2001
From: Geert Uytterhoeven <geert+renesas@glider.be>
Date: Mon, 14 Nov 2016 19:37:11 +0100
Subject: ARM: dts: r8a7790: Add device node for PRR
Add a device node for the Product Register, which provides SoC product
and revision information.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7790.dtsi | 5 +++++
1 file changed, 5 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index a946474be9cf..f554ef3c8096 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -1471,6 +1471,11 @@
};
};
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
+
sysc: system-controller@e6180000 {
compatible = "renesas,r8a7790-sysc";
reg = <0 0xe6180000 0 0x0200>;
--
cgit
From 366cd112025838fbbb1be73b7efd7f70bed33b65 Mon Sep 17 00:00:00 2001
From: Geert Uytterhoeven <geert+renesas@glider.be>
Date: Mon, 14 Nov 2016 19:37:12 +0100
Subject: ARM: dts: r8a7791: Add device node for PRR
Add a device node for the Product Register, which provides SoC product
and revision information.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7791.dtsi | 5 +++++
1 file changed, 5 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 091d7fb6ee7d..4c50de2faef1 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -1485,6 +1485,11 @@
};
};
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
+
sysc: system-controller@e6180000 {
compatible = "renesas,r8a7791-sysc";
reg = <0 0xe6180000 0 0x0200>;
--
cgit
From 7cbae74e641761ed117a5a8d903b97a9892a2426 Mon Sep 17 00:00:00 2001
From: Geert Uytterhoeven <geert+renesas@glider.be>
Date: Mon, 14 Nov 2016 19:37:13 +0100
Subject: ARM: dts: r8a7792: Add device node for PRR
Add a device node for the Product Register, which provides SoC product
and revision information.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7792.dtsi | 5 +++++
1 file changed, 5 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
index a75e0cd312c5..69789020cf39 100644
--- a/arch/arm/boot/dts/r8a7792.dtsi
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -120,6 +120,11 @@
IRQ_TYPE_LEVEL_LOW)>;
};
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
+
sysc: system-controller@e6180000 {
compatible = "renesas,r8a7792-sysc";
reg = <0 0xe6180000 0 0x0200>;
--
cgit
From c832999d3af2a9229c1c518997963def42fbaf4b Mon Sep 17 00:00:00 2001
From: Geert Uytterhoeven <geert+renesas@glider.be>
Date: Mon, 14 Nov 2016 19:37:14 +0100
Subject: ARM: dts: r8a7793: Add device node for PRR
Add a device node for the Product Register, which provides SoC product
and revision information.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7793.dtsi | 5 +++++
1 file changed, 5 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 629d3d60d1cd..a377dda17724 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -1306,6 +1306,11 @@
};
};
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
+
sysc: system-controller@e6180000 {
compatible = "renesas,r8a7793-sysc";
reg = <0 0xe6180000 0 0x0200>;
--
cgit
From 2357adb625f15e7f2b05a1464076c79876563636 Mon Sep 17 00:00:00 2001
From: Geert Uytterhoeven <geert+renesas@glider.be>
Date: Mon, 14 Nov 2016 19:37:15 +0100
Subject: ARM: dts: r8a7794: Add device node for PRR
Add a device node for the Product Register, which provides SoC product
and revision information.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7794.dtsi | 5 +++++
1 file changed, 5 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 364b4aa8d1c1..63dc7f29d216 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -1377,6 +1377,11 @@
};
};
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
+
sysc: system-controller@e6180000 {
compatible = "renesas,r8a7794-sysc";
reg = <0 0xe6180000 0 0x0200>;
--
cgit
From a91b2e690d409476d711523be8a83062b9083fb2 Mon Sep 17 00:00:00 2001
From: Ritesh Harjani <riteshh@codeaurora.org>
Date: Mon, 21 Nov 2016 12:07:14 +0530
Subject: ARM: dts: Add xo to sdhc clock node on qcom platforms
Add xo entry to sdhc clock node on all qcom platforms.
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
---
arch/arm/boot/dts/qcom-apq8084.dtsi | 16 ++++++++++------
arch/arm/boot/dts/qcom-msm8974.dtsi | 16 ++++++++++------
2 files changed, 20 insertions(+), 12 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
index 39eb7a4ed16a..80d48867107f 100644
--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -182,13 +182,13 @@
};
clocks {
- xo_board {
+ xo_board: xo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
};
- sleep_clk {
+ sleep_clk: sleep_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
@@ -416,8 +416,10 @@
reg-names = "hc_mem", "core_mem";
interrupts = <0 123 0>, <0 138 0>;
interrupt-names = "hc_irq", "pwr_irq";
- clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
- clock-names = "core", "iface";
+ clocks = <&gcc GCC_SDCC1_APPS_CLK>,
+ <&gcc GCC_SDCC1_AHB_CLK>,
+ <&xo_board>;
+ clock-names = "core", "iface", "xo";
status = "disabled";
};
@@ -427,8 +429,10 @@
reg-names = "hc_mem", "core_mem";
interrupts = <0 125 0>, <0 221 0>;
interrupt-names = "hc_irq", "pwr_irq";
- clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
- clock-names = "core", "iface";
+ clocks = <&gcc GCC_SDCC2_APPS_CLK>,
+ <&gcc GCC_SDCC2_AHB_CLK>,
+ <&xo_board>;
+ clock-names = "core", "iface", "xo";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index d2109475bdfd..49d579f28865 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -220,13 +220,13 @@
};
clocks {
- xo_board {
+ xo_board: xo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
};
- sleep_clk {
+ sleep_clk: sleep_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
@@ -558,8 +558,10 @@
reg-names = "hc_mem", "core_mem";
interrupts = <0 123 0>, <0 138 0>;
interrupt-names = "hc_irq", "pwr_irq";
- clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
- clock-names = "core", "iface";
+ clocks = <&gcc GCC_SDCC1_APPS_CLK>,
+ <&gcc GCC_SDCC1_AHB_CLK>,
+ <&xo_board>;
+ clock-names = "core", "iface", "xo";
status = "disabled";
};
@@ -569,8 +571,10 @@
reg-names = "hc_mem", "core_mem";
interrupts = <0 125 0>, <0 221 0>;
interrupt-names = "hc_irq", "pwr_irq";
- clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
- clock-names = "core", "iface";
+ clocks = <&gcc GCC_SDCC2_APPS_CLK>,
+ <&gcc GCC_SDCC2_AHB_CLK>,
+ <&xo_board>;
+ clock-names = "core", "iface", "xo";
status = "disabled";
};
--
cgit
From d289fcc888903102430dd7255f36c2d16f40ed91 Mon Sep 17 00:00:00 2001
From: Jisheng Zhang <jszhang@marvell.com>
Date: Tue, 6 Sep 2016 15:37:39 +0800
Subject: ARM: dts: berlin2q-marvell-dmp: fix regulators' name
This patch fixes the following DTC warnings with W=1:
Warning (unit_address_vs_reg): Node /regulators/regulator@0 has a unit
name, but no reg property
Warning (unit_address_vs_reg): Node /regulators/regulator@1 has a unit
name, but no reg property
Warning (unit_address_vs_reg): Node /regulators/regulator@2 has a unit
name, but no reg property
Warning (unit_address_vs_reg): Node /regulators/regulator@3 has a unit
name, but no reg property
Warning (unit_address_vs_reg): Node /regulators/regulator@4 has a unit
name, but no reg property
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
---
arch/arm/boot/dts/berlin2q-marvell-dmp.dts | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
index f485308840ab..fd954c224f0c 100644
--- a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
+++ b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
@@ -58,7 +58,7 @@
#address-cells = <1>;
#size-cells = <0>;
- reg_usb0_vbus: regulator@0 {
+ reg_usb0_vbus: regulator_usb0 {
compatible = "regulator-fixed";
regulator-name = "usb0_vbus";
regulator-min-microvolt = <5000000>;
@@ -67,7 +67,7 @@
enable-active-high;
};
- reg_usb1_vbus: regulator@1 {
+ reg_usb1_vbus: regulator_usb1 {
compatible = "regulator-fixed";
regulator-name = "usb1_vbus";
regulator-min-microvolt = <5000000>;
@@ -76,7 +76,7 @@
enable-active-high;
};
- reg_usb2_vbus: regulator@2 {
+ reg_usb2_vbus: regulator_usb2 {
compatible = "regulator-fixed";
regulator-name = "usb2_vbus";
regulator-min-microvolt = <5000000>;
@@ -85,7 +85,7 @@
enable-active-high;
};
- reg_sdio1_vmmc: regulator@3 {
+ reg_sdio1_vmmc: regulator_sdio1_vmmc {
compatible = "regulator-fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@@ -95,7 +95,7 @@
gpio = <&portb 21 GPIO_ACTIVE_HIGH>;
};
- reg_sdio1_vqmmc: regulator@4 {
+ reg_sdio1_vqmmc: regulator_sido1_vqmmc {
compatible = "regulator-gpio";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
--
cgit
From 0248994d7cce890e9bb75a8ee2d41016c990a7fd Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 20 Oct 2016 09:52:11 +0900
Subject: ARM: dts: berlin2q-marvell-dmp: fix typo in chosen node
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
---
arch/arm/boot/dts/berlin2q-marvell-dmp.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
index fd954c224f0c..57aa5f8a7c77 100644
--- a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
+++ b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
@@ -48,7 +48,7 @@
reg = <0x00000000 0x80000000>;
};
- choosen {
+ chosen {
bootargs = "earlyprintk";
stdout-path = "serial0:115200n8";
};
--
cgit
From 26ca8b52d6e18c10109cabda0f775dd9345bbfdf Mon Sep 17 00:00:00 2001
From: Uwe Kleine-König <uwe@kleine-koenig.org>
Date: Fri, 25 Nov 2016 15:26:58 +0100
Subject: ARM: dts: add support for Turris Omnia
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
This machine is an open hardware router by cz.nic driven by a
Marvell Armada 385.
Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org>
Signed-off-by: Tomas Hlavacek <tmshlvck@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/armada-385-turris-omnia.dts | 340 ++++++++++++++++++++++++++
2 files changed, 341 insertions(+)
create mode 100644 arch/arm/boot/dts/armada-385-turris-omnia.dts
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 485304914916..9a3f07e86a5a 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -921,6 +921,7 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \
armada-385-db-ap.dtb \
armada-385-linksys-caiman.dtb \
armada-385-linksys-cobra.dtb \
+ armada-385-turris-omnia.dtb \
armada-388-clearfog.dtb \
armada-388-db.dtb \
armada-388-gp.dtb \
diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/armada-385-turris-omnia.dts
new file mode 100644
index 000000000000..ab49acb2d452
--- /dev/null
+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts
@@ -0,0 +1,340 @@
+/*
+ * Device Tree file for the Turris Omnia
+ *
+ * Copyright (C) 2016 Uwe Kleine-König <uwe@kleine-koenig.org>
+ * Copyright (C) 2016 Tomas Hlavacek <tmshlvkc@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Schematic available at https://www.turris.cz/doc/_media/rtrom01-schema.pdf
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "armada-385.dtsi"
+
+/ {
+ model = "Turris Omnia";
+ compatible = "cznic,turris-omnia", "marvell,armada385", "marvell,armada380";
+
+ chosen {
+ stdout-path = &uart0;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x40000000>; /* 1024 MB */
+ };
+
+ soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+ MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
+ MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
+ MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
+
+ internal-regs {
+
+ /* USB part of the PCIe2/USB 2.0 port */
+ usb@58000 {
+ status = "okay";
+ };
+
+ sata@a8000 {
+ status = "okay";
+ };
+
+ sdhci@d8000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhci_pins>;
+ status = "okay";
+
+ bus-width = <8>;
+ no-1-8-v;
+ non-removable;
+ };
+
+ usb3@f0000 {
+ status = "okay";
+ };
+
+ usb3@f8000 {
+ status = "okay";
+ };
+ };
+
+ pcie-controller {
+ status = "okay";
+
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+
+ pcie@2,0 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+ };
+
+ pcie@3,0 {
+ /* Port 2, Lane 0 */
+ status = "okay";
+ };
+ };
+ };
+};
+
+/* Connected to 88E6176 switch, port 6 */
+ð0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ge0_rgmii_pins>;
+ status = "okay";
+ phy-mode = "rgmii-id";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
+/* Connected to 88E6176 switch, port 5 */
+ð1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ge1_rgmii_pins>;
+ status = "okay";
+ phy-mode = "rgmii-id";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
+/* WAN port */
+ð2 {
+ status = "okay";
+ phy-mode = "sgmii";
+ phy = <&phy1>;
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "okay";
+
+ i2cmux@70 {
+ compatible = "nxp,pca9547";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+ status = "okay";
+
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ /* STM32F0 command interface at address 0x2a */
+ /* leds device (in STM32F0) at address 0x2b */
+
+ eeprom@54 {
+ compatible = "at,24c64";
+ reg = <0x54>;
+
+ /* The EEPROM contains data for bootloader.
+ * Contents:
+ * struct omnia_eeprom {
+ * u32 magic; (=0x0341a034 in LE)
+ * u32 ramsize; (in GiB)
+ * char regdomain[4];
+ * u32 crc32;
+ * };
+ */
+ };
+ };
+
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ /* routed to PCIe0/mSATA connector (CN7A) */
+ };
+
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+
+ /* routed to PCIe1/USB2 connector (CN61A) */
+ };
+
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+
+ /* routed to PCIe2 connector (CN62A) */
+ };
+
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+
+ /* routed to SFP+ */
+ };
+
+ i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+
+ /* ATSHA204A at address 0x64 */
+ };
+
+ i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+
+ /* exposed on pin header */
+ };
+
+ i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+
+ pcawan: gpio@71 {
+ /*
+ * GPIO expander for SFP+ signals and
+ * and phy irq
+ */
+ compatible = "nxp,pca9538";
+ reg = <0x71>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcawan_pins>;
+
+ interrupt-parent = <&gpio1>;
+ interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+ };
+};
+
+&mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio_pins>;
+ status = "okay";
+
+ phy1: phy@1 {
+ status = "okay";
+ compatible = "ethernet-phy-id0141.0DD1", "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+
+ /* irq is connected to &pcawan pin 7 */
+ };
+
+ /* Switch MV88E7176 at address 0x10 */
+};
+
+&pinctrl {
+ pcawan_pins: pcawan-pins {
+ marvell,pins = "mpp46";
+ marvell,function = "gpio";
+ };
+
+ spi0cs0_pins: spi0cs0-pins {
+ marvell,pins = "mpp25";
+ marvell,function = "spi0";
+ };
+
+ spi0cs1_pins: spi0cs1-pins {
+ marvell,pins = "mpp26";
+ marvell,function = "spi0";
+ };
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins &spi0cs0_pins>;
+ status = "okay";
+
+ spi-nor@0 {
+ compatible = "spansion,s25fl164k", "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ reg = <0x0 0x00100000>;
+ label = "U-Boot";
+ };
+
+ partition@100000 {
+ reg = <0x00100000 0x00700000>;
+ label = "Rescue system";
+ };
+ };
+ };
+
+ /* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */
+};
+
+&uart0 {
+ /* Pin header CN10 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+&uart1 {
+ /* Pin header CN11 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ status = "okay";
+};
--
cgit
From c00f3188417f7071197f9672476d6f28eeaf8835 Mon Sep 17 00:00:00 2001
From: Niklas Cassel <niklas.cassel@axis.com>
Date: Fri, 14 Oct 2016 15:09:13 +0200
Subject: ARM: dts: artpec: add pcie support
Add PCIe support to the ARTPEC-6 SoC. This uses the existing
pcie-artpec6 driver.
So, all that is needed is device tree entries in the DTS.
Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
Signed-off-by: Jesper Nilsson <jespern@axis.com>
---
arch/arm/boot/dts/artpec6-devboard.dts | 4 ++++
arch/arm/boot/dts/artpec6.dtsi | 29 ++++++++++++++++++++++++++++-
2 files changed, 32 insertions(+), 1 deletion(-)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/artpec6-devboard.dts b/arch/arm/boot/dts/artpec6-devboard.dts
index f823ed382ac7..9dfe845694cf 100644
--- a/arch/arm/boot/dts/artpec6-devboard.dts
+++ b/arch/arm/boot/dts/artpec6-devboard.dts
@@ -46,6 +46,10 @@
status = "okay";
};
+&pcie {
+ status = "okay";
+};
+
ðernet {
status = "okay";
diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts/artpec6.dtsi
index 3489019cc0dc..767cbe8d8557 100644
--- a/arch/arm/boot/dts/artpec6.dtsi
+++ b/arch/arm/boot/dts/artpec6.dtsi
@@ -67,7 +67,7 @@
};
};
- syscon {
+ syscon: syscon@f8000000 {
compatible = "axis,artpec6-syscon", "syscon";
reg = <0xf8000000 0x48>;
};
@@ -154,6 +154,33 @@
interrupt-parent = <&intc>;
};
+ pcie: pcie@f8050000 {
+ compatible = "axis,artpec6-pcie", "snps,dw-pcie";
+ reg = <0xf8050000 0x2000
+ 0xf8040000 0x1000
+ 0xc0000000 0x2000>;
+ reg-names = "dbi", "phy", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ /* downstream I/O */
+ ranges = <0x81000000 0 0 0xc0002000 0 0x00010000
+ /* non-prefetchable memory */
+ 0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>;
+ num-lanes = <2>;
+ bus-range = <0x00 0xff>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ axis,syscon-pcie = <&syscon>;
+ status = "disabled";
+ };
+
amba@0 {
compatible = "simple-bus";
#address-cells = <0x1>;
--
cgit
From e177e7307c47f7276626b0c36e8b10e90e7321d2 Mon Sep 17 00:00:00 2001
From: Fabien Parent <fparent@baylibre.com>
Date: Thu, 24 Nov 2016 15:35:45 +0100
Subject: ARM: dts: da850-lcdk: Add ethernet0 alias to DT
In order to avoid Linux generating a random mac address on every boot,
add an ethernet0 alias that will allow u-boot to patch the dtb with
the MAC address programmed into the EEPROM.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
arch/arm/boot/dts/da850-lcdk.dts | 1 +
1 file changed, 1 insertion(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/da850-lcdk.dts b/arch/arm/boot/dts/da850-lcdk.dts
index 8411a91911fd..bd976f286bc7 100644
--- a/arch/arm/boot/dts/da850-lcdk.dts
+++ b/arch/arm/boot/dts/da850-lcdk.dts
@@ -13,6 +13,7 @@
aliases {
serial2 = &serial2;
+ ethernet0 = ð0;
};
chosen {
--
cgit
From 878e908ad95637dc6567a9b5f6876a580ae90dfa Mon Sep 17 00:00:00 2001
From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Date: Thu, 24 Nov 2016 10:31:24 +0100
Subject: ARM: dts: da850: enable memctrl and mstpri nodes per board
Currently the memory controller and master priorities drivers are
enabled in da850.dtsi. For boards for which there are no settings
defined, this makes these drivers emit error messages.
Disable the nodes in da850.dtsi and only enable them for da850-lcdk -
the only board that currently needs them.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
arch/arm/boot/dts/da850-lcdk.dts | 8 ++++++++
arch/arm/boot/dts/da850.dtsi | 2 ++
2 files changed, 10 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/da850-lcdk.dts b/arch/arm/boot/dts/da850-lcdk.dts
index bd976f286bc7..afcb4821deb1 100644
--- a/arch/arm/boot/dts/da850-lcdk.dts
+++ b/arch/arm/boot/dts/da850-lcdk.dts
@@ -228,3 +228,11 @@
};
};
};
+
+&prictrl {
+ status = "okay";
+};
+
+&memctrl {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 6205917b4f59..ffc6e1abd1b7 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -212,6 +212,7 @@
prictrl: priority-controller@14110 {
compatible = "ti,da850-mstpri";
reg = <0x14110 0x0c>;
+ status = "disabled";
};
cfgchip: chip-controller@1417c {
compatible = "ti,da830-cfgchip", "syscon", "simple-mfd";
@@ -467,5 +468,6 @@
memctrl: memory-controller@b0000000 {
compatible = "ti,da850-ddr-controller";
reg = <0xb0000000 0xe8>;
+ status = "disabled";
};
};
--
cgit
From 7937038a2b0979afeec72d86bed56f58e994913b Mon Sep 17 00:00:00 2001
From: David Lechner <david@lechnology.com>
Date: Mon, 28 Nov 2016 10:40:26 -0600
Subject: ARM: dts: da850: Add node for pullup/pulldown pinconf
This SoC has a separate pin controller for configuring pullup/pulldown
bias on groups of pins.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: David Lechner <david@lechnology.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
arch/arm/boot/dts/da850.dtsi | 5 +++++
1 file changed, 5 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index ffc6e1abd1b7..5a6f3f034423 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -434,6 +434,11 @@
ti,davinci-gpio-unbanked = <0>;
status = "disabled";
};
+ pinconf: pin-controller@22c00c {
+ compatible = "ti,da850-pupd";
+ reg = <0x22c00c 0x8>;
+ status = "disabled";
+ };
mcasp0: mcasp@100000 {
compatible = "ti,da830-mcasp-audio";
--
cgit
From e4ce904d6289f2a72affd2a0f0a44da6e5d0cce4 Mon Sep 17 00:00:00 2001
From: Axel Haslam <ahaslam@baylibre.com>
Date: Thu, 1 Dec 2016 15:10:41 +0100
Subject: ARM: dts: da850: enable high speed for mmc
The mmc controller in da850 supports high speed modes
so add cap-sd-highspeed and cap-mmc-highspeed.
Signed-off-by: Axel Haslam <ahaslam@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
arch/arm/boot/dts/da850.dtsi | 4 ++++
1 file changed, 4 insertions(+)
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 5a6f3f034423..e28283164eaa 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -316,6 +316,8 @@
mmc0: mmc@40000 {
compatible = "ti,da830-mmc";
reg = <0x40000 0x1000>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
interrupts = <16>;
dmas = <&edma0 16 0>, <&edma0 17 0>;
dma-names = "rx", "tx";
@@ -324,6 +326,8 @@
mmc1: mmc@21b000 {
compatible = "ti,da830-mmc";
reg = <0x21b000 0x1000>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
interrupts = <72>;
dmas = <&edma1 28 0>, <&edma1 29 0>;
dma-names = "rx", "tx";
--
cgit
From df2f3c48b9cd51e2612a1598342769d09d849f39 Mon Sep 17 00:00:00 2001
From: Jagan Teki <jteki@openedev.com>
Date: Fri, 23 Sep 2016 15:18:33 +0530
Subject: arm: dts: zynq: Add MicroZed board support
Added basic dts support for MicroZed board.
- UART
- SDHCI
- Ethernet
Cc: Soren Brinkmann <soren.brinkmann@xilinx.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/zynq-microzed.dts | 96 +++++++++++++++++++++++++++++++++++++
2 files changed, 97 insertions(+)
create mode 100644 arch/arm/boot/dts/zynq-microzed.dts
(limited to 'arch/arm/boot')
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index befcd2619902..a4e30984df81 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -897,6 +897,7 @@ dtb-$(CONFIG_ARCH_VT8500) += \
wm8750-apc8750.dtb \
wm8850-w70v2.dtb
dtb-$(CONFIG_ARCH_ZYNQ) += \
+ zynq-microzed.dtb \
zynq-parallella.dtb \
zynq-zc702.dtb \
zynq-zc706.dtb \
diff --git a/arch/arm/boot/dts/zynq-microzed.dts b/arch/arm/boot/dts/zynq-microzed.dts
new file mode 100644
index 000000000000..b9376a4904b4
--- /dev/null
+++ b/arch/arm/boot/dts/zynq-microzed.dts
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2011 - 2014 Xilinx
+ * Copyright (C) 2016 Jagan Teki <jteki@openedev.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+
+/ {
+ model = "Zynq MicroZED Development Board";
+ compatible = "xlnx,zynq-microzed", "xlnx,zynq-7000";
+
+ aliases {
+ ethernet0 = &gem0;
+ serial0 = &uart1;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x40000000>;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ usb_phy0: phy0 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+};
+
+&clkc {
+ ps-clk-frequency = <33333333>;
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy>;
+
+ ethernet_phy: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+&sdhci0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
+};
+
+&pinctrl0 {
+ pinctrl_usb0_default: usb0-default {
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <0>;
+ io-standard = <1>;
+ };
+
+ conf-rx {
+ pins = "MIO29", "MIO31", "MIO36";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
+ "MIO35", "MIO37", "MIO38", "MIO39";
+ bias-disable;
+ };
+ };
+};
--
cgit