From 5f41f9198f296091c6a58bc2e86af1e9f019b2a3 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Tue, 28 May 2019 09:38:14 +0100 Subject: ARM: 8864/1: Add workaround for I-Cache line size mismatch between CPU cores Some big.LITTLE systems have I-Cache line size mismatch between LITTLE and big cores. This patch adds a workaround for proper I-Cache support on such systems. Without it, some class of the userspace code (typically self-modifying) might suffer from random SIGILL failures. Similar workaround already exists for ARM64 architecture. I has been added by commit 116c81f427ff ("arm64: Work around systems with mismatched cache line sizes"). Signed-off-by: Marek Szyprowski Signed-off-by: Russell King --- arch/arm/include/asm/cacheflush.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/include/asm/cacheflush.h') diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h index ec1a5fd0d294..ec4fd2e2dd60 100644 --- a/arch/arm/include/asm/cacheflush.h +++ b/arch/arm/include/asm/cacheflush.h @@ -479,4 +479,11 @@ static inline void __sync_cache_range_r(volatile void *p, size_t size) void flush_uprobe_xol_access(struct page *page, unsigned long uaddr, void *kaddr, unsigned long len); + +#ifdef CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND +void check_cpu_icache_size(int cpuid); +#else +static inline void check_cpu_icache_size(int cpuid) { } +#endif + #endif -- cgit