From d9a790df8e984b143e71ca429316064adaecf65c Mon Sep 17 00:00:00 2001 From: Victor Kamensky Date: Thu, 7 Nov 2013 08:42:42 +0100 Subject: ARM: 7883/1: fix mov to mvn conversion in case of 64 bit phys_addr_t and BE Fix patching code to convert mov instruction into mvn instruction in case of CONFIG_ARCH_PHYS_ADDR_T_64BIT and CONFIG_ARM_PATCH_PHYS_VIRT. In BE case store into r0 proper bits so byte swapped instruction could be modified correctly. Signed-off-by: Victor Kamensky Reviewed-by: R Sricharan Acked-by: Santosh Shilimkar Signed-off-by: Russell King --- arch/arm/kernel/head.S | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'arch/arm/kernel/head.S') diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index cd788d5b6682..11d59b32fb8d 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -644,8 +644,12 @@ ARM_BE8(rev16 ip, ip) ldrcc r7, [r4], #4 @ use branch for delay slot bcc 1b bx lr +#else +#ifdef CONFIG_CPU_ENDIAN_BE8 + moveq r0, #0x00004000 @ set bit 22, mov to mvn instruction #else moveq r0, #0x400000 @ set bit 22, mov to mvn instruction +#endif b 2f 1: ldr ip, [r7, r3] #ifdef CONFIG_CPU_ENDIAN_BE8 @@ -654,7 +658,7 @@ ARM_BE8(rev16 ip, ip) tst ip, #0x000f0000 @ check the rotation field orrne ip, ip, r6, lsl #24 @ mask in offset bits 31-24 biceq ip, ip, #0x00004000 @ clear bit 22 - orreq ip, ip, r0, lsl #24 @ mask in offset bits 7-0 + orreq ip, ip, r0 @ mask in offset bits 7-0 #else bic ip, ip, #0x000000ff tst ip, #0xf00 @ check the rotation field -- cgit