From a26bce1220a4c5a7a074a779e6aad3cae63a94f7 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Fri, 7 Oct 2011 15:57:55 +0100 Subject: ARM: 7127/1: hw_breakpoint: skip v7-specific reset on v6 cores ARMv6 cores do not implement the DBGOSLAR register, so we don't need to try and clear it on boot. Furthermore, the VCR is zeroed out of reset, so we don't need to zero it explicitly when a CPU comes online. Tested-by: Marc Zyngier Signed-off-by: Will Deacon Signed-off-by: Russell King --- arch/arm/kernel/hw_breakpoint.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/kernel/hw_breakpoint.c') diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c index 5a46225f007e..814a52a9dc39 100644 --- a/arch/arm/kernel/hw_breakpoint.c +++ b/arch/arm/kernel/hw_breakpoint.c @@ -892,6 +892,10 @@ static void reset_ctrl_regs(void *unused) * later on. */ switch (debug_arch) { + case ARM_DEBUG_ARCH_V6: + case ARM_DEBUG_ARCH_V6_1: + /* ARMv6 cores just need to reset the registers. */ + goto reset_regs; case ARM_DEBUG_ARCH_V7_ECP14: /* * Ensure sticky power-down is clear (i.e. debug logic is @@ -931,6 +935,7 @@ static void reset_ctrl_regs(void *unused) asm volatile("mcr p14, 0, %0, c0, c7, 0" : : "r" (0)); isb(); +reset_regs: if (enable_monitor_mode()) return; -- cgit