From b923ff6af0d5a806a3996dac6d4393cd9792d0f4 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Mon, 23 Feb 2015 17:45:18 +0000 Subject: ARM: imx6: convert GPC to stacked domains IMX6 has been (ab)using the gic_arch_extn to provide wakeup from suspend, and it makes a lot of sense to convert this code to use stacked domains instead. This patch does just this, updating the DT files to actually reflect what the HW provides. BIG FAT WARNING: because the DTs were so far lying by not exposing the fact that the GPC block is actually the first interrupt controller in the chain, kernels with this patch applied wont have any suspend-resume facility when booted with old DTs, and old kernels with updated DTs won't even boot. Tested-by: Stefan Agner Acked-by: Stefan Agner Signed-off-by: Marc Zyngier Signed-off-by: Shawn Guo --- arch/arm/mach-imx/pm-imx6.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-imx/pm-imx6.c') diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c index 46fd695203c7..6a7c6fc780cc 100644 --- a/arch/arm/mach-imx/pm-imx6.c +++ b/arch/arm/mach-imx/pm-imx6.c @@ -310,10 +310,12 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) * Low-Power mode. * 3) Software should mask IRQ #32 right after CCM Low-Power mode * is set (set bits 0-1 of CCM_CLPCR). + * + * Note that IRQ #32 is GIC SPI #0. */ - imx_gpc_hwirq_unmask(32); + imx_gpc_hwirq_unmask(0); writel_relaxed(val, ccm_base + CLPCR); - imx_gpc_hwirq_mask(32); + imx_gpc_hwirq_mask(0); return 0; } -- cgit