From 5ae9f5dbb3376c14201f8354d857485ff3ea14af Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 11 Sep 2012 14:27:16 +0200 Subject: arm: mach-mv78xx0: use plus instead of or for address definitions Since we are going to use IOMEM() to define many base virtual addresses, we can no longer use binary or to define the individual register addresses ("binary or" arithmetic on pointers is not allowed). Instead, use the more conventional plus operator to do so. The binary or operators were actually not useful because the low-order bits of the base address were always zero, so the usage of the binary or operators was effectively identical to a plus operator. Signed-off-by: Thomas Petazzoni Acked-by: Arnd Bergmann Tested-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/mach-mv78xx0/include/mach/bridge-regs.h | 12 ++-- arch/arm/mach-mv78xx0/include/mach/mv78xx0.h | 82 ++++++++++++------------ 2 files changed, 47 insertions(+), 47 deletions(-) (limited to 'arch/arm/mach-mv78xx0') diff --git a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h index eb187e0e059b..5f03484584d4 100644 --- a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h +++ b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h @@ -11,18 +11,18 @@ #include -#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) +#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104) #define L2_WRITETHROUGH 0x00020000 -#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) +#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108) #define SOFT_RESET_OUT_EN 0x00000004 -#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) +#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c) #define SOFT_RESET 0x00000001 #define BRIDGE_INT_TIMER1_CLR (~0x0004) -#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) +#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200) #define IRQ_CAUSE_ERR_OFF 0x0000 #define IRQ_CAUSE_LOW_OFF 0x0004 #define IRQ_CAUSE_HIGH_OFF 0x0008 @@ -30,7 +30,7 @@ #define IRQ_MASK_LOW_OFF 0x0010 #define IRQ_MASK_HIGH_OFF 0x0014 -#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) -#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE | 0x0300) +#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300) +#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300) #endif diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h index e807c4c52a0b..a86e79ecfeaf 100644 --- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h +++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h @@ -65,47 +65,47 @@ /* * Register Map */ -#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x00000) -#define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE | 0x1500) -#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE | 0x1570) - -#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x10000) -#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000) -#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE | 0x0030) -#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE | 0x0034) -#define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x0100) -#define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1000) -#define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1100) -#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) -#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000) -#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) -#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100) -#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2200) -#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2200) -#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2300) -#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2300) - -#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x30000) -#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x34000) - -#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x40000) -#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x44000) -#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x48000) -#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x4c000) - -#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x50000) -#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x51000) -#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x52000) - -#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x70000) -#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x74000) - -#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x80000) -#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x84000) -#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x88000) -#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x8c000) - -#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0xa0000) +#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x00000) +#define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE + 0x1500) +#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE + 0x1570) + +#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x10000) +#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x10000) +#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE + 0x0030) +#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE + 0x0034) +#define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0100) +#define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1000) +#define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1100) +#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2000) +#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2000) +#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2100) +#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2100) +#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2200) +#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2200) +#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2300) +#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2300) + +#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x30000) +#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x34000) + +#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x40000) +#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x44000) +#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x48000) +#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x4c000) + +#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x50000) +#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x51000) +#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x52000) + +#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x70000) +#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x74000) + +#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x80000) +#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x84000) +#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x88000) +#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x8c000) + +#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0xa0000) /* * Supported devices and revisions. -- cgit From 383b99610e6084878930d4e4682dfc5e9141b038 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 11 Sep 2012 14:27:20 +0200 Subject: arm: mach-mv78xx0: use IOMEM() for base address definitions We now define all virtual base address constants using IOMEM() so that those are naturally typed as void __iomem pointers, and we do the necessary adjustements in the mach-mv78xx0 code. Note that we introduce a few temporary additional "unsigned long" casts when calling into plat-orion functions. Those are removed by followup patches converting plat-orion functions to void __iomem pointers as well. Signed-off-by: Thomas Petazzoni Acked-by: Arnd Bergmann Tested-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/mach-mv78xx0/addr-map.c | 2 +- arch/arm/mach-mv78xx0/common.c | 23 ++++++++++++++--------- arch/arm/mach-mv78xx0/include/mach/mv78xx0.h | 6 +++--- arch/arm/mach-mv78xx0/irq.c | 9 +++++---- arch/arm/mach-mv78xx0/mpp.c | 3 ++- arch/arm/mach-mv78xx0/pcie.c | 12 ++++++------ 6 files changed, 31 insertions(+), 24 deletions(-) (limited to 'arch/arm/mach-mv78xx0') diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c index a9bc84180d21..3358f079bcd1 100644 --- a/arch/arm/mach-mv78xx0/addr-map.c +++ b/arch/arm/mach-mv78xx0/addr-map.c @@ -47,7 +47,7 @@ static void __init __iomem *win_cfg_base(const struct orion_addr_map_cfg *cfg, i * so we don't need to take that into account here. */ - return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win)); + return (win < 8) ? WIN0_OFF(win) : WIN8_OFF(win); } /* diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index 3057f7d4329a..c4e3458e0674 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -130,17 +130,17 @@ static int get_tclk(void) ****************************************************************************/ static struct map_desc mv78xx0_io_desc[] __initdata = { { - .virtual = MV78XX0_CORE_REGS_VIRT_BASE, + .virtual = (unsigned long) MV78XX0_CORE_REGS_VIRT_BASE, .pfn = 0, .length = MV78XX0_CORE_REGS_SIZE, .type = MT_DEVICE, }, { - .virtual = MV78XX0_PCIE_IO_VIRT_BASE(0), + .virtual = (unsigned long) MV78XX0_PCIE_IO_VIRT_BASE(0), .pfn = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)), .length = MV78XX0_PCIE_IO_SIZE * 8, .type = MT_DEVICE, }, { - .virtual = MV78XX0_REGS_VIRT_BASE, + .virtual = (unsigned long) MV78XX0_REGS_VIRT_BASE, .pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE), .length = MV78XX0_REGS_SIZE, .type = MT_DEVICE, @@ -300,7 +300,8 @@ void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data) ****************************************************************************/ void __init mv78xx0_uart0_init(void) { - orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, + orion_uart0_init((unsigned long) UART0_VIRT_BASE, + UART0_PHYS_BASE, IRQ_MV78XX0_UART_0, tclk); } @@ -310,7 +311,8 @@ void __init mv78xx0_uart0_init(void) ****************************************************************************/ void __init mv78xx0_uart1_init(void) { - orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, + orion_uart1_init((unsigned long) UART1_VIRT_BASE, + UART1_PHYS_BASE, IRQ_MV78XX0_UART_1, tclk); } @@ -320,7 +322,8 @@ void __init mv78xx0_uart1_init(void) ****************************************************************************/ void __init mv78xx0_uart2_init(void) { - orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE, + orion_uart2_init((unsigned long) UART2_VIRT_BASE, + UART2_PHYS_BASE, IRQ_MV78XX0_UART_2, tclk); } @@ -329,7 +332,8 @@ void __init mv78xx0_uart2_init(void) ****************************************************************************/ void __init mv78xx0_uart3_init(void) { - orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE, + orion_uart3_init((unsigned long) UART3_VIRT_BASE, + UART3_PHYS_BASE, IRQ_MV78XX0_UART_3, tclk); } @@ -338,12 +342,13 @@ void __init mv78xx0_uart3_init(void) ****************************************************************************/ void __init mv78xx0_init_early(void) { - orion_time_set_base(TIMER_VIRT_BASE); + orion_time_set_base((unsigned long) TIMER_VIRT_BASE); } static void mv78xx0_timer_init(void) { - orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, + orion_time_init((unsigned long) BRIDGE_VIRT_BASE, + BRIDGE_INT_TIMER1_CLR, IRQ_MV78XX0_TIMER_1, get_tclk()); } diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h index a86e79ecfeaf..62405e8dda0e 100644 --- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h +++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h @@ -41,16 +41,16 @@ */ #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 -#define MV78XX0_CORE_REGS_VIRT_BASE 0xfe400000 +#define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000) #define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000 #define MV78XX0_CORE_REGS_SIZE SZ_16K #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20)) -#define MV78XX0_PCIE_IO_VIRT_BASE(i) (0xfe700000 + ((i) << 20)) +#define MV78XX0_PCIE_IO_VIRT_BASE(i) IOMEM(0xfe700000 + ((i) << 20)) #define MV78XX0_PCIE_IO_SIZE SZ_1M #define MV78XX0_REGS_PHYS_BASE 0xf1000000 -#define MV78XX0_REGS_VIRT_BASE 0xfef00000 +#define MV78XX0_REGS_VIRT_BASE IOMEM(0xfef00000) #define MV78XX0_REGS_SIZE SZ_1M #define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000 diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c index eff9a750bbe2..b5c40c4f524e 100644 --- a/arch/arm/mach-mv78xx0/irq.c +++ b/arch/arm/mach-mv78xx0/irq.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include "common.h" @@ -23,16 +24,16 @@ static int __initdata gpio0_irqs[4] = { void __init mv78xx0_init_irq(void) { - orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); - orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); - orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF)); + orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF); + orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF); + orion_irq_init(64, IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF); /* * Initialize gpiolib for GPIOs 0-31. (The GPIO interrupt mask * registers for core #1 are at an offset of 0x18 from those of * core #0.) */ - orion_gpio_init(NULL, 0, 32, (void __iomem *)GPIO_VIRT_BASE, + orion_gpio_init(NULL, 0, 32, GPIO_VIRT_BASE, mv78xx0_core_index() ? 0x18 : 0, IRQ_MV78XX0_GPIO_START, gpio0_irqs); } diff --git a/arch/arm/mach-mv78xx0/mpp.c b/arch/arm/mach-mv78xx0/mpp.c index df50342179e2..4da82f85d1ce 100644 --- a/arch/arm/mach-mv78xx0/mpp.c +++ b/arch/arm/mach-mv78xx0/mpp.c @@ -33,5 +33,6 @@ static unsigned int __init mv78xx0_variant(void) void __init mv78xx0_mpp_conf(unsigned int *mpp_list) { orion_mpp_conf(mpp_list, mv78xx0_variant(), - MPP_MAX, DEV_BUS_VIRT_BASE); + MPP_MAX, + (unsigned long) DEV_BUS_VIRT_BASE); } diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c index 2e56e86b6d68..e2940fbbcd68 100644 --- a/arch/arm/mach-mv78xx0/pcie.c +++ b/arch/arm/mach-mv78xx0/pcie.c @@ -36,8 +36,8 @@ static struct resource pcie_mem_space; void __init mv78xx0_pcie_id(u32 *dev, u32 *rev) { - *dev = orion_pcie_dev_id((void __iomem *)PCIE00_VIRT_BASE); - *rev = orion_pcie_rev((void __iomem *)PCIE00_VIRT_BASE); + *dev = orion_pcie_dev_id(PCIE00_VIRT_BASE); + *rev = orion_pcie_rev(PCIE00_VIRT_BASE); } static void __init mv78xx0_pcie_preinit(void) @@ -267,11 +267,11 @@ static struct hw_pci mv78xx0_pci __initdata = { .map_irq = mv78xx0_pcie_map_irq, }; -static void __init add_pcie_port(int maj, int min, unsigned long base) +static void __init add_pcie_port(int maj, int min, void __iomem *base) { printk(KERN_INFO "MV78xx0 PCIe port %d.%d: ", maj, min); - if (orion_pcie_link_up((void __iomem *)base)) { + if (orion_pcie_link_up(base)) { struct pcie_port *pp = &pcie_port[num_pcie_ports++]; printk("link up\n"); @@ -279,7 +279,7 @@ static void __init add_pcie_port(int maj, int min, unsigned long base) pp->maj = maj; pp->min = min; pp->root_bus_nr = -1; - pp->base = (void __iomem *)base; + pp->base = base; spin_lock_init(&pp->conf_lock); memset(pp->res, 0, sizeof(pp->res)); } else { @@ -293,7 +293,7 @@ void __init mv78xx0_pcie_init(int init_port0, int init_port1) if (init_port0) { add_pcie_port(0, 0, PCIE00_VIRT_BASE); - if (!orion_pcie_x4_mode((void __iomem *)PCIE00_VIRT_BASE)) { + if (!orion_pcie_x4_mode(PCIE00_VIRT_BASE)) { add_pcie_port(0, 1, PCIE01_VIRT_BASE); add_pcie_port(0, 2, PCIE02_VIRT_BASE); add_pcie_port(0, 3, PCIE03_VIRT_BASE); -- cgit From d19beac1d9358bb4a2a303f4327bf2d40ba88464 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 11 Sep 2012 14:27:23 +0200 Subject: arm: plat-orion: use void __iomem pointers for UART registration functions The registration functions for UARTs now take void __iomem pointers, so we remove the temporary "unsigned long" casts from the mach-*/common.c files. Signed-off-by: Thomas Petazzoni Acked-by: Arnd Bergmann Tested-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/mach-mv78xx0/common.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) (limited to 'arch/arm/mach-mv78xx0') diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index c4e3458e0674..fcda4a4f830d 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -300,8 +300,7 @@ void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data) ****************************************************************************/ void __init mv78xx0_uart0_init(void) { - orion_uart0_init((unsigned long) UART0_VIRT_BASE, - UART0_PHYS_BASE, + orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, IRQ_MV78XX0_UART_0, tclk); } @@ -311,8 +310,7 @@ void __init mv78xx0_uart0_init(void) ****************************************************************************/ void __init mv78xx0_uart1_init(void) { - orion_uart1_init((unsigned long) UART1_VIRT_BASE, - UART1_PHYS_BASE, + orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, IRQ_MV78XX0_UART_1, tclk); } @@ -322,8 +320,7 @@ void __init mv78xx0_uart1_init(void) ****************************************************************************/ void __init mv78xx0_uart2_init(void) { - orion_uart2_init((unsigned long) UART2_VIRT_BASE, - UART2_PHYS_BASE, + orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE, IRQ_MV78XX0_UART_2, tclk); } @@ -332,8 +329,7 @@ void __init mv78xx0_uart2_init(void) ****************************************************************************/ void __init mv78xx0_uart3_init(void) { - orion_uart3_init((unsigned long) UART3_VIRT_BASE, - UART3_PHYS_BASE, + orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE, IRQ_MV78XX0_UART_3, tclk); } -- cgit From 5a2f55019391218d8c08c6f9d32591d91200de77 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 11 Sep 2012 14:27:24 +0200 Subject: arm: plat-orion: use void __iomem pointers for MPP functions The registration function for MPP now takes void __iomem pointers, so we remove the temporary "unsigned long" casts from the mach-*/mpp.c files. Signed-off-by: Thomas Petazzoni Acked-by: Arnd Bergmann Tested-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/mach-mv78xx0/mpp.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/arm/mach-mv78xx0') diff --git a/arch/arm/mach-mv78xx0/mpp.c b/arch/arm/mach-mv78xx0/mpp.c index 4da82f85d1ce..df50342179e2 100644 --- a/arch/arm/mach-mv78xx0/mpp.c +++ b/arch/arm/mach-mv78xx0/mpp.c @@ -33,6 +33,5 @@ static unsigned int __init mv78xx0_variant(void) void __init mv78xx0_mpp_conf(unsigned int *mpp_list) { orion_mpp_conf(mpp_list, mv78xx0_variant(), - MPP_MAX, - (unsigned long) DEV_BUS_VIRT_BASE); + MPP_MAX, DEV_BUS_VIRT_BASE); } -- cgit From e96a0309f8545d539c1bf4acd5b58727a8f39818 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 11 Sep 2012 14:27:25 +0200 Subject: arm: plat-orion: use void __iomem pointers for time functions The functions for time management now take void __iomem pointers, so we remove the temporary "unsigned long" casts from the mach-*/common.c files. Signed-off-by: Thomas Petazzoni Acked-by: Arnd Bergmann Tested-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/mach-mv78xx0/common.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'arch/arm/mach-mv78xx0') diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index fcda4a4f830d..f123517a4bb8 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -338,13 +338,12 @@ void __init mv78xx0_uart3_init(void) ****************************************************************************/ void __init mv78xx0_init_early(void) { - orion_time_set_base((unsigned long) TIMER_VIRT_BASE); + orion_time_set_base(TIMER_VIRT_BASE); } static void mv78xx0_timer_init(void) { - orion_time_init((unsigned long) BRIDGE_VIRT_BASE, - BRIDGE_INT_TIMER1_CLR, + orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, IRQ_MV78XX0_TIMER_1, get_tclk()); } -- cgit From 9b7b7d8b024d3e44412abbbb0206ab8f60c459ad Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 11 Sep 2012 14:27:26 +0200 Subject: arm: plat-orion: use void __iomem pointers for addr-map functions The functions for address mapping management now take void __iomem pointers, so we remove the temporary "unsigned long" casts from the mach-*/common.c files. Signed-off-by: Thomas Petazzoni Acked-by: Arnd Bergmann Tested-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/mach-mv78xx0/addr-map.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-mv78xx0') diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c index 3358f079bcd1..a51fc247e73b 100644 --- a/arch/arm/mach-mv78xx0/addr-map.c +++ b/arch/arm/mach-mv78xx0/addr-map.c @@ -71,10 +71,10 @@ void __init mv78xx0_setup_cpu_mbus(void) */ if (mv78xx0_core_index() == 0) orion_setup_cpu_mbus_target(&addr_map_cfg, - DDR_WINDOW_CPU0_BASE); + (void __iomem *) DDR_WINDOW_CPU0_BASE); else orion_setup_cpu_mbus_target(&addr_map_cfg, - DDR_WINDOW_CPU1_BASE); + (void __iomem *) DDR_WINDOW_CPU1_BASE); } void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size, -- cgit