From ed1ebc4948fdfe4c68865e5543b4a68e5a55973b Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Fri, 27 Apr 2012 15:59:32 +0530 Subject: ARM: OMAP2: clock: Convert to common clk Convert all OMAP2 specific platform files to use COMMON clk and keep all the changes under the CONFIG_COMMON_CLK macro check so it does not break any existing code. At a later point switch to COMMON clk and get rid of all old/legacy code. Signed-off-by: Rajendra Nayak Signed-off-by: Mike Turquette [paul@pwsan.com: updated to apply] Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clkt2xxx_dpllcore.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/arm/mach-omap2/clkt2xxx_dpllcore.c') diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c index e687163a68fe..9d8388b7ee97 100644 --- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c +++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c @@ -41,7 +41,11 @@ * (currently defined as "dpll_ck" in the OMAP2xxx clock tree). Set * during dpll_ck init and used later by omap2xxx_clk_get_core_rate(). */ +#ifdef CONFIG_COMMON_CLK +static struct clk_hw_omap *dpll_core_ck; +#else static struct clk *dpll_core_ck; +#endif /** * omap2xxx_clk_get_core_rate - return the CORE_CLK rate @@ -105,13 +109,25 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate) } +#ifdef CONFIG_COMMON_CLK +unsigned long omap2_dpllcore_recalc(struct clk_hw *hw, + unsigned long parent_rate) +#else unsigned long omap2_dpllcore_recalc(struct clk *clk) +#endif { return omap2xxx_clk_get_core_rate(); } +#ifdef CONFIG_COMMON_CLK +int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); +#else int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) { +#endif u32 cur_rate, low, mult, div, valid_rate, done_rate; u32 bypass = 0; struct prcm_config tmpset; @@ -189,8 +205,16 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) * statically defined, this code may need to change to increment some * kind of use count on dpll_ck. */ +#ifdef CONFIG_COMMON_CLK +void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw) +#else void omap2xxx_clkt_dpllcore_init(struct clk *clk) +#endif { WARN(dpll_core_ck, "dpll_core_ck already set - should never happen"); +#ifdef CONFIG_COMMON_CLK + dpll_core_ck = to_clk_hw_omap(hw); +#else dpll_core_ck = clk; +#endif } -- cgit From d037e100d138fb522ed0ea3e3a915bd8e0e36f63 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Fri, 27 Apr 2012 16:55:59 +0530 Subject: ARM: OMAP2: clock: Cleanup !CONFIG_COMMON_CLK parts Clean all #ifdef's added to OMAP2 clock code to make it COMMON clk ready, not that CONFIG_COMMON_CLK is enabled. Signed-off-by: Rajendra Nayak [paul@pwsan.com: also drop CONFIG_COMMON_CLK tests around APLL recalc_rate functions] Signed-off-by: Mike Turquette [paul@pwsan.com: remove some ifdefs in mach-omap2/io.c] Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clkt2xxx_dpllcore.c | 21 --------------------- 1 file changed, 21 deletions(-) (limited to 'arch/arm/mach-omap2/clkt2xxx_dpllcore.c') diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c index 9d8388b7ee97..a0ae3c09f97a 100644 --- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c +++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c @@ -41,11 +41,7 @@ * (currently defined as "dpll_ck" in the OMAP2xxx clock tree). Set * during dpll_ck init and used later by omap2xxx_clk_get_core_rate(). */ -#ifdef CONFIG_COMMON_CLK static struct clk_hw_omap *dpll_core_ck; -#else -static struct clk *dpll_core_ck; -#endif /** * omap2xxx_clk_get_core_rate - return the CORE_CLK rate @@ -109,25 +105,16 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate) } -#ifdef CONFIG_COMMON_CLK unsigned long omap2_dpllcore_recalc(struct clk_hw *hw, unsigned long parent_rate) -#else -unsigned long omap2_dpllcore_recalc(struct clk *clk) -#endif { return omap2xxx_clk_get_core_rate(); } -#ifdef CONFIG_COMMON_CLK int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_hw_omap *clk = to_clk_hw_omap(hw); -#else -int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) -{ -#endif u32 cur_rate, low, mult, div, valid_rate, done_rate; u32 bypass = 0; struct prcm_config tmpset; @@ -205,16 +192,8 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) * statically defined, this code may need to change to increment some * kind of use count on dpll_ck. */ -#ifdef CONFIG_COMMON_CLK void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw) -#else -void omap2xxx_clkt_dpllcore_init(struct clk *clk) -#endif { WARN(dpll_core_ck, "dpll_core_ck already set - should never happen"); -#ifdef CONFIG_COMMON_CLK dpll_core_ck = to_clk_hw_omap(hw); -#else - dpll_core_ck = clk; -#endif } -- cgit