From 58cda884ecc87dcce18d463b0c8bd928dae63ad8 Mon Sep 17 00:00:00 2001 From: Jean Pihet Date: Fri, 24 Jul 2009 19:43:25 -0600 Subject: OMAP3 SDRC: add support for 2 SDRAM chip selects Some OMAP3 boards (Beagle Cx, Overo, RX51, Pandora) have 2 SDRAM parts connected to the SDRC. This patch adds the following: - add a new argument of type omap_sdrc_params struct* to omap2_init_common_hw and omap2_sdrc_init for the 2nd CS params - adapted the OMAP boards files to the new prototype of omap2_init_common_hw - add the SDRC 2nd CS registers offsets defines - adapt the sram sleep code to configure the SDRC for the 2nd CS Note: If the 2nd param to omap2_init_common_hw is NULL, then the parameters are not programmed into the SDRC CS1 registers Tested on 3430 SDP and Beagleboard rev C2 and B5, with suspend/resume and frequency changes (cpufreq). Signed-off-by: Jean Pihet Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/sdrc.c | 63 ++++++++++++++++++++++++++++++---------------- 1 file changed, 41 insertions(+), 22 deletions(-) (limited to 'arch/arm/mach-omap2/sdrc.c') diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c index 2045441e8385..2e9e38db30e9 100644 --- a/arch/arm/mach-omap2/sdrc.c +++ b/arch/arm/mach-omap2/sdrc.c @@ -32,7 +32,7 @@ #include #include "sdrc.h" -static struct omap_sdrc_params *sdrc_init_params; +static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1; void __iomem *omap2_sdrc_base; void __iomem *omap2_sms_base; @@ -45,33 +45,49 @@ void __iomem *omap2_sms_base; /** * omap2_sdrc_get_params - return SDRC register values for a given clock rate * @r: SDRC clock rate (in Hz) + * @sdrc_cs0: chip select 0 ram timings ** + * @sdrc_cs1: chip select 1 ram timings ** * * Return pre-calculated values for the SDRC_ACTIM_CTRLA, - * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL, and SDRC_MR registers, for a given - * SDRC clock rate 'r'. These parameters control various timing - * delays in the SDRAM controller that are expressed in terms of the - * number of SDRC clock cycles to wait; hence the clock rate - * dependency. Note that sdrc_init_params must be sorted rate - * descending. Also assumes that both chip-selects use the same - * timing parameters. Returns a struct omap_sdrc_params * upon - * success, or NULL upon failure. + * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in sdrc_cs[01] + * structs,for a given SDRC clock rate 'r'. + * These parameters control various timing delays in the SDRAM controller + * that are expressed in terms of the number of SDRC clock cycles to + * wait; hence the clock rate dependency. + * + * Supports 2 different timing parameters for both chip selects. + * + * Note 1: the sdrc_init_params_cs[01] must be sorted rate descending. + * Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same size + * as sdrc_init_params_cs_0. + * + * Fills in the struct omap_sdrc_params * for each chip select. + * Returns 0 upon success or -1 upon failure. */ -struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r) +int omap2_sdrc_get_params(unsigned long r, + struct omap_sdrc_params **sdrc_cs0, + struct omap_sdrc_params **sdrc_cs1) { - struct omap_sdrc_params *sp; + struct omap_sdrc_params *sp0, *sp1; - if (!sdrc_init_params) - return NULL; + if (!sdrc_init_params_cs0) + return -1; - sp = sdrc_init_params; + sp0 = sdrc_init_params_cs0; + sp1 = sdrc_init_params_cs1; - while (sp->rate && sp->rate != r) - sp++; + while (sp0->rate && sp0->rate != r) { + sp0++; + if (sdrc_init_params_cs1) + sp1++; + } - if (!sp->rate) - return NULL; + if (!sp0->rate) + return -1; - return sp; + *sdrc_cs0 = sp0; + *sdrc_cs1 = sp1; + return 0; } @@ -83,13 +99,15 @@ void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals) /** * omap2_sdrc_init - initialize SMS, SDRC devices on boot - * @sp: pointer to a null-terminated list of struct omap_sdrc_params + * @sdrc_cs[01]: pointers to a null-terminated list of struct omap_sdrc_params + * Support for 2 chip selects timings * * Turn on smart idle modes for SDRAM scheduler and controller. * Program a known-good configuration for the SDRC to deal with buggy * bootloaders. */ -void __init omap2_sdrc_init(struct omap_sdrc_params *sp) +void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0, + struct omap_sdrc_params *sdrc_cs1) { u32 l; @@ -103,7 +121,8 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sp) l |= (0x2 << 3); sdrc_write_reg(l, SDRC_SYSCONFIG); - sdrc_init_params = sp; + sdrc_init_params_cs0 = sdrc_cs0; + sdrc_init_params_cs1 = sdrc_cs1; /* XXX Enable SRFRONIDLEREQ here also? */ l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) | -- cgit