From b35cecf978e33bf8f4be0f36ffe00fe10f381c4a Mon Sep 17 00:00:00 2001 From: Thara Gopinath Date: Wed, 18 Aug 2010 12:23:12 +0530 Subject: OMAP4: Smartreflex framework extensions This patch extends the smartreflex framework to support OMAP4. The changes are minor like compiling smartreflex Kconfig option for OMAP4 also, and a couple of OMAP4 checks in the smartreflex framework. The change in sr_device.c where new logic has to be introduced for reading the efuse registers is due to the fact that in OMAP4 the efuse registers are 24 bit aligned. A __raw_readl will fail for non-32 bit aligned address and hence the 8-bit read and shift. Signed-off-by: Thara Gopinath Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/sr_device.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-omap2/sr_device.c') diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c index 9a3538fb633a..786d685c09a9 100644 --- a/arch/arm/mach-omap2/sr_device.c +++ b/arch/arm/mach-omap2/sr_device.c @@ -20,6 +20,7 @@ #include #include +#include #include #include @@ -51,7 +52,21 @@ static void __init sr_set_nvalues(struct omap_volt_data *volt_data, GFP_KERNEL); for (i = 0; i < count; i++) { - u32 v = omap_ctrl_readl(volt_data[i].sr_efuse_offs); + u32 v; + /* + * In OMAP4 the efuse registers are 24 bit aligned. + * A __raw_readl will fail for non-32 bit aligned address + * and hence the 8-bit read and shift. + */ + if (cpu_is_omap44xx()) { + u16 offset = volt_data[i].sr_efuse_offs; + + v = omap_ctrl_readb(offset) | + omap_ctrl_readb(offset + 1) << 8 | + omap_ctrl_readb(offset + 2) << 16; + } else { + v = omap_ctrl_readl(volt_data[i].sr_efuse_offs); + } nvalue_table[i].efuse_offs = volt_data[i].sr_efuse_offs; nvalue_table[i].nvalue = v; -- cgit