From 71b9114d2c13a648fbe6523dd859e611c316ad90 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Mon, 2 Sep 2019 17:47:55 +0200 Subject: ARM: s3c: move into a common directory s3c24xx and s3c64xx have a lot in common, but are split across three separate directories, which makes the interaction of the header files more complicated than necessary. Move all three directories into a new mach-s3c, with a minimal set of changes to each file. Signed-off-by: Arnd Bergmann [krzk: Rebase, add s3c24xx and s3c64xx suffix to several files, add SPDX headers to new files, remove plat-samsung from MAINTAINERS] Co-developed-by: Krzysztof Kozlowski Signed-off-by: Krzysztof Kozlowski https://lore.kernel.org/r/20200806182059.2431-39-krzk@kernel.org --- arch/arm/mach-s3c24xx/Kconfig | 583 --------- arch/arm/mach-s3c24xx/Makefile | 102 -- arch/arm/mach-s3c24xx/Makefile.boot | 9 - arch/arm/mach-s3c24xx/anubis.h | 50 - arch/arm/mach-s3c24xx/bast-ide.c | 82 -- arch/arm/mach-s3c24xx/bast-irq.c | 137 -- arch/arm/mach-s3c24xx/bast.h | 194 --- arch/arm/mach-s3c24xx/common-smdk.c | 228 ---- arch/arm/mach-s3c24xx/common-smdk.h | 11 - arch/arm/mach-s3c24xx/common.c | 680 ---------- arch/arm/mach-s3c24xx/common.h | 124 -- arch/arm/mach-s3c24xx/cpufreq-utils.c | 94 -- arch/arm/mach-s3c24xx/fb-core.h | 24 - arch/arm/mach-s3c24xx/gta02.h | 20 - arch/arm/mach-s3c24xx/h1940-bluetooth.c | 140 -- arch/arm/mach-s3c24xx/h1940.h | 52 - arch/arm/mach-s3c24xx/include/mach/dma.h | 51 - arch/arm/mach-s3c24xx/include/mach/gpio-samsung.h | 103 -- arch/arm/mach-s3c24xx/include/mach/hardware.h | 14 - arch/arm/mach-s3c24xx/include/mach/io.h | 50 - arch/arm/mach-s3c24xx/include/mach/irqs.h | 213 ---- arch/arm/mach-s3c24xx/include/mach/map.h | 159 --- arch/arm/mach-s3c24xx/include/mach/pm-core.h | 96 -- arch/arm/mach-s3c24xx/include/mach/regs-clock.h | 146 --- arch/arm/mach-s3c24xx/include/mach/regs-gpio.h | 608 --------- arch/arm/mach-s3c24xx/include/mach/regs-irq.h | 51 - .../mach-s3c24xx/include/mach/regs-s3c2443-clock.h | 238 ---- arch/arm/mach-s3c24xx/include/mach/rtc-core.h | 23 - arch/arm/mach-s3c24xx/include/mach/s3c2412.h | 25 - arch/arm/mach-s3c24xx/iotiming-s3c2410.c | 472 ------- arch/arm/mach-s3c24xx/iotiming-s3c2412.c | 278 ---- arch/arm/mach-s3c24xx/irq-pm.c | 115 -- arch/arm/mach-s3c24xx/irq-s3c24xx-fiq-exports.c | 9 - arch/arm/mach-s3c24xx/irq-s3c24xx-fiq.S | 115 -- arch/arm/mach-s3c24xx/irq-s3c24xx.c | 1337 -------------------- arch/arm/mach-s3c24xx/mach-amlm5900.c | 246 ---- arch/arm/mach-s3c24xx/mach-anubis.c | 426 ------- arch/arm/mach-s3c24xx/mach-at2440evb.c | 232 ---- arch/arm/mach-s3c24xx/mach-bast.c | 587 --------- arch/arm/mach-s3c24xx/mach-gta02.c | 580 --------- arch/arm/mach-s3c24xx/mach-h1940.c | 793 ------------ arch/arm/mach-s3c24xx/mach-jive.c | 684 ---------- arch/arm/mach-s3c24xx/mach-mini2440.c | 792 ------------ arch/arm/mach-s3c24xx/mach-n30.c | 674 ---------- arch/arm/mach-s3c24xx/mach-nexcoder.c | 161 --- arch/arm/mach-s3c24xx/mach-osiris-dvs.c | 178 --- arch/arm/mach-s3c24xx/mach-osiris.c | 409 ------ arch/arm/mach-s3c24xx/mach-otom.c | 124 -- arch/arm/mach-s3c24xx/mach-qt2410.c | 374 ------ arch/arm/mach-s3c24xx/mach-rx1950.c | 867 ------------- arch/arm/mach-s3c24xx/mach-rx3715.c | 218 ---- arch/arm/mach-s3c24xx/mach-s3c2416-dt.c | 48 - arch/arm/mach-s3c24xx/mach-smdk2410.c | 111 -- arch/arm/mach-s3c24xx/mach-smdk2413.c | 160 --- arch/arm/mach-s3c24xx/mach-smdk2416.c | 257 ---- arch/arm/mach-s3c24xx/mach-smdk2440.c | 189 --- arch/arm/mach-s3c24xx/mach-smdk2443.c | 136 -- arch/arm/mach-s3c24xx/mach-tct_hammer.c | 156 --- arch/arm/mach-s3c24xx/mach-vr1000.c | 368 ------ arch/arm/mach-s3c24xx/mach-vstms.c | 165 --- arch/arm/mach-s3c24xx/nand-core.h | 24 - arch/arm/mach-s3c24xx/osiris.h | 50 - arch/arm/mach-s3c24xx/otom.h | 25 - arch/arm/mach-s3c24xx/pll-s3c2410.c | 83 -- arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c | 95 -- arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c | 122 -- arch/arm/mach-s3c24xx/pm-h1940.S | 19 - arch/arm/mach-s3c24xx/pm-s3c2410.c | 170 --- arch/arm/mach-s3c24xx/pm-s3c2412.c | 126 -- arch/arm/mach-s3c24xx/pm-s3c2416.c | 81 -- arch/arm/mach-s3c24xx/pm.c | 121 -- arch/arm/mach-s3c24xx/regs-dsc.h | 22 - arch/arm/mach-s3c24xx/regs-mem.h | 53 - arch/arm/mach-s3c24xx/s3c2410.c | 130 -- arch/arm/mach-s3c24xx/s3c2412-power.h | 34 - arch/arm/mach-s3c24xx/s3c2412.c | 175 --- arch/arm/mach-s3c24xx/s3c2416.c | 132 -- arch/arm/mach-s3c24xx/s3c2440.c | 71 -- arch/arm/mach-s3c24xx/s3c2442.c | 62 - arch/arm/mach-s3c24xx/s3c2443.c | 112 -- arch/arm/mach-s3c24xx/s3c244x.c | 128 -- arch/arm/mach-s3c24xx/setup-i2c.c | 22 - arch/arm/mach-s3c24xx/setup-sdhci-gpio.c | 31 - arch/arm/mach-s3c24xx/setup-spi.c | 27 - arch/arm/mach-s3c24xx/setup-ts.c | 29 - arch/arm/mach-s3c24xx/simtec-audio.c | 76 -- arch/arm/mach-s3c24xx/simtec-nor.c | 74 -- arch/arm/mach-s3c24xx/simtec-pm.c | 60 - arch/arm/mach-s3c24xx/simtec-usb.c | 125 -- arch/arm/mach-s3c24xx/simtec.h | 17 - arch/arm/mach-s3c24xx/sleep-s3c2410.S | 54 - arch/arm/mach-s3c24xx/sleep-s3c2412.S | 53 - arch/arm/mach-s3c24xx/sleep.S | 69 - arch/arm/mach-s3c24xx/spi-core.h | 27 - arch/arm/mach-s3c24xx/vr1000.h | 113 -- 95 files changed, 18180 deletions(-) delete mode 100644 arch/arm/mach-s3c24xx/Kconfig delete mode 100644 arch/arm/mach-s3c24xx/Makefile delete mode 100644 arch/arm/mach-s3c24xx/Makefile.boot delete mode 100644 arch/arm/mach-s3c24xx/anubis.h delete mode 100644 arch/arm/mach-s3c24xx/bast-ide.c delete mode 100644 arch/arm/mach-s3c24xx/bast-irq.c delete mode 100644 arch/arm/mach-s3c24xx/bast.h delete mode 100644 arch/arm/mach-s3c24xx/common-smdk.c delete mode 100644 arch/arm/mach-s3c24xx/common-smdk.h delete mode 100644 arch/arm/mach-s3c24xx/common.c delete mode 100644 arch/arm/mach-s3c24xx/common.h delete mode 100644 arch/arm/mach-s3c24xx/cpufreq-utils.c delete mode 100644 arch/arm/mach-s3c24xx/fb-core.h delete mode 100644 arch/arm/mach-s3c24xx/gta02.h delete mode 100644 arch/arm/mach-s3c24xx/h1940-bluetooth.c delete mode 100644 arch/arm/mach-s3c24xx/h1940.h delete mode 100644 arch/arm/mach-s3c24xx/include/mach/dma.h delete mode 100644 arch/arm/mach-s3c24xx/include/mach/gpio-samsung.h delete mode 100644 arch/arm/mach-s3c24xx/include/mach/hardware.h delete mode 100644 arch/arm/mach-s3c24xx/include/mach/io.h delete mode 100644 arch/arm/mach-s3c24xx/include/mach/irqs.h delete mode 100644 arch/arm/mach-s3c24xx/include/mach/map.h delete mode 100644 arch/arm/mach-s3c24xx/include/mach/pm-core.h delete mode 100644 arch/arm/mach-s3c24xx/include/mach/regs-clock.h delete mode 100644 arch/arm/mach-s3c24xx/include/mach/regs-gpio.h delete mode 100644 arch/arm/mach-s3c24xx/include/mach/regs-irq.h delete mode 100644 arch/arm/mach-s3c24xx/include/mach/regs-s3c2443-clock.h delete mode 100644 arch/arm/mach-s3c24xx/include/mach/rtc-core.h delete mode 100644 arch/arm/mach-s3c24xx/include/mach/s3c2412.h delete mode 100644 arch/arm/mach-s3c24xx/iotiming-s3c2410.c delete mode 100644 arch/arm/mach-s3c24xx/iotiming-s3c2412.c delete mode 100644 arch/arm/mach-s3c24xx/irq-pm.c delete mode 100644 arch/arm/mach-s3c24xx/irq-s3c24xx-fiq-exports.c delete mode 100644 arch/arm/mach-s3c24xx/irq-s3c24xx-fiq.S delete mode 100644 arch/arm/mach-s3c24xx/irq-s3c24xx.c delete mode 100644 arch/arm/mach-s3c24xx/mach-amlm5900.c delete mode 100644 arch/arm/mach-s3c24xx/mach-anubis.c delete mode 100644 arch/arm/mach-s3c24xx/mach-at2440evb.c delete mode 100644 arch/arm/mach-s3c24xx/mach-bast.c delete mode 100644 arch/arm/mach-s3c24xx/mach-gta02.c delete mode 100644 arch/arm/mach-s3c24xx/mach-h1940.c delete mode 100644 arch/arm/mach-s3c24xx/mach-jive.c delete mode 100644 arch/arm/mach-s3c24xx/mach-mini2440.c delete mode 100644 arch/arm/mach-s3c24xx/mach-n30.c delete mode 100644 arch/arm/mach-s3c24xx/mach-nexcoder.c delete mode 100644 arch/arm/mach-s3c24xx/mach-osiris-dvs.c delete mode 100644 arch/arm/mach-s3c24xx/mach-osiris.c delete mode 100644 arch/arm/mach-s3c24xx/mach-otom.c delete mode 100644 arch/arm/mach-s3c24xx/mach-qt2410.c delete mode 100644 arch/arm/mach-s3c24xx/mach-rx1950.c delete mode 100644 arch/arm/mach-s3c24xx/mach-rx3715.c delete mode 100644 arch/arm/mach-s3c24xx/mach-s3c2416-dt.c delete mode 100644 arch/arm/mach-s3c24xx/mach-smdk2410.c delete mode 100644 arch/arm/mach-s3c24xx/mach-smdk2413.c delete mode 100644 arch/arm/mach-s3c24xx/mach-smdk2416.c delete mode 100644 arch/arm/mach-s3c24xx/mach-smdk2440.c delete mode 100644 arch/arm/mach-s3c24xx/mach-smdk2443.c delete mode 100644 arch/arm/mach-s3c24xx/mach-tct_hammer.c delete mode 100644 arch/arm/mach-s3c24xx/mach-vr1000.c delete mode 100644 arch/arm/mach-s3c24xx/mach-vstms.c delete mode 100644 arch/arm/mach-s3c24xx/nand-core.h delete mode 100644 arch/arm/mach-s3c24xx/osiris.h delete mode 100644 arch/arm/mach-s3c24xx/otom.h delete mode 100644 arch/arm/mach-s3c24xx/pll-s3c2410.c delete mode 100644 arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c delete mode 100644 arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c delete mode 100644 arch/arm/mach-s3c24xx/pm-h1940.S delete mode 100644 arch/arm/mach-s3c24xx/pm-s3c2410.c delete mode 100644 arch/arm/mach-s3c24xx/pm-s3c2412.c delete mode 100644 arch/arm/mach-s3c24xx/pm-s3c2416.c delete mode 100644 arch/arm/mach-s3c24xx/pm.c delete mode 100644 arch/arm/mach-s3c24xx/regs-dsc.h delete mode 100644 arch/arm/mach-s3c24xx/regs-mem.h delete mode 100644 arch/arm/mach-s3c24xx/s3c2410.c delete mode 100644 arch/arm/mach-s3c24xx/s3c2412-power.h delete mode 100644 arch/arm/mach-s3c24xx/s3c2412.c delete mode 100644 arch/arm/mach-s3c24xx/s3c2416.c delete mode 100644 arch/arm/mach-s3c24xx/s3c2440.c delete mode 100644 arch/arm/mach-s3c24xx/s3c2442.c delete mode 100644 arch/arm/mach-s3c24xx/s3c2443.c delete mode 100644 arch/arm/mach-s3c24xx/s3c244x.c delete mode 100644 arch/arm/mach-s3c24xx/setup-i2c.c delete mode 100644 arch/arm/mach-s3c24xx/setup-sdhci-gpio.c delete mode 100644 arch/arm/mach-s3c24xx/setup-spi.c delete mode 100644 arch/arm/mach-s3c24xx/setup-ts.c delete mode 100644 arch/arm/mach-s3c24xx/simtec-audio.c delete mode 100644 arch/arm/mach-s3c24xx/simtec-nor.c delete mode 100644 arch/arm/mach-s3c24xx/simtec-pm.c delete mode 100644 arch/arm/mach-s3c24xx/simtec-usb.c delete mode 100644 arch/arm/mach-s3c24xx/simtec.h delete mode 100644 arch/arm/mach-s3c24xx/sleep-s3c2410.S delete mode 100644 arch/arm/mach-s3c24xx/sleep-s3c2412.S delete mode 100644 arch/arm/mach-s3c24xx/sleep.S delete mode 100644 arch/arm/mach-s3c24xx/spi-core.h delete mode 100644 arch/arm/mach-s3c24xx/vr1000.h (limited to 'arch/arm/mach-s3c24xx') diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig deleted file mode 100644 index 000e3e234f71..000000000000 --- a/arch/arm/mach-s3c24xx/Kconfig +++ /dev/null @@ -1,583 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Copyright (c) 2012 Samsung Electronics Co., Ltd. -# http://www.samsung.com/ -# -# Copyright 2007 Simtec Electronics - -if ARCH_S3C24XX - -config PLAT_S3C24XX - def_bool y - select GPIOLIB - select NO_IOPORT_MAP - select S3C_DEV_NAND - select IRQ_DOMAIN - select COMMON_CLK - help - Base platform code for any Samsung S3C24XX device - - - -menu "Samsung S3C24XX SoCs Support" - -comment "S3C24XX SoCs" - -config CPU_S3C2410 - bool "Samsung S3C2410" - default y - select CPU_ARM920T - select S3C2410_COMMON_CLK - select ARM_S3C2410_CPUFREQ if ARM_S3C24XX_CPUFREQ - select S3C2410_PM if PM - help - Support for S3C2410 and S3C2410A family from the S3C24XX line - of Samsung Mobile CPUs. - -config CPU_S3C2412 - bool "Samsung S3C2412" - select CPU_ARM926T - select S3C2412_COMMON_CLK - select S3C2412_PM if PM_SLEEP - help - Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line - -config CPU_S3C2416 - bool "Samsung S3C2416/S3C2450" - select CPU_ARM926T - select S3C2416_PM if PM_SLEEP - select S3C2443_COMMON_CLK - help - Support for the S3C2416 SoC from the S3C24XX line - -config CPU_S3C2440 - bool "Samsung S3C2440" - select CPU_ARM920T - select S3C2410_COMMON_CLK - select S3C2410_PM if PM_SLEEP - help - Support for S3C2440 Samsung Mobile CPU based systems. - -config CPU_S3C2442 - bool "Samsung S3C2442" - select CPU_ARM920T - select S3C2410_COMMON_CLK - select S3C2410_PM if PM_SLEEP - help - Support for S3C2442 Samsung Mobile CPU based systems. - -config CPU_S3C244X - def_bool y - depends on CPU_S3C2440 || CPU_S3C2442 - -config CPU_S3C2443 - bool "Samsung S3C2443" - select CPU_ARM920T - select S3C2443_COMMON_CLK - help - Support for the S3C2443 SoC from the S3C24XX line - -# common code - -config S3C24XX_SMDK - bool - help - Common machine code for SMDK2410 and SMDK2440 - -config S3C24XX_SIMTEC_AUDIO - bool - depends on (ARCH_BAST || MACH_VR1000 || MACH_OSIRIS || MACH_ANUBIS) - default y - help - Add audio devices for common Simtec S3C24XX boards - -config S3C24XX_SIMTEC_PM - bool - help - Common power management code for systems that are - compatible with the Simtec style of power management - -config S3C24XX_SIMTEC_USB - bool - help - USB management code for common Simtec S3C24XX boards - -config S3C24XX_SETUP_TS - bool - help - Compile in platform device definition for Samsung TouchScreen. - -config S3C2410_PM - bool - help - Power Management code common to S3C2410 and better - -config S3C24XX_PLL - bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)" - depends on ARM_S3C24XX_CPUFREQ - help - Compile in support for changing the PLL frequency from the - S3C24XX series CPUfreq driver. The PLL takes time to settle - after a frequency change, so by default it is not enabled. - - This also means that the PLL tables for the selected CPU(s) will - be built which may increase the size of the kernel image. - -# cpu frequency items common between s3c2410 and s3c2440/s3c2442 - -config S3C2410_IOTIMING - bool - depends on ARM_S3C24XX_CPUFREQ - help - Internal node to select io timing code that is common to the s3c2410 - and s3c2440/s3c2442 cpu frequency support. - -# cpu frequency support common to s3c2412, s3c2413 and s3c2442 - -config S3C2412_IOTIMING - bool - depends on ARM_S3C24XX_CPUFREQ && (CPU_S3C2412 || CPU_S3C2443) - help - Intel node to select io timing code that is common to the s3c2412 - and the s3c2443. - -# cpu-specific sections - -if CPU_S3C2410 - -config S3C2410_PLL - bool - depends on ARM_S3C2410_CPUFREQ && S3C24XX_PLL - default y - help - Select the PLL table for the S3C2410 - -config S3C24XX_SIMTEC_NOR - bool - help - Internal node to specify machine has simtec NOR mapping - -config MACH_BAST_IDE - bool - select HAVE_PATA_PLATFORM - help - Internal node for machines with an BAST style IDE - interface - -comment "S3C2410 Boards" - -# -# The "S3C2410 Boards" list is ordered alphabetically by option text. -# (without ARCH_ or MACH_) -# - -config MACH_AML_M5900 - bool "AML M5900 Series" - select S3C24XX_SIMTEC_PM if PM - select S3C_DEV_USB_HOST - help - Say Y here if you are using the American Microsystems M5900 Series - - -config ARCH_BAST - bool "Simtec Electronics BAST (EB2410ITX)" - select ISA - select MACH_BAST_IDE - select S3C2410_COMMON_DCLK - select S3C2410_IOTIMING if ARM_S3C2410_CPUFREQ - select S3C24XX_SIMTEC_NOR - select S3C24XX_SIMTEC_PM if PM - select S3C24XX_SIMTEC_USB - select S3C_DEV_HWMON - select S3C_DEV_NAND - select S3C_DEV_USB_HOST - help - Say Y here if you are using the Simtec Electronics EB2410ITX - development board (also known as BAST) - -config BAST_PC104_IRQ - bool "BAST PC104 IRQ support" - depends on ARCH_BAST - default y - help - Say Y here to enable the PC104 IRQ routing on the - Simtec BAST (EB2410ITX) - -config ARCH_H1940 - bool "IPAQ H1940" - select PM_H1940 if PM - select S3C24XX_SETUP_TS - select S3C_DEV_NAND - select S3C_DEV_USB_HOST - help - Say Y here if you are using the HP IPAQ H1940 - -config H1940BT - tristate "Control the state of H1940 bluetooth chip" - depends on ARCH_H1940 - depends on RFKILL - help - This is a simple driver that is able to control - the state of built in bluetooth chip on h1940. - -config MACH_N30 - bool "Acer N30 family" - select S3C_DEV_NAND - select S3C_DEV_USB_HOST - help - Say Y here if you want suppt for the Acer N30, Acer N35, - Navman PiN570, Yakumo AlphaX or Airis NC05 PDAs. - -config MACH_OTOM - bool "NexVision OTOM Board" - select S3C_DEV_NAND - select S3C_DEV_USB_HOST - help - Say Y here if you are using the Nex Vision OTOM board - -config MACH_QT2410 - bool "QT2410" - select S3C_DEV_NAND - select S3C_DEV_USB_HOST - help - Say Y here if you are using the Armzone QT2410 - -config ARCH_SMDK2410 - bool "SMDK2410/A9M2410" - select S3C24XX_SMDK - select S3C_DEV_USB_HOST - help - Say Y here if you are using the SMDK2410 or the derived module A9M2410 - - -config MACH_TCT_HAMMER - bool "TCT Hammer Board" - select S3C_DEV_USB_HOST - help - Say Y here if you are using the TinCanTools Hammer Board - - -config MACH_VR1000 - bool "Thorcom VR1000" - select MACH_BAST_IDE - select S3C2410_COMMON_DCLK - select S3C24XX_SIMTEC_NOR - select S3C24XX_SIMTEC_PM if PM - select S3C24XX_SIMTEC_USB - select S3C_DEV_USB_HOST - help - Say Y here if you are using the Thorcom VR1000 board. - -endif # CPU_S3C2410 - -config S3C2412_PM_SLEEP - bool - help - Internal config node to apply sleep for S3C2412 power management. - Can be selected by another SoCs such as S3C2416 with similar - sleep procedure. - -if CPU_S3C2412 - -config CPU_S3C2412_ONLY - bool - depends on !CPU_S3C2410 && !CPU_S3C2416 && !CPU_S3C2440 && \ - !CPU_S3C2442 && !CPU_S3C2443 - default y - -config S3C2412_PM - bool - select S3C2412_PM_SLEEP - select SAMSUNG_WAKEMASK - help - Internal config node to apply S3C2412 power management - -comment "S3C2412 Boards" - -# -# The "S3C2412 Boards" list is ordered alphabetically by option text. -# (without ARCH_ or MACH_) -# - -config MACH_JIVE - bool "Logitech Jive" - select S3C_DEV_NAND - select S3C_DEV_USB_HOST - help - Say Y here if you are using the Logitech Jive. - -config MACH_JIVE_SHOW_BOOTLOADER - bool "Allow access to bootloader partitions in MTD" - depends on MACH_JIVE - -config MACH_S3C2413 - bool - help - Internal node for S3C2413 version of SMDK2413, so that - machine_is_s3c2413() will work when MACH_SMDK2413 is - selected - -config MACH_SMDK2412 - bool "SMDK2412" - select MACH_SMDK2413 - help - Say Y here if you are using an SMDK2412 - - Note, this shares support with SMDK2413, so will automatically - select MACH_SMDK2413. - -config MACH_SMDK2413 - bool "SMDK2413" - select MACH_S3C2413 - select S3C24XX_SMDK - select S3C_DEV_NAND - select S3C_DEV_USB_HOST - help - Say Y here if you are using an SMDK2413 - -config MACH_VSTMS - bool "VMSTMS" - select S3C_DEV_NAND - select S3C_DEV_USB_HOST - help - Say Y here if you are using an VSTMS board - -endif # CPU_S3C2412 - -if CPU_S3C2416 - -config S3C2416_PM - bool - select S3C2412_PM_SLEEP - select SAMSUNG_WAKEMASK - help - Internal config node to apply S3C2416 power management - -config S3C2416_SETUP_SDHCI - bool - select S3C2416_SETUP_SDHCI_GPIO - help - Internal helper functions for S3C2416 based SDHCI systems - -config S3C2416_SETUP_SDHCI_GPIO - bool - help - Common setup code for SDHCI gpio. - -comment "S3C2416 Boards" - -config MACH_SMDK2416 - bool "SMDK2416" - select S3C2416_SETUP_SDHCI - select S3C24XX_SMDK - select S3C_DEV_FB - select S3C_DEV_HSMMC - select S3C_DEV_HSMMC1 - select S3C_DEV_NAND - select S3C_DEV_USB_HOST - help - Say Y here if you are using an SMDK2416 - -config MACH_S3C2416_DT - bool "Samsung S3C2416 machine using devicetree" - select TIMER_OF - select USE_OF - select PINCTRL - select PINCTRL_S3C24XX - help - Machine support for Samsung S3C2416 machines with device tree enabled. - Select this if a fdt blob is available for the S3C2416 SoC based board. - Note: This is under development and not all peripherals can be supported - with this machine file. - -endif # CPU_S3C2416 - -if CPU_S3C2440 || CPU_S3C2442 - -config S3C2440_XTAL_12000000 - bool - help - Indicate that the build needs to support 12MHz system - crystal. - -config S3C2440_XTAL_16934400 - bool - help - Indicate that the build needs to support 16.9344MHz system - crystal. - -config S3C2440_PLL_12000000 - bool - depends on ARM_S3C2440_CPUFREQ && S3C2440_XTAL_12000000 - default y if S3C24XX_PLL - help - PLL tables for S3C2440 or S3C2442 CPUs with 12MHz crystals. - -config S3C2440_PLL_16934400 - bool - depends on ARM_S3C2440_CPUFREQ && S3C2440_XTAL_16934400 - default y if S3C24XX_PLL - help - PLL tables for S3C2440 or S3C2442 CPUs with 16.934MHz crystals. -endif - -if CPU_S3C2440 - -comment "S3C2440 Boards" - -# -# The "S3C2440 Boards" list is ordered alphabetically by option text. -# (without ARCH_ or MACH_) -# - -config MACH_ANUBIS - bool "Simtec Electronics ANUBIS" - select HAVE_PATA_PLATFORM - select S3C2410_COMMON_DCLK - select S3C2440_XTAL_12000000 - select S3C24XX_SIMTEC_PM if PM - select S3C_DEV_USB_HOST - help - Say Y here if you are using the Simtec Electronics ANUBIS - development system - -config MACH_AT2440EVB - bool "Avantech AT2440EVB development board" - select S3C_DEV_NAND - select S3C_DEV_USB_HOST - help - Say Y here if you are using the AT2440EVB development board - -config MACH_MINI2440 - bool "MINI2440 development board" - select LEDS_CLASS - select LEDS_TRIGGERS - select LEDS_TRIGGER_BACKLIGHT - select NEW_LEDS - select S3C_DEV_NAND - select S3C_DEV_USB_HOST - help - Say Y here to select support for the MINI2440. Is a 10cm x 10cm board - available via various sources. It can come with a 3.5" or 7" touch LCD. - -config MACH_NEXCODER_2440 - bool "NexVision NEXCODER 2440 Light Board" - select S3C2440_XTAL_12000000 - select S3C_DEV_NAND - select S3C_DEV_USB_HOST - help - Say Y here if you are using the Nex Vision NEXCODER 2440 Light Board - -config MACH_OSIRIS - bool "Simtec IM2440D20 (OSIRIS) module" - select S3C2410_COMMON_DCLK - select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ - select S3C2440_XTAL_12000000 - select S3C24XX_SIMTEC_PM if PM - select S3C_DEV_NAND - select S3C_DEV_USB_HOST - help - Say Y here if you are using the Simtec IM2440D20 module, also - known as the Osiris. - -config MACH_OSIRIS_DVS - tristate "Simtec IM2440D20 (OSIRIS) Dynamic Voltage Scaling driver" - depends on MACH_OSIRIS - depends on TPS65010 - help - Say Y/M here if you want to have dynamic voltage scaling support - on the Simtec IM2440D20 (OSIRIS) module via the TPS65011. - - The DVS driver alters the voltage supplied to the ARM core - depending on the frequency it is running at. The driver itself - does not do any of the frequency alteration, which is left up - to the cpufreq driver. - -config MACH_RX3715 - bool "HP iPAQ rx3715" - select PM_H1940 if PM - select S3C2440_XTAL_16934400 - select S3C_DEV_NAND - help - Say Y here if you are using the HP iPAQ rx3715. - -config ARCH_S3C2440 - bool "SMDK2440" - select S3C2440_XTAL_16934400 - select S3C24XX_SMDK - select S3C_DEV_NAND - select S3C_DEV_USB_HOST - help - Say Y here if you are using the SMDK2440. - -config SMDK2440_CPU2440 - bool "SMDK2440 with S3C2440 CPU module" - default y if ARCH_S3C2440 - select S3C2440_XTAL_16934400 - -endif # CPU_S3C2440 - -if CPU_S3C2442 - -comment "S3C2442 Boards" - -# -# The "S3C2442 Boards" list is ordered alphabetically by option text. -# (without ARCH_ or MACH_) -# - -config MACH_NEO1973_GTA02 - bool "Openmoko GTA02 / Freerunner phone" - select I2C - select MFD_PCF50633 - select PCF50633_GPIO - select POWER_SUPPLY - select S3C24XX_PWM - select S3C_DEV_USB_HOST - help - Say Y here if you are using the Openmoko GTA02 / Freerunner GSM Phone - -config MACH_RX1950 - bool "HP iPAQ rx1950" - select I2C - select PM_H1940 if PM - select S3C2410_COMMON_DCLK - select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ - select S3C2440_XTAL_16934400 - select S3C24XX_PWM - select S3C_DEV_NAND - help - Say Y here if you're using HP iPAQ rx1950 - -endif # CPU_S3C2442 - -if CPU_S3C2443 || CPU_S3C2416 - -config S3C2443_SETUP_SPI - bool - help - Common setup code for SPI GPIO configurations - -endif # CPU_S3C2443 || CPU_S3C2416 - -if CPU_S3C2443 - -comment "S3C2443 Boards" - -config MACH_SMDK2443 - bool "SMDK2443" - select S3C24XX_SMDK - select S3C_DEV_HSMMC1 - help - Say Y here if you are using an SMDK2443 - -endif # CPU_S3C2443 - -config PM_H1940 - bool - help - Internal node for H1940 and related PM - -endmenu # Samsung S3C24XX SoCs Support - -endif # ARCH_S3C24XX diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile deleted file mode 100644 index 68e583c94679..000000000000 --- a/arch/arm/mach-s3c24xx/Makefile +++ /dev/null @@ -1,102 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Copyright (c) 2012 Samsung Electronics Co., Ltd. -# http://www.samsung.com/ -# -# Copyright 2007 Simtec Electronics - -# core - -obj-y += common.o -obj-y += irq-s3c24xx.o -obj-$(CONFIG_SPI_S3C24XX_FIQ) += irq-s3c24xx-fiq.o -obj-$(CONFIG_SPI_S3C24XX_FIQ) += irq-s3c24xx-fiq-exports.o - -obj-$(CONFIG_CPU_S3C2410) += s3c2410.o -obj-$(CONFIG_S3C2410_PLL) += pll-s3c2410.o -obj-$(CONFIG_S3C2410_PM) += pm-s3c2410.o sleep-s3c2410.o - -obj-$(CONFIG_CPU_S3C2412) += s3c2412.o -obj-$(CONFIG_S3C2412_PM) += pm-s3c2412.o -obj-$(CONFIG_S3C2412_PM_SLEEP) += sleep-s3c2412.o - -obj-$(CONFIG_CPU_S3C2416) += s3c2416.o -obj-$(CONFIG_S3C2416_PM) += pm-s3c2416.o - -obj-$(CONFIG_CPU_S3C2440) += s3c2440.o -obj-$(CONFIG_CPU_S3C2442) += s3c2442.o -obj-$(CONFIG_CPU_S3C244X) += s3c244x.o -obj-$(CONFIG_S3C2440_PLL_12000000) += pll-s3c2440-12000000.o -obj-$(CONFIG_S3C2440_PLL_16934400) += pll-s3c2440-16934400.o - -obj-$(CONFIG_CPU_S3C2443) += s3c2443.o - -# PM - -obj-$(CONFIG_PM) += pm.o -obj-$(CONFIG_PM_SLEEP) += irq-pm.o sleep.o - -# common code - -obj-$(CONFIG_ARM_S3C24XX_CPUFREQ) += cpufreq-utils.o - -obj-$(CONFIG_S3C2410_IOTIMING) += iotiming-s3c2410.o -obj-$(CONFIG_S3C2412_IOTIMING) += iotiming-s3c2412.o - -# -# machine support -# following is ordered alphabetically by option text. -# - -obj-$(CONFIG_MACH_AML_M5900) += mach-amlm5900.o -obj-$(CONFIG_ARCH_BAST) += mach-bast.o -obj-$(CONFIG_BAST_PC104_IRQ) += bast-irq.o -obj-$(CONFIG_ARCH_H1940) += mach-h1940.o -obj-$(CONFIG_H1940BT) += h1940-bluetooth.o -obj-$(CONFIG_PM_H1940) += pm-h1940.o -obj-$(CONFIG_MACH_N30) += mach-n30.o -obj-$(CONFIG_MACH_OTOM) += mach-otom.o -obj-$(CONFIG_MACH_QT2410) += mach-qt2410.o -obj-$(CONFIG_ARCH_SMDK2410) += mach-smdk2410.o -obj-$(CONFIG_MACH_TCT_HAMMER) += mach-tct_hammer.o -obj-$(CONFIG_MACH_VR1000) += mach-vr1000.o - -obj-$(CONFIG_MACH_JIVE) += mach-jive.o -obj-$(CONFIG_MACH_SMDK2413) += mach-smdk2413.o -obj-$(CONFIG_MACH_VSTMS) += mach-vstms.o - -obj-$(CONFIG_MACH_SMDK2416) += mach-smdk2416.o -obj-$(CONFIG_MACH_S3C2416_DT) += mach-s3c2416-dt.o - -obj-$(CONFIG_MACH_ANUBIS) += mach-anubis.o -obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o -obj-$(CONFIG_MACH_MINI2440) += mach-mini2440.o -obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o -obj-$(CONFIG_MACH_OSIRIS) += mach-osiris.o -obj-$(CONFIG_MACH_RX3715) += mach-rx3715.o -obj-$(CONFIG_ARCH_S3C2440) += mach-smdk2440.o - -obj-$(CONFIG_MACH_NEO1973_GTA02) += mach-gta02.o -obj-$(CONFIG_MACH_RX1950) += mach-rx1950.o - -obj-$(CONFIG_MACH_SMDK2443) += mach-smdk2443.o - -# common bits of machine support - -obj-$(CONFIG_S3C24XX_SMDK) += common-smdk.o -obj-$(CONFIG_S3C24XX_SIMTEC_AUDIO) += simtec-audio.o -obj-$(CONFIG_S3C24XX_SIMTEC_NOR) += simtec-nor.o -obj-$(CONFIG_S3C24XX_SIMTEC_PM) += simtec-pm.o -obj-$(CONFIG_S3C24XX_SIMTEC_USB) += simtec-usb.o - -# machine additions - -obj-$(CONFIG_MACH_BAST_IDE) += bast-ide.o -obj-$(CONFIG_MACH_OSIRIS_DVS) += mach-osiris-dvs.o - -# device setup - -obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o -obj-$(CONFIG_S3C2443_SETUP_SPI) += setup-spi.o -obj-$(CONFIG_ARCH_S3C24XX) += setup-i2c.o -obj-$(CONFIG_S3C24XX_SETUP_TS) += setup-ts.o diff --git a/arch/arm/mach-s3c24xx/Makefile.boot b/arch/arm/mach-s3c24xx/Makefile.boot deleted file mode 100644 index 7f19e226035e..000000000000 --- a/arch/arm/mach-s3c24xx/Makefile.boot +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 - -ifeq ($(CONFIG_PM_H1940),y) - zreladdr-y += 0x30108000 - params_phys-y := 0x30100100 -else - zreladdr-y += 0x30008000 - params_phys-y := 0x30000100 -endif diff --git a/arch/arm/mach-s3c24xx/anubis.h b/arch/arm/mach-s3c24xx/anubis.h deleted file mode 100644 index 13847292e6c7..000000000000 --- a/arch/arm/mach-s3c24xx/anubis.h +++ /dev/null @@ -1,50 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2005 Simtec Electronics - * http://www.simtec.co.uk/products/ - * Ben Dooks - * - * ANUBIS - CPLD control constants - * ANUBIS - IRQ Number definitions - * ANUBIS - Memory map definitions - */ - -#ifndef __MACH_S3C24XX_ANUBIS_H -#define __MACH_S3C24XX_ANUBIS_H __FILE__ - -/* CTRL2 - NAND WP control, IDE Reset assert/check */ - -#define ANUBIS_CTRL1_NANDSEL (0x3) - -/* IDREG - revision */ - -#define ANUBIS_IDREG_REVMASK (0x7) - -/* irq */ - -#define ANUBIS_IRQ_IDE0 IRQ_EINT2 -#define ANUBIS_IRQ_IDE1 IRQ_EINT3 -#define ANUBIS_IRQ_ASIX IRQ_EINT1 - -/* map */ - -/* start peripherals off after the S3C2410 */ - -#define ANUBIS_IOADDR(x) (S3C2410_ADDR((x) + 0x01800000)) - -#define ANUBIS_PA_CPLD (S3C2410_CS1 | (1<<26)) - -/* we put the CPLD registers next, to get them out of the way */ - -#define ANUBIS_VA_CTRL1 ANUBIS_IOADDR(0x00000000) -#define ANUBIS_PA_CTRL1 ANUBIS_PA_CPLD - -#define ANUBIS_VA_IDREG ANUBIS_IOADDR(0x00300000) -#define ANUBIS_PA_IDREG (ANUBIS_PA_CPLD + (3 << 23)) - -#define ANUBIS_IDEPRI ANUBIS_IOADDR(0x01000000) -#define ANUBIS_IDEPRIAUX ANUBIS_IOADDR(0x01100000) -#define ANUBIS_IDESEC ANUBIS_IOADDR(0x01200000) -#define ANUBIS_IDESECAUX ANUBIS_IOADDR(0x01300000) - -#endif /* __MACH_S3C24XX_ANUBIS_H */ diff --git a/arch/arm/mach-s3c24xx/bast-ide.c b/arch/arm/mach-s3c24xx/bast-ide.c deleted file mode 100644 index ee6fbb407640..000000000000 --- a/arch/arm/mach-s3c24xx/bast-ide.c +++ /dev/null @@ -1,82 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright 2007 Simtec Electronics -// http://www.simtec.co.uk/products/EB2410ITX/ -// http://armlinux.simtec.co.uk/ -// Ben Dooks - -#include -#include -#include -#include - -#include -#include - -#include - -#include -#include -#include - -#include -#include - -#include "bast.h" - -/* IDE ports */ - -static struct pata_platform_info bast_ide_platdata = { - .ioport_shift = 5, -}; - -static struct resource bast_ide0_resource[] = { - [0] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDEPRI, 8 * 0x20), - [1] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDEPRIAUX + (6 * 0x20), 0x20), - [2] = DEFINE_RES_IRQ(BAST_IRQ_IDE0), -}; - -static struct platform_device bast_device_ide0 = { - .name = "pata_platform", - .id = 0, - .num_resources = ARRAY_SIZE(bast_ide0_resource), - .resource = bast_ide0_resource, - .dev = { - .platform_data = &bast_ide_platdata, - .coherent_dma_mask = ~0, - } - -}; - -static struct resource bast_ide1_resource[] = { - [0] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDESEC, 8 * 0x20), - [1] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDESECAUX + (6 * 0x20), 0x20), - [2] = DEFINE_RES_IRQ(BAST_IRQ_IDE1), -}; - -static struct platform_device bast_device_ide1 = { - .name = "pata_platform", - .id = 1, - .num_resources = ARRAY_SIZE(bast_ide1_resource), - .resource = bast_ide1_resource, - .dev = { - .platform_data = &bast_ide_platdata, - .coherent_dma_mask = ~0, - } -}; - -static struct platform_device *bast_ide_devices[] __initdata = { - &bast_device_ide0, - &bast_device_ide1, -}; - -static __init int bast_ide_init(void) -{ - if (machine_is_bast() || machine_is_vr1000()) - return platform_add_devices(bast_ide_devices, - ARRAY_SIZE(bast_ide_devices)); - - return 0; -} - -fs_initcall(bast_ide_init); diff --git a/arch/arm/mach-s3c24xx/bast-irq.c b/arch/arm/mach-s3c24xx/bast-irq.c deleted file mode 100644 index 141a35d58dd7..000000000000 --- a/arch/arm/mach-s3c24xx/bast-irq.c +++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2003-2005 Simtec Electronics -// Ben Dooks -// -// http://www.simtec.co.uk/products/EB2410ITX/ - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include "bast.h" - -#define irqdbf(x...) -#define irqdbf2(x...) - -/* handle PC104 ISA interrupts from the system CPLD */ - -/* table of ISA irq nos to the relevant mask... zero means - * the irq is not implemented -*/ -static const unsigned char bast_pc104_irqmasks[] = { - 0, /* 0 */ - 0, /* 1 */ - 0, /* 2 */ - 1, /* 3 */ - 0, /* 4 */ - 2, /* 5 */ - 0, /* 6 */ - 4, /* 7 */ - 0, /* 8 */ - 0, /* 9 */ - 8, /* 10 */ - 0, /* 11 */ - 0, /* 12 */ - 0, /* 13 */ - 0, /* 14 */ - 0, /* 15 */ -}; - -static const unsigned char bast_pc104_irqs[] = { 3, 5, 7, 10 }; - -static void -bast_pc104_mask(struct irq_data *data) -{ - unsigned long temp; - - temp = __raw_readb(BAST_VA_PC104_IRQMASK); - temp &= ~bast_pc104_irqmasks[data->irq]; - __raw_writeb(temp, BAST_VA_PC104_IRQMASK); -} - -static void -bast_pc104_maskack(struct irq_data *data) -{ - struct irq_desc *desc = irq_to_desc(BAST_IRQ_ISA); - - bast_pc104_mask(data); - desc->irq_data.chip->irq_ack(&desc->irq_data); -} - -static void -bast_pc104_unmask(struct irq_data *data) -{ - unsigned long temp; - - temp = __raw_readb(BAST_VA_PC104_IRQMASK); - temp |= bast_pc104_irqmasks[data->irq]; - __raw_writeb(temp, BAST_VA_PC104_IRQMASK); -} - -static struct irq_chip bast_pc104_chip = { - .irq_mask = bast_pc104_mask, - .irq_unmask = bast_pc104_unmask, - .irq_ack = bast_pc104_maskack -}; - -static void bast_irq_pc104_demux(struct irq_desc *desc) -{ - unsigned int stat; - unsigned int irqno; - int i; - - stat = __raw_readb(BAST_VA_PC104_IRQREQ) & 0xf; - - if (unlikely(stat == 0)) { - /* ack if we get an irq with nothing (ie, startup) */ - desc->irq_data.chip->irq_ack(&desc->irq_data); - } else { - /* handle the IRQ */ - - for (i = 0; stat != 0; i++, stat >>= 1) { - if (stat & 1) { - irqno = bast_pc104_irqs[i]; - generic_handle_irq(irqno); - } - } - } -} - -static __init int bast_irq_init(void) -{ - unsigned int i; - - if (machine_is_bast()) { - printk(KERN_INFO "BAST PC104 IRQ routing, Copyright 2005 Simtec Electronics\n"); - - /* zap all the IRQs */ - - __raw_writeb(0x0, BAST_VA_PC104_IRQMASK); - - irq_set_chained_handler(BAST_IRQ_ISA, bast_irq_pc104_demux); - - /* register our IRQs */ - - for (i = 0; i < 4; i++) { - unsigned int irqno = bast_pc104_irqs[i]; - - irq_set_chip_and_handler(irqno, &bast_pc104_chip, - handle_level_irq); - irq_clear_status_flags(irqno, IRQ_NOREQUEST); - } - } - - return 0; -} - -arch_initcall(bast_irq_init); diff --git a/arch/arm/mach-s3c24xx/bast.h b/arch/arm/mach-s3c24xx/bast.h deleted file mode 100644 index a7726f93f5eb..000000000000 --- a/arch/arm/mach-s3c24xx/bast.h +++ /dev/null @@ -1,194 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2003-2004 Simtec Electronics - * Ben Dooks - * - * BAST - CPLD control constants - * BAST - IRQ Number definitions - * BAST - Memory map definitions - */ - -#ifndef __MACH_S3C24XX_BAST_H -#define __MACH_S3C24XX_BAST_H __FILE__ - -/* CTRL1 - Audio LR routing */ - -#define BAST_CPLD_CTRL1_LRCOFF (0x00) -#define BAST_CPLD_CTRL1_LRCADC (0x01) -#define BAST_CPLD_CTRL1_LRCDAC (0x02) -#define BAST_CPLD_CTRL1_LRCARM (0x03) -#define BAST_CPLD_CTRL1_LRMASK (0x03) - -/* CTRL2 - NAND WP control, IDE Reset assert/check */ - -#define BAST_CPLD_CTRL2_WNAND (0x04) -#define BAST_CPLD_CTLR2_IDERST (0x08) - -/* CTRL3 - rom write control, CPLD identity */ - -#define BAST_CPLD_CTRL3_IDMASK (0x0e) -#define BAST_CPLD_CTRL3_ROMWEN (0x01) - -/* CTRL4 - 8bit LCD interface control/status */ - -#define BAST_CPLD_CTRL4_LLAT (0x01) -#define BAST_CPLD_CTRL4_LCDRW (0x02) -#define BAST_CPLD_CTRL4_LCDCMD (0x04) -#define BAST_CPLD_CTRL4_LCDE2 (0x01) - -/* CTRL5 - DMA routing */ - -#define BAST_CPLD_DMA0_PRIIDE (0) -#define BAST_CPLD_DMA0_SECIDE (1) -#define BAST_CPLD_DMA0_ISA15 (2) -#define BAST_CPLD_DMA0_ISA36 (3) - -#define BAST_CPLD_DMA1_PRIIDE (0 << 2) -#define BAST_CPLD_DMA1_SECIDE (1 << 2) -#define BAST_CPLD_DMA1_ISA15 (2 << 2) -#define BAST_CPLD_DMA1_ISA36 (3 << 2) - -/* irq numbers to onboard peripherals */ - -#define BAST_IRQ_USBOC IRQ_EINT18 -#define BAST_IRQ_IDE0 IRQ_EINT16 -#define BAST_IRQ_IDE1 IRQ_EINT17 -#define BAST_IRQ_PCSERIAL1 IRQ_EINT15 -#define BAST_IRQ_PCSERIAL2 IRQ_EINT14 -#define BAST_IRQ_PCPARALLEL IRQ_EINT13 -#define BAST_IRQ_ASIX IRQ_EINT11 -#define BAST_IRQ_DM9000 IRQ_EINT10 -#define BAST_IRQ_ISA IRQ_EINT9 -#define BAST_IRQ_SMALERT IRQ_EINT8 - -/* map */ - -/* - * ok, we've used up to 0x13000000, now we need to find space for the - * peripherals that live in the nGCS[x] areas, which are quite numerous - * in their space. We also have the board's CPLD to find register space - * for. - */ - -#define BAST_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000)) - -/* we put the CPLD registers next, to get them out of the way */ - -#define BAST_VA_CTRL1 BAST_IOADDR(0x00000000) -#define BAST_PA_CTRL1 (S3C2410_CS5 | 0x7800000) - -#define BAST_VA_CTRL2 BAST_IOADDR(0x00100000) -#define BAST_PA_CTRL2 (S3C2410_CS1 | 0x6000000) - -#define BAST_VA_CTRL3 BAST_IOADDR(0x00200000) -#define BAST_PA_CTRL3 (S3C2410_CS1 | 0x6800000) - -#define BAST_VA_CTRL4 BAST_IOADDR(0x00300000) -#define BAST_PA_CTRL4 (S3C2410_CS1 | 0x7000000) - -/* next, we have the PC104 ISA interrupt registers */ - -#define BAST_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000) -#define BAST_VA_PC104_IRQREQ BAST_IOADDR(0x00400000) - -#define BAST_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000) -#define BAST_VA_PC104_IRQRAW BAST_IOADDR(0x00500000) - -#define BAST_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) -#define BAST_VA_PC104_IRQMASK BAST_IOADDR(0x00600000) - -#define BAST_PA_LCD_RCMD1 (0x8800000) -#define BAST_VA_LCD_RCMD1 BAST_IOADDR(0x00700000) - -#define BAST_PA_LCD_WCMD1 (0x8000000) -#define BAST_VA_LCD_WCMD1 BAST_IOADDR(0x00800000) - -#define BAST_PA_LCD_RDATA1 (0x9800000) -#define BAST_VA_LCD_RDATA1 BAST_IOADDR(0x00900000) - -#define BAST_PA_LCD_WDATA1 (0x9000000) -#define BAST_VA_LCD_WDATA1 BAST_IOADDR(0x00A00000) - -#define BAST_PA_LCD_RCMD2 (0xA800000) -#define BAST_VA_LCD_RCMD2 BAST_IOADDR(0x00B00000) - -#define BAST_PA_LCD_WCMD2 (0xA000000) -#define BAST_VA_LCD_WCMD2 BAST_IOADDR(0x00C00000) - -#define BAST_PA_LCD_RDATA2 (0xB800000) -#define BAST_VA_LCD_RDATA2 BAST_IOADDR(0x00D00000) - -#define BAST_PA_LCD_WDATA2 (0xB000000) -#define BAST_VA_LCD_WDATA2 BAST_IOADDR(0x00E00000) - - -/* - * 0xE0000000 contains the IO space that is split by speed and - * whether the access is for 8 or 16bit IO... this ensures that - * the correct access is made - * - * 0x10000000 of space, partitioned as so: - * - * 0x00000000 to 0x04000000 8bit, slow - * 0x04000000 to 0x08000000 16bit, slow - * 0x08000000 to 0x0C000000 16bit, net - * 0x0C000000 to 0x10000000 16bit, fast - * - * each of these spaces has the following in: - * - * 0x00000000 to 0x01000000 16MB ISA IO space - * 0x01000000 to 0x02000000 16MB ISA memory space - * 0x02000000 to 0x02100000 1MB IDE primary channel - * 0x02100000 to 0x02200000 1MB IDE primary channel aux - * 0x02200000 to 0x02400000 1MB IDE secondary channel - * 0x02300000 to 0x02400000 1MB IDE secondary channel aux - * 0x02400000 to 0x02500000 1MB ASIX ethernet controller - * 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controller - * 0x02600000 to 0x02700000 1MB PC SuperIO controller - * - * the phyiscal layout of the zones are: - * nGCS2 - 8bit, slow - * nGCS3 - 16bit, slow - * nGCS4 - 16bit, net - * nGCS5 - 16bit, fast - */ - -#define BAST_VA_MULTISPACE (0xE0000000) - -#define BAST_VA_ISAIO (BAST_VA_MULTISPACE + 0x00000000) -#define BAST_VA_ISAMEM (BAST_VA_MULTISPACE + 0x01000000) -#define BAST_VA_IDEPRI (BAST_VA_MULTISPACE + 0x02000000) -#define BAST_VA_IDEPRIAUX (BAST_VA_MULTISPACE + 0x02100000) -#define BAST_VA_IDESEC (BAST_VA_MULTISPACE + 0x02200000) -#define BAST_VA_IDESECAUX (BAST_VA_MULTISPACE + 0x02300000) -#define BAST_VA_ASIXNET (BAST_VA_MULTISPACE + 0x02400000) -#define BAST_VA_DM9000 (BAST_VA_MULTISPACE + 0x02500000) -#define BAST_VA_SUPERIO (BAST_VA_MULTISPACE + 0x02600000) - -#define BAST_VAM_CS2 (0x00000000) -#define BAST_VAM_CS3 (0x04000000) -#define BAST_VAM_CS4 (0x08000000) -#define BAST_VAM_CS5 (0x0C000000) - -/* physical offset addresses for the peripherals */ - -#define BAST_PA_ISAIO (0x00000000) -#define BAST_PA_ASIXNET (0x01000000) -#define BAST_PA_SUPERIO (0x01800000) -#define BAST_PA_IDEPRI (0x02000000) -#define BAST_PA_IDEPRIAUX (0x02800000) -#define BAST_PA_IDESEC (0x03000000) -#define BAST_PA_IDESECAUX (0x03800000) -#define BAST_PA_ISAMEM (0x04000000) -#define BAST_PA_DM9000 (0x05000000) - -/* some configurations for the peripherals */ - -#define BAST_PCSIO (BAST_VA_SUPERIO + BAST_VAM_CS2) - -#define BAST_ASIXNET_CS BAST_VAM_CS5 -#define BAST_DM9000_CS BAST_VAM_CS4 - -#define BAST_IDE_CS S3C2410_CS5 - -#endif /* __MACH_S3C24XX_BAST_H */ diff --git a/arch/arm/mach-s3c24xx/common-smdk.c b/arch/arm/mach-s3c24xx/common-smdk.c deleted file mode 100644 index c0c176651f96..000000000000 --- a/arch/arm/mach-s3c24xx/common-smdk.c +++ /dev/null @@ -1,228 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (c) 2006 Simtec Electronics -// Ben Dooks -// -// Common code for SMDK2410 and SMDK2440 boards -// -// http://www.fluff.org/ben/smdk2440/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include -#include -#include -#include - -#include -#include -#include - -#include "common-smdk.h" - -/* LED devices */ - -static struct gpiod_lookup_table smdk_led4_gpio_table = { - .dev_id = "s3c24xx_led.0", - .table = { - GPIO_LOOKUP("GPF", 4, NULL, GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN), - { }, - }, -}; - -static struct gpiod_lookup_table smdk_led5_gpio_table = { - .dev_id = "s3c24xx_led.1", - .table = { - GPIO_LOOKUP("GPF", 5, NULL, GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN), - { }, - }, -}; - -static struct gpiod_lookup_table smdk_led6_gpio_table = { - .dev_id = "s3c24xx_led.2", - .table = { - GPIO_LOOKUP("GPF", 6, NULL, GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN), - { }, - }, -}; - -static struct gpiod_lookup_table smdk_led7_gpio_table = { - .dev_id = "s3c24xx_led.3", - .table = { - GPIO_LOOKUP("GPF", 7, NULL, GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN), - { }, - }, -}; - -static struct s3c24xx_led_platdata smdk_pdata_led4 = { - .name = "led4", - .def_trigger = "timer", -}; - -static struct s3c24xx_led_platdata smdk_pdata_led5 = { - .name = "led5", - .def_trigger = "nand-disk", -}; - -static struct s3c24xx_led_platdata smdk_pdata_led6 = { - .name = "led6", -}; - -static struct s3c24xx_led_platdata smdk_pdata_led7 = { - .name = "led7", -}; - -static struct platform_device smdk_led4 = { - .name = "s3c24xx_led", - .id = 0, - .dev = { - .platform_data = &smdk_pdata_led4, - }, -}; - -static struct platform_device smdk_led5 = { - .name = "s3c24xx_led", - .id = 1, - .dev = { - .platform_data = &smdk_pdata_led5, - }, -}; - -static struct platform_device smdk_led6 = { - .name = "s3c24xx_led", - .id = 2, - .dev = { - .platform_data = &smdk_pdata_led6, - }, -}; - -static struct platform_device smdk_led7 = { - .name = "s3c24xx_led", - .id = 3, - .dev = { - .platform_data = &smdk_pdata_led7, - }, -}; - -/* NAND parititon from 2.4.18-swl5 */ - -static struct mtd_partition smdk_default_nand_part[] = { - [0] = { - .name = "Boot Agent", - .size = SZ_16K, - .offset = 0, - }, - [1] = { - .name = "S3C2410 flash partition 1", - .offset = 0, - .size = SZ_2M, - }, - [2] = { - .name = "S3C2410 flash partition 2", - .offset = SZ_4M, - .size = SZ_4M, - }, - [3] = { - .name = "S3C2410 flash partition 3", - .offset = SZ_8M, - .size = SZ_2M, - }, - [4] = { - .name = "S3C2410 flash partition 4", - .offset = SZ_1M * 10, - .size = SZ_4M, - }, - [5] = { - .name = "S3C2410 flash partition 5", - .offset = SZ_1M * 14, - .size = SZ_1M * 10, - }, - [6] = { - .name = "S3C2410 flash partition 6", - .offset = SZ_1M * 24, - .size = SZ_1M * 24, - }, - [7] = { - .name = "S3C2410 flash partition 7", - .offset = SZ_1M * 48, - .size = MTDPART_SIZ_FULL, - } -}; - -static struct s3c2410_nand_set smdk_nand_sets[] = { - [0] = { - .name = "NAND", - .nr_chips = 1, - .nr_partitions = ARRAY_SIZE(smdk_default_nand_part), - .partitions = smdk_default_nand_part, - }, -}; - -/* choose a set of timings which should suit most 512Mbit - * chips and beyond. -*/ - -static struct s3c2410_platform_nand smdk_nand_info = { - .tacls = 20, - .twrph0 = 60, - .twrph1 = 20, - .nr_sets = ARRAY_SIZE(smdk_nand_sets), - .sets = smdk_nand_sets, - .ecc_mode = NAND_ECC_SOFT, -}; - -/* devices we initialise */ - -static struct platform_device __initdata *smdk_devs[] = { - &s3c_device_nand, - &smdk_led4, - &smdk_led5, - &smdk_led6, - &smdk_led7, -}; - -void __init smdk_machine_init(void) -{ - if (machine_is_smdk2443()) - smdk_nand_info.twrph0 = 50; - - s3c_nand_set_platdata(&smdk_nand_info); - - /* Disable pull-up on the LED lines */ - s3c_gpio_setpull(S3C2410_GPF(4), S3C_GPIO_PULL_NONE); - s3c_gpio_setpull(S3C2410_GPF(5), S3C_GPIO_PULL_NONE); - s3c_gpio_setpull(S3C2410_GPF(6), S3C_GPIO_PULL_NONE); - s3c_gpio_setpull(S3C2410_GPF(7), S3C_GPIO_PULL_NONE); - - /* Add lookups for the lines */ - gpiod_add_lookup_table(&smdk_led4_gpio_table); - gpiod_add_lookup_table(&smdk_led5_gpio_table); - gpiod_add_lookup_table(&smdk_led6_gpio_table); - gpiod_add_lookup_table(&smdk_led7_gpio_table); - - platform_add_devices(smdk_devs, ARRAY_SIZE(smdk_devs)); - - s3c_pm_init(); -} diff --git a/arch/arm/mach-s3c24xx/common-smdk.h b/arch/arm/mach-s3c24xx/common-smdk.h deleted file mode 100644 index c0352b06e435..000000000000 --- a/arch/arm/mach-s3c24xx/common-smdk.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2006 Simtec Electronics - * Ben Dooks - * - * Common code for SMDK2410 and SMDK2440 boards - * - * http://www.fluff.org/ben/smdk2440/ - */ - -extern void smdk_machine_init(void); diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c deleted file mode 100644 index 30b0dcd20f17..000000000000 --- a/arch/arm/mach-s3c24xx/common.c +++ /dev/null @@ -1,680 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright (c) 2004-2005 Simtec Electronics -// http://www.simtec.co.uk/products/SWLINUX/ -// Ben Dooks -// -// Common code for S3C24XX machines - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include - -#include -#include -#include - -#include "common.h" - -/* table of supported CPUs */ - -static const char name_s3c2410[] = "S3C2410"; -static const char name_s3c2412[] = "S3C2412"; -static const char name_s3c2416[] = "S3C2416/S3C2450"; -static const char name_s3c2440[] = "S3C2440"; -static const char name_s3c2442[] = "S3C2442"; -static const char name_s3c2442b[] = "S3C2442B"; -static const char name_s3c2443[] = "S3C2443"; -static const char name_s3c2410a[] = "S3C2410A"; -static const char name_s3c2440a[] = "S3C2440A"; - -static struct cpu_table cpu_ids[] __initdata = { - { - .idcode = 0x32410000, - .idmask = 0xffffffff, - .map_io = s3c2410_map_io, - .init_uarts = s3c2410_init_uarts, - .init = s3c2410_init, - .name = name_s3c2410 - }, - { - .idcode = 0x32410002, - .idmask = 0xffffffff, - .map_io = s3c2410_map_io, - .init_uarts = s3c2410_init_uarts, - .init = s3c2410a_init, - .name = name_s3c2410a - }, - { - .idcode = 0x32440000, - .idmask = 0xffffffff, - .map_io = s3c2440_map_io, - .init_uarts = s3c244x_init_uarts, - .init = s3c2440_init, - .name = name_s3c2440 - }, - { - .idcode = 0x32440001, - .idmask = 0xffffffff, - .map_io = s3c2440_map_io, - .init_uarts = s3c244x_init_uarts, - .init = s3c2440_init, - .name = name_s3c2440a - }, - { - .idcode = 0x32440aaa, - .idmask = 0xffffffff, - .map_io = s3c2442_map_io, - .init_uarts = s3c244x_init_uarts, - .init = s3c2442_init, - .name = name_s3c2442 - }, - { - .idcode = 0x32440aab, - .idmask = 0xffffffff, - .map_io = s3c2442_map_io, - .init_uarts = s3c244x_init_uarts, - .init = s3c2442_init, - .name = name_s3c2442b - }, - { - .idcode = 0x32412001, - .idmask = 0xffffffff, - .map_io = s3c2412_map_io, - .init_uarts = s3c2412_init_uarts, - .init = s3c2412_init, - .name = name_s3c2412, - }, - { /* a newer version of the s3c2412 */ - .idcode = 0x32412003, - .idmask = 0xffffffff, - .map_io = s3c2412_map_io, - .init_uarts = s3c2412_init_uarts, - .init = s3c2412_init, - .name = name_s3c2412, - }, - { /* a strange version of the s3c2416 */ - .idcode = 0x32450003, - .idmask = 0xffffffff, - .map_io = s3c2416_map_io, - .init_uarts = s3c2416_init_uarts, - .init = s3c2416_init, - .name = name_s3c2416, - }, - { - .idcode = 0x32443001, - .idmask = 0xffffffff, - .map_io = s3c2443_map_io, - .init_uarts = s3c2443_init_uarts, - .init = s3c2443_init, - .name = name_s3c2443, - }, -}; - -/* minimal IO mapping */ - -static struct map_desc s3c_iodesc[] __initdata = { - IODESC_ENT(GPIO), - IODESC_ENT(IRQ), - IODESC_ENT(MEMCTRL), - IODESC_ENT(UART) -}; - -/* read cpu identificaiton code */ - -static unsigned long s3c24xx_read_idcode_v5(void) -{ -#if defined(CONFIG_CPU_S3C2416) - /* s3c2416 is v5, with S3C24XX_GSTATUS1 instead of S3C2412_GSTATUS1 */ - - u32 gs = __raw_readl(S3C24XX_GSTATUS1); - - /* test for s3c2416 or similar device */ - if ((gs >> 16) == 0x3245) - return gs; -#endif - -#if defined(CONFIG_CPU_S3C2412) - return __raw_readl(S3C2412_GSTATUS1); -#else - return 1UL; /* don't look like an 2400 */ -#endif -} - -static unsigned long s3c24xx_read_idcode_v4(void) -{ - return __raw_readl(S3C2410_GSTATUS1); -} - -static void s3c24xx_default_idle(void) -{ - unsigned long tmp = 0; - int i; - - /* idle the system by using the idle mode which will wait for an - * interrupt to happen before restarting the system. - */ - - /* Warning: going into idle state upsets jtag scanning */ - - __raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE, - S3C2410_CLKCON); - - /* the samsung port seems to do a loop and then unset idle.. */ - for (i = 0; i < 50; i++) - tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */ - - /* this bit is not cleared on re-start... */ - - __raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE, - S3C2410_CLKCON); -} - -static struct samsung_pwm_variant s3c24xx_pwm_variant = { - .bits = 16, - .div_base = 1, - .has_tint_cstat = false, - .tclk_mask = (1 << 4), -}; - -void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) -{ - arm_pm_idle = s3c24xx_default_idle; - - /* initialise the io descriptors we need for initialisation */ - iotable_init(mach_desc, size); - iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); - - if (cpu_architecture() >= CPU_ARCH_ARMv5) { - samsung_cpu_id = s3c24xx_read_idcode_v5(); - } else { - samsung_cpu_id = s3c24xx_read_idcode_v4(); - } - - s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); - - samsung_pwm_set_platdata(&s3c24xx_pwm_variant); -} - -void __init samsung_set_timer_source(unsigned int event, unsigned int source) -{ - s3c24xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1; - s3c24xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source)); -} - -void __init samsung_timer_init(void) -{ - unsigned int timer_irqs[SAMSUNG_PWM_NUM] = { - IRQ_TIMER0, IRQ_TIMER1, IRQ_TIMER2, IRQ_TIMER3, IRQ_TIMER4, - }; - - samsung_pwm_clocksource_init(S3C_VA_TIMER, - timer_irqs, &s3c24xx_pwm_variant); -} - -/* Serial port registrations */ - -#define S3C2410_PA_UART0 (S3C24XX_PA_UART) -#define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 ) -#define S3C2410_PA_UART2 (S3C24XX_PA_UART + 0x8000 ) -#define S3C2443_PA_UART3 (S3C24XX_PA_UART + 0xC000 ) - -static struct resource s3c2410_uart0_resource[] = { - [0] = DEFINE_RES_MEM(S3C2410_PA_UART0, SZ_16K), - [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX0, \ - IRQ_S3CUART_ERR0 - IRQ_S3CUART_RX0 + 1, \ - NULL, IORESOURCE_IRQ) -}; - -static struct resource s3c2410_uart1_resource[] = { - [0] = DEFINE_RES_MEM(S3C2410_PA_UART1, SZ_16K), - [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX1, \ - IRQ_S3CUART_ERR1 - IRQ_S3CUART_RX1 + 1, \ - NULL, IORESOURCE_IRQ) -}; - -static struct resource s3c2410_uart2_resource[] = { - [0] = DEFINE_RES_MEM(S3C2410_PA_UART2, SZ_16K), - [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX2, \ - IRQ_S3CUART_ERR2 - IRQ_S3CUART_RX2 + 1, \ - NULL, IORESOURCE_IRQ) -}; - -static struct resource s3c2410_uart3_resource[] = { - [0] = DEFINE_RES_MEM(S3C2443_PA_UART3, SZ_16K), - [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX3, \ - IRQ_S3CUART_ERR3 - IRQ_S3CUART_RX3 + 1, \ - NULL, IORESOURCE_IRQ) -}; - -struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = { - [0] = { - .resources = s3c2410_uart0_resource, - .nr_resources = ARRAY_SIZE(s3c2410_uart0_resource), - }, - [1] = { - .resources = s3c2410_uart1_resource, - .nr_resources = ARRAY_SIZE(s3c2410_uart1_resource), - }, - [2] = { - .resources = s3c2410_uart2_resource, - .nr_resources = ARRAY_SIZE(s3c2410_uart2_resource), - }, - [3] = { - .resources = s3c2410_uart3_resource, - .nr_resources = ARRAY_SIZE(s3c2410_uart3_resource), - }, -}; - -#define s3c24xx_device_dma_mask (*((u64[]) { DMA_BIT_MASK(32) })) - -#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \ - defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) -static struct resource s3c2410_dma_resource[] = { - [0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA), - [1] = DEFINE_RES_IRQ(IRQ_DMA0), - [2] = DEFINE_RES_IRQ(IRQ_DMA1), - [3] = DEFINE_RES_IRQ(IRQ_DMA2), - [4] = DEFINE_RES_IRQ(IRQ_DMA3), -}; -#endif - -#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2442) -static struct s3c24xx_dma_channel s3c2410_dma_channels[DMACH_MAX] = { - [DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), }, - [DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), }, - [DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) | - S3C24XX_DMA_CHANREQ(2, 2) | - S3C24XX_DMA_CHANREQ(1, 3), - }, - [DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), }, - [DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), }, - [DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), }, - [DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), }, - [DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), }, - [DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) | - S3C24XX_DMA_CHANREQ(3, 2) | - S3C24XX_DMA_CHANREQ(3, 3), - }, - [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) | - S3C24XX_DMA_CHANREQ(1, 2), - }, - [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 2), }, - [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), }, - [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), }, - [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), }, - [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), }, -}; - -static const struct dma_slave_map s3c2410_dma_slave_map[] = { - { "s3c2410-sdi", "rx-tx", (void *)DMACH_SDI }, - { "s3c2410-spi.0", "rx", (void *)DMACH_SPI0_RX }, - { "s3c2410-spi.0", "tx", (void *)DMACH_SPI0_TX }, - { "s3c2410-spi.1", "rx", (void *)DMACH_SPI1_RX }, - { "s3c2410-spi.1", "tx", (void *)DMACH_SPI1_TX }, - /* - * The DMA request source[1] (DMACH_UARTx_SRC2) are - * not used in the UART driver. - */ - { "s3c2410-uart.0", "rx", (void *)DMACH_UART0 }, - { "s3c2410-uart.0", "tx", (void *)DMACH_UART0 }, - { "s3c2410-uart.1", "rx", (void *)DMACH_UART1 }, - { "s3c2410-uart.1", "tx", (void *)DMACH_UART1 }, - { "s3c2410-uart.2", "rx", (void *)DMACH_UART2 }, - { "s3c2410-uart.2", "tx", (void *)DMACH_UART2 }, - { "s3c24xx-iis", "rx", (void *)DMACH_I2S_IN }, - { "s3c24xx-iis", "tx", (void *)DMACH_I2S_OUT }, - { "s3c-hsudc", "rx0", (void *)DMACH_USB_EP1 }, - { "s3c-hsudc", "tx0", (void *)DMACH_USB_EP1 }, - { "s3c-hsudc", "rx1", (void *)DMACH_USB_EP2 }, - { "s3c-hsudc", "tx1", (void *)DMACH_USB_EP2 }, - { "s3c-hsudc", "rx2", (void *)DMACH_USB_EP3 }, - { "s3c-hsudc", "tx2", (void *)DMACH_USB_EP3 }, - { "s3c-hsudc", "rx3", (void *)DMACH_USB_EP4 }, - { "s3c-hsudc", "tx3", (void *)DMACH_USB_EP4 } -}; - -static struct s3c24xx_dma_platdata s3c2410_dma_platdata = { - .num_phy_channels = 4, - .channels = s3c2410_dma_channels, - .num_channels = DMACH_MAX, - .slave_map = s3c2410_dma_slave_map, - .slavecnt = ARRAY_SIZE(s3c2410_dma_slave_map), -}; - -struct platform_device s3c2410_device_dma = { - .name = "s3c2410-dma", - .id = 0, - .num_resources = ARRAY_SIZE(s3c2410_dma_resource), - .resource = s3c2410_dma_resource, - .dev = { - .dma_mask = &s3c24xx_device_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &s3c2410_dma_platdata, - }, -}; -#endif - -#ifdef CONFIG_CPU_S3C2412 -static struct s3c24xx_dma_channel s3c2412_dma_channels[DMACH_MAX] = { - [DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 }, - [DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 }, - [DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 }, - [DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 }, - [DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 }, - [DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 }, - [DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 }, - [DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 }, - [DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 }, - [DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 }, - [DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 }, - [DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 }, - [DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 }, - [DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 }, - [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 }, - [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 }, - [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, 13 }, - [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, 14 }, - [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, 15 }, - [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, 16 }, -}; - -static const struct dma_slave_map s3c2412_dma_slave_map[] = { - { "s3c2412-sdi", "rx-tx", (void *)DMACH_SDI }, - { "s3c2412-spi.0", "rx", (void *)DMACH_SPI0_RX }, - { "s3c2412-spi.0", "tx", (void *)DMACH_SPI0_TX }, - { "s3c2412-spi.1", "rx", (void *)DMACH_SPI1_RX }, - { "s3c2412-spi.1", "tx", (void *)DMACH_SPI1_TX }, - { "s3c2440-uart.0", "rx", (void *)DMACH_UART0 }, - { "s3c2440-uart.0", "tx", (void *)DMACH_UART0 }, - { "s3c2440-uart.1", "rx", (void *)DMACH_UART1 }, - { "s3c2440-uart.1", "tx", (void *)DMACH_UART1 }, - { "s3c2440-uart.2", "rx", (void *)DMACH_UART2 }, - { "s3c2440-uart.2", "tx", (void *)DMACH_UART2 }, - { "s3c2412-iis", "rx", (void *)DMACH_I2S_IN }, - { "s3c2412-iis", "tx", (void *)DMACH_I2S_OUT }, - { "s3c-hsudc", "rx0", (void *)DMACH_USB_EP1 }, - { "s3c-hsudc", "tx0", (void *)DMACH_USB_EP1 }, - { "s3c-hsudc", "rx1", (void *)DMACH_USB_EP2 }, - { "s3c-hsudc", "tx1", (void *)DMACH_USB_EP2 }, - { "s3c-hsudc", "rx2", (void *)DMACH_USB_EP3 }, - { "s3c-hsudc", "tx2", (void *)DMACH_USB_EP3 }, - { "s3c-hsudc", "rx3", (void *)DMACH_USB_EP4 }, - { "s3c-hsudc", "tx3", (void *)DMACH_USB_EP4 } -}; - -static struct s3c24xx_dma_platdata s3c2412_dma_platdata = { - .num_phy_channels = 4, - .channels = s3c2412_dma_channels, - .num_channels = DMACH_MAX, - .slave_map = s3c2412_dma_slave_map, - .slavecnt = ARRAY_SIZE(s3c2412_dma_slave_map), -}; - -struct platform_device s3c2412_device_dma = { - .name = "s3c2412-dma", - .id = 0, - .num_resources = ARRAY_SIZE(s3c2410_dma_resource), - .resource = s3c2410_dma_resource, - .dev = { - .dma_mask = &s3c24xx_device_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &s3c2412_dma_platdata, - }, -}; -#endif - -#if defined(CONFIG_CPU_S3C2440) -static struct s3c24xx_dma_channel s3c2440_dma_channels[DMACH_MAX] = { - [DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), }, - [DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), }, - [DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) | - S3C24XX_DMA_CHANREQ(6, 1) | - S3C24XX_DMA_CHANREQ(2, 2) | - S3C24XX_DMA_CHANREQ(1, 3), - }, - [DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), }, - [DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), }, - [DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), }, - [DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), }, - [DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), }, - [DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) | - S3C24XX_DMA_CHANREQ(3, 2) | - S3C24XX_DMA_CHANREQ(3, 3), - }, - [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) | - S3C24XX_DMA_CHANREQ(1, 2), - }, - [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 0) | - S3C24XX_DMA_CHANREQ(0, 2), - }, - [DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 0) | - S3C24XX_DMA_CHANREQ(5, 2), - }, - [DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 1) | - S3C24XX_DMA_CHANREQ(6, 3), - }, - [DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 2) | - S3C24XX_DMA_CHANREQ(5, 3), - }, - [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), }, - [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), }, - [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), }, - [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), }, -}; - -static const struct dma_slave_map s3c2440_dma_slave_map[] = { - /* TODO: DMACH_XD0 */ - /* TODO: DMACH_XD1 */ - { "s3c2440-sdi", "rx-tx", (void *)DMACH_SDI }, - { "s3c2410-spi.0", "rx", (void *)DMACH_SPI0 }, - { "s3c2410-spi.0", "tx", (void *)DMACH_SPI0 }, - { "s3c2410-spi.1", "rx", (void *)DMACH_SPI1 }, - { "s3c2410-spi.1", "tx", (void *)DMACH_SPI1 }, - { "s3c2440-uart.0", "rx", (void *)DMACH_UART0 }, - { "s3c2440-uart.0", "tx", (void *)DMACH_UART0 }, - { "s3c2440-uart.1", "rx", (void *)DMACH_UART1 }, - { "s3c2440-uart.1", "tx", (void *)DMACH_UART1 }, - { "s3c2440-uart.2", "rx", (void *)DMACH_UART2 }, - { "s3c2440-uart.2", "tx", (void *)DMACH_UART2 }, - { "s3c2440-uart.3", "rx", (void *)DMACH_UART3 }, - { "s3c2440-uart.3", "tx", (void *)DMACH_UART3 }, - /* TODO: DMACH_TIMER */ - { "s3c24xx-iis", "rx", (void *)DMACH_I2S_IN }, - { "s3c24xx-iis", "tx", (void *)DMACH_I2S_OUT }, - { "samsung-ac97", "rx", (void *)DMACH_PCM_IN }, - { "samsung-ac97", "tx", (void *)DMACH_PCM_OUT }, - { "samsung-ac97", "rx", (void *)DMACH_MIC_IN }, - { "s3c-hsudc", "rx0", (void *)DMACH_USB_EP1 }, - { "s3c-hsudc", "rx1", (void *)DMACH_USB_EP2 }, - { "s3c-hsudc", "rx2", (void *)DMACH_USB_EP3 }, - { "s3c-hsudc", "rx3", (void *)DMACH_USB_EP4 }, - { "s3c-hsudc", "tx0", (void *)DMACH_USB_EP1 }, - { "s3c-hsudc", "tx1", (void *)DMACH_USB_EP2 }, - { "s3c-hsudc", "tx2", (void *)DMACH_USB_EP3 }, - { "s3c-hsudc", "tx3", (void *)DMACH_USB_EP4 } -}; - -static struct s3c24xx_dma_platdata s3c2440_dma_platdata = { - .num_phy_channels = 4, - .channels = s3c2440_dma_channels, - .num_channels = DMACH_MAX, - .slave_map = s3c2440_dma_slave_map, - .slavecnt = ARRAY_SIZE(s3c2440_dma_slave_map), -}; - -struct platform_device s3c2440_device_dma = { - .name = "s3c2410-dma", - .id = 0, - .num_resources = ARRAY_SIZE(s3c2410_dma_resource), - .resource = s3c2410_dma_resource, - .dev = { - .dma_mask = &s3c24xx_device_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &s3c2440_dma_platdata, - }, -}; -#endif - -#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416) -static struct resource s3c2443_dma_resource[] = { - [0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA), - [1] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA0), - [2] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA1), - [3] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA2), - [4] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA3), - [5] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA4), - [6] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA5), -}; - -static struct s3c24xx_dma_channel s3c2443_dma_channels[DMACH_MAX] = { - [DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 }, - [DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 }, - [DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 }, - [DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 }, - [DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 }, - [DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 }, - [DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 }, - [DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 }, - [DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 }, - [DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 }, - [DMACH_UART3] = { S3C24XX_DMA_APB, true, 25 }, - [DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 }, - [DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 }, - [DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 }, - [DMACH_UART3_SRC2] = { S3C24XX_DMA_APB, true, 26 }, - [DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 }, - [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 }, - [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 }, - [DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, 28 }, - [DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, 27 }, - [DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, 29 }, -}; - -static const struct dma_slave_map s3c2443_dma_slave_map[] = { - { "s3c2440-sdi", "rx-tx", (void *)DMACH_SDI }, - { "s3c2443-spi.0", "rx", (void *)DMACH_SPI0_RX }, - { "s3c2443-spi.0", "tx", (void *)DMACH_SPI0_TX }, - { "s3c2443-spi.1", "rx", (void *)DMACH_SPI1_RX }, - { "s3c2443-spi.1", "tx", (void *)DMACH_SPI1_TX }, - { "s3c2440-uart.0", "rx", (void *)DMACH_UART0 }, - { "s3c2440-uart.0", "tx", (void *)DMACH_UART0 }, - { "s3c2440-uart.1", "rx", (void *)DMACH_UART1 }, - { "s3c2440-uart.1", "tx", (void *)DMACH_UART1 }, - { "s3c2440-uart.2", "rx", (void *)DMACH_UART2 }, - { "s3c2440-uart.2", "tx", (void *)DMACH_UART2 }, - { "s3c2440-uart.3", "rx", (void *)DMACH_UART3 }, - { "s3c2440-uart.3", "tx", (void *)DMACH_UART3 }, - { "s3c24xx-iis", "rx", (void *)DMACH_I2S_IN }, - { "s3c24xx-iis", "tx", (void *)DMACH_I2S_OUT }, -}; - -static struct s3c24xx_dma_platdata s3c2443_dma_platdata = { - .num_phy_channels = 6, - .channels = s3c2443_dma_channels, - .num_channels = DMACH_MAX, - .slave_map = s3c2443_dma_slave_map, - .slavecnt = ARRAY_SIZE(s3c2443_dma_slave_map), -}; - -struct platform_device s3c2443_device_dma = { - .name = "s3c2443-dma", - .id = 0, - .num_resources = ARRAY_SIZE(s3c2443_dma_resource), - .resource = s3c2443_dma_resource, - .dev = { - .dma_mask = &s3c24xx_device_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &s3c2443_dma_platdata, - }, -}; -#endif - -#if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2410) -void __init s3c2410_init_clocks(int xtal) -{ - s3c2410_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR); -} -#endif - -#ifdef CONFIG_CPU_S3C2412 -void __init s3c2412_init_clocks(int xtal) -{ - s3c2412_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR); -} -#endif - -#ifdef CONFIG_CPU_S3C2416 -void __init s3c2416_init_clocks(int xtal) -{ - s3c2443_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR); -} -#endif - -#if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2440) -void __init s3c2440_init_clocks(int xtal) -{ - s3c2410_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR); -} -#endif - -#if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2442) -void __init s3c2442_init_clocks(int xtal) -{ - s3c2410_common_clk_init(NULL, xtal, 2, S3C24XX_VA_CLKPWR); -} -#endif - -#ifdef CONFIG_CPU_S3C2443 -void __init s3c2443_init_clocks(int xtal) -{ - s3c2443_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR); -} -#endif - -#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2440) || \ - defined(CONFIG_CPU_S3C2442) -static struct resource s3c2410_dclk_resource[] = { - [0] = DEFINE_RES_MEM(0x56000084, 0x4), -}; - -static struct s3c2410_clk_platform_data s3c_clk_platform_data = { - .modify_misccr = s3c2410_modify_misccr, -}; - -struct platform_device s3c2410_device_dclk = { - .name = "s3c2410-dclk", - .id = 0, - .num_resources = ARRAY_SIZE(s3c2410_dclk_resource), - .resource = s3c2410_dclk_resource, - .dev = { - .platform_data = &s3c_clk_platform_data, - }, -}; -#endif diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h deleted file mode 100644 index 86826cafa15d..000000000000 --- a/arch/arm/mach-s3c24xx/common.h +++ /dev/null @@ -1,124 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Common Header for S3C24XX SoCs - */ - -#ifndef __ARCH_ARM_MACH_S3C24XX_COMMON_H -#define __ARCH_ARM_MACH_S3C24XX_COMMON_H __FILE__ - -#include -#include - -struct s3c2410_uartcfg; - -#ifdef CONFIG_CPU_S3C2410 -extern int s3c2410_init(void); -extern int s3c2410a_init(void); -extern void s3c2410_map_io(void); -extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no); -extern void s3c2410_init_clocks(int xtal); -extern void s3c2410_init_irq(void); -#else -#define s3c2410_init_clocks NULL -#define s3c2410_init_uarts NULL -#define s3c2410_map_io NULL -#define s3c2410_init NULL -#define s3c2410a_init NULL -#endif - -#ifdef CONFIG_CPU_S3C2412 -extern int s3c2412_init(void); -extern void s3c2412_map_io(void); -extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no); -extern void s3c2412_init_clocks(int xtal); -extern int s3c2412_baseclk_add(void); -extern void s3c2412_init_irq(void); -#else -#define s3c2412_init_clocks NULL -#define s3c2412_init_uarts NULL -#define s3c2412_map_io NULL -#define s3c2412_init NULL -#endif - -#ifdef CONFIG_CPU_S3C2416 -extern int s3c2416_init(void); -extern void s3c2416_map_io(void); -extern void s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no); -extern void s3c2416_init_clocks(int xtal); -extern int s3c2416_baseclk_add(void); -extern void s3c2416_init_irq(void); - -extern struct syscore_ops s3c2416_irq_syscore_ops; -#else -#define s3c2416_init_clocks NULL -#define s3c2416_init_uarts NULL -#define s3c2416_map_io NULL -#define s3c2416_init NULL -#endif - -#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) -extern void s3c244x_map_io(void); -extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no); -#else -#define s3c244x_init_uarts NULL -#endif - -#ifdef CONFIG_CPU_S3C2440 -extern int s3c2440_init(void); -extern void s3c2440_map_io(void); -extern void s3c2440_init_clocks(int xtal); -extern void s3c2440_init_irq(void); -#else -#define s3c2440_init NULL -#define s3c2440_map_io NULL -#endif - -#ifdef CONFIG_CPU_S3C2442 -extern int s3c2442_init(void); -extern void s3c2442_map_io(void); -extern void s3c2442_init_clocks(int xtal); -extern void s3c2442_init_irq(void); -#else -#define s3c2442_init NULL -#define s3c2442_map_io NULL -#endif - -#ifdef CONFIG_CPU_S3C2443 -extern int s3c2443_init(void); -extern void s3c2443_map_io(void); -extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no); -extern void s3c2443_init_clocks(int xtal); -extern int s3c2443_baseclk_add(void); -extern void s3c2443_init_irq(void); -#else -#define s3c2443_init_clocks NULL -#define s3c2443_init_uarts NULL -#define s3c2443_map_io NULL -#define s3c2443_init NULL -#endif - -extern struct syscore_ops s3c24xx_irq_syscore_ops; - -extern struct platform_device s3c2410_device_dma; -extern struct platform_device s3c2412_device_dma; -extern struct platform_device s3c2440_device_dma; -extern struct platform_device s3c2443_device_dma; - -extern struct platform_device s3c2410_device_dclk; - -enum samsung_timer_mode { - SAMSUNG_PWM0, - SAMSUNG_PWM1, - SAMSUNG_PWM2, - SAMSUNG_PWM3, - SAMSUNG_PWM4, -}; - -extern void __init samsung_set_timer_source(enum samsung_timer_mode event, - enum samsung_timer_mode source); -extern void __init samsung_timer_init(void); - -#endif /* __ARCH_ARM_MACH_S3C24XX_COMMON_H */ diff --git a/arch/arm/mach-s3c24xx/cpufreq-utils.c b/arch/arm/mach-s3c24xx/cpufreq-utils.c deleted file mode 100644 index 3bc374dd0b2d..000000000000 --- a/arch/arm/mach-s3c24xx/cpufreq-utils.c +++ /dev/null @@ -1,94 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (c) 2009 Simtec Electronics -// http://armlinux.simtec.co.uk/ -// Ben Dooks -// -// S3C24XX CPU Frequency scaling - utils for S3C2410/S3C2440/S3C2442 - -#include -#include -#include -#include -#include - -#include -#include - -#include - -#include "regs-mem.h" - -/** - * s3c2410_cpufreq_setrefresh - set SDRAM refresh value - * @cfg: The frequency configuration - * - * Set the SDRAM refresh value appropriately for the configured - * frequency. - */ -void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg) -{ - struct s3c_cpufreq_board *board = cfg->board; - unsigned long refresh; - unsigned long refval; - - /* Reduce both the refresh time (in ns) and the frequency (in MHz) - * down to ensure that we do not overflow 32 bit numbers. - * - * This should work for HCLK up to 133MHz and refresh period up - * to 30usec. - */ - - refresh = (cfg->freq.hclk / 100) * (board->refresh / 10); - refresh = DIV_ROUND_UP(refresh, (1000 * 1000)); /* apply scale */ - refresh = (1 << 11) + 1 - refresh; - - s3c_freq_dbg("%s: refresh value %lu\n", __func__, refresh); - - refval = __raw_readl(S3C2410_REFRESH); - refval &= ~((1 << 12) - 1); - refval |= refresh; - __raw_writel(refval, S3C2410_REFRESH); -} - -/** - * s3c2410_set_fvco - set the PLL value - * @cfg: The frequency configuration - */ -void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg) -{ - if (!IS_ERR(cfg->mpll)) - clk_set_rate(cfg->mpll, cfg->pll.frequency); -} - -#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) -u32 s3c2440_read_camdivn(void) -{ - return __raw_readl(S3C2440_CAMDIVN); -} - -void s3c2440_write_camdivn(u32 camdiv) -{ - __raw_writel(camdiv, S3C2440_CAMDIVN); -} -#endif - -u32 s3c24xx_read_clkdivn(void) -{ - return __raw_readl(S3C2410_CLKDIVN); -} - -void s3c24xx_write_clkdivn(u32 clkdiv) -{ - __raw_writel(clkdiv, S3C2410_CLKDIVN); -} - -u32 s3c24xx_read_mpllcon(void) -{ - return __raw_readl(S3C2410_MPLLCON); -} - -void s3c24xx_write_locktime(u32 locktime) -{ - return __raw_writel(locktime, S3C2410_LOCKTIME); -} diff --git a/arch/arm/mach-s3c24xx/fb-core.h b/arch/arm/mach-s3c24xx/fb-core.h deleted file mode 100644 index 1821e820262c..000000000000 --- a/arch/arm/mach-s3c24xx/fb-core.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2010 Samsung Electronics Co., Ltd. - * Pawel Osciak - * - * Samsung framebuffer driver core functions - */ -#ifndef __ASM_PLAT_FB_CORE_H -#define __ASM_PLAT_FB_CORE_H __FILE__ - -/* - * These functions are only for use with the core support code, such as - * the CPU-specific initialization code. - */ - -/* Re-define device name depending on support. */ -static inline void s3c_fb_setname(char *name) -{ -#ifdef CONFIG_S3C_DEV_FB - s3c_device_fb.name = name; -#endif -} - -#endif /* __ASM_PLAT_FB_CORE_H */ diff --git a/arch/arm/mach-s3c24xx/gta02.h b/arch/arm/mach-s3c24xx/gta02.h deleted file mode 100644 index d5610ba829a4..000000000000 --- a/arch/arm/mach-s3c24xx/gta02.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * GTA02 header - */ - -#ifndef __MACH_S3C24XX_GTA02_H -#define __MACH_S3C24XX_GTA02_H __FILE__ - -#include - -#define GTA02_GPIO_AUX_LED S3C2410_GPB(2) -#define GTA02_GPIO_USB_PULLUP S3C2410_GPB(9) -#define GTA02_GPIO_AUX_KEY S3C2410_GPF(6) -#define GTA02_GPIO_HOLD_KEY S3C2410_GPF(7) -#define GTA02_GPIO_AMP_SHUT S3C2410_GPJ(1) /* v2 + v3 + v4 only */ -#define GTA02_GPIO_HP_IN S3C2410_GPJ(2) /* v2 + v3 + v4 only */ - -#define GTA02_IRQ_PCF50633 IRQ_EINT9 - -#endif /* __MACH_S3C24XX_GTA02_H */ diff --git a/arch/arm/mach-s3c24xx/h1940-bluetooth.c b/arch/arm/mach-s3c24xx/h1940-bluetooth.c deleted file mode 100644 index 8533e7521b50..000000000000 --- a/arch/arm/mach-s3c24xx/h1940-bluetooth.c +++ /dev/null @@ -1,140 +0,0 @@ -// SPDX-License-Identifier: GPL-1.0+ -// -// Copyright (c) Arnaud Patard -// -// S3C2410 bluetooth "driver" - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "h1940.h" - -#define DRV_NAME "h1940-bt" - -/* Bluetooth control */ -static void h1940bt_enable(int on) -{ - if (on) { - /* Power on the chip */ - gpio_set_value(H1940_LATCH_BLUETOOTH_POWER, 1); - /* Reset the chip */ - mdelay(10); - - gpio_set_value(S3C2410_GPH(1), 1); - mdelay(10); - gpio_set_value(S3C2410_GPH(1), 0); - - h1940_led_blink_set(NULL, GPIO_LED_BLINK, NULL, NULL); - } - else { - gpio_set_value(S3C2410_GPH(1), 1); - mdelay(10); - gpio_set_value(S3C2410_GPH(1), 0); - mdelay(10); - gpio_set_value(H1940_LATCH_BLUETOOTH_POWER, 0); - - h1940_led_blink_set(NULL, GPIO_LED_NO_BLINK_LOW, NULL, NULL); - } -} - -static int h1940bt_set_block(void *data, bool blocked) -{ - h1940bt_enable(!blocked); - return 0; -} - -static const struct rfkill_ops h1940bt_rfkill_ops = { - .set_block = h1940bt_set_block, -}; - -static int h1940bt_probe(struct platform_device *pdev) -{ - struct rfkill *rfk; - int ret = 0; - - ret = gpio_request(S3C2410_GPH(1), dev_name(&pdev->dev)); - if (ret) { - dev_err(&pdev->dev, "could not get GPH1\n"); - return ret; - } - - ret = gpio_request(H1940_LATCH_BLUETOOTH_POWER, dev_name(&pdev->dev)); - if (ret) { - gpio_free(S3C2410_GPH(1)); - dev_err(&pdev->dev, "could not get BT_POWER\n"); - return ret; - } - - /* Configures BT serial port GPIOs */ - s3c_gpio_cfgpin(S3C2410_GPH(0), S3C2410_GPH0_nCTS0); - s3c_gpio_setpull(S3C2410_GPH(0), S3C_GPIO_PULL_NONE); - s3c_gpio_cfgpin(S3C2410_GPH(1), S3C2410_GPIO_OUTPUT); - s3c_gpio_setpull(S3C2410_GPH(1), S3C_GPIO_PULL_NONE); - s3c_gpio_cfgpin(S3C2410_GPH(2), S3C2410_GPH2_TXD0); - s3c_gpio_setpull(S3C2410_GPH(2), S3C_GPIO_PULL_NONE); - s3c_gpio_cfgpin(S3C2410_GPH(3), S3C2410_GPH3_RXD0); - s3c_gpio_setpull(S3C2410_GPH(3), S3C_GPIO_PULL_NONE); - - rfk = rfkill_alloc(DRV_NAME, &pdev->dev, RFKILL_TYPE_BLUETOOTH, - &h1940bt_rfkill_ops, NULL); - if (!rfk) { - ret = -ENOMEM; - goto err_rfk_alloc; - } - - ret = rfkill_register(rfk); - if (ret) - goto err_rfkill; - - platform_set_drvdata(pdev, rfk); - - return 0; - -err_rfkill: - rfkill_destroy(rfk); -err_rfk_alloc: - return ret; -} - -static int h1940bt_remove(struct platform_device *pdev) -{ - struct rfkill *rfk = platform_get_drvdata(pdev); - - platform_set_drvdata(pdev, NULL); - gpio_free(S3C2410_GPH(1)); - - if (rfk) { - rfkill_unregister(rfk); - rfkill_destroy(rfk); - } - rfk = NULL; - - h1940bt_enable(0); - - return 0; -} - - -static struct platform_driver h1940bt_driver = { - .driver = { - .name = DRV_NAME, - }, - .probe = h1940bt_probe, - .remove = h1940bt_remove, -}; - -module_platform_driver(h1940bt_driver); - -MODULE_AUTHOR("Arnaud Patard "); -MODULE_DESCRIPTION("Driver for the iPAQ H1940 bluetooth chip"); -MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-s3c24xx/h1940.h b/arch/arm/mach-s3c24xx/h1940.h deleted file mode 100644 index 5dfe9d10cd15..000000000000 --- a/arch/arm/mach-s3c24xx/h1940.h +++ /dev/null @@ -1,52 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2006 Ben Dooks - * - * Copyright (c) 2005 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks - * - * iPAQ H1940 series definitions - */ - -#ifndef __MACH_S3C24XX_H1940_H -#define __MACH_S3C24XX_H1940_H __FILE__ - -#define H1940_SUSPEND_CHECKSUM (0x30003ff8) -#define H1940_SUSPEND_RESUMEAT (0x30081000) -#define H1940_SUSPEND_CHECK (0x30080000) - -struct gpio_desc; - -extern void h1940_pm_return(void); -extern int h1940_led_blink_set(struct gpio_desc *desc, int state, - unsigned long *delay_on, - unsigned long *delay_off); - -#include - -#define H1940_LATCH_GPIO(x) (S3C_GPIO_END + (x)) - -/* SD layer latch */ - -#define H1940_LATCH_LCD_P0 H1940_LATCH_GPIO(0) -#define H1940_LATCH_LCD_P1 H1940_LATCH_GPIO(1) -#define H1940_LATCH_LCD_P2 H1940_LATCH_GPIO(2) -#define H1940_LATCH_LCD_P3 H1940_LATCH_GPIO(3) -#define H1940_LATCH_MAX1698_nSHUTDOWN H1940_LATCH_GPIO(4) -#define H1940_LATCH_LED_RED H1940_LATCH_GPIO(5) -#define H1940_LATCH_SDQ7 H1940_LATCH_GPIO(6) -#define H1940_LATCH_USB_DP H1940_LATCH_GPIO(7) - -/* CPU layer latch */ - -#define H1940_LATCH_UDA_POWER H1940_LATCH_GPIO(8) -#define H1940_LATCH_AUDIO_POWER H1940_LATCH_GPIO(9) -#define H1940_LATCH_SM803_ENABLE H1940_LATCH_GPIO(10) -#define H1940_LATCH_LCD_P4 H1940_LATCH_GPIO(11) -#define H1940_LATCH_SD_POWER H1940_LATCH_GPIO(12) -#define H1940_LATCH_BLUETOOTH_POWER H1940_LATCH_GPIO(13) -#define H1940_LATCH_LED_GREEN H1940_LATCH_GPIO(14) -#define H1940_LATCH_LED_FLASH H1940_LATCH_GPIO(15) - -#endif /* __MACH_S3C24XX_H1940_H */ diff --git a/arch/arm/mach-s3c24xx/include/mach/dma.h b/arch/arm/mach-s3c24xx/include/mach/dma.h deleted file mode 100644 index 25fc9c258fc1..000000000000 --- a/arch/arm/mach-s3c24xx/include/mach/dma.h +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2003-2006 Simtec Electronics - * Ben Dooks - * - * Samsung S3C24XX DMA support - */ - -#ifndef __ASM_ARCH_DMA_H -#define __ASM_ARCH_DMA_H __FILE__ - -#include - -/* We use `virtual` dma channels to hide the fact we have only a limited - * number of DMA channels, and not of all of them (dependent on the device) - * can be attached to any DMA source. We therefore let the DMA core handle - * the allocation of hardware channels to clients. -*/ - -enum dma_ch { - DMACH_XD0 = 0, - DMACH_XD1, - DMACH_SDI, - DMACH_SPI0, - DMACH_SPI1, - DMACH_UART0, - DMACH_UART1, - DMACH_UART2, - DMACH_TIMER, - DMACH_I2S_IN, - DMACH_I2S_OUT, - DMACH_PCM_IN, - DMACH_PCM_OUT, - DMACH_MIC_IN, - DMACH_USB_EP1, - DMACH_USB_EP2, - DMACH_USB_EP3, - DMACH_USB_EP4, - DMACH_UART0_SRC2, /* s3c2412 second uart sources */ - DMACH_UART1_SRC2, - DMACH_UART2_SRC2, - DMACH_UART3, /* s3c2443 has extra uart */ - DMACH_UART3_SRC2, - DMACH_SPI0_TX, /* s3c2443/2416/2450 hsspi0 */ - DMACH_SPI0_RX, /* s3c2443/2416/2450 hsspi0 */ - DMACH_SPI1_TX, /* s3c2443/2450 hsspi1 */ - DMACH_SPI1_RX, /* s3c2443/2450 hsspi1 */ - DMACH_MAX, /* the end entry */ -}; - -#endif /* __ASM_ARCH_DMA_H */ diff --git a/arch/arm/mach-s3c24xx/include/mach/gpio-samsung.h b/arch/arm/mach-s3c24xx/include/mach/gpio-samsung.h deleted file mode 100644 index f8a114891f16..000000000000 --- a/arch/arm/mach-s3c24xx/include/mach/gpio-samsung.h +++ /dev/null @@ -1,103 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks - * - * S3C2410 - GPIO lib support - */ - -/* some boards require extra gpio capacity to support external - * devices that need GPIO. - */ - -#ifndef GPIO_SAMSUNG_S3C24XX_H -#define GPIO_SAMSUNG_S3C24XX_H - -#include - -/* - * GPIO sizes for various SoCs: - * - * 2410 2412 2440 2443 2416 - * 2442 - * ---- ---- ---- ---- ---- - * A 23 22 25 16 27 - * B 11 11 11 11 11 - * C 16 16 16 16 16 - * D 16 16 16 16 16 - * E 16 16 16 16 16 - * F 8 8 8 8 8 - * G 16 16 16 16 8 - * H 11 11 11 15 15 - * J -- -- 13 16 -- - * K -- -- -- -- 16 - * L -- -- -- 15 14 - * M -- -- -- 2 2 - */ - -/* GPIO bank sizes */ - -#define S3C2410_GPIO_A_NR (32) -#define S3C2410_GPIO_B_NR (32) -#define S3C2410_GPIO_C_NR (32) -#define S3C2410_GPIO_D_NR (32) -#define S3C2410_GPIO_E_NR (32) -#define S3C2410_GPIO_F_NR (32) -#define S3C2410_GPIO_G_NR (32) -#define S3C2410_GPIO_H_NR (32) -#define S3C2410_GPIO_J_NR (32) /* technically 16. */ -#define S3C2410_GPIO_K_NR (32) /* technically 16. */ -#define S3C2410_GPIO_L_NR (32) /* technically 15. */ -#define S3C2410_GPIO_M_NR (32) /* technically 2. */ - -#if CONFIG_S3C_GPIO_SPACE != 0 -#error CONFIG_S3C_GPIO_SPACE cannot be nonzero at the moment -#endif - -#define S3C2410_GPIO_NEXT(__gpio) \ - ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 0) - -#ifndef __ASSEMBLY__ - -enum s3c_gpio_number { - S3C2410_GPIO_A_START = 0, - S3C2410_GPIO_B_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_A), - S3C2410_GPIO_C_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_B), - S3C2410_GPIO_D_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_C), - S3C2410_GPIO_E_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_D), - S3C2410_GPIO_F_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_E), - S3C2410_GPIO_G_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_F), - S3C2410_GPIO_H_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_G), - S3C2410_GPIO_J_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_H), - S3C2410_GPIO_K_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_J), - S3C2410_GPIO_L_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_K), - S3C2410_GPIO_M_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_L), -}; - -#endif /* __ASSEMBLY__ */ - -/* S3C2410 GPIO number definitions. */ - -#define S3C2410_GPA(_nr) (S3C2410_GPIO_A_START + (_nr)) -#define S3C2410_GPB(_nr) (S3C2410_GPIO_B_START + (_nr)) -#define S3C2410_GPC(_nr) (S3C2410_GPIO_C_START + (_nr)) -#define S3C2410_GPD(_nr) (S3C2410_GPIO_D_START + (_nr)) -#define S3C2410_GPE(_nr) (S3C2410_GPIO_E_START + (_nr)) -#define S3C2410_GPF(_nr) (S3C2410_GPIO_F_START + (_nr)) -#define S3C2410_GPG(_nr) (S3C2410_GPIO_G_START + (_nr)) -#define S3C2410_GPH(_nr) (S3C2410_GPIO_H_START + (_nr)) -#define S3C2410_GPJ(_nr) (S3C2410_GPIO_J_START + (_nr)) -#define S3C2410_GPK(_nr) (S3C2410_GPIO_K_START + (_nr)) -#define S3C2410_GPL(_nr) (S3C2410_GPIO_L_START + (_nr)) -#define S3C2410_GPM(_nr) (S3C2410_GPIO_M_START + (_nr)) - -#ifdef CONFIG_CPU_S3C244X -#define S3C_GPIO_END (S3C2410_GPJ(0) + 32) -#elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416) -#define S3C_GPIO_END (S3C2410_GPM(0) + 32) -#else -#define S3C_GPIO_END (S3C2410_GPH(0) + 32) -#endif - -#endif /* GPIO_SAMSUNG_S3C24XX_H */ diff --git a/arch/arm/mach-s3c24xx/include/mach/hardware.h b/arch/arm/mach-s3c24xx/include/mach/hardware.h deleted file mode 100644 index c732ea54984c..000000000000 --- a/arch/arm/mach-s3c24xx/include/mach/hardware.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2003 Simtec Electronics - * Ben Dooks - * - * S3C2410 - hardware - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg); - -#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-s3c24xx/include/mach/io.h b/arch/arm/mach-s3c24xx/include/mach/io.h deleted file mode 100644 index bcddf615adb6..000000000000 --- a/arch/arm/mach-s3c24xx/include/mach/io.h +++ /dev/null @@ -1,50 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * arch/arm/mach-s3c2410/include/mach/io.h - * from arch/arm/mach-rpc/include/mach/io.h - * - * Copyright (C) 1997 Russell King - * (C) 2003 Simtec Electronics -*/ - -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -#include - -/* - * ISA style IO, for each machine to sort out mappings for, - * if it implements it. We reserve two 16M regions for ISA, - * so the PC/104 can use separate addresses for 8-bit and - * 16-bit port I/O. - */ -#define PCIO_BASE S3C_ADDR(0x02000000) -#define IO_SPACE_LIMIT 0x00ffffff -#define S3C24XX_VA_ISA_WORD (PCIO_BASE) -#define S3C24XX_VA_ISA_BYTE (PCIO_BASE + 0x01000000) - -#ifdef CONFIG_ISA - -#define inb(p) readb(S3C24XX_VA_ISA_BYTE + (p)) -#define inw(p) readw(S3C24XX_VA_ISA_WORD + (p)) -#define inl(p) readl(S3C24XX_VA_ISA_WORD + (p)) - -#define outb(v,p) writeb((v), S3C24XX_VA_ISA_BYTE + (p)) -#define outw(v,p) writew((v), S3C24XX_VA_ISA_WORD + (p)) -#define outl(v,p) writel((v), S3C24XX_VA_ISA_WORD + (p)) - -#define insb(p,d,l) readsb(S3C24XX_VA_ISA_BYTE + (p),d,l) -#define insw(p,d,l) readsw(S3C24XX_VA_ISA_WORD + (p),d,l) -#define insl(p,d,l) readsl(S3C24XX_VA_ISA_WORD + (p),d,l) - -#define outsb(p,d,l) writesb(S3C24XX_VA_ISA_BYTE + (p),d,l) -#define outsw(p,d,l) writesw(S3C24XX_VA_ISA_WORD + (p),d,l) -#define outsl(p,d,l) writesl(S3C24XX_VA_ISA_WORD + (p),d,l) - -#else - -#define __io(x) (PCIO_BASE + (x)) - -#endif - -#endif diff --git a/arch/arm/mach-s3c24xx/include/mach/irqs.h b/arch/arm/mach-s3c24xx/include/mach/irqs.h deleted file mode 100644 index aaf3bae08b52..000000000000 --- a/arch/arm/mach-s3c24xx/include/mach/irqs.h +++ /dev/null @@ -1,213 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2003-2005 Simtec Electronics - * Ben Dooks - */ - - -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H __FILE__ - -/* we keep the first set of CPU IRQs out of the range of - * the ISA space, so that the PC104 has them to itself - * and we don't end up having to do horrible things to the - * standard ISA drivers.... - */ - -#define S3C2410_CPUIRQ_OFFSET (16) - -#define S3C2410_IRQ(x) ((x) + S3C2410_CPUIRQ_OFFSET) - -/* main cpu interrupts */ -#define IRQ_EINT0 S3C2410_IRQ(0) /* 16 */ -#define IRQ_EINT1 S3C2410_IRQ(1) -#define IRQ_EINT2 S3C2410_IRQ(2) -#define IRQ_EINT3 S3C2410_IRQ(3) -#define IRQ_EINT4t7 S3C2410_IRQ(4) /* 20 */ -#define IRQ_EINT8t23 S3C2410_IRQ(5) -#define IRQ_RESERVED6 S3C2410_IRQ(6) /* for s3c2410 */ -#define IRQ_CAM S3C2410_IRQ(6) /* for s3c2440,s3c2443 */ -#define IRQ_BATT_FLT S3C2410_IRQ(7) -#define IRQ_TICK S3C2410_IRQ(8) /* 24 */ -#define IRQ_WDT S3C2410_IRQ(9) /* WDT/AC97 for s3c2443 */ -#define IRQ_TIMER0 S3C2410_IRQ(10) -#define IRQ_TIMER1 S3C2410_IRQ(11) -#define IRQ_TIMER2 S3C2410_IRQ(12) -#define IRQ_TIMER3 S3C2410_IRQ(13) -#define IRQ_TIMER4 S3C2410_IRQ(14) -#define IRQ_UART2 S3C2410_IRQ(15) -#define IRQ_LCD S3C2410_IRQ(16) /* 32 */ -#define IRQ_DMA0 S3C2410_IRQ(17) /* IRQ_DMA for s3c2443 */ -#define IRQ_DMA1 S3C2410_IRQ(18) -#define IRQ_DMA2 S3C2410_IRQ(19) -#define IRQ_DMA3 S3C2410_IRQ(20) -#define IRQ_SDI S3C2410_IRQ(21) -#define IRQ_SPI0 S3C2410_IRQ(22) -#define IRQ_UART1 S3C2410_IRQ(23) -#define IRQ_RESERVED24 S3C2410_IRQ(24) /* 40 */ -#define IRQ_NFCON S3C2410_IRQ(24) /* for s3c2440 */ -#define IRQ_USBD S3C2410_IRQ(25) -#define IRQ_USBH S3C2410_IRQ(26) -#define IRQ_IIC S3C2410_IRQ(27) -#define IRQ_UART0 S3C2410_IRQ(28) /* 44 */ -#define IRQ_SPI1 S3C2410_IRQ(29) -#define IRQ_RTC S3C2410_IRQ(30) -#define IRQ_ADCPARENT S3C2410_IRQ(31) - -/* interrupts generated from the external interrupts sources */ -#define IRQ_EINT0_2412 S3C2410_IRQ(32) -#define IRQ_EINT1_2412 S3C2410_IRQ(33) -#define IRQ_EINT2_2412 S3C2410_IRQ(34) -#define IRQ_EINT3_2412 S3C2410_IRQ(35) -#define IRQ_EINT4 S3C2410_IRQ(36) /* 52 */ -#define IRQ_EINT5 S3C2410_IRQ(37) -#define IRQ_EINT6 S3C2410_IRQ(38) -#define IRQ_EINT7 S3C2410_IRQ(39) -#define IRQ_EINT8 S3C2410_IRQ(40) -#define IRQ_EINT9 S3C2410_IRQ(41) -#define IRQ_EINT10 S3C2410_IRQ(42) -#define IRQ_EINT11 S3C2410_IRQ(43) -#define IRQ_EINT12 S3C2410_IRQ(44) -#define IRQ_EINT13 S3C2410_IRQ(45) -#define IRQ_EINT14 S3C2410_IRQ(46) -#define IRQ_EINT15 S3C2410_IRQ(47) -#define IRQ_EINT16 S3C2410_IRQ(48) -#define IRQ_EINT17 S3C2410_IRQ(49) -#define IRQ_EINT18 S3C2410_IRQ(50) -#define IRQ_EINT19 S3C2410_IRQ(51) -#define IRQ_EINT20 S3C2410_IRQ(52) /* 68 */ -#define IRQ_EINT21 S3C2410_IRQ(53) -#define IRQ_EINT22 S3C2410_IRQ(54) -#define IRQ_EINT23 S3C2410_IRQ(55) - -#define IRQ_EINT_BIT(x) ((x) - IRQ_EINT4 + 4) -#define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x))) - -#define IRQ_LCD_FIFO S3C2410_IRQ(56) -#define IRQ_LCD_FRAME S3C2410_IRQ(57) - -/* IRQs for the interal UARTs, and ADC - * these need to be ordered in number of appearance in the - * SUBSRC mask register -*/ - -#define S3C2410_IRQSUB(x) S3C2410_IRQ((x)+58) - -#define IRQ_S3CUART_RX0 S3C2410_IRQSUB(0) /* 74 */ -#define IRQ_S3CUART_TX0 S3C2410_IRQSUB(1) -#define IRQ_S3CUART_ERR0 S3C2410_IRQSUB(2) - -#define IRQ_S3CUART_RX1 S3C2410_IRQSUB(3) /* 77 */ -#define IRQ_S3CUART_TX1 S3C2410_IRQSUB(4) -#define IRQ_S3CUART_ERR1 S3C2410_IRQSUB(5) - -#define IRQ_S3CUART_RX2 S3C2410_IRQSUB(6) /* 80 */ -#define IRQ_S3CUART_TX2 S3C2410_IRQSUB(7) -#define IRQ_S3CUART_ERR2 S3C2410_IRQSUB(8) - -#define IRQ_TC S3C2410_IRQSUB(9) -#define IRQ_ADC S3C2410_IRQSUB(10) - -/* extra irqs for s3c2412 */ - -#define IRQ_S3C2412_CFSDI S3C2410_IRQ(21) - -#define IRQ_S3C2412_SDI S3C2410_IRQSUB(13) -#define IRQ_S3C2412_CF S3C2410_IRQSUB(14) - - -#define IRQ_S3C2416_EINT8t15 S3C2410_IRQ(5) -#define IRQ_S3C2416_DMA S3C2410_IRQ(17) -#define IRQ_S3C2416_UART3 S3C2410_IRQ(18) -#define IRQ_S3C2416_SDI1 S3C2410_IRQ(20) -#define IRQ_S3C2416_SDI0 S3C2410_IRQ(21) - -#define IRQ_S3C2416_LCD2 S3C2410_IRQSUB(15) -#define IRQ_S3C2416_LCD3 S3C2410_IRQSUB(16) -#define IRQ_S3C2416_LCD4 S3C2410_IRQSUB(17) -#define IRQ_S3C2416_DMA0 S3C2410_IRQSUB(18) -#define IRQ_S3C2416_DMA1 S3C2410_IRQSUB(19) -#define IRQ_S3C2416_DMA2 S3C2410_IRQSUB(20) -#define IRQ_S3C2416_DMA3 S3C2410_IRQSUB(21) -#define IRQ_S3C2416_DMA4 S3C2410_IRQSUB(22) -#define IRQ_S3C2416_DMA5 S3C2410_IRQSUB(23) -#define IRQ_S32416_WDT S3C2410_IRQSUB(27) -#define IRQ_S32416_AC97 S3C2410_IRQSUB(28) - -/* second interrupt-register of s3c2416/s3c2450 */ - -#define S3C2416_IRQ(x) S3C2410_IRQ((x) + 58 + 29) -#define IRQ_S3C2416_2D S3C2416_IRQ(0) -#define IRQ_S3C2416_IIC1 S3C2416_IRQ(1) -#define IRQ_S3C2416_RESERVED2 S3C2416_IRQ(2) -#define IRQ_S3C2416_RESERVED3 S3C2416_IRQ(3) -#define IRQ_S3C2416_PCM0 S3C2416_IRQ(4) -#define IRQ_S3C2416_PCM1 S3C2416_IRQ(5) -#define IRQ_S3C2416_I2S0 S3C2416_IRQ(6) -#define IRQ_S3C2416_I2S1 S3C2416_IRQ(7) - -/* extra irqs for s3c2440 */ - -#define IRQ_S3C2440_CAM_C S3C2410_IRQSUB(11) /* S3C2443 too */ -#define IRQ_S3C2440_CAM_P S3C2410_IRQSUB(12) /* S3C2443 too */ -#define IRQ_S3C2440_WDT S3C2410_IRQSUB(13) -#define IRQ_S3C2440_AC97 S3C2410_IRQSUB(14) - -/* irqs for s3c2443 */ - -#define IRQ_S3C2443_DMA S3C2410_IRQ(17) /* IRQ_DMA1 */ -#define IRQ_S3C2443_UART3 S3C2410_IRQ(18) /* IRQ_DMA2 */ -#define IRQ_S3C2443_CFCON S3C2410_IRQ(19) /* IRQ_DMA3 */ -#define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */ -#define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */ - -#define IRQ_S3C2416_HSMMC0 S3C2410_IRQ(21) /* S3C2416/S3C2450 */ - -#define IRQ_HSMMC0 IRQ_S3C2416_HSMMC0 -#define IRQ_HSMMC1 IRQ_S3C2443_HSMMC - -#define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14) -#define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15) -#define IRQ_S3C2443_LCD3 S3C2410_IRQSUB(16) -#define IRQ_S3C2443_LCD4 S3C2410_IRQSUB(17) - -#define IRQ_S3C2443_DMA0 S3C2410_IRQSUB(18) -#define IRQ_S3C2443_DMA1 S3C2410_IRQSUB(19) -#define IRQ_S3C2443_DMA2 S3C2410_IRQSUB(20) -#define IRQ_S3C2443_DMA3 S3C2410_IRQSUB(21) -#define IRQ_S3C2443_DMA4 S3C2410_IRQSUB(22) -#define IRQ_S3C2443_DMA5 S3C2410_IRQSUB(23) - -/* UART3 */ -#define IRQ_S3C2443_RX3 S3C2410_IRQSUB(24) -#define IRQ_S3C2443_TX3 S3C2410_IRQSUB(25) -#define IRQ_S3C2443_ERR3 S3C2410_IRQSUB(26) - -#define IRQ_S3C2443_WDT S3C2410_IRQSUB(27) -#define IRQ_S3C2443_AC97 S3C2410_IRQSUB(28) - -#if defined(CONFIG_CPU_S3C2416) -#define NR_IRQS (IRQ_S3C2416_I2S1 + 1) -#else -#define NR_IRQS (IRQ_S3C2443_AC97 + 1) -#endif - -/* compatibility define. */ -#define IRQ_UART3 IRQ_S3C2443_UART3 -#define IRQ_S3CUART_RX3 IRQ_S3C2443_RX3 -#define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3 -#define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3 - -#define IRQ_LCD_VSYNC IRQ_S3C2443_LCD3 -#define IRQ_LCD_SYSTEM IRQ_S3C2443_LCD2 - -#ifdef CONFIG_CPU_S3C2440 -#define IRQ_S3C244X_AC97 IRQ_S3C2440_AC97 -#else -#define IRQ_S3C244X_AC97 IRQ_S3C2443_AC97 -#endif - -/* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */ -#define FIQ_START IRQ_EINT0 - -#endif /* __ASM_ARCH_IRQ_H */ diff --git a/arch/arm/mach-s3c24xx/include/mach/map.h b/arch/arm/mach-s3c24xx/include/mach/map.h deleted file mode 100644 index a20c9fd0d855..000000000000 --- a/arch/arm/mach-s3c24xx/include/mach/map.h +++ /dev/null @@ -1,159 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2003 Simtec Electronics - * Ben Dooks - * - * S3C2410 - Memory map definitions - */ - -#ifndef __ASM_ARCH_MAP_H -#define __ASM_ARCH_MAP_H - -#include -#include - -/* - * interrupt controller is the first thing we put in, to make - * the assembly code for the irq detection easier - */ -#define S3C2410_PA_IRQ (0x4A000000) -#define S3C24XX_SZ_IRQ SZ_1M - -/* memory controller registers */ -#define S3C2410_PA_MEMCTRL (0x48000000) -#define S3C24XX_SZ_MEMCTRL SZ_1M - -/* Timers */ -#define S3C2410_PA_TIMER (0x51000000) -#define S3C24XX_SZ_TIMER SZ_1M - -/* Clock and Power management */ -#define S3C24XX_SZ_CLKPWR SZ_1M - -/* USB Device port */ -#define S3C2410_PA_USBDEV (0x52000000) -#define S3C24XX_SZ_USBDEV SZ_1M - -/* Watchdog */ -#define S3C2410_PA_WATCHDOG (0x53000000) -#define S3C24XX_SZ_WATCHDOG SZ_1M - -/* Standard size definitions for peripheral blocks. */ - -#define S3C24XX_SZ_UART SZ_1M -#define S3C24XX_SZ_IIS SZ_1M -#define S3C24XX_SZ_ADC SZ_1M -#define S3C24XX_SZ_SPI SZ_1M -#define S3C24XX_SZ_SDI SZ_1M -#define S3C24XX_SZ_NAND SZ_1M -#define S3C24XX_SZ_GPIO SZ_1M - -/* USB host controller */ -#define S3C2410_PA_USBHOST (0x49000000) - -/* S3C2416/S3C2443/S3C2450 High-Speed USB Gadget */ -#define S3C2416_PA_HSUDC (0x49800000) -#define S3C2416_SZ_HSUDC (SZ_4K) - -/* DMA controller */ -#define S3C2410_PA_DMA (0x4B000000) -#define S3C24XX_SZ_DMA SZ_1M - -/* Clock and Power management */ -#define S3C2410_PA_CLKPWR (0x4C000000) - -/* LCD controller */ -#define S3C2410_PA_LCD (0x4D000000) -#define S3C24XX_SZ_LCD SZ_1M - -/* NAND flash controller */ -#define S3C2410_PA_NAND (0x4E000000) - -/* IIC hardware controller */ -#define S3C2410_PA_IIC (0x54000000) - -/* IIS controller */ -#define S3C2410_PA_IIS (0x55000000) - -/* RTC */ -#define S3C2410_PA_RTC (0x57000000) -#define S3C24XX_SZ_RTC SZ_1M - -/* ADC */ -#define S3C2410_PA_ADC (0x58000000) - -/* SPI */ -#define S3C2410_PA_SPI (0x59000000) -#define S3C2443_PA_SPI0 (0x52000000) -#define S3C2443_PA_SPI1 S3C2410_PA_SPI -#define S3C2410_SPI1 (0x20) -#define S3C2412_SPI1 (0x100) - -/* SDI */ -#define S3C2410_PA_SDI (0x5A000000) - -/* CAMIF */ -#define S3C2440_PA_CAMIF (0x4F000000) -#define S3C2440_SZ_CAMIF SZ_1M - -/* AC97 */ - -#define S3C2440_PA_AC97 (0x5B000000) -#define S3C2440_SZ_AC97 SZ_1M - -/* S3C2443/S3C2416 High-speed SD/MMC */ -#define S3C2443_PA_HSMMC (0x4A800000) -#define S3C2416_PA_HSMMC0 (0x4AC00000) - -#define S3C2443_PA_FB (0x4C800000) - -/* S3C2412 memory and IO controls */ -#define S3C2412_PA_SSMC (0x4F000000) - -#define S3C2412_PA_EBI (0x48800000) - -/* physical addresses of all the chip-select areas */ - -#define S3C2410_CS0 (0x00000000) -#define S3C2410_CS1 (0x08000000) -#define S3C2410_CS2 (0x10000000) -#define S3C2410_CS3 (0x18000000) -#define S3C2410_CS4 (0x20000000) -#define S3C2410_CS5 (0x28000000) -#define S3C2410_CS6 (0x30000000) -#define S3C2410_CS7 (0x38000000) - -#define S3C2410_SDRAM_PA (S3C2410_CS6) - -/* Use a single interface for common resources between S3C24XX cpus */ - -#define S3C24XX_PA_IRQ S3C2410_PA_IRQ -#define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL -#define S3C24XX_PA_DMA S3C2410_PA_DMA -#define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR -#define S3C24XX_PA_LCD S3C2410_PA_LCD -#define S3C24XX_PA_TIMER S3C2410_PA_TIMER -#define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV -#define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG -#define S3C24XX_PA_IIS S3C2410_PA_IIS -#define S3C24XX_PA_RTC S3C2410_PA_RTC -#define S3C24XX_PA_ADC S3C2410_PA_ADC -#define S3C24XX_PA_SPI S3C2410_PA_SPI -#define S3C24XX_PA_SPI1 (S3C2410_PA_SPI + S3C2410_SPI1) -#define S3C24XX_PA_SDI S3C2410_PA_SDI -#define S3C24XX_PA_NAND S3C2410_PA_NAND - -#define S3C_PA_FB S3C2443_PA_FB -#define S3C_PA_IIC S3C2410_PA_IIC -#define S3C_PA_USBHOST S3C2410_PA_USBHOST -#define S3C_PA_HSMMC0 S3C2416_PA_HSMMC0 -#define S3C_PA_HSMMC1 S3C2443_PA_HSMMC -#define S3C_PA_WDT S3C2410_PA_WATCHDOG -#define S3C_PA_NAND S3C24XX_PA_NAND - -#define S3C_PA_SPI0 S3C2443_PA_SPI0 -#define S3C_PA_SPI1 S3C2443_PA_SPI1 - -#define SAMSUNG_PA_TIMER S3C2410_PA_TIMER - -#endif /* __ASM_ARCH_MAP_H */ diff --git a/arch/arm/mach-s3c24xx/include/mach/pm-core.h b/arch/arm/mach-s3c24xx/include/mach/pm-core.h deleted file mode 100644 index a22b4a37ee57..000000000000 --- a/arch/arm/mach-s3c24xx/include/mach/pm-core.h +++ /dev/null @@ -1,96 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2008 Simtec Electronics - * Ben Dooks - * http://armlinux.simtec.co.uk/ - * - * S3C24xx - PM core support for arch/arm/plat-s3c/pm.c - */ - -#include -#include - -#include "regs-clock.h" -#include "regs-irq.h" -#include - -static inline void s3c_pm_debug_init_uart(void) -{ -#ifdef CONFIG_SAMSUNG_PM_DEBUG - unsigned long tmp = __raw_readl(S3C2410_CLKCON); - - /* re-start uart clocks */ - tmp |= S3C2410_CLKCON_UART0; - tmp |= S3C2410_CLKCON_UART1; - tmp |= S3C2410_CLKCON_UART2; - - __raw_writel(tmp, S3C2410_CLKCON); - udelay(10); -#endif -} - -static inline void s3c_pm_arch_prepare_irqs(void) -{ - __raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK); - __raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK); - - /* ack any outstanding external interrupts before we go to sleep */ - - __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND); - __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND); - __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND); - -} - -static inline void s3c_pm_arch_stop_clocks(void) -{ - __raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */ -} - -/* s3c2410_pm_show_resume_irqs - * - * print any IRQs asserted at resume time (ie, we woke from) -*/ -static inline void s3c_pm_show_resume_irqs(int start, unsigned long which, - unsigned long mask) -{ - int i; - - which &= ~mask; - - for (i = 0; i <= 31; i++) { - if (which & (1L< - * http://armlinux.simtec.co.uk/ - * - * S3C2410 clock register definitions - */ - -#ifndef __ASM_ARM_REGS_CLOCK -#define __ASM_ARM_REGS_CLOCK - -#include - -#define S3C2410_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR) - -#define S3C2410_PLLVAL(_m,_p,_s) ((_m) << 12 | ((_p) << 4) | ((_s))) - -#define S3C2410_LOCKTIME S3C2410_CLKREG(0x00) -#define S3C2410_MPLLCON S3C2410_CLKREG(0x04) -#define S3C2410_UPLLCON S3C2410_CLKREG(0x08) -#define S3C2410_CLKCON S3C2410_CLKREG(0x0C) -#define S3C2410_CLKSLOW S3C2410_CLKREG(0x10) -#define S3C2410_CLKDIVN S3C2410_CLKREG(0x14) - -#define S3C2410_CLKCON_IDLE (1<<2) -#define S3C2410_CLKCON_POWER (1<<3) -#define S3C2410_CLKCON_NAND (1<<4) -#define S3C2410_CLKCON_LCDC (1<<5) -#define S3C2410_CLKCON_USBH (1<<6) -#define S3C2410_CLKCON_USBD (1<<7) -#define S3C2410_CLKCON_PWMT (1<<8) -#define S3C2410_CLKCON_SDI (1<<9) -#define S3C2410_CLKCON_UART0 (1<<10) -#define S3C2410_CLKCON_UART1 (1<<11) -#define S3C2410_CLKCON_UART2 (1<<12) -#define S3C2410_CLKCON_GPIO (1<<13) -#define S3C2410_CLKCON_RTC (1<<14) -#define S3C2410_CLKCON_ADC (1<<15) -#define S3C2410_CLKCON_IIC (1<<16) -#define S3C2410_CLKCON_IIS (1<<17) -#define S3C2410_CLKCON_SPI (1<<18) - -#define S3C2410_CLKDIVN_PDIVN (1<<0) -#define S3C2410_CLKDIVN_HDIVN (1<<1) - -#define S3C2410_CLKSLOW_UCLK_OFF (1<<7) -#define S3C2410_CLKSLOW_MPLL_OFF (1<<5) -#define S3C2410_CLKSLOW_SLOW (1<<4) -#define S3C2410_CLKSLOW_SLOWVAL(x) (x) -#define S3C2410_CLKSLOW_GET_SLOWVAL(x) ((x) & 7) - -#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) - -/* extra registers */ -#define S3C2440_CAMDIVN S3C2410_CLKREG(0x18) - -#define S3C2440_CLKCON_CAMERA (1<<19) -#define S3C2440_CLKCON_AC97 (1<<20) - -#define S3C2440_CLKDIVN_PDIVN (1<<0) -#define S3C2440_CLKDIVN_HDIVN_MASK (3<<1) -#define S3C2440_CLKDIVN_HDIVN_1 (0<<1) -#define S3C2440_CLKDIVN_HDIVN_2 (1<<1) -#define S3C2440_CLKDIVN_HDIVN_4_8 (2<<1) -#define S3C2440_CLKDIVN_HDIVN_3_6 (3<<1) -#define S3C2440_CLKDIVN_UCLK (1<<3) - -#define S3C2440_CAMDIVN_CAMCLK_MASK (0xf<<0) -#define S3C2440_CAMDIVN_CAMCLK_SEL (1<<4) -#define S3C2440_CAMDIVN_HCLK3_HALF (1<<8) -#define S3C2440_CAMDIVN_HCLK4_HALF (1<<9) -#define S3C2440_CAMDIVN_DVSEN (1<<12) - -#define S3C2442_CAMDIVN_CAMCLK_DIV3 (1<<5) - -#endif /* CONFIG_CPU_S3C2440 or CONFIG_CPU_S3C2442 */ - -#if defined(CONFIG_CPU_S3C2412) - -#define S3C2412_OSCSET S3C2410_CLKREG(0x18) -#define S3C2412_CLKSRC S3C2410_CLKREG(0x1C) - -#define S3C2412_PLLCON_OFF (1<<20) - -#define S3C2412_CLKDIVN_PDIVN (1<<2) -#define S3C2412_CLKDIVN_HDIVN_MASK (3<<0) -#define S3C2412_CLKDIVN_ARMDIVN (1<<3) -#define S3C2412_CLKDIVN_DVSEN (1<<4) -#define S3C2412_CLKDIVN_HALFHCLK (1<<5) -#define S3C2412_CLKDIVN_USB48DIV (1<<6) -#define S3C2412_CLKDIVN_UARTDIV_MASK (15<<8) -#define S3C2412_CLKDIVN_UARTDIV_SHIFT (8) -#define S3C2412_CLKDIVN_I2SDIV_MASK (15<<12) -#define S3C2412_CLKDIVN_I2SDIV_SHIFT (12) -#define S3C2412_CLKDIVN_CAMDIV_MASK (15<<16) -#define S3C2412_CLKDIVN_CAMDIV_SHIFT (16) - -#define S3C2412_CLKCON_WDT (1<<28) -#define S3C2412_CLKCON_SPI (1<<27) -#define S3C2412_CLKCON_IIS (1<<26) -#define S3C2412_CLKCON_IIC (1<<25) -#define S3C2412_CLKCON_ADC (1<<24) -#define S3C2412_CLKCON_RTC (1<<23) -#define S3C2412_CLKCON_GPIO (1<<22) -#define S3C2412_CLKCON_UART2 (1<<21) -#define S3C2412_CLKCON_UART1 (1<<20) -#define S3C2412_CLKCON_UART0 (1<<19) -#define S3C2412_CLKCON_SDI (1<<18) -#define S3C2412_CLKCON_PWMT (1<<17) -#define S3C2412_CLKCON_USBD (1<<16) -#define S3C2412_CLKCON_CAMCLK (1<<15) -#define S3C2412_CLKCON_UARTCLK (1<<14) -/* missing 13 */ -#define S3C2412_CLKCON_USB_HOST48 (1<<12) -#define S3C2412_CLKCON_USB_DEV48 (1<<11) -#define S3C2412_CLKCON_HCLKdiv2 (1<<10) -#define S3C2412_CLKCON_HCLKx2 (1<<9) -#define S3C2412_CLKCON_SDRAM (1<<8) -/* missing 7 */ -#define S3C2412_CLKCON_USBH S3C2410_CLKCON_USBH -#define S3C2412_CLKCON_LCDC S3C2410_CLKCON_LCDC -#define S3C2412_CLKCON_NAND S3C2410_CLKCON_NAND -#define S3C2412_CLKCON_DMA3 (1<<3) -#define S3C2412_CLKCON_DMA2 (1<<2) -#define S3C2412_CLKCON_DMA1 (1<<1) -#define S3C2412_CLKCON_DMA0 (1<<0) - -/* clock sourec controls */ - -#define S3C2412_CLKSRC_EXTCLKDIV_MASK (7 << 0) -#define S3C2412_CLKSRC_EXTCLKDIV_SHIFT (0) -#define S3C2412_CLKSRC_MDIVCLK_EXTCLKDIV (1<<3) -#define S3C2412_CLKSRC_MSYSCLK_MPLL (1<<4) -#define S3C2412_CLKSRC_USYSCLK_UPLL (1<<5) -#define S3C2412_CLKSRC_UARTCLK_MPLL (1<<8) -#define S3C2412_CLKSRC_I2SCLK_MPLL (1<<9) -#define S3C2412_CLKSRC_USBCLK_HCLK (1<<10) -#define S3C2412_CLKSRC_CAMCLK_HCLK (1<<11) -#define S3C2412_CLKSRC_UREFCLK_EXTCLK (1<<12) -#define S3C2412_CLKSRC_EREFCLK_EXTCLK (1<<14) - -#endif /* CONFIG_CPU_S3C2412 */ - -#define S3C2416_CLKDIV2 S3C2410_CLKREG(0x28) - -#endif /* __ASM_ARM_REGS_CLOCK */ diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h b/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h deleted file mode 100644 index 51827d5577b6..000000000000 --- a/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h +++ /dev/null @@ -1,608 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2003-2004 Simtec Electronics - * http://www.simtec.co.uk/products/SWLINUX/ - * - * S3C2410 GPIO register definitions - */ - - -#ifndef __ASM_ARCH_REGS_GPIO_H -#define __ASM_ARCH_REGS_GPIO_H - -#include - -#define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80) - -/* general configuration options */ - -#define S3C2410_GPIO_LEAVE (0xFFFFFFFF) -#define S3C2410_GPIO_INPUT (0xFFFFFFF0) /* not available on A */ -#define S3C2410_GPIO_OUTPUT (0xFFFFFFF1) -#define S3C2410_GPIO_IRQ (0xFFFFFFF2) /* not available for all */ -#define S3C2410_GPIO_SFN2 (0xFFFFFFF2) /* bank A => addr/cs/nand */ -#define S3C2410_GPIO_SFN3 (0xFFFFFFF3) /* not available on A */ - -/* register address for the GPIO registers. - * S3C24XX_GPIOREG2 is for the second set of registers in the - * GPIO which move between s3c2410 and s3c2412 type systems */ - -#define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO) -#define S3C24XX_GPIOREG2(x) ((x) + S3C24XX_VA_GPIO2) - - -/* configure GPIO ports A..G */ - -/* port A - S3C2410: 22bits, zero in bit X makes pin X output - * 1 makes port special function, this is default -*/ -#define S3C2410_GPACON S3C2410_GPIOREG(0x00) -#define S3C2410_GPADAT S3C2410_GPIOREG(0x04) - -#define S3C2410_GPA0_ADDR0 (1<<0) -#define S3C2410_GPA1_ADDR16 (1<<1) -#define S3C2410_GPA2_ADDR17 (1<<2) -#define S3C2410_GPA3_ADDR18 (1<<3) -#define S3C2410_GPA4_ADDR19 (1<<4) -#define S3C2410_GPA5_ADDR20 (1<<5) -#define S3C2410_GPA6_ADDR21 (1<<6) -#define S3C2410_GPA7_ADDR22 (1<<7) -#define S3C2410_GPA8_ADDR23 (1<<8) -#define S3C2410_GPA9_ADDR24 (1<<9) -#define S3C2410_GPA10_ADDR25 (1<<10) -#define S3C2410_GPA11_ADDR26 (1<<11) -#define S3C2410_GPA12_nGCS1 (1<<12) -#define S3C2410_GPA13_nGCS2 (1<<13) -#define S3C2410_GPA14_nGCS3 (1<<14) -#define S3C2410_GPA15_nGCS4 (1<<15) -#define S3C2410_GPA16_nGCS5 (1<<16) -#define S3C2410_GPA17_CLE (1<<17) -#define S3C2410_GPA18_ALE (1<<18) -#define S3C2410_GPA19_nFWE (1<<19) -#define S3C2410_GPA20_nFRE (1<<20) -#define S3C2410_GPA21_nRSTOUT (1<<21) -#define S3C2410_GPA22_nFCE (1<<22) - -/* 0x08 and 0x0c are reserved on S3C2410 */ - -/* S3C2410: - * GPB is 10 IO pins, each configured by 2 bits each in GPBCON. - * 00 = input, 01 = output, 10=special function, 11=reserved - - * bit 0,1 = pin 0, 2,3= pin 1... - * - * CPBUP = pull up resistor control, 1=disabled, 0=enabled -*/ - -#define S3C2410_GPBCON S3C2410_GPIOREG(0x10) -#define S3C2410_GPBDAT S3C2410_GPIOREG(0x14) -#define S3C2410_GPBUP S3C2410_GPIOREG(0x18) - -/* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */ - -#define S3C2410_GPB0_TOUT0 (0x02 << 0) - -#define S3C2410_GPB1_TOUT1 (0x02 << 2) - -#define S3C2410_GPB2_TOUT2 (0x02 << 4) - -#define S3C2410_GPB3_TOUT3 (0x02 << 6) - -#define S3C2410_GPB4_TCLK0 (0x02 << 8) -#define S3C2410_GPB4_MASK (0x03 << 8) - -#define S3C2410_GPB5_nXBACK (0x02 << 10) -#define S3C2443_GPB5_XBACK (0x03 << 10) - -#define S3C2410_GPB6_nXBREQ (0x02 << 12) -#define S3C2443_GPB6_XBREQ (0x03 << 12) - -#define S3C2410_GPB7_nXDACK1 (0x02 << 14) -#define S3C2443_GPB7_XDACK1 (0x03 << 14) - -#define S3C2410_GPB8_nXDREQ1 (0x02 << 16) - -#define S3C2410_GPB9_nXDACK0 (0x02 << 18) -#define S3C2443_GPB9_XDACK0 (0x03 << 18) - -#define S3C2410_GPB10_nXDRE0 (0x02 << 20) -#define S3C2443_GPB10_XDREQ0 (0x03 << 20) - -#define S3C2410_GPB_PUPDIS(x) (1<<(x)) - -/* Port C consits of 16 GPIO/Special function - * - * almost identical setup to port b, but the special functions are mostly - * to do with the video system's sync/etc. -*/ - -#define S3C2410_GPCCON S3C2410_GPIOREG(0x20) -#define S3C2410_GPCDAT S3C2410_GPIOREG(0x24) -#define S3C2410_GPCUP S3C2410_GPIOREG(0x28) -#define S3C2410_GPC0_LEND (0x02 << 0) -#define S3C2410_GPC1_VCLK (0x02 << 2) -#define S3C2410_GPC2_VLINE (0x02 << 4) -#define S3C2410_GPC3_VFRAME (0x02 << 6) -#define S3C2410_GPC4_VM (0x02 << 8) -#define S3C2410_GPC5_LCDVF0 (0x02 << 10) -#define S3C2410_GPC6_LCDVF1 (0x02 << 12) -#define S3C2410_GPC7_LCDVF2 (0x02 << 14) -#define S3C2410_GPC8_VD0 (0x02 << 16) -#define S3C2410_GPC9_VD1 (0x02 << 18) -#define S3C2410_GPC10_VD2 (0x02 << 20) -#define S3C2410_GPC11_VD3 (0x02 << 22) -#define S3C2410_GPC12_VD4 (0x02 << 24) -#define S3C2410_GPC13_VD5 (0x02 << 26) -#define S3C2410_GPC14_VD6 (0x02 << 28) -#define S3C2410_GPC15_VD7 (0x02 << 30) -#define S3C2410_GPC_PUPDIS(x) (1<<(x)) - -/* - * S3C2410: Port D consists of 16 GPIO/Special function - * - * almost identical setup to port b, but the special functions are mostly - * to do with the video system's data. - * - * almost identical setup to port c -*/ - -#define S3C2410_GPDCON S3C2410_GPIOREG(0x30) -#define S3C2410_GPDDAT S3C2410_GPIOREG(0x34) -#define S3C2410_GPDUP S3C2410_GPIOREG(0x38) - -#define S3C2410_GPD0_VD8 (0x02 << 0) -#define S3C2442_GPD0_nSPICS1 (0x03 << 0) - -#define S3C2410_GPD1_VD9 (0x02 << 2) -#define S3C2442_GPD1_SPICLK1 (0x03 << 2) - -#define S3C2410_GPD2_VD10 (0x02 << 4) - -#define S3C2410_GPD3_VD11 (0x02 << 6) - -#define S3C2410_GPD4_VD12 (0x02 << 8) - -#define S3C2410_GPD5_VD13 (0x02 << 10) - -#define S3C2410_GPD6_VD14 (0x02 << 12) - -#define S3C2410_GPD7_VD15 (0x02 << 14) - -#define S3C2410_GPD8_VD16 (0x02 << 16) -#define S3C2440_GPD8_SPIMISO1 (0x03 << 16) - -#define S3C2410_GPD9_VD17 (0x02 << 18) -#define S3C2440_GPD9_SPIMOSI1 (0x03 << 18) - -#define S3C2410_GPD10_VD18 (0x02 << 20) -#define S3C2440_GPD10_SPICLK1 (0x03 << 20) - -#define S3C2410_GPD11_VD19 (0x02 << 22) - -#define S3C2410_GPD12_VD20 (0x02 << 24) - -#define S3C2410_GPD13_VD21 (0x02 << 26) - -#define S3C2410_GPD14_VD22 (0x02 << 28) -#define S3C2410_GPD14_nSS1 (0x03 << 28) - -#define S3C2410_GPD15_VD23 (0x02 << 30) -#define S3C2410_GPD15_nSS0 (0x03 << 30) - -#define S3C2410_GPD_PUPDIS(x) (1<<(x)) - -/* S3C2410: - * Port E consists of 16 GPIO/Special function - * - * again, the same as port B, but dealing with I2S, SDI, and - * more miscellaneous functions - * - * GPIO / interrupt inputs -*/ - -#define S3C2410_GPECON S3C2410_GPIOREG(0x40) -#define S3C2410_GPEDAT S3C2410_GPIOREG(0x44) -#define S3C2410_GPEUP S3C2410_GPIOREG(0x48) - -#define S3C2410_GPE0_I2SLRCK (0x02 << 0) -#define S3C2443_GPE0_AC_nRESET (0x03 << 0) -#define S3C2410_GPE0_MASK (0x03 << 0) - -#define S3C2410_GPE1_I2SSCLK (0x02 << 2) -#define S3C2443_GPE1_AC_SYNC (0x03 << 2) -#define S3C2410_GPE1_MASK (0x03 << 2) - -#define S3C2410_GPE2_CDCLK (0x02 << 4) -#define S3C2443_GPE2_AC_BITCLK (0x03 << 4) - -#define S3C2410_GPE3_I2SSDI (0x02 << 6) -#define S3C2443_GPE3_AC_SDI (0x03 << 6) -#define S3C2410_GPE3_nSS0 (0x03 << 6) -#define S3C2410_GPE3_MASK (0x03 << 6) - -#define S3C2410_GPE4_I2SSDO (0x02 << 8) -#define S3C2443_GPE4_AC_SDO (0x03 << 8) -#define S3C2410_GPE4_I2SSDI (0x03 << 8) -#define S3C2410_GPE4_MASK (0x03 << 8) - -#define S3C2410_GPE5_SDCLK (0x02 << 10) -#define S3C2443_GPE5_SD1_CLK (0x02 << 10) -#define S3C2443_GPE5_AC_BITCLK (0x03 << 10) - -#define S3C2410_GPE6_SDCMD (0x02 << 12) -#define S3C2443_GPE6_SD1_CMD (0x02 << 12) -#define S3C2443_GPE6_AC_SDI (0x03 << 12) - -#define S3C2410_GPE7_SDDAT0 (0x02 << 14) -#define S3C2443_GPE5_SD1_DAT0 (0x02 << 14) -#define S3C2443_GPE7_AC_SDO (0x03 << 14) - -#define S3C2410_GPE8_SDDAT1 (0x02 << 16) -#define S3C2443_GPE8_SD1_DAT1 (0x02 << 16) -#define S3C2443_GPE8_AC_SYNC (0x03 << 16) - -#define S3C2410_GPE9_SDDAT2 (0x02 << 18) -#define S3C2443_GPE9_SD1_DAT2 (0x02 << 18) -#define S3C2443_GPE9_AC_nRESET (0x03 << 18) - -#define S3C2410_GPE10_SDDAT3 (0x02 << 20) -#define S3C2443_GPE10_SD1_DAT3 (0x02 << 20) - -#define S3C2410_GPE11_SPIMISO0 (0x02 << 22) - -#define S3C2410_GPE12_SPIMOSI0 (0x02 << 24) - -#define S3C2410_GPE13_SPICLK0 (0x02 << 26) - -#define S3C2410_GPE14_IICSCL (0x02 << 28) -#define S3C2410_GPE14_MASK (0x03 << 28) - -#define S3C2410_GPE15_IICSDA (0x02 << 30) -#define S3C2410_GPE15_MASK (0x03 << 30) - -#define S3C2440_GPE0_ACSYNC (0x03 << 0) -#define S3C2440_GPE1_ACBITCLK (0x03 << 2) -#define S3C2440_GPE2_ACRESET (0x03 << 4) -#define S3C2440_GPE3_ACIN (0x03 << 6) -#define S3C2440_GPE4_ACOUT (0x03 << 8) - -#define S3C2410_GPE_PUPDIS(x) (1<<(x)) - -/* S3C2410: - * Port F consists of 8 GPIO/Special function - * - * GPIO / interrupt inputs - * - * GPFCON has 2 bits for each of the input pins on port F - * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 undefined - * - * pull up works like all other ports. - * - * GPIO/serial/misc pins -*/ - -#define S3C2410_GPFCON S3C2410_GPIOREG(0x50) -#define S3C2410_GPFDAT S3C2410_GPIOREG(0x54) -#define S3C2410_GPFUP S3C2410_GPIOREG(0x58) - -#define S3C2410_GPF0_EINT0 (0x02 << 0) -#define S3C2410_GPF1_EINT1 (0x02 << 2) -#define S3C2410_GPF2_EINT2 (0x02 << 4) -#define S3C2410_GPF3_EINT3 (0x02 << 6) -#define S3C2410_GPF4_EINT4 (0x02 << 8) -#define S3C2410_GPF5_EINT5 (0x02 << 10) -#define S3C2410_GPF6_EINT6 (0x02 << 12) -#define S3C2410_GPF7_EINT7 (0x02 << 14) -#define S3C2410_GPF_PUPDIS(x) (1<<(x)) - -/* S3C2410: - * Port G consists of 8 GPIO/IRQ/Special function - * - * GPGCON has 2 bits for each of the input pins on port G - * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func - * - * pull up works like all other ports. -*/ - -#define S3C2410_GPGCON S3C2410_GPIOREG(0x60) -#define S3C2410_GPGDAT S3C2410_GPIOREG(0x64) -#define S3C2410_GPGUP S3C2410_GPIOREG(0x68) - -#define S3C2410_GPG0_EINT8 (0x02 << 0) - -#define S3C2410_GPG1_EINT9 (0x02 << 2) - -#define S3C2410_GPG2_EINT10 (0x02 << 4) -#define S3C2410_GPG2_nSS0 (0x03 << 4) - -#define S3C2410_GPG3_EINT11 (0x02 << 6) -#define S3C2410_GPG3_nSS1 (0x03 << 6) - -#define S3C2410_GPG4_EINT12 (0x02 << 8) -#define S3C2410_GPG4_LCDPWREN (0x03 << 8) -#define S3C2443_GPG4_LCDPWRDN (0x03 << 8) - -#define S3C2410_GPG5_EINT13 (0x02 << 10) -#define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */ - -#define S3C2410_GPG6_EINT14 (0x02 << 12) -#define S3C2410_GPG6_SPIMOSI1 (0x03 << 12) - -#define S3C2410_GPG7_EINT15 (0x02 << 14) -#define S3C2410_GPG7_SPICLK1 (0x03 << 14) - -#define S3C2410_GPG8_EINT16 (0x02 << 16) - -#define S3C2410_GPG9_EINT17 (0x02 << 18) - -#define S3C2410_GPG10_EINT18 (0x02 << 20) - -#define S3C2410_GPG11_EINT19 (0x02 << 22) -#define S3C2410_GPG11_TCLK1 (0x03 << 22) -#define S3C2443_GPG11_CF_nIREQ (0x03 << 22) - -#define S3C2410_GPG12_EINT20 (0x02 << 24) -#define S3C2410_GPG12_XMON (0x03 << 24) -#define S3C2442_GPG12_nSPICS0 (0x03 << 24) -#define S3C2443_GPG12_nINPACK (0x03 << 24) - -#define S3C2410_GPG13_EINT21 (0x02 << 26) -#define S3C2410_GPG13_nXPON (0x03 << 26) -#define S3C2443_GPG13_CF_nREG (0x03 << 26) - -#define S3C2410_GPG14_EINT22 (0x02 << 28) -#define S3C2410_GPG14_YMON (0x03 << 28) -#define S3C2443_GPG14_CF_RESET (0x03 << 28) - -#define S3C2410_GPG15_EINT23 (0x02 << 30) -#define S3C2410_GPG15_nYPON (0x03 << 30) -#define S3C2443_GPG15_CF_PWR (0x03 << 30) - -#define S3C2410_GPG_PUPDIS(x) (1<<(x)) - -/* Port H consists of11 GPIO/serial/Misc pins - * - * GPHCON has 2 bits for each of the input pins on port H - * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func - * - * pull up works like all other ports. -*/ - -#define S3C2410_GPHCON S3C2410_GPIOREG(0x70) -#define S3C2410_GPHDAT S3C2410_GPIOREG(0x74) -#define S3C2410_GPHUP S3C2410_GPIOREG(0x78) - -#define S3C2410_GPH0_nCTS0 (0x02 << 0) -#define S3C2416_GPH0_TXD0 (0x02 << 0) - -#define S3C2410_GPH1_nRTS0 (0x02 << 2) -#define S3C2416_GPH1_RXD0 (0x02 << 2) - -#define S3C2410_GPH2_TXD0 (0x02 << 4) -#define S3C2416_GPH2_TXD1 (0x02 << 4) - -#define S3C2410_GPH3_RXD0 (0x02 << 6) -#define S3C2416_GPH3_RXD1 (0x02 << 6) - -#define S3C2410_GPH4_TXD1 (0x02 << 8) -#define S3C2416_GPH4_TXD2 (0x02 << 8) - -#define S3C2410_GPH5_RXD1 (0x02 << 10) -#define S3C2416_GPH5_RXD2 (0x02 << 10) - -#define S3C2410_GPH6_TXD2 (0x02 << 12) -#define S3C2416_GPH6_TXD3 (0x02 << 12) -#define S3C2410_GPH6_nRTS1 (0x03 << 12) -#define S3C2416_GPH6_nRTS2 (0x03 << 12) - -#define S3C2410_GPH7_RXD2 (0x02 << 14) -#define S3C2416_GPH7_RXD3 (0x02 << 14) -#define S3C2410_GPH7_nCTS1 (0x03 << 14) -#define S3C2416_GPH7_nCTS2 (0x03 << 14) - -#define S3C2410_GPH8_UCLK (0x02 << 16) -#define S3C2416_GPH8_nCTS0 (0x02 << 16) - -#define S3C2410_GPH9_CLKOUT0 (0x02 << 18) -#define S3C2442_GPH9_nSPICS0 (0x03 << 18) -#define S3C2416_GPH9_nRTS0 (0x02 << 18) - -#define S3C2410_GPH10_CLKOUT1 (0x02 << 20) -#define S3C2416_GPH10_nCTS1 (0x02 << 20) - -#define S3C2416_GPH11_nRTS1 (0x02 << 22) - -#define S3C2416_GPH12_EXTUARTCLK (0x02 << 24) - -#define S3C2416_GPH13_CLKOUT0 (0x02 << 26) - -#define S3C2416_GPH14_CLKOUT1 (0x02 << 28) - -/* The S3C2412 and S3C2413 move the GPJ register set to after - * GPH, which means all registers after 0x80 are now offset by 0x10 - * for the 2412/2413 from the 2410/2440/2442 -*/ - -/* - * Port J consists of 13 GPIO/Camera pins. GPJCON has 2 bits - * for each of the pins on port J. - * 00 - input, 01 output, 10 - camera - * - * Pull up works like all other ports. - */ - -#define S3C2413_GPJCON S3C2410_GPIOREG(0x80) -#define S3C2413_GPJDAT S3C2410_GPIOREG(0x84) -#define S3C2413_GPJUP S3C2410_GPIOREG(0x88) -#define S3C2413_GPJSLPCON S3C2410_GPIOREG(0x8C) - -/* S3C2443 and above */ -#define S3C2440_GPJCON S3C2410_GPIOREG(0xD0) -#define S3C2440_GPJDAT S3C2410_GPIOREG(0xD4) -#define S3C2440_GPJUP S3C2410_GPIOREG(0xD8) - -#define S3C2443_GPKCON S3C2410_GPIOREG(0xE0) -#define S3C2443_GPKDAT S3C2410_GPIOREG(0xE4) -#define S3C2443_GPKUP S3C2410_GPIOREG(0xE8) - -#define S3C2443_GPLCON S3C2410_GPIOREG(0xF0) -#define S3C2443_GPLDAT S3C2410_GPIOREG(0xF4) -#define S3C2443_GPLUP S3C2410_GPIOREG(0xF8) - -#define S3C2443_GPMCON S3C2410_GPIOREG(0x100) -#define S3C2443_GPMDAT S3C2410_GPIOREG(0x104) -#define S3C2443_GPMUP S3C2410_GPIOREG(0x108) - -/* miscellaneous control */ -#define S3C2410_MISCCR S3C2410_GPIOREG(0x80) - -/* see clock.h for dclk definitions */ - -/* pullup control on databus */ -#define S3C2410_MISCCR_SPUCR_HEN (0<<0) -#define S3C2410_MISCCR_SPUCR_HDIS (1<<0) -#define S3C2410_MISCCR_SPUCR_LEN (0<<1) -#define S3C2410_MISCCR_SPUCR_LDIS (1<<1) - -#define S3C2410_MISCCR_USBDEV (0<<3) -#define S3C2410_MISCCR_USBHOST (1<<3) - -#define S3C2410_MISCCR_CLK0_MPLL (0<<4) -#define S3C2410_MISCCR_CLK0_UPLL (1<<4) -#define S3C2410_MISCCR_CLK0_FCLK (2<<4) -#define S3C2410_MISCCR_CLK0_HCLK (3<<4) -#define S3C2410_MISCCR_CLK0_PCLK (4<<4) -#define S3C2410_MISCCR_CLK0_DCLK0 (5<<4) -#define S3C2410_MISCCR_CLK0_MASK (7<<4) - -#define S3C2412_MISCCR_CLK0_RTC (2<<4) - -#define S3C2410_MISCCR_CLK1_MPLL (0<<8) -#define S3C2410_MISCCR_CLK1_UPLL (1<<8) -#define S3C2410_MISCCR_CLK1_FCLK (2<<8) -#define S3C2410_MISCCR_CLK1_HCLK (3<<8) -#define S3C2410_MISCCR_CLK1_PCLK (4<<8) -#define S3C2410_MISCCR_CLK1_DCLK1 (5<<8) -#define S3C2410_MISCCR_CLK1_MASK (7<<8) - -#define S3C2412_MISCCR_CLK1_CLKsrc (0<<8) - -#define S3C2410_MISCCR_USBSUSPND0 (1<<12) -#define S3C2416_MISCCR_SEL_SUSPND (1<<12) -#define S3C2410_MISCCR_USBSUSPND1 (1<<13) - -#define S3C2410_MISCCR_nRSTCON (1<<16) - -#define S3C2410_MISCCR_nEN_SCLK0 (1<<17) -#define S3C2410_MISCCR_nEN_SCLK1 (1<<18) -#define S3C2410_MISCCR_nEN_SCLKE (1<<19) /* not 2412 */ -#define S3C2410_MISCCR_SDSLEEP (7<<17) - -#define S3C2416_MISCCR_FLT_I2C (1<<24) -#define S3C2416_MISCCR_HSSPI_EN2 (1<<31) - -/* external interrupt control... */ -/* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7 - * S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15 - * S3C2410_EXTINT2 -> irq sense control for EINT16..EINT23 - * - * note S3C2410_EXTINT2 has filtering options for EINT16..EINT23 - * - * Samsung datasheet p9-25 -*/ -#define S3C2410_EXTINT0 S3C2410_GPIOREG(0x88) -#define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C) -#define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90) - -#define S3C24XX_EXTINT0 S3C24XX_GPIOREG2(0x88) -#define S3C24XX_EXTINT1 S3C24XX_GPIOREG2(0x8C) -#define S3C24XX_EXTINT2 S3C24XX_GPIOREG2(0x90) - -/* interrupt filtering control for EINT16..EINT23 */ -#define S3C2410_EINFLT0 S3C2410_GPIOREG(0x94) -#define S3C2410_EINFLT1 S3C2410_GPIOREG(0x98) -#define S3C2410_EINFLT2 S3C2410_GPIOREG(0x9C) -#define S3C2410_EINFLT3 S3C2410_GPIOREG(0xA0) - -#define S3C24XX_EINFLT0 S3C24XX_GPIOREG2(0x94) -#define S3C24XX_EINFLT1 S3C24XX_GPIOREG2(0x98) -#define S3C24XX_EINFLT2 S3C24XX_GPIOREG2(0x9C) -#define S3C24XX_EINFLT3 S3C24XX_GPIOREG2(0xA0) - -/* values for interrupt filtering */ -#define S3C2410_EINTFLT_PCLK (0x00) -#define S3C2410_EINTFLT_EXTCLK (1<<7) -#define S3C2410_EINTFLT_WIDTHMSK(x) ((x) & 0x3f) - -/* removed EINTxxxx defs from here, not meant for this */ - -/* GSTATUS have miscellaneous information in them - * - * These move between s3c2410 and s3c2412 style systems. - */ - -#define S3C2410_GSTATUS0 S3C2410_GPIOREG(0x0AC) -#define S3C2410_GSTATUS1 S3C2410_GPIOREG(0x0B0) -#define S3C2410_GSTATUS2 S3C2410_GPIOREG(0x0B4) -#define S3C2410_GSTATUS3 S3C2410_GPIOREG(0x0B8) -#define S3C2410_GSTATUS4 S3C2410_GPIOREG(0x0BC) - -#define S3C2412_GSTATUS0 S3C2410_GPIOREG(0x0BC) -#define S3C2412_GSTATUS1 S3C2410_GPIOREG(0x0C0) -#define S3C2412_GSTATUS2 S3C2410_GPIOREG(0x0C4) -#define S3C2412_GSTATUS3 S3C2410_GPIOREG(0x0C8) -#define S3C2412_GSTATUS4 S3C2410_GPIOREG(0x0CC) - -#define S3C24XX_GSTATUS0 S3C24XX_GPIOREG2(0x0AC) -#define S3C24XX_GSTATUS1 S3C24XX_GPIOREG2(0x0B0) -#define S3C24XX_GSTATUS2 S3C24XX_GPIOREG2(0x0B4) -#define S3C24XX_GSTATUS3 S3C24XX_GPIOREG2(0x0B8) -#define S3C24XX_GSTATUS4 S3C24XX_GPIOREG2(0x0BC) - -#define S3C2410_GSTATUS0_nWAIT (1<<3) -#define S3C2410_GSTATUS0_NCON (1<<2) -#define S3C2410_GSTATUS0_RnB (1<<1) -#define S3C2410_GSTATUS0_nBATTFLT (1<<0) - -#define S3C2410_GSTATUS1_IDMASK (0xffff0000) -#define S3C2410_GSTATUS1_2410 (0x32410000) -#define S3C2410_GSTATUS1_2412 (0x32412001) -#define S3C2410_GSTATUS1_2416 (0x32416003) -#define S3C2410_GSTATUS1_2440 (0x32440000) -#define S3C2410_GSTATUS1_2442 (0x32440aaa) -/* some 2416 CPUs report this value also */ -#define S3C2410_GSTATUS1_2450 (0x32450003) - -#define S3C2410_GSTATUS2_WTRESET (1<<2) -#define S3C2410_GSTATUS2_OFFRESET (1<<1) -#define S3C2410_GSTATUS2_PONRESET (1<<0) - -/* 2412/2413 sleep configuration registers */ - -#define S3C2412_GPBSLPCON S3C2410_GPIOREG(0x1C) -#define S3C2412_GPCSLPCON S3C2410_GPIOREG(0x2C) -#define S3C2412_GPDSLPCON S3C2410_GPIOREG(0x3C) -#define S3C2412_GPFSLPCON S3C2410_GPIOREG(0x5C) -#define S3C2412_GPGSLPCON S3C2410_GPIOREG(0x6C) -#define S3C2412_GPHSLPCON S3C2410_GPIOREG(0x7C) - -/* definitions for each pin bit */ -#define S3C2412_GPIO_SLPCON_LOW ( 0x00 ) -#define S3C2412_GPIO_SLPCON_HIGH ( 0x01 ) -#define S3C2412_GPIO_SLPCON_IN ( 0x02 ) -#define S3C2412_GPIO_SLPCON_PULL ( 0x03 ) - -#define S3C2412_SLPCON_LOW(x) ( 0x00 << ((x) * 2)) -#define S3C2412_SLPCON_HIGH(x) ( 0x01 << ((x) * 2)) -#define S3C2412_SLPCON_IN(x) ( 0x02 << ((x) * 2)) -#define S3C2412_SLPCON_PULL(x) ( 0x03 << ((x) * 2)) -#define S3C2412_SLPCON_EINT(x) ( 0x02 << ((x) * 2)) /* only IRQ pins */ -#define S3C2412_SLPCON_MASK(x) ( 0x03 << ((x) * 2)) - -#define S3C2412_SLPCON_ALL_LOW (0x0) -#define S3C2412_SLPCON_ALL_HIGH (0x11111111 | 0x44444444) -#define S3C2412_SLPCON_ALL_IN (0x22222222 | 0x88888888) -#define S3C2412_SLPCON_ALL_PULL (0x33333333) - -#endif /* __ASM_ARCH_REGS_GPIO_H */ - diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-irq.h b/arch/arm/mach-s3c24xx/include/mach/regs-irq.h deleted file mode 100644 index 2921b48c56b2..000000000000 --- a/arch/arm/mach-s3c24xx/include/mach/regs-irq.h +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2003 Simtec Electronics - * http://www.simtec.co.uk/products/SWLINUX/ - */ - - -#ifndef ___ASM_ARCH_REGS_IRQ_H -#define ___ASM_ARCH_REGS_IRQ_H - -#include - -/* interrupt controller */ - -#define S3C2410_IRQREG(x) ((x) + S3C24XX_VA_IRQ) -#define S3C2410_EINTREG(x) ((x) + S3C24XX_VA_GPIO) -#define S3C24XX_EINTREG(x) ((x) + S3C24XX_VA_GPIO2) - -#define S3C2410_SRCPND S3C2410_IRQREG(0x000) -#define S3C2410_INTMOD S3C2410_IRQREG(0x004) -#define S3C2410_INTMSK S3C2410_IRQREG(0x008) -#define S3C2410_PRIORITY S3C2410_IRQREG(0x00C) -#define S3C2410_INTPND S3C2410_IRQREG(0x010) -#define S3C2410_INTOFFSET S3C2410_IRQREG(0x014) -#define S3C2410_SUBSRCPND S3C2410_IRQREG(0x018) -#define S3C2410_INTSUBMSK S3C2410_IRQREG(0x01C) - -#define S3C2416_PRIORITY_MODE1 S3C2410_IRQREG(0x030) -#define S3C2416_PRIORITY_UPDATE1 S3C2410_IRQREG(0x034) -#define S3C2416_SRCPND2 S3C2410_IRQREG(0x040) -#define S3C2416_INTMOD2 S3C2410_IRQREG(0x044) -#define S3C2416_INTMSK2 S3C2410_IRQREG(0x048) -#define S3C2416_INTPND2 S3C2410_IRQREG(0x050) -#define S3C2416_INTOFFSET2 S3C2410_IRQREG(0x054) -#define S3C2416_PRIORITY_MODE2 S3C2410_IRQREG(0x070) -#define S3C2416_PRIORITY_UPDATE2 S3C2410_IRQREG(0x074) - -/* mask: 0=enable, 1=disable - * 1 bit EINT, 4=EINT4, 23=EINT23 - * EINT0,1,2,3 are not handled here. -*/ - -#define S3C2410_EINTMASK S3C2410_EINTREG(0x0A4) -#define S3C2410_EINTPEND S3C2410_EINTREG(0X0A8) -#define S3C2412_EINTMASK S3C2410_EINTREG(0x0B4) -#define S3C2412_EINTPEND S3C2410_EINTREG(0X0B8) - -#define S3C24XX_EINTMASK S3C24XX_EINTREG(0x0A4) -#define S3C24XX_EINTPEND S3C24XX_EINTREG(0X0A8) - -#endif /* ___ASM_ARCH_REGS_IRQ_H */ diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2443-clock.h b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2443-clock.h deleted file mode 100644 index fefef7233f4b..000000000000 --- a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2443-clock.h +++ /dev/null @@ -1,238 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2007 Simtec Electronics - * Ben Dooks - * http://armlinux.simtec.co.uk/ - * - * S3C2443 clock register definitions - */ - -#ifndef __ASM_ARM_REGS_S3C2443_CLOCK -#define __ASM_ARM_REGS_S3C2443_CLOCK - -#include -#include - -#define S3C2443_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR) - -#define S3C2443_PLLCON_MDIVSHIFT 16 -#define S3C2443_PLLCON_PDIVSHIFT 8 -#define S3C2443_PLLCON_SDIVSHIFT 0 -#define S3C2443_PLLCON_MDIVMASK ((1<<(1+(23-16)))-1) -#define S3C2443_PLLCON_PDIVMASK ((1<<(1+(9-8)))-1) -#define S3C2443_PLLCON_SDIVMASK (3) - -#define S3C2443_MPLLCON S3C2443_CLKREG(0x10) -#define S3C2443_EPLLCON S3C2443_CLKREG(0x18) -#define S3C2443_CLKSRC S3C2443_CLKREG(0x20) -#define S3C2443_CLKDIV0 S3C2443_CLKREG(0x24) -#define S3C2443_CLKDIV1 S3C2443_CLKREG(0x28) -#define S3C2443_HCLKCON S3C2443_CLKREG(0x30) -#define S3C2443_PCLKCON S3C2443_CLKREG(0x34) -#define S3C2443_SCLKCON S3C2443_CLKREG(0x38) -#define S3C2443_PWRMODE S3C2443_CLKREG(0x40) -#define S3C2443_SWRST S3C2443_CLKREG(0x44) -#define S3C2443_BUSPRI0 S3C2443_CLKREG(0x50) -#define S3C2443_SYSID S3C2443_CLKREG(0x5C) -#define S3C2443_PWRCFG S3C2443_CLKREG(0x60) -#define S3C2443_RSTCON S3C2443_CLKREG(0x64) -#define S3C2443_PHYCTRL S3C2443_CLKREG(0x80) -#define S3C2443_PHYPWR S3C2443_CLKREG(0x84) -#define S3C2443_URSTCON S3C2443_CLKREG(0x88) -#define S3C2443_UCLKCON S3C2443_CLKREG(0x8C) - -#define S3C2443_PLLCON_OFF (1<<24) - -#define S3C2443_CLKSRC_EPLLREF_XTAL (2<<7) -#define S3C2443_CLKSRC_EPLLREF_EXTCLK (3<<7) -#define S3C2443_CLKSRC_EPLLREF_MPLLREF (0<<7) -#define S3C2443_CLKSRC_EPLLREF_MPLLREF2 (1<<7) -#define S3C2443_CLKSRC_EPLLREF_MASK (3<<7) - -#define S3C2443_CLKSRC_EXTCLK_DIV (1<<3) - -#define S3C2443_CLKDIV0_HALF_HCLK (1<<3) -#define S3C2443_CLKDIV0_HALF_PCLK (1<<2) - -#define S3C2443_CLKDIV0_HCLKDIV_MASK (3<<0) - -#define S3C2443_CLKDIV0_EXTDIV_MASK (3<<6) -#define S3C2443_CLKDIV0_EXTDIV_SHIFT (6) - -#define S3C2443_CLKDIV0_PREDIV_MASK (3<<4) -#define S3C2443_CLKDIV0_PREDIV_SHIFT (4) - -#define S3C2416_CLKDIV0_ARMDIV_MASK (7 << 9) -#define S3C2443_CLKDIV0_ARMDIV_MASK (15<<9) -#define S3C2443_CLKDIV0_ARMDIV_SHIFT (9) -#define S3C2443_CLKDIV0_ARMDIV_1 (0<<9) -#define S3C2443_CLKDIV0_ARMDIV_2 (8<<9) -#define S3C2443_CLKDIV0_ARMDIV_3 (2<<9) -#define S3C2443_CLKDIV0_ARMDIV_4 (9<<9) -#define S3C2443_CLKDIV0_ARMDIV_6 (10<<9) -#define S3C2443_CLKDIV0_ARMDIV_8 (11<<9) -#define S3C2443_CLKDIV0_ARMDIV_12 (13<<9) -#define S3C2443_CLKDIV0_ARMDIV_16 (15<<9) - -/* S3C2443_CLKDIV1 removed, only used in clock.c code */ - -#define S3C2443_CLKCON_NAND - -#define S3C2443_HCLKCON_DMA0 (1<<0) -#define S3C2443_HCLKCON_DMA1 (1<<1) -#define S3C2443_HCLKCON_DMA2 (1<<2) -#define S3C2443_HCLKCON_DMA3 (1<<3) -#define S3C2443_HCLKCON_DMA4 (1<<4) -#define S3C2443_HCLKCON_DMA5 (1<<5) -#define S3C2443_HCLKCON_CAMIF (1<<8) -#define S3C2443_HCLKCON_LCDC (1<<9) -#define S3C2443_HCLKCON_USBH (1<<11) -#define S3C2443_HCLKCON_USBD (1<<12) -#define S3C2416_HCLKCON_HSMMC0 (1<<15) -#define S3C2443_HCLKCON_HSMMC (1<<16) -#define S3C2443_HCLKCON_CFC (1<<17) -#define S3C2443_HCLKCON_SSMC (1<<18) -#define S3C2443_HCLKCON_DRAMC (1<<19) - -#define S3C2443_PCLKCON_UART0 (1<<0) -#define S3C2443_PCLKCON_UART1 (1<<1) -#define S3C2443_PCLKCON_UART2 (1<<2) -#define S3C2443_PCLKCON_UART3 (1<<3) -#define S3C2443_PCLKCON_IIC (1<<4) -#define S3C2443_PCLKCON_SDI (1<<5) -#define S3C2443_PCLKCON_HSSPI (1<<6) -#define S3C2443_PCLKCON_ADC (1<<7) -#define S3C2443_PCLKCON_AC97 (1<<8) -#define S3C2443_PCLKCON_IIS (1<<9) -#define S3C2443_PCLKCON_PWMT (1<<10) -#define S3C2443_PCLKCON_WDT (1<<11) -#define S3C2443_PCLKCON_RTC (1<<12) -#define S3C2443_PCLKCON_GPIO (1<<13) -#define S3C2443_PCLKCON_SPI0 (1<<14) -#define S3C2443_PCLKCON_SPI1 (1<<15) - -#define S3C2443_SCLKCON_DDRCLK (1<<16) -#define S3C2443_SCLKCON_SSMCCLK (1<<15) -#define S3C2443_SCLKCON_HSSPICLK (1<<14) -#define S3C2443_SCLKCON_HSMMCCLK_EXT (1<<13) -#define S3C2443_SCLKCON_HSMMCCLK_EPLL (1<<12) -#define S3C2443_SCLKCON_CAMCLK (1<<11) -#define S3C2443_SCLKCON_DISPCLK (1<<10) -#define S3C2443_SCLKCON_I2SCLK (1<<9) -#define S3C2443_SCLKCON_UARTCLK (1<<8) -#define S3C2443_SCLKCON_USBHOST (1<<1) - -#define S3C2443_PWRCFG_SLEEP (1<<15) - -#define S3C2443_PWRCFG_USBPHY (1 << 4) - -#define S3C2443_URSTCON_FUNCRST (1 << 2) -#define S3C2443_URSTCON_PHYRST (1 << 0) - -#define S3C2443_PHYCTRL_CLKSEL (1 << 3) -#define S3C2443_PHYCTRL_EXTCLK (1 << 2) -#define S3C2443_PHYCTRL_PLLSEL (1 << 1) -#define S3C2443_PHYCTRL_DSPORT (1 << 0) - -#define S3C2443_PHYPWR_COMMON_ON (1 << 31) -#define S3C2443_PHYPWR_ANALOG_PD (1 << 4) -#define S3C2443_PHYPWR_PLL_REFCLK (1 << 3) -#define S3C2443_PHYPWR_XO_ON (1 << 2) -#define S3C2443_PHYPWR_PLL_PWRDN (1 << 1) -#define S3C2443_PHYPWR_FSUSPEND (1 << 0) - -#define S3C2443_UCLKCON_DETECT_VBUS (1 << 31) -#define S3C2443_UCLKCON_FUNC_CLKEN (1 << 2) -#define S3C2443_UCLKCON_TCLKEN (1 << 0) - -#include - -static inline unsigned int -s3c2443_get_mpll(unsigned int pllval, unsigned int baseclk) -{ - unsigned int mdiv, pdiv, sdiv; - uint64_t fvco; - - mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT; - pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT; - sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT; - - mdiv &= S3C2443_PLLCON_MDIVMASK; - pdiv &= S3C2443_PLLCON_PDIVMASK; - sdiv &= S3C2443_PLLCON_SDIVMASK; - - fvco = (uint64_t)baseclk * (2 * (mdiv + 8)); - do_div(fvco, pdiv << sdiv); - - return (unsigned int)fvco; -} - -static inline unsigned int -s3c2443_get_epll(unsigned int pllval, unsigned int baseclk) -{ - unsigned int mdiv, pdiv, sdiv; - uint64_t fvco; - - mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT; - pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT; - sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT; - - mdiv &= S3C2443_PLLCON_MDIVMASK; - pdiv &= S3C2443_PLLCON_PDIVMASK; - sdiv &= S3C2443_PLLCON_SDIVMASK; - - fvco = (uint64_t)baseclk * (mdiv + 8); - do_div(fvco, (pdiv + 2) << sdiv); - - return (unsigned int)fvco; -} - -static inline void s3c_hsudc_init_phy(void) -{ - u32 cfg; - - cfg = readl(S3C2443_PWRCFG) | S3C2443_PWRCFG_USBPHY; - writel(cfg, S3C2443_PWRCFG); - - cfg = readl(S3C2443_URSTCON); - cfg |= (S3C2443_URSTCON_FUNCRST | S3C2443_URSTCON_PHYRST); - writel(cfg, S3C2443_URSTCON); - mdelay(1); - - cfg = readl(S3C2443_URSTCON); - cfg &= ~(S3C2443_URSTCON_FUNCRST | S3C2443_URSTCON_PHYRST); - writel(cfg, S3C2443_URSTCON); - - cfg = readl(S3C2443_PHYCTRL); - cfg &= ~(S3C2443_PHYCTRL_CLKSEL | S3C2443_PHYCTRL_DSPORT); - cfg |= (S3C2443_PHYCTRL_EXTCLK | S3C2443_PHYCTRL_PLLSEL); - writel(cfg, S3C2443_PHYCTRL); - - cfg = readl(S3C2443_PHYPWR); - cfg &= ~(S3C2443_PHYPWR_FSUSPEND | S3C2443_PHYPWR_PLL_PWRDN | - S3C2443_PHYPWR_XO_ON | S3C2443_PHYPWR_PLL_REFCLK | - S3C2443_PHYPWR_ANALOG_PD); - cfg |= S3C2443_PHYPWR_COMMON_ON; - writel(cfg, S3C2443_PHYPWR); - - cfg = readl(S3C2443_UCLKCON); - cfg |= (S3C2443_UCLKCON_DETECT_VBUS | S3C2443_UCLKCON_FUNC_CLKEN | - S3C2443_UCLKCON_TCLKEN); - writel(cfg, S3C2443_UCLKCON); -} - -static inline void s3c_hsudc_uninit_phy(void) -{ - u32 cfg; - - cfg = readl(S3C2443_PWRCFG) & ~S3C2443_PWRCFG_USBPHY; - writel(cfg, S3C2443_PWRCFG); - - writel(S3C2443_PHYPWR_FSUSPEND, S3C2443_PHYPWR); - - cfg = readl(S3C2443_UCLKCON) & ~S3C2443_UCLKCON_FUNC_CLKEN; - writel(cfg, S3C2443_UCLKCON); -} - -#endif /* __ASM_ARM_REGS_S3C2443_CLOCK */ - diff --git a/arch/arm/mach-s3c24xx/include/mach/rtc-core.h b/arch/arm/mach-s3c24xx/include/mach/rtc-core.h deleted file mode 100644 index 88510333b96b..000000000000 --- a/arch/arm/mach-s3c24xx/include/mach/rtc-core.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2011 Heiko Stuebner - * - * Samsung RTC Controller core functions - */ - -#ifndef __RTC_CORE_H -#define __RTC_CORE_H __FILE__ - -/* These functions are only for use with the core support code, such as - * the cpu specific initialisation code - */ - -extern struct platform_device s3c_device_rtc; - -/* re-define device name depending on support. */ -static inline void s3c_rtc_setname(char *name) -{ - s3c_device_rtc.name = name; -} - -#endif /* __RTC_CORE_H */ diff --git a/arch/arm/mach-s3c24xx/include/mach/s3c2412.h b/arch/arm/mach-s3c24xx/include/mach/s3c2412.h deleted file mode 100644 index 1ae369c81beb..000000000000 --- a/arch/arm/mach-s3c24xx/include/mach/s3c2412.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2008 Simtec Electronics - * Ben Dooks - * http://armlinux.simtec.co.uk/ - */ - -#ifndef __ARCH_ARM_MACH_S3C24XX_S3C2412_H -#define __ARCH_ARM_MACH_S3C24XX_S3C2412_H __FILE__ - -#include - -#define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x)) -#define S3C2412_EBIREG(x) (S3C2412_VA_EBI + (x)) - -#define S3C2412_SSMCREG(x) (S3C2412_VA_SSMC + (x)) -#define S3C2412_SSMC(x, o) (S3C2412_SSMCREG((x * 0x20) + (o))) - -#define S3C2412_REFRESH S3C2412_MEMREG(0x10) - -#define S3C2412_EBI_BANKCFG S3C2412_EBIREG(0x4) - -#define S3C2412_SSMC_BANK(x) S3C2412_SSMC(x, 0x0) - -#endif /* __ARCH_ARM_MACH_S3C24XX_S3C2412_H */ diff --git a/arch/arm/mach-s3c24xx/iotiming-s3c2410.c b/arch/arm/mach-s3c24xx/iotiming-s3c2410.c deleted file mode 100644 index 5d85c259f328..000000000000 --- a/arch/arm/mach-s3c24xx/iotiming-s3c2410.c +++ /dev/null @@ -1,472 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (c) 2006-2009 Simtec Electronics -// http://armlinux.simtec.co.uk/ -// Ben Dooks -// -// S3C24XX CPU Frequency scaling - IO timing for S3C2410/S3C2440/S3C2442 - -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include - -#include "regs-mem.h" - -#define print_ns(x) ((x) / 10), ((x) % 10) - -/** - * s3c2410_print_timing - print bank timing data for debug purposes - * @pfx: The prefix to put on the output - * @timings: The timing inforamtion to print. -*/ -static void s3c2410_print_timing(const char *pfx, - struct s3c_iotimings *timings) -{ - struct s3c2410_iobank_timing *bt; - int bank; - - for (bank = 0; bank < MAX_BANKS; bank++) { - bt = timings->bank[bank].io_2410; - if (!bt) - continue; - - printk(KERN_DEBUG "%s %d: Tacs=%d.%d, Tcos=%d.%d, Tacc=%d.%d, " - "Tcoh=%d.%d, Tcah=%d.%d\n", pfx, bank, - print_ns(bt->tacs), - print_ns(bt->tcos), - print_ns(bt->tacc), - print_ns(bt->tcoh), - print_ns(bt->tcah)); - } -} - -/** - * bank_reg - convert bank number to pointer to the control register. - * @bank: The IO bank number. - */ -static inline void __iomem *bank_reg(unsigned int bank) -{ - return S3C2410_BANKCON0 + (bank << 2); -} - -/** - * bank_is_io - test whether bank is used for IO - * @bankcon: The bank control register. - * - * This is a simplistic test to see if any BANKCON[x] is not an IO - * bank. It currently does not take into account whether BWSCON has - * an illegal width-setting in it, or if the pin connected to nCS[x] - * is actually being handled as a chip-select. - */ -static inline int bank_is_io(unsigned long bankcon) -{ - return !(bankcon & S3C2410_BANKCON_SDRAM); -} - -/** - * to_div - convert cycle time to divisor - * @cyc: The cycle time, in 10ths of nanoseconds. - * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds. - * - * Convert the given cycle time into the divisor to use to obtain it from - * HCLK. -*/ -static inline unsigned int to_div(unsigned int cyc, unsigned int hclk_tns) -{ - if (cyc == 0) - return 0; - - return DIV_ROUND_UP(cyc, hclk_tns); -} - -/** - * calc_0124 - calculate divisor control for divisors that do /0, /1. /2 and /4 - * @cyc: The cycle time, in 10ths of nanoseconds. - * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds. - * @v: Pointer to register to alter. - * @shift: The shift to get to the control bits. - * - * Calculate the divisor, and turn it into the correct control bits to - * set in the result, @v. - */ -static unsigned int calc_0124(unsigned int cyc, unsigned long hclk_tns, - unsigned long *v, int shift) -{ - unsigned int div = to_div(cyc, hclk_tns); - unsigned long val; - - s3c_freq_iodbg("%s: cyc=%d, hclk=%lu, shift=%d => div %d\n", - __func__, cyc, hclk_tns, shift, div); - - switch (div) { - case 0: - val = 0; - break; - case 1: - val = 1; - break; - case 2: - val = 2; - break; - case 3: - case 4: - val = 3; - break; - default: - return -1; - } - - *v |= val << shift; - return 0; -} - -static int calc_tacp(unsigned int cyc, unsigned long hclk, unsigned long *v) -{ - /* Currently no support for Tacp calculations. */ - return 0; -} - -/** - * calc_tacc - calculate divisor control for tacc. - * @cyc: The cycle time, in 10ths of nanoseconds. - * @nwait_en: IS nWAIT enabled for this bank. - * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds. - * @v: Pointer to register to alter. - * - * Calculate the divisor control for tACC, taking into account whether - * the bank has nWAIT enabled. The result is used to modify the value - * pointed to by @v. -*/ -static int calc_tacc(unsigned int cyc, int nwait_en, - unsigned long hclk_tns, unsigned long *v) -{ - unsigned int div = to_div(cyc, hclk_tns); - unsigned long val; - - s3c_freq_iodbg("%s: cyc=%u, nwait=%d, hclk=%lu => div=%u\n", - __func__, cyc, nwait_en, hclk_tns, div); - - /* if nWait enabled on an bank, Tacc must be at-least 4 cycles. */ - if (nwait_en && div < 4) - div = 4; - - switch (div) { - case 0: - val = 0; - break; - - case 1: - case 2: - case 3: - case 4: - val = div - 1; - break; - - case 5: - case 6: - val = 4; - break; - - case 7: - case 8: - val = 5; - break; - - case 9: - case 10: - val = 6; - break; - - case 11: - case 12: - case 13: - case 14: - val = 7; - break; - - default: - return -1; - } - - *v |= val << 8; - return 0; -} - -/** - * s3c2410_calc_bank - calculate bank timing information - * @cfg: The configuration we need to calculate for. - * @bt: The bank timing information. - * - * Given the cycle timine for a bank @bt, calculate the new BANKCON - * setting for the @cfg timing. This updates the timing information - * ready for the cpu frequency change. - */ -static int s3c2410_calc_bank(struct s3c_cpufreq_config *cfg, - struct s3c2410_iobank_timing *bt) -{ - unsigned long hclk = cfg->freq.hclk_tns; - unsigned long res; - int ret; - - res = bt->bankcon; - res &= (S3C2410_BANKCON_SDRAM | S3C2410_BANKCON_PMC16); - - /* tacp: 2,3,4,5 */ - /* tcah: 0,1,2,4 */ - /* tcoh: 0,1,2,4 */ - /* tacc: 1,2,3,4,6,7,10,14 (>4 for nwait) */ - /* tcos: 0,1,2,4 */ - /* tacs: 0,1,2,4 */ - - ret = calc_0124(bt->tacs, hclk, &res, S3C2410_BANKCON_Tacs_SHIFT); - ret |= calc_0124(bt->tcos, hclk, &res, S3C2410_BANKCON_Tcos_SHIFT); - ret |= calc_0124(bt->tcah, hclk, &res, S3C2410_BANKCON_Tcah_SHIFT); - ret |= calc_0124(bt->tcoh, hclk, &res, S3C2410_BANKCON_Tcoh_SHIFT); - - if (ret) - return -EINVAL; - - ret |= calc_tacp(bt->tacp, hclk, &res); - ret |= calc_tacc(bt->tacc, bt->nwait_en, hclk, &res); - - if (ret) - return -EINVAL; - - bt->bankcon = res; - return 0; -} - -static const unsigned int tacc_tab[] = { - [0] = 1, - [1] = 2, - [2] = 3, - [3] = 4, - [4] = 6, - [5] = 9, - [6] = 10, - [7] = 14, -}; - -/** - * get_tacc - turn tACC value into cycle time - * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds. - * @val: The bank timing register value, shifed down. - */ -static unsigned int get_tacc(unsigned long hclk_tns, - unsigned long val) -{ - val &= 7; - return hclk_tns * tacc_tab[val]; -} - -/** - * get_0124 - turn 0/1/2/4 divider into cycle time - * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds. - * @val: The bank timing register value, shifed down. - */ -static unsigned int get_0124(unsigned long hclk_tns, - unsigned long val) -{ - val &= 3; - return hclk_tns * ((val == 3) ? 4 : val); -} - -/** - * s3c2410_iotiming_getbank - turn BANKCON into cycle time information - * @cfg: The frequency configuration - * @bt: The bank timing to fill in (uses cached BANKCON) - * - * Given the BANKCON setting in @bt and the current frequency settings - * in @cfg, update the cycle timing information. - */ -static void s3c2410_iotiming_getbank(struct s3c_cpufreq_config *cfg, - struct s3c2410_iobank_timing *bt) -{ - unsigned long bankcon = bt->bankcon; - unsigned long hclk = cfg->freq.hclk_tns; - - bt->tcah = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcah_SHIFT); - bt->tcoh = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcoh_SHIFT); - bt->tcos = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcos_SHIFT); - bt->tacs = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tacs_SHIFT); - bt->tacc = get_tacc(hclk, bankcon >> S3C2410_BANKCON_Tacc_SHIFT); -} - -/** - * s3c2410_iotiming_debugfs - debugfs show io bank timing information - * @seq: The seq_file to write output to using seq_printf(). - * @cfg: The current configuration. - * @iob: The IO bank information to decode. - */ -void s3c2410_iotiming_debugfs(struct seq_file *seq, - struct s3c_cpufreq_config *cfg, - union s3c_iobank *iob) -{ - struct s3c2410_iobank_timing *bt = iob->io_2410; - unsigned long bankcon = bt->bankcon; - unsigned long hclk = cfg->freq.hclk_tns; - unsigned int tacs; - unsigned int tcos; - unsigned int tacc; - unsigned int tcoh; - unsigned int tcah; - - seq_printf(seq, "BANKCON=0x%08lx\n", bankcon); - - tcah = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcah_SHIFT); - tcoh = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcoh_SHIFT); - tcos = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcos_SHIFT); - tacs = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tacs_SHIFT); - tacc = get_tacc(hclk, bankcon >> S3C2410_BANKCON_Tacc_SHIFT); - - seq_printf(seq, - "\tRead: Tacs=%d.%d, Tcos=%d.%d, Tacc=%d.%d, Tcoh=%d.%d, Tcah=%d.%d\n", - print_ns(bt->tacs), - print_ns(bt->tcos), - print_ns(bt->tacc), - print_ns(bt->tcoh), - print_ns(bt->tcah)); - - seq_printf(seq, - "\t Set: Tacs=%d.%d, Tcos=%d.%d, Tacc=%d.%d, Tcoh=%d.%d, Tcah=%d.%d\n", - print_ns(tacs), - print_ns(tcos), - print_ns(tacc), - print_ns(tcoh), - print_ns(tcah)); -} - -/** - * s3c2410_iotiming_calc - Calculate bank timing for frequency change. - * @cfg: The frequency configuration - * @iot: The IO timing information to fill out. - * - * Calculate the new values for the banks in @iot based on the new - * frequency information in @cfg. This is then used by s3c2410_iotiming_set() - * to update the timing when necessary. - */ -int s3c2410_iotiming_calc(struct s3c_cpufreq_config *cfg, - struct s3c_iotimings *iot) -{ - struct s3c2410_iobank_timing *bt; - unsigned long bankcon; - int bank; - int ret; - - for (bank = 0; bank < MAX_BANKS; bank++) { - bankcon = __raw_readl(bank_reg(bank)); - bt = iot->bank[bank].io_2410; - - if (!bt) - continue; - - bt->bankcon = bankcon; - - ret = s3c2410_calc_bank(cfg, bt); - if (ret) { - printk(KERN_ERR "%s: cannot calculate bank %d io\n", - __func__, bank); - goto err; - } - - s3c_freq_iodbg("%s: bank %d: con=%08lx\n", - __func__, bank, bt->bankcon); - } - - return 0; - err: - return ret; -} - -/** - * s3c2410_iotiming_set - set the IO timings from the given setup. - * @cfg: The frequency configuration - * @iot: The IO timing information to use. - * - * Set all the currently used IO bank timing information generated - * by s3c2410_iotiming_calc() once the core has validated that all - * the new values are within permitted bounds. - */ -void s3c2410_iotiming_set(struct s3c_cpufreq_config *cfg, - struct s3c_iotimings *iot) -{ - struct s3c2410_iobank_timing *bt; - int bank; - - /* set the io timings from the specifier */ - - for (bank = 0; bank < MAX_BANKS; bank++) { - bt = iot->bank[bank].io_2410; - if (!bt) - continue; - - __raw_writel(bt->bankcon, bank_reg(bank)); - } -} - -/** - * s3c2410_iotiming_get - Get the timing information from current registers. - * @cfg: The frequency configuration - * @timings: The IO timing information to fill out. - * - * Calculate the @timings timing information from the current frequency - * information in @cfg, and the new frequency configuration - * through all the IO banks, reading the state and then updating @iot - * as necessary. - * - * This is used at the moment on initialisation to get the current - * configuration so that boards do not have to carry their own setup - * if the timings are correct on initialisation. - */ - -int s3c2410_iotiming_get(struct s3c_cpufreq_config *cfg, - struct s3c_iotimings *timings) -{ - struct s3c2410_iobank_timing *bt; - unsigned long bankcon; - unsigned long bwscon; - int bank; - - bwscon = __raw_readl(S3C2410_BWSCON); - - /* look through all banks to see what is currently set. */ - - for (bank = 0; bank < MAX_BANKS; bank++) { - bankcon = __raw_readl(bank_reg(bank)); - - if (!bank_is_io(bankcon)) - continue; - - s3c_freq_iodbg("%s: bank %d: con %08lx\n", - __func__, bank, bankcon); - - bt = kzalloc(sizeof(*bt), GFP_KERNEL); - if (!bt) - return -ENOMEM; - - /* find out in nWait is enabled for bank. */ - - if (bank != 0) { - unsigned long tmp = S3C2410_BWSCON_GET(bwscon, bank); - if (tmp & S3C2410_BWSCON_WS) - bt->nwait_en = 1; - } - - timings->bank[bank].io_2410 = bt; - bt->bankcon = bankcon; - - s3c2410_iotiming_getbank(cfg, bt); - } - - s3c2410_print_timing("get", timings); - return 0; -} diff --git a/arch/arm/mach-s3c24xx/iotiming-s3c2412.c b/arch/arm/mach-s3c24xx/iotiming-s3c2412.c deleted file mode 100644 index a22b5611697d..000000000000 --- a/arch/arm/mach-s3c24xx/iotiming-s3c2412.c +++ /dev/null @@ -1,278 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (c) 2006-2008 Simtec Electronics -// http://armlinux.simtec.co.uk/ -// Ben Dooks -// -// S3C2412/S3C2443 (PL093 based) IO timing support - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include - -#include -#include - -#include - -#define print_ns(x) ((x) / 10), ((x) % 10) - -/** - * s3c2412_print_timing - print timing information via printk. - * @pfx: The prefix to print each line with. - * @iot: The IO timing information - */ -static void s3c2412_print_timing(const char *pfx, struct s3c_iotimings *iot) -{ - struct s3c2412_iobank_timing *bt; - unsigned int bank; - - for (bank = 0; bank < MAX_BANKS; bank++) { - bt = iot->bank[bank].io_2412; - if (!bt) - continue; - - printk(KERN_DEBUG "%s: %d: idcy=%d.%d wstrd=%d.%d wstwr=%d,%d" - "wstoen=%d.%d wstwen=%d.%d wstbrd=%d.%d\n", pfx, bank, - print_ns(bt->idcy), - print_ns(bt->wstrd), - print_ns(bt->wstwr), - print_ns(bt->wstoen), - print_ns(bt->wstwen), - print_ns(bt->wstbrd)); - } -} - -/** - * to_div - turn a cycle length into a divisor setting. - * @cyc_tns: The cycle time in 10ths of nanoseconds. - * @clk_tns: The clock period in 10ths of nanoseconds. - */ -static inline unsigned int to_div(unsigned int cyc_tns, unsigned int clk_tns) -{ - return cyc_tns ? DIV_ROUND_UP(cyc_tns, clk_tns) : 0; -} - -/** - * calc_timing - calculate timing divisor value and check in range. - * @hwtm: The hardware timing in 10ths of nanoseconds. - * @clk_tns: The clock period in 10ths of nanoseconds. - * @err: Pointer to err variable to update in event of failure. - */ -static unsigned int calc_timing(unsigned int hwtm, unsigned int clk_tns, - unsigned int *err) -{ - unsigned int ret = to_div(hwtm, clk_tns); - - if (ret > 0xf) - *err = -EINVAL; - - return ret; -} - -/** - * s3c2412_calc_bank - calculate the bank divisor settings. - * @cfg: The current frequency configuration. - * @bt: The bank timing. - */ -static int s3c2412_calc_bank(struct s3c_cpufreq_config *cfg, - struct s3c2412_iobank_timing *bt) -{ - unsigned int hclk = cfg->freq.hclk_tns; - int err = 0; - - bt->smbidcyr = calc_timing(bt->idcy, hclk, &err); - bt->smbwstrd = calc_timing(bt->wstrd, hclk, &err); - bt->smbwstwr = calc_timing(bt->wstwr, hclk, &err); - bt->smbwstoen = calc_timing(bt->wstoen, hclk, &err); - bt->smbwstwen = calc_timing(bt->wstwen, hclk, &err); - bt->smbwstbrd = calc_timing(bt->wstbrd, hclk, &err); - - return err; -} - -/** - * s3c2412_iotiming_debugfs - debugfs show io bank timing information - * @seq: The seq_file to write output to using seq_printf(). - * @cfg: The current configuration. - * @iob: The IO bank information to decode. -*/ -void s3c2412_iotiming_debugfs(struct seq_file *seq, - struct s3c_cpufreq_config *cfg, - union s3c_iobank *iob) -{ - struct s3c2412_iobank_timing *bt = iob->io_2412; - - seq_printf(seq, - "\tRead: idcy=%d.%d wstrd=%d.%d wstwr=%d,%d" - "wstoen=%d.%d wstwen=%d.%d wstbrd=%d.%d\n", - print_ns(bt->idcy), - print_ns(bt->wstrd), - print_ns(bt->wstwr), - print_ns(bt->wstoen), - print_ns(bt->wstwen), - print_ns(bt->wstbrd)); -} - -/** - * s3c2412_iotiming_calc - calculate all the bank divisor settings. - * @cfg: The current frequency configuration. - * @iot: The bank timing information. - * - * Calculate the timing information for all the banks that are - * configured as IO, using s3c2412_calc_bank(). - */ -int s3c2412_iotiming_calc(struct s3c_cpufreq_config *cfg, - struct s3c_iotimings *iot) -{ - struct s3c2412_iobank_timing *bt; - int bank; - int ret; - - for (bank = 0; bank < MAX_BANKS; bank++) { - bt = iot->bank[bank].io_2412; - if (!bt) - continue; - - ret = s3c2412_calc_bank(cfg, bt); - if (ret) { - printk(KERN_ERR "%s: cannot calculate bank %d io\n", - __func__, bank); - goto err; - } - } - - return 0; - err: - return ret; -} - -/** - * s3c2412_iotiming_set - set the timing information - * @cfg: The current frequency configuration. - * @iot: The bank timing information. - * - * Set the IO bank information from the details calculated earlier from - * calling s3c2412_iotiming_calc(). - */ -void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg, - struct s3c_iotimings *iot) -{ - struct s3c2412_iobank_timing *bt; - void __iomem *regs; - int bank; - - /* set the io timings from the specifier */ - - for (bank = 0; bank < MAX_BANKS; bank++) { - bt = iot->bank[bank].io_2412; - if (!bt) - continue; - - regs = S3C2412_SSMC_BANK(bank); - - __raw_writel(bt->smbidcyr, regs + SMBIDCYR); - __raw_writel(bt->smbwstrd, regs + SMBWSTRDR); - __raw_writel(bt->smbwstwr, regs + SMBWSTWRR); - __raw_writel(bt->smbwstoen, regs + SMBWSTOENR); - __raw_writel(bt->smbwstwen, regs + SMBWSTWENR); - __raw_writel(bt->smbwstbrd, regs + SMBWSTBRDR); - } -} - -static inline unsigned int s3c2412_decode_timing(unsigned int clock, u32 reg) -{ - return (reg & 0xf) * clock; -} - -static void s3c2412_iotiming_getbank(struct s3c_cpufreq_config *cfg, - struct s3c2412_iobank_timing *bt, - unsigned int bank) -{ - unsigned long clk = cfg->freq.hclk_tns; /* ssmc clock??? */ - void __iomem *regs = S3C2412_SSMC_BANK(bank); - - bt->idcy = s3c2412_decode_timing(clk, __raw_readl(regs + SMBIDCYR)); - bt->wstrd = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTRDR)); - bt->wstoen = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTOENR)); - bt->wstwen = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTWENR)); - bt->wstbrd = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTBRDR)); -} - -/** - * bank_is_io - return true if bank is (possibly) IO. - * @bank: The bank number. - * @bankcfg: The value of S3C2412_EBI_BANKCFG. - */ -static inline bool bank_is_io(unsigned int bank, u32 bankcfg) -{ - if (bank < 2) - return true; - - return !(bankcfg & (1 << bank)); -} - -int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg, - struct s3c_iotimings *timings) -{ - struct s3c2412_iobank_timing *bt; - u32 bankcfg = __raw_readl(S3C2412_EBI_BANKCFG); - unsigned int bank; - - /* look through all banks to see what is currently set. */ - - for (bank = 0; bank < MAX_BANKS; bank++) { - if (!bank_is_io(bank, bankcfg)) - continue; - - bt = kzalloc(sizeof(*bt), GFP_KERNEL); - if (!bt) - return -ENOMEM; - - timings->bank[bank].io_2412 = bt; - s3c2412_iotiming_getbank(cfg, bt, bank); - } - - s3c2412_print_timing("get", timings); - return 0; -} - -/* this is in here as it is so small, it doesn't currently warrant a file - * to itself. We expect that any s3c24xx needing this is going to also - * need the iotiming support. - */ -void s3c2412_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg) -{ - struct s3c_cpufreq_board *board = cfg->board; - u32 refresh; - - WARN_ON(board == NULL); - - /* Reduce both the refresh time (in ns) and the frequency (in MHz) - * down to ensure that we do not overflow 32 bit numbers. - * - * This should work for HCLK up to 133MHz and refresh period up - * to 30usec. - */ - - refresh = (cfg->freq.hclk / 100) * (board->refresh / 10); - refresh = DIV_ROUND_UP(refresh, (1000 * 1000)); /* apply scale */ - refresh &= ((1 << 16) - 1); - - s3c_freq_dbg("%s: refresh value %u\n", __func__, (unsigned int)refresh); - - __raw_writel(refresh, S3C2412_REFRESH); -} diff --git a/arch/arm/mach-s3c24xx/irq-pm.c b/arch/arm/mach-s3c24xx/irq-pm.c deleted file mode 100644 index e0131b16a4af..000000000000 --- a/arch/arm/mach-s3c24xx/irq-pm.c +++ /dev/null @@ -1,115 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (c) 2003-2004 Simtec Electronics -// Ben Dooks -// http://armlinux.simtec.co.uk/ -// -// S3C24XX - IRQ PM code - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include - -#include - -int s3c_irq_wake(struct irq_data *data, unsigned int state) -{ - unsigned long irqbit = 1 << data->hwirq; - - if (!(s3c_irqwake_intallow & irqbit)) - return -ENOENT; - - pr_info("wake %s for hwirq %lu\n", - state ? "enabled" : "disabled", data->hwirq); - - if (!state) - s3c_irqwake_intmask |= irqbit; - else - s3c_irqwake_intmask &= ~irqbit; - - return 0; -} - -static struct sleep_save irq_save[] = { - SAVE_ITEM(S3C2410_INTMSK), - SAVE_ITEM(S3C2410_INTSUBMSK), -}; - -/* the extint values move between the s3c2410/s3c2440 and the s3c2412 - * so we use an array to hold them, and to calculate the address of - * the register at run-time -*/ - -static unsigned long save_extint[3]; -static unsigned long save_eintflt[4]; -static unsigned long save_eintmask; - -static int s3c24xx_irq_suspend(void) -{ - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(save_extint); i++) - save_extint[i] = __raw_readl(S3C24XX_EXTINT0 + (i*4)); - - for (i = 0; i < ARRAY_SIZE(save_eintflt); i++) - save_eintflt[i] = __raw_readl(S3C24XX_EINFLT0 + (i*4)); - - s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save)); - save_eintmask = __raw_readl(S3C24XX_EINTMASK); - - return 0; -} - -static void s3c24xx_irq_resume(void) -{ - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(save_extint); i++) - __raw_writel(save_extint[i], S3C24XX_EXTINT0 + (i*4)); - - for (i = 0; i < ARRAY_SIZE(save_eintflt); i++) - __raw_writel(save_eintflt[i], S3C24XX_EINFLT0 + (i*4)); - - s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save)); - __raw_writel(save_eintmask, S3C24XX_EINTMASK); -} - -struct syscore_ops s3c24xx_irq_syscore_ops = { - .suspend = s3c24xx_irq_suspend, - .resume = s3c24xx_irq_resume, -}; - -#ifdef CONFIG_CPU_S3C2416 -static struct sleep_save s3c2416_irq_save[] = { - SAVE_ITEM(S3C2416_INTMSK2), -}; - -static int s3c2416_irq_suspend(void) -{ - s3c_pm_do_save(s3c2416_irq_save, ARRAY_SIZE(s3c2416_irq_save)); - - return 0; -} - -static void s3c2416_irq_resume(void) -{ - s3c_pm_do_restore(s3c2416_irq_save, ARRAY_SIZE(s3c2416_irq_save)); -} - -struct syscore_ops s3c2416_irq_syscore_ops = { - .suspend = s3c2416_irq_suspend, - .resume = s3c2416_irq_resume, -}; -#endif diff --git a/arch/arm/mach-s3c24xx/irq-s3c24xx-fiq-exports.c b/arch/arm/mach-s3c24xx/irq-s3c24xx-fiq-exports.c deleted file mode 100644 index 84cf86376ded..000000000000 --- a/arch/arm/mach-s3c24xx/irq-s3c24xx-fiq-exports.c +++ /dev/null @@ -1,9 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include -#include -#include - -EXPORT_SYMBOL(s3c24xx_spi_fiq_rx); -EXPORT_SYMBOL(s3c24xx_spi_fiq_txrx); -EXPORT_SYMBOL(s3c24xx_spi_fiq_tx); diff --git a/arch/arm/mach-s3c24xx/irq-s3c24xx-fiq.S b/arch/arm/mach-s3c24xx/irq-s3c24xx-fiq.S deleted file mode 100644 index 2a84535a14fd..000000000000 --- a/arch/arm/mach-s3c24xx/irq-s3c24xx-fiq.S +++ /dev/null @@ -1,115 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* linux/drivers/spi/spi_s3c24xx_fiq.S - * - * Copyright 2009 Simtec Electronics - * Ben Dooks - * - * S3C24XX SPI - FIQ pseudo-DMA transfer code -*/ - -#include -#include - -#include -#include - -#include - -#define S3C2410_SPTDAT (0x10) -#define S3C2410_SPRDAT (0x14) - - .text - - @ entry to these routines is as follows, with the register names - @ defined in fiq.h so that they can be shared with the C files which - @ setup the calling registers. - @ - @ fiq_rirq The base of the IRQ registers to find S3C2410_SRCPND - @ fiq_rtmp Temporary register to hold tx/rx data - @ fiq_rspi The base of the SPI register block - @ fiq_rtx The tx buffer pointer - @ fiq_rrx The rx buffer pointer - @ fiq_rcount The number of bytes to move - - @ each entry starts with a word entry of how long it is - @ and an offset to the irq acknowledgment word - -ENTRY(s3c24xx_spi_fiq_rx) -s3c24xx_spi_fix_rx: - .word fiq_rx_end - fiq_rx_start - .word fiq_rx_irq_ack - fiq_rx_start -fiq_rx_start: - ldr fiq_rtmp, fiq_rx_irq_ack - str fiq_rtmp, [ fiq_rirq, # S3C2410_SRCPND - S3C24XX_VA_IRQ ] - - ldrb fiq_rtmp, [ fiq_rspi, # S3C2410_SPRDAT ] - strb fiq_rtmp, [ fiq_rrx ], #1 - - mov fiq_rtmp, #0xff - strb fiq_rtmp, [ fiq_rspi, # S3C2410_SPTDAT ] - - subs fiq_rcount, fiq_rcount, #1 - subnes pc, lr, #4 @@ return, still have work to do - - @@ set IRQ controller so that next op will trigger IRQ - mov fiq_rtmp, #0 - str fiq_rtmp, [ fiq_rirq, # S3C2410_INTMOD - S3C24XX_VA_IRQ ] - subs pc, lr, #4 - -fiq_rx_irq_ack: - .word 0 -fiq_rx_end: - -ENTRY(s3c24xx_spi_fiq_txrx) -s3c24xx_spi_fiq_txrx: - .word fiq_txrx_end - fiq_txrx_start - .word fiq_txrx_irq_ack - fiq_txrx_start -fiq_txrx_start: - - ldrb fiq_rtmp, [ fiq_rspi, # S3C2410_SPRDAT ] - strb fiq_rtmp, [ fiq_rrx ], #1 - - ldr fiq_rtmp, fiq_txrx_irq_ack - str fiq_rtmp, [ fiq_rirq, # S3C2410_SRCPND - S3C24XX_VA_IRQ ] - - ldrb fiq_rtmp, [ fiq_rtx ], #1 - strb fiq_rtmp, [ fiq_rspi, # S3C2410_SPTDAT ] - - subs fiq_rcount, fiq_rcount, #1 - subnes pc, lr, #4 @@ return, still have work to do - - mov fiq_rtmp, #0 - str fiq_rtmp, [ fiq_rirq, # S3C2410_INTMOD - S3C24XX_VA_IRQ ] - subs pc, lr, #4 - -fiq_txrx_irq_ack: - .word 0 - -fiq_txrx_end: - -ENTRY(s3c24xx_spi_fiq_tx) -s3c24xx_spi_fix_tx: - .word fiq_tx_end - fiq_tx_start - .word fiq_tx_irq_ack - fiq_tx_start -fiq_tx_start: - ldrb fiq_rtmp, [ fiq_rspi, # S3C2410_SPRDAT ] - - ldr fiq_rtmp, fiq_tx_irq_ack - str fiq_rtmp, [ fiq_rirq, # S3C2410_SRCPND - S3C24XX_VA_IRQ ] - - ldrb fiq_rtmp, [ fiq_rtx ], #1 - strb fiq_rtmp, [ fiq_rspi, # S3C2410_SPTDAT ] - - subs fiq_rcount, fiq_rcount, #1 - subnes pc, lr, #4 @@ return, still have work to do - - mov fiq_rtmp, #0 - str fiq_rtmp, [ fiq_rirq, # S3C2410_INTMOD - S3C24XX_VA_IRQ ] - subs pc, lr, #4 - -fiq_tx_irq_ack: - .word 0 - -fiq_tx_end: - - .end diff --git a/arch/arm/mach-s3c24xx/irq-s3c24xx.c b/arch/arm/mach-s3c24xx/irq-s3c24xx.c deleted file mode 100644 index 3965347cacf0..000000000000 --- a/arch/arm/mach-s3c24xx/irq-s3c24xx.c +++ /dev/null @@ -1,1337 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * S3C24XX IRQ handling - * - * Copyright (c) 2003-2004 Simtec Electronics - * Ben Dooks - * Copyright (c) 2012 Heiko Stuebner -*/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include - -#include -#include -#include - -#define S3C_IRQTYPE_NONE 0 -#define S3C_IRQTYPE_EINT 1 -#define S3C_IRQTYPE_EDGE 2 -#define S3C_IRQTYPE_LEVEL 3 - -struct s3c_irq_data { - unsigned int type; - unsigned long offset; - unsigned long parent_irq; - - /* data gets filled during init */ - struct s3c_irq_intc *intc; - unsigned long sub_bits; - struct s3c_irq_intc *sub_intc; -}; - -/* - * Structure holding the controller data - * @reg_pending register holding pending irqs - * @reg_intpnd special register intpnd in main intc - * @reg_mask mask register - * @domain irq_domain of the controller - * @parent parent controller for ext and sub irqs - * @irqs irq-data, always s3c_irq_data[32] - */ -struct s3c_irq_intc { - void __iomem *reg_pending; - void __iomem *reg_intpnd; - void __iomem *reg_mask; - struct irq_domain *domain; - struct s3c_irq_intc *parent; - struct s3c_irq_data *irqs; -}; - -/* - * Array holding pointers to the global controller structs - * [0] ... main_intc - * [1] ... sub_intc - * [2] ... main_intc2 on s3c2416 - */ -static struct s3c_irq_intc *s3c_intc[3]; - -static void s3c_irq_mask(struct irq_data *data) -{ - struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data); - struct s3c_irq_intc *intc = irq_data->intc; - struct s3c_irq_intc *parent_intc = intc->parent; - struct s3c_irq_data *parent_data; - unsigned long mask; - unsigned int irqno; - - mask = readl_relaxed(intc->reg_mask); - mask |= (1UL << irq_data->offset); - writel_relaxed(mask, intc->reg_mask); - - if (parent_intc) { - parent_data = &parent_intc->irqs[irq_data->parent_irq]; - - /* check to see if we need to mask the parent IRQ - * The parent_irq is always in main_intc, so the hwirq - * for find_mapping does not need an offset in any case. - */ - if ((mask & parent_data->sub_bits) == parent_data->sub_bits) { - irqno = irq_find_mapping(parent_intc->domain, - irq_data->parent_irq); - s3c_irq_mask(irq_get_irq_data(irqno)); - } - } -} - -static void s3c_irq_unmask(struct irq_data *data) -{ - struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data); - struct s3c_irq_intc *intc = irq_data->intc; - struct s3c_irq_intc *parent_intc = intc->parent; - unsigned long mask; - unsigned int irqno; - - mask = readl_relaxed(intc->reg_mask); - mask &= ~(1UL << irq_data->offset); - writel_relaxed(mask, intc->reg_mask); - - if (parent_intc) { - irqno = irq_find_mapping(parent_intc->domain, - irq_data->parent_irq); - s3c_irq_unmask(irq_get_irq_data(irqno)); - } -} - -static inline void s3c_irq_ack(struct irq_data *data) -{ - struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data); - struct s3c_irq_intc *intc = irq_data->intc; - unsigned long bitval = 1UL << irq_data->offset; - - writel_relaxed(bitval, intc->reg_pending); - if (intc->reg_intpnd) - writel_relaxed(bitval, intc->reg_intpnd); -} - -static int s3c_irq_type(struct irq_data *data, unsigned int type) -{ - switch (type) { - case IRQ_TYPE_NONE: - break; - case IRQ_TYPE_EDGE_RISING: - case IRQ_TYPE_EDGE_FALLING: - case IRQ_TYPE_EDGE_BOTH: - irq_set_handler(data->irq, handle_edge_irq); - break; - case IRQ_TYPE_LEVEL_LOW: - case IRQ_TYPE_LEVEL_HIGH: - irq_set_handler(data->irq, handle_level_irq); - break; - default: - pr_err("No such irq type %d\n", type); - return -EINVAL; - } - - return 0; -} - -static int s3c_irqext_type_set(void __iomem *gpcon_reg, - void __iomem *extint_reg, - unsigned long gpcon_offset, - unsigned long extint_offset, - unsigned int type) -{ - unsigned long newvalue = 0, value; - - /* Set the GPIO to external interrupt mode */ - value = readl_relaxed(gpcon_reg); - value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset); - writel_relaxed(value, gpcon_reg); - - /* Set the external interrupt to pointed trigger type */ - switch (type) - { - case IRQ_TYPE_NONE: - pr_warn("No edge setting!\n"); - break; - - case IRQ_TYPE_EDGE_RISING: - newvalue = S3C2410_EXTINT_RISEEDGE; - break; - - case IRQ_TYPE_EDGE_FALLING: - newvalue = S3C2410_EXTINT_FALLEDGE; - break; - - case IRQ_TYPE_EDGE_BOTH: - newvalue = S3C2410_EXTINT_BOTHEDGE; - break; - - case IRQ_TYPE_LEVEL_LOW: - newvalue = S3C2410_EXTINT_LOWLEV; - break; - - case IRQ_TYPE_LEVEL_HIGH: - newvalue = S3C2410_EXTINT_HILEV; - break; - - default: - pr_err("No such irq type %d\n", type); - return -EINVAL; - } - - value = readl_relaxed(extint_reg); - value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset); - writel_relaxed(value, extint_reg); - - return 0; -} - -static int s3c_irqext_type(struct irq_data *data, unsigned int type) -{ - void __iomem *extint_reg; - void __iomem *gpcon_reg; - unsigned long gpcon_offset, extint_offset; - - if ((data->hwirq >= 4) && (data->hwirq <= 7)) { - gpcon_reg = S3C2410_GPFCON; - extint_reg = S3C24XX_EXTINT0; - gpcon_offset = (data->hwirq) * 2; - extint_offset = (data->hwirq) * 4; - } else if ((data->hwirq >= 8) && (data->hwirq <= 15)) { - gpcon_reg = S3C2410_GPGCON; - extint_reg = S3C24XX_EXTINT1; - gpcon_offset = (data->hwirq - 8) * 2; - extint_offset = (data->hwirq - 8) * 4; - } else if ((data->hwirq >= 16) && (data->hwirq <= 23)) { - gpcon_reg = S3C2410_GPGCON; - extint_reg = S3C24XX_EXTINT2; - gpcon_offset = (data->hwirq - 8) * 2; - extint_offset = (data->hwirq - 16) * 4; - } else { - return -EINVAL; - } - - return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset, - extint_offset, type); -} - -static int s3c_irqext0_type(struct irq_data *data, unsigned int type) -{ - void __iomem *extint_reg; - void __iomem *gpcon_reg; - unsigned long gpcon_offset, extint_offset; - - if (data->hwirq <= 3) { - gpcon_reg = S3C2410_GPFCON; - extint_reg = S3C24XX_EXTINT0; - gpcon_offset = (data->hwirq) * 2; - extint_offset = (data->hwirq) * 4; - } else { - return -EINVAL; - } - - return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset, - extint_offset, type); -} - -static struct irq_chip s3c_irq_chip = { - .name = "s3c", - .irq_ack = s3c_irq_ack, - .irq_mask = s3c_irq_mask, - .irq_unmask = s3c_irq_unmask, - .irq_set_type = s3c_irq_type, - .irq_set_wake = s3c_irq_wake -}; - -static struct irq_chip s3c_irq_level_chip = { - .name = "s3c-level", - .irq_mask = s3c_irq_mask, - .irq_unmask = s3c_irq_unmask, - .irq_ack = s3c_irq_ack, - .irq_set_type = s3c_irq_type, -}; - -static struct irq_chip s3c_irqext_chip = { - .name = "s3c-ext", - .irq_mask = s3c_irq_mask, - .irq_unmask = s3c_irq_unmask, - .irq_ack = s3c_irq_ack, - .irq_set_type = s3c_irqext_type, - .irq_set_wake = s3c_irqext_wake -}; - -static struct irq_chip s3c_irq_eint0t4 = { - .name = "s3c-ext0", - .irq_ack = s3c_irq_ack, - .irq_mask = s3c_irq_mask, - .irq_unmask = s3c_irq_unmask, - .irq_set_wake = s3c_irq_wake, - .irq_set_type = s3c_irqext0_type, -}; - -static void s3c_irq_demux(struct irq_desc *desc) -{ - struct irq_chip *chip = irq_desc_get_chip(desc); - struct s3c_irq_data *irq_data = irq_desc_get_chip_data(desc); - struct s3c_irq_intc *intc = irq_data->intc; - struct s3c_irq_intc *sub_intc = irq_data->sub_intc; - unsigned int n, offset, irq; - unsigned long src, msk; - - /* we're using individual domains for the non-dt case - * and one big domain for the dt case where the subintc - * starts at hwirq number 32. - */ - offset = irq_domain_get_of_node(intc->domain) ? 32 : 0; - - chained_irq_enter(chip, desc); - - src = readl_relaxed(sub_intc->reg_pending); - msk = readl_relaxed(sub_intc->reg_mask); - - src &= ~msk; - src &= irq_data->sub_bits; - - while (src) { - n = __ffs(src); - src &= ~(1 << n); - irq = irq_find_mapping(sub_intc->domain, offset + n); - generic_handle_irq(irq); - } - - chained_irq_exit(chip, desc); -} - -static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc, - struct pt_regs *regs, int intc_offset) -{ - int pnd; - int offset; - - pnd = readl_relaxed(intc->reg_intpnd); - if (!pnd) - return false; - - /* non-dt machines use individual domains */ - if (!irq_domain_get_of_node(intc->domain)) - intc_offset = 0; - - /* We have a problem that the INTOFFSET register does not always - * show one interrupt. Occasionally we get two interrupts through - * the prioritiser, and this causes the INTOFFSET register to show - * what looks like the logical-or of the two interrupt numbers. - * - * Thanks to Klaus, Shannon, et al for helping to debug this problem - */ - offset = readl_relaxed(intc->reg_intpnd + 4); - - /* Find the bit manually, when the offset is wrong. - * The pending register only ever contains the one bit of the next - * interrupt to handle. - */ - if (!(pnd & (1 << offset))) - offset = __ffs(pnd); - - handle_domain_irq(intc->domain, intc_offset + offset, regs); - return true; -} - -asmlinkage void __exception_irq_entry s3c24xx_handle_irq(struct pt_regs *regs) -{ - do { - if (likely(s3c_intc[0])) - if (s3c24xx_handle_intc(s3c_intc[0], regs, 0)) - continue; - - if (s3c_intc[2]) - if (s3c24xx_handle_intc(s3c_intc[2], regs, 64)) - continue; - - break; - } while (1); -} - -#ifdef CONFIG_FIQ -/** - * s3c24xx_set_fiq - set the FIQ routing - * @irq: IRQ number to route to FIQ on processor. - * @ack_ptr: pointer to a location for storing the bit mask - * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing. - * - * Change the state of the IRQ to FIQ routing depending on @irq and @on. If - * @on is true, the @irq is checked to see if it can be routed and the - * interrupt controller updated to route the IRQ. If @on is false, the FIQ - * routing is cleared, regardless of which @irq is specified. - * - * returns the mask value for the register. - */ -int s3c24xx_set_fiq(unsigned int irq, u32 *ack_ptr, bool on) -{ - u32 intmod; - unsigned offs; - - if (on) { - offs = irq - FIQ_START; - if (offs > 31) - return 0; - - intmod = 1 << offs; - } else { - intmod = 0; - } - - if (ack_ptr) - *ack_ptr = intmod; - writel_relaxed(intmod, S3C2410_INTMOD); - - return intmod; -} - -EXPORT_SYMBOL_GPL(s3c24xx_set_fiq); -#endif - -static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq, - irq_hw_number_t hw) -{ - struct s3c_irq_intc *intc = h->host_data; - struct s3c_irq_data *irq_data = &intc->irqs[hw]; - struct s3c_irq_intc *parent_intc; - struct s3c_irq_data *parent_irq_data; - unsigned int irqno; - - /* attach controller pointer to irq_data */ - irq_data->intc = intc; - irq_data->offset = hw; - - parent_intc = intc->parent; - - /* set handler and flags */ - switch (irq_data->type) { - case S3C_IRQTYPE_NONE: - return 0; - case S3C_IRQTYPE_EINT: - /* On the S3C2412, the EINT0to3 have a parent irq - * but need the s3c_irq_eint0t4 chip - */ - if (parent_intc && (!soc_is_s3c2412() || hw >= 4)) - irq_set_chip_and_handler(virq, &s3c_irqext_chip, - handle_edge_irq); - else - irq_set_chip_and_handler(virq, &s3c_irq_eint0t4, - handle_edge_irq); - break; - case S3C_IRQTYPE_EDGE: - if (parent_intc || intc->reg_pending == S3C2416_SRCPND2) - irq_set_chip_and_handler(virq, &s3c_irq_level_chip, - handle_edge_irq); - else - irq_set_chip_and_handler(virq, &s3c_irq_chip, - handle_edge_irq); - break; - case S3C_IRQTYPE_LEVEL: - if (parent_intc) - irq_set_chip_and_handler(virq, &s3c_irq_level_chip, - handle_level_irq); - else - irq_set_chip_and_handler(virq, &s3c_irq_chip, - handle_level_irq); - break; - default: - pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type); - return -EINVAL; - } - - irq_set_chip_data(virq, irq_data); - - if (parent_intc && irq_data->type != S3C_IRQTYPE_NONE) { - if (irq_data->parent_irq > 31) { - pr_err("irq-s3c24xx: parent irq %lu is out of range\n", - irq_data->parent_irq); - return -EINVAL; - } - - parent_irq_data = &parent_intc->irqs[irq_data->parent_irq]; - parent_irq_data->sub_intc = intc; - parent_irq_data->sub_bits |= (1UL << hw); - - /* attach the demuxer to the parent irq */ - irqno = irq_find_mapping(parent_intc->domain, - irq_data->parent_irq); - if (!irqno) { - pr_err("irq-s3c24xx: could not find mapping for parent irq %lu\n", - irq_data->parent_irq); - return -EINVAL; - } - irq_set_chained_handler(irqno, s3c_irq_demux); - } - - return 0; -} - -static const struct irq_domain_ops s3c24xx_irq_ops = { - .map = s3c24xx_irq_map, - .xlate = irq_domain_xlate_twocell, -}; - -static void s3c24xx_clear_intc(struct s3c_irq_intc *intc) -{ - void __iomem *reg_source; - unsigned long pend; - unsigned long last; - int i; - - /* if intpnd is set, read the next pending irq from there */ - reg_source = intc->reg_intpnd ? intc->reg_intpnd : intc->reg_pending; - - last = 0; - for (i = 0; i < 4; i++) { - pend = readl_relaxed(reg_source); - - if (pend == 0 || pend == last) - break; - - writel_relaxed(pend, intc->reg_pending); - if (intc->reg_intpnd) - writel_relaxed(pend, intc->reg_intpnd); - - pr_info("irq: clearing pending status %08x\n", (int)pend); - last = pend; - } -} - -static struct s3c_irq_intc * __init s3c24xx_init_intc(struct device_node *np, - struct s3c_irq_data *irq_data, - struct s3c_irq_intc *parent, - unsigned long address) -{ - struct s3c_irq_intc *intc; - void __iomem *base = (void *)0xf6000000; /* static mapping */ - int irq_num; - int irq_start; - int ret; - - intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL); - if (!intc) - return ERR_PTR(-ENOMEM); - - intc->irqs = irq_data; - - if (parent) - intc->parent = parent; - - /* select the correct data for the controller. - * Need to hard code the irq num start and offset - * to preserve the static mapping for now - */ - switch (address) { - case 0x4a000000: - pr_debug("irq: found main intc\n"); - intc->reg_pending = base; - intc->reg_mask = base + 0x08; - intc->reg_intpnd = base + 0x10; - irq_num = 32; - irq_start = S3C2410_IRQ(0); - break; - case 0x4a000018: - pr_debug("irq: found subintc\n"); - intc->reg_pending = base + 0x18; - intc->reg_mask = base + 0x1c; - irq_num = 29; - irq_start = S3C2410_IRQSUB(0); - break; - case 0x4a000040: - pr_debug("irq: found intc2\n"); - intc->reg_pending = base + 0x40; - intc->reg_mask = base + 0x48; - intc->reg_intpnd = base + 0x50; - irq_num = 8; - irq_start = S3C2416_IRQ(0); - break; - case 0x560000a4: - pr_debug("irq: found eintc\n"); - base = (void *)0xfd000000; - - intc->reg_mask = base + 0xa4; - intc->reg_pending = base + 0xa8; - irq_num = 24; - irq_start = S3C2410_IRQ(32); - break; - default: - pr_err("irq: unsupported controller address\n"); - ret = -EINVAL; - goto err; - } - - /* now that all the data is complete, init the irq-domain */ - s3c24xx_clear_intc(intc); - intc->domain = irq_domain_add_legacy(np, irq_num, irq_start, - 0, &s3c24xx_irq_ops, - intc); - if (!intc->domain) { - pr_err("irq: could not create irq-domain\n"); - ret = -EINVAL; - goto err; - } - - set_handle_irq(s3c24xx_handle_irq); - - return intc; - -err: - kfree(intc); - return ERR_PTR(ret); -} - -static struct s3c_irq_data __maybe_unused init_eint[32] = { - { .type = S3C_IRQTYPE_NONE, }, /* reserved */ - { .type = S3C_IRQTYPE_NONE, }, /* reserved */ - { .type = S3C_IRQTYPE_NONE, }, /* reserved */ - { .type = S3C_IRQTYPE_NONE, }, /* reserved */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */ -}; - -#ifdef CONFIG_CPU_S3C2410 -static struct s3c_irq_data init_s3c2410base[32] = { - { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ - { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ - { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ - { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ - { .type = S3C_IRQTYPE_NONE, }, /* reserved */ - { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ - { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ - { .type = S3C_IRQTYPE_EDGE, }, /* WDT */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ - { .type = S3C_IRQTYPE_EDGE, }, /* LCD */ - { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */ - { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */ - { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */ - { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */ - { .type = S3C_IRQTYPE_EDGE, }, /* SDI */ - { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ - { .type = S3C_IRQTYPE_NONE, }, /* reserved */ - { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ - { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ - { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ - { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ - { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ - { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ - { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ -}; - -static struct s3c_irq_data init_s3c2410subint[32] = { - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ - { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ - { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ -}; - -void __init s3c2410_init_irq(void) -{ -#ifdef CONFIG_FIQ - init_FIQ(FIQ_START); -#endif - - s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2410base[0], NULL, - 0x4a000000); - if (IS_ERR(s3c_intc[0])) { - pr_err("irq: could not create main interrupt controller\n"); - return; - } - - s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2410subint[0], - s3c_intc[0], 0x4a000018); - s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4); -} -#endif - -#ifdef CONFIG_CPU_S3C2412 -static struct s3c_irq_data init_s3c2412base[32] = { - { .type = S3C_IRQTYPE_LEVEL, }, /* EINT0 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* EINT1 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* EINT2 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* EINT3 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ - { .type = S3C_IRQTYPE_NONE, }, /* reserved */ - { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ - { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ - { .type = S3C_IRQTYPE_EDGE, }, /* WDT */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ - { .type = S3C_IRQTYPE_EDGE, }, /* LCD */ - { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */ - { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */ - { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */ - { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* SDI/CF */ - { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ - { .type = S3C_IRQTYPE_NONE, }, /* reserved */ - { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ - { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ - { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ - { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ - { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ - { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ - { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ -}; - -static struct s3c_irq_data init_s3c2412eint[32] = { - { .type = S3C_IRQTYPE_EINT, .parent_irq = 0 }, /* EINT0 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 1 }, /* EINT1 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 2 }, /* EINT2 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 3 }, /* EINT3 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */ -}; - -static struct s3c_irq_data init_s3c2412subint[32] = { - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ - { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ - { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ - { .type = S3C_IRQTYPE_NONE, }, - { .type = S3C_IRQTYPE_NONE, }, - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* SDI */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* CF */ -}; - -void __init s3c2412_init_irq(void) -{ - pr_info("S3C2412: IRQ Support\n"); - -#ifdef CONFIG_FIQ - init_FIQ(FIQ_START); -#endif - - s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2412base[0], NULL, - 0x4a000000); - if (IS_ERR(s3c_intc[0])) { - pr_err("irq: could not create main interrupt controller\n"); - return; - } - - s3c24xx_init_intc(NULL, &init_s3c2412eint[0], s3c_intc[0], 0x560000a4); - s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2412subint[0], - s3c_intc[0], 0x4a000018); -} -#endif - -#ifdef CONFIG_CPU_S3C2416 -static struct s3c_irq_data init_s3c2416base[32] = { - { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ - { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ - { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ - { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ - { .type = S3C_IRQTYPE_NONE, }, /* reserved */ - { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ - { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ - { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */ - { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */ - { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */ - { .type = S3C_IRQTYPE_NONE, }, /* reserved */ - { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */ - { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */ - { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ - { .type = S3C_IRQTYPE_EDGE, }, /* NAND */ - { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ - { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ - { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ - { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ - { .type = S3C_IRQTYPE_NONE, }, - { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ - { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ -}; - -static struct s3c_irq_data init_s3c2416subint[32] = { - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ - { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ - { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ - { .type = S3C_IRQTYPE_NONE }, /* reserved */ - { .type = S3C_IRQTYPE_NONE }, /* reserved */ - { .type = S3C_IRQTYPE_NONE }, /* reserved */ - { .type = S3C_IRQTYPE_NONE }, /* reserved */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */ -}; - -static struct s3c_irq_data init_s3c2416_second[32] = { - { .type = S3C_IRQTYPE_EDGE }, /* 2D */ - { .type = S3C_IRQTYPE_NONE }, /* reserved */ - { .type = S3C_IRQTYPE_NONE }, /* reserved */ - { .type = S3C_IRQTYPE_NONE }, /* reserved */ - { .type = S3C_IRQTYPE_EDGE }, /* PCM0 */ - { .type = S3C_IRQTYPE_NONE }, /* reserved */ - { .type = S3C_IRQTYPE_EDGE }, /* I2S0 */ -}; - -void __init s3c2416_init_irq(void) -{ - pr_info("S3C2416: IRQ Support\n"); - -#ifdef CONFIG_FIQ - init_FIQ(FIQ_START); -#endif - - s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL, - 0x4a000000); - if (IS_ERR(s3c_intc[0])) { - pr_err("irq: could not create main interrupt controller\n"); - return; - } - - s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4); - s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2416subint[0], - s3c_intc[0], 0x4a000018); - - s3c_intc[2] = s3c24xx_init_intc(NULL, &init_s3c2416_second[0], - NULL, 0x4a000040); -} - -#endif - -#ifdef CONFIG_CPU_S3C2440 -static struct s3c_irq_data init_s3c2440base[32] = { - { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ - { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ - { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ - { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */ - { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ - { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ - { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ - { .type = S3C_IRQTYPE_EDGE, }, /* LCD */ - { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */ - { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */ - { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */ - { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */ - { .type = S3C_IRQTYPE_EDGE, }, /* SDI */ - { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */ - { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ - { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ - { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ - { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ - { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ - { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ - { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ -}; - -static struct s3c_irq_data init_s3c2440subint[32] = { - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ - { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ - { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */ -}; - -void __init s3c2440_init_irq(void) -{ - pr_info("S3C2440: IRQ Support\n"); - -#ifdef CONFIG_FIQ - init_FIQ(FIQ_START); -#endif - - s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2440base[0], NULL, - 0x4a000000); - if (IS_ERR(s3c_intc[0])) { - pr_err("irq: could not create main interrupt controller\n"); - return; - } - - s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4); - s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2440subint[0], - s3c_intc[0], 0x4a000018); -} -#endif - -#ifdef CONFIG_CPU_S3C2442 -static struct s3c_irq_data init_s3c2442base[32] = { - { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ - { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ - { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ - { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */ - { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ - { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ - { .type = S3C_IRQTYPE_EDGE, }, /* WDT */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ - { .type = S3C_IRQTYPE_EDGE, }, /* LCD */ - { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */ - { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */ - { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */ - { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */ - { .type = S3C_IRQTYPE_EDGE, }, /* SDI */ - { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */ - { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ - { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ - { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ - { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ - { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ - { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ - { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ -}; - -static struct s3c_irq_data init_s3c2442subint[32] = { - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ - { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ - { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */ -}; - -void __init s3c2442_init_irq(void) -{ - pr_info("S3C2442: IRQ Support\n"); - -#ifdef CONFIG_FIQ - init_FIQ(FIQ_START); -#endif - - s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2442base[0], NULL, - 0x4a000000); - if (IS_ERR(s3c_intc[0])) { - pr_err("irq: could not create main interrupt controller\n"); - return; - } - - s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4); - s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2442subint[0], - s3c_intc[0], 0x4a000018); -} -#endif - -#ifdef CONFIG_CPU_S3C2443 -static struct s3c_irq_data init_s3c2443base[32] = { - { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ - { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ - { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ - { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */ - { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ - { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ - { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */ - { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */ - { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */ - { .type = S3C_IRQTYPE_EDGE, }, /* CFON */ - { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */ - { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */ - { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ - { .type = S3C_IRQTYPE_EDGE, }, /* NAND */ - { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ - { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ - { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ - { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ - { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ - { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ - { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ -}; - - -static struct s3c_irq_data init_s3c2443subint[32] = { - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ - { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ - { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */ - { .type = S3C_IRQTYPE_NONE }, /* reserved */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD1 */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */ -}; - -void __init s3c2443_init_irq(void) -{ - pr_info("S3C2443: IRQ Support\n"); - -#ifdef CONFIG_FIQ - init_FIQ(FIQ_START); -#endif - - s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL, - 0x4a000000); - if (IS_ERR(s3c_intc[0])) { - pr_err("irq: could not create main interrupt controller\n"); - return; - } - - s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4); - s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2443subint[0], - s3c_intc[0], 0x4a000018); -} -#endif - -#ifdef CONFIG_OF -static int s3c24xx_irq_map_of(struct irq_domain *h, unsigned int virq, - irq_hw_number_t hw) -{ - unsigned int ctrl_num = hw / 32; - unsigned int intc_hw = hw % 32; - struct s3c_irq_intc *intc = s3c_intc[ctrl_num]; - struct s3c_irq_intc *parent_intc = intc->parent; - struct s3c_irq_data *irq_data = &intc->irqs[intc_hw]; - - /* attach controller pointer to irq_data */ - irq_data->intc = intc; - irq_data->offset = intc_hw; - - if (!parent_intc) - irq_set_chip_and_handler(virq, &s3c_irq_chip, handle_edge_irq); - else - irq_set_chip_and_handler(virq, &s3c_irq_level_chip, - handle_edge_irq); - - irq_set_chip_data(virq, irq_data); - - return 0; -} - -/* Translate our of irq notation - * format: - */ -static int s3c24xx_irq_xlate_of(struct irq_domain *d, struct device_node *n, - const u32 *intspec, unsigned int intsize, - irq_hw_number_t *out_hwirq, unsigned int *out_type) -{ - struct s3c_irq_intc *intc; - struct s3c_irq_intc *parent_intc; - struct s3c_irq_data *irq_data; - struct s3c_irq_data *parent_irq_data; - int irqno; - - if (WARN_ON(intsize < 4)) - return -EINVAL; - - if (intspec[0] > 2 || !s3c_intc[intspec[0]]) { - pr_err("controller number %d invalid\n", intspec[0]); - return -EINVAL; - } - intc = s3c_intc[intspec[0]]; - - *out_hwirq = intspec[0] * 32 + intspec[2]; - *out_type = intspec[3] & IRQ_TYPE_SENSE_MASK; - - parent_intc = intc->parent; - if (parent_intc) { - irq_data = &intc->irqs[intspec[2]]; - irq_data->parent_irq = intspec[1]; - parent_irq_data = &parent_intc->irqs[irq_data->parent_irq]; - parent_irq_data->sub_intc = intc; - parent_irq_data->sub_bits |= (1UL << intspec[2]); - - /* parent_intc is always s3c_intc[0], so no offset */ - irqno = irq_create_mapping(parent_intc->domain, intspec[1]); - if (irqno < 0) { - pr_err("irq: could not map parent interrupt\n"); - return irqno; - } - - irq_set_chained_handler(irqno, s3c_irq_demux); - } - - return 0; -} - -static const struct irq_domain_ops s3c24xx_irq_ops_of = { - .map = s3c24xx_irq_map_of, - .xlate = s3c24xx_irq_xlate_of, -}; - -struct s3c24xx_irq_of_ctrl { - char *name; - unsigned long offset; - struct s3c_irq_intc **handle; - struct s3c_irq_intc **parent; - struct irq_domain_ops *ops; -}; - -static int __init s3c_init_intc_of(struct device_node *np, - struct device_node *interrupt_parent, - struct s3c24xx_irq_of_ctrl *s3c_ctrl, int num_ctrl) -{ - struct s3c_irq_intc *intc; - struct s3c24xx_irq_of_ctrl *ctrl; - struct irq_domain *domain; - void __iomem *reg_base; - int i; - - reg_base = of_iomap(np, 0); - if (!reg_base) { - pr_err("irq-s3c24xx: could not map irq registers\n"); - return -EINVAL; - } - - domain = irq_domain_add_linear(np, num_ctrl * 32, - &s3c24xx_irq_ops_of, NULL); - if (!domain) { - pr_err("irq: could not create irq-domain\n"); - return -EINVAL; - } - - for (i = 0; i < num_ctrl; i++) { - ctrl = &s3c_ctrl[i]; - - pr_debug("irq: found controller %s\n", ctrl->name); - - intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL); - if (!intc) - return -ENOMEM; - - intc->domain = domain; - intc->irqs = kcalloc(32, sizeof(struct s3c_irq_data), - GFP_KERNEL); - if (!intc->irqs) { - kfree(intc); - return -ENOMEM; - } - - if (ctrl->parent) { - intc->reg_pending = reg_base + ctrl->offset; - intc->reg_mask = reg_base + ctrl->offset + 0x4; - - if (*(ctrl->parent)) { - intc->parent = *(ctrl->parent); - } else { - pr_warn("irq: parent of %s missing\n", - ctrl->name); - kfree(intc->irqs); - kfree(intc); - continue; - } - } else { - intc->reg_pending = reg_base + ctrl->offset; - intc->reg_mask = reg_base + ctrl->offset + 0x08; - intc->reg_intpnd = reg_base + ctrl->offset + 0x10; - } - - s3c24xx_clear_intc(intc); - s3c_intc[i] = intc; - } - - set_handle_irq(s3c24xx_handle_irq); - - return 0; -} - -static struct s3c24xx_irq_of_ctrl s3c2410_ctrl[] = { - { - .name = "intc", - .offset = 0, - }, { - .name = "subintc", - .offset = 0x18, - .parent = &s3c_intc[0], - } -}; - -int __init s3c2410_init_intc_of(struct device_node *np, - struct device_node *interrupt_parent) -{ - return s3c_init_intc_of(np, interrupt_parent, - s3c2410_ctrl, ARRAY_SIZE(s3c2410_ctrl)); -} -IRQCHIP_DECLARE(s3c2410_irq, "samsung,s3c2410-irq", s3c2410_init_intc_of); - -static struct s3c24xx_irq_of_ctrl s3c2416_ctrl[] = { - { - .name = "intc", - .offset = 0, - }, { - .name = "subintc", - .offset = 0x18, - .parent = &s3c_intc[0], - }, { - .name = "intc2", - .offset = 0x40, - } -}; - -int __init s3c2416_init_intc_of(struct device_node *np, - struct device_node *interrupt_parent) -{ - return s3c_init_intc_of(np, interrupt_parent, - s3c2416_ctrl, ARRAY_SIZE(s3c2416_ctrl)); -} -IRQCHIP_DECLARE(s3c2416_irq, "samsung,s3c2416-irq", s3c2416_init_intc_of); -#endif diff --git a/arch/arm/mach-s3c24xx/mach-amlm5900.c b/arch/arm/mach-s3c24xx/mach-amlm5900.c deleted file mode 100644 index f04eb9aa29ac..000000000000 --- a/arch/arm/mach-s3c24xx/mach-amlm5900.c +++ /dev/null @@ -1,246 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright (c) 2006 American Microsystems Limited -// David Anders -// -// @History: -// derived from linux/arch/arm/mach-s3c2410/mach-bast.c, written by -// Ben Dooks - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "common.h" - -static struct resource amlm5900_nor_resource = - DEFINE_RES_MEM(0x00000000, SZ_16M); - -static struct mtd_partition amlm5900_mtd_partitions[] = { - { - .name = "System", - .size = 0x240000, - .offset = 0, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, { - .name = "Kernel", - .size = 0x100000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "Ramdisk", - .size = 0x300000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "JFFS2", - .size = 0x9A0000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "Settings", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct physmap_flash_data amlm5900_flash_data = { - .width = 2, - .parts = amlm5900_mtd_partitions, - .nr_parts = ARRAY_SIZE(amlm5900_mtd_partitions), -}; - -static struct platform_device amlm5900_device_nor = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &amlm5900_flash_data, - }, - .num_resources = 1, - .resource = &amlm5900_nor_resource, -}; - -static struct map_desc amlm5900_iodesc[] __initdata = { -}; - -#define UCON S3C2410_UCON_DEFAULT -#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB -#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE - -static struct s3c2410_uartcfg amlm5900_uartcfgs[] = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - [2] = { - .hwport = 2, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - } -}; - -static struct gpiod_lookup_table amlm5900_mmc_gpio_table = { - .dev_id = "s3c2410-sdi", - .table = { - /* bus pins */ - GPIO_LOOKUP_IDX("GPIOE", 5, "bus", 0, GPIO_ACTIVE_HIGH), - GPIO_LOOKUP_IDX("GPIOE", 6, "bus", 1, GPIO_ACTIVE_HIGH), - GPIO_LOOKUP_IDX("GPIOE", 7, "bus", 2, GPIO_ACTIVE_HIGH), - GPIO_LOOKUP_IDX("GPIOE", 8, "bus", 3, GPIO_ACTIVE_HIGH), - GPIO_LOOKUP_IDX("GPIOE", 9, "bus", 4, GPIO_ACTIVE_HIGH), - GPIO_LOOKUP_IDX("GPIOE", 10, "bus", 5, GPIO_ACTIVE_HIGH), - { }, - }, -}; - -static struct platform_device *amlm5900_devices[] __initdata = { -#ifdef CONFIG_FB_S3C2410 - &s3c_device_lcd, -#endif - &s3c_device_adc, - &s3c_device_wdt, - &s3c_device_i2c0, - &s3c_device_ohci, - &s3c_device_rtc, - &s3c_device_usbgadget, - &s3c_device_sdi, - &amlm5900_device_nor, -}; - -static void __init amlm5900_map_io(void) -{ - s3c24xx_init_io(amlm5900_iodesc, ARRAY_SIZE(amlm5900_iodesc)); - s3c24xx_init_uarts(amlm5900_uartcfgs, ARRAY_SIZE(amlm5900_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); -} - -static void __init amlm5900_init_time(void) -{ - s3c2410_init_clocks(12000000); - samsung_timer_init(); -} - -#ifdef CONFIG_FB_S3C2410 -static struct s3c2410fb_display __initdata amlm5900_lcd_info = { - .width = 160, - .height = 160, - - .type = S3C2410_LCDCON1_STN4, - - .pixclock = 680000, /* HCLK = 100MHz */ - .xres = 160, - .yres = 160, - .bpp = 4, - .left_margin = 1 << (4 + 3), - .right_margin = 8 << 3, - .hsync_len = 48, - .upper_margin = 0, - .lower_margin = 0, - - .lcdcon5 = 0x00000001, -}; - -static struct s3c2410fb_mach_info __initdata amlm5900_fb_info = { - - .displays = &amlm5900_lcd_info, - .num_displays = 1, - .default_display = 0, - - .gpccon = 0xaaaaaaaa, - .gpccon_mask = 0xffffffff, - .gpccon_reg = S3C2410_GPCCON, - .gpcup = 0x0000ffff, - .gpcup_mask = 0xffffffff, - .gpcup_reg = S3C2410_GPCUP, - - .gpdcon = 0xaaaaaaaa, - .gpdcon_mask = 0xffffffff, - .gpdcon_reg = S3C2410_GPDCON, - .gpdup = 0x0000ffff, - .gpdup_mask = 0xffffffff, - .gpdup_reg = S3C2410_GPDUP, -}; -#endif - -static irqreturn_t -amlm5900_wake_interrupt(int irq, void *ignored) -{ - return IRQ_HANDLED; -} - -static void amlm5900_init_pm(void) -{ - int ret = 0; - - ret = request_irq(IRQ_EINT9, &amlm5900_wake_interrupt, - IRQF_TRIGGER_RISING | IRQF_SHARED, - "amlm5900_wakeup", &amlm5900_wake_interrupt); - if (ret != 0) { - printk(KERN_ERR "AML-M5900: no wakeup irq, %d?\n", ret); - } else { - enable_irq_wake(IRQ_EINT9); - /* configure the suspend/resume status pin */ - s3c_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT); - s3c_gpio_setpull(S3C2410_GPF(2), S3C_GPIO_PULL_UP); - } -} -static void __init amlm5900_init(void) -{ - amlm5900_init_pm(); -#ifdef CONFIG_FB_S3C2410 - s3c24xx_fb_set_platdata(&amlm5900_fb_info); -#endif - s3c_i2c0_set_platdata(NULL); - gpiod_add_lookup_table(&amlm5900_mmc_gpio_table); - platform_add_devices(amlm5900_devices, ARRAY_SIZE(amlm5900_devices)); -} - -MACHINE_START(AML_M5900, "AML_M5900") - .atag_offset = 0x100, - .map_io = amlm5900_map_io, - .init_irq = s3c2410_init_irq, - .init_machine = amlm5900_init, - .init_time = amlm5900_init_time, -MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c b/arch/arm/mach-s3c24xx/mach-anubis.c deleted file mode 100644 index 15cab0976941..000000000000 --- a/arch/arm/mach-s3c24xx/mach-anubis.c +++ /dev/null @@ -1,426 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright 2003-2009 Simtec Electronics -// http://armlinux.simtec.co.uk/ -// Ben Dooks - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include -#include -#include - -#include "anubis.h" -#include "common.h" -#include "simtec.h" - -#define COPYRIGHT ", Copyright 2005-2009 Simtec Electronics" - -static struct map_desc anubis_iodesc[] __initdata = { - /* ISA IO areas */ - - { - .virtual = (u32)S3C24XX_VA_ISA_BYTE, - .pfn = __phys_to_pfn(0x0), - .length = SZ_4M, - .type = MT_DEVICE, - }, { - .virtual = (u32)S3C24XX_VA_ISA_WORD, - .pfn = __phys_to_pfn(0x0), - .length = SZ_4M, - .type = MT_DEVICE, - }, - - /* we could possibly compress the next set down into a set of smaller tables - * pagetables, but that would mean using an L2 section, and it still means - * we cannot actually feed the same register to an LDR due to 16K spacing - */ - - /* CPLD control registers */ - - { - .virtual = (u32)ANUBIS_VA_CTRL1, - .pfn = __phys_to_pfn(ANUBIS_PA_CTRL1), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = (u32)ANUBIS_VA_IDREG, - .pfn = __phys_to_pfn(ANUBIS_PA_IDREG), - .length = SZ_4K, - .type = MT_DEVICE, - }, -}; - -#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK -#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB -#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE - -static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2, - }, - [1] = { - .hwport = 2, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2, - }, -}; - -/* NAND Flash on Anubis board */ - -static int external_map[] = { 2 }; -static int chip0_map[] = { 0 }; -static int chip1_map[] = { 1 }; - -static struct mtd_partition __initdata anubis_default_nand_part[] = { - [0] = { - .name = "Boot Agent", - .size = SZ_16K, - .offset = 0, - }, - [1] = { - .name = "/boot", - .size = SZ_4M - SZ_16K, - .offset = SZ_16K, - }, - [2] = { - .name = "user1", - .offset = SZ_4M, - .size = SZ_32M - SZ_4M, - }, - [3] = { - .name = "user2", - .offset = SZ_32M, - .size = MTDPART_SIZ_FULL, - } -}; - -static struct mtd_partition __initdata anubis_default_nand_part_large[] = { - [0] = { - .name = "Boot Agent", - .size = SZ_128K, - .offset = 0, - }, - [1] = { - .name = "/boot", - .size = SZ_4M - SZ_128K, - .offset = SZ_128K, - }, - [2] = { - .name = "user1", - .offset = SZ_4M, - .size = SZ_32M - SZ_4M, - }, - [3] = { - .name = "user2", - .offset = SZ_32M, - .size = MTDPART_SIZ_FULL, - } -}; - -/* the Anubis has 3 selectable slots for nand-flash, the two - * on-board chip areas, as well as the external slot. - * - * Note, there is no current hot-plug support for the External - * socket. -*/ - -static struct s3c2410_nand_set __initdata anubis_nand_sets[] = { - [1] = { - .name = "External", - .nr_chips = 1, - .nr_map = external_map, - .nr_partitions = ARRAY_SIZE(anubis_default_nand_part), - .partitions = anubis_default_nand_part, - }, - [0] = { - .name = "chip0", - .nr_chips = 1, - .nr_map = chip0_map, - .nr_partitions = ARRAY_SIZE(anubis_default_nand_part), - .partitions = anubis_default_nand_part, - }, - [2] = { - .name = "chip1", - .nr_chips = 1, - .nr_map = chip1_map, - .nr_partitions = ARRAY_SIZE(anubis_default_nand_part), - .partitions = anubis_default_nand_part, - }, -}; - -static void anubis_nand_select(struct s3c2410_nand_set *set, int slot) -{ - unsigned int tmp; - - slot = set->nr_map[slot] & 3; - - pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n", - slot, set, set->nr_map); - - tmp = __raw_readb(ANUBIS_VA_CTRL1); - tmp &= ~ANUBIS_CTRL1_NANDSEL; - tmp |= slot; - - pr_debug("anubis_nand: ctrl1 now %02x\n", tmp); - - __raw_writeb(tmp, ANUBIS_VA_CTRL1); -} - -static struct s3c2410_platform_nand __initdata anubis_nand_info = { - .tacls = 25, - .twrph0 = 55, - .twrph1 = 40, - .nr_sets = ARRAY_SIZE(anubis_nand_sets), - .sets = anubis_nand_sets, - .select_chip = anubis_nand_select, - .ecc_mode = NAND_ECC_SOFT, -}; - -/* IDE channels */ - -static struct pata_platform_info anubis_ide_platdata = { - .ioport_shift = 5, -}; - -static struct resource anubis_ide0_resource[] = { - [0] = DEFINE_RES_MEM(S3C2410_CS3, 8 * 32), - [2] = DEFINE_RES_MEM(S3C2410_CS3 + (1 << 26) + (6 * 32), 32), - [3] = DEFINE_RES_IRQ(ANUBIS_IRQ_IDE0), -}; - -static struct platform_device anubis_device_ide0 = { - .name = "pata_platform", - .id = 0, - .num_resources = ARRAY_SIZE(anubis_ide0_resource), - .resource = anubis_ide0_resource, - .dev = { - .platform_data = &anubis_ide_platdata, - .coherent_dma_mask = ~0, - }, -}; - -static struct resource anubis_ide1_resource[] = { - [0] = DEFINE_RES_MEM(S3C2410_CS4, 8 * 32), - [1] = DEFINE_RES_MEM(S3C2410_CS4 + (1 << 26) + (6 * 32), 32), - [2] = DEFINE_RES_IRQ(ANUBIS_IRQ_IDE0), -}; - -static struct platform_device anubis_device_ide1 = { - .name = "pata_platform", - .id = 1, - .num_resources = ARRAY_SIZE(anubis_ide1_resource), - .resource = anubis_ide1_resource, - .dev = { - .platform_data = &anubis_ide_platdata, - .coherent_dma_mask = ~0, - }, -}; - -/* Asix AX88796 10/100 ethernet controller */ - -static struct ax_plat_data anubis_asix_platdata = { - .flags = AXFLG_MAC_FROMDEV, - .wordlength = 2, - .dcr_val = 0x48, - .rcr_val = 0x40, -}; - -static struct resource anubis_asix_resource[] = { - [0] = DEFINE_RES_MEM(S3C2410_CS5, 0x20 * 0x20), - [1] = DEFINE_RES_IRQ(ANUBIS_IRQ_ASIX), -}; - -static struct platform_device anubis_device_asix = { - .name = "ax88796", - .id = 0, - .num_resources = ARRAY_SIZE(anubis_asix_resource), - .resource = anubis_asix_resource, - .dev = { - .platform_data = &anubis_asix_platdata, - } -}; - -/* SM501 */ - -static struct resource anubis_sm501_resource[] = { - [0] = DEFINE_RES_MEM(S3C2410_CS2, SZ_8M), - [1] = DEFINE_RES_MEM(S3C2410_CS2 + SZ_64M - SZ_2M, SZ_2M), - [2] = DEFINE_RES_IRQ(IRQ_EINT0), -}; - -static struct sm501_initdata anubis_sm501_initdata = { - .gpio_high = { - .set = 0x3F000000, /* 24bit panel */ - .mask = 0x0, - }, - .misc_timing = { - .set = 0x010100, /* SDRAM timing */ - .mask = 0x1F1F00, - }, - .misc_control = { - .set = SM501_MISC_PNL_24BIT, - .mask = 0, - }, - - .devices = SM501_USE_GPIO, - - /* set the SDRAM and bus clocks */ - .mclk = 72 * MHZ, - .m1xclk = 144 * MHZ, -}; - -static struct sm501_platdata_gpio_i2c anubis_sm501_gpio_i2c[] = { - [0] = { - .bus_num = 1, - .pin_scl = 44, - .pin_sda = 45, - }, - [1] = { - .bus_num = 2, - .pin_scl = 40, - .pin_sda = 41, - }, -}; - -static struct sm501_platdata anubis_sm501_platdata = { - .init = &anubis_sm501_initdata, - .gpio_base = -1, - .gpio_i2c = anubis_sm501_gpio_i2c, - .gpio_i2c_nr = ARRAY_SIZE(anubis_sm501_gpio_i2c), -}; - -static struct platform_device anubis_device_sm501 = { - .name = "sm501", - .id = 0, - .num_resources = ARRAY_SIZE(anubis_sm501_resource), - .resource = anubis_sm501_resource, - .dev = { - .platform_data = &anubis_sm501_platdata, - }, -}; - -/* Standard Anubis devices */ - -static struct platform_device *anubis_devices[] __initdata = { - &s3c2410_device_dclk, - &s3c_device_ohci, - &s3c_device_wdt, - &s3c_device_adc, - &s3c_device_i2c0, - &s3c_device_rtc, - &s3c_device_nand, - &anubis_device_ide0, - &anubis_device_ide1, - &anubis_device_asix, - &anubis_device_sm501, -}; - -/* I2C devices. */ - -static struct i2c_board_info anubis_i2c_devs[] __initdata = { - { - I2C_BOARD_INFO("tps65011", 0x48), - .irq = IRQ_EINT20, - } -}; - -/* Audio setup */ -static struct s3c24xx_audio_simtec_pdata __initdata anubis_audio = { - .have_mic = 1, - .have_lout = 1, - .output_cdclk = 1, - .use_mpllin = 1, - .amp_gpio = S3C2410_GPB(2), - .amp_gain[0] = S3C2410_GPD(10), - .amp_gain[1] = S3C2410_GPD(11), -}; - -static void __init anubis_map_io(void) -{ - s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc)); - s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); - - /* check for the newer revision boards with large page nand */ - - if ((__raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK) >= 4) { - printk(KERN_INFO "ANUBIS-B detected (revision %d)\n", - __raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK); - anubis_nand_sets[0].partitions = anubis_default_nand_part_large; - anubis_nand_sets[0].nr_partitions = ARRAY_SIZE(anubis_default_nand_part_large); - } else { - /* ensure that the GPIO is setup */ - gpio_request_one(S3C2410_GPA(0), GPIOF_OUT_INIT_HIGH, NULL); - gpio_free(S3C2410_GPA(0)); - } -} - -static void __init anubis_init_time(void) -{ - s3c2440_init_clocks(12000000); - samsung_timer_init(); -} - -static void __init anubis_init(void) -{ - s3c_i2c0_set_platdata(NULL); - s3c_nand_set_platdata(&anubis_nand_info); - simtec_audio_add(NULL, false, &anubis_audio); - - platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices)); - - i2c_register_board_info(0, anubis_i2c_devs, - ARRAY_SIZE(anubis_i2c_devs)); -} - - -MACHINE_START(ANUBIS, "Simtec-Anubis") - /* Maintainer: Ben Dooks */ - .atag_offset = 0x100, - .map_io = anubis_map_io, - .init_machine = anubis_init, - .init_irq = s3c2440_init_irq, - .init_time = anubis_init_time, -MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-at2440evb.c b/arch/arm/mach-s3c24xx/mach-at2440evb.c deleted file mode 100644 index 7fcb24a49ad8..000000000000 --- a/arch/arm/mach-s3c24xx/mach-at2440evb.c +++ /dev/null @@ -1,232 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (c) 2008 Ramax Lo -// Based on mach-anubis.c by Ben Dooks -// and modifications by SBZ and -// Weibing -// -// For product information, visit http://www.arm.com/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include - -#include "common.h" - -static struct map_desc at2440evb_iodesc[] __initdata = { - /* Nothing here */ -}; - -#define UCON S3C2410_UCON_DEFAULT -#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE) -#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE) - -static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2, - }, -}; - -/* NAND Flash on AT2440EVB board */ - -static struct mtd_partition __initdata at2440evb_default_nand_part[] = { - [0] = { - .name = "Boot Agent", - .size = SZ_256K, - .offset = 0, - }, - [1] = { - .name = "Kernel", - .size = SZ_2M, - .offset = SZ_256K, - }, - [2] = { - .name = "Root", - .offset = SZ_256K + SZ_2M, - .size = MTDPART_SIZ_FULL, - }, -}; - -static struct s3c2410_nand_set __initdata at2440evb_nand_sets[] = { - [0] = { - .name = "nand", - .nr_chips = 1, - .nr_partitions = ARRAY_SIZE(at2440evb_default_nand_part), - .partitions = at2440evb_default_nand_part, - }, -}; - -static struct s3c2410_platform_nand __initdata at2440evb_nand_info = { - .tacls = 25, - .twrph0 = 55, - .twrph1 = 40, - .nr_sets = ARRAY_SIZE(at2440evb_nand_sets), - .sets = at2440evb_nand_sets, - .ecc_mode = NAND_ECC_SOFT, -}; - -/* DM9000AEP 10/100 ethernet controller */ - -static struct resource at2440evb_dm9k_resource[] = { - [0] = DEFINE_RES_MEM(S3C2410_CS3, 4), - [1] = DEFINE_RES_MEM(S3C2410_CS3 + 4, 4), - [2] = DEFINE_RES_NAMED(IRQ_EINT7, 1, NULL, IORESOURCE_IRQ \ - | IORESOURCE_IRQ_HIGHEDGE), -}; - -static struct dm9000_plat_data at2440evb_dm9k_pdata = { - .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM), -}; - -static struct platform_device at2440evb_device_eth = { - .name = "dm9000", - .id = -1, - .num_resources = ARRAY_SIZE(at2440evb_dm9k_resource), - .resource = at2440evb_dm9k_resource, - .dev = { - .platform_data = &at2440evb_dm9k_pdata, - }, -}; - -static struct s3c24xx_mci_pdata at2440evb_mci_pdata __initdata = { - .set_power = s3c24xx_mci_def_set_power, -}; - -static struct gpiod_lookup_table at2440evb_mci_gpio_table = { - .dev_id = "s3c2410-sdi", - .table = { - /* Card detect S3C2410_GPG(10) */ - GPIO_LOOKUP("GPIOG", 10, "cd", GPIO_ACTIVE_LOW), - /* bus pins */ - GPIO_LOOKUP_IDX("GPIOE", 5, "bus", 0, GPIO_ACTIVE_HIGH), - GPIO_LOOKUP_IDX("GPIOE", 6, "bus", 1, GPIO_ACTIVE_HIGH), - GPIO_LOOKUP_IDX("GPIOE", 7, "bus", 2, GPIO_ACTIVE_HIGH), - GPIO_LOOKUP_IDX("GPIOE", 8, "bus", 3, GPIO_ACTIVE_HIGH), - GPIO_LOOKUP_IDX("GPIOE", 9, "bus", 4, GPIO_ACTIVE_HIGH), - GPIO_LOOKUP_IDX("GPIOE", 10, "bus", 5, GPIO_ACTIVE_HIGH), - { }, - }, -}; - - -/* 7" LCD panel */ - -static struct s3c2410fb_display at2440evb_lcd_cfg __initdata = { - - .lcdcon5 = S3C2410_LCDCON5_FRM565 | - S3C2410_LCDCON5_INVVLINE | - S3C2410_LCDCON5_INVVFRAME | - S3C2410_LCDCON5_PWREN | - S3C2410_LCDCON5_HWSWP, - - .type = S3C2410_LCDCON1_TFT, - - .width = 800, - .height = 480, - - .pixclock = 33333, /* HCLK 60 MHz, divisor 2 */ - .xres = 800, - .yres = 480, - .bpp = 16, - .left_margin = 88, - .right_margin = 40, - .hsync_len = 128, - .upper_margin = 32, - .lower_margin = 11, - .vsync_len = 2, -}; - -static struct s3c2410fb_mach_info at2440evb_fb_info __initdata = { - .displays = &at2440evb_lcd_cfg, - .num_displays = 1, - .default_display = 0, -}; - -static struct platform_device *at2440evb_devices[] __initdata = { - &s3c_device_ohci, - &s3c_device_wdt, - &s3c_device_adc, - &s3c_device_i2c0, - &s3c_device_rtc, - &s3c_device_nand, - &s3c_device_sdi, - &s3c_device_lcd, - &at2440evb_device_eth, -}; - -static void __init at2440evb_map_io(void) -{ - s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc)); - s3c24xx_init_uarts(at2440evb_uartcfgs, ARRAY_SIZE(at2440evb_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); -} - -static void __init at2440evb_init_time(void) -{ - s3c2440_init_clocks(16934400); - samsung_timer_init(); -} - -static void __init at2440evb_init(void) -{ - s3c24xx_fb_set_platdata(&at2440evb_fb_info); - gpiod_add_lookup_table(&at2440evb_mci_gpio_table); - s3c24xx_mci_set_platdata(&at2440evb_mci_pdata); - s3c_nand_set_platdata(&at2440evb_nand_info); - s3c_i2c0_set_platdata(NULL); - - platform_add_devices(at2440evb_devices, ARRAY_SIZE(at2440evb_devices)); -} - - -MACHINE_START(AT2440EVB, "AT2440EVB") - .atag_offset = 0x100, - .map_io = at2440evb_map_io, - .init_machine = at2440evb_init, - .init_irq = s3c2440_init_irq, - .init_time = at2440evb_init_time, -MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-bast.c b/arch/arm/mach-s3c24xx/mach-bast.c deleted file mode 100644 index 7e3ce48539c4..000000000000 --- a/arch/arm/mach-s3c24xx/mach-bast.c +++ /dev/null @@ -1,587 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright 2003-2008 Simtec Electronics -// Ben Dooks -// -// http://www.simtec.co.uk/products/EB2410ITX/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include - -#include "bast.h" -#include "common.h" -#include "simtec.h" - -#define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics" - -/* macros for virtual address mods for the io space entries */ -#define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5) -#define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4) -#define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3) -#define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2) - -/* macros to modify the physical addresses for io space */ - -#define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2)) -#define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3)) -#define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4)) -#define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5)) - -static struct map_desc bast_iodesc[] __initdata = { - /* ISA IO areas */ - { - .virtual = (u32)S3C24XX_VA_ISA_BYTE, - .pfn = PA_CS2(BAST_PA_ISAIO), - .length = SZ_16M, - .type = MT_DEVICE, - }, { - .virtual = (u32)S3C24XX_VA_ISA_WORD, - .pfn = PA_CS3(BAST_PA_ISAIO), - .length = SZ_16M, - .type = MT_DEVICE, - }, - /* bast CPLD control registers, and external interrupt controls */ - { - .virtual = (u32)BAST_VA_CTRL1, - .pfn = __phys_to_pfn(BAST_PA_CTRL1), - .length = SZ_1M, - .type = MT_DEVICE, - }, { - .virtual = (u32)BAST_VA_CTRL2, - .pfn = __phys_to_pfn(BAST_PA_CTRL2), - .length = SZ_1M, - .type = MT_DEVICE, - }, { - .virtual = (u32)BAST_VA_CTRL3, - .pfn = __phys_to_pfn(BAST_PA_CTRL3), - .length = SZ_1M, - .type = MT_DEVICE, - }, { - .virtual = (u32)BAST_VA_CTRL4, - .pfn = __phys_to_pfn(BAST_PA_CTRL4), - .length = SZ_1M, - .type = MT_DEVICE, - }, - /* PC104 IRQ mux */ - { - .virtual = (u32)BAST_VA_PC104_IRQREQ, - .pfn = __phys_to_pfn(BAST_PA_PC104_IRQREQ), - .length = SZ_1M, - .type = MT_DEVICE, - }, { - .virtual = (u32)BAST_VA_PC104_IRQRAW, - .pfn = __phys_to_pfn(BAST_PA_PC104_IRQRAW), - .length = SZ_1M, - .type = MT_DEVICE, - }, { - .virtual = (u32)BAST_VA_PC104_IRQMASK, - .pfn = __phys_to_pfn(BAST_PA_PC104_IRQMASK), - .length = SZ_1M, - .type = MT_DEVICE, - }, - - /* peripheral space... one for each of fast/slow/byte/16bit */ - /* note, ide is only decoded in word space, even though some registers - * are only 8bit */ - - /* slow, byte */ - { VA_C2(BAST_VA_ISAIO), PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, - { VA_C2(BAST_VA_ISAMEM), PA_CS2(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE }, - { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE }, - - /* slow, word */ - { VA_C3(BAST_VA_ISAIO), PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, - { VA_C3(BAST_VA_ISAMEM), PA_CS3(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE }, - { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE }, - - /* fast, byte */ - { VA_C4(BAST_VA_ISAIO), PA_CS4(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, - { VA_C4(BAST_VA_ISAMEM), PA_CS4(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE }, - { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE }, - - /* fast, word */ - { VA_C5(BAST_VA_ISAIO), PA_CS5(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, - { VA_C5(BAST_VA_ISAMEM), PA_CS5(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE }, - { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE }, -}; - -#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK -#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB -#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE - -static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - /* port 2 is not actually used */ - [2] = { - .hwport = 2, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - } -}; - -/* NAND Flash on BAST board */ - -#ifdef CONFIG_PM -static int bast_pm_suspend(void) -{ - /* ensure that an nRESET is not generated on resume. */ - gpio_direction_output(S3C2410_GPA(21), 1); - return 0; -} - -static void bast_pm_resume(void) -{ - s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT); -} - -#else -#define bast_pm_suspend NULL -#define bast_pm_resume NULL -#endif - -static struct syscore_ops bast_pm_syscore_ops = { - .suspend = bast_pm_suspend, - .resume = bast_pm_resume, -}; - -static int smartmedia_map[] = { 0 }; -static int chip0_map[] = { 1 }; -static int chip1_map[] = { 2 }; -static int chip2_map[] = { 3 }; - -static struct mtd_partition __initdata bast_default_nand_part[] = { - [0] = { - .name = "Boot Agent", - .size = SZ_16K, - .offset = 0, - }, - [1] = { - .name = "/boot", - .size = SZ_4M - SZ_16K, - .offset = SZ_16K, - }, - [2] = { - .name = "user", - .offset = SZ_4M, - .size = MTDPART_SIZ_FULL, - } -}; - -/* the bast has 4 selectable slots for nand-flash, the three - * on-board chip areas, as well as the external SmartMedia - * slot. - * - * Note, there is no current hot-plug support for the SmartMedia - * socket. -*/ - -static struct s3c2410_nand_set __initdata bast_nand_sets[] = { - [0] = { - .name = "SmartMedia", - .nr_chips = 1, - .nr_map = smartmedia_map, - .options = NAND_SCAN_SILENT_NODEV, - .nr_partitions = ARRAY_SIZE(bast_default_nand_part), - .partitions = bast_default_nand_part, - }, - [1] = { - .name = "chip0", - .nr_chips = 1, - .nr_map = chip0_map, - .nr_partitions = ARRAY_SIZE(bast_default_nand_part), - .partitions = bast_default_nand_part, - }, - [2] = { - .name = "chip1", - .nr_chips = 1, - .nr_map = chip1_map, - .options = NAND_SCAN_SILENT_NODEV, - .nr_partitions = ARRAY_SIZE(bast_default_nand_part), - .partitions = bast_default_nand_part, - }, - [3] = { - .name = "chip2", - .nr_chips = 1, - .nr_map = chip2_map, - .options = NAND_SCAN_SILENT_NODEV, - .nr_partitions = ARRAY_SIZE(bast_default_nand_part), - .partitions = bast_default_nand_part, - } -}; - -static void bast_nand_select(struct s3c2410_nand_set *set, int slot) -{ - unsigned int tmp; - - slot = set->nr_map[slot] & 3; - - pr_debug("bast_nand: selecting slot %d (set %p,%p)\n", - slot, set, set->nr_map); - - tmp = __raw_readb(BAST_VA_CTRL2); - tmp &= BAST_CPLD_CTLR2_IDERST; - tmp |= slot; - tmp |= BAST_CPLD_CTRL2_WNAND; - - pr_debug("bast_nand: ctrl2 now %02x\n", tmp); - - __raw_writeb(tmp, BAST_VA_CTRL2); -} - -static struct s3c2410_platform_nand __initdata bast_nand_info = { - .tacls = 30, - .twrph0 = 60, - .twrph1 = 60, - .nr_sets = ARRAY_SIZE(bast_nand_sets), - .sets = bast_nand_sets, - .select_chip = bast_nand_select, - .ecc_mode = NAND_ECC_SOFT, -}; - -/* DM9000 */ - -static struct resource bast_dm9k_resource[] = { - [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000, 4), - [1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000 + 0x40, 0x40), - [2] = DEFINE_RES_NAMED(BAST_IRQ_DM9000 , 1, NULL, IORESOURCE_IRQ \ - | IORESOURCE_IRQ_HIGHLEVEL), -}; - -/* for the moment we limit ourselves to 16bit IO until some - * better IO routines can be written and tested -*/ - -static struct dm9000_plat_data bast_dm9k_platdata = { - .flags = DM9000_PLATF_16BITONLY, -}; - -static struct platform_device bast_device_dm9k = { - .name = "dm9000", - .id = 0, - .num_resources = ARRAY_SIZE(bast_dm9k_resource), - .resource = bast_dm9k_resource, - .dev = { - .platform_data = &bast_dm9k_platdata, - } -}; - -/* serial devices */ - -#define SERIAL_BASE (S3C2410_CS2 + BAST_PA_SUPERIO) -#define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ) -#define SERIAL_CLK (1843200) - -static struct plat_serial8250_port bast_sio_data[] = { - [0] = { - .mapbase = SERIAL_BASE + 0x2f8, - .irq = BAST_IRQ_PCSERIAL1, - .flags = SERIAL_FLAGS, - .iotype = UPIO_MEM, - .regshift = 0, - .uartclk = SERIAL_CLK, - }, - [1] = { - .mapbase = SERIAL_BASE + 0x3f8, - .irq = BAST_IRQ_PCSERIAL2, - .flags = SERIAL_FLAGS, - .iotype = UPIO_MEM, - .regshift = 0, - .uartclk = SERIAL_CLK, - }, - { } -}; - -static struct platform_device bast_sio = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = &bast_sio_data, - }, -}; - -/* we have devices on the bus which cannot work much over the - * standard 100KHz i2c bus frequency -*/ - -static struct s3c2410_platform_i2c __initdata bast_i2c_info = { - .flags = 0, - .slave_addr = 0x10, - .frequency = 100*1000, -}; - -/* Asix AX88796 10/100 ethernet controller */ - -static struct ax_plat_data bast_asix_platdata = { - .flags = AXFLG_MAC_FROMDEV, - .wordlength = 2, - .dcr_val = 0x48, - .rcr_val = 0x40, -}; - -static struct resource bast_asix_resource[] = { - [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET, 0x18 * 0x20), - [1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20), 1), - [2] = DEFINE_RES_IRQ(BAST_IRQ_ASIX), -}; - -static struct platform_device bast_device_asix = { - .name = "ax88796", - .id = 0, - .num_resources = ARRAY_SIZE(bast_asix_resource), - .resource = bast_asix_resource, - .dev = { - .platform_data = &bast_asix_platdata - } -}; - -/* Asix AX88796 10/100 ethernet controller parallel port */ - -static struct resource bast_asixpp_resource[] = { - [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20), \ - 0x30 * 0x20), -}; - -static struct platform_device bast_device_axpp = { - .name = "ax88796-pp", - .id = 0, - .num_resources = ARRAY_SIZE(bast_asixpp_resource), - .resource = bast_asixpp_resource, -}; - -/* LCD/VGA controller */ - -static struct s3c2410fb_display __initdata bast_lcd_info[] = { - { - .type = S3C2410_LCDCON1_TFT, - .width = 640, - .height = 480, - - .pixclock = 33333, - .xres = 640, - .yres = 480, - .bpp = 4, - .left_margin = 40, - .right_margin = 20, - .hsync_len = 88, - .upper_margin = 30, - .lower_margin = 32, - .vsync_len = 3, - - .lcdcon5 = 0x00014b02, - }, - { - .type = S3C2410_LCDCON1_TFT, - .width = 640, - .height = 480, - - .pixclock = 33333, - .xres = 640, - .yres = 480, - .bpp = 8, - .left_margin = 40, - .right_margin = 20, - .hsync_len = 88, - .upper_margin = 30, - .lower_margin = 32, - .vsync_len = 3, - - .lcdcon5 = 0x00014b02, - }, - { - .type = S3C2410_LCDCON1_TFT, - .width = 640, - .height = 480, - - .pixclock = 33333, - .xres = 640, - .yres = 480, - .bpp = 16, - .left_margin = 40, - .right_margin = 20, - .hsync_len = 88, - .upper_margin = 30, - .lower_margin = 32, - .vsync_len = 3, - - .lcdcon5 = 0x00014b02, - }, -}; - -/* LCD/VGA controller */ - -static struct s3c2410fb_mach_info __initdata bast_fb_info = { - - .displays = bast_lcd_info, - .num_displays = ARRAY_SIZE(bast_lcd_info), - .default_display = 1, -}; - -/* I2C devices fitted. */ - -static struct i2c_board_info bast_i2c_devs[] __initdata = { - { - I2C_BOARD_INFO("tlv320aic23", 0x1a), - }, { - I2C_BOARD_INFO("simtec-pmu", 0x6b), - }, { - I2C_BOARD_INFO("ch7013", 0x75), - }, -}; - -static struct s3c_hwmon_pdata bast_hwmon_info = { - /* LCD contrast (0-6.6V) */ - .in[0] = &(struct s3c_hwmon_chcfg) { - .name = "lcd-contrast", - .mult = 3300, - .div = 512, - }, - /* LED current feedback */ - .in[1] = &(struct s3c_hwmon_chcfg) { - .name = "led-feedback", - .mult = 3300, - .div = 1024, - }, - /* LCD feedback (0-6.6V) */ - .in[2] = &(struct s3c_hwmon_chcfg) { - .name = "lcd-feedback", - .mult = 3300, - .div = 512, - }, - /* Vcore (1.8-2.0V), Vref 3.3V */ - .in[3] = &(struct s3c_hwmon_chcfg) { - .name = "vcore", - .mult = 3300, - .div = 1024, - }, -}; - -/* Standard BAST devices */ -// cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0 - -static struct platform_device *bast_devices[] __initdata = { - &s3c2410_device_dclk, - &s3c_device_ohci, - &s3c_device_lcd, - &s3c_device_wdt, - &s3c_device_i2c0, - &s3c_device_rtc, - &s3c_device_nand, - &s3c_device_adc, - &s3c_device_hwmon, - &bast_device_dm9k, - &bast_device_asix, - &bast_device_axpp, - &bast_sio, -}; - -static struct s3c_cpufreq_board __initdata bast_cpufreq = { - .refresh = 7800, /* 7.8usec */ - .auto_io = 1, - .need_io = 1, -}; - -static struct s3c24xx_audio_simtec_pdata __initdata bast_audio = { - .have_mic = 1, - .have_lout = 1, -}; - -static void __init bast_map_io(void) -{ - s3c_hwmon_set_platdata(&bast_hwmon_info); - - s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc)); - s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); -} - -static void __init bast_init_time(void) -{ - s3c2410_init_clocks(12000000); - samsung_timer_init(); -} - -static void __init bast_init(void) -{ - register_syscore_ops(&bast_pm_syscore_ops); - - s3c_i2c0_set_platdata(&bast_i2c_info); - s3c_nand_set_platdata(&bast_nand_info); - s3c24xx_fb_set_platdata(&bast_fb_info); - platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices)); - - i2c_register_board_info(0, bast_i2c_devs, - ARRAY_SIZE(bast_i2c_devs)); - - usb_simtec_init(); - nor_simtec_init(); - simtec_audio_add(NULL, true, &bast_audio); - - WARN_ON(gpio_request(S3C2410_GPA(21), "bast nreset")); - - s3c_cpufreq_setboard(&bast_cpufreq); -} - -MACHINE_START(BAST, "Simtec-BAST") - /* Maintainer: Ben Dooks */ - .atag_offset = 0x100, - .map_io = bast_map_io, - .init_irq = s3c2410_init_irq, - .init_machine = bast_init, - .init_time = bast_init_time, -MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-gta02.c b/arch/arm/mach-s3c24xx/mach-gta02.c deleted file mode 100644 index a28e92142b04..000000000000 --- a/arch/arm/mach-s3c24xx/mach-gta02.c +++ /dev/null @@ -1,580 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// S3C2442 Machine Support for Openmoko GTA02 / FreeRunner. -// -// Copyright (C) 2006-2009 by Openmoko, Inc. -// Authors: Harald Welte -// Andy Green -// Werner Almesberger -// All rights reserved. - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include - -#include -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include - -#include "common.h" -#include "gta02.h" - -static struct pcf50633 *gta02_pcf; - -/* - * This gets called frequently when we paniced. - */ - -static long gta02_panic_blink(int state) -{ - long delay = 0; - char led; - - led = (state) ? 1 : 0; - gpio_direction_output(GTA02_GPIO_AUX_LED, led); - - return delay; -} - - -static struct map_desc gta02_iodesc[] __initdata = { - { - .virtual = 0xe0000000, - .pfn = __phys_to_pfn(S3C2410_CS3 + 0x01000000), - .length = SZ_1M, - .type = MT_DEVICE - }, -}; - -#define UCON (S3C2410_UCON_DEFAULT | S3C2443_UCON_RXERR_IRQEN) -#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB) -#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE) - -static struct s3c2410_uartcfg gta02_uartcfgs[] = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - [2] = { - .hwport = 2, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, -}; - -#ifdef CONFIG_CHARGER_PCF50633 -/* - * On GTA02 the 1A charger features a 48K resistor to 0V on the ID pin. - * We use this to recognize that we can pull 1A from the USB socket. - * - * These constants are the measured pcf50633 ADC levels with the 1A - * charger / 48K resistor, and with no pulldown resistor. - */ - -#define ADC_NOM_CHG_DETECT_1A 6 -#define ADC_NOM_CHG_DETECT_USB 43 - -#ifdef CONFIG_PCF50633_ADC -static void -gta02_configure_pmu_for_charger(struct pcf50633 *pcf, void *unused, int res) -{ - int ma; - - /* Interpret charger type */ - if (res < ((ADC_NOM_CHG_DETECT_USB + ADC_NOM_CHG_DETECT_1A) / 2)) { - - /* - * Sanity - stop GPO driving out now that we have a 1A charger - * GPO controls USB Host power generation on GTA02 - */ - pcf50633_gpio_set(pcf, PCF50633_GPO, 0); - - ma = 1000; - } else - ma = 100; - - pcf50633_mbc_usb_curlim_set(pcf, ma); -} -#endif - -static struct delayed_work gta02_charger_work; -static int gta02_usb_vbus_draw; - -static void gta02_charger_worker(struct work_struct *work) -{ - if (gta02_usb_vbus_draw) { - pcf50633_mbc_usb_curlim_set(gta02_pcf, gta02_usb_vbus_draw); - return; - } - -#ifdef CONFIG_PCF50633_ADC - pcf50633_adc_async_read(gta02_pcf, - PCF50633_ADCC1_MUX_ADCIN1, - PCF50633_ADCC1_AVERAGE_16, - gta02_configure_pmu_for_charger, - NULL); -#else - /* - * If the PCF50633 ADC is disabled we fallback to a - * 100mA limit for safety. - */ - pcf50633_mbc_usb_curlim_set(gta02_pcf, 100); -#endif -} - -#define GTA02_CHARGER_CONFIGURE_TIMEOUT ((3000 * HZ) / 1000) - -static void gta02_pmu_event_callback(struct pcf50633 *pcf, int irq) -{ - if (irq == PCF50633_IRQ_USBINS) { - schedule_delayed_work(>a02_charger_work, - GTA02_CHARGER_CONFIGURE_TIMEOUT); - - return; - } - - if (irq == PCF50633_IRQ_USBREM) { - cancel_delayed_work_sync(>a02_charger_work); - gta02_usb_vbus_draw = 0; - } -} - -static void gta02_udc_vbus_draw(unsigned int ma) -{ - if (!gta02_pcf) - return; - - gta02_usb_vbus_draw = ma; - - schedule_delayed_work(>a02_charger_work, - GTA02_CHARGER_CONFIGURE_TIMEOUT); -} -#else /* !CONFIG_CHARGER_PCF50633 */ -#define gta02_pmu_event_callback NULL -#define gta02_udc_vbus_draw NULL -#endif - -static char *gta02_batteries[] = { - "battery", -}; - -static struct pcf50633_bl_platform_data gta02_backlight_data = { - .default_brightness = 0x3f, - .default_brightness_limit = 0, - .ramp_time = 5, -}; - -static struct pcf50633_platform_data gta02_pcf_pdata = { - .resumers = { - [0] = PCF50633_INT1_USBINS | - PCF50633_INT1_USBREM | - PCF50633_INT1_ALARM, - [1] = PCF50633_INT2_ONKEYF, - [2] = PCF50633_INT3_ONKEY1S, - [3] = PCF50633_INT4_LOWSYS | - PCF50633_INT4_LOWBAT | - PCF50633_INT4_HIGHTMP, - }, - - .batteries = gta02_batteries, - .num_batteries = ARRAY_SIZE(gta02_batteries), - - .charger_reference_current_ma = 1000, - - .backlight_data = >a02_backlight_data, - - .reg_init_data = { - [PCF50633_REGULATOR_AUTO] = { - .constraints = { - .min_uV = 3300000, - .max_uV = 3300000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .always_on = 1, - .apply_uV = 1, - }, - }, - [PCF50633_REGULATOR_DOWN1] = { - .constraints = { - .min_uV = 1300000, - .max_uV = 1600000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .always_on = 1, - .apply_uV = 1, - }, - }, - [PCF50633_REGULATOR_DOWN2] = { - .constraints = { - .min_uV = 1800000, - .max_uV = 1800000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .apply_uV = 1, - .always_on = 1, - }, - }, - [PCF50633_REGULATOR_HCLDO] = { - .constraints = { - .min_uV = 2000000, - .max_uV = 3300000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - }, - }, - [PCF50633_REGULATOR_LDO1] = { - .constraints = { - .min_uV = 3300000, - .max_uV = 3300000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .apply_uV = 1, - }, - }, - [PCF50633_REGULATOR_LDO2] = { - .constraints = { - .min_uV = 3300000, - .max_uV = 3300000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .apply_uV = 1, - }, - }, - [PCF50633_REGULATOR_LDO3] = { - .constraints = { - .min_uV = 3000000, - .max_uV = 3000000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .apply_uV = 1, - }, - }, - [PCF50633_REGULATOR_LDO4] = { - .constraints = { - .min_uV = 3200000, - .max_uV = 3200000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .apply_uV = 1, - }, - }, - [PCF50633_REGULATOR_LDO5] = { - .constraints = { - .min_uV = 3000000, - .max_uV = 3000000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .apply_uV = 1, - }, - }, - [PCF50633_REGULATOR_LDO6] = { - .constraints = { - .min_uV = 3000000, - .max_uV = 3000000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - }, - }, - [PCF50633_REGULATOR_MEMLDO] = { - .constraints = { - .min_uV = 1800000, - .max_uV = 1800000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - }, - }, - - }, - .mbc_event_callback = gta02_pmu_event_callback, -}; - - -/* NOR Flash. */ - -#define GTA02_FLASH_BASE 0x18000000 /* GCS3 */ -#define GTA02_FLASH_SIZE 0x200000 /* 2MBytes */ - -static struct physmap_flash_data gta02_nor_flash_data = { - .width = 2, -}; - -static struct resource gta02_nor_flash_resource = - DEFINE_RES_MEM(GTA02_FLASH_BASE, GTA02_FLASH_SIZE); - -static struct platform_device gta02_nor_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = >a02_nor_flash_data, - }, - .resource = >a02_nor_flash_resource, - .num_resources = 1, -}; - - -static struct platform_device s3c24xx_pwm_device = { - .name = "s3c24xx_pwm", - .num_resources = 0, -}; - -static struct platform_device gta02_dfbmcs320_device = { - .name = "dfbmcs320", -}; - -static struct i2c_board_info gta02_i2c_devs[] __initdata = { - { - I2C_BOARD_INFO("pcf50633", 0x73), - .irq = GTA02_IRQ_PCF50633, - .platform_data = >a02_pcf_pdata, - }, - { - I2C_BOARD_INFO("wm8753", 0x1a), - }, -}; - -static struct s3c2410_nand_set __initdata gta02_nand_sets[] = { - [0] = { - /* - * This name is also hard-coded in the boot loaders, so - * changing it would would require all users to upgrade - * their boot loaders, some of which are stored in a NOR - * that is considered to be immutable. - */ - .name = "neo1973-nand", - .nr_chips = 1, - .flash_bbt = 1, - }, -}; - -/* - * Choose a set of timings derived from S3C@2442B MCP54 - * data sheet (K5D2G13ACM-D075 MCP Memory). - */ - -static struct s3c2410_platform_nand __initdata gta02_nand_info = { - .tacls = 0, - .twrph0 = 25, - .twrph1 = 15, - .nr_sets = ARRAY_SIZE(gta02_nand_sets), - .sets = gta02_nand_sets, - .ecc_mode = NAND_ECC_SOFT, -}; - - -/* Get PMU to set USB current limit accordingly. */ -static struct s3c2410_udc_mach_info gta02_udc_cfg __initdata = { - .vbus_draw = gta02_udc_vbus_draw, - .pullup_pin = GTA02_GPIO_USB_PULLUP, -}; - -/* USB */ -static struct s3c2410_hcd_info gta02_usb_info __initdata = { - .port[0] = { - .flags = S3C_HCDFLG_USED, - }, - .port[1] = { - .flags = 0, - }, -}; - -/* Touchscreen */ -static struct s3c2410_ts_mach_info gta02_ts_info = { - .delay = 10000, - .presc = 0xff, /* slow as we can go */ - .oversampling_shift = 2, -}; - -/* Buttons */ -static struct gpio_keys_button gta02_buttons[] = { - { - .gpio = GTA02_GPIO_AUX_KEY, - .code = KEY_PHONE, - .desc = "Aux", - .type = EV_KEY, - .debounce_interval = 100, - }, - { - .gpio = GTA02_GPIO_HOLD_KEY, - .code = KEY_PAUSE, - .desc = "Hold", - .type = EV_KEY, - .debounce_interval = 100, - }, -}; - -static struct gpio_keys_platform_data gta02_buttons_pdata = { - .buttons = gta02_buttons, - .nbuttons = ARRAY_SIZE(gta02_buttons), -}; - -static struct platform_device gta02_buttons_device = { - .name = "gpio-keys", - .id = -1, - .dev = { - .platform_data = >a02_buttons_pdata, - }, -}; - -static struct gpiod_lookup_table gta02_audio_gpio_table = { - .dev_id = "neo1973-audio", - .table = { - GPIO_LOOKUP("GPIOJ", 2, "amp-shut", GPIO_ACTIVE_HIGH), - GPIO_LOOKUP("GPIOJ", 1, "hp", GPIO_ACTIVE_HIGH), - { }, - }, -}; - -static struct platform_device gta02_audio = { - .name = "neo1973-audio", - .id = -1, -}; - -static struct gpiod_lookup_table gta02_mmc_gpio_table = { - .dev_id = "s3c2410-sdi", - .table = { - /* bus pins */ - GPIO_LOOKUP_IDX("GPIOE", 5, "bus", 0, GPIO_ACTIVE_HIGH), - GPIO_LOOKUP_IDX("GPIOE", 6, "bus", 1, GPIO_ACTIVE_HIGH), - GPIO_LOOKUP_IDX("GPIOE", 7, "bus", 2, GPIO_ACTIVE_HIGH), - GPIO_LOOKUP_IDX("GPIOE", 8, "bus", 3, GPIO_ACTIVE_HIGH), - GPIO_LOOKUP_IDX("GPIOE", 9, "bus", 4, GPIO_ACTIVE_HIGH), - GPIO_LOOKUP_IDX("GPIOE", 10, "bus", 5, GPIO_ACTIVE_HIGH), - { }, - }, -}; - -static void __init gta02_map_io(void) -{ - s3c24xx_init_io(gta02_iodesc, ARRAY_SIZE(gta02_iodesc)); - s3c24xx_init_uarts(gta02_uartcfgs, ARRAY_SIZE(gta02_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); -} - - -/* These are the guys that don't need to be children of PMU. */ - -static struct platform_device *gta02_devices[] __initdata = { - &s3c_device_ohci, - &s3c_device_wdt, - &s3c_device_sdi, - &s3c_device_usbgadget, - &s3c_device_nand, - >a02_nor_flash, - &s3c24xx_pwm_device, - &s3c_device_iis, - &s3c_device_i2c0, - >a02_dfbmcs320_device, - >a02_buttons_device, - &s3c_device_adc, - &s3c_device_ts, - >a02_audio, -}; - -static void gta02_poweroff(void) -{ - pcf50633_reg_set_bit_mask(gta02_pcf, PCF50633_REG_OOCSHDWN, 1, 1); -} - -static void __init gta02_machine_init(void) -{ - /* Set the panic callback to turn AUX LED on or off. */ - panic_blink = gta02_panic_blink; - - s3c_pm_init(); - -#ifdef CONFIG_CHARGER_PCF50633 - INIT_DELAYED_WORK(>a02_charger_work, gta02_charger_worker); -#endif - - s3c24xx_udc_set_platdata(>a02_udc_cfg); - s3c24xx_ts_set_platdata(>a02_ts_info); - s3c_ohci_set_platdata(>a02_usb_info); - s3c_nand_set_platdata(>a02_nand_info); - s3c_i2c0_set_platdata(NULL); - - i2c_register_board_info(0, gta02_i2c_devs, ARRAY_SIZE(gta02_i2c_devs)); - - /* Configure the I2S pins (GPE0...GPE4) in correct mode */ - s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2), - S3C_GPIO_PULL_NONE); - - gpiod_add_lookup_table(>a02_audio_gpio_table); - gpiod_add_lookup_table(>a02_mmc_gpio_table); - platform_add_devices(gta02_devices, ARRAY_SIZE(gta02_devices)); - pm_power_off = gta02_poweroff; - - regulator_has_full_constraints(); -} - -static void __init gta02_init_time(void) -{ - s3c2442_init_clocks(12000000); - samsung_timer_init(); -} - -MACHINE_START(NEO1973_GTA02, "GTA02") - /* Maintainer: Nelson Castillo */ - .atag_offset = 0x100, - .map_io = gta02_map_io, - .init_irq = s3c2442_init_irq, - .init_machine = gta02_machine_init, - .init_time = gta02_init_time, -MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c deleted file mode 100644 index 3cb56fc9db5c..000000000000 --- a/arch/arm/mach-s3c24xx/mach-h1940.c +++ /dev/null @@ -1,793 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (c) 2003-2005 Simtec Electronics -// Ben Dooks -// -// https://www.handhelds.org/projects/h1940.html - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include