From 1f2d6c49f087c84ed54ad3e0801faeca3e2ccfdd Mon Sep 17 00:00:00 2001 From: Changhwan Youn Date: Mon, 29 Nov 2010 17:04:46 +0900 Subject: ARM: S5PV310: Limit the irqs which support cascade interrupt The irqs from SPI(0) to SPI(39) and SPI(51), SPI(53) are connected to the interrupt combiner. This patch limits the irqs which should be initialized to support cascade interrupt. Signed-off-by: Changhwan Youn Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/cpu.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm/mach-s5pv310/cpu.c') diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-s5pv310/cpu.c index 82ce4aa6d61a..3d0c1cb68d9e 100644 --- a/arch/arm/mach-s5pv310/cpu.c +++ b/arch/arm/mach-s5pv310/cpu.c @@ -127,6 +127,15 @@ void __init s5pv310_init_irq(void) gic_cpu_init(0, S5P_VA_GIC_CPU); for (irq = 0; irq < MAX_COMBINER_NR; irq++) { + + /* + * From SPI(0) to SPI(39) and SPI(51), SPI(53) are + * connected to the interrupt combiner. These irqs + * should be initialized to support cascade interrupt. + */ + if ((irq >= 40) && !(irq == 51) && !(irq == 53)) + continue; + combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq), COMBINER_IRQ(irq, 0)); combiner_cascade_irq(irq, IRQ_SPI(irq)); -- cgit From a50eb1c7680973f5441ca20ac4da0af2055d0d87 Mon Sep 17 00:00:00 2001 From: Changhwan Youn Date: Fri, 26 Nov 2010 13:21:53 +0900 Subject: ARM: S5PV310: Set bit 22 in the PL310 (cache controller) AuxCtlr register This patch is applied according to the commit 1a8e41cd672f894bbd74874eac601e6cedf838fb (ARM: 6395/1: VExpress: Set bit 22 in the PL310 (cache controller) AuxCtlr register). Actually, S5PV310 has same cache controller(PL310). Following is from Catalin Marinas' commit. Clearing bit 22 in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a Cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption. Signed-off-by: Changhwan Youn Cc: Cc: Catalin Marinas Cc: Russell King Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mach-s5pv310/cpu.c') diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-s5pv310/cpu.c index 82ce4aa6d61a..b2a37d0f9d7a 100644 --- a/arch/arm/mach-s5pv310/cpu.c +++ b/arch/arm/mach-s5pv310/cpu.c @@ -168,7 +168,7 @@ static int __init s5pv310_l2x0_cache_init(void) __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, S5P_VA_L2CC + L2X0_POWER_CTRL); - l2x0_init(S5P_VA_L2CC, 0x7C070001, 0xC200ffff); + l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff); return 0; } -- cgit From d6d8b481999507a20012b7ee924bdaf5bfb52a05 Mon Sep 17 00:00:00 2001 From: Changhwan Youn Date: Fri, 3 Dec 2010 17:15:40 +0900 Subject: ARM: S5PV310: Add support Power Domain This patch adds support Power Domain for S5PV310 and S5PC210. Signed-off-by: Changhwan Youn Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/cpu.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/mach-s5pv310/cpu.c') diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-s5pv310/cpu.c index b2a37d0f9d7a..7b6e066e2271 100644 --- a/arch/arm/mach-s5pv310/cpu.c +++ b/arch/arm/mach-s5pv310/cpu.c @@ -42,6 +42,11 @@ static struct map_desc s5pv310_iodesc[] __initdata = { .pfn = __phys_to_pfn(S5PV310_PA_CMU), .length = SZ_128K, .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_PMU, + .pfn = __phys_to_pfn(S5PV310_PA_PMU), + .length = SZ_64K, + .type = MT_DEVICE, }, { .virtual = (unsigned long)S5P_VA_COMBINER_BASE, .pfn = __phys_to_pfn(S5PV310_PA_COMBINER), -- cgit