From d1d8c666683cdbef18329ff8f3743ddaca8842ee Mon Sep 17 00:00:00 2001 From: Colin Cross Date: Sun, 1 May 2011 15:26:51 -0700 Subject: ARM: tegra: irq: Move legacy_irq.c into irq.c Now that irq.c is just an interface layer between the gic and legacy_irq.c, move the contents of legacy_irq.c into irq.c. Signed-off-by: Colin Cross --- arch/arm/mach-tegra/irq.c | 77 +++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 65 insertions(+), 12 deletions(-) (limited to 'arch/arm/mach-tegra/irq.c') diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index 4fa7a37ea5e4..da1749108c7d 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c @@ -18,8 +18,6 @@ */ #include -#include -#include #include #include #include @@ -27,40 +25,95 @@ #include #include -#include #include "board.h" +#define INT_SYS_NR (INT_GPIO_BASE - INT_PRI_BASE) +#define INT_SYS_SZ (INT_SEC_BASE - INT_PRI_BASE) +#define PPI_NR ((INT_SYS_NR+INT_SYS_SZ-1)/INT_SYS_SZ) + +#define ICTLR_CPU_IEP_VFIQ 0x08 +#define ICTLR_CPU_IEP_FIR 0x14 +#define ICTLR_CPU_IEP_FIR_SET 0x18 +#define ICTLR_CPU_IEP_FIR_CLR 0x1c + +#define ICTLR_CPU_IER 0x20 +#define ICTLR_CPU_IER_SET 0x24 +#define ICTLR_CPU_IER_CLR 0x28 +#define ICTLR_CPU_IEP_CLASS 0x2C + +#define ICTLR_COP_IER 0x30 +#define ICTLR_COP_IER_SET 0x34 +#define ICTLR_COP_IER_CLR 0x38 +#define ICTLR_COP_IEP_CLASS 0x3c + +#define NUM_ICTLRS 4 +#define FIRST_LEGACY_IRQ 32 + +static void __iomem *ictlr_reg_base[] = { + IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE), + IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE), + IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE), + IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE), +}; + +static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg) +{ + void __iomem *base; + u32 mask; + + BUG_ON(irq < FIRST_LEGACY_IRQ || + irq >= FIRST_LEGACY_IRQ + NUM_ICTLRS * 32); + + base = ictlr_reg_base[(irq - FIRST_LEGACY_IRQ) / 32]; + mask = BIT((irq - FIRST_LEGACY_IRQ) % 32); + + __raw_writel(mask, base + reg); +} + static void tegra_mask(struct irq_data *d) { - if (d->irq >= 32) - tegra_legacy_mask_irq(d->irq); + if (d->irq < FIRST_LEGACY_IRQ) + return; + + tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_CLR); } static void tegra_unmask(struct irq_data *d) { - if (d->irq >= 32) - tegra_legacy_unmask_irq(d->irq); + if (d->irq < FIRST_LEGACY_IRQ) + return; + + tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_SET); } static void tegra_ack(struct irq_data *d) { - if (d->irq >= 32) - tegra_legacy_force_irq_clr(d->irq); + if (d->irq < FIRST_LEGACY_IRQ) + return; + + tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR); } static int tegra_retrigger(struct irq_data *d) { - if (d->irq < 32) + if (d->irq < FIRST_LEGACY_IRQ) return 0; - tegra_legacy_force_irq_set(d->irq); + tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_SET); + return 1; } void __init tegra_init_irq(void) { - tegra_init_legacy_irq(); + int i; + + for (i = 0; i < NUM_ICTLRS; i++) { + void __iomem *ictlr = ictlr_reg_base[i]; + writel(~0, ictlr + ICTLR_CPU_IER_CLR); + writel(0, ictlr + ICTLR_CPU_IEP_CLASS); + } gic_arch_extn.irq_ack = tegra_ack; gic_arch_extn.irq_mask = tegra_mask; -- cgit