From 57886616ca7bff844a6427436d0c8faf74653f73 Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Thu, 3 Jan 2013 14:42:59 +0800 Subject: ARM: tegra: update the cache maintenance order for CPU shutdown Updating the cache maintenance order before CPU shutdown when doing CPU hotplug. The old order: * clean L1 by flush_cache_all * exit SMP * CPU shutdown Adapt to: * disable L1 data cache by clear C bit * clean L1 by v7_flush_dcache_louis * exit SMP * CPU shutdown For CPU hotplug case, it's no need to do "flush_cache_all". And we should disable L1 data cache before clean L1 data cache. Then leaving the SMP coherency. Signed-off-by: Joseph Lo Acked-by: Peter De Schrijver Signed-off-by: Stephen Warren --- arch/arm/mach-tegra/sleep-tegra30.S | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch/arm/mach-tegra/sleep-tegra30.S') diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index 562a8e7e413d..63a15bd9b653 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -32,9 +32,6 @@ * Should never return. */ ENTRY(tegra30_hotplug_shutdown) - /* Turn off SMP coherency */ - exit_smp r4, r5 - /* Powergate this CPU */ mov r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN bl tegra30_cpu_shutdown -- cgit