From 29a0e7beab8e05be53d5b9c050253a4dc417041e Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Tue, 13 Nov 2012 10:04:48 +0800 Subject: ARM: tegra: retain L2 content over CPU suspend/resume The L2 RAM is in different power domain from the CPU cluster. So the L2 content can be retained over CPU suspend/resume. To do that, we need to disable L2 after the MMU is disabled, and enable L2 before the MMU is enabled. But the L2 controller is in the same power domain with the CPU cluster. We need to restore it's settings and re-enable it after the power be resumed. Signed-off-by: Joseph Lo Acked-by: Peter De Schrijver Signed-off-by: Stephen Warren --- arch/arm/mach-tegra/sleep.S | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/mach-tegra/sleep.S') diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S index 88f4de986a52..26afa7cbed11 100644 --- a/arch/arm/mach-tegra/sleep.S +++ b/arch/arm/mach-tegra/sleep.S @@ -27,6 +27,7 @@ #include #include #include +#include #include "iomap.h" @@ -98,6 +99,12 @@ ENTRY(tegra_shut_off_mmu) dsb mcr p15, 0, r3, c1, c0, 0 isb +#ifdef CONFIG_CACHE_L2X0 + /* Disable L2 cache */ + mov32 r4, TEGRA_ARM_PERIF_BASE + 0x3000 + mov r5, #0 + str r5, [r4, #L2X0_CTRL] +#endif mov pc, r0 ENDPROC(tegra_shut_off_mmu) .popsection -- cgit