From e932900a3279b5dbb6d8f43c7b369003620e137c Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 20 Mar 2013 10:15:28 +0100 Subject: arm: zynq: Use standard timer binding Use cdns,ttc because this driver is Cadence Rev06 Triple Timer Counter and everybody can use it without xilinx specific function name or probing. Also use standard dt description for timer and also prepare for moving to clocksource initialization. Signed-off-by: Michal Simek --- arch/arm/mach-zynq/common.c | 1 + arch/arm/mach-zynq/timer.c | 261 +++++++++++++++++++++++++++++++------------- 2 files changed, 189 insertions(+), 73 deletions(-) (limited to 'arch/arm/mach-zynq') diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index 5c8983218183..76493b050beb 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c index f9fbc9c1e7a6..82357d94a0e0 100644 --- a/arch/arm/mach-zynq/timer.c +++ b/arch/arm/mach-zynq/timer.c @@ -1,7 +1,7 @@ /* * This file contains driver for the Xilinx PS Timer Counter IP. * - * Copyright (C) 2011 Xilinx + * Copyright (C) 2011-2013 Xilinx * * based on arch/mips/kernel/time.c timer driver * @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -23,6 +24,21 @@ #include #include "common.h" +/* + * This driver configures the 2 16-bit count-up timers as follows: + * + * T1: Timer 1, clocksource for generic timekeeping + * T2: Timer 2, clockevent source for hrtimers + * T3: Timer 3, + * + * The input frequency to the timer module for emulation is 2.5MHz which is + * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32, + * the timers are clocked at 78.125KHz (12.8 us resolution). + + * The input frequency to the timer module in silicon is configurable and + * obtained from device tree. The pre-scaler of 32 is used. + */ + /* * Timer Register Offset Definitions of Timer 1, Increment base address by 4 * and use same offsets for Timer 2 @@ -44,17 +60,24 @@ #define PRESCALE 2048 /* The exponent must match this */ #define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1) #define CLK_CNTRL_PRESCALE_EN 1 -#define CNT_CNTRL_RESET (1<<4) +#define CNT_CNTRL_RESET (1 << 4) /** * struct xttcps_timer - This definition defines local timer structure * * @base_addr: Base address of timer - **/ + * @clk: Associated clock source + * @clk_rate_change_nb Notifier block for clock rate changes + */ struct xttcps_timer { - void __iomem *base_addr; + void __iomem *base_addr; + struct clk *clk; + struct notifier_block clk_rate_change_nb; }; +#define to_xttcps_timer(x) \ + container_of(x, struct xttcps_timer, clk_rate_change_nb) + struct xttcps_timer_clocksource { struct xttcps_timer xttc; struct clocksource cs; @@ -66,7 +89,6 @@ struct xttcps_timer_clocksource { struct xttcps_timer_clockevent { struct xttcps_timer xttc; struct clock_event_device ce; - struct clk *clk; }; #define to_xttcps_timer_clkevent(x) \ @@ -167,8 +189,8 @@ static void xttcps_set_mode(enum clock_event_mode mode, switch (mode) { case CLOCK_EVT_MODE_PERIODIC: xttcps_set_interval(timer, - DIV_ROUND_CLOSEST(clk_get_rate(xttce->clk), - PRESCALE * HZ)); + DIV_ROUND_CLOSEST(clk_get_rate(xttce->xttc.clk), + PRESCALE * HZ)); break; case CLOCK_EVT_MODE_ONESHOT: case CLOCK_EVT_MODE_UNUSED: @@ -189,79 +211,148 @@ static void xttcps_set_mode(enum clock_event_mode mode, } } -static void __init zynq_ttc_setup_clocksource(struct device_node *np, - void __iomem *base) +static int xttcps_rate_change_clocksource_cb(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct clk_notifier_data *ndata = data; + struct xttcps_timer *xttcps = to_xttcps_timer(nb); + struct xttcps_timer_clocksource *xttccs = container_of(xttcps, + struct xttcps_timer_clocksource, xttc); + + switch (event) { + case POST_RATE_CHANGE: + /* + * Do whatever is necessary to maintain a proper time base + * + * I cannot find a way to adjust the currently used clocksource + * to the new frequency. __clocksource_updatefreq_hz() sounds + * good, but does not work. Not sure what's that missing. + * + * This approach works, but triggers two clocksource switches. + * The first after unregister to clocksource jiffies. And + * another one after the register to the newly registered timer. + * + * Alternatively we could 'waste' another HW timer to ping pong + * between clock sources. That would also use one register and + * one unregister call, but only trigger one clocksource switch + * for the cost of another HW timer used by the OS. + */ + clocksource_unregister(&xttccs->cs); + clocksource_register_hz(&xttccs->cs, + ndata->new_rate / PRESCALE); + /* fall through */ + case PRE_RATE_CHANGE: + case ABORT_RATE_CHANGE: + default: + return NOTIFY_DONE; + } +} + +static void __init xttc_setup_clocksource(struct clk *clk, void __iomem *base) { struct xttcps_timer_clocksource *ttccs; - struct clk *clk; int err; - u32 reg; ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL); if (WARN_ON(!ttccs)) return; - err = of_property_read_u32(np, "reg", ®); - if (WARN_ON(err)) - return; + ttccs->xttc.clk = clk; - clk = of_clk_get_by_name(np, "cpu_1x"); - if (WARN_ON(IS_ERR(clk))) - return; - - err = clk_prepare_enable(clk); + err = clk_prepare_enable(ttccs->xttc.clk); if (WARN_ON(err)) return; - ttccs->xttc.base_addr = base + reg * 4; + ttccs->xttc.clk_rate_change_nb.notifier_call = + xttcps_rate_change_clocksource_cb; + ttccs->xttc.clk_rate_change_nb.next = NULL; + if (clk_notifier_register(ttccs->xttc.clk, + &ttccs->xttc.clk_rate_change_nb)) + pr_warn("Unable to register clock notifier.\n"); - ttccs->cs.name = np->name; + ttccs->xttc.base_addr = base; + ttccs->cs.name = "xttcps_clocksource"; ttccs->cs.rating = 200; ttccs->cs.read = __xttc_clocksource_read; ttccs->cs.mask = CLOCKSOURCE_MASK(16); ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS; + /* + * Setup the clock source counter to be an incrementing counter + * with no interrupt and it rolls over at 0xFFFF. Pre-scale + * it by 32 also. Let it start running now. + */ __raw_writel(0x0, ttccs->xttc.base_addr + XTTCPS_IER_OFFSET); __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, ttccs->xttc.base_addr + XTTCPS_CLK_CNTRL_OFFSET); __raw_writel(CNT_CNTRL_RESET, ttccs->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET); - err = clocksource_register_hz(&ttccs->cs, clk_get_rate(clk) / PRESCALE); + err = clocksource_register_hz(&ttccs->cs, + clk_get_rate(ttccs->xttc.clk) / PRESCALE); if (WARN_ON(err)) return; + } -static void __init zynq_ttc_setup_clockevent(struct device_node *np, - void __iomem *base) +static int xttcps_rate_change_clockevent_cb(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct clk_notifier_data *ndata = data; + struct xttcps_timer *xttcps = to_xttcps_timer(nb); + struct xttcps_timer_clockevent *xttcce = container_of(xttcps, + struct xttcps_timer_clockevent, xttc); + + switch (event) { + case POST_RATE_CHANGE: + { + unsigned long flags; + + /* + * clockevents_update_freq should be called with IRQ disabled on + * the CPU the timer provides events for. The timer we use is + * common to both CPUs, not sure if we need to run on both + * cores. + */ + local_irq_save(flags); + clockevents_update_freq(&xttcce->ce, + ndata->new_rate / PRESCALE); + local_irq_restore(flags); + + /* fall through */ + } + case PRE_RATE_CHANGE: + case ABORT_RATE_CHANGE: + default: + return NOTIFY_DONE; + } +} + +static void __init xttc_setup_clockevent(struct clk *clk, + void __iomem *base, u32 irq) { struct xttcps_timer_clockevent *ttcce; - int err, irq; - u32 reg; + int err; ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL); if (WARN_ON(!ttcce)) return; - err = of_property_read_u32(np, "reg", ®); - if (WARN_ON(err)) - return; + ttcce->xttc.clk = clk; - ttcce->xttc.base_addr = base + reg * 4; - - ttcce->clk = of_clk_get_by_name(np, "cpu_1x"); - if (WARN_ON(IS_ERR(ttcce->clk))) - return; - - err = clk_prepare_enable(ttcce->clk); + err = clk_prepare_enable(ttcce->xttc.clk); if (WARN_ON(err)) return; - irq = irq_of_parse_and_map(np, 0); - if (WARN_ON(!irq)) - return; + ttcce->xttc.clk_rate_change_nb.notifier_call = + xttcps_rate_change_clockevent_cb; + ttcce->xttc.clk_rate_change_nb.next = NULL; + if (clk_notifier_register(ttcce->xttc.clk, + &ttcce->xttc.clk_rate_change_nb)) + pr_warn("Unable to register clock notifier.\n"); - ttcce->ce.name = np->name; + ttcce->xttc.base_addr = base; + ttcce->ce.name = "xttcps_clockevent"; ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; ttcce->ce.set_next_event = xttcps_set_next_event; ttcce->ce.set_mode = xttcps_set_mode; @@ -269,56 +360,80 @@ static void __init zynq_ttc_setup_clockevent(struct device_node *np, ttcce->ce.irq = irq; ttcce->ce.cpumask = cpu_possible_mask; + /* + * Setup the clock event timer to be an interval timer which + * is prescaled by 32 using the interval interrupt. Leave it + * disabled for now. + */ __raw_writel(0x23, ttcce->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET); __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, ttcce->xttc.base_addr + XTTCPS_CLK_CNTRL_OFFSET); __raw_writel(0x1, ttcce->xttc.base_addr + XTTCPS_IER_OFFSET); - err = request_irq(irq, xttcps_clock_event_interrupt, IRQF_TIMER, - np->name, ttcce); + err = request_irq(irq, xttcps_clock_event_interrupt, + IRQF_DISABLED | IRQF_TIMER, + ttcce->ce.name, ttcce); if (WARN_ON(err)) return; clockevents_config_and_register(&ttcce->ce, - clk_get_rate(ttcce->clk) / PRESCALE, - 1, 0xfffe); + clk_get_rate(ttcce->xttc.clk) / PRESCALE, 1, 0xfffe); } -static const __initconst struct of_device_id zynq_ttc_match[] = { - { .compatible = "xlnx,ttc-counter-clocksource", - .data = zynq_ttc_setup_clocksource, }, - { .compatible = "xlnx,ttc-counter-clockevent", - .data = zynq_ttc_setup_clockevent, }, - {} -}; - /** * xttcps_timer_init - Initialize the timer * * Initializes the timer hardware and register the clock source and clock event * timers with Linux kernal timer framework - **/ + */ +static void __init xttcps_timer_init_of(struct device_node *timer) +{ + unsigned int irq; + void __iomem *timer_baseaddr; + struct clk *clk; + + /* + * Get the 1st Triple Timer Counter (TTC) block from the device tree + * and use it. Note that the event timer uses the interrupt and it's the + * 2nd TTC hence the irq_of_parse_and_map(,1) + */ + timer_baseaddr = of_iomap(timer, 0); + if (!timer_baseaddr) { + pr_err("ERROR: invalid timer base address\n"); + BUG(); + } + + irq = irq_of_parse_and_map(timer, 1); + if (irq <= 0) { + pr_err("ERROR: invalid interrupt number\n"); + BUG(); + } + + clk = of_clk_get_by_name(timer, "cpu_1x"); + if (IS_ERR(clk)) { + pr_err("ERROR: timer input clock not found\n"); + BUG(); + } + + xttc_setup_clocksource(clk, timer_baseaddr); + xttc_setup_clockevent(clk, timer_baseaddr + 4, irq); + + pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq); +} + void __init xttcps_timer_init(void) { - struct device_node *np; - - for_each_compatible_node(np, NULL, "xlnx,ttc") { - struct device_node *np_chld; - void __iomem *base; - - base = of_iomap(np, 0); - if (WARN_ON(!base)) - return; - - for_each_available_child_of_node(np, np_chld) { - int (*cb)(struct device_node *np, void __iomem *base); - const struct of_device_id *match; - - match = of_match_node(zynq_ttc_match, np_chld); - if (match) { - cb = match->data; - cb(np_chld, base); - } - } + const char * const timer_list[] = { + "cdns,ttc", + NULL + }; + struct device_node *timer; + + timer = of_find_compatible_node(NULL, NULL, timer_list[0]); + if (!timer) { + pr_err("ERROR: no compatible timer found\n"); + BUG(); } + + xttcps_timer_init_of(timer); } -- cgit From c5263bb8b7944f1e34b36b5ea8a9119fc48a31ae Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 20 Mar 2013 10:24:59 +0100 Subject: arm: zynq: Move timer to clocksource interface Use clocksource timer initialization. Signed-off-by: Michal Simek --- arch/arm/mach-zynq/common.c | 2 +- arch/arm/mach-zynq/common.h | 2 -- arch/arm/mach-zynq/timer.c | 43 ++++++++++++++++++++----------------------- 3 files changed, 21 insertions(+), 26 deletions(-) (limited to 'arch/arm/mach-zynq') diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index 76493b050beb..68e0907de5d0 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c @@ -78,7 +78,7 @@ static void __init xilinx_zynq_timer_init(void) xilinx_zynq_clocks_init(slcr); - xttcps_timer_init(); + clocksource_of_init(); } /** diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h index 8b4dbbaa01cf..5050bb10bb12 100644 --- a/arch/arm/mach-zynq/common.h +++ b/arch/arm/mach-zynq/common.h @@ -17,6 +17,4 @@ #ifndef __MACH_ZYNQ_COMMON_H__ #define __MACH_ZYNQ_COMMON_H__ -void __init xttcps_timer_init(void); - #endif diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c index 82357d94a0e0..ab5b839e22f0 100644 --- a/arch/arm/mach-zynq/timer.c +++ b/arch/arm/mach-zynq/timer.c @@ -22,7 +22,6 @@ #include #include #include -#include "common.h" /* * This driver configures the 2 16-bit count-up timers as follows: @@ -260,8 +259,10 @@ static void __init xttc_setup_clocksource(struct clk *clk, void __iomem *base) ttccs->xttc.clk = clk; err = clk_prepare_enable(ttccs->xttc.clk); - if (WARN_ON(err)) + if (WARN_ON(err)) { + kfree(ttccs); return; + } ttccs->xttc.clk_rate_change_nb.notifier_call = xttcps_rate_change_clocksource_cb; @@ -290,9 +291,10 @@ static void __init xttc_setup_clocksource(struct clk *clk, void __iomem *base) err = clocksource_register_hz(&ttccs->cs, clk_get_rate(ttccs->xttc.clk) / PRESCALE); - if (WARN_ON(err)) + if (WARN_ON(err)) { + kfree(ttccs); return; - + } } static int xttcps_rate_change_clockevent_cb(struct notifier_block *nb, @@ -341,8 +343,10 @@ static void __init xttc_setup_clockevent(struct clk *clk, ttcce->xttc.clk = clk; err = clk_prepare_enable(ttcce->xttc.clk); - if (WARN_ON(err)) + if (WARN_ON(err)) { + kfree(ttcce); return; + } ttcce->xttc.clk_rate_change_nb.notifier_call = xttcps_rate_change_clockevent_cb; @@ -373,8 +377,10 @@ static void __init xttc_setup_clockevent(struct clk *clk, err = request_irq(irq, xttcps_clock_event_interrupt, IRQF_DISABLED | IRQF_TIMER, ttcce->ce.name, ttcce); - if (WARN_ON(err)) + if (WARN_ON(err)) { + kfree(ttcce); return; + } clockevents_config_and_register(&ttcce->ce, clk_get_rate(ttcce->xttc.clk) / PRESCALE, 1, 0xfffe); @@ -386,11 +392,17 @@ static void __init xttc_setup_clockevent(struct clk *clk, * Initializes the timer hardware and register the clock source and clock event * timers with Linux kernal timer framework */ -static void __init xttcps_timer_init_of(struct device_node *timer) +static void __init xttcps_timer_init(struct device_node *timer) { unsigned int irq; void __iomem *timer_baseaddr; struct clk *clk; + static int initialized; + + if (initialized) + return; + + initialized = 1; /* * Get the 1st Triple Timer Counter (TTC) block from the device tree @@ -421,19 +433,4 @@ static void __init xttcps_timer_init_of(struct device_node *timer) pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq); } -void __init xttcps_timer_init(void) -{ - const char * const timer_list[] = { - "cdns,ttc", - NULL - }; - struct device_node *timer; - - timer = of_find_compatible_node(NULL, NULL, timer_list[0]); - if (!timer) { - pr_err("ERROR: no compatible timer found\n"); - BUG(); - } - - xttcps_timer_init_of(timer); -} +CLOCKSOURCE_OF_DECLARE(ttc, "cdns,ttc", xttcps_timer_init); -- cgit From 9e09dc5f7fdc1e914c3b7bc186fa4b54d05a88d6 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 27 Mar 2013 12:05:28 +0100 Subject: arm: zynq: Do not use xilinx specific function names Remove all xilinx specific names from the driver because this is generic driver for cadence ttc. xttc->ttc ttcps->ttc ... No functional changes in this driver. Signed-off-by: Michal Simek --- arch/arm/mach-zynq/timer.c | 212 ++++++++++++++++++++++----------------------- 1 file changed, 106 insertions(+), 106 deletions(-) (limited to 'arch/arm/mach-zynq') diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c index ab5b839e22f0..685bc60e210a 100644 --- a/arch/arm/mach-zynq/timer.c +++ b/arch/arm/mach-zynq/timer.c @@ -1,5 +1,5 @@ /* - * This file contains driver for the Xilinx PS Timer Counter IP. + * This file contains driver for the Cadence Triple Timer Counter Rev 06 * * Copyright (C) 2011-2013 Xilinx * @@ -42,14 +42,14 @@ * Timer Register Offset Definitions of Timer 1, Increment base address by 4 * and use same offsets for Timer 2 */ -#define XTTCPS_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */ -#define XTTCPS_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */ -#define XTTCPS_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */ -#define XTTCPS_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */ -#define XTTCPS_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */ -#define XTTCPS_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */ +#define TTC_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */ +#define TTC_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */ +#define TTC_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */ +#define TTC_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */ +#define TTC_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */ +#define TTC_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */ -#define XTTCPS_CNT_CNTRL_DISABLE_MASK 0x1 +#define TTC_CNT_CNTRL_DISABLE_MASK 0x1 /* * Setup the timers to use pre-scaling, using a fixed value for now that will @@ -62,161 +62,161 @@ #define CNT_CNTRL_RESET (1 << 4) /** - * struct xttcps_timer - This definition defines local timer structure + * struct ttc_timer - This definition defines local timer structure * * @base_addr: Base address of timer * @clk: Associated clock source * @clk_rate_change_nb Notifier block for clock rate changes */ -struct xttcps_timer { +struct ttc_timer { void __iomem *base_addr; struct clk *clk; struct notifier_block clk_rate_change_nb; }; -#define to_xttcps_timer(x) \ - container_of(x, struct xttcps_timer, clk_rate_change_nb) +#define to_ttc_timer(x) \ + container_of(x, struct ttc_timer, clk_rate_change_nb) -struct xttcps_timer_clocksource { - struct xttcps_timer xttc; +struct ttc_timer_clocksource { + struct ttc_timer ttc; struct clocksource cs; }; -#define to_xttcps_timer_clksrc(x) \ - container_of(x, struct xttcps_timer_clocksource, cs) +#define to_ttc_timer_clksrc(x) \ + container_of(x, struct ttc_timer_clocksource, cs) -struct xttcps_timer_clockevent { - struct xttcps_timer xttc; +struct ttc_timer_clockevent { + struct ttc_timer ttc; struct clock_event_device ce; }; -#define to_xttcps_timer_clkevent(x) \ - container_of(x, struct xttcps_timer_clockevent, ce) +#define to_ttc_timer_clkevent(x) \ + container_of(x, struct ttc_timer_clockevent, ce) /** - * xttcps_set_interval - Set the timer interval value + * ttc_set_interval - Set the timer interval value * * @timer: Pointer to the timer instance * @cycles: Timer interval ticks **/ -static void xttcps_set_interval(struct xttcps_timer *timer, +static void ttc_set_interval(struct ttc_timer *timer, unsigned long cycles) { u32 ctrl_reg; /* Disable the counter, set the counter value and re-enable counter */ - ctrl_reg = __raw_readl(timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET); - ctrl_reg |= XTTCPS_CNT_CNTRL_DISABLE_MASK; - __raw_writel(ctrl_reg, timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET); + ctrl_reg = __raw_readl(timer->base_addr + TTC_CNT_CNTRL_OFFSET); + ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK; + __raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); - __raw_writel(cycles, timer->base_addr + XTTCPS_INTR_VAL_OFFSET); + __raw_writel(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET); /* * Reset the counter (0x10) so that it starts from 0, one-shot * mode makes this needed for timing to be right. */ ctrl_reg |= CNT_CNTRL_RESET; - ctrl_reg &= ~XTTCPS_CNT_CNTRL_DISABLE_MASK; - __raw_writel(ctrl_reg, timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET); + ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK; + __raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); } /** - * xttcps_clock_event_interrupt - Clock event timer interrupt handler + * ttc_clock_event_interrupt - Clock event timer interrupt handler * * @irq: IRQ number of the Timer - * @dev_id: void pointer to the xttcps_timer instance + * @dev_id: void pointer to the ttc_timer instance * * returns: Always IRQ_HANDLED - success **/ -static irqreturn_t xttcps_clock_event_interrupt(int irq, void *dev_id) +static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id) { - struct xttcps_timer_clockevent *xttce = dev_id; - struct xttcps_timer *timer = &xttce->xttc; + struct ttc_timer_clockevent *ttce = dev_id; + struct ttc_timer *timer = &ttce->ttc; /* Acknowledge the interrupt and call event handler */ - __raw_readl(timer->base_addr + XTTCPS_ISR_OFFSET); + __raw_readl(timer->base_addr + TTC_ISR_OFFSET); - xttce->ce.event_handler(&xttce->ce); + ttce->ce.event_handler(&ttce->ce); return IRQ_HANDLED; } /** - * __xttc_clocksource_read - Reads the timer counter register + * __ttc_clocksource_read - Reads the timer counter register * * returns: Current timer counter register value **/ -static cycle_t __xttc_clocksource_read(struct clocksource *cs) +static cycle_t __ttc_clocksource_read(struct clocksource *cs) { - struct xttcps_timer *timer = &to_xttcps_timer_clksrc(cs)->xttc; + struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc; return (cycle_t)__raw_readl(timer->base_addr + - XTTCPS_COUNT_VAL_OFFSET); + TTC_COUNT_VAL_OFFSET); } /** - * xttcps_set_next_event - Sets the time interval for next event + * ttc_set_next_event - Sets the time interval for next event * * @cycles: Timer interval ticks * @evt: Address of clock event instance * * returns: Always 0 - success **/ -static int xttcps_set_next_event(unsigned long cycles, +static int ttc_set_next_event(unsigned long cycles, struct clock_event_device *evt) { - struct xttcps_timer_clockevent *xttce = to_xttcps_timer_clkevent(evt); - struct xttcps_timer *timer = &xttce->xttc; + struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt); + struct ttc_timer *timer = &ttce->ttc; - xttcps_set_interval(timer, cycles); + ttc_set_interval(timer, cycles); return 0; } /** - * xttcps_set_mode - Sets the mode of timer + * ttc_set_mode - Sets the mode of timer * * @mode: Mode to be set * @evt: Address of clock event instance **/ -static void xttcps_set_mode(enum clock_event_mode mode, +static void ttc_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) { - struct xttcps_timer_clockevent *xttce = to_xttcps_timer_clkevent(evt); - struct xttcps_timer *timer = &xttce->xttc; + struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt); + struct ttc_timer *timer = &ttce->ttc; u32 ctrl_reg; switch (mode) { case CLOCK_EVT_MODE_PERIODIC: - xttcps_set_interval(timer, - DIV_ROUND_CLOSEST(clk_get_rate(xttce->xttc.clk), + ttc_set_interval(timer, + DIV_ROUND_CLOSEST(clk_get_rate(ttce->ttc.clk), PRESCALE * HZ)); break; case CLOCK_EVT_MODE_ONESHOT: case CLOCK_EVT_MODE_UNUSED: case CLOCK_EVT_MODE_SHUTDOWN: ctrl_reg = __raw_readl(timer->base_addr + - XTTCPS_CNT_CNTRL_OFFSET); - ctrl_reg |= XTTCPS_CNT_CNTRL_DISABLE_MASK; + TTC_CNT_CNTRL_OFFSET); + ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK; __raw_writel(ctrl_reg, - timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET); + timer->base_addr + TTC_CNT_CNTRL_OFFSET); break; case CLOCK_EVT_MODE_RESUME: ctrl_reg = __raw_readl(timer->base_addr + - XTTCPS_CNT_CNTRL_OFFSET); - ctrl_reg &= ~XTTCPS_CNT_CNTRL_DISABLE_MASK; + TTC_CNT_CNTRL_OFFSET); + ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK; __raw_writel(ctrl_reg, - timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET); + timer->base_addr + TTC_CNT_CNTRL_OFFSET); break; } } -static int xttcps_rate_change_clocksource_cb(struct notifier_block *nb, +static int ttc_rate_change_clocksource_cb(struct notifier_block *nb, unsigned long event, void *data) { struct clk_notifier_data *ndata = data; - struct xttcps_timer *xttcps = to_xttcps_timer(nb); - struct xttcps_timer_clocksource *xttccs = container_of(xttcps, - struct xttcps_timer_clocksource, xttc); + struct ttc_timer *ttc = to_ttc_timer(nb); + struct ttc_timer_clocksource *ttccs = container_of(ttc, + struct ttc_timer_clocksource, ttc); switch (event) { case POST_RATE_CHANGE: @@ -236,8 +236,8 @@ static int xttcps_rate_change_clocksource_cb(struct notifier_block *nb, * one unregister call, but only trigger one clocksource switch * for the cost of another HW timer used by the OS. */ - clocksource_unregister(&xttccs->cs); - clocksource_register_hz(&xttccs->cs, + clocksource_unregister(&ttccs->cs); + clocksource_register_hz(&ttccs->cs, ndata->new_rate / PRESCALE); /* fall through */ case PRE_RATE_CHANGE: @@ -247,34 +247,34 @@ static int xttcps_rate_change_clocksource_cb(struct notifier_block *nb, } } -static void __init xttc_setup_clocksource(struct clk *clk, void __iomem *base) +static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base) { - struct xttcps_timer_clocksource *ttccs; + struct ttc_timer_clocksource *ttccs; int err; ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL); if (WARN_ON(!ttccs)) return; - ttccs->xttc.clk = clk; + ttccs->ttc.clk = clk; - err = clk_prepare_enable(ttccs->xttc.clk); + err = clk_prepare_enable(ttccs->ttc.clk); if (WARN_ON(err)) { kfree(ttccs); return; } - ttccs->xttc.clk_rate_change_nb.notifier_call = - xttcps_rate_change_clocksource_cb; - ttccs->xttc.clk_rate_change_nb.next = NULL; - if (clk_notifier_register(ttccs->xttc.clk, - &ttccs->xttc.clk_rate_change_nb)) + ttccs->ttc.clk_rate_change_nb.notifier_call = + ttc_rate_change_clocksource_cb; + ttccs->ttc.clk_rate_change_nb.next = NULL; + if (clk_notifier_register(ttccs->ttc.clk, + &ttccs->ttc.clk_rate_change_nb)) pr_warn("Unable to register clock notifier.\n"); - ttccs->xttc.base_addr = base; - ttccs->cs.name = "xttcps_clocksource"; + ttccs->ttc.base_addr = base; + ttccs->cs.name = "ttc_clocksource"; ttccs->cs.rating = 200; - ttccs->cs.read = __xttc_clocksource_read; + ttccs->cs.read = __ttc_clocksource_read; ttccs->cs.mask = CLOCKSOURCE_MASK(16); ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS; @@ -283,27 +283,27 @@ static void __init xttc_setup_clocksource(struct clk *clk, void __iomem *base) * with no interrupt and it rolls over at 0xFFFF. Pre-scale * it by 32 also. Let it start running now. */ - __raw_writel(0x0, ttccs->xttc.base_addr + XTTCPS_IER_OFFSET); + __raw_writel(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET); __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, - ttccs->xttc.base_addr + XTTCPS_CLK_CNTRL_OFFSET); + ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); __raw_writel(CNT_CNTRL_RESET, - ttccs->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET); + ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET); err = clocksource_register_hz(&ttccs->cs, - clk_get_rate(ttccs->xttc.clk) / PRESCALE); + clk_get_rate(ttccs->ttc.clk) / PRESCALE); if (WARN_ON(err)) { kfree(ttccs); return; } } -static int xttcps_rate_change_clockevent_cb(struct notifier_block *nb, +static int ttc_rate_change_clockevent_cb(struct notifier_block *nb, unsigned long event, void *data) { struct clk_notifier_data *ndata = data; - struct xttcps_timer *xttcps = to_xttcps_timer(nb); - struct xttcps_timer_clockevent *xttcce = container_of(xttcps, - struct xttcps_timer_clockevent, xttc); + struct ttc_timer *ttc = to_ttc_timer(nb); + struct ttc_timer_clockevent *ttcce = container_of(ttc, + struct ttc_timer_clockevent, ttc); switch (event) { case POST_RATE_CHANGE: @@ -317,7 +317,7 @@ static int xttcps_rate_change_clockevent_cb(struct notifier_block *nb, * cores. */ local_irq_save(flags); - clockevents_update_freq(&xttcce->ce, + clockevents_update_freq(&ttcce->ce, ndata->new_rate / PRESCALE); local_irq_restore(flags); @@ -330,36 +330,36 @@ static int xttcps_rate_change_clockevent_cb(struct notifier_block *nb, } } -static void __init xttc_setup_clockevent(struct clk *clk, +static void __init ttc_setup_clockevent(struct clk *clk, void __iomem *base, u32 irq) { - struct xttcps_timer_clockevent *ttcce; + struct ttc_timer_clockevent *ttcce; int err; ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL); if (WARN_ON(!ttcce)) return; - ttcce->xttc.clk = clk; + ttcce->ttc.clk = clk; - err = clk_prepare_enable(ttcce->xttc.clk); + err = clk_prepare_enable(ttcce->ttc.clk); if (WARN_ON(err)) { kfree(ttcce); return; } - ttcce->xttc.clk_rate_change_nb.notifier_call = - xttcps_rate_change_clockevent_cb; - ttcce->xttc.clk_rate_change_nb.next = NULL; - if (clk_notifier_register(ttcce->xttc.clk, - &ttcce->xttc.clk_rate_change_nb)) + ttcce->ttc.clk_rate_change_nb.notifier_call = + ttc_rate_change_clockevent_cb; + ttcce->ttc.clk_rate_change_nb.next = NULL; + if (clk_notifier_register(ttcce->ttc.clk, + &ttcce->ttc.clk_rate_change_nb)) pr_warn("Unable to register clock notifier.\n"); - ttcce->xttc.base_addr = base; - ttcce->ce.name = "xttcps_clockevent"; + ttcce->ttc.base_addr = base; + ttcce->ce.name = "ttc_clockevent"; ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; - ttcce->ce.set_next_event = xttcps_set_next_event; - ttcce->ce.set_mode = xttcps_set_mode; + ttcce->ce.set_next_event = ttc_set_next_event; + ttcce->ce.set_mode = ttc_set_mode; ttcce->ce.rating = 200; ttcce->ce.irq = irq; ttcce->ce.cpumask = cpu_possible_mask; @@ -369,12 +369,12 @@ static void __init xttc_setup_clockevent(struct clk *clk, * is prescaled by 32 using the interval interrupt. Leave it * disabled for now. */ - __raw_writel(0x23, ttcce->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET); + __raw_writel(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET); __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, - ttcce->xttc.base_addr + XTTCPS_CLK_CNTRL_OFFSET); - __raw_writel(0x1, ttcce->xttc.base_addr + XTTCPS_IER_OFFSET); + ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); + __raw_writel(0x1, ttcce->ttc.base_addr + TTC_IER_OFFSET); - err = request_irq(irq, xttcps_clock_event_interrupt, + err = request_irq(irq, ttc_clock_event_interrupt, IRQF_DISABLED | IRQF_TIMER, ttcce->ce.name, ttcce); if (WARN_ON(err)) { @@ -383,16 +383,16 @@ static void __init xttc_setup_clockevent(struct clk *clk, } clockevents_config_and_register(&ttcce->ce, - clk_get_rate(ttcce->xttc.clk) / PRESCALE, 1, 0xfffe); + clk_get_rate(ttcce->ttc.clk) / PRESCALE, 1, 0xfffe); } /** - * xttcps_timer_init - Initialize the timer + * ttc_timer_init - Initialize the timer * * Initializes the timer hardware and register the clock source and clock event * timers with Linux kernal timer framework */ -static void __init xttcps_timer_init(struct device_node *timer) +static void __init ttc_timer_init(struct device_node *timer) { unsigned int irq; void __iomem *timer_baseaddr; @@ -427,10 +427,10 @@ static void __init xttcps_timer_init(struct device_node *timer) BUG(); } - xttc_setup_clocksource(clk, timer_baseaddr); - xttc_setup_clockevent(clk, timer_baseaddr + 4, irq); + ttc_setup_clocksource(clk, timer_baseaddr); + ttc_setup_clockevent(clk, timer_baseaddr + 4, irq); pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq); } -CLOCKSOURCE_OF_DECLARE(ttc, "cdns,ttc", xttcps_timer_init); +CLOCKSOURCE_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init); -- cgit From 4f0f234fce1d263cc9881456352e8fd56ead0514 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 20 Mar 2013 10:46:01 +0100 Subject: arm: zynq: Move timer to generic location Move zynq timer out of mach folder to generic location and enable it. Signed-off-by: Michal Simek --- arch/arm/mach-zynq/Kconfig | 1 + arch/arm/mach-zynq/Makefile | 2 +- arch/arm/mach-zynq/timer.c | 436 -------------------------------------------- 3 files changed, 2 insertions(+), 437 deletions(-) delete mode 100644 arch/arm/mach-zynq/timer.c (limited to 'arch/arm/mach-zynq') diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index adb6c0ea0e53..d70651e8b705 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -9,5 +9,6 @@ config ARCH_ZYNQ select MIGHT_HAVE_CACHE_L2X0 select USE_OF select SPARSE_IRQ + select CADENCE_TTC_TIMER help Support for Xilinx Zynq ARM Cortex A9 Platform diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile index 397268c1b250..320faedeb484 100644 --- a/arch/arm/mach-zynq/Makefile +++ b/arch/arm/mach-zynq/Makefile @@ -3,4 +3,4 @@ # # Common support -obj-y := common.o timer.o +obj-y := common.o diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c deleted file mode 100644 index 685bc60e210a..000000000000 --- a/arch/arm/mach-zynq/timer.c +++ /dev/null @@ -1,436 +0,0 @@ -/* - * This file contains driver for the Cadence Triple Timer Counter Rev 06 - * - * Copyright (C) 2011-2013 Xilinx - * - * based on arch/mips/kernel/time.c timer driver - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include - -/* - * This driver configures the 2 16-bit count-up timers as follows: - * - * T1: Timer 1, clocksource for generic timekeeping - * T2: Timer 2, clockevent source for hrtimers - * T3: Timer 3, - * - * The input frequency to the timer module for emulation is 2.5MHz which is - * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32, - * the timers are clocked at 78.125KHz (12.8 us resolution). - - * The input frequency to the timer module in silicon is configurable and - * obtained from device tree. The pre-scaler of 32 is used. - */ - -/* - * Timer Register Offset Definitions of Timer 1, Increment base address by 4 - * and use same offsets for Timer 2 - */ -#define TTC_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */ -#define TTC_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */ -#define TTC_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */ -#define TTC_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */ -#define TTC_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */ -#define TTC_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */ - -#define TTC_CNT_CNTRL_DISABLE_MASK 0x1 - -/* - * Setup the timers to use pre-scaling, using a fixed value for now that will - * work across most input frequency, but it may need to be more dynamic - */ -#define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */ -#define PRESCALE 2048 /* The exponent must match this */ -#define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1) -#define CLK_CNTRL_PRESCALE_EN 1 -#define CNT_CNTRL_RESET (1 << 4) - -/** - * struct ttc_timer - This definition defines local timer structure - * - * @base_addr: Base address of timer - * @clk: Associated clock source - * @clk_rate_change_nb Notifier block for clock rate changes - */ -struct ttc_timer { - void __iomem *base_addr; - struct clk *clk; - struct notifier_block clk_rate_change_nb; -}; - -#define to_ttc_timer(x) \ - container_of(x, struct ttc_timer, clk_rate_change_nb) - -struct ttc_timer_clocksource { - struct ttc_timer ttc; - struct clocksource cs; -}; - -#define to_ttc_timer_clksrc(x) \ - container_of(x, struct ttc_timer_clocksource, cs) - -struct ttc_timer_clockevent { - struct ttc_timer ttc; - struct clock_event_device ce; -}; - -#define to_ttc_timer_clkevent(x) \ - container_of(x, struct ttc_timer_clockevent, ce) - -/** - * ttc_set_interval - Set the timer interval value - * - * @timer: Pointer to the timer instance - * @cycles: Timer interval ticks - **/ -static void ttc_set_interval(struct ttc_timer *timer, - unsigned long cycles) -{ - u32 ctrl_reg; - - /* Disable the counter, set the counter value and re-enable counter */ - ctrl_reg = __raw_readl(timer->base_addr + TTC_CNT_CNTRL_OFFSET); - ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK; - __raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); - - __raw_writel(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET); - - /* - * Reset the counter (0x10) so that it starts from 0, one-shot - * mode makes this needed for timing to be right. - */ - ctrl_reg |= CNT_CNTRL_RESET; - ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK; - __raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); -} - -/** - * ttc_clock_event_interrupt - Clock event timer interrupt handler - * - * @irq: IRQ number of the Timer - * @dev_id: void pointer to the ttc_timer instance - * - * returns: Always IRQ_HANDLED - success - **/ -static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id) -{ - struct ttc_timer_clockevent *ttce = dev_id; - struct ttc_timer *timer = &ttce->ttc; - - /* Acknowledge the interrupt and call event handler */ - __raw_readl(timer->base_addr + TTC_ISR_OFFSET); - - ttce->ce.event_handler(&ttce->ce); - - return IRQ_HANDLED; -} - -/** - * __ttc_clocksource_read - Reads the timer counter register - * - * returns: Current timer counter register value - **/ -static cycle_t __ttc_clocksource_read(struct clocksource *cs) -{ - struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc; - - return (cycle_t)__raw_readl(timer->base_addr + - TTC_COUNT_VAL_OFFSET); -} - -/** - * ttc_set_next_event - Sets the time interval for next event - * - * @cycles: Timer interval ticks - * @evt: Address of clock event instance - * - * returns: Always 0 - success - **/ -static int ttc_set_next_event(unsigned long cycles, - struct clock_event_device *evt) -{ - struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt); - struct ttc_timer *timer = &ttce->ttc; - - ttc_set_interval(timer, cycles); - return 0; -} - -/** - * ttc_set_mode - Sets the mode of timer - * - * @mode: Mode to be set - * @evt: Address of clock event instance - **/ -static void ttc_set_mode(enum clock_event_mode mode, - struct clock_event_device *evt) -{ - struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt); - struct ttc_timer *timer = &ttce->ttc; - u32 ctrl_reg; - - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - ttc_set_interval(timer, - DIV_ROUND_CLOSEST(clk_get_rate(ttce->ttc.clk), - PRESCALE * HZ)); - break; - case CLOCK_EVT_MODE_ONESHOT: - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_SHUTDOWN: - ctrl_reg = __raw_readl(timer->base_addr + - TTC_CNT_CNTRL_OFFSET); - ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK; - __raw_writel(ctrl_reg, - timer->base_addr + TTC_CNT_CNTRL_OFFSET); - break; - case CLOCK_EVT_MODE_RESUME: - ctrl_reg = __raw_readl(timer->base_addr + - TTC_CNT_CNTRL_OFFSET); - ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK; - __raw_writel(ctrl_reg, - timer->base_addr + TTC_CNT_CNTRL_OFFSET); - break; - } -} - -static int ttc_rate_change_clocksource_cb(struct notifier_block *nb, - unsigned long event, void *data) -{ - struct clk_notifier_data *ndata = data; - struct ttc_timer *ttc = to_ttc_timer(nb); - struct ttc_timer_clocksource *ttccs = container_of(ttc, - struct ttc_timer_clocksource, ttc); - - switch (event) { - case POST_RATE_CHANGE: - /* - * Do whatever is necessary to maintain a proper time base - * - * I cannot find a way to adjust the currently used clocksource - * to the new frequency. __clocksource_updatefreq_hz() sounds - * good, but does not work. Not sure what's that missing. - * - * This approach works, but triggers two clocksource switches. - * The first after unregister to clocksource jiffies. And - * another one after the register to the newly registered timer. - * - * Alternatively we could 'waste' another HW timer to ping pong - * between clock sources. That would also use one register and - * one unregister call, but only trigger one clocksource switch - * for the cost of another HW timer used by the OS. - */ - clocksource_unregister(&ttccs->cs); - clocksource_register_hz(&ttccs->cs, - ndata->new_rate / PRESCALE); - /* fall through */ - case PRE_RATE_CHANGE: - case ABORT_RATE_CHANGE: - default: - return NOTIFY_DONE; - } -} - -static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base) -{ - struct ttc_timer_clocksource *ttccs; - int err; - - ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL); - if (WARN_ON(!ttccs)) - return; - - ttccs->ttc.clk = clk; - - err = clk_prepare_enable(ttccs->ttc.clk); - if (WARN_ON(err)) { - kfree(ttccs); - return; - } - - ttccs->ttc.clk_rate_change_nb.notifier_call = - ttc_rate_change_clocksource_cb; - ttccs->ttc.clk_rate_change_nb.next = NULL; - if (clk_notifier_register(ttccs->ttc.clk, - &ttccs->ttc.clk_rate_change_nb)) - pr_warn("Unable to register clock notifier.\n"); - - ttccs->ttc.base_addr = base; - ttccs->cs.name = "ttc_clocksource"; - ttccs->cs.rating = 200; - ttccs->cs.read = __ttc_clocksource_read; - ttccs->cs.mask = CLOCKSOURCE_MASK(16); - ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS; - - /* - * Setup the clock source counter to be an incrementing counter - * with no interrupt and it rolls over at 0xFFFF. Pre-scale - * it by 32 also. Let it start running now. - */ - __raw_writel(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET); - __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, - ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); - __raw_writel(CNT_CNTRL_RESET, - ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET); - - err = clocksource_register_hz(&ttccs->cs, - clk_get_rate(ttccs->ttc.clk) / PRESCALE); - if (WARN_ON(err)) { - kfree(ttccs); - return; - } -} - -static int ttc_rate_change_clockevent_cb(struct notifier_block *nb, - unsigned long event, void *data) -{ - struct clk_notifier_data *ndata = data; - struct ttc_timer *ttc = to_ttc_timer(nb); - struct ttc_timer_clockevent *ttcce = container_of(ttc, - struct ttc_timer_clockevent, ttc); - - switch (event) { - case POST_RATE_CHANGE: - { - unsigned long flags; - - /* - * clockevents_update_freq should be called with IRQ disabled on - * the CPU the timer provides events for. The timer we use is - * common to both CPUs, not sure if we need to run on both - * cores. - */ - local_irq_save(flags); - clockevents_update_freq(&ttcce->ce, - ndata->new_rate / PRESCALE); - local_irq_restore(flags); - - /* fall through */ - } - case PRE_RATE_CHANGE: - case ABORT_RATE_CHANGE: - default: - return NOTIFY_DONE; - } -} - -static void __init ttc_setup_clockevent(struct clk *clk, - void __iomem *base, u32 irq) -{ - struct ttc_timer_clockevent *ttcce; - int err; - - ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL); - if (WARN_ON(!ttcce)) - return; - - ttcce->ttc.clk = clk; - - err = clk_prepare_enable(ttcce->ttc.clk); - if (WARN_ON(err)) { - kfree(ttcce); - return; - } - - ttcce->ttc.clk_rate_change_nb.notifier_call = - ttc_rate_change_clockevent_cb; - ttcce->ttc.clk_rate_change_nb.next = NULL; - if (clk_notifier_register(ttcce->ttc.clk, - &ttcce->ttc.clk_rate_change_nb)) - pr_warn("Unable to register clock notifier.\n"); - - ttcce->ttc.base_addr = base; - ttcce->ce.name = "ttc_clockevent"; - ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; - ttcce->ce.set_next_event = ttc_set_next_event; - ttcce->ce.set_mode = ttc_set_mode; - ttcce->ce.rating = 200; - ttcce->ce.irq = irq; - ttcce->ce.cpumask = cpu_possible_mask; - - /* - * Setup the clock event timer to be an interval timer which - * is prescaled by 32 using the interval interrupt. Leave it - * disabled for now. - */ - __raw_writel(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET); - __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, - ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); - __raw_writel(0x1, ttcce->ttc.base_addr + TTC_IER_OFFSET); - - err = request_irq(irq, ttc_clock_event_interrupt, - IRQF_DISABLED | IRQF_TIMER, - ttcce->ce.name, ttcce); - if (WARN_ON(err)) { - kfree(ttcce); - return; - } - - clockevents_config_and_register(&ttcce->ce, - clk_get_rate(ttcce->ttc.clk) / PRESCALE, 1, 0xfffe); -} - -/** - * ttc_timer_init - Initialize the timer - * - * Initializes the timer hardware and register the clock source and clock event - * timers with Linux kernal timer framework - */ -static void __init ttc_timer_init(struct device_node *timer) -{ - unsigned int irq; - void __iomem *timer_baseaddr; - struct clk *clk; - static int initialized; - - if (initialized) - return; - - initialized = 1; - - /* - * Get the 1st Triple Timer Counter (TTC) block from the device tree - * and use it. Note that the event timer uses the interrupt and it's the - * 2nd TTC hence the irq_of_parse_and_map(,1) - */ - timer_baseaddr = of_iomap(timer, 0); - if (!timer_baseaddr) { - pr_err("ERROR: invalid timer base address\n"); - BUG(); - } - - irq = irq_of_parse_and_map(timer, 1); - if (irq <= 0) { - pr_err("ERROR: invalid interrupt number\n"); - BUG(); - } - - clk = of_clk_get_by_name(timer, "cpu_1x"); - if (IS_ERR(clk)) { - pr_err("ERROR: timer input clock not found\n"); - BUG(); - } - - ttc_setup_clocksource(clk, timer_baseaddr); - ttc_setup_clockevent(clk, timer_baseaddr + 4, irq); - - pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq); -} - -CLOCKSOURCE_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init); -- cgit