From 877ec119dbbf9576953efc457ede5243621ad6eb Mon Sep 17 00:00:00 2001 From: Vladimir Murzin Date: Mon, 16 Oct 2017 12:52:35 +0100 Subject: ARM: 8706/1: NOMMU: Move out MPU setup in separate module MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Having MPU handling code in dedicated module makes it easier to enhance/maintain it. Tested-by: Szemző András Tested-by: Alexandre TORGUE Tested-by: Benjamin Gaignard Signed-off-by: Vladimir Murzin Signed-off-by: Russell King --- arch/arm/mm/pmsa-v7.c | 262 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 262 insertions(+) create mode 100644 arch/arm/mm/pmsa-v7.c (limited to 'arch/arm/mm/pmsa-v7.c') diff --git a/arch/arm/mm/pmsa-v7.c b/arch/arm/mm/pmsa-v7.c new file mode 100644 index 000000000000..cc987715457d --- /dev/null +++ b/arch/arm/mm/pmsa-v7.c @@ -0,0 +1,262 @@ +/* + * Based on linux/arch/arm/mm/nommu.c + * + * ARM PMSAv7 supporting functions. + */ + +#include + +#include +#include +#include + +#include "mm.h" + +/* Region number */ +static void rgnr_write(u32 v) +{ + asm("mcr p15, 0, %0, c6, c2, 0" : : "r" (v)); +} + +/* Data-side / unified region attributes */ + +/* Region access control register */ +static void dracr_write(u32 v) +{ + asm("mcr p15, 0, %0, c6, c1, 4" : : "r" (v)); +} + +/* Region size register */ +static void drsr_write(u32 v) +{ + asm("mcr p15, 0, %0, c6, c1, 2" : : "r" (v)); +} + +/* Region base address register */ +static void drbar_write(u32 v) +{ + asm("mcr p15, 0, %0, c6, c1, 0" : : "r" (v)); +} + +static u32 drbar_read(void) +{ + u32 v; + asm("mrc p15, 0, %0, c6, c1, 0" : "=r" (v)); + return v; +} +/* Optional instruction-side region attributes */ + +/* I-side Region access control register */ +static void iracr_write(u32 v) +{ + asm("mcr p15, 0, %0, c6, c1, 5" : : "r" (v)); +} + +/* I-side Region size register */ +static void irsr_write(u32 v) +{ + asm("mcr p15, 0, %0, c6, c1, 3" : : "r" (v)); +} + +/* I-side Region base address register */ +static void irbar_write(u32 v) +{ + asm("mcr p15, 0, %0, c6, c1, 1" : : "r" (v)); +} + +static unsigned long irbar_read(void) +{ + unsigned long v; + asm("mrc p15, 0, %0, c6, c1, 1" : "=r" (v)); + return v; +} + +/* MPU initialisation functions */ +void __init adjust_lowmem_bounds_mpu(void) +{ + phys_addr_t phys_offset = PHYS_OFFSET; + phys_addr_t aligned_region_size, specified_mem_size, rounded_mem_size; + struct memblock_region *reg; + bool first = true; + phys_addr_t mem_start; + phys_addr_t mem_end; + + for_each_memblock(memory, reg) { + if (first) { + /* + * Initially only use memory continuous from + * PHYS_OFFSET */ + if (reg->base != phys_offset) + panic("First memory bank must be contiguous from PHYS_OFFSET"); + + mem_start = reg->base; + mem_end = reg->base + reg->size; + specified_mem_size = reg->size; + first = false; + } else { + /* + * memblock auto merges contiguous blocks, remove + * all blocks afterwards in one go (we can't remove + * blocks separately while iterating) + */ + pr_notice("Ignoring RAM after %pa, memory at %pa ignored\n", + &mem_end, ®->base); + memblock_remove(reg->base, 0 - reg->base); + break; + } + } + + /* + * MPU has curious alignment requirements: Size must be power of 2, and + * region start must be aligned to the region size + */ + if (phys_offset != 0) + pr_info("PHYS_OFFSET != 0 => MPU Region size constrained by alignment requirements\n"); + + /* + * Maximum aligned region might overflow phys_addr_t if phys_offset is + * 0. Hence we keep everything below 4G until we take the smaller of + * the aligned_region_size and rounded_mem_size, one of which is + * guaranteed to be smaller than the maximum physical address. + */ + aligned_region_size = (phys_offset - 1) ^ (phys_offset); + /* Find the max power-of-two sized region that fits inside our bank */ + rounded_mem_size = (1 << __fls(specified_mem_size)) - 1; + + /* The actual region size is the smaller of the two */ + aligned_region_size = aligned_region_size < rounded_mem_size + ? aligned_region_size + 1 + : rounded_mem_size + 1; + + if (aligned_region_size != specified_mem_size) { + pr_warn("Truncating memory from %pa to %pa (MPU region constraints)", + &specified_mem_size, &aligned_region_size); + memblock_remove(mem_start + aligned_region_size, + specified_mem_size - aligned_region_size); + + mem_end = mem_start + aligned_region_size; + } + + pr_debug("MPU Region from %pa size %pa (end %pa))\n", + &phys_offset, &aligned_region_size, &mem_end); + +} + +static int mpu_present(void) +{ + return ((read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA) == MMFR0_PMSAv7); +} + +static int mpu_max_regions(void) +{ + /* + * We don't support a different number of I/D side regions so if we + * have separate instruction and data memory maps then return + * whichever side has a smaller number of supported regions. + */ + u32 dregions, iregions, mpuir; + mpuir = read_cpuid(CPUID_MPUIR); + + dregions = iregions = (mpuir & MPUIR_DREGION_SZMASK) >> MPUIR_DREGION; + + /* Check for separate d-side and i-side memory maps */ + if (mpuir & MPUIR_nU) + iregions = (mpuir & MPUIR_IREGION_SZMASK) >> MPUIR_IREGION; + + /* Use the smallest of the two maxima */ + return min(dregions, iregions); +} + +static int mpu_iside_independent(void) +{ + /* MPUIR.nU specifies whether there is *not* a unified memory map */ + return read_cpuid(CPUID_MPUIR) & MPUIR_nU; +} + +static int mpu_min_region_order(void) +{ + u32 drbar_result, irbar_result; + /* We've kept a region free for this probing */ + rgnr_write(MPU_PROBE_REGION); + isb(); + /* + * As per ARM ARM, write 0xFFFFFFFC to DRBAR to find the minimum + * region order + */ + drbar_write(0xFFFFFFFC); + drbar_result = irbar_result = drbar_read(); + drbar_write(0x0); + /* If the MPU is non-unified, we use the larger of the two minima*/ + if (mpu_iside_independent()) { + irbar_write(0xFFFFFFFC); + irbar_result = irbar_read(); + irbar_write(0x0); + } + isb(); /* Ensure that MPU region operations have completed */ + /* Return whichever result is larger */ + return __ffs(max(drbar_result, irbar_result)); +} + +static int mpu_setup_region(unsigned int number, phys_addr_t start, + unsigned int size_order, unsigned int properties) +{ + u32 size_data; + + /* We kept a region free for probing resolution of MPU regions*/ + if (number > mpu_max_regions() || number == MPU_PROBE_REGION) + return -ENOENT; + + if (size_order > 32) + return -ENOMEM; + + if (size_order < mpu_min_region_order()) + return -ENOMEM; + + /* Writing N to bits 5:1 (RSR_SZ) specifies region size 2^N+1 */ + size_data = ((size_order - 1) << MPU_RSR_SZ) | 1 << MPU_RSR_EN; + + dsb(); /* Ensure all previous data accesses occur with old mappings */ + rgnr_write(number); + isb(); + drbar_write(start); + dracr_write(properties); + isb(); /* Propagate properties before enabling region */ + drsr_write(size_data); + + /* Check for independent I-side registers */ + if (mpu_iside_independent()) { + irbar_write(start); + iracr_write(properties); + isb(); + irsr_write(size_data); + } + isb(); + + /* Store region info (we treat i/d side the same, so only store d) */ + mpu_rgn_info.rgns[number].dracr = properties; + mpu_rgn_info.rgns[number].drbar = start; + mpu_rgn_info.rgns[number].drsr = size_data; + return 0; +} + +/* +* Set up default MPU regions, doing nothing if there is no MPU +*/ +void __init mpu_setup(void) +{ + int region_err; + if (!mpu_present()) + return; + + region_err = mpu_setup_region(MPU_RAM_REGION, PHYS_OFFSET, + ilog2(memblock.memory.regions[0].size), + MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL); + if (region_err) { + panic("MPU region initialization failure! %d", region_err); + } else { + pr_info("Using ARMv7 PMSA Compliant MPU. " + "Region independence: %s, Max regions: %d\n", + mpu_iside_independent() ? "Yes" : "No", + mpu_max_regions()); + } +} -- cgit From e8b47e12d6c72f26a8ce85974f98a4050ac7ca24 Mon Sep 17 00:00:00 2001 From: Vladimir Murzin Date: Mon, 16 Oct 2017 12:53:18 +0100 Subject: ARM: 8707/1: NOMMU: Update MPU accessors to use cp15 helpers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently, inline assembly for accessing to MPU's cp15 lacks volatile keyword which opens possibility to compiler to optimise such accesses as soon as we start using them more intensively. Rather than fixing inline asm, lets move MPU accessors to use cp15 helpers which do the right thing. Tested-by: Szemző András Tested-by: Alexandre TORGUE Tested-by: Benjamin Gaignard Signed-off-by: Vladimir Murzin Signed-off-by: Russell King --- arch/arm/mm/pmsa-v7.c | 48 ++++++++++++++++++++++++++---------------------- 1 file changed, 26 insertions(+), 22 deletions(-) (limited to 'arch/arm/mm/pmsa-v7.c') diff --git a/arch/arm/mm/pmsa-v7.c b/arch/arm/mm/pmsa-v7.c index cc987715457d..484f5aa51090 100644 --- a/arch/arm/mm/pmsa-v7.c +++ b/arch/arm/mm/pmsa-v7.c @@ -12,63 +12,67 @@ #include "mm.h" +#define DRBAR __ACCESS_CP15(c6, 0, c1, 0) +#define IRBAR __ACCESS_CP15(c6, 0, c1, 1) +#define DRSR __ACCESS_CP15(c6, 0, c1, 2) +#define IRSR __ACCESS_CP15(c6, 0, c1, 3) +#define DRACR __ACCESS_CP15(c6, 0, c1, 4) +#define IRACR __ACCESS_CP15(c6, 0, c1, 5) +#define RNGNR __ACCESS_CP15(c6, 0, c2, 0) + /* Region number */ -static void rgnr_write(u32 v) +static inline void rgnr_write(u32 v) { - asm("mcr p15, 0, %0, c6, c2, 0" : : "r" (v)); + write_sysreg(v, RNGNR); } /* Data-side / unified region attributes */ /* Region access control register */ -static void dracr_write(u32 v) +static inline void dracr_write(u32 v) { - asm("mcr p15, 0, %0, c6, c1, 4" : : "r" (v)); + write_sysreg(v, DRACR); } /* Region size register */ -static void drsr_write(u32 v) +static inline void drsr_write(u32 v) { - asm("mcr p15, 0, %0, c6, c1, 2" : : "r" (v)); + write_sysreg(v, DRSR); } /* Region base address register */ -static void drbar_write(u32 v) +static inline void drbar_write(u32 v) { - asm("mcr p15, 0, %0, c6, c1, 0" : : "r" (v)); + write_sysreg(v, DRBAR); } -static u32 drbar_read(void) +static inline u32 drbar_read(void) { - u32 v; - asm("mrc p15, 0, %0, c6, c1, 0" : "=r" (v)); - return v; + return read_sysreg(DRBAR); } /* Optional instruction-side region attributes */ /* I-side Region access control register */ -static void iracr_write(u32 v) +static inline void iracr_write(u32 v) { - asm("mcr p15, 0, %0, c6, c1, 5" : : "r" (v)); + write_sysreg(v, IRACR); } /* I-side Region size register */ -static void irsr_write(u32 v) +static inline void irsr_write(u32 v) { - asm("mcr p15, 0, %0, c6, c1, 3" : : "r" (v)); + write_sysreg(v, IRSR); } /* I-side Region base address register */ -static void irbar_write(u32 v) +static inline void irbar_write(u32 v) { - asm("mcr p15, 0, %0, c6, c1, 1" : : "r" (v)); + write_sysreg(v, IRBAR); } -static unsigned long irbar_read(void) +static inline u32 irbar_read(void) { - unsigned long v; - asm("mrc p15, 0, %0, c6, c1, 1" : "=r" (v)); - return v; + return read_sysreg(IRBAR); } /* MPU initialisation functions */ -- cgit From a0995c0805b63c930b99970f2c9d5e4f167ca65b Mon Sep 17 00:00:00 2001 From: Vladimir Murzin Date: Mon, 16 Oct 2017 12:54:05 +0100 Subject: ARM: 8708/1: NOMMU: Rework MPU to be mostly done in C MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently, there are several issues with how MPU is setup: 1. We won't boot if MPU is missing 2. We won't boot if use XIP 3. Further extension of MPU setup requires asm skills The 1st point can be relaxed, so we can continue with boot CPU even if MPU is missed and fail boot for secondaries only. To address the 2nd point we could create region covering CONFIG_XIP_PHYS_ADDR - _end and that might work for the first stage of MPU enable, but due to MPU's alignment requirement we could cover too much, IOW we need more flexibility in how we're partitioning memory regions... and it'd be hardly possible to archive because of the 3rd point. This patch is trying to address 1st and 3rd issues and paves the path for 2nd and further improvements. The most visible change introduced with this patch is that we start using mpu_rgn_info array (as it was supposed?), so change in MPU setup done by boot CPU is recorded there and feed to secondaries. It allows us to keep minimal region setup for boot CPU and do the rest in C. Since we start programming MPU regions in C evaluation of MPU constrains (number of regions supported and minimal region order) can be done once, which in turn open possibility to free-up "probe" region early. Tested-by: Szemző András Tested-by: Alexandre TORGUE Tested-by: Benjamin Gaignard Signed-off-by: Vladimir Murzin Signed-off-by: Russell King --- arch/arm/mm/pmsa-v7.c | 70 +++++++++++++++++++++++++++++++++++++-------------- 1 file changed, 51 insertions(+), 19 deletions(-) (limited to 'arch/arm/mm/pmsa-v7.c') diff --git a/arch/arm/mm/pmsa-v7.c b/arch/arm/mm/pmsa-v7.c index 484f5aa51090..cd798271a78d 100644 --- a/arch/arm/mm/pmsa-v7.c +++ b/arch/arm/mm/pmsa-v7.c @@ -12,6 +12,9 @@ #include "mm.h" +static unsigned int __initdata mpu_min_region_order; +static unsigned int __initdata mpu_max_regions; + #define DRBAR __ACCESS_CP15(c6, 0, c1, 0) #define IRBAR __ACCESS_CP15(c6, 0, c1, 1) #define DRSR __ACCESS_CP15(c6, 0, c1, 2) @@ -75,6 +78,11 @@ static inline u32 irbar_read(void) return read_sysreg(IRBAR); } +static int __init mpu_present(void) +{ + return ((read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA) == MMFR0_PMSAv7); +} + /* MPU initialisation functions */ void __init adjust_lowmem_bounds_mpu(void) { @@ -85,6 +93,9 @@ void __init adjust_lowmem_bounds_mpu(void) phys_addr_t mem_start; phys_addr_t mem_end; + if (!mpu_present()) + return; + for_each_memblock(memory, reg) { if (first) { /* @@ -146,12 +157,7 @@ void __init adjust_lowmem_bounds_mpu(void) } -static int mpu_present(void) -{ - return ((read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA) == MMFR0_PMSAv7); -} - -static int mpu_max_regions(void) +static int __init __mpu_max_regions(void) { /* * We don't support a different number of I/D side regions so if we @@ -159,6 +165,7 @@ static int mpu_max_regions(void) * whichever side has a smaller number of supported regions. */ u32 dregions, iregions, mpuir; + mpuir = read_cpuid(CPUID_MPUIR); dregions = iregions = (mpuir & MPUIR_DREGION_SZMASK) >> MPUIR_DREGION; @@ -171,15 +178,16 @@ static int mpu_max_regions(void) return min(dregions, iregions); } -static int mpu_iside_independent(void) +static int __init mpu_iside_independent(void) { /* MPUIR.nU specifies whether there is *not* a unified memory map */ return read_cpuid(CPUID_MPUIR) & MPUIR_nU; } -static int mpu_min_region_order(void) +static int __init __mpu_min_region_order(void) { u32 drbar_result, irbar_result; + /* We've kept a region free for this probing */ rgnr_write(MPU_PROBE_REGION); isb(); @@ -198,22 +206,24 @@ static int mpu_min_region_order(void) } isb(); /* Ensure that MPU region operations have completed */ /* Return whichever result is larger */ + return __ffs(max(drbar_result, irbar_result)); } -static int mpu_setup_region(unsigned int number, phys_addr_t start, +static int __init mpu_setup_region(unsigned int number, phys_addr_t start, unsigned int size_order, unsigned int properties) { u32 size_data; /* We kept a region free for probing resolution of MPU regions*/ - if (number > mpu_max_regions() || number == MPU_PROBE_REGION) + if (number > mpu_max_regions + || number >= MPU_MAX_REGIONS) return -ENOENT; if (size_order > 32) return -ENOMEM; - if (size_order < mpu_min_region_order()) + if (size_order < mpu_min_region_order) return -ENOMEM; /* Writing N to bits 5:1 (RSR_SZ) specifies region size 2^N+1 */ @@ -240,6 +250,9 @@ static int mpu_setup_region(unsigned int number, phys_addr_t start, mpu_rgn_info.rgns[number].dracr = properties; mpu_rgn_info.rgns[number].drbar = start; mpu_rgn_info.rgns[number].drsr = size_data; + + mpu_rgn_info.used++; + return 0; } @@ -248,19 +261,38 @@ static int mpu_setup_region(unsigned int number, phys_addr_t start, */ void __init mpu_setup(void) { - int region_err; + int region = 0, err = 0; + if (!mpu_present()) return; - region_err = mpu_setup_region(MPU_RAM_REGION, PHYS_OFFSET, - ilog2(memblock.memory.regions[0].size), - MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL); - if (region_err) { - panic("MPU region initialization failure! %d", region_err); + /* Free-up MPU_PROBE_REGION */ + mpu_min_region_order = __mpu_min_region_order(); + + /* How many regions are supported */ + mpu_max_regions = __mpu_max_regions(); + + /* Now setup MPU (order is important) */ + + /* Background */ + err |= mpu_setup_region(region++, 0, 32, + MPU_ACR_XN | MPU_RGN_STRONGLY_ORDERED | MPU_AP_PL1RW_PL0NA); + + /* RAM */ + err |= mpu_setup_region(region++, PHYS_OFFSET, + ilog2(memblock.memory.regions[0].size), + MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL); + + /* Vectors */ + err |= mpu_setup_region(region++, vectors_base, + ilog2(2 * PAGE_SIZE), + MPU_AP_PL1RW_PL0NA | MPU_RGN_NORMAL); + if (err) { + panic("MPU region initialization failure! %d", err); } else { pr_info("Using ARMv7 PMSA Compliant MPU. " - "Region independence: %s, Max regions: %d\n", + "Region independence: %s, Used %d of %d regions\n", mpu_iside_independent() ? "Yes" : "No", - mpu_max_regions()); + mpu_rgn_info.used, mpu_max_regions); } } -- cgit From 9fcb01a9f54c28062a73a545c29137a4cc104c72 Mon Sep 17 00:00:00 2001 From: Vladimir Murzin Date: Mon, 16 Oct 2017 12:57:48 +0100 Subject: ARM: 8711/1: V7M: Add support for MPU to M-class MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch makes it possible to use MPU with v7M cores. Tested-by: Szemző András Tested-by: Alexandre TORGUE Tested-by: Benjamin Gaignard Signed-off-by: Vladimir Murzin Signed-off-by: Russell King --- arch/arm/mm/pmsa-v7.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 51 insertions(+), 2 deletions(-) (limited to 'arch/arm/mm/pmsa-v7.c') diff --git a/arch/arm/mm/pmsa-v7.c b/arch/arm/mm/pmsa-v7.c index cd798271a78d..06e2a853cab9 100644 --- a/arch/arm/mm/pmsa-v7.c +++ b/arch/arm/mm/pmsa-v7.c @@ -15,6 +15,8 @@ static unsigned int __initdata mpu_min_region_order; static unsigned int __initdata mpu_max_regions; +#ifndef CONFIG_CPU_V7M + #define DRBAR __ACCESS_CP15(c6, 0, c1, 0) #define IRBAR __ACCESS_CP15(c6, 0, c1, 1) #define DRSR __ACCESS_CP15(c6, 0, c1, 2) @@ -78,6 +80,51 @@ static inline u32 irbar_read(void) return read_sysreg(IRBAR); } +#else + +static inline void rgnr_write(u32 v) +{ + writel_relaxed(v, BASEADDR_V7M_SCB + MPU_RNR); +} + +/* Data-side / unified region attributes */ + +/* Region access control register */ +static inline void dracr_write(u32 v) +{ + u32 rsr = readl_relaxed(BASEADDR_V7M_SCB + MPU_RASR) & GENMASK(15, 0); + + writel_relaxed((v << 16) | rsr, BASEADDR_V7M_SCB + MPU_RASR); +} + +/* Region size register */ +static inline void drsr_write(u32 v) +{ + u32 racr = readl_relaxed(BASEADDR_V7M_SCB + MPU_RASR) & GENMASK(31, 16); + + writel_relaxed(v | racr, BASEADDR_V7M_SCB + MPU_RASR); +} + +/* Region base address register */ +static inline void drbar_write(u32 v) +{ + writel_relaxed(v, BASEADDR_V7M_SCB + MPU_RBAR); +} + +static inline u32 drbar_read(void) +{ + return readl_relaxed(BASEADDR_V7M_SCB + MPU_RBAR); +} + +/* ARMv7-M only supports a unified MPU, so I-side operations are nop */ + +static inline void iracr_write(u32 v) {} +static inline void irsr_write(u32 v) {} +static inline void irbar_write(u32 v) {} +static inline unsigned long irbar_read(void) {return 0;} + +#endif + static int __init mpu_present(void) { return ((read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA) == MMFR0_PMSAv7); @@ -166,7 +213,7 @@ static int __init __mpu_max_regions(void) */ u32 dregions, iregions, mpuir; - mpuir = read_cpuid(CPUID_MPUIR); + mpuir = read_cpuid_mputype(); dregions = iregions = (mpuir & MPUIR_DREGION_SZMASK) >> MPUIR_DREGION; @@ -181,7 +228,7 @@ static int __init __mpu_max_regions(void) static int __init mpu_iside_independent(void) { /* MPUIR.nU specifies whether there is *not* a unified memory map */ - return read_cpuid(CPUID_MPUIR) & MPUIR_nU; + return read_cpuid_mputype() & MPUIR_nU; } static int __init __mpu_min_region_order(void) @@ -284,9 +331,11 @@ void __init mpu_setup(void) MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL); /* Vectors */ +#ifndef CONFIG_CPU_V7M err |= mpu_setup_region(region++, vectors_base, ilog2(2 * PAGE_SIZE), MPU_AP_PL1RW_PL0NA | MPU_RGN_NORMAL); +#endif if (err) { panic("MPU region initialization failure! %d", err); } else { -- cgit From 5c9d9a1b3a540779ba3f2d5e81150b2d92dcb74a Mon Sep 17 00:00:00 2001 From: Vladimir Murzin Date: Mon, 16 Oct 2017 12:59:15 +0100 Subject: ARM: 8712/1: NOMMU: Use more MPU regions to cover memory MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PMSAv7 defines curious alignment requirements to the regions: - size must be power of 2, and - region start must be aligned to the region size Because of that we currently adjust lowmem bounds plus we assign only one MPU region to cover memory all these lead to significant amount of memory could be wasted. As an example, consider 64Mb of memory at 0x70000000 - it fits alignment requirements nicely; now, imagine that 2Mb of memory is reserved for coherent DMA allocation, so now Linux is expected to see 62Mb of memory... and here annoying thing happens - memory gets truncated to 32Mb (we've lost 30Mb!), i.e. MPU layout looks like: 0: base 0x70000000, size 0x2000000 This patch tries to allocate as much as possible MPU slots to minimise amount of truncated memory. Moreover, with this patch MPU subregions starting to get used. MPU subregions allow us reduce the number of MPU slots used. For example given above, MPU layout looks like: 0: base 0x70000000, size 0x2000000 1: base 0x72000000, size 0x1000000 2: base 0x73000000, size 0x1000000, disable subreg 7 (0x73e00000 - 0x73ffffff) Where without subregions we'd get: 0: base 0x70000000, size 0x2000000 1: base 0x72000000, size 0x1000000 2: base 0x73000000, size 0x800000 3: base 0x73800000, size 0x400000 4: base 0x73c00000, size 0x200000 To achieve better layout we fist try to cover specified memory as is (maybe with help of subregions) and if we failed, we truncate memory to fit alignment requirements (so it occupies one MPU slot) and perform one more attempt with the reminder, and so on till we either cover all memory or run out of MPU slots. Tested-by: Szemző András Tested-by: Alexandre TORGUE Tested-by: Benjamin Gaignard Signed-off-by: Vladimir Murzin Signed-off-by: Russell King --- arch/arm/mm/pmsa-v7.c | 190 ++++++++++++++++++++++++++++++++++++++------------ 1 file changed, 144 insertions(+), 46 deletions(-) (limited to 'arch/arm/mm/pmsa-v7.c') diff --git a/arch/arm/mm/pmsa-v7.c b/arch/arm/mm/pmsa-v7.c index 06e2a853cab9..ef204634a16e 100644 --- a/arch/arm/mm/pmsa-v7.c +++ b/arch/arm/mm/pmsa-v7.c @@ -4,6 +4,7 @@ * ARM PMSAv7 supporting functions. */ +#include #include #include @@ -12,9 +13,20 @@ #include "mm.h" +struct region { + phys_addr_t base; + phys_addr_t size; + unsigned long subreg; +}; + +static struct region __initdata mem[MPU_MAX_REGIONS]; + static unsigned int __initdata mpu_min_region_order; static unsigned int __initdata mpu_max_regions; +static int __init __mpu_min_region_order(void); +static int __init __mpu_max_regions(void); + #ifndef CONFIG_CPU_V7M #define DRBAR __ACCESS_CP15(c6, 0, c1, 0) @@ -130,19 +142,120 @@ static int __init mpu_present(void) return ((read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA) == MMFR0_PMSAv7); } +static bool __init try_split_region(phys_addr_t base, phys_addr_t size, struct region *region) +{ + unsigned long subreg, bslots, sslots; + phys_addr_t abase = base & ~(size - 1); + phys_addr_t asize = base + size - abase; + phys_addr_t p2size = 1 << __fls(asize); + phys_addr_t bdiff, sdiff; + + if (p2size != asize) + p2size *= 2; + + bdiff = base - abase; + sdiff = p2size - asize; + subreg = p2size / MPU_NR_SUBREGS; + + if ((bdiff % subreg) || (sdiff % subreg)) + return false; + + bslots = bdiff / subreg; + sslots = sdiff / subreg; + + if (bslots || sslots) { + int i; + + if (subreg < MPU_MIN_SUBREG_SIZE) + return false; + + if (bslots + sslots > MPU_NR_SUBREGS) + return false; + + for (i = 0; i < bslots; i++) + _set_bit(i, ®ion->subreg); + + for (i = 1; i <= sslots; i++) + _set_bit(MPU_NR_SUBREGS - i, ®ion->subreg); + } + + region->base = abase; + region->size = p2size; + + return true; +} + +static int __init allocate_region(phys_addr_t base, phys_addr_t size, + unsigned int limit, struct region *regions) +{ + int count = 0; + phys_addr_t diff = size; + int attempts = MPU_MAX_REGIONS; + + while (diff) { + /* Try cover region as is (maybe with help of subregions) */ + if (try_split_region(base, size, ®ions[count])) { + count++; + base += size; + diff -= size; + size = diff; + } else { + /* + * Maximum aligned region might overflow phys_addr_t + * if "base" is 0. Hence we keep everything below 4G + * until we take the smaller of the aligned region + * size ("asize") and rounded region size ("p2size"), + * one of which is guaranteed to be smaller than the + * maximum physical address. + */ + phys_addr_t asize = (base - 1) ^ base; + phys_addr_t p2size = (1 << __fls(diff)) - 1; + + size = asize < p2size ? asize + 1 : p2size + 1; + } + + if (count > limit) + break; + + if (!attempts) + break; + + attempts--; + } + + return count; +} + /* MPU initialisation functions */ void __init adjust_lowmem_bounds_mpu(void) { phys_addr_t phys_offset = PHYS_OFFSET; - phys_addr_t aligned_region_size, specified_mem_size, rounded_mem_size; + phys_addr_t specified_mem_size, total_mem_size = 0; struct memblock_region *reg; bool first = true; phys_addr_t mem_start; phys_addr_t mem_end; + unsigned int mem_max_regions; + int num, i; if (!mpu_present()) return; + /* Free-up MPU_PROBE_REGION */ + mpu_min_region_order = __mpu_min_region_order(); + + /* How many regions are supported */ + mpu_max_regions = __mpu_max_regions(); + + mem_max_regions = min((unsigned int)MPU_MAX_REGIONS, mpu_max_regions); + + /* We need to keep one slot for background region */ + mem_max_regions--; + +#ifndef CONFIG_CPU_V7M + /* ... and one for vectors */ + mem_max_regions--; +#endif for_each_memblock(memory, reg) { if (first) { /* @@ -168,40 +281,23 @@ void __init adjust_lowmem_bounds_mpu(void) } } - /* - * MPU has curious alignment requirements: Size must be power of 2, and - * region start must be aligned to the region size - */ - if (phys_offset != 0) - pr_info("PHYS_OFFSET != 0 => MPU Region size constrained by alignment requirements\n"); - - /* - * Maximum aligned region might overflow phys_addr_t if phys_offset is - * 0. Hence we keep everything below 4G until we take the smaller of - * the aligned_region_size and rounded_mem_size, one of which is - * guaranteed to be smaller than the maximum physical address. - */ - aligned_region_size = (phys_offset - 1) ^ (phys_offset); - /* Find the max power-of-two sized region that fits inside our bank */ - rounded_mem_size = (1 << __fls(specified_mem_size)) - 1; + num = allocate_region(mem_start, specified_mem_size, mem_max_regions, mem); - /* The actual region size is the smaller of the two */ - aligned_region_size = aligned_region_size < rounded_mem_size - ? aligned_region_size + 1 - : rounded_mem_size + 1; + for (i = 0; i < num; i++) { + unsigned long subreg = mem[i].size / MPU_NR_SUBREGS; - if (aligned_region_size != specified_mem_size) { - pr_warn("Truncating memory from %pa to %pa (MPU region constraints)", - &specified_mem_size, &aligned_region_size); - memblock_remove(mem_start + aligned_region_size, - specified_mem_size - aligned_region_size); + total_mem_size += mem[i].size - subreg * hweight_long(mem[i].subreg); - mem_end = mem_start + aligned_region_size; + pr_debug("MPU: base %pa size %pa disable subregions: %*pbl\n", + &mem[i].base, &mem[i].size, MPU_NR_SUBREGS, &mem[i].subreg); } - pr_debug("MPU Region from %pa size %pa (end %pa))\n", - &phys_offset, &aligned_region_size, &mem_end); - + if (total_mem_size != specified_mem_size) { + pr_warn("Truncating memory from %pa to %pa (MPU region constraints)", + &specified_mem_size, &total_mem_size); + memblock_remove(mem_start + total_mem_size, + specified_mem_size - total_mem_size); + } } static int __init __mpu_max_regions(void) @@ -258,7 +354,8 @@ static int __init __mpu_min_region_order(void) } static int __init mpu_setup_region(unsigned int number, phys_addr_t start, - unsigned int size_order, unsigned int properties) + unsigned int size_order, unsigned int properties, + unsigned int subregions) { u32 size_data; @@ -275,6 +372,7 @@ static int __init mpu_setup_region(unsigned int number, phys_addr_t start, /* Writing N to bits 5:1 (RSR_SZ) specifies region size 2^N+1 */ size_data = ((size_order - 1) << MPU_RSR_SZ) | 1 << MPU_RSR_EN; + size_data |= subregions << MPU_RSR_SD; dsb(); /* Ensure all previous data accesses occur with old mappings */ rgnr_write(number); @@ -308,33 +406,33 @@ static int __init mpu_setup_region(unsigned int number, phys_addr_t start, */ void __init mpu_setup(void) { - int region = 0, err = 0; + int i, region = 0, err = 0; if (!mpu_present()) return; - /* Free-up MPU_PROBE_REGION */ - mpu_min_region_order = __mpu_min_region_order(); - - /* How many regions are supported */ - mpu_max_regions = __mpu_max_regions(); - - /* Now setup MPU (order is important) */ + /* Setup MPU (order is important) */ /* Background */ err |= mpu_setup_region(region++, 0, 32, - MPU_ACR_XN | MPU_RGN_STRONGLY_ORDERED | MPU_AP_PL1RW_PL0NA); + MPU_ACR_XN | MPU_RGN_STRONGLY_ORDERED | MPU_AP_PL1RW_PL0NA, + 0); /* RAM */ - err |= mpu_setup_region(region++, PHYS_OFFSET, - ilog2(memblock.memory.regions[0].size), - MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL); + for (i = 0; i < ARRAY_SIZE(mem); i++) { + if (!mem[i].size) + continue; + + err |= mpu_setup_region(region++, mem[i].base, ilog2(mem[i].size), + MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL, + mem[i].subreg); + } /* Vectors */ #ifndef CONFIG_CPU_V7M - err |= mpu_setup_region(region++, vectors_base, - ilog2(2 * PAGE_SIZE), - MPU_AP_PL1RW_PL0NA | MPU_RGN_NORMAL); + err |= mpu_setup_region(region++, vectors_base, ilog2(2 * PAGE_SIZE), + MPU_AP_PL1RW_PL0NA | MPU_RGN_NORMAL, + 0); #endif if (err) { panic("MPU region initialization failure! %d", err); -- cgit From 216218308cfb0939aeecb246b34faf6e179c8d57 Mon Sep 17 00:00:00 2001 From: Vladimir Murzin Date: Mon, 16 Oct 2017 13:00:45 +0100 Subject: ARM: 8713/1: NOMMU: Support MPU in XIP configuration Currently, there is assumption in early MPU setup code that kernel image is located in RAM, which is obviously not true for XIP. To run code from ROM we need to make sure that it is covered by MPU. However, due to we allocate regions (semi-)dynamically we can run into issue of trimming region we are running from in case ROM spawns several MPU regions. To help deal with that we enforce minimum alignments for start end end of XIP address space as 1MB and 128Kb correspondingly. Tested-by: Alexandre TORGUE Tested-by: Benjamin Gaignard Signed-off-by: Vladimir Murzin Signed-off-by: Russell King --- arch/arm/mm/pmsa-v7.c | 49 ++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 44 insertions(+), 5 deletions(-) (limited to 'arch/arm/mm/pmsa-v7.c') diff --git a/arch/arm/mm/pmsa-v7.c b/arch/arm/mm/pmsa-v7.c index ef204634a16e..106ae1c435a3 100644 --- a/arch/arm/mm/pmsa-v7.c +++ b/arch/arm/mm/pmsa-v7.c @@ -7,9 +7,11 @@ #include #include +#include #include #include #include +#include #include "mm.h" @@ -20,6 +22,9 @@ struct region { }; static struct region __initdata mem[MPU_MAX_REGIONS]; +#ifdef CONFIG_XIP_KERNEL +static struct region __initdata xip[MPU_MAX_REGIONS]; +#endif static unsigned int __initdata mpu_min_region_order; static unsigned int __initdata mpu_max_regions; @@ -229,7 +234,6 @@ static int __init allocate_region(phys_addr_t base, phys_addr_t size, /* MPU initialisation functions */ void __init adjust_lowmem_bounds_mpu(void) { - phys_addr_t phys_offset = PHYS_OFFSET; phys_addr_t specified_mem_size, total_mem_size = 0; struct memblock_region *reg; bool first = true; @@ -256,8 +260,19 @@ void __init adjust_lowmem_bounds_mpu(void) /* ... and one for vectors */ mem_max_regions--; #endif + +#ifdef CONFIG_XIP_KERNEL + /* plus some regions to cover XIP ROM */ + num = allocate_region(CONFIG_XIP_PHYS_ADDR, __pa(_exiprom) - CONFIG_XIP_PHYS_ADDR, + mem_max_regions, xip); + + mem_max_regions -= num; +#endif + for_each_memblock(memory, reg) { if (first) { + phys_addr_t phys_offset = PHYS_OFFSET; + /* * Initially only use memory continuous from * PHYS_OFFSET */ @@ -355,7 +370,7 @@ static int __init __mpu_min_region_order(void) static int __init mpu_setup_region(unsigned int number, phys_addr_t start, unsigned int size_order, unsigned int properties, - unsigned int subregions) + unsigned int subregions, bool need_flush) { u32 size_data; @@ -374,6 +389,9 @@ static int __init mpu_setup_region(unsigned int number, phys_addr_t start, size_data = ((size_order - 1) << MPU_RSR_SZ) | 1 << MPU_RSR_EN; size_data |= subregions << MPU_RSR_SD; + if (need_flush) + flush_cache_all(); + dsb(); /* Ensure all previous data accesses occur with old mappings */ rgnr_write(number); isb(); @@ -416,7 +434,28 @@ void __init mpu_setup(void) /* Background */ err |= mpu_setup_region(region++, 0, 32, MPU_ACR_XN | MPU_RGN_STRONGLY_ORDERED | MPU_AP_PL1RW_PL0NA, - 0); + 0, false); + +#ifdef CONFIG_XIP_KERNEL + /* ROM */ + for (i = 0; i < ARRAY_SIZE(xip); i++) { + /* + * In case we overwrite RAM region we set earlier in + * head-nommu.S (which is cachable) all subsequent + * data access till we setup RAM bellow would be done + * with BG region (which is uncachable), thus we need + * to clean and invalidate cache. + */ + bool need_flush = region == MPU_RAM_REGION; + + if (!xip[i].size) + continue; + + err |= mpu_setup_region(region++, xip[i].base, ilog2(xip[i].size), + MPU_AP_PL1RO_PL0NA | MPU_RGN_NORMAL, + xip[i].subreg, need_flush); + } +#endif /* RAM */ for (i = 0; i < ARRAY_SIZE(mem); i++) { @@ -425,14 +464,14 @@ void __init mpu_setup(void) err |= mpu_setup_region(region++, mem[i].base, ilog2(mem[i].size), MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL, - mem[i].subreg); + mem[i].subreg, false); } /* Vectors */ #ifndef CONFIG_CPU_V7M err |= mpu_setup_region(region++, vectors_base, ilog2(2 * PAGE_SIZE), MPU_AP_PL1RW_PL0NA | MPU_RGN_NORMAL, - 0); + 0, false); #endif if (err) { panic("MPU region initialization failure! %d", err); -- cgit From fe9c0589eeef4b3edbaad9f7500679a2eeafe951 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 2 Nov 2017 13:20:31 +0100 Subject: ARM: 8719/1: NOMMU: work around maybe-uninitialized warning The reworked MPU code produces a new warning in some configurations, presumably starting with the code move after the compiler now makes different inlining decisions: arch/arm/mm/pmsa-v7.c: In function 'adjust_lowmem_bounds_mpu': arch/arm/mm/pmsa-v7.c:310:5: error: 'specified_mem_size' may be used uninitialized in this function [-Werror=maybe-uninitialized] This appears to be harmless, as we know that there is always at least one memblock, and the only way this could get triggered is if the for_each_memblock() loop was never entered. I could not come up with a better workaround than initializing the specified_mem_size to zero, but at least that is the value that the variable would have in the hypothetical case of no memblocks. Fixes: 877ec119dbbf ("ARM: 8706/1: NOMMU: Move out MPU setup in separate module") Signed-off-by: Arnd Bergmann Reviewed-by: Vladimir Murzin Signed-off-by: Russell King --- arch/arm/mm/pmsa-v7.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mm/pmsa-v7.c') diff --git a/arch/arm/mm/pmsa-v7.c b/arch/arm/mm/pmsa-v7.c index 106ae1c435a3..976df60ac426 100644 --- a/arch/arm/mm/pmsa-v7.c +++ b/arch/arm/mm/pmsa-v7.c @@ -234,7 +234,7 @@ static int __init allocate_region(phys_addr_t base, phys_addr_t size, /* MPU initialisation functions */ void __init adjust_lowmem_bounds_mpu(void) { - phys_addr_t specified_mem_size, total_mem_size = 0; + phys_addr_t specified_mem_size = 0, total_mem_size = 0; struct memblock_region *reg; bool first = true; phys_addr_t mem_start; -- cgit