From c00a19c8b143db31d660ee965e6a6f782ef090ff Mon Sep 17 00:00:00 2001 From: Amit Daniel Kachhap Date: Thu, 17 Nov 2022 06:28:22 +0100 Subject: ARM: 9268/1: vfp: Add hwcap FPHP and ASIMDHP for FEAT_FP16 Floating point half-precision (FPHP) and Advanced SIMD half-precision (ASIMDHP) are VFP features (FEAT_FP16) represented by MVFR1 identification register. These capabilities can optionally exist with VFPv3 and mandatory with VFPv4. Both these new features exist for Armv8 architecture in AArch32 state. These hwcaps may be useful for the userspace to add conditional check before trying to use FEAT_FP16 feature specific instructions. Reviewed-by: Linus Walleij Signed-off-by: Amit Daniel Kachhap Signed-off-by: Russell King (Oracle) --- arch/arm/vfp/vfpmodule.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/vfp') diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c index 2cb355c1b5b7..55dcd96c7e3b 100644 --- a/arch/arm/vfp/vfpmodule.c +++ b/arch/arm/vfp/vfpmodule.c @@ -831,6 +831,10 @@ static int __init vfp_init(void) if ((fmrx(MVFR1) & 0xf0000000) == 0x10000000) elf_hwcap |= HWCAP_VFPv4; + if (((fmrx(MVFR1) & MVFR1_ASIMDHP_MASK) >> MVFR1_ASIMDHP_BIT) == 0x2) + elf_hwcap |= HWCAP_ASIMDHP; + if (((fmrx(MVFR1) & MVFR1_FPHP_MASK) >> MVFR1_FPHP_BIT) == 0x3) + elf_hwcap |= HWCAP_FPHP; } /* Extract the architecture version on pre-cpuid scheme */ } else { -- cgit