From 4035ff36a6e0a07a1f0b0609520e17bd69a74c8b Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 20 Aug 2019 07:29:01 +0000 Subject: arm64: dts: fsl: Remove num-lanes property from PCIe nodes Remove the num-lanes property to avoid the driver setting the link width. On FSL Layerscape SoCs, the number of lanes assigned to PCIe controller is not fixed, it is determined by the selected SerDes protocol in the RCW (Reset Configuration Word). The PCIe link training is completed automatically through the selected SerDes protocol - the link width set-up is updated by hardware after power on reset, so the num-lanes property is not needed for Layerscape PCIe. The current num-lanes property was added erroneously, which actually indicates the maximum lanes the PCIe controller can support up to, instead of the lanes assigned to the PCIe controller. The link width set by SerDes protocol will be overridden by the num-lanes property, hence the subsequent re-training will fail when the assigned lanes do not match the value in the num-lanes property. Remove the property to fix the issue Signed-off-by: Hou Zhiqiang Signed-off-by: Lorenzo Pieralisi Reviewed-by: Andrew Murray --- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi') diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 71d9ed9ff985..c084c7a4b6a6 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -677,7 +677,6 @@ #size-cells = <2>; device_type = "pci"; dma-coherent; - num-lanes = <4>; num-viewport = <6>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ @@ -704,7 +703,6 @@ #size-cells = <2>; device_type = "pci"; dma-coherent; - num-lanes = <2>; num-viewport = <6>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ @@ -731,7 +729,6 @@ #size-cells = <2>; device_type = "pci"; dma-coherent; - num-lanes = <2>; num-viewport = <6>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ -- cgit