From 8580b6aa02acc8a2094d01a291a06774ef6ded2e Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Wed, 14 Sep 2022 16:46:56 -0500 Subject: arm64: dts: ls1043a: Add SCFG phandle for PCIe nodes The LS1043A PCIe controller has some control registers in SCFG block, so add the SCFG phandle for each PCIe controller node. Signed-off-by: Hou Zhiqiang Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi') diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index d04d4ac66d2a..e1c5d685a9e3 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -901,6 +901,7 @@ <0000 0 0 2 &gic 0 111 0x4>, <0000 0 0 3 &gic 0 112 0x4>, <0000 0 0 4 &gic 0 113 0x4>; + fsl,pcie-scfg = <&scfg 0>; status = "disabled"; }; @@ -927,6 +928,7 @@ <0000 0 0 2 &gic 0 121 0x4>, <0000 0 0 3 &gic 0 122 0x4>, <0000 0 0 4 &gic 0 123 0x4>; + fsl,pcie-scfg = <&scfg 1>; status = "disabled"; }; @@ -953,6 +955,7 @@ <0000 0 0 2 &gic 0 155 0x4>, <0000 0 0 3 &gic 0 156 0x4>, <0000 0 0 4 &gic 0 157 0x4>; + fsl,pcie-scfg = <&scfg 2>; status = "disabled"; }; -- cgit