From 8c30e7caac7467a89a69b22d1de7b489aa26b8a8 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Sat, 25 Apr 2020 20:29:50 +0800 Subject: arm64: dts: imx8mn: Update VDD_ARM 1.2GHz setpoint voltage The latest datasheet Rev. 0.1, 03/2020 removes below constrain: "If VDD_SOC/GPU/DDR = 0.95V, then VDD_ARM must be >= 0.95V." So, for 1.2GHz setpoint VDD_ARM can use its typical voltage directly. The datasheet can be downloaded from below link: https://www.nxp.com/docs/en/data-sheet/IMX8MNCEC.pdf Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts/freescale/imx8mn.dtsi') diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index fa78f0163270..de6e2cfa8d1e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -121,7 +121,7 @@ opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <950000>; + opp-microvolt = <850000>; opp-supported-hw = <0xb00>, <0x7>; clock-latency-ns = <150000>; opp-suspend; -- cgit From 9e6337e6fdb1573ed0371557505d2292cb78245d Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 7 May 2020 13:56:10 +0800 Subject: arm64: dts: imx8m: assign clocks for A53 Assign IMX8M*_CLK_A53_SRC's parent to system pll1 and assign IMX8M*_CLK_A53_CORE's parent to arm pll out as what is done in drivers/clk/imx/clk-imx8m*.c, then we could remove the settings in driver which triggers lockdep warning. Reported-by: Leonard Crestez Reviewed-by: Dong Aisheng Reviewed-by: Leonard Crestez Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'arch/arm64/boot/dts/freescale/imx8mn.dtsi') diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index de6e2cfa8d1e..e5f206d08269 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -426,13 +426,17 @@ <&clk_ext3>, <&clk_ext4>; clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4"; - assigned-clocks = <&clk IMX8MN_CLK_NOC>, + assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>, + <&clk IMX8MN_CLK_A53_CORE>, + <&clk IMX8MN_CLK_NOC>, <&clk IMX8MN_CLK_AUDIO_AHB>, <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>, <&clk IMX8MN_SYS_PLL3>; - assigned-clock-parents = <&clk IMX8MN_SYS_PLL3_OUT>, + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>, + <&clk IMX8MN_ARM_PLL_OUT>, + <&clk IMX8MN_SYS_PLL3_OUT>, <&clk IMX8MN_SYS_PLL1_800M>; - assigned-clock-rates = <0>, + assigned-clock-rates = <0>, <0>, <0>, <400000000>, <400000000>, <600000000>; -- cgit