From 9ad9773e89f8e06148b2a0e77fcdcd716f8f3b18 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Fri, 11 Mar 2022 18:23:51 +0100
Subject: arm64: dts: imx8mp: Add missing speed grade phandle

And missing speed grade phandle to cpu@0 node.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Anson Huang <Anson.Huang@nxp.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: NXP Linux Team <linux-imx@nxp.com>
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
 arch/arm64/boot/dts/freescale/imx8mp.dtsi | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'arch/arm64/boot/dts/freescale/imx8mp.dtsi')

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index afd36374dccb..68e6c9099f65 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -59,6 +59,8 @@
 			d-cache-line-size = <64>;
 			d-cache-sets = <128>;
 			next-level-cache = <&A53_L2>;
+			nvmem-cells = <&cpu_speed_grade>;
+			nvmem-cell-names = "speed_grade";
 			#cooling-cells = <2>;
 		};
 
-- 
cgit