From 47cf40af64c35a69ef6a193c47768ad1bda29db2 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Fri, 4 Oct 2019 16:27:29 +0200 Subject: arm64: dts: marvell: Prepare the introduction of CP115 CP110 and CP115 are almost the same in terms of features and have a very limited set of differences. Let's create an armada-cp11x.dtsi file which will be used to instantiate both CP110 and CP115 nodes. The only changes between the two armada-cp11{0,x}.dtsi files are the following naming in macros: s/CP110/CP11X/. Signed-off-by: Miquel Raynal Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'arch/arm64/boot/dts/marvell/armada-70x0.dtsi') diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi index e5c6d7c25819..4e78ccd207b7 100644 --- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi @@ -17,23 +17,23 @@ /* * Instantiate the CP110 */ -#define CP110_NAME cp0 -#define CP110_BASE f2000000 -#define CP110_PCIE_IO_BASE 0xf9000000 -#define CP110_PCIE_MEM_BASE 0xf6000000 -#define CP110_PCIE0_BASE f2600000 -#define CP110_PCIE1_BASE f2620000 -#define CP110_PCIE2_BASE f2640000 +#define CP11X_NAME cp0 +#define CP11X_BASE f2000000 +#define CP11X_PCIE_IO_BASE 0xf9000000 +#define CP11X_PCIE_MEM_BASE 0xf6000000 +#define CP11X_PCIE0_BASE f2600000 +#define CP11X_PCIE1_BASE f2620000 +#define CP11X_PCIE2_BASE f2640000 #include "armada-cp110.dtsi" -#undef CP110_NAME -#undef CP110_BASE -#undef CP110_PCIE_IO_BASE -#undef CP110_PCIE_MEM_BASE -#undef CP110_PCIE0_BASE -#undef CP110_PCIE1_BASE -#undef CP110_PCIE2_BASE +#undef CP11X_NAME +#undef CP11X_BASE +#undef CP11X_PCIE_IO_BASE +#undef CP11X_PCIE_MEM_BASE +#undef CP11X_PCIE0_BASE +#undef CP11X_PCIE1_BASE +#undef CP11X_PCIE2_BASE &cp0_gpio1 { status = "okay"; -- cgit From 1399672e48b573f6526b9ac78cfd50314f0b01a6 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Fri, 4 Oct 2019 16:27:30 +0200 Subject: arm64: dts: marvell: Drop PCIe I/O ranges from CP11x file As an example, Armada 70x0 and 80x0 SoC 0xf9000000 region points to RUNIT/SPICS0 while it is referenced in the DT as PCIe I/O memory range. This shows that I/O memory has never been used/working on the old SoCs despite the region being advertised. As PCIe I/O ranges will not be supported in newer SoCs using CP11x co-processors, let's simply drop them. It is not harmful in any case as PCIe device drivers can do it all with the regular mapped memory anyway. Signed-off-by: Miquel Raynal Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm64/boot/dts/marvell/armada-70x0.dtsi') diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi index 4e78ccd207b7..ac28903ea409 100644 --- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi @@ -19,7 +19,6 @@ */ #define CP11X_NAME cp0 #define CP11X_BASE f2000000 -#define CP11X_PCIE_IO_BASE 0xf9000000 #define CP11X_PCIE_MEM_BASE 0xf6000000 #define CP11X_PCIE0_BASE f2600000 #define CP11X_PCIE1_BASE f2620000 @@ -29,7 +28,6 @@ #undef CP11X_NAME #undef CP11X_BASE -#undef CP11X_PCIE_IO_BASE #undef CP11X_PCIE_MEM_BASE #undef CP11X_PCIE0_BASE #undef CP11X_PCIE1_BASE -- cgit From 5f07b26e85dc86f017833ea745ff4e5b420280cd Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Fri, 4 Oct 2019 16:27:31 +0200 Subject: arm64: dts: marvell: Externalize PCIe macros from CP11x file PCIe macros are specific to CP110 and will not fit CP115 constraints. To keep the same way the files are organized, just move some macros out of the CP11x generic file and define them directly in SoC DTSI, instead of defining single addresses in the SoC DTSI and reusing them in macros. In the end: * CP11X_PCIE_MEM_BASE SoC define is dropped * CP11X_PCIEx_MEM_BASE is moved out of the generic DT to be put in the SoC files as it replaces the above definition. * As the CP11X_PCIEx_MEM_SIZE macro is also subject to change with newer SoCs, we put it in the SoC files as well. Signed-off-by: Miquel Raynal Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts/marvell/armada-70x0.dtsi') diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi index ac28903ea409..293403a1a333 100644 --- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi @@ -19,7 +19,8 @@ */ #define CP11X_NAME cp0 #define CP11X_BASE f2000000 -#define CP11X_PCIE_MEM_BASE 0xf6000000 +#define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000)) +#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 #define CP11X_PCIE0_BASE f2600000 #define CP11X_PCIE1_BASE f2620000 #define CP11X_PCIE2_BASE f2640000 @@ -28,7 +29,8 @@ #undef CP11X_NAME #undef CP11X_BASE -#undef CP11X_PCIE_MEM_BASE +#undef CP11X_PCIEx_MEM_BASE +#undef CP11X_PCIEx_MEM_SIZE #undef CP11X_PCIE0_BASE #undef CP11X_PCIE1_BASE #undef CP11X_PCIE2_BASE -- cgit