From 91f1be92eb511c549b1e2e723bdeb13e7cb33a99 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 2 Jan 2018 15:55:58 +0100 Subject: arm64: dts: marvell: replace cpm by cp0, cps by cp1 In preparation for the introduction of more than 2 CPs in upcoming SoCs, it makes sense to move away from the "CP master" (cpm) and "CP slave" (cps) naming, and use instead cp0/cp1. This commit is the result of: sed 's%cpm%cp0g%' arch/arm64/boot/dts/marvell/* sed 's%cps%cp1g%' arch/arm64/boot/dts/marvell/* So it is a purely mechaninal change. Signed-off-by: Thomas Petazzoni Suggested-by: Hanna Hawa Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts | 76 +++++++++++------------ 1 file changed, 38 insertions(+), 38 deletions(-) (limited to 'arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts') diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts index b3350827ee55..c7aca67bd244 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts @@ -84,9 +84,9 @@ v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 { compatible = "regulator-fixed"; enable-active-high; - gpio = <&cpm_gpio2 15 GPIO_ACTIVE_HIGH>; + gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&cpm_xhci_vbus_pins>; + pinctrl-0 = <&cp0_xhci_vbus_pins>; regulator-name = "v_5v0_usb3_hst_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -120,17 +120,17 @@ vqmmc-supply = <&v_vddo_h>; }; -&cpm_i2c0 { +&cp0_i2c0 { clock-frequency = <100000>; pinctrl-names = "default"; - pinctrl-0 = <&cpm_i2c0_pins>; + pinctrl-0 = <&cp0_i2c0_pins>; status = "okay"; }; -&cpm_i2c1 { +&cp0_i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; - pinctrl-0 = <&cpm_i2c1_pins>; + pinctrl-0 = <&cp0_i2c1_pins>; status = "okay"; i2c-switch@70 { @@ -157,9 +157,9 @@ }; }; -&cpm_mdio { +&cp0_mdio { pinctrl-names = "default"; - pinctrl-0 = <&cpm_ge_mdio_pins>; + pinctrl-0 = <&cp0_ge_mdio_pins>; status = "okay"; ge_phy: ethernet-phy@0 { @@ -167,44 +167,44 @@ }; }; -&cpm_pcie0 { +&cp0_pcie0 { pinctrl-names = "default"; - pinctrl-0 = <&cpm_pcie_pins>; + pinctrl-0 = <&cp0_pcie_pins>; num-lanes = <4>; num-viewport = <8>; - reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>; + reset-gpio = <&cp0_gpio1 20 GPIO_ACTIVE_LOW>; status = "okay"; }; -&cpm_pinctrl { - cpm_ge_mdio_pins: ge-mdio-pins { +&cp0_pinctrl { + cp0_ge_mdio_pins: ge-mdio-pins { marvell,pins = "mpp32", "mpp34"; marvell,function = "ge"; }; - cpm_i2c1_pins: i2c1-pins { + cp0_i2c1_pins: i2c1-pins { marvell,pins = "mpp35", "mpp36"; marvell,function = "i2c1"; }; - cpm_i2c0_pins: i2c0-pins { + cp0_i2c0_pins: i2c0-pins { marvell,pins = "mpp37", "mpp38"; marvell,function = "i2c0"; }; - cpm_xhci_vbus_pins: xhci0-vbus-pins { + cp0_xhci_vbus_pins: xhci0-vbus-pins { marvell,pins = "mpp47"; marvell,function = "gpio"; }; - cpm_pcie_pins: pcie-pins { + cp0_pcie_pins: pcie-pins { marvell,pins = "mpp52"; marvell,function = "gpio"; }; - cpm_sdhci_pins: sdhci-pins { + cp0_sdhci_pins: sdhci-pins { marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59", "mpp60", "mpp61"; marvell,function = "sdio"; }; }; -&cpm_xmdio { +&cp0_xmdio { status = "okay"; phy0: ethernet-phy@0 { @@ -218,83 +218,83 @@ }; }; -&cpm_ethernet { +&cp0_ethernet { status = "okay"; }; -&cpm_eth0 { +&cp0_eth0 { status = "okay"; /* Network PHY */ phy = <&phy0>; phy-mode = "10gbase-kr"; /* Generic PHY, providing serdes lanes */ - phys = <&cpm_comphy4 0>; + phys = <&cp0_comphy4 0>; }; -&cpm_sata0 { +&cp0_sata0 { /* CPM Lane 0 - U29 */ status = "okay"; }; -&cpm_sdhci0 { +&cp0_sdhci0 { /* U6 */ broken-cd; bus-width = <4>; pinctrl-names = "default"; - pinctrl-0 = <&cpm_sdhci_pins>; + pinctrl-0 = <&cp0_sdhci_pins>; status = "okay"; vqmmc-supply = <&v_3_3>; }; -&cpm_usb3_0 { +&cp0_usb3_0 { /* J38? - USB2.0 only */ status = "okay"; }; -&cpm_usb3_1 { +&cp0_usb3_1 { /* J38? - USB2.0 only */ status = "okay"; }; -&cps_ethernet { +&cp1_ethernet { status = "okay"; }; -&cps_eth0 { +&cp1_eth0 { status = "okay"; /* Network PHY */ phy = <&phy8>; phy-mode = "10gbase-kr"; /* Generic PHY, providing serdes lanes */ - phys = <&cps_comphy4 0>; + phys = <&cp1_comphy4 0>; }; -&cps_eth1 { +&cp1_eth1 { /* CPS Lane 0 - J5 (Gigabit RJ45) */ status = "okay"; /* Network PHY */ phy = <&ge_phy>; phy-mode = "sgmii"; /* Generic PHY, providing serdes lanes */ - phys = <&cps_comphy0 1>; + phys = <&cp1_comphy0 1>; }; -&cps_pinctrl { - cps_spi1_pins: spi1-pins { +&cp1_pinctrl { + cp1_spi1_pins: spi1-pins { marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16"; marvell,function = "spi1"; }; }; -&cps_sata0 { +&cp1_sata0 { /* CPS Lane 1 - U32 */ /* CPS Lane 3 - U31 */ status = "okay"; }; -&cps_spi1 { +&cp1_spi1 { pinctrl-names = "default"; - pinctrl-0 = <&cps_spi1_pins>; + pinctrl-0 = <&cp1_spi1_pins>; status = "okay"; spi-flash@0 { @@ -304,7 +304,7 @@ }; }; -&cps_usb3_0 { +&cp1_usb3_0 { /* CPS Lane 2 - CON7 */ usb-phy = <&usb3h0_phy>; status = "okay"; -- cgit