From 61192a9d8a6367ae1b8234876941b037910a2459 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Wed, 22 Jun 2022 16:23:00 +0300 Subject: arm64: tegra: Mark BPMP channels as no-memory-wc The Tegra SYSRAM contains regions access to which is restricted to certain hardware blocks on the system, and speculative accesses to those will cause issues. Patch 'misc: sram: Only map reserved areas in Tegra SYSRAM' attempted to resolve this by only mapping the regions specified in the device tree on the assumption that there are no such restricted areas within the 64K-aligned area of memory that contains the memory we wish to map. Turns out this assumption is wrong, as there are such areas above the 4K pages described in the device trees. As such, we need to use the bigger hammer that is no-memory-wc, which causes the memory to be mapped as Device memory to which speculative accesses are disallowed. As such, the previous patch in the series, 'firmware: tegra: bpmp: do only aligned access to IPC memory area', is required with this patch to make the BPMP driver only issue aligned memory accesses as those are also required with Device memory. Fixes: fec29bf04994 ("misc: sram: Only map reserved areas in Tegra SYSRAM") Signed-off-by: Mikko Perttunen Reviewed-by: Yousaf Kaukab Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64/boot/dts/nvidia/tegra186.dtsi') diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index cd8c4f392f0b..a87b52434939 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1843,6 +1843,7 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x30000000 0x50000>; + no-memory-wc; cpu_bpmp_tx: sram@4e000 { reg = <0x4e000 0x1000>; -- cgit