From b4791e695526939be3c4f043fe69222d2ba7c171 Mon Sep 17 00:00:00 2001 From: Danny Lin Date: Mon, 11 Jan 2021 17:32:53 -0800 Subject: arm64: dts: qcom: sm8250: Define CPU topology sm8250 has a big.LITTLE CPU setup with DynamIQ, so all cores are within the same CPU cluster and LLC (Last-Level Cache) domain. Define this topology to help the scheduler make decisions. Signed-off-by: Danny Lin Link: https://lore.kernel.org/r/20210112013255.415253-1-danny@kdrag0n.dev Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'arch/arm64/boot/dts/qcom/sm8250.dtsi') diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 1c3ab5a3783d..8d5c5d44187a 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -203,6 +203,42 @@ next-level-cache = <&L3_0>; }; }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + + core6 { + cpu = <&CPU6>; + }; + + core7 { + cpu = <&CPU7>; + }; + }; + }; }; firmware { -- cgit