From c681c6fcc5ddfa0492ca015b0bf325cd4881ce07 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Wed, 27 Oct 2021 16:37:26 +0200 Subject: arm64: dts: rockchip: add interrupt and headphone-detection for Rock Pi4's audio codec As schematics at [1] and [2] show C- and plus-revisions have interrupt and headphone detection lines of ES8316 codec connected. Add them to the respective device trees. [1] https://dl.radxa.com/rockpi4/docs/hw/rockpi4/rockpi_4c_v12_sch_20200620.pdf [2] https://dl.radxa.com/rockpi4/docs/hw/rockpi4/rockpi4b_plus_v16_sch_20200628.pdf Signed-off-by: Alex Bee Link: https://lore.kernel.org/r/20211027143726.165809-2-knaerzche@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 12 +++++++++++- arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts | 11 +++++++++++ arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts | 11 +++++++++++ arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts | 11 +++++++++++ 4 files changed, 44 insertions(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts/rockchip') diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi index 98136c88fa49..54f5957e704c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi @@ -36,7 +36,7 @@ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; }; - sound { + sound: sound { compatible = "audio-graph-card"; label = "Analog"; dais = <&i2s0_p0>; @@ -543,6 +543,16 @@ }; }; + es8316 { + hp_detect: hp-detect { + rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + hp_int: hp-int { + rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + pcie { pcie_pwr_en: pcie-pwr-en { rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts index 281a04b2f5e9..f5a68d8d072d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts @@ -12,3 +12,14 @@ model = "Radxa ROCK Pi 4A+"; compatible = "radxa,rockpi4a-plus", "radxa,rockpi4", "rockchip,rk3399"; }; + +&es8316 { + pinctrl-0 = <&hp_detect &hp_int>; + pinctrl-names = "default"; + interrupt-parent = <&gpio1>; + interrupts = ; +}; + +&sound { + hp-det-gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts index dfad13d2ab24..81bea953c891 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts @@ -17,6 +17,13 @@ }; }; +&es8316 { + pinctrl-0 = <&hp_detect &hp_int>; + pinctrl-names = "default"; + interrupt-parent = <&gpio1>; + interrupts = ; +}; + &sdio0 { status = "okay"; @@ -31,6 +38,10 @@ }; }; +&sound { + hp-det-gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; +}; + &uart0 { status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts index 99169bcd51c0..0ad7b6e22f70 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts @@ -17,6 +17,13 @@ }; }; +&es8316 { + pinctrl-0 = <&hp_detect &hp_int>; + pinctrl-names = "default"; + interrupt-parent = <&gpio1>; + interrupts = ; +}; + &sdio0 { status = "okay"; @@ -31,6 +38,10 @@ }; }; +&sound { + hp-det-gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; +}; + &uart0 { status = "okay"; -- cgit From e92df2c61c1046d26379b97141e1e968f3ccc63d Mon Sep 17 00:00:00 2001 From: Dennis Gilmore Date: Tue, 26 Oct 2021 10:07:47 -0500 Subject: arm64: dts: rockchip: define usb hub and 2.5GbE nic on helios64 Add the 4 ports on the internal hub and define and turn on the 2.5GbE nic. Signed-off-by: Dennis Gilmore Tested-by: Florian Klink Link: https://lore.kernel.org/r/20211026150751.70115-1-dgilmore@redhat.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3399-kobol-helios64.dts | 52 ++++++++++++++++++++++ 1 file changed, 52 insertions(+) (limited to 'arch/arm64/boot/dts/rockchip') diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts index 63c7681843da..8767dd2891ae 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts @@ -101,6 +101,18 @@ vin-supply = <&vcc5v0_perdev>; }; + usblan_power: usblan-power { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_lan_en>; + regulator-name = "usblan_power"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_usb>; + }; + vcc1v8_sys_s0: vcc1v8-sys-s0 { compatible = "regulator-fixed"; regulator-name = "vcc1v8_sys_s0"; @@ -432,6 +444,10 @@ vcc5v0_usb_en: vcc5v0-usb-en { rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; }; + + usb_lan_en: usb-lan-en { + rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; }; vcc3v0-sd { @@ -530,5 +546,41 @@ usb@fe900000 { dr_mode = "host"; status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + hub@1 { + compatible = "usb2109,0815"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + port@2 { + reg = <2>; + #trigger-source-cells = <0>; + }; + + port@3 { + reg = <3>; + #trigger-source-cells = <0>; + }; + + device@4 { + compatible = "usbbda,8156"; + reg = <4>; + #address-cells = <2>; + #size-cells = <0>; + + interface@0 { /* interface 0 of configuration 1 */ + compatible = "usbbda,8156.config1.0"; + reg = <0 1>; + }; + }; + }; }; }; -- cgit From 755fff528b1b760c700dbf39928ff3dda825f748 Mon Sep 17 00:00:00 2001 From: Dennis Gilmore Date: Thu, 28 Oct 2021 19:53:19 -0500 Subject: arm64: dts: rockchip: add variables for pcie completion to helios64 without ep-gpios defined u-boot does not initialise PCIe rockchip_pcie pcie@f8000000: failed to find ep-gpios property additionally set max-link-speed and pinctrl-names for completeness with this patch and the ones from Florian Klink applied to the dts file in u-boot sata drives show up in both u-boot and linux Signed-off-by: Dennis Gilmore Acked-By: Florian Klink Link: https://lore.kernel.org/r/20211029005323.144652-1-dgilmore@redhat.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm64/boot/dts/rockchip') diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts index 8767dd2891ae..ac193e5a2295 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts @@ -401,7 +401,10 @@ }; &pcie0 { + ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; + max-link-speed = <2>; num-lanes = <2>; + pinctrl-names = "default"; status = "okay"; vpcie12v-supply = <&vcc12v_dcin>; -- cgit From 8169b9894dbd2d4e440cfbc5fe9f733e5876a564 Mon Sep 17 00:00:00 2001 From: Florian Klink Date: Wed, 20 Oct 2021 11:59:22 +0200 Subject: arm64: dts: rockchip: Enable HDD power on helios64 This adds the hdd_{a,b}_power blocks present in the armbian helios64 dts. [1] Without those powered up, no HDDs will appear (except one connected via the m.2 slot). >From https://wiki.kobol.io/helios64/sata/#hdd-power: > The power delivery of the HDDs is divided into two group: > > HDD Rail A (Max. 3x Drives) > HDD Rail B (Max. 2x Drives) > > Helios64 implements a power staggering approach where HDD Rail A will be > powered up first, then few seconds later HDD Rail B will be powered up. > This power control scenario is performed to reduce the inrush current > during disk spin-up. In practice, this power staggering approach will be included in the bootloader (not in the kernel), as we might want to boot from a SATA drive. >From my experiments, if the bootloader doesn't implement the power staggering, only one HDD will get recognized (probably cause the others didn't boot due to few power). Still, it makes sense to expose this block in the device-tree, so the kernel can ensure both rails are on (and this can be shared with u-boot). [1] https://github.com/armbian/build/blob/744ea89a589d62cb6f409baab60fc6664520bc39/patch/kernel/archive/rockchip64-5.14/add-board-helios64.patch Signed-off-by: Florian Klink Tested-by: Dennis Gilmore Link: https://lore.kernel.org/r/20211020095926.735938-1-flokli@flokli.de Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3399-kobol-helios64.dts | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'arch/arm64/boot/dts/rockchip') diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts index ac193e5a2295..627ee88e9dc2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts @@ -89,6 +89,30 @@ }; }; + hdd_a_power: hdd-a-power { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&hdd_a_power_en>; + pinctrl-names = "default"; + regulator-always-on; + regulator-boot-on; + regulator-name = "hdd_a_power"; + startup-delay-us = <2000000>; + }; + + hdd_b_power: hdd-b-power { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&hdd_b_power_en>; + pinctrl-names = "default"; + regulator-always-on; + regulator-boot-on; + regulator-name = "hdd_b_power"; + startup-delay-us = <2000000>; + }; + pcie_power: pcie-power { compatible = "regulator-fixed"; enable-active-high; @@ -444,6 +468,14 @@ }; power { + hdd_a_power_en: hdd-a-power-en { + rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + hdd_b_power_en: hdd-b-power-en { + rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vcc5v0_usb_en: vcc5v0-usb-en { rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; }; -- cgit From 2e4dbcf7177e5dd1f7cb53c59cb2f394e35fd7ba Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 8 Dec 2021 13:03:12 +0100 Subject: arm64: dts: rockchip: Change pwm pinctrl-name to "default" on rk356x The pinctrl state "active" is neither documented nor used by the PWM driver. Rename it to "default" Signed-off-by: Sascha Hauer Link: https://lore.kernel.org/r/20211208120312.3300390-1-s.hauer@pengutronix.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) (limited to 'arch/arm64/boot/dts/rockchip') diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 46d9552f6028..29e8516ef0cb 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -269,7 +269,7 @@ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm0m0_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -280,7 +280,7 @@ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm1m0_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -291,7 +291,7 @@ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm2m0_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -302,7 +302,7 @@ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm3_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -951,7 +951,7 @@ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm4_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -962,7 +962,7 @@ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm5_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -973,7 +973,7 @@ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm6_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -984,7 +984,7 @@ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm7_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -995,7 +995,7 @@ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm8m0_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -1006,7 +1006,7 @@ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm9m0_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -1017,7 +1017,7 @@ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm10m0_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -1028,7 +1028,7 @@ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm11m0_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -1039,7 +1039,7 @@ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm12m0_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -1050,7 +1050,7 @@ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm13m0_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -1061,7 +1061,7 @@ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm14m0_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -1072,7 +1072,7 @@ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm15m0_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; -- cgit From aaa552d84580e9213d0e2bf0f9243477d1227bdd Mon Sep 17 00:00:00 2001 From: Nicolas Frattaroli Date: Sat, 27 Nov 2021 15:19:08 +0100 Subject: arm64: dts: rockchip: Add spi nodes on rk356x This adds the four spi nodes (spi0, spi1, spi2, spi3) to the rk356x dtsi. These are from the downstream device tree, though I have double-checked that their interrupts and DMA numbers are correct. I have also tested spi1 with an SPI device. Signed-off-by: Nicolas Frattaroli Link: https://lore.kernel.org/r/20211127141910.12649-3-frattaroli.nicolas@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 64 ++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) (limited to 'arch/arm64/boot/dts/rockchip') diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 29e8516ef0cb..a68033a23975 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -39,6 +39,10 @@ serial7 = &uart7; serial8 = &uart8; serial9 = &uart9; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; }; cpus { @@ -742,6 +746,66 @@ clock-names = "tclk", "pclk"; }; + spi0: spi@fe610000 { + compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfe610000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 20>, <&dmac0 21>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@fe620000 { + compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfe620000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 22>, <&dmac0 23>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@fe630000 { + compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfe630000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 24>, <&dmac0 25>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@fe640000 { + compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfe640000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 26>, <&dmac0 27>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + uart1: serial@fe650000 { compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; reg = <0x0 0xfe650000 0x0 0x100>; -- cgit From ea1847c09c34234c2980b99b6bb732a55447c33f Mon Sep 17 00:00:00 2001 From: Nicolas Frattaroli Date: Sat, 27 Nov 2021 15:19:09 +0100 Subject: arm64: dts: rockchip: Add spi1 pins on Quartz64 A The Quartz64 Model A has the SPI pins broken out on its pin header. The actual pins being used though are not the m0 variant, but the m1 variant, which also lacks the cs1 pin. This commit overrides pinctrl-0 accordingly for this board. spi1 is intentionally left disabled, as anyone wishing to add SPI devices needs to edit the dts anyway, and the pins are more useful as GPIOs for the rest of the users. Signed-off-by: Nicolas Frattaroli Link: https://lore.kernel.org/r/20211127141910.12649-4-frattaroli.nicolas@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm64/boot/dts/rockchip') diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts index 4d4b2a301b1a..166399b7f13f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts @@ -509,6 +509,11 @@ status = "okay"; }; +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>; +}; + &tsadc { /* tshut mode 0:CRU 1:GPIO */ rockchip,hw-tshut-mode = <1>; -- cgit From a39891a6e420daeb55abc99cde4278511ac861d7 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Sun, 12 Dec 2021 00:38:17 +0100 Subject: arm64: dts: rockchip: Add missing secondary compatible for PX30 DSI Add second DSI compatible to comply with DT schema validation comming in the second patch. Signed-off-by: David Heidelberg Link: https://lore.kernel.org/r/20211211233818.88482-1-david@ixit.cz Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/px30.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts/rockchip') diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index 00f50b05d55a..f972704dfe7a 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -1072,7 +1072,7 @@ }; dsi: dsi@ff450000 { - compatible = "rockchip,px30-mipi-dsi"; + compatible = "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi"; reg = <0x0 0xff450000 0x0 0x10000>; interrupts = ; clocks = <&cru PCLK_MIPI_DSI>; -- cgit From f471b1b2db0819917c54099ab68349ad6a7e9e19 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 12 Nov 2021 19:53:59 +0530 Subject: arm64: dts: rockchip: Fix Bluetooth on ROCK Pi 4 boards This patch fixes the Bluetooth on ROCK Pi 4 boards. ROCK Pi 4 boards has BCM4345C5 and now it is supported on Mainline Linux, brcm,bcm43438-bt still working but observed the BT Audio issues with latest test. So, use the BCM4345C5 compatible and its associated properties like clock-names as lpo and max-speed. Attach vbat and vddio supply rails as well. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20211112142359.320798-1-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts | 7 +++++-- arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts | 7 +++++-- arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts | 7 +++++-- 3 files changed, 15 insertions(+), 6 deletions(-) (limited to 'arch/arm64/boot/dts/rockchip') diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts index 81bea953c891..cec3b7b1b947 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts @@ -46,13 +46,16 @@ status = "okay"; bluetooth { - compatible = "brcm,bcm43438-bt"; + compatible = "brcm,bcm4345c5"; clocks = <&rk808 1>; - clock-names = "ext_clock"; + clock-names = "lpo"; device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + max-speed = <1500000>; pinctrl-names = "default"; pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts index 6c63e617063c..cf48746a3ad8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts @@ -34,13 +34,16 @@ status = "okay"; bluetooth { - compatible = "brcm,bcm43438-bt"; + compatible = "brcm,bcm4345c5"; clocks = <&rk808 1>; - clock-names = "ext_clock"; + clock-names = "lpo"; device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + max-speed = <1500000>; pinctrl-names = "default"; pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts index 0ad7b6e22f70..793d84833921 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts @@ -46,14 +46,17 @@ status = "okay"; bluetooth { - compatible = "brcm,bcm43438-bt"; + compatible = "brcm,bcm4345c5"; clocks = <&rk808 1>; - clock-names = "ext_clock"; + clock-names = "lpo"; device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + max-speed = <1500000>; pinctrl-names = "default"; pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; }; }; -- cgit