From 995504b6fa47005d20104f20922e65e4ad8d3e50 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Thu, 23 Jul 2020 16:11:37 -0500 Subject: arm64: dts: ti: k3-j721e: Fix interconnect node names The various CBASS interconnect nodes on K3 J721E SoCs are defined using the node name "interconnect". This is not a valid node name as per the dt-schema. Fix these node names to use the standard name used for SoC interconnects, "bus". Signed-off-by: Suman Anna Signed-off-by: Nishanth Menon Reviewed-by: Lokesh Vutla Link: https://lore.kernel.org/r/20200723211137.26641-3-s-anna@ti.com --- arch/arm64/boot/dts/ti/k3-j721e.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts/ti/k3-j721e.dtsi') diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi index d035b61e0e16..f787aa73aaae 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -120,7 +120,7 @@ interrupts = ; }; - cbass_main: interconnect@100000 { + cbass_main: bus@100000 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; @@ -155,7 +155,7 @@ <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; - cbass_mcu_wakeup: interconnect@28380000 { + cbass_mcu_wakeup: bus@28380000 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; -- cgit From 1aedefe13ba263d0d7d1cfbb38aadebbd5bab34e Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 3 Sep 2020 08:00:08 -0500 Subject: arm64: dts: ti: k3-j721e: Use lower case hexadecimal Device tree convention uses lower case a-f for hexadecimals. Fix the same. Signed-off-by: Nishanth Menon Reviewed-by: Lokesh Vutla Acked-by: Suman Anna Link: https://lore.kernel.org/r/20200903130015.21361-2-nm@ti.com --- arch/arm64/boot/dts/ti/k3-j721e.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts/ti/k3-j721e.dtsi') diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi index f787aa73aaae..1bb8235d9ffb 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -127,7 +127,7 @@ ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ - <0x00 0x00A40000 0x00 0x00A40000 0x00 0x00000800>, /* timesync router */ + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */ <0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */ <0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */ <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ -- cgit From 4e5833884f6656042eb100e9bcd68072e3338b25 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Mon, 14 Sep 2020 20:51:14 +0530 Subject: arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes Add PCIe device tree nodes (both RC and EP) for the four PCIe instances here. Also add the missing translations required in the "ranges" DT property of cbass_main to access all the four PCIe instances. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20200914152115.1788-2-kishon@ti.com --- arch/arm64/boot/dts/ti/k3-j721e.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts/ti/k3-j721e.dtsi') diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi index 1bb8235d9ffb..cc483f7344af 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -132,9 +132,12 @@ <0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */ <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ - <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/ + <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01800000>, /* PCIe Core*/ + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/ <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */ <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */ + <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */ + <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */ <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */ <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */ <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */ -- cgit