From 69f8aec4f900dc8af6e38957beefcd3b763bfb5a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 14 Jun 2021 17:25:20 +0200 Subject: arm64: zynqmp: Add missing mio-bank properties to dc1 and dc5 Add missing mio-bank properties to zc1751 dc1 and dc5 boards. The same change was done by commit 63481699d6e3 ("arm64: dts: zynqmp: Add missing mio-bank properties to sdhcis"). Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/2b2ab31639c706651dfd319f5b6bc59e68f111b6.1623684253.git.michal.simek@xilinx.com --- arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts') diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts index f57cb5356cef..dd129347174a 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts @@ -364,6 +364,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; bus-width = <8>; + xlnx,mio-bank = <0>; }; /* SD1 with level shifter */ @@ -371,6 +372,7 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; + xlnx,mio-bank = <1>; }; &uart0 { -- cgit