From 929dcf7dce56ea03795b7293975687d252c29215 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 22 Aug 2023 02:50:07 +0200 Subject: arm64: dts: imx8mp: Switch PCIe to HSIO PLL on i.MX8MP DHCOM PDK2 and generate clock from SoC The PDK2 carrier board had to be manually patched to obtain working PCIe with the i.MX8MP DHCOM SoM so far, because the PCIe clock generator has not been connected to the PCIe block REF_PAD_CLK inputs. Switch to use of HSIO PLL as the clock source for the PCIe block instead, and use the REF_PAD_CLK as outputs to generate PCIe clock from the SoC. This way, it is not necessary to patch the PDK2 in any way to obtain a working PCIe. Note that PDK3 has PCIe clock generator always connected to REF_PAD_CLK and is not affected. Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts index e9fb5f7f39b5..3b1c940860e0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts @@ -186,9 +186,9 @@ &pcie_phy { clock-names = "ref"; - clocks = <&clk IMX8MP_SYS_PLL2_100M>; + clocks = <&hsio_blk_ctrl>; fsl,clkreq-unsupported; - fsl,refclk-pad-mode = ; + fsl,refclk-pad-mode = ; status = "okay"; }; -- cgit