From e4e06a50b04296d17a4cf098a515fb452106ecf0 Mon Sep 17 00:00:00 2001 From: Lars Povlsen Date: Mon, 15 Jun 2020 15:32:41 +0200 Subject: arm64: dts: sparx5: Add Sparx5 SoC DPLL clock This adds a DPLL clock to the Sparx5 SoC. It is used to generate clock to misc peripherals, specifically the SDHCI/eMMC controller. Link: https://lore.kernel.org/r/20200615133242.24911-10-lars.povlsen@microchip.com Signed-off-by: Lars Povlsen Signed-off-by: Arnd Bergmann --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 39 ++++++++++++++++++------------- 1 file changed, 23 insertions(+), 16 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index baf4176ce1df..161846caf9c9 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -72,20 +72,29 @@ ; }; - clocks: clocks { - #address-cells = <2>; - #size-cells = <1>; - ranges; - ahb_clk: ahb-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <250000000>; - }; - sys_clk: sys-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <625000000>; - }; + lcpll_clk: lcpll-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <2500000000>; + }; + + clks: clock-controller@61110000c { + compatible = "microchip,sparx5-dpll"; + #clock-cells = <1>; + clocks = <&lcpll_clk>; + reg = <0x6 0x1110000c 0x24>; + }; + + ahb_clk: ahb-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; + }; + + sys_clk: sys-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <625000000>; }; axi: axi@600000000 { @@ -161,8 +170,6 @@ pins = "GPIO_26", "GPIO_27"; function = "uart2"; }; - }; - }; }; -- cgit