From 86f2159468d55aca1793c1f0f3d95213501b32f3 Mon Sep 17 00:00:00 2001 From: Artem Lapkin Date: Wed, 15 Dec 2021 11:02:36 +0800 Subject: arm64: dts: meson-sm1: add spdifin and pdifout nodes Add spdifin spdifout nodes for Amlogic SM1 SoCs. Signed-off-by: Artem Lapkin Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong [narmstrong: subject and DT fixups from mailing-list review] Link: https://lore.kernel.org/r/20211215030236.340841-1-art@khadas.com --- arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi index 3d8b1f4f2001..3c07a89bfd27 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi @@ -356,6 +356,33 @@ status = "disabled"; }; + spdifin: audio-controller@400 { + compatible = "amlogic,g12a-spdifin", + "amlogic,axg-spdifin"; + reg = <0x0 0x400 0x0 0x30>; + #sound-dai-cells = <0>; + sound-name-prefix = "SPDIFIN"; + interrupts = ; + clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, + <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; + clock-names = "pclk", "refclk"; + resets = <&clkc_audio AUD_RESET_SPDIFIN>; + status = "disabled"; + }; + + spdifout_a: audio-controller@480 { + compatible = "amlogic,g12a-spdifout", + "amlogic,axg-spdifout"; + reg = <0x0 0x480 0x0 0x50>; + #sound-dai-cells = <0>; + sound-name-prefix = "SPDIFOUT_A"; + clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, + <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; + clock-names = "pclk", "mclk"; + resets = <&clkc_audio AUD_RESET_SPDIFOUT>; + status = "disabled"; + }; + tdmout_a: audio-controller@500 { compatible = "amlogic,sm1-tdmout"; reg = <0x0 0x500 0x0 0x40>; -- cgit From b5a03ecec30c1a71d51de3e73a2e7ab23c3ddeb6 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Wed, 12 Jan 2022 02:27:05 +0000 Subject: arm64: dts: meson: add common SM1 ac2xx dtsi Add a common dtsi for Android STB devices based on the Amlogic S905X3 (AC213/AC214) and S905D3 (AC201/AC202) reference designs. The dtsi is loosely based on the existing SEI610 device-tree. Signed-off-by: Christian Hewitt Tested-by: Martin Blumenstingl # X96-Air with Gbit PHY Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220112022713.25962-2-christianshewitt@gmail.com --- arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi | 300 +++++++++++++++++++++++ 1 file changed, 300 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi new file mode 100644 index 000000000000..46a34731f7e2 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi @@ -0,0 +1,300 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre SAS. All rights reserved. + * Copyright (c) 2020 Christian Hewitt + * + * AC200/AC202 = S905D3 + * AC213/AC214 = S905X3 + * + */ + +#include "meson-sm1.dtsi" +#include +#include +#include + +/ { + aliases { + serial0 = &uart_AO; + ethernet0 = ðmac; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; + }; + + cvbs-connector { + compatible = "composite-video-connector"; + + port { + cvbs_connector_in: endpoint { + remote-endpoint = <&cvbs_vdac_out>; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_tmds_out>; + }; + }; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; + + ao_5v: regulator-ao_5v { + compatible = "regulator-fixed"; + regulator-name = "AO_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_in>; + regulator-always-on; + }; + + dc_in: regulator-dc_in { + compatible = "regulator-fixed"; + regulator-name = "DC_IN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + emmc_1v8: regulator-emmc_1v8 { + compatible = "regulator-fixed"; + regulator-name = "EMMC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_in>; + regulator-always-on; + }; + + vddcpu: regulator-vddcpu { + compatible = "pwm-regulator"; + + regulator-name = "VDDCPU"; + regulator-min-microvolt = <690000>; + regulator-max-microvolt = <1050000>; + + vin-supply = <&dc_in>; + + pwms = <&pwm_AO_cd 1 1500 0>; + pwm-dutycycle-range = <100 0>; + + regulator-boot-on; + regulator-always-on; + }; + + vddio_ao1v8: regulator-vddio_ao1v8 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; +}; + +&cec_AO { + pinctrl-0 = <&cec_ao_a_h_pins>; + pinctrl-names = "default"; + status = "disabled"; + hdmi-phandle = <&hdmi_tx>; +}; + +&cecb_AO { + pinctrl-0 = <&cec_ao_b_h_pins>; + pinctrl-names = "default"; + status = "okay"; + hdmi-phandle = <&hdmi_tx>; +}; + +&cpu0 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu1 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU1_CLK>; + clock-latency = <50000>; +}; + +&cpu2 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU2_CLK>; + clock-latency = <50000>; +}; + +&cpu3 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU3_CLK>; + clock-latency = <50000>; +}; + +&cvbs_vdac_port { + cvbs_vdac_out: endpoint { + remote-endpoint = <&cvbs_connector_in>; + }; +}; + +&hdmi_tx { + status = "okay"; + pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; + pinctrl-names = "default"; +}; + +&hdmi_tx_tmds_port { + hdmi_tx_tmds_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; + +&pwm_AO_ab { + status = "okay"; + pinctrl-0 = <&pwm_ao_a_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin0"; +}; + +&pwm_AO_cd { + pinctrl-0 = <&pwm_ao_d_e_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin1"; + status = "okay"; +}; + +&pwm_ef { + status = "okay"; + pinctrl-0 = <&pwm_e_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin0"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao1v8>; +}; + +/* SDIO */ +&sd_emmc_a { + status = "okay"; + pinctrl-0 = <&sdio_pins>; + pinctrl-1 = <&sdio_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + sd-uhs-sdr104; + max-frequency = <200000000>; + + non-removable; + disable-wp; + + /* WiFi firmware requires power to be kept while in suspend */ + keep-power-in-suspend; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_ao1v8>; +}; + +/* SD Card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_c_pins>; + pinctrl-1 = <&sdcard_clk_gate_c_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <4>; + cap-sd-highspeed; + /* CRC errors are observed at 50MHz */ + max-frequency = <35000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddao_3v3>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&emmc_1v8>; +}; + +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +&usb { + status = "okay"; + dr_mode = "otg"; +}; -- cgit From 37875d9dcb42d489ba28518b50fed0b2ba768b03 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Wed, 12 Jan 2022 02:27:07 +0000 Subject: arm64: dts: meson: add initial device-trees for X96-AIR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Amediatek X96-AIR is based on Amlogic S905X3 reference board designs and ships in multiple configurations: – 4GB DDR3 + 64GB eMMC + WiFi a/b/g/n/ac + BT + Gb Ethernet – 4GB DDR3 + 32GB eMMC + WiFi a/b/g/n/ac + BT + Gb Ethernet – 4GB DDR3 + 32GB eMMC + WiFi b/g/n (no BT) + 10/100 Ethernet – 2GB DDR3 + 16GB eMMC + WiFi b/g/n (no BT) + 10/100 Ethernet ... - HDMI 2.1 video - S/PDIF optical output - AV output - 2x USB 2.0 inc. OTG port - 1x USB 3.0 port - IR receiver - 1x micro SD card slot (internal) - 1x Reset/Update button (in AV jack) - 7-segment VFD The device-tree with -gbit suffix supports models with Gigabit Ethernet, and the device-tree with no suffix supports models with 10/100 Ethernet. Signed-off-by: Christian Hewitt Tested-by: Martin Blumenstingl # X96-Air with Gbit PHY Tested-by: Piotr Oniszczuk # X96-Air with 10/100 Eth Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220112022713.25962-4-christianshewitt@gmail.com --- arch/arm64/boot/dts/amlogic/Makefile | 2 + .../boot/dts/amlogic/meson-sm1-x96-air-gbit.dts | 133 +++++++++++++++++++++ arch/arm64/boot/dts/amlogic/meson-sm1-x96-air.dts | 112 +++++++++++++++++ 3 files changed, 247 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/meson-sm1-x96-air-gbit.dts create mode 100644 arch/arm64/boot/dts/amlogic/meson-sm1-x96-air.dts (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index 5148cd9e5146..1c0e554f54fc 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -56,4 +56,6 @@ dtb-$(CONFIG_ARCH_MESON) += meson-sm1-khadas-vim3l.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-c4.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-hc4.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-sei610.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x96-air.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x96-air-gbit.dtb dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air-gbit.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air-gbit.dts new file mode 100644 index 000000000000..7e1a74046ba5 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air-gbit.dts @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre SAS. All rights reserved. + * Copyright (c) 2020 Christian Hewitt + */ + +/dts-v1/; + +#include "meson-sm1-ac2xx.dtsi" +#include + +/ { + compatible = "amediatech,x96-air-gbit", "amlogic,sm1"; + model = "Shenzhen Amediatech Technology Co., Ltd X96 Air"; + + sound { + compatible = "amlogic,axg-sound-card"; + model = "X96-AIR"; + audio-aux-devs = <&tdmout_b>; + audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", + "TDMOUT_B IN 1", "FRDDR_B OUT 1", + "TDMOUT_B IN 2", "FRDDR_C OUT 1", + "TDM_B Playback", "TDMOUT_B OUT"; + + assigned-clocks = <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&frddr_a>; + }; + + dai-link-1 { + sound-dai = <&frddr_b>; + }; + + dai-link-2 { + sound-dai = <&frddr_c>; + }; + + /* 8ch hdmi interface */ + dai-link-3 { + sound-dai = <&tdmif_b>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-0 = <1 1>; + dai-tdm-slot-tx-mask-1 = <1 1>; + dai-tdm-slot-tx-mask-2 = <1 1>; + dai-tdm-slot-tx-mask-3 = <1 1>; + mclk-fs = <256>; + + codec { + sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; + }; + }; + + /* hdmi glue */ + dai-link-4 { + sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; + + codec { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&arb { + status = "okay"; +}; + +&clkc_audio { + status = "okay"; +}; + +ðmac { + status = "okay"; + + pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; + pinctrl-names = "default"; + phy-mode = "rgmii-txid"; + phy-handle = <&external_phy>; + + rx-internal-delay-ps = <800>; +}; + +&ext_mdio { + external_phy: ethernet-phy@0 { + /* Realtek RTL8211F (0x001cc916) */ + reg = <0>; + max-speed = <1000>; + + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + + interrupt-parent = <&gpio_intc>; + /* MAC_INTR on GPIOZ_14 */ + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&frddr_a { + status = "okay"; +}; + +&frddr_b { + status = "okay"; +}; + +&frddr_c { + status = "okay"; +}; + +&ir { + linux,rc-map-name = "rc-x96max"; +}; + +&tdmif_b { + status = "okay"; +}; + +&tdmout_b { + status = "okay"; +}; + +&tohdmitx { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air.dts new file mode 100644 index 000000000000..cd93d798f2a3 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air.dts @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre SAS. All rights reserved. + * Copyright (c) 2020 Christian Hewitt + */ + +/dts-v1/; + +#include "meson-sm1-ac2xx.dtsi" +#include + +/ { + compatible = "amediatech,x96-air", "amlogic,sm1"; + model = "Shenzhen Amediatech Technology Co., Ltd X96 Air"; + + sound { + compatible = "amlogic,axg-sound-card"; + model = "X96-AIR"; + audio-aux-devs = <&tdmout_b>; + audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", + "TDMOUT_B IN 1", "FRDDR_B OUT 1", + "TDMOUT_B IN 2", "FRDDR_C OUT 1", + "TDM_B Playback", "TDMOUT_B OUT"; + + assigned-clocks = <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&frddr_a>; + }; + + dai-link-1 { + sound-dai = <&frddr_b>; + }; + + dai-link-2 { + sound-dai = <&frddr_c>; + }; + + /* 8ch hdmi interface */ + dai-link-3 { + sound-dai = <&tdmif_b>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-0 = <1 1>; + dai-tdm-slot-tx-mask-1 = <1 1>; + dai-tdm-slot-tx-mask-2 = <1 1>; + dai-tdm-slot-tx-mask-3 = <1 1>; + mclk-fs = <256>; + + codec { + sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; + }; + }; + + /* hdmi glue */ + dai-link-4 { + sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; + + codec { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&arb { + status = "okay"; +}; + +&clkc_audio { + status = "okay"; +}; + +ðmac { + status = "okay"; + phy-handle = <&internal_ephy>; + phy-mode = "rmii"; +}; + +&frddr_a { + status = "okay"; +}; + +&frddr_b { + status = "okay"; +}; + +&frddr_c { + status = "okay"; +}; + +&ir { + linux,rc-map-name = "rc-beelink-gs1"; +}; + +&tdmif_b { + status = "okay"; +}; + +&tdmout_b { + status = "okay"; +}; + +&tohdmitx { + status = "okay"; +}; -- cgit From 8b749a0205bd41cafae37e878fd4a1b57b7b24f3 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Wed, 12 Jan 2022 02:27:10 +0000 Subject: arm64: dts: meson: add initial device-trees for A95XF3-AIR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The CYX A95XF3-AIR is based on Amlogic S905X3 reference board designs and ships in multiple configurations: – 4GB DDR3 + 64GB eMMC + WiFi a/b/g/n/ac + BT + Gb Ethernet – 4GB DDR3 + 32GB eMMC + WiFi a/b/g/n/ac + BT + Gb Ethernet – 2GB DDR3 + 16GB eMMC + WiFi b/g/n (no BT) + 10/100 Ethernet ... - HDMI 2.1 video - S/PDIF optical output - AV output - 1x USB 2.0 OTG port - 1x USB 3.0 port - IR receiver - 1x micro SD card slot (internal) - 1x Reset/Update button (in AV jack) - 7-segment VFD - Multicolour case LED 'arc' The device-tree with -gbit suffix supports models with Gigabit Ethernet, and the device-tree with no suffix supports models with 10/100 Ethernet. Signed-off-by: Christian Hewitt Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220112022713.25962-7-christianshewitt@gmail.com --- arch/arm64/boot/dts/amlogic/Makefile | 2 + .../boot/dts/amlogic/meson-sm1-a95xf3-air-gbit.dts | 129 +++++++++++++++++++++ .../boot/dts/amlogic/meson-sm1-a95xf3-air.dts | 108 +++++++++++++++++ 3 files changed, 239 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air-gbit.dts create mode 100644 arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air.dts (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index 1c0e554f54fc..e87adc6593df 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -51,6 +51,8 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxm-rbox-pro.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-libretech-pc.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-vega-s96.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-wetek-core2.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-sm1-a95xf3-air.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-sm1-a95xf3-air-gbit.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-bananapi-m5.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-khadas-vim3l.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-c4.dtb diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air-gbit.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air-gbit.dts new file mode 100644 index 000000000000..d1debccdc1c2 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air-gbit.dts @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre SAS. All rights reserved. + * Copyright (c) 2020 Christian Hewitt + */ + +/dts-v1/; + +#include "meson-sm1-ac2xx.dtsi" +#include + +/ { + compatible = "cyx,a95xf3-air-gbit", "amlogic,sm1"; + model = "Shenzhen CYX Industrial Co., Ltd A95XF3-AIR"; + + sound { + compatible = "amlogic,axg-sound-card"; + model = "A95XF3-AIR"; + audio-aux-devs = <&tdmout_b>; + audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", + "TDMOUT_B IN 1", "FRDDR_B OUT 1", + "TDMOUT_B IN 2", "FRDDR_C OUT 1", + "TDM_B Playback", "TDMOUT_B OUT"; + + assigned-clocks = <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&frddr_a>; + }; + + dai-link-1 { + sound-dai = <&frddr_b>; + }; + + dai-link-2 { + sound-dai = <&frddr_c>; + }; + + /* 8ch hdmi interface */ + dai-link-3 { + sound-dai = <&tdmif_b>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-0 = <1 1>; + dai-tdm-slot-tx-mask-1 = <1 1>; + dai-tdm-slot-tx-mask-2 = <1 1>; + dai-tdm-slot-tx-mask-3 = <1 1>; + mclk-fs = <256>; + + codec { + sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; + }; + }; + + /* hdmi glue */ + dai-link-4 { + sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; + + codec { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&arb { + status = "okay"; +}; + +&clkc_audio { + status = "okay"; +}; + +ðmac { + status = "okay"; + + pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; + pinctrl-names = "default"; + phy-mode = "rgmii-txid"; + phy-handle = <&external_phy>; + + rx-internal-delay-ps = <800>; +}; + +&ext_mdio { + external_phy: ethernet-phy@0 { + /* Realtek RTL8211F (0x001cc916) */ + reg = <0>; + max-speed = <1000>; + + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + + interrupt-parent = <&gpio_intc>; + /* MAC_INTR on GPIOZ_14 */ + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&frddr_a { + status = "okay"; +}; + +&frddr_b { + status = "okay"; +}; + +&frddr_c { + status = "okay"; +}; + +&tdmif_b { + status = "okay"; +}; + +&tdmout_b { + status = "okay"; +}; + +&tohdmitx { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air.dts new file mode 100644 index 000000000000..c94f2870b78b --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air.dts @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre SAS. All rights reserved. + * Copyright (c) 2020 Christian Hewitt + */ + +/dts-v1/; + +#include "meson-sm1-ac2xx.dtsi" +#include + +/ { + compatible = "cyx,a95xf3-air", "amlogic,sm1"; + model = "Shenzhen CYX Industrial Co., Ltd A95XF3-AIR"; + + sound { + compatible = "amlogic,axg-sound-card"; + model = "A95XF3-AIR"; + audio-aux-devs = <&tdmout_b>; + audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", + "TDMOUT_B IN 1", "FRDDR_B OUT 1", + "TDMOUT_B IN 2", "FRDDR_C OUT 1", + "TDM_B Playback", "TDMOUT_B OUT"; + + assigned-clocks = <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&frddr_a>; + }; + + dai-link-1 { + sound-dai = <&frddr_b>; + }; + + dai-link-2 { + sound-dai = <&frddr_c>; + }; + + /* 8ch hdmi interface */ + dai-link-3 { + sound-dai = <&tdmif_b>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-0 = <1 1>; + dai-tdm-slot-tx-mask-1 = <1 1>; + dai-tdm-slot-tx-mask-2 = <1 1>; + dai-tdm-slot-tx-mask-3 = <1 1>; + mclk-fs = <256>; + + codec { + sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; + }; + }; + + /* hdmi glue */ + dai-link-4 { + sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; + + codec { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&arb { + status = "okay"; +}; + +&clkc_audio { + status = "okay"; +}; + +ðmac { + status = "okay"; + phy-handle = <&internal_ephy>; + phy-mode = "rmii"; +}; + +&frddr_a { + status = "okay"; +}; + +&frddr_b { + status = "okay"; +}; + +&frddr_c { + status = "okay"; +}; + +&tdmif_b { + status = "okay"; +}; + +&tdmout_b { + status = "okay"; +}; + +&tohdmitx { + status = "okay"; +}; -- cgit From ac7b4433714a37e2c4b61acc6ce9b4538175e836 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Wed, 12 Jan 2022 02:27:13 +0000 Subject: arm64: dts: meson: add initial device-tree for H96-Max The Haochuangyi H96-Max is based on the Amlogic S905X3 reference design with the following specs: - 4GB DDR4 RAM - 32/64/128GB eMMC - HDMI 2.1 video - S/PDIF optical output - AV output - 10/100/1000 Base-T Ethernet - AP6356S Wireless (802.11 a/b/g/n/ac, BT 4.1) - 1x USB 2.0 OTG port - 1x USB 3.0 port - IR receiver - 1x micro SD card slot (internal) - 1x Reset/Update button (in AV jack) - 7-segment VFD Signed-off-by: Christian Hewitt Tested-by: Benoit Masson Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220112022713.25962-10-christianshewitt@gmail.com --- arch/arm64/boot/dts/amlogic/Makefile | 1 + arch/arm64/boot/dts/amlogic/meson-sm1-h96-max.dts | 145 ++++++++++++++++++++++ 2 files changed, 146 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/meson-sm1-h96-max.dts (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index e87adc6593df..868d74044072 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -54,6 +54,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxm-wetek-core2.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-a95xf3-air.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-a95xf3-air-gbit.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-bananapi-m5.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-sm1-h96-max.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-khadas-vim3l.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-c4.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-hc4.dtb diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-h96-max.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-h96-max.dts new file mode 100644 index 000000000000..0f6660e68e72 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-h96-max.dts @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre SAS. All rights reserved. + * Copyright (c) 2020 Christian Hewitt + */ + +/dts-v1/; + +#include "meson-sm1-ac2xx.dtsi" +#include + +/ { + compatible = "haochuangyi,h96-max", "amlogic,sm1"; + model = "Shenzhen Haochuangyi Technology Co., Ltd H96 Max"; + + sound { + compatible = "amlogic,axg-sound-card"; + model = "H96-MAX"; + audio-aux-devs = <&tdmout_b>; + audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", + "TDMOUT_B IN 1", "FRDDR_B OUT 1", + "TDMOUT_B IN 2", "FRDDR_C OUT 1", + "TDM_B Playback", "TDMOUT_B OUT"; + + assigned-clocks = <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&frddr_a>; + }; + + dai-link-1 { + sound-dai = <&frddr_b>; + }; + + dai-link-2 { + sound-dai = <&frddr_c>; + }; + + /* 8ch hdmi interface */ + dai-link-3 { + sound-dai = <&tdmif_b>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-0 = <1 1>; + dai-tdm-slot-tx-mask-1 = <1 1>; + dai-tdm-slot-tx-mask-2 = <1 1>; + dai-tdm-slot-tx-mask-3 = <1 1>; + mclk-fs = <256>; + + codec { + sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; + }; + }; + + /* hdmi glue */ + dai-link-4 { + sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; + + codec { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&arb { + status = "okay"; +}; + +&clkc_audio { + status = "okay"; +}; + +ðmac { + status = "okay"; + + pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; + pinctrl-names = "default"; + phy-mode = "rgmii-txid"; + phy-handle = <&external_phy>; + + rx-internal-delay-ps = <800>; +}; + +&ext_mdio { + external_phy: ethernet-phy@0 { + /* Realtek RTL8211F (0x001cc916) */ + reg = <0>; + max-speed = <1000>; + + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + + interrupt-parent = <&gpio_intc>; + /* MAC_INTR on GPIOZ_14 */ + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&frddr_a { + status = "okay"; +}; + +&frddr_b { + status = "okay"; +}; + +&frddr_c { + status = "okay"; +}; + +&tdmif_b { + status = "okay"; +}; + +&tdmout_b { + status = "okay"; +}; + +&tohdmitx { + status = "okay"; +}; + +&uart_A { + status = "okay"; + + pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + max-speed = <2000000>; + clocks = <&wifi32k>; + clock-names = "lpo"; + }; +}; -- cgit From ac4dfd0d1d350412c7e4958821a5d7e47edc5a73 Mon Sep 17 00:00:00 2001 From: Xianwei Zhao Date: Thu, 6 Jan 2022 19:22:14 +0800 Subject: arm64: dts: add support for S4 based Amlogic AQ222 Add basic support for the Amlogic S4 based Amlogic AQ222 board: which describe components as follows: CPU, GIC, IRQ, Timer, UART. It's capable of booting up into the serial console. Signed-off-by: Xianwei Zhao Signed-off-by: Neil Armstrong [narmstrong: fixed memory unit address warning] Link: https://lore.kernel.org/r/20220106112214.6987-1-xianwei.zhao@amlogic.com --- arch/arm64/boot/dts/amlogic/Makefile | 1 + .../boot/dts/amlogic/meson-s4-s805x2-aq222.dts | 30 +++++++ arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 99 ++++++++++++++++++++++ 3 files changed, 130 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts create mode 100644 arch/arm64/boot/dts/amlogic/meson-s4.dtsi (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index 868d74044072..13f73ca700ef 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -62,3 +62,4 @@ dtb-$(CONFIG_ARCH_MESON) += meson-sm1-sei610.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x96-air.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x96-air-gbit.dtb dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-s4-s805x2-aq222.dtb diff --git a/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts b/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts new file mode 100644 index 000000000000..8ffbcb2b1ac5 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "meson-s4.dtsi" + +/ { + model = "Amlogic Meson S4 AQ222 Development Board"; + compatible = "amlogic,aq222", "amlogic,s4"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart_B; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; + +}; + +&uart_B { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi new file mode 100644 index 000000000000..bf9ae1e1016b --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. + */ + +#include +#include + +/ { + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35","arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35","arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a35","arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a35","arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@fff01000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xfff01000 0 0x1000>, + <0x0 0xfff02000 0 0x2000>, + <0x0 0xfff04000 0 0x2000>, + <0x0 0xfff06000 0 0x2000>; + interrupts = ; + }; + + apb4: apb4@fe000000 { + compatible = "simple-bus"; + reg = <0x0 0xfe000000 0x0 0x480000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; + + uart_B: serial@7a000 { + compatible = "amlogic,meson-s4-uart", + "amlogic,meson-ao-uart"; + reg = <0x0 0x7a000 0x0 0x18>; + interrupts = ; + status = "disabled"; + clocks = <&xtal>, <&xtal>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + }; + }; + }; +}; -- cgit From 073983233302641d080b524640cc99be696e802a Mon Sep 17 00:00:00 2001 From: Gary Bisson Date: Wed, 12 Jan 2022 22:16:41 +0100 Subject: arm64: dts: meson-g12-common: add more pwm_f options Add missing PWM_F pin muxing for GPIOA_11 and GPIOZ_12. Signed-off-by: Gary Bisson Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220112211642.2248901-3-gary.bisson@boundarydevices.com --- arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi index 517519e6e87f..c20b86923887 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi @@ -839,6 +839,22 @@ }; }; + pwm_f_z_pins: pwm-f-z { + mux { + groups = "pwm_f_z"; + function = "pwm_f"; + bias-disable; + }; + }; + + pwm_f_a_pins: pwm-f-a { + mux { + groups = "pwm_f_a"; + function = "pwm_f"; + bias-disable; + }; + }; + pwm_f_x_pins: pwm-f-x { mux { groups = "pwm_f_x"; -- cgit From 2c420d79dae47f9fa3bb8ccb76eaba864c579721 Mon Sep 17 00:00:00 2001 From: Gary Bisson Date: Wed, 12 Jan 2022 22:16:42 +0100 Subject: arm64: dts: meson-g12-common: add uart_ao_b pins muxing - RX/TX signals can be mapped on 2 different pairs of pins so supporting both options - RTS/CTS signals however only have 1 option available Signed-off-by: Gary Bisson Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220112211642.2248901-4-gary.bisson@boundarydevices.com --- arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 27 +++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi index c20b86923887..6d99c23261fb 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi @@ -1897,6 +1897,33 @@ }; }; + uart_ao_b_2_3_pins: uart-ao-b-2-3 { + mux { + groups = "uart_ao_b_tx_2", + "uart_ao_b_rx_3"; + function = "uart_ao_b"; + bias-disable; + }; + }; + + uart_ao_b_8_9_pins: uart-ao-b-8-9 { + mux { + groups = "uart_ao_b_tx_8", + "uart_ao_b_rx_9"; + function = "uart_ao_b"; + bias-disable; + }; + }; + + uart_ao_b_cts_rts_pins: uart-ao-b-cts-rts { + mux { + groups = "uart_ao_b_cts", + "uart_ao_b_rts"; + function = "uart_ao_b"; + bias-disable; + }; + }; + pwm_a_e_pins: pwm-a-e { mux { groups = "pwm_a_e"; -- cgit From 91c4c3e06a256c980235116b764b350ced811720 Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Wed, 15 Dec 2021 16:02:51 -0500 Subject: arm64: dts: rockchip: add usb2 nodes to rk3568 device tree Add the requisite nodes to the rk3568 device tree to enable the usb2 device controllers. Includes the usb2phy nodes, usb2phy grf nodes, and usb2 controller nodes. Signed-off-by: Peter Geis Tested-by: Michael Riesch Link: https://lore.kernel.org/r/20211215210252.120923-8-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 98 ++++++++++++++++++++++++++++++++ 1 file changed, 98 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index a68033a23975..8ee2fab676f4 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -208,6 +208,50 @@ msi-controller; }; + usb_host0_ehci: usb@fd800000 { + compatible = "generic-ehci"; + reg = <0x0 0xfd800000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, + <&cru PCLK_USB>; + phys = <&u2phy1_otg>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host0_ohci: usb@fd840000 { + compatible = "generic-ohci"; + reg = <0x0 0xfd840000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, + <&cru PCLK_USB>; + phys = <&u2phy1_otg>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host1_ehci: usb@fd880000 { + compatible = "generic-ehci"; + reg = <0x0 0xfd880000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, + <&cru PCLK_USB>; + phys = <&u2phy1_host>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host1_ohci: usb@fd8c0000 { + compatible = "generic-ohci"; + reg = <0x0 0xfd8c0000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, + <&cru PCLK_USB>; + phys = <&u2phy1_host>; + phy-names = "usb"; + status = "disabled"; + }; + pmugrf: syscon@fdc20000 { compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; reg = <0x0 0xfdc20000 0x0 0x10000>; @@ -223,6 +267,16 @@ reg = <0x0 0xfdc60000 0x0 0x10000>; }; + usb2phy0_grf: syscon@fdca0000 { + compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; + reg = <0x0 0xfdca0000 0x0 0x8000>; + }; + + usb2phy1_grf: syscon@fdca8000 { + compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; + reg = <0x0 0xfdca8000 0x0 0x8000>; + }; + pmucru: clock-controller@fdd00000 { compatible = "rockchip,rk3568-pmucru"; reg = <0x0 0xfdd00000 0x0 0x1000>; @@ -1141,6 +1195,50 @@ status = "disabled"; }; + u2phy0: usb2phy@fe8a0000 { + compatible = "rockchip,rk3568-usb2phy"; + reg = <0x0 0xfe8a0000 0x0 0x10000>; + clocks = <&pmucru CLK_USBPHY0_REF>; + clock-names = "phyclk"; + clock-output-names = "clk_usbphy0_480m"; + interrupts = ; + rockchip,usbgrf = <&usb2phy0_grf>; + #clock-cells = <0>; + status = "disabled"; + + u2phy0_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + + u2phy0_otg: otg-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + + u2phy1: usb2phy@fe8b0000 { + compatible = "rockchip,rk3568-usb2phy"; + reg = <0x0 0xfe8b0000 0x0 0x10000>; + clocks = <&pmucru CLK_USBPHY1_REF>; + clock-names = "phyclk"; + clock-output-names = "clk_usbphy1_480m"; + interrupts = ; + rockchip,usbgrf = <&usb2phy1_grf>; + #clock-cells = <0>; + status = "disabled"; + + u2phy1_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + + u2phy1_otg: otg-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + pinctrl: pinctrl { compatible = "rockchip,rk3568-pinctrl"; rockchip,grf = <&grf>; -- cgit From 1ff37c22b16188f03400914ee20c597dd56ce25c Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Wed, 15 Dec 2021 16:02:52 -0500 Subject: arm64: dts: rockchip: add Quartz64-A usb2 support Add the nodes and regulators to enable usb2 support on the Quartz64 Model A. Signed-off-by: Peter Geis Tested-by: Michael Riesch Link: https://lore.kernel.org/r/20211215210252.120923-9-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 52 ++++++++++++++++++++++ 1 file changed, 52 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts index 166399b7f13f..f1d6bf10c650 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts @@ -124,6 +124,22 @@ vin-supply = <&vcc12v_dcin>; }; + /* all four ports are controlled by one gpio + * the host ports are sourced from vcc5v0_usb + * the otg port is sourced from vcc5v0_midu + */ + vcc5v0_usb20_host: vcc5v0_usb20_host { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb20_host_en>; + regulator-name = "vcc5v0_usb20_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + vcc3v3_sd: vcc3v3_sd { compatible = "regulator-fixed"; enable-active-low; @@ -477,6 +493,12 @@ }; }; + usb2 { + vcc5v0_usb20_host_en: vcc5v0-usb20-host-en { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + vcc_sd { vcc_sd_h: vcc-sd-h { rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; @@ -551,3 +573,33 @@ &uart2 { status = "okay"; }; + +&u2phy1_host { + phy-supply = <&vcc5v0_usb20_host>; + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_usb20_host>; + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; -- cgit From 756d68ee6e93c10d22688e0e8fee98c9f998750b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 11 Jan 2022 21:17:11 +0100 Subject: arm64: dts: exynos: align pinctrl with dtschema in Exynos5433 Align the pin controller related nodes with dtschema. No functional change expected. The macros used to define pin configuration do not work well with node name suffix "-pin" or prefix "pin-", so level of indirection via second macro is needed. For similar reason pcie-wlanen has to stop using the macro. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220111201722.327219-11-krzysztof.kozlowski@canonical.com --- arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi | 211 +++++++++-------- .../boot/dts/exynos/exynos5433-tm2-common.dtsi | 259 +++++++++++---------- 2 files changed, 241 insertions(+), 229 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi index 32a6518517e5..4b46af3e164d 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi @@ -11,16 +11,25 @@ #include -#define PIN(_func, _pin, _pull, _drv) \ - _pin { \ +#define PIN(_pin, _func, _pull, _drv) \ + pin- ## _pin { \ samsung,pins = #_pin; \ samsung,pin-function = ; \ samsung,pin-pud = ; \ samsung,pin-drv = ; \ } +#define PIN_IN(_pin, _pull, _drv) \ + PIN(_pin, INPUT, _pull, _drv) + +#define PIN_OT(_pin, _pull, _drv) \ + PIN(_pin, OUTPUT, _pull, _drv) + +#define PIN_F2(_pin, _pull, _drv) \ + PIN(_pin, 2, _pull, _drv) + &pinctrl_alive { - gpa0: gpa0 { + gpa0: gpa0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -37,7 +46,7 @@ #interrupt-cells = <2>; }; - gpa1: gpa1 { + gpa1: gpa1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -54,7 +63,7 @@ #interrupt-cells = <2>; }; - gpa2: gpa2 { + gpa2: gpa2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -62,7 +71,7 @@ #interrupt-cells = <2>; }; - gpa3: gpa3 { + gpa3: gpa3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -70,7 +79,7 @@ #interrupt-cells = <2>; }; - gpf1: gpf1 { + gpf1: gpf1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -78,7 +87,7 @@ #interrupt-cells = <2>; }; - gpf2: gpf2 { + gpf2: gpf2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -86,7 +95,7 @@ #interrupt-cells = <2>; }; - gpf3: gpf3 { + gpf3: gpf3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -94,7 +103,7 @@ #interrupt-cells = <2>; }; - gpf4: gpf4 { + gpf4: gpf4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -102,7 +111,7 @@ #interrupt-cells = <2>; }; - gpf5: gpf5 { + gpf5: gpf5-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -112,7 +121,7 @@ }; &pinctrl_aud { - gpz0: gpz0 { + gpz0: gpz0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -120,7 +129,7 @@ #interrupt-cells = <2>; }; - gpz1: gpz1 { + gpz1: gpz1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -128,7 +137,7 @@ #interrupt-cells = <2>; }; - i2s0_bus: i2s0-bus { + i2s0_bus: i2s0-bus-pins { samsung,pins = "gpz0-0", "gpz0-1", "gpz0-2", "gpz0-3", "gpz0-4", "gpz0-5", "gpz0-6"; samsung,pin-function = ; @@ -136,14 +145,14 @@ samsung,pin-drv = ; }; - pcm0_bus: pcm0-bus { + pcm0_bus: pcm0-bus-pins { samsung,pins = "gpz1-0", "gpz1-1", "gpz1-2", "gpz1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart_aud_bus: uart-aud-bus { + uart_aud_bus: uart-aud-bus-pins { samsung,pins = "gpz1-3", "gpz1-2", "gpz1-1", "gpz1-0"; samsung,pin-function = ; samsung,pin-pud = ; @@ -152,7 +161,7 @@ }; &pinctrl_cpif { - gpv6: gpv6 { + gpv6: gpv6-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -162,7 +171,7 @@ }; &pinctrl_ese { - gpj2: gpj2 { + gpj2: gpj2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -172,7 +181,7 @@ }; &pinctrl_finger { - gpd5: gpd5 { + gpd5: gpd5-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -180,14 +189,14 @@ #interrupt-cells = <2>; }; - spi2_bus: spi2-bus { + spi2_bus: spi2-bus-pins { samsung,pins = "gpd5-0", "gpd5-2", "gpd5-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hs_i2c6_bus: hs-i2c6-bus { + hs_i2c6_bus: hs-i2c6-bus-pins { samsung,pins = "gpd5-3", "gpd5-2"; samsung,pin-function = ; samsung,pin-pud = ; @@ -196,7 +205,7 @@ }; &pinctrl_fsys { - gph1: gph1 { + gph1: gph1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -204,7 +213,7 @@ #interrupt-cells = <2>; }; - gpr4: gpr4 { + gpr4: gpr4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -212,7 +221,7 @@ #interrupt-cells = <2>; }; - gpr0: gpr0 { + gpr0: gpr0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -220,7 +229,7 @@ #interrupt-cells = <2>; }; - gpr1: gpr1 { + gpr1: gpr1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -228,7 +237,7 @@ #interrupt-cells = <2>; }; - gpr2: gpr2 { + gpr2: gpr2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -236,7 +245,7 @@ #interrupt-cells = <2>; }; - gpr3: gpr3 { + gpr3: gpr3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -244,139 +253,139 @@ #interrupt-cells = <2>; }; - sd0_clk: sd0-clk { + sd0_clk: sd0-clk-pins { samsung,pins = "gpr0-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_cmd: sd0-cmd { + sd0_cmd: sd0-cmd-pins { samsung,pins = "gpr0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_rdqs: sd0-rdqs { + sd0_rdqs: sd0-rdqs-pins { samsung,pins = "gpr0-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_qrdy: sd0-qrdy { + sd0_qrdy: sd0-qrdy-pins { samsung,pins = "gpr0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_bus1: sd0-bus-width1 { + sd0_bus1: sd0-bus-width1-pins { samsung,pins = "gpr1-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_bus4: sd0-bus-width4 { + sd0_bus4: sd0-bus-width4-pins { samsung,pins = "gpr1-1", "gpr1-2", "gpr1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_bus8: sd0-bus-width8 { + sd0_bus8: sd0-bus-width8-pins { samsung,pins = "gpr1-4", "gpr1-5", "gpr1-6", "gpr1-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_clk: sd1-clk { + sd1_clk: sd1-clk-pins { samsung,pins = "gpr2-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_cmd: sd1-cmd { + sd1_cmd: sd1-cmd-pins { samsung,pins = "gpr2-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_bus1: sd1-bus-width1 { + sd1_bus1: sd1-bus-width1-pins { samsung,pins = "gpr3-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_bus4: sd1-bus-width4 { + sd1_bus4: sd1-bus-width4-pins { samsung,pins = "gpr3-1", "gpr3-2", "gpr3-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_bus8: sd1-bus-width8 { + sd1_bus8: sd1-bus-width8-pins { samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pcie_bus: pcie_bus { + pcie_bus: pcie-bus-pins { samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd2_clk: sd2-clk { + sd2_clk: sd2-clk-pins { samsung,pins = "gpr4-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_cmd: sd2-cmd { + sd2_cmd: sd2-cmd-pins { samsung,pins = "gpr4-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_cd: sd2-cd { + sd2_cd: sd2-cd-pins { samsung,pins = "gpr4-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_bus1: sd2-bus-width1 { + sd2_bus1: sd2-bus-width1-pins { samsung,pins = "gpr4-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_bus4: sd2-bus-width4 { + sd2_bus4: sd2-bus-width4-pins { samsung,pins = "gpr4-4", "gpr4-5", "gpr4-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_clk_output: sd2-clk-output { + sd2_clk_output: sd2-clk-output-pins { samsung,pins = "gpr4-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_cmd_output: sd2-cmd-output { + sd2_cmd_output: sd2-cmd-output-pins { samsung,pins = "gpr4-1"; samsung,pin-function = ; samsung,pin-pud = ; @@ -385,7 +394,7 @@ }; &pinctrl_imem { - gpf0: gpf0 { + gpf0: gpf0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -395,7 +404,7 @@ }; &pinctrl_nfc { - gpj0: gpj0 { + gpj0: gpj0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -403,7 +412,7 @@ #interrupt-cells = <2>; }; - hs_i2c4_bus: hs-i2c4-bus { + hs_i2c4_bus: hs-i2c4-bus-pins { samsung,pins = "gpj0-1", "gpj0-0"; samsung,pin-function = ; samsung,pin-pud = ; @@ -412,7 +421,7 @@ }; &pinctrl_peric { - gpv7: gpv7 { + gpv7: gpv7-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -420,7 +429,7 @@ #interrupt-cells = <2>; }; - gpb0: gpb0 { + gpb0: gpb0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -428,7 +437,7 @@ #interrupt-cells = <2>; }; - gpc0: gpc0 { + gpc0: gpc0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -436,7 +445,7 @@ #interrupt-cells = <2>; }; - gpc1: gpc1 { + gpc1: gpc1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -444,7 +453,7 @@ #interrupt-cells = <2>; }; - gpc2: gpc2 { + gpc2: gpc2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -452,7 +461,7 @@ #interrupt-cells = <2>; }; - gpc3: gpc3 { + gpc3: gpc3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -460,7 +469,7 @@ #interrupt-cells = <2>; }; - gpg0: gpg0 { + gpg0: gpg0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -468,7 +477,7 @@ #interrupt-cells = <2>; }; - gpd0: gpd0 { + gpd0: gpd0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -476,7 +485,7 @@ #interrupt-cells = <2>; }; - gpd1: gpd1 { + gpd1: gpd1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -484,7 +493,7 @@ #interrupt-cells = <2>; }; - gpd2: gpd2 { + gpd2: gpd2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -492,7 +501,7 @@ #interrupt-cells = <2>; }; - gpd4: gpd4 { + gpd4: gpd4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -500,7 +509,7 @@ #interrupt-cells = <2>; }; - gpd8: gpd8 { + gpd8: gpd8-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -508,7 +517,7 @@ #interrupt-cells = <2>; }; - gpd6: gpd6 { + gpd6: gpd6-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -516,7 +525,7 @@ #interrupt-cells = <2>; }; - gpd7: gpd7 { + gpd7: gpd7-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -524,7 +533,7 @@ #interrupt-cells = <2>; }; - gpg1: gpg1 { + gpg1: gpg1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -532,7 +541,7 @@ #interrupt-cells = <2>; }; - gpg2: gpg2 { + gpg2: gpg2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -540,7 +549,7 @@ #interrupt-cells = <2>; }; - gpg3: gpg3 { + gpg3: gpg3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -548,21 +557,21 @@ #interrupt-cells = <2>; }; - hs_i2c8_bus: hs-i2c8-bus { + hs_i2c8_bus: hs-i2c8-bus-pins { samsung,pins = "gpb0-1", "gpb0-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hs_i2c9_bus: hs-i2c9-bus { + hs_i2c9_bus: hs-i2c9-bus-pins { samsung,pins = "gpb0-3", "gpb0-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2s1_bus: i2s1-bus { + i2s1_bus: i2s1-bus-pins { samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2", "gpd4-3", "gpd4-4"; samsung,pin-function = ; @@ -570,7 +579,7 @@ samsung,pin-drv = ; }; - pcm1_bus: pcm1-bus { + pcm1_bus: pcm1-bus-pins { samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2", "gpd4-3", "gpd4-4"; samsung,pin-function = ; @@ -578,193 +587,193 @@ samsung,pin-drv = ; }; - spdif_bus: spdif-bus { + spdif_bus: spdif-bus-pins { samsung,pins = "gpd4-3", "gpd4-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - fimc_is_spi_pin0: fimc-is-spi-pin0 { + fimc_is_spi_pin0: fimc-is-spi-pin0-pins { samsung,pins = "gpc3-3", "gpc3-2", "gpc3-1", "gpc3-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - fimc_is_spi_pin1: fimc-is-spi-pin1 { + fimc_is_spi_pin1: fimc-is-spi-pin1-pins { samsung,pins = "gpc3-7", "gpc3-6", "gpc3-5", "gpc3-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart0_bus: uart0-bus { + uart0_bus: uart0-bus-pins { samsung,pins = "gpd0-3", "gpd0-2", "gpd0-1", "gpd0-0"; samsung,pin-function = ; samsung,pin-pud = ; }; - hs_i2c2_bus: hs-i2c2-bus { + hs_i2c2_bus: hs-i2c2-bus-pins { samsung,pins = "gpd0-3", "gpd0-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart2_bus: uart2-bus { + uart2_bus: uart2-bus-pins { samsung,pins = "gpd1-5", "gpd1-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - uart1_bus: uart1-bus { + uart1_bus: uart1-bus-pins { samsung,pins = "gpd1-3", "gpd1-2", "gpd1-1", "gpd1-0"; samsung,pin-function = ; samsung,pin-pud = ; }; - hs_i2c3_bus: hs-i2c3-bus { + hs_i2c3_bus: hs-i2c3-bus-pins { samsung,pins = "gpd1-3", "gpd1-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hs_i2c0_bus: hs-i2c0-bus { + hs_i2c0_bus: hs-i2c0-bus-pins { samsung,pins = "gpd2-1", "gpd2-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hs_i2c1_bus: hs-i2c1-bus { + hs_i2c1_bus: hs-i2c1-bus-pins { samsung,pins = "gpd2-3", "gpd2-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm0_out: pwm0-out { + pwm0_out: pwm0-out-pins { samsung,pins = "gpd2-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm1_out: pwm1-out { + pwm1_out: pwm1-out-pins { samsung,pins = "gpd2-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm2_out: pwm2-out { + pwm2_out: pwm2-out-pins { samsung,pins = "gpd2-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm3_out: pwm3-out { + pwm3_out: pwm3-out-pins { samsung,pins = "gpd2-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - spi1_bus: spi1-bus { + spi1_bus: spi1-bus-pins { samsung,pins = "gpd6-2", "gpd6-4", "gpd6-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hs_i2c7_bus: hs-i2c7-bus { + hs_i2c7_bus: hs-i2c7-bus-pins { samsung,pins = "gpd2-7", "gpd2-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - spi0_bus: spi0-bus { + spi0_bus: spi0-bus-pins { samsung,pins = "gpd8-0", "gpd6-0", "gpd6-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hs_i2c10_bus: hs-i2c10-bus { + hs_i2c10_bus: hs-i2c10-bus-pins { samsung,pins = "gpg3-1", "gpg3-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hs_i2c11_bus: hs-i2c11-bus { + hs_i2c11_bus: hs-i2c11-bus-pins { samsung,pins = "gpg3-3", "gpg3-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - spi3_bus: spi3-bus { + spi3_bus: spi3-bus-pins { samsung,pins = "gpg3-4", "gpg3-6", "gpg3-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - spi4_bus: spi4-bus { + spi4_bus: spi4-bus-pins { samsung,pins = "gpv7-1", "gpv7-3", "gpv7-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - fimc_is_uart: fimc-is-uart { + fimc_is_uart: fimc-is-uart-pins { samsung,pins = "gpc1-1", "gpc0-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - fimc_is_ch0_i2c: fimc-is-ch0_i2c { + fimc_is_ch0_i2c: fimc-is-ch0-i2c-pins { samsung,pins = "gpc2-1", "gpc2-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - fimc_is_ch0_mclk: fimc-is-ch0_mclk { + fimc_is_ch0_mclk: fimc-is-ch0-mclk-pins { samsung,pins = "gpd7-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - fimc_is_ch1_i2c: fimc-is-ch1-i2c { + fimc_is_ch1_i2c: fimc-is-ch1-i2c-pins { samsung,pins = "gpc2-3", "gpc2-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - fimc_is_ch1_mclk: fimc-is-ch1-mclk { + fimc_is_ch1_mclk: fimc-is-ch1-mclk-pins { samsung,pins = "gpd7-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - fimc_is_ch2_i2c: fimc-is-ch2-i2c { + fimc_is_ch2_i2c: fimc-is-ch2-i2c-pins { samsung,pins = "gpc2-5", "gpc2-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - fimc_is_ch2_mclk: fimc-is-ch2-mclk { + fimc_is_ch2_mclk: fimc-is-ch2-mclk-pins { samsung,pins = "gpd7-2"; samsung,pin-function = ; samsung,pin-pud = ; @@ -773,7 +782,7 @@ }; &pinctrl_touch { - gpj1: gpj1 { + gpj1: gpj1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -781,7 +790,7 @@ #interrupt-cells = <2>; }; - hs_i2c5_bus: hs-i2c5-bus { + hs_i2c5_bus: hs-i2c5-bus-pins { samsung,pins = "gpj1-1", "gpj1-0"; samsung,pin-function = ; samsung,pin-pud = ; diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi index cbcc01a66aab..be1b6b7da059 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi @@ -1011,80 +1011,80 @@ pinctrl-0 = <&initial_alive>; initial_alive: initial-state { - PIN(INPUT, gpa0-0, DOWN, FAST_SR1); - PIN(INPUT, gpa0-1, NONE, FAST_SR1); - PIN(INPUT, gpa0-2, DOWN, FAST_SR1); - PIN(INPUT, gpa0-3, NONE, FAST_SR1); - PIN(INPUT, gpa0-4, NONE, FAST_SR1); - PIN(INPUT, gpa0-5, DOWN, FAST_SR1); - PIN(INPUT, gpa0-6, NONE, FAST_SR1); - PIN(INPUT, gpa0-7, NONE, FAST_SR1); - - PIN(INPUT, gpa1-0, UP, FAST_SR1); - PIN(INPUT, gpa1-1, UP, FAST_SR1); - PIN(INPUT, gpa1-2, NONE, FAST_SR1); - PIN(INPUT, gpa1-3, DOWN, FAST_SR1); - PIN(INPUT, gpa1-4, DOWN, FAST_SR1); - PIN(INPUT, gpa1-5, NONE, FAST_SR1); - PIN(INPUT, gpa1-6, NONE, FAST_SR1); - PIN(INPUT, gpa1-7, NONE, FAST_SR1); - - PIN(INPUT, gpa2-0, NONE, FAST_SR1); - PIN(INPUT, gpa2-1, NONE, FAST_SR1); - PIN(INPUT, gpa2-2, NONE, FAST_SR1); - PIN(INPUT, gpa2-3, DOWN, FAST_SR1); - PIN(INPUT, gpa2-4, NONE, FAST_SR1); - PIN(INPUT, gpa2-5, DOWN, FAST_SR1); - PIN(INPUT, gpa2-6, DOWN, FAST_SR1); - PIN(INPUT, gpa2-7, NONE, FAST_SR1); - - PIN(INPUT, gpa3-0, DOWN, FAST_SR1); - PIN(INPUT, gpa3-1, DOWN, FAST_SR1); - PIN(INPUT, gpa3-2, NONE, FAST_SR1); - PIN(INPUT, gpa3-3, DOWN, FAST_SR1); - PIN(INPUT, gpa3-4, NONE, FAST_SR1); - PIN(INPUT, gpa3-5, DOWN, FAST_SR1); - PIN(INPUT, gpa3-6, DOWN, FAST_SR1); - PIN(INPUT, gpa3-7, DOWN, FAST_SR1); - - PIN(INPUT, gpf1-0, NONE, FAST_SR1); - PIN(INPUT, gpf1-1, NONE, FAST_SR1); - PIN(INPUT, gpf1-2, DOWN, FAST_SR1); - PIN(INPUT, gpf1-4, UP, FAST_SR1); - PIN(OUTPUT, gpf1-5, NONE, FAST_SR1); - PIN(INPUT, gpf1-6, DOWN, FAST_SR1); - PIN(INPUT, gpf1-7, DOWN, FAST_SR1); - - PIN(INPUT, gpf2-0, DOWN, FAST_SR1); - PIN(INPUT, gpf2-1, DOWN, FAST_SR1); - PIN(INPUT, gpf2-2, DOWN, FAST_SR1); - PIN(INPUT, gpf2-3, DOWN, FAST_SR1); - - PIN(INPUT, gpf3-0, DOWN, FAST_SR1); - PIN(INPUT, gpf3-1, DOWN, FAST_SR1); - PIN(INPUT, gpf3-2, NONE, FAST_SR1); - PIN(INPUT, gpf3-3, DOWN, FAST_SR1); - - PIN(INPUT, gpf4-0, DOWN, FAST_SR1); - PIN(INPUT, gpf4-1, DOWN, FAST_SR1); - PIN(INPUT, gpf4-2, DOWN, FAST_SR1); - PIN(INPUT, gpf4-3, DOWN, FAST_SR1); - PIN(INPUT, gpf4-4, DOWN, FAST_SR1); - PIN(INPUT, gpf4-5, DOWN, FAST_SR1); - PIN(INPUT, gpf4-6, DOWN, FAST_SR1); - PIN(INPUT, gpf4-7, DOWN, FAST_SR1); - - PIN(INPUT, gpf5-0, DOWN, FAST_SR1); - PIN(INPUT, gpf5-1, DOWN, FAST_SR1); - PIN(INPUT, gpf5-2, DOWN, FAST_SR1); - PIN(INPUT, gpf5-3, DOWN, FAST_SR1); - PIN(OUTPUT, gpf5-4, NONE, FAST_SR1); - PIN(INPUT, gpf5-5, DOWN, FAST_SR1); - PIN(INPUT, gpf5-6, DOWN, FAST_SR1); - PIN(INPUT, gpf5-7, DOWN, FAST_SR1); + PIN_IN(gpa0-0, DOWN, FAST_SR1); + PIN_IN(gpa0-1, NONE, FAST_SR1); + PIN_IN(gpa0-2, DOWN, FAST_SR1); + PIN_IN(gpa0-3, NONE, FAST_SR1); + PIN_IN(gpa0-4, NONE, FAST_SR1); + PIN_IN(gpa0-5, DOWN, FAST_SR1); + PIN_IN(gpa0-6, NONE, FAST_SR1); + PIN_IN(gpa0-7, NONE, FAST_SR1); + + PIN_IN(gpa1-0, UP, FAST_SR1); + PIN_IN(gpa1-1, UP, FAST_SR1); + PIN_IN(gpa1-2, NONE, FAST_SR1); + PIN_IN(gpa1-3, DOWN, FAST_SR1); + PIN_IN(gpa1-4, DOWN, FAST_SR1); + PIN_IN(gpa1-5, NONE, FAST_SR1); + PIN_IN(gpa1-6, NONE, FAST_SR1); + PIN_IN(gpa1-7, NONE, FAST_SR1); + + PIN_IN(gpa2-0, NONE, FAST_SR1); + PIN_IN(gpa2-1, NONE, FAST_SR1); + PIN_IN(gpa2-2, NONE, FAST_SR1); + PIN_IN(gpa2-3, DOWN, FAST_SR1); + PIN_IN(gpa2-4, NONE, FAST_SR1); + PIN_IN(gpa2-5, DOWN, FAST_SR1); + PIN_IN(gpa2-6, DOWN, FAST_SR1); + PIN_IN(gpa2-7, NONE, FAST_SR1); + + PIN_IN(gpa3-0, DOWN, FAST_SR1); + PIN_IN(gpa3-1, DOWN, FAST_SR1); + PIN_IN(gpa3-2, NONE, FAST_SR1); + PIN_IN(gpa3-3, DOWN, FAST_SR1); + PIN_IN(gpa3-4, NONE, FAST_SR1); + PIN_IN(gpa3-5, DOWN, FAST_SR1); + PIN_IN(gpa3-6, DOWN, FAST_SR1); + PIN_IN(gpa3-7, DOWN, FAST_SR1); + + PIN_IN(gpf1-0, NONE, FAST_SR1); + PIN_IN(gpf1-1, NONE, FAST_SR1); + PIN_IN(gpf1-2, DOWN, FAST_SR1); + PIN_IN(gpf1-4, UP, FAST_SR1); + PIN_OT(gpf1-5, NONE, FAST_SR1); + PIN_IN(gpf1-6, DOWN, FAST_SR1); + PIN_IN(gpf1-7, DOWN, FAST_SR1); + + PIN_IN(gpf2-0, DOWN, FAST_SR1); + PIN_IN(gpf2-1, DOWN, FAST_SR1); + PIN_IN(gpf2-2, DOWN, FAST_SR1); + PIN_IN(gpf2-3, DOWN, FAST_SR1); + + PIN_IN(gpf3-0, DOWN, FAST_SR1); + PIN_IN(gpf3-1, DOWN, FAST_SR1); + PIN_IN(gpf3-2, NONE, FAST_SR1); + PIN_IN(gpf3-3, DOWN, FAST_SR1); + + PIN_IN(gpf4-0, DOWN, FAST_SR1); + PIN_IN(gpf4-1, DOWN, FAST_SR1); + PIN_IN(gpf4-2, DOWN, FAST_SR1); + PIN_IN(gpf4-3, DOWN, FAST_SR1); + PIN_IN(gpf4-4, DOWN, FAST_SR1); + PIN_IN(gpf4-5, DOWN, FAST_SR1); + PIN_IN(gpf4-6, DOWN, FAST_SR1); + PIN_IN(gpf4-7, DOWN, FAST_SR1); + + PIN_IN(gpf5-0, DOWN, FAST_SR1); + PIN_IN(gpf5-1, DOWN, FAST_SR1); + PIN_IN(gpf5-2, DOWN, FAST_SR1); + PIN_IN(gpf5-3, DOWN, FAST_SR1); + PIN_OT(gpf5-4, NONE, FAST_SR1); + PIN_IN(gpf5-5, DOWN, FAST_SR1); + PIN_IN(gpf5-6, DOWN, FAST_SR1); + PIN_IN(gpf5-7, DOWN, FAST_SR1); }; - te_irq: te-irq { + te_irq: te-irq-pins { samsung,pins = "gpf1-3"; samsung,pin-function = <0xf>; }; @@ -1095,8 +1095,8 @@ pinctrl-0 = <&initial_cpif>; initial_cpif: initial-state { - PIN(INPUT, gpv6-0, DOWN, FAST_SR1); - PIN(INPUT, gpv6-1, DOWN, FAST_SR1); + PIN_IN(gpv6-0, DOWN, FAST_SR1); + PIN_IN(gpv6-1, DOWN, FAST_SR1); }; }; @@ -1104,13 +1104,16 @@ pinctrl-names = "default"; pinctrl-0 = <&initial_ese>; - pcie_wlanen: pcie-wlanen { - PIN(INPUT, gpj2-0, UP, FAST_SR4); + pcie_wlanen: pcie-wlanen-pins { + samsung,pins = "gpj2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; initial_ese: initial-state { - PIN(INPUT, gpj2-1, DOWN, FAST_SR1); - PIN(INPUT, gpj2-2, DOWN, FAST_SR1); + PIN_IN(gpj2-1, DOWN, FAST_SR1); + PIN_IN(gpj2-2, DOWN, FAST_SR1); }; }; @@ -1119,11 +1122,11 @@ pinctrl-0 = <&initial_fsys>; initial_fsys: initial-state { - PIN(INPUT, gpr3-0, NONE, FAST_SR1); - PIN(INPUT, gpr3-1, DOWN, FAST_SR1); - PIN(INPUT, gpr3-2, DOWN, FAST_SR1); - PIN(INPUT, gpr3-3, DOWN, FAST_SR1); - PIN(INPUT, gpr3-7, NONE, FAST_SR1); + PIN_IN(gpr3-0, NONE, FAST_SR1); + PIN_IN(gpr3-1, DOWN, FAST_SR1); + PIN_IN(gpr3-2, DOWN, FAST_SR1); + PIN_IN(gpr3-3, DOWN, FAST_SR1); + PIN_IN(gpr3-7, NONE, FAST_SR1); }; }; @@ -1132,14 +1135,14 @@ pinctrl-0 = <&initial_imem>; initial_imem: initial-state { - PIN(INPUT, gpf0-0, UP, FAST_SR1); - PIN(INPUT, gpf0-1, UP, FAST_SR1); - PIN(INPUT, gpf0-2, DOWN, FAST_SR1); - PIN(INPUT, gpf0-3, UP, FAST_SR1); - PIN(INPUT, gpf0-4, DOWN, FAST_SR1); - PIN(INPUT, gpf0-5, NONE, FAST_SR1); - PIN(INPUT, gpf0-6, DOWN, FAST_SR1); - PIN(INPUT, gpf0-7, UP, FAST_SR1); + PIN_IN(gpf0-0, UP, FAST_SR1); + PIN_IN(gpf0-1, UP, FAST_SR1); + PIN_IN(gpf0-2, DOWN, FAST_SR1); + PIN_IN(gpf0-3, UP, FAST_SR1); + PIN_IN(gpf0-4, DOWN, FAST_SR1); + PIN_IN(gpf0-5, NONE, FAST_SR1); + PIN_IN(gpf0-6, DOWN, FAST_SR1); + PIN_IN(gpf0-7, UP, FAST_SR1); }; }; @@ -1148,7 +1151,7 @@ pinctrl-0 = <&initial_nfc>; initial_nfc: initial-state { - PIN(INPUT, gpj0-2, DOWN, FAST_SR1); + PIN_IN(gpj0-2, DOWN, FAST_SR1); }; }; @@ -1157,53 +1160,53 @@ pinctrl-0 = <&initial_peric>; initial_peric: initial-state { - PIN(INPUT, gpv7-0, DOWN, FAST_SR1); - PIN(INPUT, gpv7-1, DOWN, FAST_SR1); - PIN(INPUT, gpv7-2, NONE, FAST_SR1); - PIN(INPUT, gpv7-3, DOWN, FAST_SR1); - PIN(INPUT, gpv7-4, DOWN, FAST_SR1); - PIN(INPUT, gpv7-5, DOWN, FAST_SR1); + PIN_IN(gpv7-0, DOWN, FAST_SR1); + PIN_IN(gpv7-1, DOWN, FAST_SR1); + PIN_IN(gpv7-2, NONE, FAST_SR1); + PIN_IN(gpv7-3, DOWN, FAST_SR1); + PIN_IN(gpv7-4, DOWN, FAST_SR1); + PIN_IN(gpv7-5, DOWN, FAST_SR1); - PIN(INPUT, gpb0-4, DOWN, FAST_SR1); + PIN_IN(gpb0-4, DOWN, FAST_SR1); - PIN(INPUT, gpc0-2, DOWN, FAST_SR1); - PIN(INPUT, gpc0-5, DOWN, FAST_SR1); - PIN(INPUT, gpc0-7, DOWN, FAST_SR1); + PIN_IN(gpc0-2, DOWN, FAST_SR1); + PIN_IN(gpc0-5, DOWN, FAST_SR1); + PIN_IN(gpc0-7, DOWN, FAST_SR1); - PIN(INPUT, gpc1-1, DOWN, FAST_SR1); + PIN_IN(gpc1-1, DOWN, FAST_SR1); - PIN(INPUT, gpc3-4, NONE, FAST_SR1); - PIN(INPUT, gpc3-5, NONE, FAST_SR1); - PIN(INPUT, gpc3-6, NONE, FAST_SR1); - PIN(INPUT, gpc3-7, NONE, FAST_SR1); + PIN_IN(gpc3-4, NONE, FAST_SR1); + PIN_IN(gpc3-5, NONE, FAST_SR1); + PIN_IN(gpc3-6, NONE, FAST_SR1); + PIN_IN(gpc3-7, NONE, FAST_SR1); - PIN(OUTPUT, gpg0-0, NONE, FAST_SR1); - PIN(2, gpg0-1, DOWN, FAST_SR1); + PIN_OT(gpg0-0, NONE, FAST_SR1); + PIN_F2(gpg0-1, DOWN, FAST_SR1); - PIN(INPUT, gpd2-5, DOWN, FAST_SR1); + PIN_IN(gpd2-5, DOWN, FAST_SR1); - PIN(INPUT, gpd4-0, NONE, FAST_SR1); - PIN(INPUT, gpd4-1, DOWN, FAST_SR1); - PIN(INPUT, gpd4-2, DOWN, FAST_SR1); - PIN(INPUT, gpd4-3, DOWN, FAST_SR1); - PIN(INPUT, gpd4-4, DOWN, FAST_SR1); + PIN_IN(gpd4-0, NONE, FAST_SR1); + PIN_IN(gpd4-1, DOWN, FAST_SR1); + PIN_IN(gpd4-2, DOWN, FAST_SR1); + PIN_IN(gpd4-3, DOWN, FAST_SR1); + PIN_IN(gpd4-4, DOWN, FAST_SR1); - PIN(INPUT, gpd6-3, DOWN, FAST_SR1); + PIN_IN(gpd6-3, DOWN, FAST_SR1); - PIN(INPUT, gpd8-1, UP, FAST_SR1); + PIN_IN(gpd8-1, UP, FAST_SR1); - PIN(INPUT, gpg1-0, DOWN, FAST_SR1); - PIN(INPUT, gpg1-1, DOWN, FAST_SR1); - PIN(INPUT, gpg1-2, DOWN, FAST_SR1); - PIN(INPUT, gpg1-3, DOWN, FAST_SR1); - PIN(INPUT, gpg1-4, DOWN, FAST_SR1); + PIN_IN(gpg1-0, DOWN, FAST_SR1); + PIN_IN(gpg1-1, DOWN, FAST_SR1); + PIN_IN(gpg1-2, DOWN, FAST_SR1); + PIN_IN(gpg1-3, DOWN, FAST_SR1); + PIN_IN(gpg1-4, DOWN, FAST_SR1); - PIN(INPUT, gpg2-0, DOWN, FAST_SR1); - PIN(INPUT, gpg2-1, DOWN, FAST_SR1); + PIN_IN(gpg2-0, DOWN, FAST_SR1); + PIN_IN(gpg2-1, DOWN, FAST_SR1); - PIN(INPUT, gpg3-0, DOWN, FAST_SR1); - PIN(INPUT, gpg3-1, DOWN, FAST_SR1); - PIN(INPUT, gpg3-5, DOWN, FAST_SR1); + PIN_IN(gpg3-0, DOWN, FAST_SR1); + PIN_IN(gpg3-1, DOWN, FAST_SR1); + PIN_IN(gpg3-5, DOWN, FAST_SR1); }; }; @@ -1212,7 +1215,7 @@ pinctrl-0 = <&initial_touch>; initial_touch: initial-state { - PIN(INPUT, gpj1-2, DOWN, FAST_SR1); + PIN_IN(gpj1-2, DOWN, FAST_SR1); }; }; -- cgit From ee045adb3768f508d33ed7780443c2a67c89a872 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 11 Jan 2022 21:17:12 +0100 Subject: arm64: dts: exynos: align pinctrl with dtschema in Exynos7 Align the pin controller related nodes with dtschema. No functional change expected. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Alim Akhtar Link: https://lore.kernel.org/r/20220111201722.327219-12-krzysztof.kozlowski@canonical.com --- arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 6 +- arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi | 176 ++++++++++++------------ 2 files changed, 91 insertions(+), 91 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts index 125c03f351d9..2826bafade8a 100644 --- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts +++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts @@ -354,7 +354,7 @@ }; &pinctrl_alive { - pmic_irq: pmic-irq { + pmic_irq: pmic-irq-pins { samsung,pins = "gpa0-2"; samsung,pin-pud = ; samsung,pin-drv = ; @@ -393,14 +393,14 @@ }; &pinctrl_bus1 { - usb30_vbus_en: usb30-vbus-en { + usb30_vbus_en: usb30-vbus-en-pins { samsung,pins = "gph1-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - usb3drd_boost_en: usb3drd-boost-en { + usb3drd_boost_en: usb3drd-boost-en-pins { samsung,pins = "gpf4-1"; samsung,pin-function = ; samsung,pin-pud = ; diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi index 472dd649aa7e..be9b971f3697 100644 --- a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi @@ -12,7 +12,7 @@ #include &pinctrl_alive { - gpa0: gpa0 { + gpa0: gpa0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -29,7 +29,7 @@ ; }; - gpa1: gpa1 { + gpa1: gpa1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -46,7 +46,7 @@ ; }; - gpa2: gpa2 { + gpa2: gpa2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -54,7 +54,7 @@ #interrupt-cells = <2>; }; - gpa3: gpa3 { + gpa3: gpa3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -64,7 +64,7 @@ }; &pinctrl_bus0 { - gpb0: gpb0 { + gpb0: gpb0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -72,7 +72,7 @@ #interrupt-cells = <2>; }; - gpc0: gpc0 { + gpc0: gpc0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -80,7 +80,7 @@ #interrupt-cells = <2>; }; - gpc1: gpc1 { + gpc1: gpc1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -88,7 +88,7 @@ #interrupt-cells = <2>; }; - gpc2: gpc2 { + gpc2: gpc2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -96,7 +96,7 @@ #interrupt-cells = <2>; }; - gpc3: gpc3 { + gpc3: gpc3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -104,7 +104,7 @@ #interrupt-cells = <2>; }; - gpd0: gpd0 { + gpd0: gpd0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -112,7 +112,7 @@ #interrupt-cells = <2>; }; - gpd1: gpd1 { + gpd1: gpd1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -120,7 +120,7 @@ #interrupt-cells = <2>; }; - gpd2: gpd2 { + gpd2: gpd2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -128,7 +128,7 @@ #interrupt-cells = <2>; }; - gpd4: gpd4 { + gpd4: gpd4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -136,7 +136,7 @@ #interrupt-cells = <2>; }; - gpd5: gpd5 { + gpd5: gpd5-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -144,7 +144,7 @@ #interrupt-cells = <2>; }; - gpd6: gpd6 { + gpd6: gpd6-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -152,7 +152,7 @@ #interrupt-cells = <2>; }; - gpd7: gpd7 { + gpd7: gpd7-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -160,7 +160,7 @@ #interrupt-cells = <2>; }; - gpd8: gpd8 { + gpd8: gpd8-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -168,7 +168,7 @@ #interrupt-cells = <2>; }; - gpg0: gpg0 { + gpg0: gpg0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -176,7 +176,7 @@ #interrupt-cells = <2>; }; - gpg3: gpg3 { + gpg3: gpg3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -184,161 +184,161 @@ #interrupt-cells = <2>; }; - hs_i2c10_bus: hs-i2c10-bus { + hs_i2c10_bus: hs-i2c10-bus-pins { samsung,pins = "gpb0-1", "gpb0-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hs_i2c11_bus: hs-i2c11-bus { + hs_i2c11_bus: hs-i2c11-bus-pins { samsung,pins = "gpb0-3", "gpb0-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hs_i2c2_bus: hs-i2c2-bus { + hs_i2c2_bus: hs-i2c2-bus-pins { samsung,pins = "gpd0-3", "gpd0-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart0_data: uart0-data { + uart0_data: uart0-data-pins { samsung,pins = "gpd0-0", "gpd0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart0_fctl: uart0-fctl { + uart0_fctl: uart0-fctl-pins { samsung,pins = "gpd0-2", "gpd0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart2_data: uart2-data { + uart2_data: uart2-data-pins { samsung,pins = "gpd1-4", "gpd1-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hs_i2c3_bus: hs-i2c3-bus { + hs_i2c3_bus: hs-i2c3-bus-pins { samsung,pins = "gpd1-3", "gpd1-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart1_data: uart1-data { + uart1_data: uart1-data-pins { samsung,pins = "gpd1-0", "gpd1-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart1_fctl: uart1-fctl { + uart1_fctl: uart1-fctl-pins { samsung,pins = "gpd1-2", "gpd1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hs_i2c0_bus: hs-i2c0-bus { + hs_i2c0_bus: hs-i2c0-bus-pins { samsung,pins = "gpd2-1", "gpd2-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hs_i2c1_bus: hs-i2c1-bus { + hs_i2c1_bus: hs-i2c1-bus-pins { samsung,pins = "gpd2-3", "gpd2-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hs_i2c9_bus: hs-i2c9-bus { + hs_i2c9_bus: hs-i2c9-bus-pins { samsung,pins = "gpd2-7", "gpd2-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm0_out: pwm0-out { + pwm0_out: pwm0-out-pins { samsung,pins = "gpd2-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm1_out: pwm1-out { + pwm1_out: pwm1-out-pins { samsung,pins = "gpd2-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm2_out: pwm2-out { + pwm2_out: pwm2-out-pins { samsung,pins = "gpd2-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm3_out: pwm3-out { + pwm3_out: pwm3-out-pins { samsung,pins = "gpd2-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hs_i2c8_bus: hs-i2c8-bus { + hs_i2c8_bus: hs-i2c8-bus-pins { samsung,pins = "gpd5-3", "gpd5-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart3_data: uart3-data { + uart3_data: uart3-data-pins { samsung,pins = "gpd5-0", "gpd5-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - spi2_bus: spi2-bus { + spi2_bus: spi2-bus-pins { samsung,pins = "gpd5-0", "gpd5-1", "gpd5-2", "gpd5-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - spi1_bus: spi1-bus { + spi1_bus: spi1-bus-pins { samsung,pins = "gpd6-2", "gpd6-3", "gpd6-4", "gpd6-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - spi0_bus: spi0-bus { + spi0_bus: spi0-bus-pins { samsung,pins = "gpd8-0", "gpd8-1", "gpd6-0", "gpd6-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hs_i2c4_bus: hs-i2c4-bus { + hs_i2c4_bus: hs-i2c4-bus-pins { samsung,pins = "gpg3-1", "gpg3-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hs_i2c5_bus: hs-i2c5-bus { + hs_i2c5_bus: hs-i2c5-bus-pins { samsung,pins = "gpg3-3", "gpg3-2"; samsung,pin-function = ; samsung,pin-pud = ; @@ -347,7 +347,7 @@ }; &pinctrl_nfc { - gpj0: gpj0 { + gpj0: gpj0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -355,7 +355,7 @@ #interrupt-cells = <2>; }; - hs_i2c6_bus: hs-i2c6-bus { + hs_i2c6_bus: hs-i2c6-bus-pins { samsung,pins = "gpj0-1", "gpj0-0"; samsung,pin-function = ; samsung,pin-pud = ; @@ -364,7 +364,7 @@ }; &pinctrl_touch { - gpj1: gpj1 { + gpj1: gpj1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -372,7 +372,7 @@ #interrupt-cells = <2>; }; - hs_i2c7_bus: hs-i2c7-bus { + hs_i2c7_bus: hs-i2c7-bus-pins { samsung,pins = "gpj1-1", "gpj1-0"; samsung,pin-function = ; samsung,pin-pud = ; @@ -381,7 +381,7 @@ }; &pinctrl_ff { - gpg4: gpg4 { + gpg4: gpg4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -389,7 +389,7 @@ #interrupt-cells = <2>; }; - spi3_bus: spi3-bus { + spi3_bus: spi3-bus-pins { samsung,pins = "gpg4-0", "gpg4-1", "gpg4-2", "gpg4-3"; samsung,pin-function = ; samsung,pin-pud = ; @@ -398,7 +398,7 @@ }; &pinctrl_ese { - gpv7: gpv7 { + gpv7: gpv7-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -406,7 +406,7 @@ #interrupt-cells = <2>; }; - spi4_bus: spi4-bus { + spi4_bus: spi4-bus-pins { samsung,pins = "gpv7-0", "gpv7-1", "gpv7-2", "gpv7-3"; samsung,pin-function = ; samsung,pin-pud = ; @@ -415,7 +415,7 @@ }; &pinctrl_fsys0 { - gpr4: gpr4 { + gpr4: gpr4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -423,35 +423,35 @@ #interrupt-cells = <2>; }; - sd2_clk: sd2-clk { + sd2_clk: sd2-clk-pins { samsung,pins = "gpr4-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_cmd: sd2-cmd { + sd2_cmd: sd2-cmd-pins { samsung,pins = "gpr4-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_cd: sd2-cd { + sd2_cd: sd2-cd-pins { samsung,pins = "gpr4-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_bus1: sd2-bus-width1 { + sd2_bus1: sd2-bus-width1-pins { samsung,pins = "gpr4-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_bus4: sd2-bus-width4 { + sd2_bus4: sd2-bus-width4-pins { samsung,pins = "gpr4-4", "gpr4-5", "gpr4-6"; samsung,pin-function = ; samsung,pin-pud = ; @@ -460,7 +460,7 @@ }; &pinctrl_fsys1 { - gpr0: gpr0 { + gpr0: gpr0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -468,7 +468,7 @@ #interrupt-cells = <2>; }; - gpr1: gpr1 { + gpr1: gpr1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -476,7 +476,7 @@ #interrupt-cells = <2>; }; - gpr2: gpr2 { + gpr2: gpr2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -484,7 +484,7 @@ #interrupt-cells = <2>; }; - gpr3: gpr3 { + gpr3: gpr3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -492,105 +492,105 @@ #interrupt-cells = <2>; }; - sd0_clk: sd0-clk { + sd0_clk: sd0-clk-pins { samsung,pins = "gpr0-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_cmd: sd0-cmd { + sd0_cmd: sd0-cmd-pins { samsung,pins = "gpr0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_ds: sd0-ds { + sd0_ds: sd0-ds-pins { samsung,pins = "gpr0-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_qrdy: sd0-qrdy { + sd0_qrdy: sd0-qrdy-pins { samsung,pins = "gpr0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_bus1: sd0-bus-width1 { + sd0_bus1: sd0-bus-width1-pins { samsung,pins = "gpr1-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_bus4: sd0-bus-width4 { + sd0_bus4: sd0-bus-width4-pins { samsung,pins = "gpr1-1", "gpr1-2", "gpr1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_bus8: sd0-bus-width8 { + sd0_bus8: sd0-bus-width8-pins { samsung,pins = "gpr1-4", "gpr1-5", "gpr1-6", "gpr1-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_clk: sd1-clk { + sd1_clk: sd1-clk-pins { samsung,pins = "gpr2-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_cmd: sd1-cmd { + sd1_cmd: sd1-cmd-pins { samsung,pins = "gpr2-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_ds: sd1-ds { + sd1_ds: sd1-ds-pins { samsung,pins = "gpr2-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_qrdy: sd1-qrdy { + sd1_qrdy: sd1-qrdy-pins { samsung,pins = "gpr2-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_int: sd1-int { + sd1_int: sd1-int-pins { samsung,pins = "gpr2-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_bus1: sd1-bus-width1 { + sd1_bus1: sd1-bus-width1-pins { samsung,pins = "gpr3-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_bus4: sd1-bus-width4 { + sd1_bus4: sd1-bus-width4-pins { samsung,pins = "gpr3-1", "gpr3-2", "gpr3-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_bus8: sd1-bus-width8 { + sd1_bus8: sd1-bus-width8-pins { samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7"; samsung,pin-function = ; samsung,pin-pud = ; @@ -599,7 +599,7 @@ }; &pinctrl_bus1 { - gpf0: gpf0 { + gpf0: gpf0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -607,7 +607,7 @@ #interrupt-cells = <2>; }; - gpf1: gpf1 { + gpf1: gpf1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -615,7 +615,7 @@ #interrupt-cells = <2>; }; - gpf2: gpf2 { + gpf2: gpf2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -623,7 +623,7 @@ #interrupt-cells = <2>; }; - gpf3: gpf3 { + gpf3: gpf3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -631,7 +631,7 @@ #interrupt-cells = <2>; }; - gpf4: gpf4 { + gpf4: gpf4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -639,7 +639,7 @@ #interrupt-cells = <2>; }; - gpf5: gpf5 { + gpf5: gpf5-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -647,7 +647,7 @@ #interrupt-cells = <2>; }; - gpg1: gpg1 { + gpg1: gpg1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -655,7 +655,7 @@ #interrupt-cells = <2>; }; - gpg2: gpg2 { + gpg2: gpg2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -663,7 +663,7 @@ #interrupt-cells = <2>; }; - gph1: gph1 { + gph1: gph1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -671,7 +671,7 @@ #interrupt-cells = <2>; }; - gpv6: gpv6 { + gpv6: gpv6-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -679,21 +679,21 @@ #interrupt-cells = <2>; }; - spi5_bus: spi5-bus { + spi5_bus: spi5-bus-pins { samsung,pins = "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - ufs_refclk_out: ufs-refclk-out { + ufs_refclk_out: ufs-refclk-out-pins { samsung,pins = "gpg2-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - ufs_rst_n: ufs-rst-n { + ufs_rst_n: ufs-rst-n-pins { samsung,pins = "gph1-5"; samsung,pin-function = ; samsung,pin-pud = ; -- cgit From 71b8d1253b7fe0be0ecf79a7249389c8711f0f94 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 11 Jan 2022 21:17:14 +0100 Subject: arm64: dts: exynos: align pinctrl with dtschema in ExynosAutov9 Align the pin controller related nodes with dtschema. No functional change expected. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Sam Protsenko Reviewed-by: Chanho Park Tested-by: Chanho Park Link: https://lore.kernel.org/r/20220111201722.327219-14-krzysztof.kozlowski@canonical.com --- .../boot/dts/exynos/exynosautov9-pinctrl.dtsi | 50 +++++++++++----------- 1 file changed, 25 insertions(+), 25 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/exynos/exynosautov9-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9-pinctrl.dtsi index 2407b03b5404..ef0349d1c3d0 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9-pinctrl.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov9-pinctrl.dtsi @@ -11,7 +11,7 @@ #include &pinctrl_alive { - gpa0: gpa0 { + gpa0: gpa0-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -27,7 +27,7 @@ ; }; - gpa1: gpa1 { + gpa1: gpa1-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -47,7 +47,7 @@ samsung,pin-function = ; }; - gpq0: gpq0 { + gpq0: gpq0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -69,7 +69,7 @@ }; &pinctrl_aud { - gpb0: gpb0 { + gpb0: gpb0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -77,7 +77,7 @@ #interrupt-cells = <2>; }; - gpb1: gpb1 { + gpb1: gpb1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -85,7 +85,7 @@ #interrupt-cells = <2>; }; - gpb2: gpb2 { + gpb2: gpb2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -93,7 +93,7 @@ #interrupt-cells = <2>; }; - gpb3: gpb3 { + gpb3: gpb3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -199,7 +199,7 @@ }; &pinctrl_fsys0 { - gpf0: gpf0 { + gpf0: gpf0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -207,7 +207,7 @@ #interrupt-cells = <2>; }; - gpf1: gpf1 { + gpf1: gpf1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -355,7 +355,7 @@ }; &pinctrl_fsys1 { - gpf8: gpf8 { + gpf8: gpf8-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -393,7 +393,7 @@ }; &pinctrl_fsys2 { - gpf2: gpf2 { + gpf2: gpf2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -401,7 +401,7 @@ #interrupt-cells = <2>; }; - gpf3: gpf3 { + gpf3: gpf3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -409,7 +409,7 @@ #interrupt-cells = <2>; }; - gpf4: gpf4 { + gpf4: gpf4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -417,7 +417,7 @@ #interrupt-cells = <2>; }; - gpf5: gpf5 { + gpf5: gpf5-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -425,7 +425,7 @@ #interrupt-cells = <2>; }; - gpf6: gpf6 { + gpf6: gpf6-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -499,7 +499,7 @@ }; &pinctrl_peric0 { - gpp0: gpp0 { + gpp0: gpp0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -507,7 +507,7 @@ #interrupt-cells = <2>; }; - gpp1: gpp1 { + gpp1: gpp1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -515,7 +515,7 @@ #interrupt-cells = <2>; }; - gpp2: gpp2 { + gpp2: gpp2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -523,7 +523,7 @@ #interrupt-cells = <2>; }; - gpg0: gpg0 { + gpg0: gpg0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -833,7 +833,7 @@ }; &pinctrl_peric1 { - gpp3: gpp3 { + gpp3: gpp3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -841,7 +841,7 @@ #interrupt-cells = <2>; }; - gpp4: gpp4 { + gpp4: gpp4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -849,7 +849,7 @@ #interrupt-cells = <2>; }; - gpp5: gpp5 { + gpp5: gpp5-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -857,7 +857,7 @@ #interrupt-cells = <2>; }; - gpg1: gpg1 { + gpg1: gpg1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -865,7 +865,7 @@ #interrupt-cells = <2>; }; - gpg2: gpg2 { + gpg2: gpg2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -873,7 +873,7 @@ #interrupt-cells = <2>; }; - gpg3: gpg3 { + gpg3: gpg3-gpio-bank { gpio-controller; #gpio-cells = <2>; -- cgit From 41bd4354a1513afa4a9dd9940d8cd790fbd00e68 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 11 Jan 2022 21:17:22 +0100 Subject: arm64: dts: exynos: use dedicated wake-up pinctrl compatible in ExynosAutov9 Older Samsung Exynos SoC pin controller nodes (Exynos3250, Exynos4, Exynos5, Exynos5433) with external wake-up interrupts, expected to have one interrupt for multiplexing these wake-up interrupts. Also they expected to have exactly one pin controller capable of external wake-up interrupts. It seems however that newer ARMv8 Exynos SoC like Exynos850 and ExynosAutov9 have differences: 1. No multiplexed external wake-up interrupt, only direct, 2. More than one pin controller capable of external wake-up interrupts. Use dedicated ExynosAutov9 compatible for its external wake-up interrupts controller to indicate the differences. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Sam Protsenko Reviewed-by: Chanho Park Tested-by: Chanho Park Link: https://lore.kernel.org/r/20220111201722.327219-22-krzysztof.kozlowski@canonical.com --- arch/arm64/boot/dts/exynos/exynosautov9.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi index de8fcb82eaec..807d500d6022 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi @@ -208,7 +208,7 @@ reg = <0x10450000 0x1000>; wakeup-interrupt-controller { - compatible = "samsung,exynos7-wakeup-eint"; + compatible = "samsung,exynosautov9-wakeup-eint"; }; }; -- cgit From 7638d3c945beb6c781acf5dd0a78e04c76f1c32f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 11 Jan 2022 18:48:01 +0100 Subject: arm64: dts: exynos: Align MAX77843 nodes with dtschema on TM2 The newly introduced dtschema for MAX77843 MUIC require the children to have proper naming and a port@0 property. This should not have actual impact on MFD children driver binding, because the max77843 MFD driver uses compatibles. The port@0 is disabled to avoid any impact. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220111174805.223732-2-krzysztof.kozlowski@canonical.com --- arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi index cbcc01a66aab..03f7c9acaacb 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi @@ -858,10 +858,10 @@ interrupts = <5 IRQ_TYPE_EDGE_FALLING>; reg = <0x66>; - muic: max77843-muic { + muic: extcon { compatible = "maxim,max77843-muic"; - musb_con: musb-connector { + musb_con: connector { compatible = "samsung,usb-connector-11pin", "usb-b-connector"; label = "micro-USB"; @@ -871,6 +871,17 @@ #address-cells = <1>; #size-cells = <0>; + port@0 { + /* + * TODO: The DTS this is based on does not have + * port@0 which is a required property. The ports + * look incomplete and need fixing. + * Add a disabled port just to satisfy dtschema. + */ + reg = <0>; + status = "disabled"; + }; + port@3 { reg = <3>; musb_con_to_mhl: endpoint { @@ -910,7 +921,7 @@ }; }; - haptic: max77843-haptic { + haptic: motor-driver { compatible = "maxim,max77843-haptic"; haptic-supply = <&ldo38_reg>; pwms = <&pwm 0 33670 0>; -- cgit From 372d171cd9b472cff7852211195f211150bc27d2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 2 Jan 2022 12:53:49 +0100 Subject: arm64: dts: exynos: add necessary clock inputs in Exynos7 Exynos7 devicetree bindings require more input clocks for TOP0 and PERIC1 clock controllers, than already provided. Existing DTS was not matching the bindings, so let's update the DTS, even though the error could be in the bindings. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220102115356.75796-1-krzysztof.kozlowski@canonical.com --- arch/arm64/boot/dts/exynos/exynos7.dtsi | 33 +++++++++++++++++++++++++++------ 1 file changed, 27 insertions(+), 6 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index c3efbc8add38..3e53ff2be455 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -177,10 +177,11 @@ clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>, <&clock_topc DOUT_SCLK_BUS1_PLL>, <&clock_topc DOUT_SCLK_CC_PLL>, - <&clock_topc DOUT_SCLK_MFC_PLL>; + <&clock_topc DOUT_SCLK_MFC_PLL>, + <&clock_topc DOUT_SCLK_AUD_PLL>; clock-names = "fin_pll", "dout_sclk_bus0_pll", "dout_sclk_bus1_pll", "dout_sclk_cc_pll", - "dout_sclk_mfc_pll"; + "dout_sclk_mfc_pll", "dout_sclk_aud_pll"; }; clock_top1: clock-controller@105e0000 { @@ -218,12 +219,32 @@ compatible = "samsung,exynos7-clock-peric1"; reg = <0x14c80000 0xd00>; #clock-cells = <1>; - clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>, + clocks = <&fin_pll>, + <&clock_top0 DOUT_ACLK_PERIC1>, <&clock_top0 CLK_SCLK_UART1>, <&clock_top0 CLK_SCLK_UART2>, - <&clock_top0 CLK_SCLK_UART3>; - clock-names = "fin_pll", "dout_aclk_peric1_66", - "sclk_uart1", "sclk_uart2", "sclk_uart3"; + <&clock_top0 CLK_SCLK_UART3>, + <&clock_top0 CLK_SCLK_SPI0>, + <&clock_top0 CLK_SCLK_SPI1>, + <&clock_top0 CLK_SCLK_SPI2>, + <&clock_top0 CLK_SCLK_SPI3>, + <&clock_top0 CLK_SCLK_SPI4>, + <&clock_top0 CLK_SCLK_I2S1>, + <&clock_top0 CLK_SCLK_PCM1>, + <&clock_top0 CLK_SCLK_SPDIF>; + clock-names = "fin_pll", + "dout_aclk_peric1_66", + "sclk_uart1", + "sclk_uart2", + "sclk_uart3", + "sclk_spi0", + "sclk_spi1", + "sclk_spi2", + "sclk_spi3", + "sclk_spi4", + "sclk_i2s1", + "sclk_pcm1", + "sclk_spdif"; }; clock_peris: clock-controller@10040000 { -- cgit From 9eca8bdf0a254c3e6c56d34b2412388abd68e035 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 23 Jun 2021 17:02:29 +0200 Subject: arm64: dts: renesas: r8a779a0: Add INTC-EX device node Populate the device node for the Interrupt Controller for External Devices (INTC-EX) on R-Car V3U, which serves external IRQ pins IRQ[0-5]. Signed-off-by: Geert Uytterhoeven Tested-by: Kieran Bingham Link: https://lore.kernel.org/r/4e2297e1066df483c0434df487df5b79e76b75b8.1624460378.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 1e7ed12ebc87..9ad1b23ad2ec 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -340,6 +340,21 @@ #thermal-sensor-cells = <1>; }; + intc_ex: interrupt-controller@e61c0000 { + compatible = "renesas,intc-ex-r8a779a0", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = , + , + , + , + , + ; + clocks = <&cpg CPG_CORE R8A779A0_CLK_CP>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + }; + tmu0: timer@e61e0000 { compatible = "renesas,tmu-r8a779a0", "renesas,tmu"; reg = <0 0xe61e0000 0 0x30>; -- cgit From 3a4f33ee57faaae498e6997ec8a4262e00da223e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 8 Dec 2021 16:56:24 -0300 Subject: arm64: dts: renesas: beacon: Remove the 'pm-ignore-notify' property The 'pm-ignore-notify' property is not a valid property and there is no bindings documentation for it. Drop such invalid property. Signed-off-by: Fabio Estevam Link: https://lore.kernel.org/r/20211208195624.1864654-1-festevam@gmail.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi index 0d136809eb96..17d5c4501bbe 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi @@ -293,7 +293,6 @@ vqmmc-supply = <®_1p8v>; non-removable; cap-power-off-card; - pm-ignore-notify; keep-power-in-suspend; mmc-pwrseq = <&wlan_pwrseq>; status = "okay"; -- cgit From 65d2bc885b01642bbd0898b8af573783ab84f835 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 16 Dec 2021 11:43:03 +0000 Subject: arm64: dts: renesas: rzg2l-smarc: Move pinctrl definitions RZ/G2L and RZ/G2LC SMARC EVK use the same carrier board, but the pin mappings between the RZ/G2L and the RZ/G2LC SMARC SoM are different. Therefore we need to update the carrier board pin definitions based on the corresponding SoM pin mapping. Move pinctrl definitions out of the RZ/G2L SMARC common file, so that we can reuse the common file to support RZ/G2LC SMARC EVK. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20211216114305.5842-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts | 1 + .../boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi | 137 +++++++++++++++++++++ arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 127 ------------------- 3 files changed, 138 insertions(+), 127 deletions(-) create mode 100644 arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts index 247b0b3f1b58..886d38886d05 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "r9a07g044l2.dtsi" #include "rzg2l-smarc-som.dtsi" +#include "rzg2l-smarc-pinfunction.dtsi" #include "rzg2l-smarc.dtsi" / { diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi new file mode 100644 index 000000000000..71d83e447670 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2L SMARC pincontrol parts + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include +#include + +&pinctrl { + pinctrl-0 = <&sound_clk_pins>; + pinctrl-names = "default"; + + can0_pins: can0 { + pinmux = , /* TX */ + ; /* RX */ + }; + + /* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */ + can0-stb { + gpio-hog; + gpios = ; + output-low; + line-name = "can0_stb"; + }; + + can1_pins: can1 { + pinmux = , /* TX */ + ; /* RX */ + }; + + /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */ + can1-stb { + gpio-hog; + gpios = ; + output-low; + line-name = "can1_stb"; + }; + + i2c0_pins: i2c0 { + pins = "RIIC0_SDA", "RIIC0_SCL"; + input-enable; + }; + + i2c1_pins: i2c1 { + pins = "RIIC1_SDA", "RIIC1_SCL"; + input-enable; + }; + + i2c3_pins: i2c3 { + pinmux = , /* SDA */ + ; /* SCL */ + }; + + scif0_pins: scif0 { + pinmux = , /* TxD */ + ; /* RxD */ + }; + + scif2_pins: scif2 { + pinmux = , /* TxD */ + , /* RxD */ + , /* CTS# */ + ; /* RTS# */ + }; + + sd1-pwr-en-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "sd1_pwr_en"; + }; + + sdhi1_pins: sd1 { + sd1_data { + pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; + power-source = <3300>; + }; + + sd1_ctrl { + pins = "SD1_CLK", "SD1_CMD"; + power-source = <3300>; + }; + + sd1_mux { + pinmux = ; /* SD1_CD */ + }; + }; + + sdhi1_pins_uhs: sd1_uhs { + sd1_data_uhs { + pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; + power-source = <1800>; + }; + + sd1_ctrl_uhs { + pins = "SD1_CLK", "SD1_CMD"; + power-source = <1800>; + }; + + sd1_mux_uhs { + pinmux = ; /* SD1_CD */ + }; + }; + + sound_clk_pins: sound_clk { + pins = "AUDIO_CLK1", "AUDIO_CLK2"; + input-enable; + }; + + spi1_pins: spi1 { + pinmux = , /* CK */ + , /* MOSI */ + , /* MISO */ + ; /* SSL */ + }; + + ssi0_pins: ssi0 { + pinmux = , /* BCK */ + , /* RCK */ + , /* TXD */ + ; /* RXD */ + }; + + usb0_pins: usb0 { + pinmux = , /* VBUS */ + , /* OVC */ + ; /* OTG_ID */ + }; + + usb1_pins: usb1 { + pinmux = , /* VBUS */ + ; /* OVC */ + }; +}; + diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index 6f2a8bdfa225..46abb29718cc 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -162,133 +162,6 @@ status = "okay"; }; -&pinctrl { - pinctrl-0 = <&sound_clk_pins>; - pinctrl-names = "default"; - - can0_pins: can0 { - pinmux = , /* TX */ - ; /* RX */ - }; - - /* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */ - can0-stb { - gpio-hog; - gpios = ; - output-low; - line-name = "can0_stb"; - }; - - can1_pins: can1 { - pinmux = , /* TX */ - ; /* RX */ - }; - - /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */ - can1-stb { - gpio-hog; - gpios = ; - output-low; - line-name = "can1_stb"; - }; - - i2c0_pins: i2c0 { - pins = "RIIC0_SDA", "RIIC0_SCL"; - input-enable; - }; - - i2c1_pins: i2c1 { - pins = "RIIC1_SDA", "RIIC1_SCL"; - input-enable; - }; - - i2c3_pins: i2c3 { - pinmux = , /* SDA */ - ; /* SCL */ - }; - - scif0_pins: scif0 { - pinmux = , /* TxD */ - ; /* RxD */ - }; - - scif2_pins: scif2 { - pinmux = , /* TxD */ - , /* RxD */ - , /* CTS# */ - ; /* RTS# */ - }; - - sd1-pwr-en-hog { - gpio-hog; - gpios = ; - output-high; - line-name = "sd1_pwr_en"; - }; - - sdhi1_pins: sd1 { - sd1_data { - pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; - power-source = <3300>; - }; - - sd1_ctrl { - pins = "SD1_CLK", "SD1_CMD"; - power-source = <3300>; - }; - - sd1_mux { - pinmux = ; /* SD1_CD */ - }; - }; - - sdhi1_pins_uhs: sd1_uhs { - sd1_data_uhs { - pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; - power-source = <1800>; - }; - - sd1_ctrl_uhs { - pins = "SD1_CLK", "SD1_CMD"; - power-source = <1800>; - }; - - sd1_mux_uhs { - pinmux = ; /* SD1_CD */ - }; - }; - - sound_clk_pins: sound_clk { - pins = "AUDIO_CLK1", "AUDIO_CLK2"; - input-enable; - }; - - spi1_pins: spi1 { - pinmux = , /* CK */ - , /* MOSI */ - , /* MISO */ - ; /* SSL */ - }; - - ssi0_pins: ssi0 { - pinmux = , /* BCK */ - , /* RCK */ - , /* TXD */ - ; /* RXD */ - }; - - usb0_pins: usb0 { - pinmux = , /* VBUS */ - , /* OVC */ - ; /* OTG_ID */ - }; - - usb1_pins: usb1 { - pinmux = , /* VBUS */ - ; /* OVC */ - }; -}; - &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; -- cgit From 3a3c2a48d8c6ba586a2eda249b0e2f5f19609dfd Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 16 Dec 2021 11:43:04 +0000 Subject: arm64: dts: renesas: Add initial DTSI for RZ/G2LC SoC The RZ/G2L and RZ/G2LC SoCs are similar and they share the same DEVID. RZ/G2LC has fewer peripherals compared to RZ/G2L. SSI (3 channels vs 4 channels) GbEthernet (1 channel vs 2 channels) SCIFA (4 channels vs 5 channels) ADC is only supported in RZ/G2L. Add the initial DTSI for the RZ/G2LC SoC by reusing the common r9a07g044.dtsi file with unsupported device nodes deleted in the below SoC specific dtsi files. r9a07g044c1.dtsi => RZ/G2LC R9A07G044C1 SoC specific parts r9a07g044c2.dtsi => RZ/G2LC R9A07G044C2 SoC specific parts Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20211216114305.5842-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi | 32 ++++++++++++++++++++++++++++ arch/arm64/boot/dts/renesas/r9a07g044c2.dtsi | 20 +++++++++++++++++ 2 files changed, 52 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044c2.dtsi (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi new file mode 100644 index 000000000000..1d57df706939 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2LC R9A07G044C1 SoC specific parts + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a07g044.dtsi" + +/ { + compatible = "renesas,r9a07g044c1", "renesas,r9a07g044"; + + cpus { + /delete-node/ cpu-map; + /delete-node/ cpu@100; + }; + + timer { + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; + +&soc { + /delete-node/ ssi@1004a800; + /delete-node/ serial@1004c800; + /delete-node/ adc@10059000; + /delete-node/ ethernet@11c30000; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044c2.dtsi new file mode 100644 index 000000000000..7bb8917fe421 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2LC R9A07G044C2 SoC specific parts + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a07g044.dtsi" + +/ { + compatible = "renesas,r9a07g044c2", "renesas,r9a07g044"; +}; + +&soc { + /delete-node/ ssi@1004a800; + /delete-node/ serial@1004c800; + /delete-node/ adc@10059000; + /delete-node/ ethernet@11c30000; +}; -- cgit From ce0c63b6a5ef86208d1008ce6c42a7a7180aaf75 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 16 Dec 2021 11:43:05 +0000 Subject: arm64: dts: renesas: Add initial device tree for RZ/G2LC SMARC EVK Add basic support for the RZ/G2LC SMARC EVK (based on R9A07G044C2): - memory - External input clock - SCIF - GbEthernet - Audio Clock It shares the same carrier board with RZ/G2L, but the pin mapping is different. Disable the device nodes which are not tested and delete the corresponding pinctrl definitions. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20211216114305.5842-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 1 + arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts | 114 +++++++++++++++++++++ .../boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 25 +++++ arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi | 76 ++++++++++++++ 4 files changed, 216 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts create mode 100644 arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi create mode 100644 arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 5bc8065a7864..f1ab09486bab 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -75,4 +75,5 @@ dtb-$(CONFIG_ARCH_R8A77961) += r8a779m3-ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs.dtb +dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts new file mode 100644 index 000000000000..728a2275ea8d --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2LC SMARC EVK board + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a07g044c2.dtsi" +#include "rzg2lc-smarc-som.dtsi" +#include "rzg2lc-smarc-pinfunction.dtsi" +#include "rzg2l-smarc.dtsi" + +/ { + model = "Renesas SMARC EVK based on r9a07g044c2"; + compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044"; + +}; + +&canfd { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&ehci0 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&ehci1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&hsusb { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&i2c0 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&i2c1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&i2c3 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&ohci0 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&ohci1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&phyrst { + status = "disabled"; +}; + +&scif2 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&sdhi1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-1; + /delete-property/ pinctrl-names; + /delete-property/ vmmc-supply; + status = "disabled"; +}; + +&spi1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&ssi0 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&usb2_phy0 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&usb2_phy1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi new file mode 100644 index 000000000000..5333a1f9a0e7 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2LC SMARC pincontrol parts + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include +#include + +&pinctrl { + pinctrl-0 = <&sound_clk_pins>; + pinctrl-names = "default"; + + scif0_pins: scif0 { + pinmux = , /* TxD */ + ; /* RxD */ + }; + + sound_clk_pins: sound_clk { + pins = "AUDIO_CLK1", "AUDIO_CLK2"; + input-enable; + }; +}; + diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi new file mode 100644 index 000000000000..e1d7a3a689c6 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2LC SMARC SOM common parts + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include +#include + +/ { + aliases { + ethernet0 = ð0; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x38000000>; + }; +}; + +ð0 { + pinctrl-0 = <ð0_pins>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + phy0: ethernet-phy@7 { + compatible = "ethernet-phy-id0022.1640", + "ethernet-phy-ieee802.3-c22"; + reg = <7>; + rxc-skew-psec = <2400>; + txc-skew-psec = <2400>; + rxdv-skew-psec = <0>; + txdv-skew-psec = <0>; + rxd0-skew-psec = <0>; + rxd1-skew-psec = <0>; + rxd2-skew-psec = <0>; + rxd3-skew-psec = <0>; + txd0-skew-psec = <0>; + txd1-skew-psec = <0>; + txd2-skew-psec = <0>; + txd3-skew-psec = <0>; + }; +}; + +&extal_clk { + clock-frequency = <24000000>; +}; + +&pinctrl { + eth0_pins: eth0 { + pinmux = , /* ET0_LINKSTA */ + , /* ET0_MDC */ + , /* ET0_MDIO */ + , /* ET0_TXC */ + , /* ET0_TX_CTL */ + , /* ET0_TXD0 */ + , /* ET0_TXD1 */ + , /* ET0_TXD2 */ + , /* ET0_TXD3 */ + , /* ET0_RXC */ + , /* ET0_RX_CTL */ + , /* ET0_RXD0 */ + , /* ET0_RXD1 */ + , /* ET0_RXD2 */ + ; /* ET0_RXD3 */ + }; +}; + -- cgit From 9199da68372a3c2f89936649a4fe777329119c41 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Thu, 16 Dec 2021 17:34:36 +0100 Subject: arm64: dts: renesas: condor: Enable MAX9286 Enable the MAX9286 GMSL deserializers on Condor-V3H board. Connected cameras should be defined in a device-tree overlay or included after these definitions. Signed-off-by: Jacopo Mondi Reviewed-by: Kieran Bingham Link: https://lore.kernel.org/r/20211216163439.139579-5-jacopo+renesas@jmondi.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 191 ++++++++++++++++++++++++ 1 file changed, 191 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts index 3d6d10c82f48..43ed033eb512 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts +++ b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts @@ -108,6 +108,34 @@ }; }; +&csi40 { + status = "okay"; + + ports { + port@0 { + csi40_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&max9286_out0>; + }; + }; + }; +}; + +&csi41 { + status = "okay"; + + ports { + port@0 { + csi41_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&max9286_out1>; + }; + }; + }; +}; + &du { clocks = <&cpg CPG_MOD 724>, <&x1_clk>; @@ -200,6 +228,164 @@ }; }; +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + gmsl0: gmsl-deserializer@48 { + compatible = "maxim,max9286"; + reg = <0x48>; + + maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>; + enable-gpios = <&io_expander0 0 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + + port@2 { + reg = <2>; + }; + + port@3 { + reg = <3>; + }; + + port@4 { + reg = <4>; + max9286_out0: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&csi40_in>; + }; + }; + }; + + i2c-mux { + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + status = "disabled"; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + status = "disabled"; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + status = "disabled"; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + status = "disabled"; + }; + }; + }; + + gmsl1: gmsl-deserializer@4a { + compatible = "maxim,max9286"; + reg = <0x4a>; + + maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>; + enable-gpios = <&io_expander1 0 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + + port@2 { + reg = <2>; + }; + + port@3 { + reg = <3>; + }; + + port@4 { + reg = <4>; + max9286_out1: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&csi41_in>; + }; + }; + }; + + i2c-mux { + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + status = "disabled"; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + status = "disabled"; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + status = "disabled"; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + status = "disabled"; + }; + }; + }; +}; + &lvds0 { status = "okay"; @@ -256,6 +442,11 @@ function = "i2c0"; }; + i2c1_pins: i2c1 { + groups = "i2c1"; + function = "i2c1"; + }; + mmc_pins: mmc { groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; function = "mmc"; -- cgit From 557165ffb92e35850dda85cf1a7d0e6ef93b8d36 Mon Sep 17 00:00:00 2001 From: Kieran Bingham Date: Thu, 16 Dec 2021 17:34:37 +0100 Subject: arm64: dts: renesas: eagle: Enable MAX9286 Enable the MAX9286 GMSL deserializer on the Eagle-V3M board. Connected cameras should be defined in a device-tree overlay or included after these definitions. Reviewed-by: Laurent Pinchart Signed-off-by: Kieran Bingham Signed-off-by: Jacopo Mondi Reviewed-by: Kieran Bingham Link: https://lore.kernel.org/r/20211216163439.139579-6-jacopo+renesas@jmondi.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 102 +++++++++++++++++++++++++ 1 file changed, 102 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts index b579d3189a93..49d1a929aef7 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts @@ -113,6 +113,20 @@ }; }; +&csi40 { + status = "okay"; + + ports { + port@0 { + csi40_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&max9286_out0>; + }; + }; + }; +}; + &du { clocks = <&cpg CPG_MOD 724>, <&x1_clk>; clock-names = "du.0", "dclkin.0"; @@ -172,6 +186,89 @@ }; }; +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + gmsl0: gmsl-deserializer@48 { + compatible = "maxim,max9286"; + reg = <0x48>; + + maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>; + enable-gpios = <&io_expander 0 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + + port@2 { + reg = <2>; + }; + + port@3 { + reg = <3>; + }; + + port@4 { + reg = <4>; + max9286_out0: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&csi40_in>; + }; + }; + }; + + i2c-mux { + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + status = "disabled"; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + status = "disabled"; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + status = "disabled"; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + status = "disabled"; + }; + }; + }; +}; + &lvds0 { status = "okay"; @@ -200,6 +297,11 @@ function = "i2c0"; }; + i2c3_pins: i2c3 { + groups = "i2c3_a"; + function = "i2c3"; + }; + qspi0_pins: qspi0 { groups = "qspi0_ctrl", "qspi0_data4"; function = "qspi0"; -- cgit From ad6a6ed4d954cfddf48e4a36d69d4cfd92344e9a Mon Sep 17 00:00:00 2001 From: Kieran Bingham Date: Thu, 16 Dec 2021 17:34:38 +0100 Subject: arm64: dts: renesas: Add GMSL cameras .dtsi Describe the FAKRA connector available on Eagle and Condor boards that allow to connect GMSL camera modules such as IMI RDACM20 and RDACM21. Signed-off-by: Kieran Bingham Signed-off-by: Jacopo Mondi Reviewed-by: Laurent Pinchart Link: https://lore.kernel.org/r/20211216163439.139579-7-jacopo+renesas@jmondi.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/gmsl-cameras.dtsi | 332 ++++++++++++++++++++++++++ 1 file changed, 332 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/gmsl-cameras.dtsi (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/renesas/gmsl-cameras.dtsi b/arch/arm64/boot/dts/renesas/gmsl-cameras.dtsi new file mode 100644 index 000000000000..d45f072f8cdf --- /dev/null +++ b/arch/arm64/boot/dts/renesas/gmsl-cameras.dtsi @@ -0,0 +1,332 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Ideas on Board + * Copyright (C) 2021 Jacopo Mondi + * + * Device Tree Source (overlay) that describes GMSL camera connected to + * Fakra connectors for the Eagle V3M and Condor V3H (and compatible) boards. + * + * The following cameras are currently supported: RDACM20 and RDACM21. + * + * The board .dts file that include this has to select which cameras are in use + * by specifying the camera model with: + * + * #define GMSL_CAMERA_RDACM20 + * or + * #define GMSL_CAMERA_RDACM21 + * + * And which cameras are connected to the board by defining: + * for GMSL channel 0: + * #define GMSL_CAMERA_0 + * #define GMSL_CAMERA_1 + * #define GMSL_CAMERA_2 + * #define GMSL_CAMERA_3 + * + * for GMSL channel 1: + * #define GMSL_CAMERA_4 + * #define GMSL_CAMERA_5 + * #define GMSL_CAMERA_6 + * #define GMSL_CAMERA_7 + */ + +#include + +/* Validate the board file settings. */ +#if !defined(GMSL_CAMERA_RDACM20) && !defined(GMSL_CAMERA_RDACM21) +#error "Camera model should be defined by the board file" +#endif + +#if defined(GMSL_CAMERA_RDACM20) && defined(GMSL_CAMERA_RDACM21) +#error "A single camera model should be selected" +#endif + +#if !defined(GMSL_CAMERA_0) && !defined(GMSL_CAMERA_1) && \ + !defined(GMSL_CAMERA_2) && !defined(GMSL_CAMERA_3) && \ + !defined(GMSL_CAMERA_4) && !defined(GMSL_CAMERA_5) && \ + !defined(GMSL_CAMERA_6) && !defined(GMSL_CAMERA_7) +#error "At least one camera should be selected" +#endif + +/* Deduce from the enabled cameras which GMSL channels are active. */ +#if defined(GMSL_CAMERA_0) || defined(GMSL_CAMERA_1) || \ + defined(GMSL_CAMERA_2) || defined(GMSL_CAMERA_3) +#define GMSL_0 +#endif + +#if defined(GMSL_CAMERA_4) || defined(GMSL_CAMERA_5) || \ + defined(GMSL_CAMERA_6) || defined(GMSL_CAMERA_7) +#define GMSL_1 +#endif + +/* Deduce the camera model compatible string. */ +#if defined(GMSL_CAMERA_RDACM20) +#define GMSL_CAMERA_MODEL "imi,rdacm20" +#elif defined(GMSL_CAMERA_RDACM21) +#define GMSL_CAMERA_MODEL "imi,rdacm21" +#endif + +#ifdef GMSL_0 +&vin0 { + status = "okay"; +}; + +&vin1 { + status = "okay"; +}; + +&vin2 { + status = "okay"; +}; + +&vin3 { + status = "okay"; +}; + +&gmsl0 { + status = "okay"; + +#if defined(GMSL_CAMERA_RDACM21) + maxim,reverse-channel-microvolt = <100000>; +#endif + + ports { +#ifdef GMSL_CAMERA_0 + port@0 { + max9286_in0: endpoint { + remote-endpoint = <&fakra_con0>; + }; + }; +#endif + +#ifdef GMSL_CAMERA_1 + port@1 { + max9286_in1: endpoint{ + remote-endpoint = <&fakra_con1>; + }; + + }; +#endif + +#ifdef GMSL_CAMERA_2 + port@2 { + max9286_in2: endpoint { + remote-endpoint = <&fakra_con2>; + }; + + }; +#endif + +#ifdef GMSL_CAMERA_3 + port@3 { + max9286_in3: endpoint { + remote-endpoint = <&fakra_con3>; + }; + + }; +#endif + }; + + i2c-mux { +#ifdef GMSL_CAMERA_0 + i2c@0 { + status = "okay"; + + camera@51 { + compatible = GMSL_CAMERA_MODEL; + reg = <0x51>, <0x61>; + + port { + fakra_con0: endpoint { + remote-endpoint = <&max9286_in0>; + }; + }; + }; + }; +#endif + +#ifdef GMSL_CAMERA_1 + i2c@1 { + status = "okay"; + + camera@52 { + compatible = GMSL_CAMERA_MODEL; + reg = <0x52>, <0x62>; + + port { + fakra_con1: endpoint { + remote-endpoint = <&max9286_in1>; + }; + }; + }; + }; +#endif + +#ifdef GMSL_CAMERA_2 + i2c@2 { + status = "okay"; + + camera@53 { + compatible = GMSL_CAMERA_MODEL; + reg = <0x53>, <0x63>; + + port { + fakra_con2: endpoint { + remote-endpoint = <&max9286_in2>; + }; + }; + }; + }; +#endif + +#ifdef GMSL_CAMERA_3 + i2c@3 { + status = "okay"; + + camera@54 { + compatible = GMSL_CAMERA_MODEL; + reg = <0x54>, <0x64>; + + port { + fakra_con3: endpoint { + remote-endpoint = <&max9286_in3>; + }; + }; + }; + }; +#endif + }; +}; +#endif /* ifdef GMSL_0 */ + +#ifdef GMSL_1 +&vin4 { + status = "okay"; +}; + +&vin5 { + status = "okay"; +}; + +&vin6 { + status = "okay"; +}; + +&vin7 { + status = "okay"; +}; + +&gmsl1 { + status = "okay"; + +#if defined(GMSL_CAMERA_RDACM21) + maxim,reverse-channel-microvolt = <100000>; +#endif + + ports { +#ifdef GMSL_CAMERA_4 + port@0 { + max9286_in4: endpoint { + remote-endpoint = <&fakra_con4>; + }; + }; +#endif + +#ifdef GMSL_CAMERA_5 + port@1 { + max9286_in5: endpoint{ + remote-endpoint = <&fakra_con5>; + }; + + }; +#endif + +#ifdef GMSL_CAMERA_6 + port@2 { + max9286_in6: endpoint { + remote-endpoint = <&fakra_con6>; + }; + + }; +#endif + +#ifdef GMSL_CAMERA_7 + port@3 { + max9286_in7: endpoint { + remote-endpoint = <&fakra_con7>; + }; + + }; +#endif + }; + + i2c-mux { +#ifdef GMSL_CAMERA_4 + i2c@0 { + status = "okay"; + + camera@55 { + compatible = GMSL_CAMERA_MODEL; + reg = <0x55>, <0x65>; + + port { + fakra_con4: endpoint { + remote-endpoint = <&max9286_in4>; + }; + }; + }; + }; +#endif + +#ifdef GMSL_CAMERA_5 + i2c@1 { + status = "okay"; + + camera@56 { + compatible = GMSL_CAMERA_MODEL; + reg = <0x56>, <0x66>; + + port { + fakra_con5: endpoint { + remote-endpoint = <&max9286_in5>; + }; + }; + }; + }; +#endif + +#ifdef GMSL_CAMERA_6 + i2c@2 { + status = "okay"; + + camera@57 { + compatible = GMSL_CAMERA_MODEL; + reg = <0x57>, <0x67>; + + port { + fakra_con6: endpoint { + remote-endpoint = <&max9286_in6>; + }; + }; + }; + }; +#endif + +#ifdef GMSL_CAMERA_7 + i2c@3 { + status = "okay"; + + camera@58 { + compatible = GMSL_CAMERA_MODEL; + reg = <0x58>, <0x68>; + + port { + fakra_con7: endpoint { + remote-endpoint = <&max9286_in7>; + }; + }; + }; + }; +#endif + }; +}; +#endif /* ifdef GMSL_1 */ -- cgit From 8b88873b8fb52237e613299837e0b97b6719a9a6 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Tue, 21 Dec 2021 14:27:22 +0900 Subject: arm64: dts: renesas: r8a779f0: Add sys-dmac nodes Add SYS-DMAC nodes for r8a779f0. Signed-off-by: Yoshihiro Shimoda Reviewed-by: Ulrich Hecht Link: https://lore.kernel.org/r/20211221052722.597407-4-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 70 +++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index eda597766eaf..5426532d10e2 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -94,6 +94,76 @@ status = "disabled"; }; + dmac0: dma-controller@e7350000 { + compatible = "renesas,dmac-r8a779f0", + "renesas,rcar-gen4-dmac"; + reg = <0 0xe7350000 0 0x1000>, + <0 0xe7300000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", "ch4", + "ch5", "ch6", "ch7", "ch8", "ch9", + "ch10", "ch11", "ch12", "ch13", + "ch14", "ch15"; + clocks = <&cpg CPG_MOD 709>; + clock-names = "fck"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 709>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + dmac1: dma-controller@e7351000 { + compatible = "renesas,dmac-r8a779f0", + "renesas,rcar-gen4-dmac"; + reg = <0 0xe7351000 0 0x1000>, + <0 0xe7310000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", "ch4", + "ch5", "ch6", "ch7", "ch8", "ch9", + "ch10", "ch11", "ch12", "ch13", + "ch14", "ch15"; + clocks = <&cpg CPG_MOD 710>; + clock-names = "fck"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 710>; + #dma-cells = <1>; + dma-channels = <16>; + }; + gic: interrupt-controller@f1000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; -- cgit From d45db61c2e569e0e95925a41bdb926913487f21a Mon Sep 17 00:00:00 2001 From: Nikita Yushchenko Date: Fri, 24 Dec 2021 08:23:08 +0300 Subject: arm64: dts: renesas: r8a77961: Add lvds0 device node Add the missing lvds0 node for the R-Car M3-W+ SoC. Signed-off-by: Nikita Yushchenko Reviewed-by: Laurent Pinchart Link: https://lore.kernel.org/r/20211224052309.1997096-3-nikita.yoush@cogentembedded.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77961.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index ac9b587f6fc5..59509e20575d 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -2722,6 +2722,33 @@ port@2 { reg = <2>; du_out_lvds0: endpoint { + remote-endpoint = <&lvds0_in>; + }; + }; + }; + }; + + lvds0: lvds@feb90000 { + compatible = "renesas,r8a77961-lvds"; + reg = <0 0xfeb90000 0 0x14>; + clocks = <&cpg CPG_MOD 727>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 727>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = <&du_out_lvds0>; + }; + }; + port@1 { + reg = <1>; + lvds0_out: endpoint { }; }; }; -- cgit From 72a2cab3a10bbfcc9cccc763834acded015d9282 Mon Sep 17 00:00:00 2001 From: Nikita Yushchenko Date: Sat, 25 Dec 2021 14:53:09 +0300 Subject: arm64: dts: renesas: ulcb-kf: Add KF HDMI output This patch adds nodes needed to enable DRM video output over the HDMI connector located on the Kingfisher board. Signed-off-by: Nikita Yushchenko Link: https://lore.kernel.org/r/20211225115308.2152364-1-nikita.yoush@cogentembedded.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 94 ++++++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi index 61bd4df09df0..222097d84783 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi @@ -26,6 +26,31 @@ select-gpios = <&gpio_exp_75 13 GPIO_ACTIVE_HIGH>; }; + hdmi1-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con: endpoint { + remote-endpoint = <&adv7513_out>; + }; + }; + }; + + hdmi_1v8: regulator-hdmi-1v8 { + compatible = "regulator-fixed"; + regulator-name = "hdmi-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + hdmi_3v3: regulator-hdmi-3v3 { + compatible = "regulator-fixed"; + regulator-name = "hdmi-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + snd_3p3v: regulator-snd_3p3v { compatible = "regulator-fixed"; regulator-name = "snd-3.3v"; @@ -65,6 +90,10 @@ status = "okay"; }; +&du_out_rgb { + remote-endpoint = <&adv7513_in>; +}; + &ehci0 { dr_mode = "otg"; status = "okay"; @@ -91,6 +120,58 @@ reg = <0x71>; reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; + /* HDMIoSDA, HDMIoSCL */ + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + + hdmi@3d { + compatible = "adi,adv7513"; + reg = <0x3d>; + + pinctrl-0 = <&hdmi1_pins>; + pinctrl-names = "default"; + + interrupt-parent = <&gpio2>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + + clocks = <&cs2000>; + clock-names = "cec"; + + pd-gpios = <&gpio_exp_75 5 GPIO_ACTIVE_LOW>; + + avdd-supply = <&hdmi_1v8>; + dvdd-supply = <&hdmi_1v8>; + pvdd-supply = <&hdmi_1v8>; + dvdd-3v-supply = <&hdmi_3v3>; + bgvdd-supply = <&hdmi_1v8>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7513_in: endpoint { + remote-endpoint = <&du_out_rgb>; + }; + }; + + port@1 { + reg = <1>; + adv7513_out: endpoint { + remote-endpoint = <&hdmi1_con>; + }; + }; + }; + }; + }; + /* Audio_SDA, Audio_SCL */ i2c@7 { #address-cells = <1>; @@ -264,6 +345,19 @@ function = "can1"; }; + hdmi1_pins: hdmi1 { + adv7513-interrupt { + pins = "GP_2_14"; + bias-pull-up; + }; + + du { + groups = "du_rgb888", "du_sync", "du_clk_out_0", + "du_disp"; + function = "du"; + }; + }; + hscif0_pins: hscif0 { groups = "hscif0_data", "hscif0_ctrl"; function = "hscif0"; -- cgit From eceb6f8677d31ae21e43bcfc4eea76a77f7982e7 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Wed, 8 Dec 2021 19:48:45 +0100 Subject: arm64: xilinx: dts: drop legacy property #stream-id-cells Property #stream-id-cells is legacy leftover and isn't currently documented nor used. Signed-off-by: David Heidelberg Link: https://lore.kernel.org/r/20211208184846.101166-1-david@ixit.cz Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 28 ---------------------------- 1 file changed, 28 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 74e66443e4ce..493719f71fb5 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -262,7 +262,6 @@ interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; - #stream-id-cells = <1>; iommus = <&smmu 0x14e8>; power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -275,7 +274,6 @@ interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; - #stream-id-cells = <1>; iommus = <&smmu 0x14e9>; power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -288,7 +286,6 @@ interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; - #stream-id-cells = <1>; iommus = <&smmu 0x14ea>; power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -301,7 +298,6 @@ interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; - #stream-id-cells = <1>; iommus = <&smmu 0x14eb>; power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -314,7 +310,6 @@ interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; - #stream-id-cells = <1>; iommus = <&smmu 0x14ec>; power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -327,7 +322,6 @@ interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; - #stream-id-cells = <1>; iommus = <&smmu 0x14ed>; power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -340,7 +334,6 @@ interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; - #stream-id-cells = <1>; iommus = <&smmu 0x14ee>; power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -353,7 +346,6 @@ interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; - #stream-id-cells = <1>; iommus = <&smmu 0x14ef>; power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -383,7 +375,6 @@ interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; - #stream-id-cells = <1>; iommus = <&smmu 0x868>; power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -396,7 +387,6 @@ interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; - #stream-id-cells = <1>; iommus = <&smmu 0x869>; power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -409,7 +399,6 @@ interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; - #stream-id-cells = <1>; iommus = <&smmu 0x86a>; power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -422,7 +411,6 @@ interrupts = <0 80 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; - #stream-id-cells = <1>; iommus = <&smmu 0x86b>; power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -435,7 +423,6 @@ interrupts = <0 81 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; - #stream-id-cells = <1>; iommus = <&smmu 0x86c>; power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -448,7 +435,6 @@ interrupts = <0 82 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; - #stream-id-cells = <1>; iommus = <&smmu 0x86d>; power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -461,7 +447,6 @@ interrupts = <0 83 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; - #stream-id-cells = <1>; iommus = <&smmu 0x86e>; power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -474,7 +459,6 @@ interrupts = <0 84 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; - #stream-id-cells = <1>; iommus = <&smmu 0x86f>; power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -495,7 +479,6 @@ interrupts = <0 14 4>; #address-cells = <1>; #size-cells = <0>; - #stream-id-cells = <1>; iommus = <&smmu 0x872>; power-domains = <&zynqmp_firmware PD_NAND>; }; @@ -509,7 +492,6 @@ clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; - #stream-id-cells = <1>; iommus = <&smmu 0x874>; power-domains = <&zynqmp_firmware PD_ETH_0>; }; @@ -523,7 +505,6 @@ clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; - #stream-id-cells = <1>; iommus = <&smmu 0x875>; power-domains = <&zynqmp_firmware PD_ETH_1>; }; @@ -537,7 +518,6 @@ clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; - #stream-id-cells = <1>; iommus = <&smmu 0x876>; power-domains = <&zynqmp_firmware PD_ETH_2>; }; @@ -551,7 +531,6 @@ clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; - #stream-id-cells = <1>; iommus = <&smmu 0x877>; power-domains = <&zynqmp_firmware PD_ETH_3>; }; @@ -621,7 +600,6 @@ <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; - #stream-id-cells = <1>; iommus = <&smmu 0x4d0>; power-domains = <&zynqmp_firmware PD_PCIE>; pcie_intc: legacy-interrupt-controller { @@ -642,7 +620,6 @@ <0x0 0xc0000000 0x0 0x8000000>; #address-cells = <1>; #size-cells = <0>; - #stream-id-cells = <1>; iommus = <&smmu 0x873>; power-domains = <&zynqmp_firmware PD_QSPI>; }; @@ -674,7 +651,6 @@ interrupts = <0 133 4>; power-domains = <&zynqmp_firmware PD_SATA>; resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; - #stream-id-cells = <4>; iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; }; @@ -686,7 +662,6 @@ interrupts = <0 48 4>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; - #stream-id-cells = <1>; iommus = <&smmu 0x870>; #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; @@ -700,7 +675,6 @@ interrupts = <0 49 4>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; - #stream-id-cells = <1>; iommus = <&smmu 0x871>; #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; @@ -825,7 +799,6 @@ interrupt-parent = <&gic>; interrupt-names = "dwc_usb3", "otg"; interrupts = <0 65 4>, <0 69 4>; - #stream-id-cells = <1>; iommus = <&smmu 0x860>; snps,quirk-frame-length-adjustment = <0x20>; /* dma-coherent; */ @@ -852,7 +825,6 @@ interrupt-parent = <&gic>; interrupt-names = "dwc_usb3", "otg"; interrupts = <0 70 4>, <0 74 4>; - #stream-id-cells = <1>; iommus = <&smmu 0x861>; snps,quirk-frame-length-adjustment = <0x20>; /* dma-coherent; */ -- cgit From 1ff2d58e60c8093e9be935b1f191341c0cda957a Mon Sep 17 00:00:00 2001 From: Michael Tretter Date: Wed, 12 Jan 2022 16:15:40 +0100 Subject: arm64: zynqmp: Add missing #dma-cells property Requesting the dma controllers fails if #dma-cells is not defined. Add the missing property. Signed-off-by: Michael Tretter Link: https://lore.kernel.org/r/20220112151541.1328732-3-m.tretter@pengutronix.de Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 493719f71fb5..6d96b6b99f84 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -261,6 +261,7 @@ interrupt-parent = <&gic>; interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14e8>; power-domains = <&zynqmp_firmware PD_GDMA>; @@ -273,6 +274,7 @@ interrupt-parent = <&gic>; interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14e9>; power-domains = <&zynqmp_firmware PD_GDMA>; @@ -285,6 +287,7 @@ interrupt-parent = <&gic>; interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14ea>; power-domains = <&zynqmp_firmware PD_GDMA>; @@ -297,6 +300,7 @@ interrupt-parent = <&gic>; interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14eb>; power-domains = <&zynqmp_firmware PD_GDMA>; @@ -309,6 +313,7 @@ interrupt-parent = <&gic>; interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14ec>; power-domains = <&zynqmp_firmware PD_GDMA>; @@ -321,6 +326,7 @@ interrupt-parent = <&gic>; interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14ed>; power-domains = <&zynqmp_firmware PD_GDMA>; @@ -333,6 +339,7 @@ interrupt-parent = <&gic>; interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14ee>; power-domains = <&zynqmp_firmware PD_GDMA>; @@ -345,6 +352,7 @@ interrupt-parent = <&gic>; interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14ef>; power-domains = <&zynqmp_firmware PD_GDMA>; @@ -374,6 +382,7 @@ interrupt-parent = <&gic>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <64>; iommus = <&smmu 0x868>; power-domains = <&zynqmp_firmware PD_ADMA>; @@ -386,6 +395,7 @@ interrupt-parent = <&gic>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <64>; iommus = <&smmu 0x869>; power-domains = <&zynqmp_firmware PD_ADMA>; @@ -398,6 +408,7 @@ interrupt-parent = <&gic>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <64>; iommus = <&smmu 0x86a>; power-domains = <&zynqmp_firmware PD_ADMA>; @@ -410,6 +421,7 @@ interrupt-parent = <&gic>; interrupts = <0 80 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <64>; iommus = <&smmu 0x86b>; power-domains = <&zynqmp_firmware PD_ADMA>; @@ -422,6 +434,7 @@ interrupt-parent = <&gic>; interrupts = <0 81 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <64>; iommus = <&smmu 0x86c>; power-domains = <&zynqmp_firmware PD_ADMA>; @@ -434,6 +447,7 @@ interrupt-parent = <&gic>; interrupts = <0 82 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <64>; iommus = <&smmu 0x86d>; power-domains = <&zynqmp_firmware PD_ADMA>; @@ -446,6 +460,7 @@ interrupt-parent = <&gic>; interrupts = <0 83 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <64>; iommus = <&smmu 0x86e>; power-domains = <&zynqmp_firmware PD_ADMA>; @@ -458,6 +473,7 @@ interrupt-parent = <&gic>; interrupts = <0 84 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <64>; iommus = <&smmu 0x86f>; power-domains = <&zynqmp_firmware PD_ADMA>; -- cgit From 3a14f0e614082821ef65de7e1fb39e74c2ee4ee3 Mon Sep 17 00:00:00 2001 From: Michael Tretter Date: Wed, 12 Jan 2022 16:15:41 +0100 Subject: arm64: zynqmp: Rename dma to dma-controller The ZynqMP dma engines are actually dma-controllers as specified by the device tree binding. Rename the device tree nodes accordingly. Signed-off-by: Michael Tretter Link: https://lore.kernel.org/r/20220112151541.1328732-4-m.tretter@pengutronix.de Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 6d96b6b99f84..3e15391e5b37 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -254,7 +254,7 @@ }; /* GDMA */ - fpd_dma_chan1: dma@fd500000 { + fpd_dma_chan1: dma-controller@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; @@ -267,7 +267,7 @@ power-domains = <&zynqmp_firmware PD_GDMA>; }; - fpd_dma_chan2: dma@fd510000 { + fpd_dma_chan2: dma-controller@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; @@ -280,7 +280,7 @@ power-domains = <&zynqmp_firmware PD_GDMA>; }; - fpd_dma_chan3: dma@fd520000 { + fpd_dma_chan3: dma-controller@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; @@ -293,7 +293,7 @@ power-domains = <&zynqmp_firmware PD_GDMA>; }; - fpd_dma_chan4: dma@fd530000 { + fpd_dma_chan4: dma-controller@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; @@ -306,7 +306,7 @@ power-domains = <&zynqmp_firmware PD_GDMA>; }; - fpd_dma_chan5: dma@fd540000 { + fpd_dma_chan5: dma-controller@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; @@ -319,7 +319,7 @@ power-domains = <&zynqmp_firmware PD_GDMA>; }; - fpd_dma_chan6: dma@fd550000 { + fpd_dma_chan6: dma-controller@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; @@ -332,7 +332,7 @@ power-domains = <&zynqmp_firmware PD_GDMA>; }; - fpd_dma_chan7: dma@fd560000 { + fpd_dma_chan7: dma-controller@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; @@ -345,7 +345,7 @@ power-domains = <&zynqmp_firmware PD_GDMA>; }; - fpd_dma_chan8: dma@fd570000 { + fpd_dma_chan8: dma-controller@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; @@ -375,7 +375,7 @@ * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access. */ - lpd_dma_chan1: dma@ffa80000 { + lpd_dma_chan1: dma-controller@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; @@ -388,7 +388,7 @@ power-domains = <&zynqmp_firmware PD_ADMA>; }; - lpd_dma_chan2: dma@ffa90000 { + lpd_dma_chan2: dma-controller@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x0 0x1000>; @@ -401,7 +401,7 @@ power-domains = <&zynqmp_firmware PD_ADMA>; }; - lpd_dma_chan3: dma@ffaa0000 { + lpd_dma_chan3: dma-controller@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x0 0x1000>; @@ -414,7 +414,7 @@ power-domains = <&zynqmp_firmware PD_ADMA>; }; - lpd_dma_chan4: dma@ffab0000 { + lpd_dma_chan4: dma-controller@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x0 0x1000>; @@ -427,7 +427,7 @@ power-domains = <&zynqmp_firmware PD_ADMA>; }; - lpd_dma_chan5: dma@ffac0000 { + lpd_dma_chan5: dma-controller@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x0 0x1000>; @@ -440,7 +440,7 @@ power-domains = <&zynqmp_firmware PD_ADMA>; }; - lpd_dma_chan6: dma@ffad0000 { + lpd_dma_chan6: dma-controller@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x0 0x1000>; @@ -453,7 +453,7 @@ power-domains = <&zynqmp_firmware PD_ADMA>; }; - lpd_dma_chan7: dma@ffae0000 { + lpd_dma_chan7: dma-controller@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x0 0x1000>; @@ -466,7 +466,7 @@ power-domains = <&zynqmp_firmware PD_ADMA>; }; - lpd_dma_chan8: dma@ffaf0000 { + lpd_dma_chan8: dma-controller@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x0 0x1000>; -- cgit From 73ba850270da49857629f63f6636db92b53c5f35 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Thu, 13 Jan 2022 14:58:18 +0800 Subject: arm64: dts: mediatek: Correct uart clock of MT8192 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When the initial devicetree for mt8192 was added in 48489980e27e ("arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile"), the clock driver for mt8192 was not yet upstream, so the clock property nodes were set to the clk26m clock as a placeholder. Given that the clock driver has since been added through 710573dee31b ("clk: mediatek: Add MT8192 basic clocks support"), as well as its dt-bindings through f35f1a23e0e1 ("clk: mediatek: Add dt-bindings of MT8192 clocks") and devicetree nodes through 5d2b897bc6f5 ("arm64: dts: mediatek: Add mt8192 clock controllers"), fix the uart clock property to point to the actual clock. Signed-off-by: Allen-KH Cheng Reviewed-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220113065822.11809-2-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 53d790c335f9..2c1926f6a49d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -327,7 +327,7 @@ "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x1000>; interrupts = ; - clocks = <&clk26m>, <&clk26m>; + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; clock-names = "baud", "bus"; status = "disabled"; }; @@ -337,7 +337,7 @@ "mediatek,mt6577-uart"; reg = <0 0x11003000 0 0x1000>; interrupts = ; - clocks = <&clk26m>, <&clk26m>; + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; clock-names = "baud", "bus"; status = "disabled"; }; -- cgit From 7f0c5b39dbb616303cfb650c6eb47a7187dd0648 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Thu, 13 Jan 2022 14:58:19 +0800 Subject: arm64: dts: mediatek: Correct SPI clock of MT8192 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When the initial devicetree for mt8192 was added in 48489980e27e ("arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile"), the clock driver for mt8192 was not yet upstream, so the clock property nodes were set to the clk26m clock as a placeholder. Given that the clock driver has since been added through 710573dee31b ("clk: mediatek: Add MT8192 basic clocks support"), as well as its dt-bindings through f35f1a23e0e1 ("clk: mediatek: Add dt-bindings of MT8192 clocks") and devicetree nodes through 5d2b897bc6f5 ("arm64: dts: mediatek: Add mt8192 clock controllers"), fix the SPI clock property to point to the actual clock. Signed-off-by: Allen-KH Cheng Reviewed-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220113065822.11809-3-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 48 ++++++++++++++++---------------- 1 file changed, 24 insertions(+), 24 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 2c1926f6a49d..017dcb55ee30 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -355,9 +355,9 @@ #size-cells = <0>; reg = <0 0x1100a000 0 0x1000>; interrupts = ; - clocks = <&clk26m>, - <&clk26m>, - <&clk26m>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI0>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; }; @@ -369,9 +369,9 @@ #size-cells = <0>; reg = <0 0x11010000 0 0x1000>; interrupts = ; - clocks = <&clk26m>, - <&clk26m>, - <&clk26m>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI1>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; }; @@ -383,9 +383,9 @@ #size-cells = <0>; reg = <0 0x11012000 0 0x1000>; interrupts = ; - clocks = <&clk26m>, - <&clk26m>, - <&clk26m>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI2>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; }; @@ -397,9 +397,9 @@ #size-cells = <0>; reg = <0 0x11013000 0 0x1000>; interrupts = ; - clocks = <&clk26m>, - <&clk26m>, - <&clk26m>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI3>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; }; @@ -411,9 +411,9 @@ #size-cells = <0>; reg = <0 0x11018000 0 0x1000>; interrupts = ; - clocks = <&clk26m>, - <&clk26m>, - <&clk26m>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI4>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; }; @@ -425,9 +425,9 @@ #size-cells = <0>; reg = <0 0x11019000 0 0x1000>; interrupts = ; - clocks = <&clk26m>, - <&clk26m>, - <&clk26m>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI5>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; }; @@ -439,9 +439,9 @@ #size-cells = <0>; reg = <0 0x1101d000 0 0x1000>; interrupts = ; - clocks = <&clk26m>, - <&clk26m>, - <&clk26m>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI6>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; }; @@ -453,9 +453,9 @@ #size-cells = <0>; reg = <0 0x1101e000 0 0x1000>; interrupts = ; - clocks = <&clk26m>, - <&clk26m>, - <&clk26m>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI7>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; }; -- cgit From aa247c07f710b3c67689ea3c0c6d27d3f7384874 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Thu, 13 Jan 2022 14:58:20 +0800 Subject: arm64: dts: mediatek: Correct Nor Flash clock of MT8192 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When the initial devicetree for mt8192 was added in 48489980e27e ("arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile"), the clock driver for mt8192 was not yet upstream, so the clock property nodes were set to the clk26m clock as a placeholder. Given that the clock driver has since been added through 710573dee31b ("clk: mediatek: Add MT8192 basic clocks support"), as well as its dt-bindings through f35f1a23e0e1 ("clk: mediatek: Add dt-bindings of MT8192 clocks") and devicetree nodes through 5d2b897bc6f5 ("arm64: dts: mediatek: Add mt8192 clock controllers"), fix the Nor Flash clock property to point to the actual clock. Signed-off-by: Allen-KH Cheng Reviewed-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220113065822.11809-4-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 017dcb55ee30..879b5a40078d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -464,10 +464,12 @@ compatible = "mediatek,mt8192-nor"; reg = <0 0x11234000 0 0xe0>; interrupts = ; - clocks = <&clk26m>, - <&clk26m>, - <&clk26m>; + clocks = <&topckgen CLK_TOP_SFLASH_SEL>, + <&infracfg CLK_INFRA_FLASHIF_SFLASH>, + <&infracfg CLK_INFRA_FLASHIF_TOP_H_133M>; clock-names = "spi", "sf", "axi"; + assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; + assigned-clock-parents = <&clk26m>; #address-cells = <1>; #size-cells = <0>; status = "disable"; -- cgit From 226231544f937e3bbb05b73c10556f17172f1a4d Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Thu, 13 Jan 2022 14:58:21 +0800 Subject: arm64: dts: mediatek: Correct I2C clock of MT8192 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When the initial devicetree for mt8192 was added in 48489980e27e ("arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile"), the clock driver for mt8192 was not yet upstream, so the clock property nodes were set to the clk26m clock as a placeholder. Given that the clock driver has since been added through 710573dee31b ("clk: mediatek: Add MT8192 basic clocks support"), as well as its dt-bindings through f35f1a23e0e1 ("clk: mediatek: Add dt-bindings of MT8192 clocks") and devicetree nodes through 5d2b897bc6f5 ("arm64: dts: mediatek: Add mt8192 clock controllers"), fix the I2C clock property to point to the actual clock. Signed-off-by: Allen-KH Cheng Reviewed-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220113065822.11809-5-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 30 ++++++++++++++++++++---------- 1 file changed, 20 insertions(+), 10 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 879b5a40078d..697fe2a272e8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -486,7 +486,8 @@ reg = <0 0x11cb0000 0 0x1000>, <0 0x10217300 0 0x80>; interrupts = ; - clocks = <&clk26m>, <&clk26m>; + clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>, + <&infracfg CLK_INFRA_AP_DMA>; clock-names = "main", "dma"; clock-div = <1>; #address-cells = <1>; @@ -505,7 +506,8 @@ reg = <0 0x11d00000 0 0x1000>, <0 0x10217600 0 0x180>; interrupts = ; - clocks = <&clk26m>, <&clk26m>; + clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, + <&infracfg CLK_INFRA_AP_DMA>; clock-names = "main", "dma"; clock-div = <1>; #address-cells = <1>; @@ -518,7 +520,8 @@ reg = <0 0x11d01000 0 0x1000>, <0 0x10217780 0 0x180>; interrupts = ; - clocks = <&clk26m>, <&clk26m>; + clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>, + <&infracfg CLK_INFRA_AP_DMA>; clock-names = "main", "dma"; clock-div = <1>; #address-cells = <1>; @@ -531,7 +534,8 @@ reg = <0 0x11d02000 0 0x1000>, <0 0x10217900 0 0x180>; interrupts = ; - clocks = <&clk26m>, <&clk26m>; + clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>, + <&infracfg CLK_INFRA_AP_DMA>; clock-names = "main", "dma"; clock-div = <1>; #address-cells = <1>; @@ -550,7 +554,8 @@ reg = <0 0x11d20000 0 0x1000>, <0 0x10217100 0 0x80>; interrupts = ; - clocks = <&clk26m>, <&clk26m>; + clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>, + <&infracfg CLK_INFRA_AP_DMA>; clock-names = "main", "dma"; clock-div = <1>; #address-cells = <1>; @@ -563,7 +568,8 @@ reg = <0 0x11d21000 0 0x1000>, <0 0x10217180 0 0x180>; interrupts = ; - clocks = <&clk26m>, <&clk26m>; + clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>, + <&infracfg CLK_INFRA_AP_DMA>; clock-names = "main", "dma"; clock-div = <1>; #address-cells = <1>; @@ -576,7 +582,8 @@ reg = <0 0x11d22000 0 0x1000>, <0 0x10217380 0 0x180>; interrupts = ; - clocks = <&clk26m>, <&clk26m>; + clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>, + <&infracfg CLK_INFRA_AP_DMA>; clock-names = "main", "dma"; clock-div = <1>; #address-cells = <1>; @@ -595,7 +602,8 @@ reg = <0 0x11e00000 0 0x1000>, <0 0x10217500 0 0x80>; interrupts = ; - clocks = <&clk26m>, <&clk26m>; + clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>, + <&infracfg CLK_INFRA_AP_DMA>; clock-names = "main", "dma"; clock-div = <1>; #address-cells = <1>; @@ -614,7 +622,8 @@ reg = <0 0x11f00000 0 0x1000>, <0 0x10217080 0 0x80>; interrupts = ; - clocks = <&clk26m>, <&clk26m>; + clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>, + <&infracfg CLK_INFRA_AP_DMA>; clock-names = "main", "dma"; clock-div = <1>; #address-cells = <1>; @@ -627,7 +636,8 @@ reg = <0 0x11f01000 0 0x1000>, <0 0x10217580 0 0x80>; interrupts = ; - clocks = <&clk26m>, <&clk26m>; + clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>, + <&infracfg CLK_INFRA_AP_DMA>; clock-names = "main", "dma"; clock-div = <1>; #address-cells = <1>; -- cgit From dde3c175187cc598ecfaedc4f98ecbaa87c832e7 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Thu, 13 Jan 2022 14:58:22 +0800 Subject: arm64: dts: mediatek: Correct system timer clock of MT8192 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When the initial devicetree for mt8192 was added in 48489980e27e ("arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile"), the clock driver for mt8192 was not yet upstream, so the clock property nodes were set to the clk26m clock as a placeholder. Given that the clock driver has since been added through 710573dee31b ("clk: mediatek: Add MT8192 basic clocks support"), as well as its dt-bindings through f35f1a23e0e1 ("clk: mediatek: Add dt-bindings of MT8192 clocks") and devicetree nodes through 5d2b897bc6f5 ("arm64: dts: mediatek: Add mt8192 clock controllers"), fix the systimer clock property to point to the actual clock. Signed-off-by: Allen-KH Cheng Reviewed-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220113065822.11809-6-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 697fe2a272e8..cc3953df0153 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -312,7 +312,7 @@ "mediatek,mt6765-timer"; reg = <0 0x10017000 0 0x1000>; interrupts = ; - clocks = <&clk26m>; + clocks = <&topckgen CLK_TOP_CSW_F26M_D2>; clock-names = "clk13m"; }; -- cgit From 31c33503fdb3965d6aaf0db4a8c42e7d8cef1dff Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 23 Jan 2022 12:16:33 +0100 Subject: arm64: dts: exynos: add USB DWC3 supplies to Espresso board Add required voltage regulators for USB DWC3 block on Exynos7 Espresso board. Due to lack of schematics of Espresso board, the choice of regulators is approximate. What bindings call VDD10, for Exynos7 should be actually called VDD09 (0.9 V). Use regulators with a matching voltage range based on vendor sources for Meizu Pro 5 M576 handset (also with Exynos7420). Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220123111644.25540-2-krzysztof.kozlowski@canonical.com --- arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 5 +++++ arch/arm64/boot/dts/exynos/exynos7.dtsi | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts index 125c03f351d9..4c45e689d34a 100644 --- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts +++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts @@ -412,6 +412,11 @@ status = "okay"; }; +&usbdrd { + vdd10-supply = <&ldo4_reg>; + vdd33-supply = <&ldo6_reg>; +}; + &usbdrd_phy { vbus-supply = <&usb30_vbus_reg>; vbus-boost-supply = <&usb3drd_boost_5v>; diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index 3e53ff2be455..960823b8247a 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -693,7 +693,7 @@ #phy-cells = <1>; }; - usbdrd3 { + usbdrd: usb { compatible = "samsung,exynos7-dwusb3"; clocks = <&clock_fsys0 ACLK_USBDRD300>, <&clock_fsys0 SCLK_USBDRD300_SUSPENDCLK>, -- cgit From 1ff6797c326b4fd3cc011095d96cec7194a85ea9 Mon Sep 17 00:00:00 2001 From: Balakrishna Godavarthi Date: Wed, 15 Dec 2021 22:36:03 +0530 Subject: arm64: dts: qcom: sc7280: Add bluetooth node on SC7280 IDP boards Add bluetooth SoC WCN6750 node for SC7280 IDP boards. Signed-off-by: Balakrishna Godavarthi Reviewed-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1639587963-22503-1-git-send-email-bgodavar@codeaurora.org --- arch/arm64/boot/dts/qcom/sc7280-idp.dts | 4 ++++ arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 36 ++++++++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7280-idp2.dts | 4 ++++ 3 files changed, 44 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts index 9b991ba5daaf..19bd228760ed 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts @@ -56,6 +56,10 @@ }; }; +&bluetooth { + vddio-supply = <&vreg_l19b_1p8>; +}; + &ipa { status = "okay"; modem-init; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index d623d71d8bd4..a146d0ddad0f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -14,6 +14,11 @@ #include "pmk8350.dtsi" / { + aliases { + bluetooth0 = &bluetooth; + serial1 = &uart7; + }; + gpio-keys { compatible = "gpio-keys"; label = "gpio-keys"; @@ -422,6 +427,23 @@ <&tlmm 31 IRQ_TYPE_EDGE_FALLING>; pinctrl-names = "default", "sleep"; pinctrl-1 = <&qup_uart7_sleep_cts>, <&qup_uart7_sleep_rts>, <&qup_uart7_sleep_tx>, <&qup_uart7_sleep_rx>; + + bluetooth: bluetooth { + compatible = "qcom,wcn6750-bt"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_en>, <&sw_ctrl>; + enable-gpios = <&tlmm 85 GPIO_ACTIVE_HIGH>; + swctrl-gpios = <&tlmm 86 GPIO_ACTIVE_HIGH>; + vddaon-supply = <&vreg_s7b_0p9>; + vddbtcxmx-supply = <&vreg_s7b_0p9>; + vddrfacmn-supply = <&vreg_s7b_0p9>; + vddrfa0p8-supply = <&vreg_s7b_0p9>; + vddrfa1p7-supply = <&vreg_s1b_1p8>; + vddrfa1p2-supply = <&vreg_s8b_1p2>; + vddrfa2p2-supply = <&vreg_s1c_2p2>; + vddasd-supply = <&vreg_l11c_2p8>; + max-speed = <3200000>; + }; }; /* PINCTRL - additions to nodes defined in sc7280.dtsi */ @@ -491,6 +513,13 @@ }; &tlmm { + bt_en: bt-en { + pins = "gpio85"; + function = "gpio"; + output-low; + bias-disable; + }; + nvme_pwren: nvme-pwren { function = "gpio"; }; @@ -554,6 +583,13 @@ */ bias-pull-up; }; + + sw_ctrl: sw-ctrl { + pins = "gpio86"; + function = "gpio"; + input-enable; + bias-pull-down; + }; }; &sdc1_on { diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp2.dts b/arch/arm64/boot/dts/qcom/sc7280-idp2.dts index 0382c770650a..73b9911dd802 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp2.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp2.dts @@ -23,6 +23,10 @@ }; }; +&bluetooth { + vddio-supply = <&vreg_l18b_1p8>; +}; + &nvme_pwren { pins = "gpio51"; }; -- cgit From 87f7409da95ef287255d5abf0f6eddb5ada72713 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Fri, 24 Dec 2021 17:31:07 +0100 Subject: arm64: dts: qcom: msm8996: use standartized naming for spmi node Following naming convention, rename qcom,spmi@ node to spmi@ Signed-off-by: David Heidelberg Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211224163107.53708-1-david@ixit.cz --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 91bc974aeb0a..2c9c21287beb 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1546,7 +1546,7 @@ reg = <0x00290000 0x10000>; }; - spmi_bus: qcom,spmi@400f000 { + spmi_bus: spmi@400f000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x0400f000 0x1000>, <0x04400000 0x800000>, -- cgit From 073a39a2a63abd46339a50eb07bd23958d99efbe Mon Sep 17 00:00:00 2001 From: Satya Priya Date: Tue, 23 Nov 2021 17:19:27 +0530 Subject: arm64: dts: qcom: sc7280: Add pmg1110 regulators for sc7280-crd Add pmg1110 pmic regulators support. Signed-off-by: Satya Priya Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1637668167-31325-4-git-send-email-quic_c_skakit@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280-crd.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sc7280-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-crd.dts index cd2755ce530d..e2efbdde53a3 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-crd.dts @@ -23,6 +23,18 @@ }; }; +&apps_rsc { + pmg1110-regulators { + compatible = "qcom,pmg1110-rpmh-regulators"; + qcom,pmic-id = "k"; + + vreg_s1k_1p0: smps1 { + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + }; + }; +}; + ap_tp_i2c: &i2c0 { status = "okay"; clock-frequency = <400000>; -- cgit From 18b1db6a162c29695920fdf212ccb8d7d5c07e9a Mon Sep 17 00:00:00 2001 From: Alim Akhtar Date: Mon, 24 Jan 2022 19:46:42 +0530 Subject: arm64: dts: fsd: Add initial device tree support Add initial device tree support for "Full Self-Driving" (FSD) SoC This SoC contain three clusters of four cortex-a72 CPUs and various peripheral IPs. Cc: linux-fsd@tesla.com Reviewed-by: Krzysztof Kozlowski Signed-off-by: Arjun K V Signed-off-by: Aswani Reddy Signed-off-by: Ajay Kumar Signed-off-by: Sriranjani P Signed-off-by: Chandrasekar R Signed-off-by: Shashank Prashar Signed-off-by: Alim Akhtar Link: https://lore.kernel.org/r/20220124141644.71052-15-alim.akhtar@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/tesla/Makefile | 3 + arch/arm64/boot/dts/tesla/fsd-evb.dts | 39 ++ arch/arm64/boot/dts/tesla/fsd.dtsi | 652 ++++++++++++++++++++++++++++++++++ 4 files changed, 695 insertions(+) create mode 100644 arch/arm64/boot/dts/tesla/Makefile create mode 100644 arch/arm64/boot/dts/tesla/fsd-evb.dts create mode 100644 arch/arm64/boot/dts/tesla/fsd.dtsi (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 639e01a4d855..1ba04e31a438 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -27,6 +27,7 @@ subdir-y += rockchip subdir-y += socionext subdir-y += sprd subdir-y += synaptics +subdir-y += tesla subdir-y += ti subdir-y += toshiba subdir-y += xilinx diff --git a/arch/arm64/boot/dts/tesla/Makefile b/arch/arm64/boot/dts/tesla/Makefile new file mode 100644 index 000000000000..a1ee50e2fd06 --- /dev/null +++ b/arch/arm64/boot/dts/tesla/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_TESLA_FSD) += \ + fsd-evb.dtb diff --git a/arch/arm64/boot/dts/tesla/fsd-evb.dts b/arch/arm64/boot/dts/tesla/fsd-evb.dts new file mode 100644 index 000000000000..5af560c1b5e6 --- /dev/null +++ b/arch/arm64/boot/dts/tesla/fsd-evb.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Tesla FSD board device tree source + * + * Copyright (c) 2017-2021 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2017-2021 Tesla, Inc. + * https://www.tesla.com + */ + +/dts-v1/; +#include "fsd.dtsi" + +/ { + model = "Tesla Full Self-Driving (FSD) Evaluation board"; + compatible = "tesla,fsd-evb", "tesla,fsd"; + + aliases { + serial0 = &serial_0; + serial1 = &serial_1; + }; + + chosen { + stdout-path = &serial_0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x2 0x00000000>; + }; +}; + +&fin_pll { + clock-frequency = <24000000>; +}; + +&serial_0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi new file mode 100644 index 000000000000..25b480147541 --- /dev/null +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -0,0 +1,652 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Tesla Full Self-Driving SoC device tree source + * + * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2017-2022 Tesla, Inc. + * https://www.tesla.com + */ + +#include +#include + +/ { + compatible = "tesla,fsd"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + i2c0 = &hsi2c_0; + i2c1 = &hsi2c_1; + i2c2 = &hsi2c_2; + i2c3 = &hsi2c_3; + i2c4 = &hsi2c_4; + i2c5 = &hsi2c_5; + i2c6 = &hsi2c_6; + i2c7 = &hsi2c_7; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpucl0_0>; + }; + core1 { + cpu = <&cpucl0_1>; + }; + core2 { + cpu = <&cpucl0_2>; + }; + core3 { + cpu = <&cpucl0_3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpucl1_0>; + }; + core1 { + cpu = <&cpucl1_1>; + }; + core2 { + cpu = <&cpucl1_2>; + }; + core3 { + cpu = <&cpucl1_3>; + }; + }; + + cluster2 { + core0 { + cpu = <&cpucl2_0>; + }; + core1 { + cpu = <&cpucl2_1>; + }; + core2 { + cpu = <&cpucl2_2>; + }; + core3 { + cpu = <&cpucl2_3>; + }; + }; + }; + + /* Cluster 0 */ + cpucl0_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x000>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + cpucl0_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x001>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + cpucl0_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x002>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + cpucl0_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x003>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP>; + }; + + /* Cluster 1 */ + cpucl1_0: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x100>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + cpucl1_1: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x101>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + cpucl1_2: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x102>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + cpucl1_3: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x103>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + /* Cluster 2 */ + cpucl2_0: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x200>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + cpucl2_1: cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x201>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + cpucl2_2: cpu@202 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x202>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + cpucl2_3: cpu@203 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x203>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep { + idle-state-name = "c2"; + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <30>; + exit-latency-us = <75>; + min-residency-us = <300>; + }; + }; + }; + + arm-pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-affinity = <&cpucl0_0>, <&cpucl0_1>, <&cpucl0_2>, + <&cpucl0_3>, <&cpucl1_0>, <&cpucl1_1>, + <&cpucl1_2>, <&cpucl1_3>, <&cpucl2_0>, + <&cpucl2_1>, <&cpucl2_2>, <&cpucl2_3>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + fin_pll: clock { + compatible = "fixed-clock"; + clock-output-names = "fin_pll"; + #clock-cells = <0>; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x0 0x0 0x18000000>; + dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; + + gic: interrupt-controller@10400000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x10400000 0x0 0x10000>, /* GICD */ + <0x0 0x10600000 0x0 0x200000>; /* GICR_RD+GICR_SGI */ + interrupts = ; + }; + + smmu_imem: iommu@10200000 { + compatible = "arm,mmu-500"; + reg = <0x0 0x10200000 0x0 0x10000>; + #iommu-cells = <2>; + #global-interrupts = <7>; + interrupts = , /* Global secure fault */ + , /* Global non-secure fault */ + , /* Combined secure interrupt */ + , /* Combined non-secure interrupt */ + /* Performance counter interrupts */ + , /* for FSYS1_0 */ + , /* for FSYS1_1 */ + , /* for IMEM_0 */ + /* Per context non-secure context interrupts, 0-3 interrupts */ + , /* for CONTEXT_0 */ + , /* for CONTEXT_1 */ + , /* for CONTEXT_2 */ + ; /* for CONTEXT_3 */ + }; + + smmu_isp: iommu@12100000 { + compatible = "arm,mmu-500"; + reg = <0x0 0x12100000 0x0 0x10000>; + #iommu-cells = <2>; + #global-interrupts = <11>; + interrupts = , /* Global secure fault */ + , /* Global non-secure fault */ + , /* Combined secure interrupt */ + , /* Combined non-secure interrupt */ + /* Performance counter interrupts */ + , /* for CAM_CSI */ + , /* for CAM_DP_0 */ + , /* for CAM_DP_1 */ + , /* for CAM_ISP_0 */ + , /* for CAM_ISP_1 */ + , /* for CAM_MFC_0 */ + , /* for CAM_MFC_1 */ + /* Per context non-secure context interrupts, 0-7 interrupts */ + , /* for CONTEXT_0 */ + , /* for CONTEXT_1 */ + , /* for CONTEXT_2 */ + , /* for CONTEXT_3 */ + , /* for CONTEXT_4 */ + , /* for CONTEXT_5 */ + , /* for CONTEXT_6 */ + ; /* for CONTEXT_7 */ + }; + + smmu_peric: iommu@14900000 { + compatible = "arm,mmu-500"; + reg = <0x0 0x14900000 0x0 0x10000>; + #iommu-cells = <2>; + #global-interrupts = <5>; + interrupts = , /* Global secure fault */ + , /* Global non-secure fault */ + , /* Combined secure interrupt */ + , /* Combined non-secure interrupt */ + /* Performance counter interrupts */ + , /* for PERIC */ + /* Per context non-secure context interrupts, 0-1 interrupts */ + , /* for CONTEXT_0 */ + ; /* for CONTEXT_1 */ + }; + + smmu_fsys0: iommu@15450000 { + compatible = "arm,mmu-500"; + reg = <0x0 0x15450000 0x0 0x10000>; + #iommu-cells = <2>; + #global-interrupts = <5>; + interrupts = , /* Global secure fault */ + , /* Global non-secure fault */ + , /* Combined secure interrupt */ + , /* Combined non-secure interrupt */ + /* Performance counter interrupts */ + , /* for FSYS0 */ + /* Per context non-secure context interrupts, 0-1 interrupts */ + , /* for CONTEXT_0 */ + ; /* for CONTEXT_1 */ + }; + + clock_imem: clock-controller@10010000 { + compatible = "tesla,fsd-clock-imem"; + reg = <0x0 0x10010000 0x0 0x3000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_cmu DOUT_CMU_IMEM_TCUCLK>, + <&clock_cmu DOUT_CMU_IMEM_ACLK>, + <&clock_cmu DOUT_CMU_IMEM_DMACLK>; + clock-names = "fin_pll", + "dout_cmu_imem_tcuclk", + "dout_cmu_imem_aclk", + "dout_cmu_imem_dmaclk"; + }; + + clock_cmu: clock-controller@11c10000 { + compatible = "tesla,fsd-clock-cmu"; + reg = <0x0 0x11c10000 0x0 0x3000>; + #clock-cells = <1>; + clocks = <&fin_pll>; + clock-names = "fin_pll"; + }; + + clock_csi: clock-controller@12610000 { + compatible = "tesla,fsd-clock-cam_csi"; + reg = <0x0 0x12610000 0x0 0x3000>; + #clock-cells = <1>; + clocks = <&fin_pll>; + clock-names = "fin_pll"; + }; + + clock_mfc: clock-controller@12810000 { + compatible = "tesla,fsd-clock-mfc"; + reg = <0x0 0x12810000 0x0 0x3000>; + #clock-cells = <1>; + clocks = <&fin_pll>; + clock-names = "fin_pll"; + }; + + clock_peric: clock-controller@14010000 { + compatible = "tesla,fsd-clock-peric"; + reg = <0x0 0x14010000 0x0 0x3000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_cmu DOUT_CMU_PLL_SHARED0_DIV4>, + <&clock_cmu DOUT_CMU_PERIC_SHARED1DIV36>, + <&clock_cmu DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK>, + <&clock_cmu DOUT_CMU_PERIC_SHARED0DIV20>, + <&clock_cmu DOUT_CMU_PERIC_SHARED1DIV4_DMACLK>; + clock-names = "fin_pll", + "dout_cmu_pll_shared0_div4", + "dout_cmu_peric_shared1div36", + "dout_cmu_peric_shared0div3_tbuclk", + "dout_cmu_peric_shared0div20", + "dout_cmu_peric_shared1div4_dmaclk"; + }; + + clock_fsys0: clock-controller@15010000 { + compatible = "tesla,fsd-clock-fsys0"; + reg = <0x0 0x15010000 0x0 0x3000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_cmu DOUT_CMU_PLL_SHARED0_DIV6>, + <&clock_cmu DOUT_CMU_FSYS0_SHARED1DIV4>, + <&clock_cmu DOUT_CMU_FSYS0_SHARED0DIV4>; + clock-names = "fin_pll", + "dout_cmu_pll_shared0_div6", + "dout_cmu_fsys0_shared1div4", + "dout_cmu_fsys0_shared0div4"; + }; + + clock_fsys1: clock-controller@16810000 { + compatible = "tesla,fsd-clock-fsys1"; + reg = <0x0 0x16810000 0x0 0x3000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV8>, + <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV4>; + clock-names = "fin_pll", + "dout_cmu_fsys1_shared0div8", + "dout_cmu_fsys1_shared0div4"; + }; + + mdma0: dma-controller@10100000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0x10100000 0x0 0x1000>; + interrupts = ; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + clocks = <&clock_imem IMEM_DMA0_IPCLKPORT_ACLK>; + clock-names = "apb_pclk"; + iommus = <&smmu_imem 0x800 0x0>; + }; + + mdma1: dma-controller@10110000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0x10110000 0x0 0x1000>; + interrupts = ; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + clocks = <&clock_imem IMEM_DMA1_IPCLKPORT_ACLK>; + clock-names = "apb_pclk"; + iommus = <&smmu_imem 0x801 0x0>; + }; + + pdma0: dma-controller@14280000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0x14280000 0x0 0x1000>; + interrupts = ; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + clocks = <&clock_peric PERIC_DMA0_IPCLKPORT_ACLK>; + clock-names = "apb_pclk"; + iommus = <&smmu_peric 0x2 0x0>; + }; + + pdma1: dma-controller@14290000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0x14290000 0x0 0x1000>; + interrupts = ; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + clocks = <&clock_peric PERIC_DMA1_IPCLKPORT_ACLK>; + clock-names = "apb_pclk"; + iommus = <&smmu_peric 0x1 0x0>; + }; + + serial_0: serial@14180000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x0 0x14180000 0x0 0x100>; + interrupts = ; + dmas = <&pdma1 1>, <&pdma1 0>; + dma-names = "rx", "tx"; + clocks = <&clock_peric PERIC_PCLK_UART0>, + <&clock_peric PERIC_SCLK_UART0>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + serial_1: serial@14190000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x0 0x14190000 0x0 0x100>; + interrupts = ; + dmas = <&pdma1 3>, <&pdma1 2>; + dma-names = "rx", "tx"; + clocks = <&clock_peric PERIC_PCLK_UART1>, + <&clock_peric PERIC_SCLK_UART1>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + pmu_system_controller: system-controller@11400000 { + compatible = "samsung,exynos7-pmu", "syscon"; + reg = <0x0 0x11400000 0x0 0x5000>; + }; + + watchdog_0: watchdog@100a0000 { + compatible = "samsung,exynos7-wdt"; + reg = <0x0 0x100a0000 0x0 0x100>; + interrupts = ; + samsung,syscon-phandle = <&pmu_system_controller>; + clocks = <&fin_pll>; + clock-names = "watchdog"; + }; + + watchdog_1: watchdog@100b0000 { + compatible = "samsung,exynos7-wdt"; + reg = <0x0 0x100b0000 0x0 0x100>; + interrupts = ; + samsung,syscon-phandle = <&pmu_system_controller>; + clocks = <&fin_pll>; + clock-names = "watchdog"; + }; + + watchdog_2: watchdog@100c0000 { + compatible = "samsung,exynos7-wdt"; + reg = <0x0 0x100c0000 0x0 0x100>; + interrupts = ; + samsung,syscon-phandle = <&pmu_system_controller>; + clocks = <&fin_pll>; + clock-names = "watchdog"; + }; + + pwm_0: pwm@14100000 { + compatible = "samsung,exynos4210-pwm"; + reg = <0x0 0x14100000 0x0 0x100>; + samsung,pwm-outputs = <0>, <1>, <2>, <3>; + #pwm-cells = <3>; + clocks = <&clock_peric PERIC_PWM0_IPCLKPORT_I_PCLK_S0>; + clock-names = "timers"; + status = "disabled"; + }; + + pwm_1: pwm@14110000 { + compatible = "samsung,exynos4210-pwm"; + reg = <0x0 0x14110000 0x0 0x100>; + samsung,pwm-outputs = <0>, <1>, <2>, <3>; + #pwm-cells = <3>; + clocks = <&clock_peric PERIC_PWM1_IPCLKPORT_I_PCLK_S0>; + clock-names = "timers"; + status = "disabled"; + }; + + hsi2c_0: i2c@14200000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x0 0x14200000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c0_bus>; + clocks = <&clock_peric PERIC_PCLK_HSI2C0>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_1: i2c@14210000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x0 0x14210000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c1_bus>; + clocks = <&clock_peric PERIC_PCLK_HSI2C1>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_2: i2c@14220000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x0 0x14220000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c2_bus>; + clocks = <&clock_peric PERIC_PCLK_HSI2C2>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_3: i2c@14230000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x0 0x14230000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c3_bus>; + clocks = <&clock_peric PERIC_PCLK_HSI2C3>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_4: i2c@14240000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x0 0x14240000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c4_bus>; + clocks = <&clock_peric PERIC_PCLK_HSI2C4>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_5: i2c@14250000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x0 0x14250000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c5_bus>; + clocks = <&clock_peric PERIC_PCLK_HSI2C5>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_6: i2c@14260000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x0 0x14260000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c6_bus>; + clocks = <&clock_peric PERIC_PCLK_HSI2C6>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_7: i2c@14270000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x0 0x14270000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c7_bus>; + clocks = <&clock_peric PERIC_PCLK_HSI2C7>; + clock-names = "hsi2c"; + status = "disabled"; + }; + }; +}; -- cgit From 684dac402f212d8ededbe7d97bc42a5e49533f40 Mon Sep 17 00:00:00 2001 From: Alim Akhtar Date: Mon, 24 Jan 2022 19:46:43 +0530 Subject: arm64: dts: fsd: Add initial pinctrl support Add initial pin configuration nodes for FSD SoC. Cc: linux-fsd@tesla.com Signed-off-by: Shashank Prashar Signed-off-by: Aswani Reddy Signed-off-by: Alim Akhtar Link: https://lore.kernel.org/r/20220124141644.71052-16-alim.akhtar@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 335 +++++++++++++++++++++++++++++ arch/arm64/boot/dts/tesla/fsd.dtsi | 22 ++ 2 files changed, 357 insertions(+) create mode 100644 arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi new file mode 100644 index 000000000000..d4d0cb005712 --- /dev/null +++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi @@ -0,0 +1,335 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Tesla Full Self-Driving SoC device tree source + * + * Copyright (c) 2017-2021 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2017-2021 Tesla, Inc. + * https://www.tesla.com + */ + +#include + +&pinctrl_fsys0 { + gpf0: gpf0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf6: gpf6-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf4: gpf4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf5: gpf5-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&pinctrl_peric { + gpc8: gpc8-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf2: gpf2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf3: gpf3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd0: gpd0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb0: gpb0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb1: gpb1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb4: gpb4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb5: gpb5-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb6: gpb6-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb7: gpb7-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd2: gpd2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd3: gpd3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg0: gpg0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg1: gpg1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg2: gpg2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg3: gpg3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg4: gpg4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg5: gpg5-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg6: gpg6-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg7: gpg7-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pwm0_out: pwm0-out-pins { + samsung,pins = "gpb6-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm1_out: pwm1-out-pins { + samsung,pins = "gpb6-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hs_i2c0_bus: hs-i2c0-bus-pins { + samsung,pins = "gpb0-0", "gpb0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hs_i2c1_bus: hs-i2c1-bus-pins { + samsung,pins = "gpb0-2", "gpb0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hs_i2c2_bus: hs-i2c2-bus-pins { + samsung,pins = "gpb0-4", "gpb0-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hs_i2c3_bus: hs-i2c3-bus-pins { + samsung,pins = "gpb0-6", "gpb0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hs_i2c4_bus: hs-i2c4-bus-pins { + samsung,pins = "gpb1-0", "gpb1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hs_i2c5_bus: hs-i2c5-bus-pins { + samsung,pins = "gpb1-2", "gpb1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hs_i2c6_bus: hs-i2c6-bus-pins { + samsung,pins = "gpb1-4", "gpb1-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hs_i2c7_bus: hs-i2c7-bus-pins { + samsung,pins = "gpb1-6", "gpb1-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart0_data: uart0-data-pins { + samsung,pins = "gpb7-0", "gpb7-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart1_data: uart1-data-pins { + samsung,pins = "gpb7-4", "gpb7-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi0_bus: spi0-bus-pins { + samsung,pins = "gpb4-0", "gpb4-2", "gpb4-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi1_bus: spi1-bus-pins { + samsung,pins = "gpb4-4", "gpb4-6", "gpb4-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi2_bus: spi2-bus-pins { + samsung,pins = "gpb5-0", "gpb5-2", "gpb5-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_pmu { + gpq0: gpq0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; +}; diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi index 25b480147541..b7f05f78c601 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -26,6 +26,9 @@ i2c5 = &hsi2c_5; i2c6 = &hsi2c_6; i2c7 = &hsi2c_7; + pinctrl0 = &pinctrl_fsys0; + pinctrl1 = &pinctrl_peric; + pinctrl2 = &pinctrl_pmu; }; cpus { @@ -648,5 +651,24 @@ clock-names = "hsi2c"; status = "disabled"; }; + + pinctrl_pmu: pinctrl@114f0000 { + compatible = "tesla,fsd-pinctrl"; + reg = <0x0 0x114f0000 0x0 0x1000>; + }; + + pinctrl_peric: pinctrl@141f0000 { + compatible = "tesla,fsd-pinctrl"; + reg = <0x0 0x141f0000 0x0 0x1000>; + interrupts = ; + }; + + pinctrl_fsys0: pinctrl@15020000 { + compatible = "tesla,fsd-pinctrl"; + reg = <0x0 0x15020000 0x0 0x1000>; + interrupts = ; + }; }; }; + +#include "fsd-pinctrl.dtsi" -- cgit From c705c871106e35221f486765fcc3d978a4434c38 Mon Sep 17 00:00:00 2001 From: Nikita Yushchenko Date: Wed, 12 Jan 2022 23:52:05 +0300 Subject: arm64: dts: renesas: ulcb-kf: Add 9-asix sensor device This adds nodes for the lsm9ds0 sensor installed on the KF board. With this patch, the sensor data becomes available over the IIO sysfs interface. The interrupt definition is not added yet, because the interrupt lines of lsm9ds0 are pulled to VCC on the board, which implies a need for active-low configuration. But the st_sensors drivers currently can't work with active-low interrupts on this chip. Signed-off-by: Nikita Yushchenko Link: https://lore.kernel.org/r/20220112205205.4082026-1-nikita.yoush@cogentembedded.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi index 222097d84783..30f185547012 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi @@ -37,6 +37,13 @@ }; }; + accel_3v3: regulator-acc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "accel-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + hdmi_1v8: regulator-hdmi-1v8 { compatible = "regulator-fixed"; regulator-name = "hdmi-1v8"; @@ -178,6 +185,14 @@ #size-cells = <0>; reg = <7>; + accelerometer@1d { + compatible = "st,lsm9ds0-imu"; + reg = <0x1d>; + + vdd-supply = <&accel_3v3>; + vddio-supply = <&accel_3v3>; + }; + pcm3168a: audio-codec@44 { #sound-dai-cells = <0>; compatible = "ti,pcm3168a"; @@ -212,6 +227,14 @@ }; }; }; + + gyroscope@6b { + compatible = "st,lsm9ds0-gyro"; + reg = <0x6b>; + + vdd-supply = <&accel_3v3>; + vddio-supply = <&accel_3v3>; + }; }; }; -- cgit From 283252132cb578cffe761380056caf0aa6a9cf25 Mon Sep 17 00:00:00 2001 From: Niklas Söderlund Date: Thu, 13 Jan 2022 17:32:39 +0100 Subject: arm64: dts: renesas: falcon-csi-dsi: Add and connect MAX96712 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The sub-board contains three MAX96712 connected to the main-board using I2C and CSI-2, record the connections. Also enable all nodes (VIN, CSI-2 and ISP) that are part of the downstream video capture pipeline. Signed-off-by: Niklas Söderlund Link: https://lore.kernel.org/r/20220113163239.3035073-1-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi | 229 +++++++++++++++++++++ 1 file changed, 229 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi index f791c76f1bcf..e06b8eda85e1 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi @@ -5,6 +5,63 @@ * Copyright (C) 2021 Glider bv */ +&csi40 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csi40_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&max96712_out0>; + }; + }; + }; +}; + +&csi42 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csi42_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&max96712_out1>; + }; + }; + }; +}; + +&csi43 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csi43_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&max96712_out2>; + }; + }; + }; +}; + &i2c0 { pca9654_a: gpio@21 { compatible = "onnn,pca9654"; @@ -34,3 +91,175 @@ pagesize = <8>; }; }; + +&i2c1 { + gmsl0: gmsl-deserializer@49 { + compatible = "maxim,max96712"; + reg = <0x49>; + enable-gpios = <&pca9654_a 0 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + max96712_out0: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&csi40_in>; + }; + }; + }; + }; + + gmsl1: gmsl-deserializer@4b { + compatible = "maxim,max96712"; + reg = <0x4b>; + enable-gpios = <&pca9654_b 0 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + max96712_out1: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + lane-polarities = <0 0 0 0 1>; + remote-endpoint = <&csi42_in>; + }; + }; + }; + }; + + gmsl2: gmsl-deserializer@6b { + compatible = "maxim,max96712"; + reg = <0x6b>; + enable-gpios = <&pca9654_c 0 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + max96712_out2: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + lane-polarities = <0 0 0 0 1>; + remote-endpoint = <&csi43_in>; + }; + }; + }; + }; +}; + +&isp0 { + status = "okay"; +}; + +&isp2 { + status = "okay"; +}; + +&isp3 { + status = "okay"; +}; + +&vin00 { + status = "okay"; +}; + +&vin01 { + status = "okay"; +}; + +&vin02 { + status = "okay"; +}; + +&vin03 { + status = "okay"; +}; + +&vin04 { + status = "okay"; +}; + +&vin05 { + status = "okay"; +}; + +&vin06 { + status = "okay"; +}; + +&vin07 { + status = "okay"; +}; + +&vin16 { + status = "okay"; +}; + +&vin17 { + status = "okay"; +}; + +&vin18 { + status = "okay"; +}; + +&vin19 { + status = "okay"; +}; + +&vin20 { + status = "okay"; +}; + +&vin21 { + status = "okay"; +}; + +&vin22 { + status = "okay"; +}; + +&vin23 { + status = "okay"; +}; + +&vin24 { + status = "okay"; +}; + +&vin25 { + status = "okay"; +}; + +&vin26 { + status = "okay"; +}; + +&vin27 { + status = "okay"; +}; + +&vin28 { + status = "okay"; +}; + +&vin29 { + status = "okay"; +}; + +&vin30 { + status = "okay"; +}; + +&vin31 { + status = "okay"; +}; -- cgit From 953b392aef3504dbd7cacab11bceca43e59d2f62 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 18 Jan 2022 17:48:31 +0100 Subject: arm64: dts: renesas: Miscellaneous whitespace fixes Make whitespace and indentation more consistent. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/3f2bcae1253c7a31d3eb6755185092a1f2b99b09.1642524439.git.geert+renesas@glider.be --- .../boot/dts/renesas/beacon-renesom-baseboard.dtsi | 9 ++++----- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 14 +++++++------- .../boot/dts/renesas/r8a774b1-beacon-rzg2n-kit.dts | 2 +- arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 4 ++-- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 10 +++++----- .../boot/dts/renesas/r8a774e1-beacon-rzg2h-kit.dts | 2 +- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 4 ++-- arch/arm64/boot/dts/renesas/r8a77951.dtsi | 14 +++++++------- arch/arm64/boot/dts/renesas/r8a77960.dtsi | 14 +++++++------- arch/arm64/boot/dts/renesas/r8a77961.dtsi | 4 ++-- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 14 +++++++------- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 12 ++++++------ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 12 ++++++------ arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 20 ++++++++++---------- 14 files changed, 67 insertions(+), 68 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi index 2692cc64bff6..5ad6cd1864c1 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi @@ -359,11 +359,10 @@ clocks = <&x304_clk>; clock-names = "xin"; - assigned-clocks = <&versaclock6_bb 1>, - <&versaclock6_bb 2>, - <&versaclock6_bb 3>, - <&versaclock6_bb 4>; - assigned-clock-rates = <24000000>, <24000000>, <24000000>, <24576000>; + assigned-clocks = <&versaclock6_bb 1>, <&versaclock6_bb 2>, + <&versaclock6_bb 3>, <&versaclock6_bb 4>; + assigned-clock-rates = <24000000>, <24000000>, <24000000>, + <24576000>; OUT1 { idt,mode = ; diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index eda6a840371a..12846125a4c9 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -1698,12 +1698,12 @@ * clkout : #clock-cells = <0>; <&rcar_sound>; * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; */ - compatible = "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ + compatible = "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; clocks = <&cpg CPG_MOD 1005>, @@ -2010,7 +2010,7 @@ dma-names = "rx", "tx"; }; ssiu40: ssiu-32 { - dmas = <&audma0 0x71>, <&audma1 0x72>; + dmas = <&audma0 0x71>, <&audma1 0x72>; dma-names = "rx", "tx"; }; ssiu41: ssiu-33 { diff --git a/arch/arm64/boot/dts/renesas/r8a774b1-beacon-rzg2n-kit.dts b/arch/arm64/boot/dts/renesas/r8a774b1-beacon-rzg2n-kit.dts index 3c0d59def8ee..89d708346ba8 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1-beacon-rzg2n-kit.dts +++ b/arch/arm64/boot/dts/renesas/r8a774b1-beacon-rzg2n-kit.dts @@ -11,7 +11,7 @@ / { model = "Beacon Embedded Works RZ/G2N Development Kit"; - compatible = "beacon,beacon-rzg2n", "renesas,r8a774b1"; + compatible = "beacon,beacon-rzg2n", "renesas,r8a774b1"; aliases { serial0 = &scif2; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index 44f79fbd75dc..a4b406a346f9 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -1571,7 +1571,7 @@ * clkout : #clock-cells = <0>; <&rcar_sound>; * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; */ - compatible = "renesas,rcar_sound-r8a774b1", "renesas,rcar_sound-gen3"; + compatible = "renesas,rcar_sound-r8a774b1", "renesas,rcar_sound-gen3"; reg = <0 0xec500000 0 0x1000>, /* SCU */ <0 0xec5a0000 0 0x100>, /* ADG */ <0 0xec540000 0 0x1000>, /* SSIU */ @@ -1883,7 +1883,7 @@ dma-names = "rx", "tx"; }; ssiu40: ssiu-32 { - dmas = <&audma0 0x71>, <&audma1 0x72>; + dmas = <&audma0 0x71>, <&audma1 0x72>; dma-names = "rx", "tx"; }; ssiu41: ssiu-33 { diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index b8dcbbbf3db5..e123c8d1bab9 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -1328,11 +1328,11 @@ */ compatible = "renesas,rcar_sound-r8a774c0", "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; clocks = <&cpg CPG_MOD 1005>, diff --git a/arch/arm64/boot/dts/renesas/r8a774e1-beacon-rzg2h-kit.dts b/arch/arm64/boot/dts/renesas/r8a774e1-beacon-rzg2h-kit.dts index 7b6649a3ded0..3e9ced3b2d33 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1-beacon-rzg2h-kit.dts +++ b/arch/arm64/boot/dts/renesas/r8a774e1-beacon-rzg2h-kit.dts @@ -11,7 +11,7 @@ / { model = "Beacon Embedded Works RZ/G2H Development Kit"; - compatible = "beacon,beacon-rzg2h", "renesas,r8a774e1"; + compatible = "beacon,beacon-rzg2h", "renesas,r8a774e1"; aliases { serial0 = &scif2; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index e6d8610730a8..989c1c00dcdc 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -1784,7 +1784,7 @@ * clkout : #clock-cells = <0>; <&rcar_sound>; * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; */ - compatible = "renesas,rcar_sound-r8a774e1", "renesas,rcar_sound-gen3"; + compatible = "renesas,rcar_sound-r8a774e1", "renesas,rcar_sound-gen3"; reg = <0 0xec500000 0 0x1000>, /* SCU */ <0 0xec5a0000 0 0x100>, /* ADG */ <0 0xec540000 0 0x1000>, /* SSIU */ @@ -2043,7 +2043,7 @@ dma-names = "rx", "tx"; }; ssiu40: ssiu-32 { - dmas = <&audma0 0x71>, <&audma1 0x72>; + dmas = <&audma0 0x71>, <&audma1 0x72>; dma-names = "rx", "tx"; }; ssiu41: ssiu-33 { diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 9265a5702792..4e294b1e1f9a 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -2018,12 +2018,12 @@ * clkout : #clock-cells = <0>; <&rcar_sound>; * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; */ - compatible = "renesas,rcar_sound-r8a7795", "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ + compatible = "renesas,rcar_sound-r8a7795", "renesas,rcar_sound-gen3"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; clocks = <&cpg CPG_MOD 1005>, @@ -2277,7 +2277,7 @@ dma-names = "rx", "tx"; }; ssiu40: ssiu-32 { - dmas = <&audma0 0x71>, <&audma1 0x72>; + dmas = <&audma0 0x71>, <&audma1 0x72>; dma-names = "rx", "tx"; }; ssiu41: ssiu-33 { diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index 26f7103d11da..6cdb062bf3fa 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -1890,12 +1890,12 @@ * clkout : #clock-cells = <0>; <&rcar_sound>; * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; */ - compatible = "renesas,rcar_sound-r8a7796", "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ + compatible = "renesas,rcar_sound-r8a7796", "renesas,rcar_sound-gen3"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; clocks = <&cpg CPG_MOD 1005>, @@ -2202,7 +2202,7 @@ dma-names = "rx", "tx"; }; ssiu40: ssiu-32 { - dmas = <&audma0 0x71>, <&audma1 0x72>; + dmas = <&audma0 0x71>, <&audma1 0x72>; dma-names = "rx", "tx"; }; ssiu41: ssiu-33 { diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 59509e20575d..b6e4fd5d3d50 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -1734,7 +1734,7 @@ * clkout : #clock-cells = <0>; <&rcar_sound>; * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; */ - compatible = "renesas,rcar_sound-r8a77961", "renesas,rcar_sound-gen3"; + compatible = "renesas,rcar_sound-r8a77961", "renesas,rcar_sound-gen3"; reg = <0 0xec500000 0 0x1000>, /* SCU */ <0 0xec5a0000 0 0x100>, /* ADG */ <0 0xec540000 0 0x1000>, /* SSIU */ @@ -2046,7 +2046,7 @@ dma-names = "rx", "tx"; }; ssiu40: ssiu-32 { - dmas = <&audma0 0x71>, <&audma1 0x72>; + dmas = <&audma0 0x71>, <&audma1 0x72>; dma-names = "rx", "tx"; }; ssiu41: ssiu-33 { diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index f898aad72b9d..4d21bc0ca85e 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -1753,12 +1753,12 @@ * clkout : #clock-cells = <0>; <&rcar_sound>; * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; */ - compatible = "renesas,rcar_sound-r8a77965", "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ + compatible = "renesas,rcar_sound-r8a77965", "renesas,rcar_sound-gen3"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; clocks = <&cpg CPG_MOD 1005>, @@ -2012,7 +2012,7 @@ dma-names = "rx", "tx"; }; ssiu40: ssiu-32 { - dmas = <&audma0 0x71>, <&audma1 0x72>; + dmas = <&audma0 0x71>, <&audma1 0x72>; dma-names = "rx", "tx"; }; ssiu41: ssiu-33 { diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 14caedd0c959..a5fe14384906 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -1489,12 +1489,12 @@ * clkout : #clock-cells = <0>; <&rcar_sound>; * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; */ - compatible = "renesas,rcar_sound-r8a77990", "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ + compatible = "renesas,rcar_sound-r8a77990", "renesas,rcar_sound-gen3"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; clocks = <&cpg CPG_MOD 1005>, diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index f29f3982a492..34f581238370 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -1046,12 +1046,12 @@ * clkout : #clock-cells = <0>; <&rcar_sound>; * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; */ - compatible = "renesas,rcar_sound-r8a77995", "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ + compatible = "renesas,rcar_sound-r8a77995", "renesas,rcar_sound-gen3"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; clocks = <&cpg CPG_MOD 1005>, diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 9ad1b23ad2ec..c4be288b1912 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -102,7 +102,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 916>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 916>; + resets = <&cpg 916>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pfc 0 0 28>; @@ -116,7 +116,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 915>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 915>; + resets = <&cpg 915>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pfc 0 32 31>; @@ -130,7 +130,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 915>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 915>; + resets = <&cpg 915>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pfc 0 64 25>; @@ -144,7 +144,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 916>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 916>; + resets = <&cpg 916>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pfc 0 96 17>; @@ -158,7 +158,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 917>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 917>; + resets = <&cpg 917>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pfc 0 128 27>; @@ -172,7 +172,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 917>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 917>; + resets = <&cpg 917>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pfc 0 160 21>; @@ -186,7 +186,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 918>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 918>; + resets = <&cpg 918>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pfc 0 192 21>; @@ -200,7 +200,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 918>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 918>; + resets = <&cpg 918>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pfc 0 224 21>; @@ -214,7 +214,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 918>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 918>; + resets = <&cpg 918>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pfc 0 256 21>; @@ -228,7 +228,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 918>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 918>; + resets = <&cpg 918>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pfc 0 288 21>; -- cgit From fb912a1b474e6e3486f1a5057411fdbeec942ea0 Mon Sep 17 00:00:00 2001 From: Nikita Yushchenko Date: Thu, 20 Jan 2022 08:15:59 +0300 Subject: arm64: dts: renesas: rcar-gen3: Add MOST devices This patch adds the MLP device nodes to dtsi files for R-Car Gen3 SoCs that have it. Signed-off-by: Nikita Yushchenko Link: https://lore.kernel.org/r/20220120051559.746322-1-nikita.yoush@cogentembedded.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77951.dtsi | 12 ++++++++++++ arch/arm64/boot/dts/renesas/r8a77960.dtsi | 12 ++++++++++++ arch/arm64/boot/dts/renesas/r8a77961.dtsi | 12 ++++++++++++ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 12 ++++++++++++ arch/arm64/boot/dts/renesas/r8a77990.dtsi | 12 ++++++++++++ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 12 ++++++++++++ 6 files changed, 72 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 4e294b1e1f9a..4e87e8776a2b 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -2412,6 +2412,18 @@ }; }; + mlp: mlp@ec520000 { + compatible = "renesas,r8a7795-mlp", + "renesas,rcar-gen3-mlp"; + reg = <0 0xec520000 0 0x800>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 802>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 802>; + status = "disabled"; + }; + audma0: dma-controller@ec700000 { compatible = "renesas,dmac-r8a7795", "renesas,rcar-dmac"; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index 6cdb062bf3fa..6f79da8cc8c0 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -2284,6 +2284,18 @@ }; }; + mlp: mlp@ec520000 { + compatible = "renesas,r8a7796-mlp", + "renesas,rcar-gen3-mlp"; + reg = <0 0xec520000 0 0x800>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 802>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 802>; + status = "disabled"; + }; + audma0: dma-controller@ec700000 { compatible = "renesas,dmac-r8a7796", "renesas,rcar-dmac"; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index b6e4fd5d3d50..68cbbb322acf 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -2128,6 +2128,18 @@ }; }; + mlp: mlp@ec520000 { + compatible = "renesas,r8a77961-mlp", + "renesas,rcar-gen3-mlp"; + reg = <0 0xec520000 0 0x800>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 802>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 802>; + status = "disabled"; + }; + audma0: dma-controller@ec700000 { compatible = "renesas,dmac-r8a77961", "renesas,rcar-dmac"; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 4d21bc0ca85e..9f858af8b762 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -2147,6 +2147,18 @@ }; }; + mlp: mlp@ec520000 { + compatible = "renesas,r8a77965-mlp", + "renesas,rcar-gen3-mlp"; + reg = <0 0xec520000 0 0x800>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 802>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 802>; + status = "disabled"; + }; + audma0: dma-controller@ec700000 { compatible = "renesas,dmac-r8a77965", "renesas,rcar-dmac"; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index a5fe14384906..7e0f1aab2135 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -1682,6 +1682,18 @@ }; }; + mlp: mlp@ec520000 { + compatible = "renesas,r8a77990-mlp", + "renesas,rcar-gen3-mlp"; + reg = <0 0xec520000 0 0x800>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 802>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 802>; + status = "disabled"; + }; + audma0: dma-controller@ec700000 { compatible = "renesas,dmac-r8a77990", "renesas,rcar-dmac"; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index 34f581238370..cac1f9467ffa 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -1132,6 +1132,18 @@ }; }; + mlp: mlp@ec520000 { + compatible = "renesas,r8a77995-mlp", + "renesas,rcar-gen3-mlp"; + reg = <0 0xec520000 0 0x800>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 802>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 802>; + status = "disabled"; + }; + audma0: dma-controller@ec700000 { compatible = "renesas,dmac-r8a77995", "renesas,rcar-dmac"; -- cgit From 0e684f6e935317b26dfe9b9f3197d2cecbb7d429 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 24 Jan 2022 11:11:40 +0900 Subject: arm64: dts: renesas: ulcb/ulcb-kf: switch to use audio-graph-card2 for sound Current ULCB{-KF} are using audio-graph-card. Now ALSA is supporting new audio-graph-card2 which can easily handle more advanced feature. Let's switch to use it. Signed-off-by: Kuninori Morimoto Link: https://lore.kernel.org/r/20220124021142.224592-2-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 22 ++++++++-------------- arch/arm64/boot/dts/renesas/ulcb.dtsi | 20 +++++++------------- 2 files changed, 15 insertions(+), 27 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi index 30f185547012..889d117dadf5 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi @@ -419,12 +419,9 @@ reg = <2>; rsnd_for_pcm3168a_play: endpoint { remote-endpoint = <&pcm3168a_endpoint_p>; - - dai-format = "i2s"; - bitclock-master = <&rsnd_for_pcm3168a_play>; - frame-master = <&rsnd_for_pcm3168a_play>; + bitclock-master; + frame-master; dai-tdm-slot-num = <8>; - playback = <&ssi3>; }; }; @@ -432,12 +429,9 @@ reg = <3>; rsnd_for_pcm3168a_capture: endpoint { remote-endpoint = <&pcm3168a_endpoint_c>; - - dai-format = "i2s"; - bitclock-master = <&rsnd_for_pcm3168a_capture>; - frame-master = <&rsnd_for_pcm3168a_capture>; + bitclock-master; + frame-master; dai-tdm-slot-num = <6>; - capture = <&ssi4>; }; }; @@ -477,10 +471,10 @@ }; &sound_card { - dais = <&rsnd_port0 /* ak4613 */ - &rsnd_port1 /* HDMI0 */ - &rsnd_port2 /* pcm3168a playback */ - &rsnd_port3 /* pcm3168a capture */ + links = <&rsnd_port0 /* ak4613 */ + &rsnd_port1 /* HDMI0 */ + &rsnd_port2 /* pcm3168a playback */ + &rsnd_port3 /* pcm3168a capture */ >; }; diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index a7e93df4ced8..b4bdb2d7e4ba 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -95,11 +95,11 @@ }; sound_card: sound { - compatible = "audio-graph-card"; + compatible = "audio-graph-card2"; label = "rcar-sound"; - dais = <&rsnd_port0 /* ak4613 */ - &rsnd_port1 /* HDMI0 */ + links = <&rsnd_port0 /* ak4613 */ + &rsnd_port1 /* HDMI0 */ >; }; @@ -408,11 +408,8 @@ reg = <0>; rsnd_for_ak4613: endpoint { remote-endpoint = <&ak4613_endpoint>; - - dai-format = "left_j"; - bitclock-master = <&rsnd_for_ak4613>; - frame-master = <&rsnd_for_ak4613>; - + bitclock-master; + frame-master; playback = <&ssi0>, <&src0>, <&dvc0>; capture = <&ssi1>, <&src1>, <&dvc1>; }; @@ -421,11 +418,8 @@ reg = <1>; rsnd_for_hdmi: endpoint { remote-endpoint = <&dw_hdmi0_snd_in>; - - dai-format = "i2s"; - bitclock-master = <&rsnd_for_hdmi>; - frame-master = <&rsnd_for_hdmi>; - + bitclock-master; + frame-master; playback = <&ssi2>; }; }; -- cgit From bd1e3696a052b9b2bd3c1c72ef4bf800a3a1e286 Mon Sep 17 00:00:00 2001 From: Aswani Reddy Date: Tue, 25 Jan 2022 08:46:04 +0530 Subject: arm64: dts: fsd: Add SPI device nodes Adds device tree node for SPI IPs Cc: linux-fsd@tesla.com Signed-off-by: Aswani Reddy Signed-off-by: Alim Akhtar Reviewed-by: Krzysztof Kozlowski Reviewed-by: Andi Shyti Link: https://lore.kernel.org/r/20220125031604.76009-4-alim.akhtar@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/tesla/fsd.dtsi | 57 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi index b7f05f78c601..da4acd68b976 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -29,6 +29,9 @@ pinctrl0 = &pinctrl_fsys0; pinctrl1 = &pinctrl_peric; pinctrl2 = &pinctrl_pmu; + spi0 = &spi_0; + spi1 = &spi_1; + spi2 = &spi_2; }; cpus { @@ -668,6 +671,60 @@ reg = <0x0 0x15020000 0x0 0x1000>; interrupts = ; }; + + spi_0: spi@14140000 { + compatible = "tesla,fsd-spi"; + reg = <0x0 0x14140000 0x0 0x100>; + interrupts = ; + dmas = <&pdma1 4>, <&pdma1 5>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock_peric PERIC_PCLK_SPI0>, + <&clock_peric PERIC_SCLK_SPI0>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_bus>; + num-cs = <1>; + status = "disabled"; + }; + + spi_1: spi@14150000 { + compatible = "tesla,fsd-spi"; + reg = <0x0 0x14150000 0x0 0x100>; + interrupts = ; + dmas = <&pdma1 6>, <&pdma1 7>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock_peric PERIC_PCLK_SPI1>, + <&clock_peric PERIC_SCLK_SPI1>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_bus>; + num-cs = <1>; + status = "disabled"; + }; + + spi_2: spi@14160000 { + compatible = "tesla,fsd-spi"; + reg = <0x0 0x14160000 0x0 0x100>; + interrupts = ; + dmas = <&pdma1 8>, <&pdma1 9>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock_peric PERIC_PCLK_SPI2>, + <&clock_peric PERIC_SCLK_SPI2>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_bus>; + num-cs = <1>; + status = "disabled"; + }; }; }; -- cgit From 9ade1ab4d85f5fc31a5d6cf5147702ed5c1b5b10 Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Sat, 29 Jan 2022 17:24:39 +0100 Subject: arm64: dts: rockchip: fix vcc3v3_lcd{0,1}_n regulators in rk3568-evb1-10 The voltages VCC3V3_LCD{0,1} can be enabled with the pins GPIO0_C7 and GPIO0_C5, respectively. This patch modifies the device tree in order to reflect this. Signed-off-by: Michael Riesch Link: https://lore.kernel.org/r/20220129162440.5415-1-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts | 25 ++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts index 184e2aa2416a..197aaf7ee348 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts @@ -56,7 +56,13 @@ vcc3v3_lcd0_n: vcc3v3-lcd0-n { compatible = "regulator-fixed"; regulator-name = "vcc3v3_lcd0_n"; - regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc3v3_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_lcd0_n_en>; regulator-state-mem { regulator-off-in-suspend; @@ -66,7 +72,13 @@ vcc3v3_lcd1_n: vcc3v3-lcd1-n { compatible = "regulator-fixed"; regulator-name = "vcc3v3_lcd1_n"; - regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc3v3_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_lcd1_n_en>; regulator-state-mem { regulator-off-in-suspend; @@ -339,6 +351,15 @@ }; &pinctrl { + display { + vcc3v3_lcd0_n_en: vcc3v3_lcd0_n_en { + rockchip,pins = <0 RK_PC7 0 &pcfg_pull_none>; + }; + vcc3v3_lcd1_n_en: vcc3v3_lcd1_n_en { + rockchip,pins = <0 RK_PC5 0 &pcfg_pull_none>; + }; + }; + pmic { pmic_int: pmic_int { rockchip,pins = -- cgit From 922237a6c211d9fe46b5dfb56307872cdced386d Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Sat, 29 Jan 2022 17:24:40 +0100 Subject: arm64: dts: rockchip: add the touchscreen controller to rk3568-evb1-v10 The Rockchip RK3568 EVB1 comes with a mounted touch display featuring a Goodix GT1158 touch controller (according to the product ID register). Signed-off-by: Michael Riesch Link: https://lore.kernel.org/r/20220129162440.5415-2-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts | 26 ++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts index 197aaf7ee348..d8c20a23e856 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts @@ -330,6 +330,23 @@ }; }; +&i2c1 { + status = "okay"; + + touchscreen0: goodix@14 { + compatible = "goodix,gt1151"; + reg = <0x14>; + interrupt-parent = <&gpio0>; + interrupts = ; + AVDD28-supply = <&vcc3v3_lcd0_n>; + irq-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_int &touch_rst>; + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + VDDIO-supply = <&vcc3v3_lcd0_n>; + }; +}; + &mdio0 { rgmii_phy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; @@ -366,6 +383,15 @@ <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; }; }; + + touchscreen { + touch_int: touch_int { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + touch_rst: touch_rst { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &pmu_io_domains { -- cgit From 827dfba89ae150cd0fd88bc13117540cb4882943 Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Thu, 27 Jan 2022 19:38:06 -0500 Subject: arm64: dts: rockchip: add Quartz64-A pmu_io_domains Several io power domains on the Quartz64-A operate at 1.8v. Add the pmu_io_domains definition to enable support for this. This permits the enablement of the following features: sdio - wifi support sdhci - mmc-hs200-1_8v Signed-off-by: Peter Geis Link: https://lore.kernel.org/r/20220128003809.3291407-3-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts index f1d6bf10c650..4310dcb5d253 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts @@ -506,6 +506,19 @@ }; }; +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc1v8_dvp>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + &sdhci { bus-width = <8>; mmc-hs200-1_8v; -- cgit From 2ed1e35457a1917a9c567c186a5adc7ce6341b6e Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Thu, 27 Jan 2022 19:38:07 -0500 Subject: arm64: dts: rockchip: add Quartz64-A sdmmc1 node The sdmmc1 node on Quartz64-A supports the optional wifi module from Pine64. Add the sdmmc1 node and requisite sdio_pwrseq to enable wifi support on the Quartz64-A. Signed-off-by: Peter Geis Link: https://lore.kernel.org/r/20220128003809.3291407-4-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 43 ++++++++++++++++++++++ 1 file changed, 43 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts index 4310dcb5d253..94a164d6bce9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts @@ -73,6 +73,17 @@ }; }; + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + post-power-on-delay-ms = <100>; + power-off-delay-us = <5000000>; + reset-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>; + }; + spdif_dit: spdif-dit { compatible = "linux,spdif-dit"; #sound-dai-cells = <0>; @@ -163,6 +174,17 @@ regulator-max-microvolt = <4400000>; vin-supply = <&vbus>; }; + + /* sourced from vcc_sys, sdio module operates internally at 3.3v */ + vcc_wl: vcc_wl { + compatible = "regulator-fixed"; + regulator-name = "vcc_wl"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; }; &cpu0 { @@ -499,6 +521,12 @@ }; }; + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + vcc_sd { vcc_sd_h: vcc-sd-h { rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; @@ -540,6 +568,21 @@ status = "okay"; }; +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + vmmc-supply = <&vcc_wl>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + &spdif { status = "okay"; }; -- cgit From 2943660fe301aa650cdf60226a2a350d09145823 Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Thu, 27 Jan 2022 19:38:08 -0500 Subject: arm64: dts: rockchip: add Quartz64-A con40 hardware The Quartz64-A has a 40 pin connector that exposes various functions. Annotate the functions exposed in the device tree. Enable i2c3, which is pulled up to vcc_3v3 on board. The following functions are currently exposed: i2c3 spi1 uart2 uart0 spdif Signed-off-by: Peter Geis Link: https://lore.kernel.org/r/20220128003809.3291407-5-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts index 94a164d6bce9..8332627f483b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts @@ -467,6 +467,14 @@ }; }; +/* i2c3 is exposed on con40 + * pin 3 - i2c3_sda_m0, pullup to vcc_3v3 + * pin 5 - i2c3_scl_m0, pullup to vcc_3v3 + */ +&i2c3 { + status = "okay"; +}; + &i2s1_8ch { pinctrl-names = "default"; pinctrl-0 = <&i2s1m0_sclktx @@ -583,10 +591,17 @@ status = "okay"; }; +/* spdif is exposed on con40 pin 18 */ &spdif { status = "okay"; }; +/* spi1 is exposed on con40 + * pin 11 - spi1_mosi_m1 + * pin 13 - spi1_miso_m1 + * pin 15 - spi1_clk_m1 + * pin 17 - spi1_cs0_m1 + */ &spi1 { pinctrl-names = "default"; pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>; @@ -600,6 +615,10 @@ status = "okay"; }; +/* uart0 is exposed on con40 + * pin 12 - uart0_tx + * pin 14 - uart0_rx + */ &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer>; @@ -626,6 +645,10 @@ }; }; +/* uart2 is exposed on con40 + * pin 8 - uart2_tx_m0_debug + * pin 10 - uart2_rx_m0_debug + */ &uart2 { status = "okay"; }; -- cgit From bfb3c7fa3950f2dece0bfec1df5fbce7117345af Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Mon, 31 Jan 2022 15:08:48 +0200 Subject: arm64: dts: exynos: Add initial Exynos850 SoC support Samsung Exynos850 is ARMv8-based mobile-oriented SoC. This patch adds initial SoC support. It's not comprehensive yet, some more devices will be added later. Right now only crucial system components and most needed platform devices are defined. Crucial features (needed to boot Linux up to shell with serial console): * Octa cores (Cortex-A55), supporting PSCI v1.0 * ARM architected timer (armv8-timer) * Interrupt controller (GIC-400) * Pinctrl nodes for GPIO * Serial node Basic platform features: * Clock controller CMUs * OSCCLK clock * MCT timer * ARM PMU (Performance Monitor Unit) * Chip-id * RTC * Reset * Watchdog timers * eMMC * I2C * HSI2C * USI All those features are tested on E850-96 board with minimal BusyBox rootfs. Reviewed-by: Chanho Park Signed-off-by: Sam Protsenko Link: https://lore.kernel.org/r/20220131130849.2667-2-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi | 663 +++++++++++++++++++ arch/arm64/boot/dts/exynos/exynos850.dtsi | 741 ++++++++++++++++++++++ 2 files changed, 1404 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/exynos/exynos850.dtsi (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi new file mode 100644 index 000000000000..6c31da70e223 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi @@ -0,0 +1,663 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos850 SoC pin-mux and pin-config device tree source + * + * Copyright (C) 2017 Samsung Electronics Co., Ltd. + * Copyright (C) 2021 Linaro Ltd. + * + * Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device + * tree nodes in this file. + */ + +#include +#include + +&pinctrl_alive { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + gpa2: gpa2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + gpa3: gpa3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + gpa4: gpa4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + gpq0: gpq0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* I2C5 (also called CAM_PMIC_I2C in TRM) */ + i2c5_pins: i2c5-pins { + samsung,pins = "gpa3-5", "gpa3-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* I2C6 (also called MOTOR_I2C in TRM) */ + i2c6_pins: i2c6-pins { + samsung,pins = "gpa3-7", "gpa4-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* USI: UART_DEBUG_0 pins */ + uart0_pins: uart0-pins { + samsung,pins = "gpq0-0", "gpq0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI: UART_DEBUG_1 pins */ + uart1_pins: uart1-pins { + samsung,pins = "gpa3-7", "gpa4-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + +&pinctrl_cmgp { + gpm0: gpm0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm1: gpm1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm2: gpm2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm3: gpm3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm4: gpm4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm5: gpm5 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm6: gpm6 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm7: gpm7 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + /* USI_CMGP0: HSI2C function */ + hsi2c3_pins: hsi2c3-pins { + samsung,pins = "gpm0-0", "gpm1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* USI_CMGP0: UART function (4 pins, Auto Flow Control) */ + uart1_single_pins: uart1-single-pins { + samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0", "gpm3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI_CMGP0: UART function (2 pins, Non-Auto Flow Control) */ + uart1_dual_pins: uart1-dual-pins { + samsung,pins = "gpm0-0", "gpm1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI_CMGP0: SPI function */ + spi1_pins: spi1-pins { + samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0", "gpm3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* USI_CMGP1: HSI2C function */ + hsi2c4_pins: hsi2c4-pins { + samsung,pins = "gpm4-0", "gpm5-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* USI_CMGP1: UART function (4 pins, Auto Flow Control) */ + uart2_single_pins: uart2-single-pins { + samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0", "gpm7-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI_CMGP1: UART function (2 pins, Non-Auto Flow Control) */ + uart2_dual_pins: uart2-dual-pins { + samsung,pins = "gpm4-0", "gpm5-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI_CMGP1: SPI function */ + spi2_pins: spi2-pins { + samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0", "gpm7-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_aud { + gpb0: gpb0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb1: gpb1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + aud_codec_mclk_pins: aud-codec-mclk-pins { + samsung,pins = "gpb0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_codec_mclk_idle_pins: aud-codec-mclk-idle-pins { + samsung,pins = "gpb0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_i2s0_pins: aud-i2s0-pins { + samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_i2s0_idle_pins: aud-i2s0-idle-pins { + samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_i2s1_pins: aud-i2s1-pins { + samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_i2s1_idle_pins: aud-i2s1-idle-pins { + samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_fm_pins: aud-fm-pins { + samsung,pins = "gpb1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_fm_idle_pins: aud-fm-idle-pins { + samsung,pins = "gpb1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + +&pinctrl_hsi { + gpf2: gpf2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sd2_clk_pins: sd2-clk-pins { + samsung,pins = "gpf2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_cmd_pins: sd2-cmd-pins { + samsung,pins = "gpf2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_bus1_pins: sd2-bus1-pins { + samsung,pins = "gpf2-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_bus4_pins: sd2-bus4-pins { + samsung,pins = "gpf2-3", "gpf2-4", "gpf2-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_pdn_pins: sd2-pdn-pins { + samsung,pins = "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", + "gpf2-4", "gpf2-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + +&pinctrl_core { + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sd0_clk_pins: sd0-clk-pins { + samsung,pins = "gpf0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_cmd_pins: sd0-cmd-pins { + samsung,pins = "gpf0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_rdqs_pins: sd0-rdqs-pins { + samsung,pins = "gpf0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_nreset_pins: sd0-nreset-pins { + samsung,pins = "gpf0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus1_pins: sd0-bus1-pins { + samsung,pins = "gpf1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus4_pins: sd0-bus4-pins { + samsung,pins = "gpf1-1", "gpf1-2", "gpf1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus8_pins: sd0-bus8-pins { + samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_peri { + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg0: gpg0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg1: gpg1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg2: gpg2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg3: gpg3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp0: gpp0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + gpp1: gpp1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp2: gpp2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sensor_mclk0_in_pins: sensor-mclk0-in-pins { + samsung,pins = "gpc0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk0_out_pins: sensor-mclk0-out-pins { + samsung,pins = "gpc0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk0_fn_pins: sensor-mclk0-fn-pins { + samsung,pins = "gpc0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk1_in_pins: sensor-mclk1-in-pins { + samsung,pins = "gpc0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk1_out_pins: sensor-mclk1-out-pins { + samsung,pins = "gpc0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk1_fn_pins: sensor-mclk1-fn-pins { + samsung,pins = "gpc0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk2_in_pins: sensor-mclk2-in-pins { + samsung,pins = "gpc0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk2_out_pins: sensor-mclk2-out-pins { + samsung,pins = "gpc0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk2_fn_pins: sensor-mclk2-fn-pins { + samsung,pins = "gpc0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* USI: HSI2C0 */ + hsi2c0_pins: hsi2c0-pins { + samsung,pins = "gpc1-0", "gpc1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* USI: HSI2C1 */ + hsi2c1_pins: hsi2c1-pins { + samsung,pins = "gpc1-2", "gpc1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* USI: HSI2C2 */ + hsi2c2_pins: hsi2c2-pins { + samsung,pins = "gpc1-4", "gpc1-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* USI: SPI */ + spi0_pins: spi0-pins { + samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2", "gpp2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c0_pins: i2c0-pins { + samsung,pins = "gpp0-0", "gpp0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c1_pins: i2c1-pins { + samsung,pins = "gpp0-2", "gpp0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c2_pins: i2c2-pins { + samsung,pins = "gpp0-4", "gpp0-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c3_pins: i2c3-pins { + samsung,pins = "gpp1-0", "gpp1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c4_pins: i2c4-pins { + samsung,pins = "gpp1-2", "gpp1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + xclkout_pins: xclkout-pins { + samsung,pins = "gpq0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi new file mode 100644 index 000000000000..c9457593f6cc --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -0,0 +1,741 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung Exynos850 SoC device tree source + * + * Copyright (C) 2018 Samsung Electronics Co., Ltd. + * Copyright (C) 2021 Linaro Ltd. + * + * Samsung Exynos850 SoC device nodes are listed in this file. + * Exynos850 based board files can include this file and provide + * values for board specific bindings. + */ + +#include +#include +#include + +/ { + /* Also known under engineering name Exynos3830 */ + compatible = "samsung,exynos850"; + #address-cells = <2>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + aliases { + pinctrl0 = &pinctrl_alive; + pinctrl1 = &pinctrl_cmgp; + pinctrl2 = &pinctrl_aud; + pinctrl3 = &pinctrl_hsi; + pinctrl4 = &pinctrl_core; + pinctrl5 = &pinctrl_peri; + mmc0 = &mmc_0; + serial0 = &serial_0; + serial1 = &serial_1; + serial2 = &serial_2; + i2c0 = &i2c_0; + i2c1 = &i2c_1; + i2c2 = &i2c_2; + i2c3 = &i2c_3; + i2c4 = &i2c_4; + i2c5 = &i2c_5; + i2c6 = &i2c_6; + i2c7 = &hsi2c_0; + i2c8 = &hsi2c_1; + i2c9 = &hsi2c_2; + i2c10 = &hsi2c_3; + i2c11 = &hsi2c_4; + }; + + arm-pmu { + compatible = "arm,cortex-a55-pmu"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, + <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; + }; + + /* Main system clock (XTCXO); external, must be 26 MHz */ + oscclk: clock-oscclk { + compatible = "fixed-clock"; + clock-output-names = "oscclk"; + #clock-cells = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x1>; + enable-method = "psci"; + }; + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x2>; + enable-method = "psci"; + }; + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x3>; + enable-method = "psci"; + }; + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + }; + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x101>; + enable-method = "psci"; + }; + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x102>; + enable-method = "psci"; + }; + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x103>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + /* Hypervisor Virtual Timer interrupt is not wired to GIC */ + interrupts = + , + , + , + ; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x20000000>; + + chipid@10000000 { + compatible = "samsung,exynos850-chipid"; + reg = <0x10000000 0x100>; + }; + + timer@10040000 { + compatible = "samsung,exynos4210-mct"; + reg = <0x10040000 0x800>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&oscclk>, <&cmu_peri CLK_GOUT_MCT_PCLK>; + clock-names = "fin_pll", "mct"; + }; + + gic: interrupt-controller@12a01000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + reg = <0x12a01000 0x1000>, + <0x12a02000 0x2000>, + <0x12a04000 0x2000>, + <0x12a06000 0x2000>; + interrupt-controller; + interrupts = ; + }; + + pmu_system_controller: system-controller@11860000 { + compatible = "samsung,exynos850-pmu", "syscon"; + reg = <0x11860000 0x10000>; + clocks = <&cmu_apm CLK_GOUT_PMU_ALIVE_PCLK>; + + reboot: syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pmu_system_controller>; + offset = <0x3a00>; /* SYSTEM_CONFIGURATION */ + mask = <0x2>; /* SWRESET_SYSTEM */ + value = <0x2>; /* reset value */ + }; + }; + + watchdog_cl0: watchdog@10050000 { + compatible = "samsung,exynos850-wdt"; + reg = <0x10050000 0x100>; + interrupts = ; + clocks = <&cmu_peri CLK_GOUT_WDT0_PCLK>, <&oscclk>; + clock-names = "watchdog", "watchdog_src"; + samsung,syscon-phandle = <&pmu_system_controller>; + samsung,cluster-index = <0>; + status = "disabled"; + }; + + watchdog_cl1: watchdog@10060000 { + compatible = "samsung,exynos850-wdt"; + reg = <0x10060000 0x100>; + interrupts = ; + clocks = <&cmu_peri CLK_GOUT_WDT1_PCLK>, <&oscclk>; + clock-names = "watchdog", "watchdog_src"; + samsung,syscon-phandle = <&pmu_system_controller>; + samsung,cluster-index = <1>; + status = "disabled"; + }; + + cmu_peri: clock-controller@10030000 { + compatible = "samsung,exynos850-cmu-peri"; + reg = <0x10030000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>, + <&cmu_top CLK_DOUT_PERI_UART>, + <&cmu_top CLK_DOUT_PERI_IP>; + clock-names = "oscclk", "dout_peri_bus", + "dout_peri_uart", "dout_peri_ip"; + }; + + cmu_apm: clock-controller@11800000 { + compatible = "samsung,exynos850-cmu-apm"; + reg = <0x11800000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, <&cmu_top CLK_DOUT_CLKCMU_APM_BUS>; + clock-names = "oscclk", "dout_clkcmu_apm_bus"; + }; + + cmu_cmgp: clock-controller@11c00000 { + compatible = "samsung,exynos850-cmu-cmgp"; + reg = <0x11c00000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, <&cmu_apm CLK_GOUT_CLKCMU_CMGP_BUS>; + clock-names = "oscclk", "gout_clkcmu_cmgp_bus"; + }; + + cmu_core: clock-controller@12000000 { + compatible = "samsung,exynos850-cmu-core"; + reg = <0x12000000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, <&cmu_top CLK_DOUT_CORE_BUS>, + <&cmu_top CLK_DOUT_CORE_CCI>, + <&cmu_top CLK_DOUT_CORE_MMC_EMBD>, + <&cmu_top CLK_DOUT_CORE_SSS>; + clock-names = "oscclk", "dout_core_bus", + "dout_core_cci", "dout_core_mmc_embd", + "dout_core_sss"; + }; + + cmu_top: clock-controller@120e0000 { + compatible = "samsung,exynos850-cmu-top"; + reg = <0x120e0000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>; + clock-names = "oscclk"; + }; + + cmu_dpu: clock-controller@13000000 { + compatible = "samsung,exynos850-cmu-dpu"; + reg = <0x13000000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, <&cmu_top CLK_DOUT_DPU>; + clock-names = "oscclk", "dout_dpu"; + }; + + cmu_hsi: clock-controller@13400000 { + compatible = "samsung,exynos850-cmu-hsi"; + reg = <0x13400000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_HSI_BUS>, + <&cmu_top CLK_DOUT_HSI_MMC_CARD>, + <&cmu_top CLK_DOUT_HSI_USB20DRD>; + clock-names = "oscclk", "dout_hsi_bus", + "dout_hsi_mmc_card", "dout_hsi_usb20drd"; + }; + + pinctrl_alive: pinctrl@11850000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x11850000 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + wakeup-interrupt-controller { + compatible = "samsung,exynos7-wakeup-eint"; + }; + }; + + pinctrl_cmgp: pinctrl@11c30000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x11c30000 0x1000>; + interrupts = , + , + , + , + , + , + , + ; + + wakeup-interrupt-controller { + compatible = "samsung,exynos7-wakeup-eint"; + }; + }; + + pinctrl_core: pinctrl@12070000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x12070000 0x1000>; + interrupts = ; + }; + + pinctrl_hsi: pinctrl@13430000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x13430000 0x1000>; + interrupts = ; + }; + + pinctrl_peri: pinctrl@139b0000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x139b0000 0x1000>; + interrupts = ; + }; + + pinctrl_aud: pinctrl@14a60000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x14a60000 0x1000>; + }; + + rtc: rtc@11a30000 { + compatible = "samsung,s3c6410-rtc"; + reg = <0x11a30000 0x100>; + interrupts = , + ; + clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>; + clock-names = "rtc"; + status = "disabled"; + }; + + mmc_0: mmc@12100000 { + compatible = "samsung,exynos7-dw-mshc-smu"; + reg = <0x12100000 0x2000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_core CLK_GOUT_MMC_EMBD_ACLK>, + <&cmu_core CLK_GOUT_MMC_EMBD_SDCLKIN>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; + }; + + i2c_0: i2c@13830000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13830000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clocks = <&cmu_peri CLK_GOUT_I2C0_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + i2c_1: i2c@13840000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13840000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clocks = <&cmu_peri CLK_GOUT_I2C1_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + i2c_2: i2c@13850000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13850000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + clocks = <&cmu_peri CLK_GOUT_I2C2_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + i2c_3: i2c@13860000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13860000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + clocks = <&cmu_peri CLK_GOUT_I2C3_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + i2c_4: i2c@13870000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13870000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + clocks = <&cmu_peri CLK_GOUT_I2C4_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + /* I2C_5 (also called CAM_PMIC_I2C in TRM) */ + i2c_5: i2c@13880000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13880000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins>; + clocks = <&cmu_peri CLK_GOUT_I2C5_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + /* I2C_6 (also called MOTOR_I2C in TRM) */ + i2c_6: i2c@13890000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13890000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_pins>; + clocks = <&cmu_peri CLK_GOUT_I2C6_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + sysreg_peri: syscon@10020000 { + compatible = "samsung,exynos850-sysreg", "syscon"; + reg = <0x10020000 0x10000>; + clocks = <&cmu_peri CLK_GOUT_SYSREG_PERI_PCLK>; + }; + + sysreg_cmgp: syscon@11c20000 { + compatible = "samsung,exynos850-sysreg", "syscon"; + reg = <0x11c20000 0x10000>; + clocks = <&cmu_cmgp CLK_GOUT_SYSREG_CMGP_PCLK>; + }; + + usi_uart: usi@138200c0 { + compatible = "samsung,exynos850-usi"; + reg = <0x138200c0 0x20>; + samsung,sysreg = <&sysreg_peri 0x1010>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peri CLK_GOUT_UART_PCLK>, + <&cmu_peri CLK_GOUT_UART_IPCLK>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + serial_0: serial@13820000 { + compatible = "samsung,exynos850-uart"; + reg = <0x13820000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + clocks = <&cmu_peri CLK_GOUT_UART_PCLK>, + <&cmu_peri CLK_GOUT_UART_IPCLK>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + }; + + usi_hsi2c_0: usi@138a00c0 { + compatible = "samsung,exynos850-usi"; + reg = <0x138a00c0 0x20>; + samsung,sysreg = <&sysreg_peri 0x1020>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peri CLK_GOUT_HSI2C0_PCLK>, + <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_0: i2c@138a0000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x138a0000 0xc0>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c0_pins>; + clocks = <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>, + <&cmu_peri CLK_GOUT_HSI2C0_PCLK>; + clock-names = "hsi2c", "hsi2c_pclk"; + status = "disabled"; + }; + }; + + usi_hsi2c_1: usi@138b00c0 { + compatible = "samsung,exynos850-usi"; + reg = <0x138b00c0 0x20>; + samsung,sysreg = <&sysreg_peri 0x1030>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peri CLK_GOUT_HSI2C1_PCLK>, + <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_1: i2c@138b0000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x138b0000 0xc0>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c1_pins>; + clocks = <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>, + <&cmu_peri CLK_GOUT_HSI2C1_PCLK>; + clock-names = "hsi2c", "hsi2c_pclk"; + status = "disabled"; + }; + }; + + usi_hsi2c_2: usi@138c00c0 { + compatible = "samsung,exynos850-usi"; + reg = <0x138c00c0 0x20>; + samsung,sysreg = <&sysreg_peri 0x1040>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peri CLK_GOUT_HSI2C2_PCLK>, + <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_2: i2c@138c0000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x138c0000 0xc0>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c2_pins>; + clocks = <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>, + <&cmu_peri CLK_GOUT_HSI2C2_PCLK>; + clock-names = "hsi2c", "hsi2c_pclk"; + status = "disabled"; + }; + }; + + usi_spi_0: usi@139400c0 { + compatible = "samsung,exynos850-usi"; + reg = <0x139400c0 0x20>; + samsung,sysreg = <&sysreg_peri 0x1050>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peri CLK_GOUT_SPI0_PCLK>, + <&cmu_peri CLK_GOUT_SPI0_IPCLK>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + }; + + usi_cmgp0: usi@11d000c0 { + compatible = "samsung,exynos850-usi"; + reg = <0x11d000c0 0x20>; + samsung,sysreg = <&sysreg_cmgp 0x2000>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_3: i2c@11d00000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x11d00000 0xc0>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c3_pins>; + clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>; + clock-names = "hsi2c", "hsi2c_pclk"; + status = "disabled"; + }; + + serial_1: serial@11d00000 { + compatible = "samsung,exynos850-uart"; + reg = <0x11d00000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_single_pins>; + clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + }; + + usi_cmgp1: usi@11d200c0 { + compatible = "samsung,exynos850-usi"; + reg = <0x11d200c0 0x20>; + samsung,sysreg = <&sysreg_cmgp 0x2010>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_4: i2c@11d20000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x11d20000 0xc0>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c4_pins>; + clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>; + clock-names = "hsi2c", "hsi2c_pclk"; + status = "disabled"; + }; + + serial_2: serial@11d20000 { + compatible = "samsung,exynos850-uart"; + reg = <0x11d20000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_single_pins>; + clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + }; + }; +}; + +#include "exynos850-pinctrl.dtsi" -- cgit From 363e52998c839ce77d7d5dd6f3e575bb68449afd Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Mon, 31 Jan 2022 15:08:49 +0200 Subject: arm64: dts: exynos: Add initial E850-96 board support E850-96 is a 96boards development board manufactured by WinLink. It incorporates Samsung Exynos850 SoC, and is compatible with 96boards mezzanine boards [1], as it follows 96boards standards. This patch adds minimal support for E850-96 board. Next features are enabled in board dts file and verified with minimal BusyBox rootfs: * User buttons * LEDs * Serial console * Watchdog timers * RTC * eMMC [1] https://www.96boards.org/products/mezzanine/ Signed-off-by: Sam Protsenko Link: https://lore.kernel.org/r/20220131130849.2667-3-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/Makefile | 1 + arch/arm64/boot/dts/exynos/exynos850-e850-96.dts | 195 +++++++++++++++++++++++ 2 files changed, 196 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/exynos850-e850-96.dts (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile index b41e86df0a84..be9df8e85c59 100644 --- a/arch/arm64/boot/dts/exynos/Makefile +++ b/arch/arm64/boot/dts/exynos/Makefile @@ -3,4 +3,5 @@ dtb-$(CONFIG_ARCH_EXYNOS) += \ exynos5433-tm2.dtb \ exynos5433-tm2e.dtb \ exynos7-espresso.dtb \ + exynos850-e850-96.dtb \ exynosautov9-sadk.dtb diff --git a/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts b/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts new file mode 100644 index 000000000000..7b5a61d22cc5 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * WinLink E850-96 board device tree source + * + * Copyright (C) 2018 Samsung Electronics Co., Ltd. + * Copyright (C) 2021 Linaro Ltd. + * + * Device tree source file for WinLink's E850-96 board which is based on + * Samsung Exynos850 SoC. + */ + +/dts-v1/; + +#include "exynos850.dtsi" +#include +#include +#include + +/ { + model = "WinLink E850-96 board"; + compatible = "winlink,e850-96", "samsung,exynos850"; + + chosen { + stdout-path = &serial_0; + }; + + /* + * RAM: 4 GiB (eMCP): + * - 2 GiB at 0x80000000 + * - 2 GiB at 0x880000000 + * + * 0xbab00000..0xbfffffff: secure memory (85 MiB). + */ + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x3ab00000>, + <0x0 0xc0000000 0x40000000>, + <0x8 0x80000000 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key_voldown_pins &key_volup_pins>; + + volume-down-key { + label = "Volume Down"; + linux,code = ; + gpios = <&gpa1 0 GPIO_ACTIVE_LOW>; + }; + + volume-up-key { + label = "Volume Up"; + linux,code = ; + gpios = <&gpa0 7 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + /* HEART_BEAT_LED */ + user_led1: led-1 { + label = "yellow:user1"; + gpios = <&gpg2 2 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_HEARTBEAT; + linux,default-trigger = "heartbeat"; + }; + + /* eMMC_LED */ + user_led2: led-2 { + label = "yellow:user2"; + gpios = <&gpg2 3 GPIO_ACTIVE_HIGH>; + color = ; + linux,default-trigger = "mmc0"; + }; + + /* SD_LED */ + user_led3: led-3 { + label = "white:user3"; + gpios = <&gpg2 4 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_SD; + linux,default-trigger = "mmc2"; + }; + + /* WIFI_LED */ + wlan_active_led: led-4 { + label = "yellow:wlan"; + gpios = <&gpg2 6 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_WLAN; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + + /* BLUETOOTH_LED */ + bt_active_led: led-5 { + label = "blue:bt"; + gpios = <&gpg2 7 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_BLUETOOTH; + linux,default-trigger = "hci0rx"; + default-state = "off"; + }; + }; + + /* + * RTC clock (XrtcXTI); external, must be 32.768 kHz. + * + * TODO: Remove this once RTC clock is implemented properly as part of + * PMIC driver. + */ + rtcclk: clock-rtcclk { + compatible = "fixed-clock"; + clock-output-names = "rtcclk"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; +}; + +&cmu_hsi { + clocks = <&oscclk>, <&rtcclk>, + <&cmu_top CLK_DOUT_HSI_BUS>, + <&cmu_top CLK_DOUT_HSI_MMC_CARD>, + <&cmu_top CLK_DOUT_HSI_USB20DRD>; + clock-names = "oscclk", "rtcclk", "dout_hsi_bus", + "dout_hsi_mmc_card", "dout_hsi_usb20drd"; +}; + +&mmc_0 { + status = "okay"; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + cap-mmc-highspeed; + non-removable; + mmc-hs400-enhanced-strobe; + card-detect-delay = <200>; + clock-frequency = <800000000>; + bus-width = <8>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <2 4>; + samsung,dw-mshc-hs400-timing = <0 2>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk_pins &sd0_cmd_pins &sd0_rdqs_pins &sd0_nreset_pins + &sd0_bus1_pins &sd0_bus4_pins &sd0_bus8_pins>; +}; + +&oscclk { + clock-frequency = <26000000>; +}; + +&pinctrl_alive { + key_voldown_pins: key-voldown-pins { + samsung,pins = "gpa1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + key_volup_pins: key-volup-pins { + samsung,pins = "gpa0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&rtc { + status = "okay"; + clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>, <&rtcclk>; + clock-names = "rtc", "rtc_src"; +}; + +&serial_0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + +&usi_uart { + samsung,clkreq-on; /* needed for UART mode */ + status = "okay"; +}; + +&watchdog_cl0 { + status = "okay"; +}; + +&watchdog_cl1 { + status = "okay"; +}; -- cgit From 2002c282cb89f5735bff14619b94e9c7328d3258 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 29 Jan 2022 18:53:28 +0100 Subject: arm64: dts: exynos: align pl330 node name with dtschema Fixes dtbs_check warnings like: pdma@15610000: $nodename:0: 'pdma@15610000' does not match '^dma-controller(@.*)?$' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Alim Akhtar Link: https://lore.kernel.org/r/20220129175332.298666-1-krzysztof.kozlowski@canonical.com --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 6 +++--- arch/arm64/boot/dts/exynos/exynos7.dtsi | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index bfe4ed8a23d6..b4cde77e02d3 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -1858,7 +1858,7 @@ status = "disabled"; }; - pdma0: pdma@15610000 { + pdma0: dma-controller@15610000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x15610000 0x1000>; interrupts = ; @@ -1869,7 +1869,7 @@ #dma-requests = <32>; }; - pdma1: pdma@15600000 { + pdma1: dma-controller@15600000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x15600000 0x1000>; interrupts = ; @@ -1891,7 +1891,7 @@ #size-cells = <1>; ranges; - adma: adma@11420000 { + adma: dma-controller@11420000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x11420000 0x1000>; interrupts = ; diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index 960823b8247a..3364b09c3158 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -142,7 +142,7 @@ <0x11006000 0x2000>; }; - pdma0: pdma@10e10000 { + pdma0: dma-controller@10e10000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x10E10000 0x1000>; interrupts = ; @@ -153,7 +153,7 @@ #dma-requests = <32>; }; - pdma1: pdma@10eb0000 { + pdma1: dma-controller@10eb0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x10EB0000 0x1000>; interrupts = ; -- cgit From ff72497f572844b8e5a787e27380576527f175af Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 29 Jan 2022 18:53:29 +0100 Subject: arm64: dts: exynos: drop unneeded syscon phandle in Exynos5433 LPASS Exynos5433 LPASS audio node does not use syscon phandle since commit addebf1588ab ("mfd: exynos-lpass: Remove pad retention control"). It was also dropped from bindings. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Alim Akhtar Link: https://lore.kernel.org/r/20220129175332.298666-2-krzysztof.kozlowski@canonical.com --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index b4cde77e02d3..661567d2dd7a 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -1885,7 +1885,6 @@ reg = <0x11400000 0x100>, <0x11500000 0x08>; clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>; clock-names = "sfr0_ctrl"; - samsung,pmu-syscon = <&pmu_system_controller>; power-domains = <&pd_aud>; #address-cells = <1>; #size-cells = <1>; -- cgit From 1b968998a3cbd346e7b01a5b41f4c88b979ae7d5 Mon Sep 17 00:00:00 2001 From: Sandeep Maheswaram Date: Thu, 2 Dec 2021 10:47:28 +0530 Subject: arm64: dts: qcom: sc7280: Move USB2 controller nodes from common dtsi to SKU1 Move USB2 controller and phy nodes from common dtsi file as it is required only for SKU1 board and change the mode to host mode as it will be used in host mode for SKU1. Signed-off-by: Sandeep Maheswaram Reviewed-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1638422248-24221-1-git-send-email-quic_c_sanm@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280-idp.dts | 16 ++++++++++++++++ arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 16 ---------------- 2 files changed, 16 insertions(+), 16 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts index 19bd228760ed..a7be133a782f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts @@ -84,3 +84,19 @@ qcom,pre-scaling = <1 1>; }; }; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; + +&usb_2_hsphy { + status = "okay"; + + vdda-pll-supply = <&vreg_l10c_0p8>; + vdda33-supply = <&vreg_l2b_3p0>; + vdda18-supply = <&vreg_l1c_1p8>; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index a146d0ddad0f..e5cd0129ad10 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -403,22 +403,6 @@ vdda-pll-supply = <&vreg_l1b_0p8>; }; -&usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { - dr_mode = "peripheral"; -}; - -&usb_2_hsphy { - status = "okay"; - - vdda-pll-supply = <&vreg_l10c_0p8>; - vdda33-supply = <&vreg_l2b_3p0>; - vdda18-supply = <&vreg_l1c_1p8>; -}; - &uart7 { status = "okay"; -- cgit From bb59462e414f8c0c55800064e9be4c596ae6898d Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 15 Dec 2021 20:45:29 -0800 Subject: arm64: dts: qcom: sc7180: Add board regulators for MIPI camera trogdor boards Some trogdor boards have on-board regulators for the MIPI camera components. Add nodes describing these regulators so boards with these supplies can consume them. Cc: Douglas Anderson Cc: Matthias Kaehlcke Signed-off-by: Stephen Boyd Reviewed-by: Douglas Anderson Reviewed-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211216044529.733652-1-swboyd@chromium.org --- .../arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi | 16 +++ .../boot/dts/qcom/sc7180-trogdor-homestar.dtsi | 16 +++ arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 122 +++++++++++++++++++++ 3 files changed, 154 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi index 14ed09f30a73..c81805ef2250 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi @@ -142,6 +142,22 @@ ap_ts_pen_1v8: &i2c4 { }; }; +&pp1800_uf_cam { + status = "okay"; +}; + +&pp1800_wf_cam { + status = "okay"; +}; + +&pp2800_uf_cam { + status = "okay"; +}; + +&pp2800_wf_cam { + status = "okay"; +}; + &pp3300_dx_edp { gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi index f32369af1351..bff2b556cc75 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi @@ -146,6 +146,22 @@ ap_ts_pen_1v8: &i2c4 { }; }; +&pp1800_uf_cam { + status = "okay"; +}; + +&pp1800_wf_cam { + status = "okay"; +}; + +&pp2800_uf_cam { + status = "okay"; +}; + +&pp2800_wf_cam { + status = "okay"; +}; + &pp3300_dx_edp { gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index bd5909ffb3dc..7d8bf66e8ffe 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -144,6 +144,100 @@ vin-supply = <&ppvar_sys>; }; + pp1800_ec: + pp1800_sensors: + pp1800_ldo: pp1800-ldo-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp1800_ldo"; + + /* EC turns on with hibernate_l; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + /* + * Actually should be pp1800_h1 but we don't have any need to + * model that so we use the parent of pp1800_h1. + */ + vin-supply = <&pp3300_a>; + }; + + pp1800_uf_cam: pp1800-uf-cam-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp1800_uf_cam"; + status = "disabled"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&uf_cam_en>; + + vin-supply = <&pp1800_ldo>; + regulator-enable-ramp-delay = <1000>; + }; + + pp1800_wf_cam: pp1800-wf-cam-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp1800_wf_cam"; + status = "disabled"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&wf_cam_en>; + + vin-supply = <&pp1800_ldo>; + regulator-enable-ramp-delay = <1000>; + }; + + pp2800_uf_cam: pp2800-uf-cam-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp2800_uf_cam"; + status = "disabled"; + + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + + gpio = <&tlmm 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * The pinconf can only be referenced once so we put it on the + * first regulator and comment it out here. + * pinctrl-names = "default"; + * pinctrl-0 = <&uf_cam_en>; + */ + + vin-supply = <&pp3300_a>; + }; + + pp2800_vcm_wf_cam: + pp2800_wf_cam: pp2800-wf-cam-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp2800_wf_cam"; + status = "disabled"; + + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + + gpio = <&tlmm 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * The pinconf can only be referenced once so we put it on the + * first regulator and comment it out here. + * pinctrl-names = "default"; + * pinctrl-0 = <&wf_cam_en>; + */ + + vin-supply = <&pp3300_a>; + }; + pp3300_audio: pp3300_codec: pp3300-codec-regulator { compatible = "regulator-fixed"; @@ -1521,4 +1615,32 @@ ap_spi_fp: &spi10 { drive-strength = <2>; }; }; + + uf_cam_en: uf-cam-en { + pinmux { + pins = "gpio6"; + function = "gpio"; + }; + + pinconf { + pins = "gpio6"; + drive-strength = <2>; + /* External pull down */ + bias-disable; + }; + }; + + wf_cam_en: wf-cam-en { + pinmux { + pins = "gpio7"; + function = "gpio"; + }; + + pinconf { + pins = "gpio7"; + drive-strength = <2>; + /* External pull down */ + bias-disable; + }; + }; }; -- cgit From fcb68dfda5cbd816d27ac50c287833848874f61c Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Fri, 24 Dec 2021 21:33:10 +0530 Subject: arm64: dts: qcom: sc7280: add display dt nodes Add mdss and mdp DT nodes for sc7280. Signed-off-by: Krishna Manikandan Reviewed-by: Stephen Boyd Signed-off-by: Sankeerth Billakanti Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1640361793-26486-2-git-send-email-quic_sbillaka@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 90 ++++++++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 937c2e0e93eb..d138f9ded9a3 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2779,6 +2779,96 @@ #power-domain-cells = <1>; }; + mdss: display-subsystem@ae00000 { + compatible = "qcom,sc7280-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", + "ahb", + "core"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + assigned-clock-rates = <300000000>; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "mdp0-mem"; + + iommus = <&apps_smmu 0x900 0x402>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,sc7280-dpu"; + reg = <0 0x0ae01000 0 0x8f030>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>; + assigned-clock-rates = <300000000>, + <19200000>, + <19200000>; + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SC7280_CX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + status = "disabled"; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-380000000 { + opp-hz = /bits/ 64 <380000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-506666667 { + opp-hz = /bits/ 64 <506666667>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sc7280-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>; -- cgit From 43137272f0bc5e05e4c4c6f7bfce017bfb9e16b5 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Fri, 24 Dec 2021 21:33:11 +0530 Subject: arm64: dts: qcom: sc7280: Add DSI display nodes Add DSI controller and PHY nodes for sc7280. Signed-off-by: Rajeev Nandan Signed-off-by: Krishna Manikandan Reviewed-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd Signed-off-by: Sankeerth Billakanti Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1640361793-26486-3-git-send-email-quic_sbillaka@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 111 ++++++++++++++++++++++++++++++++++- 1 file changed, 109 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index d138f9ded9a3..fe53e0bed136 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2766,8 +2766,14 @@ reg = <0 0xaf00000 0 0x20000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_DISP_GPLL0_CLK_SRC>, - <0>, <0>, <0>, <0>, <0>, <0>; - clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", + <&mdss_dsi_phy 0>, + <&mdss_dsi_phy 1>, + <0>, + <0>, + <0>, + <0>; + clock-names = "bi_tcxo", + "gcc_disp_gpll0_clk", "dsi0_phy_pll_out_byteclk", "dsi0_phy_pll_out_dsiclk", "dp_phy_pll_link_clk", @@ -2843,6 +2849,18 @@ status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + mdp_opp_table: opp-table { compatible = "operating-points-v2"; @@ -2867,6 +2885,95 @@ }; }; }; + + mdss_dsi: dsi@ae94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SC7280_CX>; + + phys = <&mdss_dsi_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + + dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi_phy: phy@ae94400 { + compatible = "qcom,sc7280-dsi-phy-7nm"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94900 0 0x280>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; }; pdc: interrupt-controller@b220000 { -- cgit From 25940788d170251373d8975d359706350818fa0f Mon Sep 17 00:00:00 2001 From: Sankeerth Billakanti Date: Fri, 24 Dec 2021 21:33:12 +0530 Subject: arm64: dts: qcom: sc7280: add edp display dt nodes Add edp controller and phy DT nodes for sc7280. Signed-off-by: Sankeerth Billakanti Signed-off-by: Krishna Manikandan Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1640361793-26486-4-git-send-email-quic_sbillaka@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 107 ++++++++++++++++++++++++++++++++++- 1 file changed, 105 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index fe53e0bed136..ba4dc230e037 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2770,8 +2770,8 @@ <&mdss_dsi_phy 1>, <0>, <0>, - <0>, - <0>; + <&mdss_edp_phy 0>, + <&mdss_edp_phy 1>; clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", "dsi0_phy_pll_out_byteclk", @@ -2859,6 +2859,13 @@ remote-endpoint = <&dsi0_in>; }; }; + + port@1 { + reg = <1>; + dpu_intf5_out: endpoint { + remote-endpoint = <&edp_in>; + }; + }; }; mdp_opp_table: opp-table { @@ -2974,6 +2981,102 @@ status = "disabled"; }; + + mdss_edp: edp@aea0000 { + compatible = "qcom,sc7280-edp"; + + reg = <0 0xaea0000 0 0x200>, + <0 0xaea0200 0 0x200>, + <0 0xaea0400 0 0xc00>, + <0 0xaea1000 0 0x400>; + + interrupt-parent = <&mdss>; + interrupts = <14>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_EDP_CLKREF_EN>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; + clock-names = "core_xo", + "core_ref", + "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + #clock-cells = <1>; + assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; + assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; + + phys = <&mdss_edp_phy>; + phy-names = "dp"; + + operating-points-v2 = <&edp_opp_table>; + power-domains = <&rpmhpd SC7280_CX>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + edp_in: endpoint { + remote-endpoint = <&dpu_intf5_out>; + }; + }; + }; + + edp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_edp_phy: phy@aec2a00 { + compatible = "qcom,sc7280-edp-phy"; + + reg = <0 0xaec2a00 0 0x19c>, + <0 0xaec2200 0 0xa0>, + <0 0xaec2600 0 0xa0>, + <0 0xaec2000 0 0x1c0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_EDP_CLKREF_EN>; + clock-names = "aux", + "cfg_ahb"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; }; pdc: interrupt-controller@b220000 { -- cgit From fc6b1225d20de0298a7b0e52eb3843d71e1992e8 Mon Sep 17 00:00:00 2001 From: Kuogee Hsieh Date: Fri, 24 Dec 2021 21:33:13 +0530 Subject: arm64: dts: qcom: sc7280: Add Display Port node Signed-off-by: Kuogee Hsieh Reviewed-by: Stephen Boyd Signed-off-by: Sankeerth Billakanti Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1640361793-26486-5-git-send-email-quic_sbillaka@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 90 +++++++++++++++++++++++++++++++++++- 1 file changed, 88 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index ba4dc230e037..5b9312ddf5cf 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2768,8 +2768,8 @@ <&gcc GCC_DISP_GPLL0_CLK_SRC>, <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>, - <0>, - <0>, + <&dp_phy 0>, + <&dp_phy 1>, <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; clock-names = "bi_tcxo", @@ -2866,6 +2866,13 @@ remote-endpoint = <&edp_in>; }; }; + + port@2 { + reg = <2>; + dpu_intf0_out: endpoint { + remote-endpoint = <&dp_in>; + }; + }; }; mdp_opp_table: opp-table { @@ -3077,6 +3084,79 @@ status = "disabled"; }; + + mdss_dp: displayport-controller@ae90000 { + compatible = "qcom,sc7280-dp"; + + reg = <0 0x0ae90000 0 0x1400>; + + interrupt-parent = <&mdss>; + interrupts = <12>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + #clock-cells = <1>; + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; + phys = <&dp_phy>; + phy-names = "dp"; + + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd SC7280_CX>; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dp_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + dp_out: endpoint { }; + }; + }; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; }; pdc: interrupt-controller@b220000 { @@ -3179,6 +3259,12 @@ bias-pull-up; }; + dp_hot_plug_det: dp-hot-plug-det { + pins = "gpio47"; + function = "dp_hot"; + bias-disable; + }; + qspi_clk: qspi-clk { pins = "gpio14"; function = "qspi_clk"; -- cgit From 7b1e0a87730e32aac0089182c8cfe3b5fa6434fb Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Tue, 25 Jan 2022 00:14:37 +0530 Subject: arm64: dts: qcom: sc7280: Add camcc clock node Add the camera clock controller node for SC7280 SoC. Signed-off-by: Taniya Das Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220124184437.9278-1-tdas@codeaurora.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 5b9312ddf5cf..6840196d6224 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -4,7 +4,7 @@ * * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. */ - +#include #include #include #include @@ -2761,6 +2761,18 @@ #power-domain-cells = <1>; }; + camcc: clock-controller@ad00000 { + compatible = "qcom,sc7280-camcc"; + reg = <0 0x0ad00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + dispcc: clock-controller@af00000 { compatible = "qcom,sc7280-dispcc"; reg = <0 0xaf00000 0 0x20000>; -- cgit From 142a4d995c6adb6bf5b22166f51b525e83c96661 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Tue, 25 Jan 2022 14:44:18 -0800 Subject: arm64: dts: qcom: sc7280: Fix gmu unit address When processing sc7280 device trees, I can see: Warning (simple_bus_reg): /soc@0/gmu@3d69000: simple-bus unit address format error, expected "3d6a000" There's a clear typo in the node name. Fix it. Fixes: 96c471970b7b ("arm64: dts: qcom: sc7280: Add gpu support") Signed-off-by: Douglas Anderson Reviewed-by: Stephen Boyd Reviewed-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220125144316.v2.1.I19f60014e9be4b9dda4d66b5d56ef3d9600b6e10@changeid --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 6840196d6224..a1b0d23a350b 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -1790,7 +1790,7 @@ }; }; - gmu: gmu@3d69000 { + gmu: gmu@3d6a000 { compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; reg = <0 0x03d6a000 0 0x34000>, <0 0x3de0000 0 0x10000>, -- cgit From 61a6262f95e0c400baee59ced0721f49ffca604c Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Tue, 25 Jan 2022 14:44:19 -0800 Subject: arm64: dts: qcom: sc7280: Move herobrine-r0 to its own dts The upcoming herobrine-r1 board is really not very similar to herobrine-r0. Let's get rid of the "herobrine.dtsi" file and stick all the content in the -r0 dts file directly. We'll also rename the dts so it's obvious that it's just for -r0. While renaming, let's actually name the file so it's obvious that "herobrine" is both the name of the board and the name of the "baseboard". In other words "herobrine" is an actual board but also often used as the name of a whole class of similar boards that forked from a design. While "herobrine-herobrine" is a bit of mouthful it makes it more obvious which things are part of an actual board rather than the baseboard. NOTE: herobrine-rev0's days are likely doomed and this device tree is likely to be deleted in the future. Signed-off-by: Douglas Anderson Reviewed-by: Stephen Boyd Reviewed-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220125144316.v2.2.Id9716db8c133bcb14c9413144048f8d00ae2674f@changeid --- arch/arm64/boot/dts/qcom/Makefile | 2 +- .../dts/qcom/sc7280-herobrine-herobrine-r0.dts | 1418 ++++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7280-herobrine.dts | 14 - arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 1412 ------------------- 4 files changed, 1419 insertions(+), 1427 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts delete mode 100644 arch/arm64/boot/dts/qcom/sc7280-herobrine.dts delete mode 100644 arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index f7232052d286..9db743826391 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -82,7 +82,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r0.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp2.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-crd.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts new file mode 100644 index 000000000000..8676c93590b5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts @@ -0,0 +1,1418 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Herobrine board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include + +#include "sc7280.dtsi" + +/* PMICs depend on spmi_bus label and so must come after SoC */ +#include "pm7325.dtsi" +#include "pm8350c.dtsi" +#include "pmk8350.dtsi" + +/ { + model = "Google Herobrine (rev0)"; + compatible = "google,herobrine", + "qcom,sc7280"; +}; + +/* + * Reserved memory changes + * + * Delete all unused memory nodes and define the peripheral memory regions + * required by the board dts. + * + */ + +/delete-node/ &hyp_mem; +/delete-node/ &xbl_mem; +/delete-node/ &sec_apps_mem; + +/* Increase the size from 2MB to 8MB */ +&rmtfs_mem { + reg = <0x0 0x83600000 0x0 0x800000>; +}; + +/ { + reserved-memory { + adsp_mem: memory@86700000 { + reg = <0x0 0x86700000 0x0 0x2800000>; + no-map; + }; + + camera_mem: memory@8ad00000 { + reg = <0x0 0x8ad00000 0x0 0x500000>; + no-map; + }; + + venus_mem: memory@8b200000 { + reg = <0x0 0x8b200000 0x0 0x500000>; + no-map; + }; + + mpss_mem: memory@8b800000 { + reg = <0x0 0x8b800000 0x0 0xf600000>; + no-map; + }; + + wpss_mem: memory@9ae00000 { + reg = <0x0 0x9ae00000 0x0 0x1900000>; + no-map; + }; + + mba_mem: memory@9c700000 { + reg = <0x0 0x9c700000 0x0 0x200000>; + no-map; + }; + }; + + aliases { + serial0 = &uart5; + serial1 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + /* FIXED REGULATORS - parents above children */ + + /* This is the top level supply and variable voltage */ + ppvar_sys: ppvar-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "ppvar_sys"; + regulator-always-on; + regulator-boot-on; + }; + + /* This divides ppvar_sys by 2, so voltage is variable */ + src_vph_pwr: src-vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "src_vph_pwr"; + + /* EC turns on with switchcap_on; always on for AP */ + regulator-always-on; + regulator-boot-on; + + vin-supply = <&ppvar_sys>; + }; + + pp5000_s3: pp5000-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp5000_s3"; + + /* EC turns on with en_pp5000_s3; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + vin-supply = <&ppvar_sys>; + }; + + pp3300_z1: pp3300-z1-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp3300_z1"; + + /* EC turns on with en_pp3300_z1; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + vin-supply = <&ppvar_sys>; + }; + + pp3300_audio: + pp3300_codec: pp3300-codec-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp3300_codec"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&en_pp3300_codec>; + + vin-supply = <&pp3300_z1>; + }; + + pp3300_cam: + pp3300_edp: + pp3300_ts: pp3300-edp-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp3300_edp"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 80 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&en_pp3300_dx_edp>; + + vin-supply = <&pp3300_z1>; + }; + + pp3300_fp: + pp3300_fp_ls: + pp3300_mcu: pp3300-fp-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp3300_fp"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-boot-on; + regulator-always-on; + + /* + * WARNING: it is intentional that GPIO 42 isn't listed here. + * The userspace script for updating the fingerprint firmware + * needs to control the FP regulators during a FW update, + * hence the signal can't be owned by the kernel regulator. + */ + + pinctrl-names = "default"; + pinctrl-0 = <&en_fp_rails>; + + vin-supply = <&pp3300_z1>; + }; + + pp3300_hub: pp3300-hub-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp3300_hub"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-boot-on; + regulator-always-on; + + gpio = <&tlmm 24 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&en_pp3300_hub>; + + vin-supply = <&pp3300_z1>; + }; + + pp3300_tp: pp3300-tp-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp3300_tp"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + /* AP turns on with PP1800_L18B_S0; always on for AP */ + regulator-always-on; + regulator-boot-on; + + vin-supply = <&pp3300_z1>; + }; + + pp2850_uf_cam: pp2850-uf-cam { + compatible = "regulator-fixed"; + regulator-name = "pp2850_uf_cam"; + + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + + gpio = <&tlmm 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&uf_cam_en>; + + vin-supply = <&pp3300_cam>; + }; + + pp2850_vcm_wf_cam: pp2850-vcm-wf-cam { + compatible = "regulator-fixed"; + regulator-name = "pp2850_vcm_wf_cam"; + + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + + gpio = <&tlmm 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&wf_cam_en>; + + vin-supply = <&pp3300_cam>; + }; + + pp2850_wf_cam: pp2850-wf-cam { + compatible = "regulator-fixed"; + regulator-name = "pp2850_wf_cam"; + + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + + gpio = <&tlmm 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * The pinconf can only be referenced once so we put it on the + * first regulator and comment it out here. + * + * pinctrl-names = "default"; + * pinctrl-0 = <&wf_cam_en>; + */ + + vin-supply = <&pp3300_cam>; + }; + + pp1800_fp: pp1800-fp-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp1800_fp"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-boot-on; + regulator-always-on; + + /* + * WARNING: it is intentional that GPIO 42 isn't listed here. + * The userspace script for updating the fingerprint firmware + * needs to control the FP regulators during a FW update, + * hence the signal can't be owned by the kernel regulator. + */ + + pinctrl-names = "default"; + pinctrl-0 = <&en_fp_rails>; + + vin-supply = <&pp1800_l18b_s0>; + status = "disabled"; + }; + + pp1800_uf_cam: pp1800-uf-cam { + compatible = "regulator-fixed"; + regulator-name = "pp1800_uf_cam"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * The pinconf can only be referenced once so we put it on the + * first regulator and comment it out here. + * + * pinctrl-names = "default"; + * pinctrl-0 = <&uf_cam_en>; + */ + + vin-supply = <&pp1800_l19b>; + }; + + pp1800_wf_cam: pp1800-wf-cam { + compatible = "regulator-fixed"; + regulator-name = "pp1800_wf_cam"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * The pinconf can only be referenced once so we put it on the + * first regulator and comment it out here. + * + * pinctrl-names = "default"; + * pinctrl-0 = <&wf_cam_en>; + */ + + vin-supply = <&pp1800_l19b>; + }; + + pp1200_wf_cam: pp1200-wf-cam { + compatible = "regulator-fixed"; + regulator-name = "pp1200_wf_cam"; + + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + gpio = <&tlmm 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * The pinconf can only be referenced once so we put it on the + * first regulator and comment it out here. + * + * pinctrl-names = "default"; + * pinctrl-0 = <&wf_cam_en>; + */ + + vin-supply = <&pp1200_l6b>; + }; + + /* BOARD-SPECIFIC TOP LEVEL NODES */ + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pen_pdct_l>; + + pen_insert: pen-insert { + label = "Pen Insert"; + + /* Insert = low, eject = high */ + gpios = <&tlmm 39 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + wakeup-event-action = ; + wakeup-source; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + status = "disabled"; + keyboard_backlight: keyboard-backlight { + status = "disabled"; + label = "cros_ec::kbd_backlight"; + pwms = <&cros_ec_pwm 0>; + max-brightness = <1023>; + }; + }; +}; + +&apps_rsc { + pm7325-regulators { + compatible = "qcom,pm7325-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd19_pmu_pcie_i: + vdd19_pmu_rfa_i: + vreg_s1b_wlan: + vreg_s1b: smps1 { + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2040000>; + }; + + vdd_pmu_aon_i: + vreg_s7b_wlan: + vreg_s7b: smps7 { + regulator-min-microvolt = <535000>; + regulator-max-microvolt = <1120000>; + }; + + vdd13_pmu_pcie_i: + vdd13_pmu_rfa_i: + vreg_s8b_wlan: + vreg_s8b: smps8 { + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1500000>; + }; + + vdda_usb_ss_dp_core: + vreg_l1b: ldo1 { + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <925000>; + regulator-initial-mode = ; + }; + + vdda_usb_hs0_3p1: + vreg_l2b: ldo2 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + pp1200_l6b: + vdd_ufs_1p2: + vdd_vref: + vdda_csi01_1p2: + vdda_csi23_1p2: + vdda_csi4_1p2: + vdda_dsi0_1p2: + vdda_pcie0_1p2: + vdda_pcie1_1p2: + vdda_usb_ss_dp_1p2: + vdda_qlink0_1p2_ck: + vdda_qlink1_1p2_ck: + vreg_l6b_1p2: + vreg_l6b: ldo6 { + regulator-min-microvolt = <1120000>; + regulator-max-microvolt = <1408000>; + regulator-initial-mode = ; + }; + + pp2950_l7b: + vreg_l7b: ldo7 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + codec_vcc: + pp1800_l18b_s0: + pp1800_ts: + vdd1: + vddpx_0: + vddpx_3: + vddpx_7: + vreg_l18b: ldo18 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + pp1800_l19b: + vddpx_ts: + vddpx_wl4otp: + vreg_l19b: ldo19 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + pm8350c-regulators { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_s1c: smps1 { + regulator-min-microvolt = <2190000>; + regulator-max-microvolt = <2210000>; + }; + + vddpx_1: + vreg_s9c: smps9 { + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + }; + + pp1800_l1c: + pp1800_pen: + vdd_a_gfx_cs_1p1: + vdd_a_cxo_1p8: + vdd_qfprom: + vdda_apc_cs_1p8: + vdda_qrefs_1p8: + vdda_turing_q6_cs_1p8: + vdda_usb_hs0_1p8: + vreg_l1c: ldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = ; + }; + + dmic_vdd: + pp1800_alc5682: + pp1800_l2c: + pp1800_vreg_alc5682: + vreg_l2c: ldo2 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = ; + }; + + pp3300_sar: + pp3300_sensor: + vreg_l3c: ldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3540000>; + regulator-initial-mode = ; + }; + + ppvar_uim1: + vddpx_5: + vreg_l4c: ldo4 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + pp2950_l5c: + uim_vcc: + vddpx_6: + vreg_l5c: ldo5 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + ppvar_l6c: + vddpx_2: + vreg_l6c: ldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-initial-mode = ; + }; + + vreg_l7c: ldo7 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + pp1800_prox: + pp1800_sar: + vreg_l8c: ldo8 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + pp2950_l9c: + vreg_l9c: ldo9 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vdd_a_gnss_0p9: + vdd_ufs_core: + vdd_usb_hs0_core: + vdd_vref_0p9: + vdda_csi01_0p9: + vdda_csi23_0p9: + vdda_csi4_0p9: + vdda_dsi0_pll_0p9: + vdda_dsi0_0p9: + vdda_pcie0_core: + vdda_pcie1_core: + vdda_qlink0_0p9: + vdda_qlink1_0p9: + vdda_qlink0_0p9_ck: + vdda_qlink1_0p9_ck: + vdda_qrefs_0p875: + vreg_l10c_0p8: + vreg_l10c: ldo10 { + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1050000>; + regulator-initial-mode = ; + }; + + pp2800_l11c: + vreg_l11c: ldo11 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + pp1800_l12c: + vreg_l12c: ldo12 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + pp3300_l13c: + vreg_l13c: ldo13 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_bob: bob { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + }; +}; + +ap_tp_i2c: &i2c1 { + status = "okay"; + clock-frequency = <400000>; + + trackpad: trackpad@15 { + compatible = "elan,ekth3000"; + reg = <0x15>; + pinctrl-names = "default"; + pinctrl-0 = <&tp_int_odl>; + + interrupt-parent = <&tlmm>; + interrupts = <102 IRQ_TYPE_EDGE_FALLING>; + + vcc-supply = <&pp3300_z1>; + + wakeup-source; + }; +}; + +ap_h1_i2c: &i2c12 { + status = "okay"; + clock-frequency = <400000>; + + tpm@50 { + compatible = "google,cr50"; + reg = <0x50>; + + pinctrl-names = "default"; + pinctrl-0 = <&h1_ap_int_odl>; + + interrupt-parent = <&tlmm>; + interrupts = <54 IRQ_TYPE_EDGE_RISING>; + }; +}; + +ap_ts_pen: &i2c13 { + status = "okay"; + clock-frequency = <400000>; + + ap_ts: touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; + + interrupt-parent = <&tlmm>; + interrupts = <81 IRQ_TYPE_LEVEL_LOW>; + + post-power-on-delay-ms = <20>; + hid-descr-addr = <0x0001>; + + vdd-supply = <&pp3300_ts>; + }; +}; + +&pm7325_gpios { + status = "disabled"; /* No GPIOs are connected */ +}; + +&pmk8350_gpios { + status = "disabled"; /* No GPIOs are connected */ +}; + +&pmk8350_pon { + status = "disabled"; +}; + +&pmk8350_rtc { + status = "disabled"; +}; + +&pmk8350_vadc { + pmk8350_die_temp { + reg = ; + label = "pmk8350_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + pmr735a_die_temp { + reg = ; + label = "pmr735a_die_temp"; + qcom,pre-scaling = <1 1>; + }; +}; + +&qfprom { + vcc-supply = <&vdd_qfprom>; +}; + +&qspi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + + spi-max-frequency = <37500000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + }; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&sdhc_1 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + vmmc-supply = <&pp2950_l7b>; + vqmmc-supply = <&pp1800_l19b>; +}; + +&sdhc_2 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + vmmc-supply = <&pp2950_l9c>; + vqmmc-supply = <&ppvar_l6c>; + + cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; +}; + +ap_ec_spi: &spi8 { + status = "okay"; + + pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs_gpio_init_high>, <&qup_spi8_cs_gpio>; + cs-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; + + cros_ec: ec@0 { + compatible = "google,cros-ec-spi"; + reg = <0>; + interrupt-parent = <&tlmm>; + interrupts = <142 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ap_ec_int_l>; + spi-max-frequency = <3000000>; + + cros_ec_pwm: ec-pwm { + compatible = "google,cros-ec-pwm"; + #pwm-cells = <1>; + }; + + i2c_tunnel: i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + google,remote-bus = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + typec { + compatible = "google,cros-ec-typec"; + #address-cells = <1>; + #size-cells = <0>; + + usb_c0: connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + label = "left"; + power-role = "dual"; + data-role = "host"; + try-power-role = "source"; + }; + + usb_c1: connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + label = "right"; + power-role = "dual"; + data-role = "host"; + try-power-role = "source"; + }; + }; + }; +}; + +#include +#include + +&keyboard_controller { + function-row-physmap = < + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + >; + linux,keymap = < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + + CROS_STD_MAIN_KEYMAP + >; +}; + +&uart5 { + compatible = "qcom,geni-debug-uart"; + status = "okay"; +}; + +&uart7 { + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "host"; +}; + +&usb_1_hsphy { + status = "okay"; + + vdda-pll-supply = <&vdd_usb_hs0_core>; + vdda33-supply = <&vdda_usb_hs0_3p1>; + vdda18-supply = <&vdda_usb_hs0_1p8>; +}; + +&usb_1_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vdda_usb_ss_dp_1p2>; + vdda-pll-supply = <&vdda_usb_ss_dp_core>; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; + +&usb_2_hsphy { + status = "okay"; + + vdda-pll-supply = <&vdd_usb_hs0_core>; + vdda33-supply = <&vdda_usb_hs0_3p1>; + vdda18-supply = <&vdda_usb_hs0_1p8>; +}; + +/* PINCTRL - additions to nodes defined in sc7280.dtsi */ + +&qspi_cs0 { + bias-disable; +}; + +&qspi_clk { + bias-disable; +}; + +&qspi_data01 { + /* High-Z when no transfers; nice to park the lines */ + bias-pull-up; +}; + +&qup_uart5_rx { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_uart5_tx { + drive-strength = <2>; + bias-disable; +}; + +&qup_uart7_cts { + /* + * Configure a pull-down on CTS to match the pull of + * the Bluetooth module. + */ + bias-pull-down; +}; + +&qup_uart7_rts { + /* We'll drive RTS, so no pull */ + drive-strength = <2>; + bias-disable; +}; + +&qup_uart7_tx { + /* We'll drive TX, so no pull */ + drive-strength = <2>; + bias-disable; +}; + +&qup_uart7_rx { + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module is + * in tri-state (module powered off or not driving the + * signal yet). + */ + bias-pull-up; +}; + +&sdc1_on { + clk { + bias-disable; + drive-strength = <16>; + }; + + cmd { + bias-pull-up; + drive-strength = <10>; + }; + + data { + bias-pull-up; + drive-strength = <10>; + }; + + rclk { + bias-pull-down; + }; +}; + +&sdc2_on { + clk { + bias-disable; + drive-strength = <16>; + }; + + cmd { + bias-pull-up; + drive-strength = <10>; + }; + + data { + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd { + pins = "gpio91"; + bias-pull-up; + }; +}; + +/* PINCTRL - board-specific pinctrl */ + +&pm8350c_gpios { + gpio-line-names = "AP_SUSPEND", + "", + "", + "AP_BL_EN", + "", + "SD_CD_ODL", + "", + "", + "AP_BL_PWM"; + + ap_bl_en: ap-bl-en { + pins = "gpio4"; + function = "normal"; + qcom,drive-strength = ; + bias-disable; + + /* Force backlight to be disabled to match state at boot. */ + output-low; + }; +}; + +&tlmm { + gpio-line-names = "HP_I2C_SDA", /* 0 */ + "HP_I2C_SCL", + "SSD_RST_L", + "PE_WAKE_ODL", + "AP_TP_I2C_SDA", + "AP_TP_I2C_SCL", + "UF_CAM_EN", + "WF_CAM_EN", + "AP_SAR_SENSOR_SDA", + "AP_SAR_SENSOR_SCL", + + "", /* 10 */ + "", + "AP_SPI_MOSI", + "AP_SPI_MISO", + "AP_SPI_CLK", + "AP_SPI_CS0_L", + "", + "", + "EDP_HPD", + "", + + "UF_CAM_RST_L", /* 20 */ + "WF_CAM_RST_L", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "EN_PP3300_HUB", + "", + "HOST2WLAN_SOL", + "WLAN2HOST_SOL", + "BT_UART_CTS", + "BT_UART_RTS", + + "BT_UART_TXD", /* 30 */ + "BT_UART_RXD", + "AP_EC_SPI_MISO", + "AP_EC_SPI_MOSI", + "AP_EC_SPI_CLK", + "AP_EC_SPI_CS_L", + "", + "", + "", + "PEN_PDCT_L", + + "IO_BRD_ID0", /* 40 */ + "IO_BRD_ID1", + "EN_FP_RAILS", + "PEN_IRQ_L", + "AP_SPI_FP_MISO", + "AP_SPI_FP_MOSI", + "AP_SPI_FP_CLK", + "AP_SPI_FP_CS_L", + "AP_H1_SPI_MISO", + "AP_H1_SPI_MOSI", + + "AP_H1_SPI_CLK", /* 50 */ + "AP_H1_SPI_CS_L", + "AP_TS_PEN_I2C_SDA", + "AP_TS_PEN_I2C_SCL", + "H1_AP_INT_ODL", + "", + "LCM_RST_1V8_L", + "AMP_EN", + "", + "DP_HOT_PLUG_DET", + + "HUB_RST_L", /* 60 */ + "FP_TO_AP_IRQ_L", + "", + "", + "UF_CAM_MCLK", + "WF_CAM_MCLK", + "IO_BRD_ID2", + "EN_PP3300_CODEC", + "EC_IN_RW_ODL", + "UF_CAM_SDA", + + "UF_CAM_SCL", /* 70 */ + "WF_CAM_SDA", + "WF_CAM_SCL", + "AP_BRD_ID0", + "AP_BRD_ID1", + "AP_BRD_ID2", + "", + "FPMCU_BOOT0", + "FP_RST_L", + "PE_CLKREQ_ODL", + + "EN_EDP_PP3300", /* 80 */ + "TS_INT_L", + "FORCE_USB_BOOT", + "WCD_RST_L", + "WLAN_EN", + "BT_EN", + "WLAN_SW_CTRL", + "PCIE0_RESET_L", + "PCIE0_CLK_REQ_L", + "PCIE0_WAKE_L", + + "AS_EN", /* 90 */ + "SD_CD_ODL", + "", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics + * call it BIOS_FLASH_WP_L. + */ + "AP_FLASH_WP_L", + "BT_WLAN_SB_CLK", + "BT_WLAN_SB_DATA", + "HP_MCLK", + "HP_BCLK", + "HP_DOUT", + "HP_DIN", + + "HP_LRCLK", /* 100 */ + "HP_IRQ", + "TP_INT_ODL", + "", + "IO_SKU_ID2", + "TS_RESET_L", + "AMP_BCLK", + "AMP_DIN", + "AMP_LRCLK", + "UIM2_DATA", + + "UIM2_CLK", /* 110 */ + "UIM2_RST", + "UIM2_PRESENT", + "UIM1_DATA", + "UIM1_CLK", + "UIM1_RST", + "", + "RFFE0_CLK", + "RFFE0_DATA/BOOT_CONFIG_0", + "RFFE1_CLK", + + "RFFE1_DATA/BOOT_CONFIG_1", /* 120 */ + "RFFE2_CLK", + "RFFE2_DATA/BOOT_CONFIG_2", + "RFFE3_CLK", + "RFFE3_DATA/BOOT_CONFIG_3", + "RFFE4_CLK", + "RFFE4_DATA", + "WCI2_LTE_COEX_RXD", + "WCI2_LTE_COEX_TXD", + "IO_SKU_ID0", + + "IO_SKU_ID1", /* 130 */ + "", + "", + "QLINK0_REQ", + "QLINK0_EN", + "QLINK0_WMSS_RESET_L", + "QLINK1_REQ", + "QLINK1_EN", + "QLINK1_WMSS_RESET_L", + "FORCED_USB_BOOT_POL", + + "", /* 140 */ + "P_SENSOR_INT_L", + "AP_EC_INT_L", + "", + "WCD_SWR_TX_CLK", + "WCD_SWR_TX_DATA_0", + "WCD_SWR_TX_DATA_1", + "WCD_SWR_RX_CLK", + "WCD_SWR_RX_DATA_0", + "WCD_SWR_RX_DATA_1", + + "", /* 150 */ + "", + "", + "", + "", + "", + "", + "", + "WCD_SWR_TX_DATA_2", + "", + + "", /* 160 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + + "", /* 170 */ + "SENS_UART_TXD", + "SENS_UART_RXD", + "", + "", + ""; + + /* + * pinctrl settings for pins that have no real owners. + */ + pinctrl-names = "default"; + pinctrl-0 = <&bios_flash_wp_l>; + + amp_en: amp-en { + pins = "gpio57"; + function = "gpio"; + bias-pull-down; + }; + + ap_ec_int_l: ap-ec-int-l { + pins = "gpio142"; + input-enable; + bias-pull-up; + }; + + bios_flash_wp_l: bios-flash-wp-l { + pins = "gpio93"; + function = "gpio"; + input-enable; + bias-disable; + }; + + bt_en: bt-en { + pins = "gpio85"; + function = "gpio"; + drive-strength = <2>; + output-low; + bias-pull-down; + }; + + en_fp_rails: en-fp-rails { + pins = "gpio42"; + drive-strength = <2>; + output-high; + bias-disable; + }; + + en_pp3300_codec: en-pp3300-codec { + pins = "gpio67"; + drive-strength = <2>; + bias-disable; + }; + + en_pp3300_dx_edp: en-pp3300-dx-edp { + pins = "gpio80"; + function = "gpio"; + drive-strength = <2>; + /* Has external pulldown */ + bias-disable; + }; + + en_pp3300_hub: en-pp3300-hub { + pins = "gpio24"; + function = "gpio"; + drive-strength = <2>; + /* Has external pulldown */ + bias-disable; + }; + + fp_to_ap_irq_l: fp-to-ap-irq-l { + pins = "gpio61"; + function = "gpio"; + input-enable; + /* Has external pullup */ + bias-disable; + }; + + h1_ap_int_odl: h1-ap-int-odl { + pins = "gpio54"; + function = "gpio"; + input-enable; + bias-pull-up; + }; + + hp_irq: hp-irq { + pins = "gpio101"; + function = "gpio"; + bias-pull-up; + }; + + p_sensor_int_l: p-sensor-int-l { + pins = "gpio141"; + function = "gpio"; + input-enable; + bias-pull-up; + }; + + pen_irq_l: pen-irq-l { + pins = "gpio43"; + function = "gpio"; + /* Has external pullup */ + bias-disable; + }; + + pen_pdct_l: pen-pdct-l { + pins = "gpio39"; + function = "gpio"; + /* Has external pullup */ + bias-disable; + }; + + qup_spi8_cs_gpio_init_high: qup-spi8-cs-gpio-init-high { + pins = "gpio35"; + output-high; + }; + + qup_spi11_cs_gpio_init_high: qup-spi11-cs-gpio-init-high { + pins = "gpio47"; + output-high; + }; + + qup_spi12_cs_gpio_init_high: qup-spi12-cs-gpio-init-high { + pins = "gpio51"; + output-high; + }; + + qup_uart7_sleep_cts: qup-uart7-sleep-cts { + pins = "gpio28"; + function = "gpio"; + /* + * Configure a pull-down on CTS to match the pull of + * the Bluetooth module. + */ + bias-pull-down; + }; + + qup_uart7_sleep_rts: qup-uart7-sleep-rts { + pins = "gpio29"; + function = "gpio"; + /* + * Configure pull-down on RTS. As RTS is active low + * signal, pull it low to indicate the BT SoC that it + * can wakeup the system anytime from suspend state by + * pulling RX low (by sending wakeup bytes). + */ + bias-pull-down; + }; + + qup_uart7_sleep_rx: qup-uart7-sleep-rx { + pins = "gpio31"; + function = "gpio"; + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module + * is floating which may cause spurious wakeups. + */ + bias-pull-up; + }; + + qup_uart7_sleep_tx: qup-uart7-sleep-tx { + pins = "gpio30"; + function = "gpio"; + /* + * Configure pull-up on TX when it isn't actively driven + * to prevent BT SoC from receiving garbage during sleep. + */ + bias-pull-up; + }; + + tp_int_odl: tp-int-odl { + pins = "gpio102"; + function = "gpio"; + /* Has external pullup */ + bias-disable; + }; + + ts_int_l: ts-int-l { + pins = "gpio81"; + function = "gpio"; + /* Has external pullup */ + bias-pull-up; + }; + + ts_reset_l: ts-reset-l { + pins = "gpio105"; + function = "gpio"; + /* Has external pullup */ + bias-disable; + drive-strength = <2>; + }; + + uf_cam_en: uf-cam-en { + pins = "gpio6"; + function = "gpio"; + drive-strength = <2>; + /* Has external pulldown */ + bias-disable; + }; + + wf_cam_en: wf-cam-en { + pins = "gpio7"; + function = "gpio"; + drive-strength = <2>; + /* Has external pulldown */ + bias-disable; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dts deleted file mode 100644 index 7a92679a688b..000000000000 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Herobrine board device tree source - * - * Copyright 2021 Google LLC. - */ - -#include "sc7280-herobrine.dtsi" - -/ { - model = "Google Herobrine"; - compatible = "google,herobrine", - "qcom,sc7280"; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi deleted file mode 100644 index 4619fa9fcacd..000000000000 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ /dev/null @@ -1,1412 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Herobrine board device tree source - * - * Copyright 2021 Google LLC. - */ - -/dts-v1/; - -#include -#include -#include -#include -#include -#include -#include - -#include "sc7280.dtsi" - -/* PMICs depend on spmi_bus label and so must come after SoC */ -#include "pm7325.dtsi" -#include "pm8350c.dtsi" -#include "pmk8350.dtsi" - -/* - * Reserved memory changes - * - * Delete all unused memory nodes and define the peripheral memory regions - * required by the board dts. - * - */ - -/delete-node/ &hyp_mem; -/delete-node/ &xbl_mem; -/delete-node/ &sec_apps_mem; - -/* Increase the size from 2MB to 8MB */ -&rmtfs_mem { - reg = <0x0 0x83600000 0x0 0x800000>; -}; - -/ { - reserved-memory { - adsp_mem: memory@86700000 { - reg = <0x0 0x86700000 0x0 0x2800000>; - no-map; - }; - - camera_mem: memory@8ad00000 { - reg = <0x0 0x8ad00000 0x0 0x500000>; - no-map; - }; - - venus_mem: memory@8b200000 { - reg = <0x0 0x8b200000 0x0 0x500000>; - no-map; - }; - - mpss_mem: memory@8b800000 { - reg = <0x0 0x8b800000 0x0 0xf600000>; - no-map; - }; - - wpss_mem: memory@9ae00000 { - reg = <0x0 0x9ae00000 0x0 0x1900000>; - no-map; - }; - - mba_mem: memory@9c700000 { - reg = <0x0 0x9c700000 0x0 0x200000>; - no-map; - }; - }; - - aliases { - serial0 = &uart5; - serial1 = &uart7; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - /* FIXED REGULATORS - parents above children */ - - /* This is the top level supply and variable voltage */ - ppvar_sys: ppvar-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "ppvar_sys"; - regulator-always-on; - regulator-boot-on; - }; - - /* This divides ppvar_sys by 2, so voltage is variable */ - src_vph_pwr: src-vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "src_vph_pwr"; - - /* EC turns on with switchcap_on; always on for AP */ - regulator-always-on; - regulator-boot-on; - - vin-supply = <&ppvar_sys>; - }; - - pp5000_s3: pp5000-s3-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp5000_s3"; - - /* EC turns on with en_pp5000_s3; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - vin-supply = <&ppvar_sys>; - }; - - pp3300_z1: pp3300-z1-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp3300_z1"; - - /* EC turns on with en_pp3300_z1; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - vin-supply = <&ppvar_sys>; - }; - - pp3300_audio: - pp3300_codec: pp3300-codec-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp3300_codec"; - - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&en_pp3300_codec>; - - vin-supply = <&pp3300_z1>; - }; - - pp3300_cam: - pp3300_edp: - pp3300_ts: pp3300-edp-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp3300_edp"; - - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 80 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&en_pp3300_dx_edp>; - - vin-supply = <&pp3300_z1>; - }; - - pp3300_fp: - pp3300_fp_ls: - pp3300_mcu: pp3300-fp-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp3300_fp"; - - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-boot-on; - regulator-always-on; - - /* - * WARNING: it is intentional that GPIO 42 isn't listed here. - * The userspace script for updating the fingerprint firmware - * needs to control the FP regulators during a FW update, - * hence the signal can't be owned by the kernel regulator. - */ - - pinctrl-names = "default"; - pinctrl-0 = <&en_fp_rails>; - - vin-supply = <&pp3300_z1>; - }; - - pp3300_hub: pp3300-hub-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp3300_hub"; - - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-boot-on; - regulator-always-on; - - gpio = <&tlmm 24 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&en_pp3300_hub>; - - vin-supply = <&pp3300_z1>; - }; - - pp3300_tp: pp3300-tp-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp3300_tp"; - - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - /* AP turns on with PP1800_L18B_S0; always on for AP */ - regulator-always-on; - regulator-boot-on; - - vin-supply = <&pp3300_z1>; - }; - - pp2850_uf_cam: pp2850-uf-cam { - compatible = "regulator-fixed"; - regulator-name = "pp2850_uf_cam"; - - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - - gpio = <&tlmm 6 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&uf_cam_en>; - - vin-supply = <&pp3300_cam>; - }; - - pp2850_vcm_wf_cam: pp2850-vcm-wf-cam { - compatible = "regulator-fixed"; - regulator-name = "pp2850_vcm_wf_cam"; - - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - - gpio = <&tlmm 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&wf_cam_en>; - - vin-supply = <&pp3300_cam>; - }; - - pp2850_wf_cam: pp2850-wf-cam { - compatible = "regulator-fixed"; - regulator-name = "pp2850_wf_cam"; - - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - - gpio = <&tlmm 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - /* - * The pinconf can only be referenced once so we put it on the - * first regulator and comment it out here. - * - * pinctrl-names = "default"; - * pinctrl-0 = <&wf_cam_en>; - */ - - vin-supply = <&pp3300_cam>; - }; - - pp1800_fp: pp1800-fp-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp1800_fp"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - regulator-always-on; - - /* - * WARNING: it is intentional that GPIO 42 isn't listed here. - * The userspace script for updating the fingerprint firmware - * needs to control the FP regulators during a FW update, - * hence the signal can't be owned by the kernel regulator. - */ - - pinctrl-names = "default"; - pinctrl-0 = <&en_fp_rails>; - - vin-supply = <&pp1800_l18b_s0>; - status = "disabled"; - }; - - pp1800_uf_cam: pp1800-uf-cam { - compatible = "regulator-fixed"; - regulator-name = "pp1800_uf_cam"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - gpio = <&tlmm 6 GPIO_ACTIVE_HIGH>; - enable-active-high; - /* - * The pinconf can only be referenced once so we put it on the - * first regulator and comment it out here. - * - * pinctrl-names = "default"; - * pinctrl-0 = <&uf_cam_en>; - */ - - vin-supply = <&pp1800_l19b>; - }; - - pp1800_wf_cam: pp1800-wf-cam { - compatible = "regulator-fixed"; - regulator-name = "pp1800_wf_cam"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - gpio = <&tlmm 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - /* - * The pinconf can only be referenced once so we put it on the - * first regulator and comment it out here. - * - * pinctrl-names = "default"; - * pinctrl-0 = <&wf_cam_en>; - */ - - vin-supply = <&pp1800_l19b>; - }; - - pp1200_wf_cam: pp1200-wf-cam { - compatible = "regulator-fixed"; - regulator-name = "pp1200_wf_cam"; - - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - - gpio = <&tlmm 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - /* - * The pinconf can only be referenced once so we put it on the - * first regulator and comment it out here. - * - * pinctrl-names = "default"; - * pinctrl-0 = <&wf_cam_en>; - */ - - vin-supply = <&pp1200_l6b>; - }; - - /* BOARD-SPECIFIC TOP LEVEL NODES */ - - gpio_keys: gpio-keys { - compatible = "gpio-keys"; - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&pen_pdct_l>; - - pen_insert: pen-insert { - label = "Pen Insert"; - - /* Insert = low, eject = high */ - gpios = <&tlmm 39 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - wakeup-event-action = ; - wakeup-source; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - status = "disabled"; - keyboard_backlight: keyboard-backlight { - status = "disabled"; - label = "cros_ec::kbd_backlight"; - pwms = <&cros_ec_pwm 0>; - max-brightness = <1023>; - }; - }; -}; - -&apps_rsc { - pm7325-regulators { - compatible = "qcom,pm7325-rpmh-regulators"; - qcom,pmic-id = "b"; - - vdd19_pmu_pcie_i: - vdd19_pmu_rfa_i: - vreg_s1b_wlan: - vreg_s1b: smps1 { - regulator-min-microvolt = <1856000>; - regulator-max-microvolt = <2040000>; - }; - - vdd_pmu_aon_i: - vreg_s7b_wlan: - vreg_s7b: smps7 { - regulator-min-microvolt = <535000>; - regulator-max-microvolt = <1120000>; - }; - - vdd13_pmu_pcie_i: - vdd13_pmu_rfa_i: - vreg_s8b_wlan: - vreg_s8b: smps8 { - regulator-min-microvolt = <1256000>; - regulator-max-microvolt = <1500000>; - }; - - vdda_usb_ss_dp_core: - vreg_l1b: ldo1 { - regulator-min-microvolt = <825000>; - regulator-max-microvolt = <925000>; - regulator-initial-mode = ; - }; - - vdda_usb_hs0_3p1: - vreg_l2b: ldo2 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3544000>; - regulator-initial-mode = ; - }; - - pp1200_l6b: - vdd_ufs_1p2: - vdd_vref: - vdda_csi01_1p2: - vdda_csi23_1p2: - vdda_csi4_1p2: - vdda_dsi0_1p2: - vdda_pcie0_1p2: - vdda_pcie1_1p2: - vdda_usb_ss_dp_1p2: - vdda_qlink0_1p2_ck: - vdda_qlink1_1p2_ck: - vreg_l6b_1p2: - vreg_l6b: ldo6 { - regulator-min-microvolt = <1120000>; - regulator-max-microvolt = <1408000>; - regulator-initial-mode = ; - }; - - pp2950_l7b: - vreg_l7b: ldo7 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - codec_vcc: - pp1800_l18b_s0: - pp1800_ts: - vdd1: - vddpx_0: - vddpx_3: - vddpx_7: - vreg_l18b: ldo18 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2000000>; - regulator-initial-mode = ; - }; - - pp1800_l19b: - vddpx_ts: - vddpx_wl4otp: - vreg_l19b: ldo19 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - }; - - pm8350c-regulators { - compatible = "qcom,pm8350c-rpmh-regulators"; - qcom,pmic-id = "c"; - - vreg_s1c: smps1 { - regulator-min-microvolt = <2190000>; - regulator-max-microvolt = <2210000>; - }; - - vddpx_1: - vreg_s9c: smps9 { - regulator-min-microvolt = <1010000>; - regulator-max-microvolt = <1170000>; - }; - - pp1800_l1c: - pp1800_pen: - vdd_a_gfx_cs_1p1: - vdd_a_cxo_1p8: - vdd_qfprom: - vdda_apc_cs_1p8: - vdda_qrefs_1p8: - vdda_turing_q6_cs_1p8: - vdda_usb_hs0_1p8: - vreg_l1c: ldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1980000>; - regulator-initial-mode = ; - }; - - dmic_vdd: - pp1800_alc5682: - pp1800_l2c: - pp1800_vreg_alc5682: - vreg_l2c: ldo2 { - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <1980000>; - regulator-initial-mode = ; - }; - - pp3300_sar: - pp3300_sensor: - vreg_l3c: ldo3 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3540000>; - regulator-initial-mode = ; - }; - - ppvar_uim1: - vddpx_5: - vreg_l4c: ldo4 { - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <3300000>; - regulator-initial-mode = ; - }; - - pp2950_l5c: - uim_vcc: - vddpx_6: - vreg_l5c: ldo5 { - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <3300000>; - regulator-initial-mode = ; - }; - - ppvar_l6c: - vddpx_2: - vreg_l6c: ldo6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - regulator-initial-mode = ; - }; - - vreg_l7c: ldo7 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3544000>; - regulator-initial-mode = ; - }; - - pp1800_prox: - pp1800_sar: - vreg_l8c: ldo8 { - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <2000000>; - regulator-initial-mode = ; - }; - - pp2950_l9c: - vreg_l9c: ldo9 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vdd_a_gnss_0p9: - vdd_ufs_core: - vdd_usb_hs0_core: - vdd_vref_0p9: - vdda_csi01_0p9: - vdda_csi23_0p9: - vdda_csi4_0p9: - vdda_dsi0_pll_0p9: - vdda_dsi0_0p9: - vdda_pcie0_core: - vdda_pcie1_core: - vdda_qlink0_0p9: - vdda_qlink1_0p9: - vdda_qlink0_0p9_ck: - vdda_qlink1_0p9_ck: - vdda_qrefs_0p875: - vreg_l10c_0p8: - vreg_l10c: ldo10 { - regulator-min-microvolt = <720000>; - regulator-max-microvolt = <1050000>; - regulator-initial-mode = ; - }; - - pp2800_l11c: - vreg_l11c: ldo11 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3544000>; - regulator-initial-mode = ; - }; - - pp1800_l12c: - vreg_l12c: ldo12 { - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <2000000>; - regulator-initial-mode = ; - }; - - pp3300_l13c: - vreg_l13c: ldo13 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3544000>; - regulator-initial-mode = ; - }; - - vreg_bob: bob { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3960000>; - regulator-initial-mode = ; - }; - }; -}; - -ap_tp_i2c: &i2c1 { - status = "okay"; - clock-frequency = <400000>; - - trackpad: trackpad@15 { - compatible = "elan,ekth3000"; - reg = <0x15>; - pinctrl-names = "default"; - pinctrl-0 = <&tp_int_odl>; - - interrupt-parent = <&tlmm>; - interrupts = <102 IRQ_TYPE_EDGE_FALLING>; - - vcc-supply = <&pp3300_z1>; - - wakeup-source; - }; -}; - -ap_h1_i2c: &i2c12 { - status = "okay"; - clock-frequency = <400000>; - - tpm@50 { - compatible = "google,cr50"; - reg = <0x50>; - - pinctrl-names = "default"; - pinctrl-0 = <&h1_ap_int_odl>; - - interrupt-parent = <&tlmm>; - interrupts = <54 IRQ_TYPE_EDGE_RISING>; - }; -}; - -ap_ts_pen: &i2c13 { - status = "okay"; - clock-frequency = <400000>; - - ap_ts: touchscreen@10 { - compatible = "hid-over-i2c"; - reg = <0x10>; - pinctrl-names = "default"; - pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; - - interrupt-parent = <&tlmm>; - interrupts = <81 IRQ_TYPE_LEVEL_LOW>; - - post-power-on-delay-ms = <20>; - hid-descr-addr = <0x0001>; - - vdd-supply = <&pp3300_ts>; - }; -}; - -&pm7325_gpios { - status = "disabled"; /* No GPIOs are connected */ -}; - -&pmk8350_gpios { - status = "disabled"; /* No GPIOs are connected */ -}; - -&pmk8350_pon { - status = "disabled"; -}; - -&pmk8350_rtc { - status = "disabled"; -}; - -&pmk8350_vadc { - pmk8350_die_temp { - reg = ; - label = "pmk8350_die_temp"; - qcom,pre-scaling = <1 1>; - }; - - pmr735a_die_temp { - reg = ; - label = "pmr735a_die_temp"; - qcom,pre-scaling = <1 1>; - }; -}; - -&qfprom { - vcc-supply = <&vdd_qfprom>; -}; - -&qspi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - - spi-max-frequency = <37500000>; - spi-tx-bus-width = <2>; - spi-rx-bus-width = <2>; - }; -}; - -&qupv3_id_0 { - status = "okay"; -}; - -&qupv3_id_1 { - status = "okay"; -}; - -&sdhc_1 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_on>; - pinctrl-1 = <&sdc1_off>; - vmmc-supply = <&pp2950_l7b>; - vqmmc-supply = <&pp1800_l19b>; -}; - -&sdhc_2 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_on>; - pinctrl-1 = <&sdc2_off>; - vmmc-supply = <&pp2950_l9c>; - vqmmc-supply = <&ppvar_l6c>; - - cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; -}; - -ap_ec_spi: &spi8 { - status = "okay"; - - pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs_gpio_init_high>, <&qup_spi8_cs_gpio>; - cs-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; - - cros_ec: ec@0 { - compatible = "google,cros-ec-spi"; - reg = <0>; - interrupt-parent = <&tlmm>; - interrupts = <142 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ap_ec_int_l>; - spi-max-frequency = <3000000>; - - cros_ec_pwm: ec-pwm { - compatible = "google,cros-ec-pwm"; - #pwm-cells = <1>; - }; - - i2c_tunnel: i2c-tunnel { - compatible = "google,cros-ec-i2c-tunnel"; - google,remote-bus = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - typec { - compatible = "google,cros-ec-typec"; - #address-cells = <1>; - #size-cells = <0>; - - usb_c0: connector@0 { - compatible = "usb-c-connector"; - reg = <0>; - label = "left"; - power-role = "dual"; - data-role = "host"; - try-power-role = "source"; - }; - - usb_c1: connector@1 { - compatible = "usb-c-connector"; - reg = <1>; - label = "right"; - power-role = "dual"; - data-role = "host"; - try-power-role = "source"; - }; - }; - }; -}; - -#include -#include - -&keyboard_controller { - function-row-physmap = < - MATRIX_KEY(0x00, 0x02, 0) /* T1 */ - MATRIX_KEY(0x03, 0x02, 0) /* T2 */ - MATRIX_KEY(0x02, 0x02, 0) /* T3 */ - MATRIX_KEY(0x01, 0x02, 0) /* T4 */ - MATRIX_KEY(0x03, 0x04, 0) /* T5 */ - MATRIX_KEY(0x02, 0x04, 0) /* T6 */ - MATRIX_KEY(0x01, 0x04, 0) /* T7 */ - MATRIX_KEY(0x02, 0x09, 0) /* T8 */ - MATRIX_KEY(0x01, 0x09, 0) /* T9 */ - MATRIX_KEY(0x00, 0x04, 0) /* T10 */ - >; - linux,keymap = < - MATRIX_KEY(0x00, 0x02, KEY_BACK) - MATRIX_KEY(0x03, 0x02, KEY_REFRESH) - MATRIX_KEY(0x02, 0x02, KEY_ZOOM) - MATRIX_KEY(0x01, 0x02, KEY_SCALE) - MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) - MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) - MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) - MATRIX_KEY(0x02, 0x09, KEY_MUTE) - MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) - MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) - - CROS_STD_MAIN_KEYMAP - >; -}; - -&uart5 { - compatible = "qcom,geni-debug-uart"; - status = "okay"; -}; - -&uart7 { - status = "okay"; -}; - -&usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { - dr_mode = "host"; -}; - -&usb_1_hsphy { - status = "okay"; - - vdda-pll-supply = <&vdd_usb_hs0_core>; - vdda33-supply = <&vdda_usb_hs0_3p1>; - vdda18-supply = <&vdda_usb_hs0_1p8>; -}; - -&usb_1_qmpphy { - status = "okay"; - - vdda-phy-supply = <&vdda_usb_ss_dp_1p2>; - vdda-pll-supply = <&vdda_usb_ss_dp_core>; -}; - -&usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { - dr_mode = "host"; -}; - -&usb_2_hsphy { - status = "okay"; - - vdda-pll-supply = <&vdd_usb_hs0_core>; - vdda33-supply = <&vdda_usb_hs0_3p1>; - vdda18-supply = <&vdda_usb_hs0_1p8>; -}; - -/* PINCTRL - additions to nodes defined in sc7280.dtsi */ - -&qspi_cs0 { - bias-disable; -}; - -&qspi_clk { - bias-disable; -}; - -&qspi_data01 { - /* High-Z when no transfers; nice to park the lines */ - bias-pull-up; -}; - -&qup_uart5_rx { - drive-strength = <2>; - bias-pull-up; -}; - -&qup_uart5_tx { - drive-strength = <2>; - bias-disable; -}; - -&qup_uart7_cts { - /* - * Configure a pull-down on CTS to match the pull of - * the Bluetooth module. - */ - bias-pull-down; -}; - -&qup_uart7_rts { - /* We'll drive RTS, so no pull */ - drive-strength = <2>; - bias-disable; -}; - -&qup_uart7_tx { - /* We'll drive TX, so no pull */ - drive-strength = <2>; - bias-disable; -}; - -&qup_uart7_rx { - /* - * Configure a pull-up on RX. This is needed to avoid - * garbage data when the TX pin of the Bluetooth module is - * in tri-state (module powered off or not driving the - * signal yet). - */ - bias-pull-up; -}; - -&sdc1_on { - clk { - bias-disable; - drive-strength = <16>; - }; - - cmd { - bias-pull-up; - drive-strength = <10>; - }; - - data { - bias-pull-up; - drive-strength = <10>; - }; - - rclk { - bias-pull-down; - }; -}; - -&sdc2_on { - clk { - bias-disable; - drive-strength = <16>; - }; - - cmd { - bias-pull-up; - drive-strength = <10>; - }; - - data { - bias-pull-up; - drive-strength = <10>; - }; - - sd-cd { - pins = "gpio91"; - bias-pull-up; - }; -}; - -/* PINCTRL - board-specific pinctrl */ - -&pm8350c_gpios { - gpio-line-names = "AP_SUSPEND", - "", - "", - "AP_BL_EN", - "", - "SD_CD_ODL", - "", - "", - "AP_BL_PWM"; - - ap_bl_en: ap-bl-en { - pins = "gpio4"; - function = "normal"; - qcom,drive-strength = ; - bias-disable; - - /* Force backlight to be disabled to match state at boot. */ - output-low; - }; -}; - -&tlmm { - gpio-line-names = "HP_I2C_SDA", /* 0 */ - "HP_I2C_SCL", - "SSD_RST_L", - "PE_WAKE_ODL", - "AP_TP_I2C_SDA", - "AP_TP_I2C_SCL", - "UF_CAM_EN", - "WF_CAM_EN", - "AP_SAR_SENSOR_SDA", - "AP_SAR_SENSOR_SCL", - - "", /* 10 */ - "", - "AP_SPI_MOSI", - "AP_SPI_MISO", - "AP_SPI_CLK", - "AP_SPI_CS0_L", - "", - "", - "EDP_HPD", - "", - - "UF_CAM_RST_L", /* 20 */ - "WF_CAM_RST_L", - "UART_AP_TX_DBG_RX", - "UART_DBG_TX_AP_RX", - "EN_PP3300_HUB", - "", - "HOST2WLAN_SOL", - "WLAN2HOST_SOL", - "BT_UART_CTS", - "BT_UART_RTS", - - "BT_UART_TXD", /* 30 */ - "BT_UART_RXD", - "AP_EC_SPI_MISO", - "AP_EC_SPI_MOSI", - "AP_EC_SPI_CLK", - "AP_EC_SPI_CS_L", - "", - "", - "", - "PEN_PDCT_L", - - "IO_BRD_ID0", /* 40 */ - "IO_BRD_ID1", - "EN_FP_RAILS", - "PEN_IRQ_L", - "AP_SPI_FP_MISO", - "AP_SPI_FP_MOSI", - "AP_SPI_FP_CLK", - "AP_SPI_FP_CS_L", - "AP_H1_SPI_MISO", - "AP_H1_SPI_MOSI", - - "AP_H1_SPI_CLK", /* 50 */ - "AP_H1_SPI_CS_L", - "AP_TS_PEN_I2C_SDA", - "AP_TS_PEN_I2C_SCL", - "H1_AP_INT_ODL", - "", - "LCM_RST_1V8_L", - "AMP_EN", - "", - "DP_HOT_PLUG_DET", - - "HUB_RST_L", /* 60 */ - "FP_TO_AP_IRQ_L", - "", - "", - "UF_CAM_MCLK", - "WF_CAM_MCLK", - "IO_BRD_ID2", - "EN_PP3300_CODEC", - "EC_IN_RW_ODL", - "UF_CAM_SDA", - - "UF_CAM_SCL", /* 70 */ - "WF_CAM_SDA", - "WF_CAM_SCL", - "AP_BRD_ID0", - "AP_BRD_ID1", - "AP_BRD_ID2", - "", - "FPMCU_BOOT0", - "FP_RST_L", - "PE_CLKREQ_ODL", - - "EN_EDP_PP3300", /* 80 */ - "TS_INT_L", - "FORCE_USB_BOOT", - "WCD_RST_L", - "WLAN_EN", - "BT_EN", - "WLAN_SW_CTRL", - "PCIE0_RESET_L", - "PCIE0_CLK_REQ_L", - "PCIE0_WAKE_L", - - "AS_EN", /* 90 */ - "SD_CD_ODL", - "", - /* - * AP_FLASH_WP_L is crossystem ABI. Schematics - * call it BIOS_FLASH_WP_L. - */ - "AP_FLASH_WP_L", - "BT_WLAN_SB_CLK", - "BT_WLAN_SB_DATA", - "HP_MCLK", - "HP_BCLK", - "HP_DOUT", - "HP_DIN", - - "HP_LRCLK", /* 100 */ - "HP_IRQ", - "TP_INT_ODL", - "", - "IO_SKU_ID2", - "TS_RESET_L", - "AMP_BCLK", - "AMP_DIN", - "AMP_LRCLK", - "UIM2_DATA", - - "UIM2_CLK", /* 110 */ - "UIM2_RST", - "UIM2_PRESENT", - "UIM1_DATA", - "UIM1_CLK", - "UIM1_RST", - "", - "RFFE0_CLK", - "RFFE0_DATA/BOOT_CONFIG_0", - "RFFE1_CLK", - - "RFFE1_DATA/BOOT_CONFIG_1", /* 120 */ - "RFFE2_CLK", - "RFFE2_DATA/BOOT_CONFIG_2", - "RFFE3_CLK", - "RFFE3_DATA/BOOT_CONFIG_3", - "RFFE4_CLK", - "RFFE4_DATA", - "WCI2_LTE_COEX_RXD", - "WCI2_LTE_COEX_TXD", - "IO_SKU_ID0", - - "IO_SKU_ID1", /* 130 */ - "", - "", - "QLINK0_REQ", - "QLINK0_EN", - "QLINK0_WMSS_RESET_L", - "QLINK1_REQ", - "QLINK1_EN", - "QLINK1_WMSS_RESET_L", - "FORCED_USB_BOOT_POL", - - "", /* 140 */ - "P_SENSOR_INT_L", - "AP_EC_INT_L", - "", - "WCD_SWR_TX_CLK", - "WCD_SWR_TX_DATA_0", - "WCD_SWR_TX_DATA_1", - "WCD_SWR_RX_CLK", - "WCD_SWR_RX_DATA_0", - "WCD_SWR_RX_DATA_1", - - "", /* 150 */ - "", - "", - "", - "", - "", - "", - "", - "WCD_SWR_TX_DATA_2", - "", - - "", /* 160 */ - "", - "", - "", - "", - "", - "", - "", - "", - "", - - "", /* 170 */ - "SENS_UART_TXD", - "SENS_UART_RXD", - "", - "", - ""; - - /* - * pinctrl settings for pins that have no real owners. - */ - pinctrl-names = "default"; - pinctrl-0 = <&bios_flash_wp_l>; - - amp_en: amp-en { - pins = "gpio57"; - function = "gpio"; - bias-pull-down; - }; - - ap_ec_int_l: ap-ec-int-l { - pins = "gpio142"; - input-enable; - bias-pull-up; - }; - - bios_flash_wp_l: bios-flash-wp-l { - pins = "gpio93"; - function = "gpio"; - input-enable; - bias-disable; - }; - - bt_en: bt-en { - pins = "gpio85"; - function = "gpio"; - drive-strength = <2>; - output-low; - bias-pull-down; - }; - - en_fp_rails: en-fp-rails { - pins = "gpio42"; - drive-strength = <2>; - output-high; - bias-disable; - }; - - en_pp3300_codec: en-pp3300-codec { - pins = "gpio67"; - drive-strength = <2>; - bias-disable; - }; - - en_pp3300_dx_edp: en-pp3300-dx-edp { - pins = "gpio80"; - function = "gpio"; - drive-strength = <2>; - /* Has external pulldown */ - bias-disable; - }; - - en_pp3300_hub: en-pp3300-hub { - pins = "gpio24"; - function = "gpio"; - drive-strength = <2>; - /* Has external pulldown */ - bias-disable; - }; - - fp_to_ap_irq_l: fp-to-ap-irq-l { - pins = "gpio61"; - function = "gpio"; - input-enable; - /* Has external pullup */ - bias-disable; - }; - - h1_ap_int_odl: h1-ap-int-odl { - pins = "gpio54"; - function = "gpio"; - input-enable; - bias-pull-up; - }; - - hp_irq: hp-irq { - pins = "gpio101"; - function = "gpio"; - bias-pull-up; - }; - - p_sensor_int_l: p-sensor-int-l { - pins = "gpio141"; - function = "gpio"; - input-enable; - bias-pull-up; - }; - - pen_irq_l: pen-irq-l { - pins = "gpio43"; - function = "gpio"; - /* Has external pullup */ - bias-disable; - }; - - pen_pdct_l: pen-pdct-l { - pins = "gpio39"; - function = "gpio"; - /* Has external pullup */ - bias-disable; - }; - - qup_spi8_cs_gpio_init_high: qup-spi8-cs-gpio-init-high { - pins = "gpio35"; - output-high; - }; - - qup_spi11_cs_gpio_init_high: qup-spi11-cs-gpio-init-high { - pins = "gpio47"; - output-high; - }; - - qup_spi12_cs_gpio_init_high: qup-spi12-cs-gpio-init-high { - pins = "gpio51"; - output-high; - }; - - qup_uart7_sleep_cts: qup-uart7-sleep-cts { - pins = "gpio28"; - function = "gpio"; - /* - * Configure a pull-down on CTS to match the pull of - * the Bluetooth module. - */ - bias-pull-down; - }; - - qup_uart7_sleep_rts: qup-uart7-sleep-rts { - pins = "gpio29"; - function = "gpio"; - /* - * Configure pull-down on RTS. As RTS is active low - * signal, pull it low to indicate the BT SoC that it - * can wakeup the system anytime from suspend state by - * pulling RX low (by sending wakeup bytes). - */ - bias-pull-down; - }; - - qup_uart7_sleep_rx: qup-uart7-sleep-rx { - pins = "gpio31"; - function = "gpio"; - /* - * Configure a pull-up on RX. This is needed to avoid - * garbage data when the TX pin of the Bluetooth module - * is floating which may cause spurious wakeups. - */ - bias-pull-up; - }; - - qup_uart7_sleep_tx: qup-uart7-sleep-tx { - pins = "gpio30"; - function = "gpio"; - /* - * Configure pull-up on TX when it isn't actively driven - * to prevent BT SoC from receiving garbage during sleep. - */ - bias-pull-up; - }; - - tp_int_odl: tp-int-odl { - pins = "gpio102"; - function = "gpio"; - /* Has external pullup */ - bias-disable; - }; - - ts_int_l: ts-int-l { - pins = "gpio81"; - function = "gpio"; - /* Has external pullup */ - bias-pull-up; - }; - - ts_reset_l: ts-reset-l { - pins = "gpio105"; - function = "gpio"; - /* Has external pullup */ - bias-disable; - drive-strength = <2>; - }; - - uf_cam_en: uf-cam-en { - pins = "gpio6"; - function = "gpio"; - drive-strength = <2>; - /* Has external pulldown */ - bias-disable; - }; - - wf_cam_en: wf-cam-en { - pins = "gpio7"; - function = "gpio"; - drive-strength = <2>; - /* Has external pulldown */ - bias-disable; - }; -}; -- cgit From 90c856602e0346ce9ff234062e86a198d71fa723 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Tue, 25 Jan 2022 14:44:20 -0800 Subject: arm64: dts: qcom: sc7280: Factor out Chrome common fragment This factors out a device tree fragment from some sc7280 device trees. It represents the device tree bits that should be included for "Chrome" based sc7280 boards. On these boards the bootloader (Coreboot + Depthcharge) configures things slightly different than the bootloader that Qualcomm provides. The modem firmware on these boards also works differently than on other Qulacomm products and thus the reserved memory map needs to be adjusted. NOTES: - This is _not_ quite a no-op change. The "herobrine" and "idp" fragments here were different and it looks like someone simply forgot to update the herobrine version. This updates a few numbers to match IDP. This will also cause the `pmk8350_pon` to be disabled on idp/crd, which I belive is a correct change. - At the moment this assumes LTE skus. Once it's clearer how WiFi SKUs will work (how much of the memory map they can reclaim) we may add an extra fragment that will rejigger one way or the other. Signed-off-by: Douglas Anderson Reviewed-by: Stephen Boyd Reviewed-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220125144316.v2.3.Iac012fa8d727be46448d47027a1813ea716423ce@changeid --- arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi | 97 ++++++++++++++++++++++ .../dts/qcom/sc7280-herobrine-herobrine-r0.dts | 70 +--------------- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 75 +---------------- 3 files changed, 101 insertions(+), 141 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi new file mode 100644 index 000000000000..9f4a9c263c35 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * sc7280 fragment for devices with Chrome bootloader + * + * This file mainly tries to abstract out the memory protections put into + * place by the Chrome bootloader which are different than what's put into + * place by Qualcomm's typical bootloader. It also has a smattering of other + * things that will hold true for any conceivable Chrome design + * + * Copyright 2022 Google LLC. + */ + +/* + * Reserved memory changes + * + * Delete all unused memory nodes and define the peripheral memory regions + * required by the setup for Chrome boards. + */ + +/delete-node/ &hyp_mem; +/delete-node/ &xbl_mem; +/delete-node/ &reserved_xbl_uefi_log; +/delete-node/ &sec_apps_mem; + +/ { + reserved-memory { + adsp_mem: memory@86700000 { + reg = <0x0 0x86700000 0x0 0x2800000>; + no-map; + }; + + camera_mem: memory@8ad00000 { + reg = <0x0 0x8ad00000 0x0 0x500000>; + no-map; + }; + + venus_mem: memory@8b200000 { + reg = <0x0 0x8b200000 0x0 0x500000>; + no-map; + }; + + mpss_mem: memory@8b800000 { + reg = <0x0 0x8b800000 0x0 0xf600000>; + no-map; + }; + + wpss_mem: memory@9ae00000 { + reg = <0x0 0x9ae00000 0x0 0x1900000>; + no-map; + }; + + mba_mem: memory@9c700000 { + reg = <0x0 0x9c700000 0x0 0x200000>; + no-map; + }; + }; +}; + +/* The PMIC PON code isn't compatible w/ how Chrome EC/BIOS handle things. */ +&pmk8350_pon { + status = "disabled"; +}; + +/* + * Chrome designs always boot from SPI flash hooked up to the qspi. + * + * It's expected that all boards will support "dual SPI" at 37.5 MHz. + * If some boards need a different speed or have a package that allows + * Quad SPI together with WP then those boards can easily override. + */ +&qspi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>; + + spi_flash: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + + spi-max-frequency = <37500000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + }; +}; + +/* Modem setup is different on Chrome setups than typical Qualcomm setup */ +&remoteproc_mpss { + status = "okay"; + compatible = "qcom,sc7280-mss-pil"; + iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>; + memory-region = <&mba_mem>, <&mpss_mem>; +}; + +/* Increase the size from 2.5MB to 8MB */ +&rmtfs_mem { + reg = <0x0 0x9c900000 0x0 0x800000>; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts index 8676c93590b5..67680a13c234 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts @@ -22,62 +22,15 @@ #include "pm8350c.dtsi" #include "pmk8350.dtsi" +#include "sc7280-chrome-common.dtsi" + / { model = "Google Herobrine (rev0)"; compatible = "google,herobrine", "qcom,sc7280"; }; -/* - * Reserved memory changes - * - * Delete all unused memory nodes and define the peripheral memory regions - * required by the board dts. - * - */ - -/delete-node/ &hyp_mem; -/delete-node/ &xbl_mem; -/delete-node/ &sec_apps_mem; - -/* Increase the size from 2MB to 8MB */ -&rmtfs_mem { - reg = <0x0 0x83600000 0x0 0x800000>; -}; - / { - reserved-memory { - adsp_mem: memory@86700000 { - reg = <0x0 0x86700000 0x0 0x2800000>; - no-map; - }; - - camera_mem: memory@8ad00000 { - reg = <0x0 0x8ad00000 0x0 0x500000>; - no-map; - }; - - venus_mem: memory@8b200000 { - reg = <0x0 0x8b200000 0x0 0x500000>; - no-map; - }; - - mpss_mem: memory@8b800000 { - reg = <0x0 0x8b800000 0x0 0xf600000>; - no-map; - }; - - wpss_mem: memory@9ae00000 { - reg = <0x0 0x9ae00000 0x0 0x1900000>; - no-map; - }; - - mba_mem: memory@9c700000 { - reg = <0x0 0x9c700000 0x0 0x200000>; - no-map; - }; - }; - aliases { serial0 = &uart5; serial1 = &uart7; @@ -691,10 +644,6 @@ ap_ts_pen: &i2c13 { status = "disabled"; /* No GPIOs are connected */ }; -&pmk8350_pon { - status = "disabled"; -}; - &pmk8350_rtc { status = "disabled"; }; @@ -717,21 +666,6 @@ ap_ts_pen: &i2c13 { vcc-supply = <&vdd_qfprom>; }; -&qspi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - - spi-max-frequency = <37500000>; - spi-tx-bus-width = <2>; - spi-rx-bus-width = <2>; - }; -}; - &qupv3_id_0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index e5cd0129ad10..05bb7d2839a8 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -13,6 +13,8 @@ #include "pm8350c.dtsi" #include "pmk8350.dtsi" +#include "sc7280-chrome-common.dtsi" + / { aliases { bluetooth0 = &bluetooth; @@ -50,58 +52,6 @@ }; }; -/* - * Reserved memory changes - * - * Delete all unused memory nodes and define the peripheral memory regions - * required by the board dts. - * - */ - -/delete-node/ &hyp_mem; -/delete-node/ &xbl_mem; -/delete-node/ &reserved_xbl_uefi_log; -/delete-node/ &sec_apps_mem; - -/* Increase the size from 2.5MB to 8MB */ -&rmtfs_mem { - reg = <0x0 0x9c900000 0x0 0x800000>; -}; - -/ { - reserved-memory { - adsp_mem: memory@86700000 { - reg = <0x0 0x86700000 0x0 0x2800000>; - no-map; - }; - - camera_mem: memory@8ad00000 { - reg = <0x0 0x8ad00000 0x0 0x500000>; - no-map; - }; - - venus_mem: memory@8b200000 { - reg = <0x0 0x8b200000 0x0 0x500000>; - no-map; - }; - - mpss_mem: memory@8b800000 { - reg = <0x0 0x8b800000 0x0 0xf600000>; - no-map; - }; - - wpss_mem: memory@9ae00000 { - reg = <0x0 0x9ae00000 0x0 0x1900000>; - no-map; - }; - - mba_mem: memory@9c700000 { - reg = <0x0 0x9c700000 0x0 0x200000>; - no-map; - }; - }; -}; - &apps_rsc { pm7325-regulators { compatible = "qcom,pm7325-rpmh-regulators"; @@ -318,20 +268,6 @@ vcc-supply = <&vreg_l1c_1p8>; }; -&qspi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <37500000>; - spi-tx-bus-width = <2>; - spi-rx-bus-width = <2>; - }; -}; - &qupv3_id_0 { status = "okay"; }; @@ -340,13 +276,6 @@ status = "okay"; }; -&remoteproc_mpss { - status = "okay"; - compatible = "qcom,sc7280-mss-pil"; - iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>; - memory-region = <&mba_mem &mpss_mem>; -}; - &sdhc_1 { status = "okay"; -- cgit From 58d5ea52bd22da53e2e561ada8b4608b73023f01 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Tue, 25 Jan 2022 14:44:21 -0800 Subject: arm64: dts: qcom: sc7280: Factor gpio.h include to sc7280.dtsi Though sc7280 itself doesn't need any of the defines in gpio.h, it's highly likely that the actual boards will use them. Let's add the include to the sc7280.dtsi file so that boards don't need to do it. Suggested-by: Konrad Dybcio Signed-off-by: Douglas Anderson Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220125144316.v2.4.I3194c8bdb2ad3212665286fa273710a3c4840e94@changeid --- arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts | 1 - arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 1 - arch/arm64/boot/dts/qcom/sc7280.dtsi | 1 + 3 files changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts index 67680a13c234..ad4fe288b53c 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts @@ -7,7 +7,6 @@ /dts-v1/; -#include #include #include #include diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 05bb7d2839a8..78da9ac983db 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -5,7 +5,6 @@ * Copyright (c) 2021, The Linux Foundation. All rights reserved. */ -#include #include #include #include "sc7280.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index a1b0d23a350b..d4009cc0bb78 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include -- cgit From 3f99518c6f6520ad0fd14d862d54ee12f16156b4 Mon Sep 17 00:00:00 2001 From: Jean THOMAS Date: Thu, 2 Dec 2021 00:18:31 +0100 Subject: arm64: dts: qcom: msm8992-lg-bullhead: Place LG Bullhead generic code into a DTSI file This patch puts the generic code common across all hardware revisions into a DTSI file. It also prefixes the DTS filename with the vendor name, to follow the naming convention used by other DTS files. Signed-off-by: Jean THOMAS Reviewed-by: Petr Vorel Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211201231832.188634-1-virgule@jeanthomas.me --- arch/arm64/boot/dts/qcom/Makefile | 2 +- .../boot/dts/qcom/msm8992-bullhead-rev-101.dts | 304 --------------------- .../boot/dts/qcom/msm8992-lg-bullhead-rev-101.dts | 14 + arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi | 302 ++++++++++++++++++++ 4 files changed, 317 insertions(+), 305 deletions(-) delete mode 100644 arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts create mode 100644 arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-101.dts create mode 100644 arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 9db743826391..8c6598fed98a 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -18,7 +18,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a5u-eur.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-j5.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-serranove.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8992-lg-bullhead-rev-101.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-msft-lumia-octagon-talkman.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-xiaomi-libra.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts deleted file mode 100644 index 4da6c44bf532..000000000000 --- a/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts +++ /dev/null @@ -1,304 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2015, LGE Inc. All rights reserved. - * Copyright (c) 2016, The Linux Foundation. All rights reserved. - * Copyright (c) 2021, Petr Vorel - */ - -/dts-v1/; - -#include "msm8992.dtsi" -#include "pm8994.dtsi" -#include "pmi8994.dtsi" - -/* cont_splash_mem has different memory mapping */ -/delete-node/ &cont_splash_mem; - -/ { - model = "LG Nexus 5X"; - compatible = "lg,bullhead", "qcom,msm8992"; - chassis-type = "handset"; - - /* required for bootloader to select correct board */ - qcom,msm-id = <251 0>, <252 0>; - qcom,board-id = <0xb64 0>; - qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>; - - /* Bullhead firmware doesn't support PSCI */ - /delete-node/ psci; - - aliases { - serial0 = &blsp1_uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ramoops@1ff00000 { - compatible = "ramoops"; - reg = <0x0 0x1ff00000 0x0 0x40000>; - console-size = <0x10000>; - record-size = <0x10000>; - ftrace-size = <0x10000>; - pmsg-size = <0x20000>; - }; - - cont_splash_mem: memory@3400000 { - reg = <0 0x03400000 0 0x1200000>; - no-map; - }; - }; -}; - -&blsp1_uart2 { - status = "okay"; -}; - -&rpm_requests { - pm8994_regulators: pm8994-regulators { - compatible = "qcom,rpm-pm8994-regulators"; - - vdd_l1-supply = <&pm8994_s1>; - vdd_l2_26_28-supply = <&pm8994_s3>; - vdd_l3_11-supply = <&pm8994_s3>; - vdd_l4_27_31-supply = <&pm8994_s3>; - vdd_l5_7-supply = <&pm8994_s3>; - vdd_l6_12_32-supply = <&pm8994_s5>; - vdd_l8_16_30-supply = <&vph_pwr>; - vdd_l9_10_18_22-supply = <&vph_pwr>; - vdd_l13_19_23_24-supply = <&vph_pwr>; - vdd_l14_15-supply = <&pm8994_s5>; - vdd_l17_29-supply = <&vph_pwr>; - vdd_l20_21-supply = <&vph_pwr>; - vdd_l25-supply = <&pm8994_s5>; - vdd_lvs1_2 = <&pm8994_s4>; - - /* S1, S2, S6 and S12 are managed by RPMPD */ - - pm8994_s1: s1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - }; - - pm8994_s2: s2 { - /* TODO */ - }; - - pm8994_s3: s3 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - }; - - pm8994_s4: s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-allow-set-load; - regulator-system-load = <325000>; - }; - - pm8994_s5: s5 { - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - }; - - pm8994_s7: s7 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - /* S8, S9, S10 and S11 - SPMI-managed VDD_APC */ - - pm8994_l1: l1 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - pm8994_l2: l2 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - }; - - pm8994_l3: l3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - pm8994_l4: l4 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - /* L5 is inaccessible from RPM */ - - pm8994_l6: l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - /* L7 is inaccessible from RPM */ - - pm8994_l8: l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8994_l9: l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8994_l10: l10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8994_l11: l11 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - pm8994_l12: l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8994_l13: l13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pm8994_l14: l14 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - pm8994_l15: l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8994_l16: l16 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - pm8994_l17: l17 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - pm8994_l18: l18 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - pm8994_l19: l19 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8994_l20: l20 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-always-on; - regulator-boot-on; - regulator-allow-set-load; - regulator-system-load = <570000>; - }; - - pm8994_l21: l21 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - pm8994_l22: l22 { - regulator-min-microvolt = <3100000>; - regulator-max-microvolt = <3100000>; - }; - - pm8994_l23: l23 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - pm8994_l24: l24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3150000>; - }; - - pm8994_l25: l25 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8994_l26: l26 { - /* TODO: value from downstream - regulator-min-microvolt = <987500>; - fails to apply */ - }; - - pm8994_l27: l27 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - pm8994_l28: l28 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - pm8994_l29: l29 { - /* TODO: Unsupported voltage range. - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - qcom,init-voltage = <2800000>; - */ - }; - - pm8994_l30: l30 { - /* TODO: get this verified - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,init-voltage = <1800000>; - */ - }; - - pm8994_l31: l31 { - regulator-min-microvolt = <1262500>; - regulator-max-microvolt = <1262500>; - }; - - pm8994_l32: l32 { - /* TODO: get this verified - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,init-voltage = <1800000>; - */ - }; - }; - - pmi8994_regulators: pmi8994-regulators { - compatible = "qcom,rpm-pmi8994-regulators"; - - vdd_s1-supply = <&vph_pwr>; - vdd_bst_byp-supply = <&vph_pwr>; - - pmi8994_s1: s1 {}; - - /* S2 & S3 - VDD_GFX */ - - pmi8994_bby: boost-bypass {}; - }; -}; - -&sdhc1 { - status = "okay"; - - mmc-hs400-1_8v; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-101.dts new file mode 100644 index 000000000000..e6a5ebd30e2f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-101.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) Jean Thomas + */ + +/dts-v1/; + +#include "msm8992-lg-bullhead.dtsi" + +/ { + model = "LG Nexus 5X rev 1.01"; + + /* required for bootloader to select correct board */ + qcom,board-id = <0xb64 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi new file mode 100644 index 000000000000..3b0cc85d6674 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi @@ -0,0 +1,302 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2015, LGE Inc. All rights reserved. + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * Copyright (c) 2021, Petr Vorel + */ + +/dts-v1/; + +#include "msm8992.dtsi" +#include "pm8994.dtsi" +#include "pmi8994.dtsi" + +/* cont_splash_mem has different memory mapping */ +/delete-node/ &cont_splash_mem; + +/ { + model = "LG Nexus 5X"; + compatible = "lg,bullhead", "qcom,msm8992"; + chassis-type = "handset"; + + qcom,msm-id = <251 0>, <252 0>; + qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>; + + /* Bullhead firmware doesn't support PSCI */ + /delete-node/ psci; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ramoops@1ff00000 { + compatible = "ramoops"; + reg = <0x0 0x1ff00000 0x0 0x40000>; + console-size = <0x10000>; + record-size = <0x10000>; + ftrace-size = <0x10000>; + pmsg-size = <0x20000>; + }; + + cont_splash_mem: memory@3400000 { + reg = <0 0x03400000 0 0x1200000>; + no-map; + }; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&rpm_requests { + pm8994_regulators: pm8994-regulators { + compatible = "qcom,rpm-pm8994-regulators"; + + vdd_l1-supply = <&pm8994_s1>; + vdd_l2_26_28-supply = <&pm8994_s3>; + vdd_l3_11-supply = <&pm8994_s3>; + vdd_l4_27_31-supply = <&pm8994_s3>; + vdd_l5_7-supply = <&pm8994_s3>; + vdd_l6_12_32-supply = <&pm8994_s5>; + vdd_l8_16_30-supply = <&vph_pwr>; + vdd_l9_10_18_22-supply = <&vph_pwr>; + vdd_l13_19_23_24-supply = <&vph_pwr>; + vdd_l14_15-supply = <&pm8994_s5>; + vdd_l17_29-supply = <&vph_pwr>; + vdd_l20_21-supply = <&vph_pwr>; + vdd_l25-supply = <&pm8994_s5>; + vdd_lvs1_2 = <&pm8994_s4>; + + /* S1, S2, S6 and S12 are managed by RPMPD */ + + pm8994_s1: s1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + }; + + pm8994_s2: s2 { + /* TODO */ + }; + + pm8994_s3: s3 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + pm8994_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allow-set-load; + regulator-system-load = <325000>; + }; + + pm8994_s5: s5 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + }; + + pm8994_s7: s7 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + /* S8, S9, S10 and S11 - SPMI-managed VDD_APC */ + + pm8994_l1: l1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + pm8994_l2: l2 { + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + }; + + pm8994_l3: l3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8994_l4: l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + /* L5 is inaccessible from RPM */ + + pm8994_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + /* L7 is inaccessible from RPM */ + + pm8994_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8994_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8994_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8994_l11: l11 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8994_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8994_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8994_l14: l14 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8994_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8994_l16: l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8994_l17: l17 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8994_l18: l18 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + pm8994_l19: l19 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8994_l20: l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-always-on; + regulator-boot-on; + regulator-allow-set-load; + regulator-system-load = <570000>; + }; + + pm8994_l21: l21 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + pm8994_l22: l22 { + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + }; + + pm8994_l23: l23 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + pm8994_l24: l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3150000>; + }; + + pm8994_l25: l25 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8994_l26: l26 { + /* TODO: value from downstream + regulator-min-microvolt = <987500>; + fails to apply */ + }; + + pm8994_l27: l27 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + pm8994_l28: l28 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + pm8994_l29: l29 { + /* TODO: Unsupported voltage range. + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + qcom,init-voltage = <2800000>; + */ + }; + + pm8994_l30: l30 { + /* TODO: get this verified + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + */ + }; + + pm8994_l31: l31 { + regulator-min-microvolt = <1262500>; + regulator-max-microvolt = <1262500>; + }; + + pm8994_l32: l32 { + /* TODO: get this verified + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + */ + }; + }; + + pmi8994_regulators: pmi8994-regulators { + compatible = "qcom,rpm-pmi8994-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_bst_byp-supply = <&vph_pwr>; + + pmi8994_s1: s1 {}; + + /* S2 & S3 - VDD_GFX */ + + pmi8994_bby: boost-bypass {}; + }; +}; + +&sdhc1 { + status = "okay"; + + mmc-hs400-1_8v; +}; -- cgit From cd4bd4704ec8cff3d045493e2130c7095bbabf78 Mon Sep 17 00:00:00 2001 From: Jean THOMAS Date: Thu, 2 Dec 2021 00:18:32 +0100 Subject: arm64: dts: qcom: msm8992-lg-bullhead: Add support for LG Bullhead rev 1.0 This commit implements a DTS file for LG Bullhead (Nexus 5X) rev 1.0 with its matching "qcom,board-id" property. Signed-off-by: Jean THOMAS Reviewed-by: Petr Vorel Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211201231832.188634-2-virgule@jeanthomas.me --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-10.dts | 14 ++++++++++++++ 2 files changed, 15 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-10.dts (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 8c6598fed98a..596e5df1c92b 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -18,6 +18,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a5u-eur.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-j5.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-serranove.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8992-lg-bullhead-rev-10.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-lg-bullhead-rev-101.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-msft-lumia-octagon-talkman.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-xiaomi-libra.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-10.dts b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-10.dts new file mode 100644 index 000000000000..7e6bce4af441 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-10.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) Jean Thomas + */ + +/dts-v1/; + +#include "msm8992-lg-bullhead.dtsi" + +/ { + model = "LG Nexus 5X rev 1.0"; + + /* required for bootloader to select correct board */ + qcom,board-id = <0xa64 0>; +}; -- cgit From 015bbdd314110ad20d440bec4d8483f73f4a8b58 Mon Sep 17 00:00:00 2001 From: Robert Foss Date: Mon, 6 Dec 2021 16:40:02 +0100 Subject: arm64: dts: qcom: apq8016-sbc: Remove clock-lanes property from &camss node The clock-lanes property is no longer used as it is not programmable by the CSIPHY hardware block of Qcom ISPs and should be removed. Signed-off-by: Robert Foss Reviewed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211206154003.39892-2-robert.foss@linaro.org --- arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index a5320d6d30e7..b7a578aafcbb 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -253,7 +253,6 @@ port@0 { reg = <0>; csiphy0_ep: endpoint { - clock-lanes = <1>; data-lanes = <0 2>; remote-endpoint = <&ov5640_ep>; status = "okay"; @@ -289,7 +288,6 @@ port { ov5640_ep: endpoint { - clock-lanes = <1>; data-lanes = <0 2>; remote-endpoint = <&csiphy0_ep>; }; -- cgit From 6bf3c1895f5848977ab3912eb76fd996bc4d2768 Mon Sep 17 00:00:00 2001 From: Robert Foss Date: Mon, 6 Dec 2021 16:40:03 +0100 Subject: arm64: dts: qcom: sdm845-db845c: Remove clock-lanes property from &camss node The clock-lanes property is no longer used as it is not programmable by the CSIPHY hardware block of Qcom ISPs and should be removed. Signed-off-by: Robert Foss Reviewed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211206154003.39892-3-robert.foss@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 13f80a0b6faa..2cf4b932aee2 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -1125,7 +1125,6 @@ port@0 { reg = <0>; csiphy0_ep: endpoint { - clock-lanes = <7>; data-lanes = <0 1 2 3>; remote-endpoint = <&ov8856_ep>; }; @@ -1166,7 +1165,6 @@ port { ov8856_ep: endpoint { - clock-lanes = <1>; link-frequencies = /bits/ 64 <360000000 180000000>; data-lanes = <1 2 3 4>; @@ -1211,7 +1209,6 @@ port { ov7251_ep: endpoint { - clock-lanes = <1>; data-lanes = <0 1>; // remote-endpoint = <&csiphy3_ep>; }; -- cgit From 625c24460dbbc3b6c9a148c0a30f0830893fc909 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Mon, 13 Dec 2021 20:51:04 +0100 Subject: arm64: dts: qcom: sdm845: fix microphone bias properties and values replace millivolt with correct microvolt and adjust value to the minimal value allowed by documentation. Found with `make qcom/sdm845-oneplus-fajita.dtb`. Fixes: arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dt.yaml: codec@1: 'qcom,micbias1-microvolt' is a required property From schema: Documentation/devicetree/bindings/sound/qcom,wcd934x.yaml arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dt.yaml: codec@1: 'qcom,micbias2-microvolt' is a required property From schema: Documentation/devicetree/bindings/sound/qcom,wcd934x.yaml arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dt.yaml: codec@1: 'qcom,micbias3-microvolt' is a required property From schema: Documentation/devicetree/bindings/sound/qcom,wcd934x.yaml arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dt.yaml: codec@1: 'qcom,micbias4-microvolt' is a required property From schema: Documentation/devicetree/bindings/sound/qcom,wcd934x.yaml arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dt.yaml: codec@1: 'qcom,micbias1-millivolt', 'qcom,micbias2-millivolt', 'qcom,micbias3-millivolt', 'qcom,micbias4-millivolt' do not match any of the regexes: '^.*@[0-9a-f]+$', 'pinctrl-[0-9]+' Fixes: 27ca1de07dc3 ("arm64: dts: qcom: sdm845: add slimbus nodes") Signed-off-by: David Heidelberg Tested-by: Steev Klimaszewski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211213195105.114596-1-david@ixit.cz --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index cfdeaa81f1bb..1bb4d98db96f 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -3613,10 +3613,10 @@ #clock-cells = <0>; clock-frequency = <9600000>; clock-output-names = "mclk"; - qcom,micbias1-millivolt = <1800>; - qcom,micbias2-millivolt = <1800>; - qcom,micbias3-millivolt = <1800>; - qcom,micbias4-millivolt = <1800>; + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; #address-cells = <1>; #size-cells = <1>; -- cgit From 2f1145117946756da4cafe3821d8f0a5d441f5e3 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Tue, 14 Dec 2021 11:24:50 +0100 Subject: arm64: dts: qcom: update qcom,domain property Since 'qcom,apr-domain' is deprecated in favor of 'qcom,domain', update accordingly. Signed-off-by: David Heidelberg Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211214102451.29084-1-david@ixit.cz --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 2c9c21287beb..ea65f2ad4a10 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -3054,7 +3054,7 @@ power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>; compatible = "qcom,apr-v2"; qcom,smd-channels = "apr_audio_svc"; - qcom,apr-domain = ; + qcom,domain = ; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 9217c3a51f79..240293592ef9 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -2160,7 +2160,7 @@ apr { compatible = "qcom,apr-v2"; qcom,glink-channels = "apr_audio_svc"; - qcom,apr-domain = ; + qcom,domain = ; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 1bb4d98db96f..5d1d38eb1dfb 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -787,7 +787,7 @@ apr { compatible = "qcom,apr-v2"; qcom,glink-channels = "apr_audio_svc"; - qcom,apr-domain = ; + qcom,domain = ; #address-cells = <1>; #size-cells = <0>; qcom,intents = <512 20>; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 5617a46e5ccd..2272efd1506b 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -4320,7 +4320,7 @@ apr { compatible = "qcom,apr-v2"; qcom,glink-channels = "apr_audio_svc"; - qcom,apr-domain = ; + qcom,domain = ; #address-cells = <1>; #size-cells = <0>; -- cgit From 7be1c395ee40e35493eb4b2ef2d643de1c626a98 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Tue, 14 Dec 2021 14:27:49 +0100 Subject: arm64: dts: qcom: fix thermal zones naming Rename thermal zones according to dt-schema. Fixes multiple `make dtbs_check` warnings about name convetion. Signed-off-by: David Heidelberg Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211214132750.69782-1-david@ixit.cz --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/msm8998.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sm8150.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sm8250.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sm8350.dtsi | 16 ++++++++-------- 6 files changed, 18 insertions(+), 18 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index ea65f2ad4a10..fd58d7b00243 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -3273,7 +3273,7 @@ }; }; - gpu-thermal-top { + gpu-top-thermal { polling-delay-passive = <250>; polling-delay = <1000>; @@ -3295,7 +3295,7 @@ }; }; - gpu-thermal-bottom { + gpu-bottom-thermal { polling-delay-passive = <250>; polling-delay = <1000>; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index f273bc1ff629..453a049f693d 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -674,7 +674,7 @@ }; }; - gpu-thermal-bottom { + gpu-bottom-thermal { polling-delay-passive = <250>; polling-delay = <1000>; @@ -689,7 +689,7 @@ }; }; - gpu-thermal-top { + gpu-top-thermal { polling-delay-passive = <250>; polling-delay = <1000>; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 5d1d38eb1dfb..5fac82f026fd 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -5258,7 +5258,7 @@ }; }; - gpu-thermal-top { + gpu-top-thermal { polling-delay-passive = <250>; polling-delay = <1000>; @@ -5273,7 +5273,7 @@ }; }; - gpu-thermal-bottom { + gpu-bottom-thermal { polling-delay-passive = <250>; polling-delay = <1000>; diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 6012322a5984..c1067b31b299 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -4265,7 +4265,7 @@ }; }; - gpu-thermal-top { + gpu-top-thermal { polling-delay-passive = <250>; polling-delay = <1000>; @@ -4445,7 +4445,7 @@ }; }; - gpu-thermal-bottom { + gpu-bottom-thermal { polling-delay-passive = <250>; polling-delay = <1000>; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 2272efd1506b..93570a61c2af 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -5172,7 +5172,7 @@ }; }; - gpu-thermal-top { + gpu-top-thermal { polling-delay-passive = <250>; polling-delay = <1000>; @@ -5307,7 +5307,7 @@ }; }; - gpu-thermal-bottom { + gpu-bottom-thermal { polling-delay-passive = <250>; polling-delay = <1000>; diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 53b39e718fb6..abd15999773c 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2991,7 +2991,7 @@ }; }; - gpu-thermal-top { + gpu-top-thermal { polling-delay-passive = <250>; polling-delay = <1000>; @@ -3006,7 +3006,7 @@ }; }; - gpu-thermal-bottom { + gpu-bottom-thermal { polling-delay-passive = <250>; polling-delay = <1000>; @@ -3096,7 +3096,7 @@ }; }; - modem1-thermal-top { + modem1-top-thermal { polling-delay-passive = <250>; polling-delay = <1000>; @@ -3111,7 +3111,7 @@ }; }; - modem2-thermal-top { + modem2-top-thermal { polling-delay-passive = <250>; polling-delay = <1000>; @@ -3126,7 +3126,7 @@ }; }; - modem3-thermal-top { + modem3-top-thermal { polling-delay-passive = <250>; polling-delay = <1000>; @@ -3141,7 +3141,7 @@ }; }; - modem4-thermal-top { + modem4-top-thermal { polling-delay-passive = <250>; polling-delay = <1000>; @@ -3156,7 +3156,7 @@ }; }; - camera-thermal-top { + camera-top-thermal { polling-delay-passive = <250>; polling-delay = <1000>; @@ -3171,7 +3171,7 @@ }; }; - cam-thermal-bottom { + cam-bottom-thermal { polling-delay-passive = <250>; polling-delay = <1000>; -- cgit From ff15ae73eeee62d8eb7554ecc21f2908f32f33a9 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 14 Dec 2021 14:51:24 +0100 Subject: arm64: dts: qcom: apq8016-sbc: Fix dtbs_check warnings for &sound qcom,apq8016-sbc-sndcard is now covered by the qcom,sm8250.yaml schema which has slightly different recommendations for the naming of properties and nodes. The old naming is still functional but deprecated. Update the &sound node in apq8016-sbc to fix the following dtbs_check warnings: apq8016-sbc.dt.yaml: sound@7702000: 'model' is a required property From schema: sound/qcom,sm8250.yaml apq8016-sbc.dt.yaml: sound@7702000: 'external-dai-link@0', ... do not match any of the regexes: '.*-dai-link$', ... From schema: sound/qcom,sm8250.yaml Cc: Srinivas Kandagatla Signed-off-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211214135124.2380-1-stephan@gerhold.net --- arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index b7a578aafcbb..7c1eab605c15 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -349,12 +349,12 @@ pinctrl-0 = <&cdc_pdm_lines_act &ext_sec_tlmm_lines_act &ext_mclk_tlmm_lines_act>; pinctrl-1 = <&cdc_pdm_lines_sus &ext_sec_tlmm_lines_sus &ext_mclk_tlmm_lines_sus>; pinctrl-names = "default", "sleep"; - qcom,model = "DB410c"; - qcom,audio-routing = + model = "DB410c"; + audio-routing = "AMIC2", "MIC BIAS Internal2", "AMIC3", "MIC BIAS External1"; - external-dai-link@0 { + quaternary-dai-link { link-name = "ADV7533"; cpu { sound-dai = <&lpass MI2S_QUATERNARY>; @@ -364,7 +364,7 @@ }; }; - internal-codec-playback-dai-link@0 { + primary-dai-link { link-name = "WCD"; cpu { sound-dai = <&lpass MI2S_PRIMARY>; @@ -374,7 +374,7 @@ }; }; - internal-codec-capture-dai-link@0 { + tertiary-dai-link { link-name = "WCD-Capture"; cpu { sound-dai = <&lpass MI2S_TERTIARY>; -- cgit From d60507200485bc778bf6a5556271d784ab09d913 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 15 Dec 2021 02:14:48 +0300 Subject: arm64: dts: qcom: sm8250: fix PCIe bindings to follow schema Replace (unused) enable-gpio binding with schema-defined wake-gpios. The GPIO line is still unused, but at least we'd follow the defined schema. While we are at it, change perst-gpio property to follow the preferred naming schema (perst-gpios). Fixes: 13e948a36db7 ("arm64: dts: qcom: sm8250: Commonize PCIe pins") Cc: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211214231448.2044987-1-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 93570a61c2af..db57c115d262 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1740,8 +1740,8 @@ phys = <&pcie0_lane>; phy-names = "pciephy"; - perst-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>; - enable-gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; @@ -1844,8 +1844,8 @@ phys = <&pcie1_lane>; phy-names = "pciephy"; - perst-gpio = <&tlmm 82 GPIO_ACTIVE_LOW>; - enable-gpio = <&tlmm 84 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; @@ -1950,8 +1950,8 @@ phys = <&pcie2_lane>; phy-names = "pciephy"; - perst-gpio = <&tlmm 85 GPIO_ACTIVE_LOW>; - enable-gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pcie2_default_state>; -- cgit From 63a4021fef47d6075c23c35795591cb849aa3df2 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Wed, 15 Dec 2021 00:46:47 +0100 Subject: arm64: dts: qcom: sdm845: rename memory@ nodes to more descriptive names Pure effort to avoid `make dtbs_check` warnings about memory@ nodes, which should have property device_type set to memory. Fixes warnings as: arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dt.yaml: memory@f5b00000: 'device_type' is a required property From schema: dtschema/schemas/memory.yaml Signed-off-by: David Heidelberg Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211214234648.23369-1-david@ixit.cz --- .../arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 8 ++--- arch/arm64/boot/dts/qcom/sdm845.dtsi | 38 +++++++++++----------- 2 files changed, 23 insertions(+), 23 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 7f42e5315ecb..511ca72f465e 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -54,7 +54,7 @@ * it is otherwise possible for an allocation adjacent to the * rmtfs_mem region to trigger an XPU violation, causing a crash. */ - rmtfs_lower_guard: memory@f5b00000 { + rmtfs_lower_guard: rmtfs-lower-guard@f5b00000 { no-map; reg = <0 0xf5b00000 0 0x1000>; }; @@ -63,7 +63,7 @@ * but given the same address every time. Hard code it as this address is * where the modem firmware expects it to be. */ - rmtfs_mem: memory@f5b01000 { + rmtfs_mem: rmtfs-mem@f5b01000 { compatible = "qcom,rmtfs-mem"; reg = <0 0xf5b01000 0 0x200000>; no-map; @@ -71,7 +71,7 @@ qcom,client-id = <1>; qcom,vmid = <15>; }; - rmtfs_upper_guard: memory@f5d01000 { + rmtfs_upper_guard: rmtfs-upper-guard@f5d01000 { no-map; reg = <0 0xf5d01000 0 0x1000>; }; @@ -80,7 +80,7 @@ * It seems like reserving the old rmtfs_mem region is also needed to prevent * random crashes which are most likely modem related, more testing needed. */ - removed_region: memory@88f00000 { + removed_region: removed-region@88f00000 { no-map; reg = <0 0x88f00000 0 0x1c00000>; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 5fac82f026fd..28f7dc5c886a 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -79,22 +79,22 @@ #size-cells = <2>; ranges; - hyp_mem: memory@85700000 { + hyp_mem: hyp-mem@85700000 { reg = <0 0x85700000 0 0x600000>; no-map; }; - xbl_mem: memory@85e00000 { + xbl_mem: xbl-mem@85e00000 { reg = <0 0x85e00000 0 0x100000>; no-map; }; - aop_mem: memory@85fc0000 { + aop_mem: aop-mem@85fc0000 { reg = <0 0x85fc0000 0 0x20000>; no-map; }; - aop_cmd_db_mem: memory@85fe0000 { + aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 { compatible = "qcom,cmd-db"; reg = <0x0 0x85fe0000 0 0x20000>; no-map; @@ -107,12 +107,12 @@ hwlocks = <&tcsr_mutex 3>; }; - tz_mem: memory@86200000 { + tz_mem: tz@86200000 { reg = <0 0x86200000 0 0x2d00000>; no-map; }; - rmtfs_mem: memory@88f00000 { + rmtfs_mem: rmtfs@88f00000 { compatible = "qcom,rmtfs-mem"; reg = <0 0x88f00000 0 0x200000>; no-map; @@ -121,67 +121,67 @@ qcom,vmid = <15>; }; - qseecom_mem: memory@8ab00000 { + qseecom_mem: qseecom@8ab00000 { reg = <0 0x8ab00000 0 0x1400000>; no-map; }; - camera_mem: memory@8bf00000 { + camera_mem: camera-mem@8bf00000 { reg = <0 0x8bf00000 0 0x500000>; no-map; }; - ipa_fw_mem: memory@8c400000 { + ipa_fw_mem: ipa-fw@8c400000 { reg = <0 0x8c400000 0 0x10000>; no-map; }; - ipa_gsi_mem: memory@8c410000 { + ipa_gsi_mem: ipa-gsi@8c410000 { reg = <0 0x8c410000 0 0x5000>; no-map; }; - gpu_mem: memory@8c415000 { + gpu_mem: gpu@8c415000 { reg = <0 0x8c415000 0 0x2000>; no-map; }; - adsp_mem: memory@8c500000 { + adsp_mem: adsp@8c500000 { reg = <0 0x8c500000 0 0x1a00000>; no-map; }; - wlan_msa_mem: memory@8df00000 { + wlan_msa_mem: wlan-msa@8df00000 { reg = <0 0x8df00000 0 0x100000>; no-map; }; - mpss_region: memory@8e000000 { + mpss_region: mpss@8e000000 { reg = <0 0x8e000000 0 0x7800000>; no-map; }; - venus_mem: memory@95800000 { + venus_mem: venus@95800000 { reg = <0 0x95800000 0 0x500000>; no-map; }; - cdsp_mem: memory@95d00000 { + cdsp_mem: cdsp@95d00000 { reg = <0 0x95d00000 0 0x800000>; no-map; }; - mba_region: memory@96500000 { + mba_region: mba@96500000 { reg = <0 0x96500000 0 0x200000>; no-map; }; - slpi_mem: memory@96700000 { + slpi_mem: slpi@96700000 { reg = <0 0x96700000 0 0x1400000>; no-map; }; - spss_mem: memory@97b00000 { + spss_mem: spss@97b00000 { reg = <0 0x97b00000 0 0x100000>; no-map; }; -- cgit From abdd4b7a7a70b861c77151afab23880b5f80e9bc Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Thu, 16 Dec 2021 14:43:48 +0200 Subject: arm64: dts: qcom: sm8150: add i2c and spi dma channels By listing relevant DMA channels for the various QUPv3 instances, we can work on adding support for DMA to the respective drivers. Signed-off-by: Felipe Balbi Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211216124348.370059-1-balbi@kernel.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 120 +++++++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index c1067b31b299..e680c32371c0 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -932,6 +932,9 @@ reg = <0 0x00880000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c0_default>; interrupts = ; @@ -946,6 +949,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi0_default>; interrupts = ; @@ -960,6 +966,9 @@ reg = <0 0x00884000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c1_default>; interrupts = ; @@ -974,6 +983,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi1_default>; interrupts = ; @@ -988,6 +1000,9 @@ reg = <0 0x00888000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c2_default>; interrupts = ; @@ -1002,6 +1017,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi2_default>; interrupts = ; @@ -1016,6 +1034,9 @@ reg = <0 0x0088c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c3_default>; interrupts = ; @@ -1030,6 +1051,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi3_default>; interrupts = ; @@ -1044,6 +1068,9 @@ reg = <0 0x00890000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c4_default>; interrupts = ; @@ -1058,6 +1085,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi4_default>; interrupts = ; @@ -1072,6 +1102,9 @@ reg = <0 0x00894000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c5_default>; interrupts = ; @@ -1086,6 +1119,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi5_default>; interrupts = ; @@ -1100,6 +1136,9 @@ reg = <0 0x00898000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, + <&gpi_dma0 1 6 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c6_default>; interrupts = ; @@ -1114,6 +1153,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, + <&gpi_dma0 1 6 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi6_default>; interrupts = ; @@ -1128,6 +1170,9 @@ reg = <0 0x0089c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, + <&gpi_dma0 1 7 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c7_default>; interrupts = ; @@ -1142,6 +1187,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, + <&gpi_dma0 1 7 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi7_default>; interrupts = ; @@ -1192,6 +1240,9 @@ reg = <0 0x00a80000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c8_default>; interrupts = ; @@ -1206,6 +1257,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi8_default>; interrupts = ; @@ -1220,6 +1274,9 @@ reg = <0 0x00a84000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c9_default>; interrupts = ; @@ -1234,6 +1291,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi9_default>; interrupts = ; @@ -1248,6 +1308,9 @@ reg = <0 0x00a88000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c10_default>; interrupts = ; @@ -1262,6 +1325,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi10_default>; interrupts = ; @@ -1276,6 +1342,9 @@ reg = <0 0x00a8c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c11_default>; interrupts = ; @@ -1290,6 +1359,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi11_default>; interrupts = ; @@ -1313,6 +1385,9 @@ reg = <0 0x00a90000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c12_default>; interrupts = ; @@ -1327,6 +1402,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi12_default>; interrupts = ; @@ -1341,6 +1419,9 @@ reg = <0 0x0094000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, + <&gpi_dma2 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c16_default>; interrupts = ; @@ -1355,6 +1436,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, + <&gpi_dma2 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi16_default>; interrupts = ; @@ -1406,6 +1490,9 @@ reg = <0 0x00c80000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, + <&gpi_dma2 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c17_default>; interrupts = ; @@ -1420,6 +1507,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, + <&gpi_dma2 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi17_default>; interrupts = ; @@ -1434,6 +1524,9 @@ reg = <0 0x00c84000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, + <&gpi_dma2 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c18_default>; interrupts = ; @@ -1448,6 +1541,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, + <&gpi_dma2 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi18_default>; interrupts = ; @@ -1462,6 +1558,9 @@ reg = <0 0x00c88000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, + <&gpi_dma2 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c19_default>; interrupts = ; @@ -1476,6 +1575,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, + <&gpi_dma2 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi19_default>; interrupts = ; @@ -1490,6 +1592,9 @@ reg = <0 0x00c8c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, + <&gpi_dma2 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c13_default>; interrupts = ; @@ -1504,6 +1609,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, + <&gpi_dma2 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi13_default>; interrupts = ; @@ -1518,6 +1626,9 @@ reg = <0 0x00c90000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, + <&gpi_dma2 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c14_default>; interrupts = ; @@ -1532,6 +1643,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, + <&gpi_dma2 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi14_default>; interrupts = ; @@ -1546,6 +1660,9 @@ reg = <0 0x00c94000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, + <&gpi_dma2 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c15_default>; interrupts = ; @@ -1560,6 +1677,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, + <&gpi_dma2 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi15_default>; interrupts = ; -- cgit From 2a03c21cca5ffd527c9ea2e88e52e58e1c69331b Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Fri, 17 Dec 2021 14:45:46 +0200 Subject: arm64: dts: qcom: sm8150: simplify references to pwrkey and resin Since commit d0a6ce59ea4e ("arm64: dts: qcom: sm8150: Add support for SONY Xperia 1 / 5 (Kumano platform)"), we can directly refer to pwrkey and resin by their new labels, respectively pon_pwrkey and pon_resin. Simplify microsof surface duo DTS by utilizing the new labels. Signed-off-by: Felipe Balbi Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211217124546.1192281-1-balbi@kernel.org --- .../boot/dts/qcom/sm8150-microsoft-surface-duo.dts | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts index 5901c28e6696..a73317e1a824 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts @@ -430,18 +430,8 @@ /* MAX34417 @ 0x1e */ }; -&pon { - pwrkey { - status = "okay"; - }; - - resin { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = ; - }; +&pon_pwrkey { + status = "okay"; }; &qupv3_id_0 { @@ -476,6 +466,12 @@ firmware-name = "qcom/sm8150/microsoft/slpi.mdt"; }; +&pon_resin { + status = "okay"; + + linux,code = ; +}; + &tlmm { gpio-reserved-ranges = <126 4>; -- cgit From fad35efa75a22050bb4b7cace8c1c9dd4fc70d16 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 17 Dec 2021 15:11:36 -0600 Subject: arm64: dts: qcom: msm8998: Fix cache nodes The msm8998 cache nodes have some issues. First, L1 caches are described within cpu nodes, not as separate nodes. The 'next-level-cache' property is of course in the correct location, otherwise the cache hierarchy walking would not work. Remove all the L1 cache nodes. Second, 'arm,arch-cache' is not a documented compatible string. "cache" is a sufficient compatible string for the Arm architected caches. Signed-off-by: Rob Herring Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211217211136.3536443-1-robh@kernel.org --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 52 ++--------------------------------- 1 file changed, 2 insertions(+), 50 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 453a049f693d..2fda21e810c9 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -138,15 +138,9 @@ cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; next-level-cache = <&L2_0>; L2_0: l2-cache { - compatible = "arm,arch-cache"; + compatible = "cache"; cache-level = <2>; }; - L1_I_0: l1-icache { - compatible = "arm,arch-cache"; - }; - L1_D_0: l1-dcache { - compatible = "arm,arch-cache"; - }; }; CPU1: cpu@1 { @@ -157,12 +151,6 @@ capacity-dmips-mhz = <1024>; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; next-level-cache = <&L2_0>; - L1_I_1: l1-icache { - compatible = "arm,arch-cache"; - }; - L1_D_1: l1-dcache { - compatible = "arm,arch-cache"; - }; }; CPU2: cpu@2 { @@ -173,12 +161,6 @@ capacity-dmips-mhz = <1024>; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; next-level-cache = <&L2_0>; - L1_I_2: l1-icache { - compatible = "arm,arch-cache"; - }; - L1_D_2: l1-dcache { - compatible = "arm,arch-cache"; - }; }; CPU3: cpu@3 { @@ -189,12 +171,6 @@ capacity-dmips-mhz = <1024>; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; next-level-cache = <&L2_0>; - L1_I_3: l1-icache { - compatible = "arm,arch-cache"; - }; - L1_D_3: l1-dcache { - compatible = "arm,arch-cache"; - }; }; CPU4: cpu@100 { @@ -206,15 +182,9 @@ cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; next-level-cache = <&L2_1>; L2_1: l2-cache { - compatible = "arm,arch-cache"; + compatible = "cache"; cache-level = <2>; }; - L1_I_100: l1-icache { - compatible = "arm,arch-cache"; - }; - L1_D_100: l1-dcache { - compatible = "arm,arch-cache"; - }; }; CPU5: cpu@101 { @@ -225,12 +195,6 @@ capacity-dmips-mhz = <1536>; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; next-level-cache = <&L2_1>; - L1_I_101: l1-icache { - compatible = "arm,arch-cache"; - }; - L1_D_101: l1-dcache { - compatible = "arm,arch-cache"; - }; }; CPU6: cpu@102 { @@ -241,12 +205,6 @@ capacity-dmips-mhz = <1536>; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; next-level-cache = <&L2_1>; - L1_I_102: l1-icache { - compatible = "arm,arch-cache"; - }; - L1_D_102: l1-dcache { - compatible = "arm,arch-cache"; - }; }; CPU7: cpu@103 { @@ -257,12 +215,6 @@ capacity-dmips-mhz = <1536>; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; next-level-cache = <&L2_1>; - L1_I_103: l1-icache { - compatible = "arm,arch-cache"; - }; - L1_D_103: l1-dcache { - compatible = "arm,arch-cache"; - }; }; cpu-map { -- cgit From 0b9ae7ecdf54c5cce4b4cb052196b2b1c1ddbb6e Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Mon, 20 Dec 2021 15:55:26 +0100 Subject: arm64: dts: qcom: msm8996: qcom,controlled-remotely is boolean QCOM BAM parses property `qcom,controlled-remotely` as a boolean, adjust dts to reflect that. Discovered while converting text documentation into yaml format. Signed-off-by: David Heidelberg Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211220145526.49102-1-david@ixit.cz --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index fd58d7b00243..ae09007866e8 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -713,7 +713,7 @@ clock-names = "bam_clk"; #dma-cells = <1>; qcom,ee = <0>; - qcom,controlled-remotely = <1>; + qcom,controlled-remotely; }; crypto: crypto@67a000 { -- cgit From 3b87b01d747386e0429996266c063d7700d9813e Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Mon, 20 Dec 2021 22:14:43 +0100 Subject: arm64: dts: qcom: sdm845: add missing power-controller compatible dt-schema expect to have fallback compatible, which is now in-place. Fixes warning generated by `make qcom/sdm845-oneplus-fajita.dtb`: arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dt.yaml: power-controller@c300000: compatible: ['qcom,sdm845-aoss-qmp'] is too short From schema: Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml Signed-off-by: David Heidelberg Komu: David Heidelberg Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211220211443.106754-1-david@ixit.cz --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 28f7dc5c886a..0d6286d27dd4 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4619,7 +4619,7 @@ }; aoss_qmp: power-controller@c300000 { - compatible = "qcom,sdm845-aoss-qmp"; + compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x100000>; interrupts = ; mboxes = <&apss_shared 0>; -- cgit From ffd6cc92ab9cb426896481fa8372d38cbe53f76b Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Thu, 23 Dec 2021 09:56:40 +0200 Subject: arm64: dts: qcom: sm8250: add description of dcvsh interrupts The change adds SM8250 cpufreq-epss controller interrupts for each CPU core cluster. Signed-off-by: Vladimir Zapolskiy Cc: Thara Gopinath Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211223075640.2924569-1-vladimir.zapolskiy@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index db57c115d262..88cd82ed75b7 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -4571,7 +4571,10 @@ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; clock-names = "xo", "alternate"; - + interrupts = , + , + ; + interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; #freq-domain-cells = <1>; }; }; -- cgit From 4ec48ebfc3eab546c66c62ee13028f7e271cf496 Mon Sep 17 00:00:00 2001 From: Petr Vorel Date: Thu, 23 Dec 2021 09:31:52 +0100 Subject: arm64: dts: qcom: msm8994: SoC specific compatible strings for qcom-sdhci Signed-off-by: Petr Vorel Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211223083153.22435-2-petr.vorel@gmail.com --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 5a9a5ed0565f..955bdb0639fe 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -444,7 +444,7 @@ }; sdhc1: sdhci@f9824900 { - compatible = "qcom,sdhci-msm-v4"; + compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -467,7 +467,7 @@ }; sdhc2: sdhci@f98a4900 { - compatible = "qcom,sdhci-msm-v4"; + compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; reg-names = "hc_mem", "core_mem"; -- cgit From 52f6fa2d2d723b5f07b07856dc15a14c3f59d3a3 Mon Sep 17 00:00:00 2001 From: Petr Vorel Date: Thu, 23 Dec 2021 09:31:53 +0100 Subject: arm64: dts: qcom: msm8996: SoC specific compatible strings for qcom-sdhci Signed-off-by: Petr Vorel Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211223083153.22435-3-petr.vorel@gmail.com --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index ae09007866e8..5646195ba0a1 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -2693,7 +2693,7 @@ }; sdhc1: sdhci@7464900 { - compatible = "qcom,sdhci-msm-v4"; + compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; reg = <0x07464900 0x11c>, <0x07464000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -2716,7 +2716,7 @@ }; sdhc2: sdhci@74a4900 { - compatible = "qcom,sdhci-msm-v4"; + compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; reg = <0x074a4900 0x314>, <0x074a4000 0x800>; reg-names = "hc_mem", "core_mem"; -- cgit From e3e8a472429923d1c430bf388e9e3df1d9cc63a7 Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Mon, 27 Dec 2021 08:46:03 +0200 Subject: arm64: dts: qcom: ipq6018: add pcie max-link-speed Add the generic 'max-link-speed' property to describe the IPQ6018 PCIe link generation limit. This allows the generic dwc code to configure the link speed correctly. Signed-off-by: Baruch Siach Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/fcf41277cf8529437374a5c10b2b1fcad30cd7c2.1640587131.git.baruch@tkos.co.il --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 66ec5615651d..c25156a8ce6f 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -425,6 +425,7 @@ linux,pci-domain = <0>; bus-range = <0x00 0xff>; num-lanes = <1>; + max-link-speed = <3>; #address-cells = <3>; #size-cells = <2>; -- cgit From 5239ce22278a664c419e7afcbc38a93c6c569bc0 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Mon, 27 Dec 2021 22:52:37 +0100 Subject: arm64: dts: qcom: pms405: assign device specific compatible Follow common pattern for this device, first specific and then generic compatible. Signed-off-by: David Heidelberg Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211227215238.113956-1-david@ixit.cz --- arch/arm64/boot/dts/qcom/pms405.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi b/arch/arm64/boot/dts/qcom/pms405.dtsi index 172be177fc8f..98d173a377d5 100644 --- a/arch/arm64/boot/dts/qcom/pms405.dtsi +++ b/arch/arm64/boot/dts/qcom/pms405.dtsi @@ -32,7 +32,7 @@ &spmi_bus { pms405_0: pms405@0 { - compatible = "qcom,spmi-pmic"; + compatible = "qcom,pms405", "qcom,spmi-pmic"; reg = <0x0 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; @@ -139,7 +139,7 @@ }; pms405_1: pms405@1 { - compatible = "qcom,spmi-pmic"; + compatible = "qcom,pms405", "qcom,spmi-pmic"; reg = <0x1 SPMI_USID>; pms405_spmi_regulators: regulators { -- cgit From fe508ced49dd51a700c0f9ec7826d523cfe621b2 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 29 Dec 2021 18:03:57 +0100 Subject: arm64: dts: qcom: pm6150l: Add wled node WLED is used for controlling the backlight on some boards, add the node for it. Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211229170358.2457006-4-luca.weiss@fairphone.com --- arch/arm64/boot/dts/qcom/pm6150l.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/pm6150l.dtsi b/arch/arm64/boot/dts/qcom/pm6150l.dtsi index 3ca2860bb0cf..7aa2ef90cb6a 100644 --- a/arch/arm64/boot/dts/qcom/pm6150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150l.dtsi @@ -52,5 +52,15 @@ reg = <0x5 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; + + pm6150l_wled: leds@d800 { + compatible = "qcom,pm6150l-wled"; + reg = <0xd800>, <0xd900>; + interrupts = <0x5 0xd8 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ovp"; + label = "backlight"; + + status = "disabled"; + }; }; }; -- cgit From 7a52967d9050f3e430373bc51c56865b49a38573 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 29 Dec 2021 18:03:58 +0100 Subject: arm64: dts: qcom: sm7225-fairphone-fp4: Configure WLED WLED is used for controlling the display backlight on this phone, so configure the node and enable it. Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211229170358.2457006-5-luca.weiss@fairphone.com --- arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index d4af9e0dad87..adb6ca2be2a5 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -10,6 +10,7 @@ #include #include #include "sm7225.dtsi" +#include "pm6150l.dtsi" #include "pm6350.dtsi" / { @@ -300,6 +301,14 @@ firmware-name = "qcom/sm7225/fairphone4/modem.mdt"; }; +&pm6150l_wled { + status = "okay"; + + qcom,switching-freq = <800>; + qcom,current-limit-microamp = <20000>; + qcom,num-strings = <2>; +}; + &pm6350_gpios { gpio_keys_pin: gpio-keys-pin { pins = "gpio2"; -- cgit From 640e71aac554c70180a9b4faa455e80a58fb369e Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Wed, 29 Dec 2021 20:37:31 +0100 Subject: arm64: dts: qcom: msm8916: improve usb hs node formating qcom,init-seq registers are in pairs Signed-off-by: David Heidelberg Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211229193731.72690-1-david@ixit.cz --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 41897eb3736a..0a0be43529f6 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1731,8 +1731,10 @@ clock-names = "ref", "sleep"; resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; reset-names = "phy", "por"; - qcom,init-seq = /bits/ 8 <0x0 0x44 - 0x1 0x6b 0x2 0x24 0x3 0x13>; + qcom,init-seq = /bits/ 8 <0x0 0x44>, + <0x1 0x6b>, + <0x2 0x24>, + <0x3 0x13>; }; }; }; -- cgit From a90b8adfa2ddfd74944fa73be97fabe230f0046d Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Wed, 29 Dec 2021 23:01:17 +0100 Subject: Revert "arm64: dts: qcom: sm6125: Avoid using missing SM6125_VDDCX" This reverts commit c23f1b77358c173a25ef21303d2a8cc893e9ce22. The SM6125_VDDCX constant was replaced with 0 temporarily as the header patch defining this constant resided in a different branch, creating an unwanted dependency of the dts branch on the drivers branch. Now (by the time this patch will be applied) that both branches have been merged upstream, it is safe to revert to the constant again. Signed-off-by: Marijn Suijten Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211229220117.293542-1-marijn.suijten@somainline.org --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 49e6bca646c2..e81b2a7794fb 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -449,7 +449,7 @@ <&xo_board>; clock-names = "iface", "core", "xo"; - power-domains = <&rpmpd 0>; + power-domains = <&rpmpd SM6125_VDDCX>; bus-width = <8>; non-removable; @@ -474,7 +474,7 @@ pinctrl-1 = <&sdc2_state_off>; pinctrl-names = "default", "sleep"; - power-domains = <&rpmpd 0>; + power-domains = <&rpmpd SM6125_VDDCX>; bus-width = <4>; status = "disabled"; -- cgit From 1f87900493845c0a0d731496150e915649209f1c Mon Sep 17 00:00:00 2001 From: Petr Vorel Date: Fri, 31 Dec 2021 22:36:35 +0100 Subject: arm64: dts: qcom: msm8916-j5: Fix typo Fixes: bd943653b10d ("arm64: dts: qcom: Add device tree for Samsung J5 2015 (samsung-j5)") Signed-off-by: Petr Vorel Reviewed-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211231213635.116324-1-petr.vorel@gmail.com --- arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts index 687bea438a57..6c408d61de75 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts @@ -41,7 +41,7 @@ }; home-key { - lable = "Home Key"; + label = "Home Key"; gpios = <&msmgpio 109 GPIO_ACTIVE_LOW>; linux,code = ; }; -- cgit From 2ffcfe791d05e19feb105419efc030fc8ae1e527 Mon Sep 17 00:00:00 2001 From: Thara Gopinath Date: Thu, 6 Jan 2022 12:31:37 -0500 Subject: arm64: dts: qcom: sm8150: Add support for LMh node Add LMh nodes for cpu cluster0 and cpu cluster1 for sm8150 SoC. Signed-off-by: Thara Gopinath Reviewed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220106173138.411097-3-thara.gopinath@linaro.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index e680c32371c0..901c25a6c9c5 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -3769,6 +3769,30 @@ #freq-domain-cells = <1>; }; + lmh_cluster1: lmh@18350800 { + compatible = "qcom,sm8150-lmh"; + reg = <0 0x18350800 0 0x400>; + interrupts = ; + cpus = <&CPU4>; + qcom,lmh-temp-arm-millicelsius = <60000>; + qcom,lmh-temp-low-millicelsius = <84500>; + qcom,lmh-temp-high-millicelsius = <85000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + lmh_cluster0: lmh@18358800 { + compatible = "qcom,sm8150-lmh"; + reg = <0 0x18358800 0 0x400>; + interrupts = ; + cpus = <&CPU0>; + qcom,lmh-temp-arm-millicelsius = <60000>; + qcom,lmh-temp-low-millicelsius = <84500>; + qcom,lmh-temp-high-millicelsius = <85000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + wifi: wifi@18800000 { compatible = "qcom,wcn3990-wifi"; reg = <0 0x18800000 0 0x800000>; -- cgit From 42124b947e8eee401b778e9bdc5017d205ad8b71 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Thu, 6 Jan 2022 22:25:12 +0100 Subject: arm64: dts: qcom: ipq8074: add SMEM support IPQ8074 uses SMEM like other modern QCA SoC-s, so since its already supported by the kernel add the required DT nodes. Signed-off-by: Robert Marko Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220106212512.1970828-1-robimarko@gmail.com --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index e6cc261201ef..bd70092b7156 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -76,6 +76,20 @@ method = "smc"; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + smem@4ab00000 { + compatible = "qcom,smem"; + reg = <0x0 0x4ab00000 0x0 0x00100000>; + no-map; + + hwlocks = <&tcsr_mutex 0>; + }; + }; + firmware { scm { compatible = "qcom,scm-ipq8074", "qcom,scm"; @@ -331,6 +345,12 @@ #reset-cells = <0x1>; }; + tcsr_mutex: hwlock@1905000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x01905000 0x20000>; + #hwlock-cells = <1>; + }; + spmi_bus: spmi@200f000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x0200f000 0x001000>, -- cgit From c210c1d8f19d3a33802af1bc79934188d994e92c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 29 Jan 2022 18:55:57 +0100 Subject: arm64: dts: broadcom: align pl330 node name with dtschema Fixes dtbs_check warnings like: dma@310000: $nodename:0: 'dma@310000' does not match '^dma-controller(@.*)?$' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi | 2 +- arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi index 2cfeaf3b0a87..6da38ac317f2 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi @@ -276,7 +276,7 @@ mboxes = <&pdc3 0>; }; - dma0: dma@61360000 { + dma0: dma-controller@61360000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x61360000 0x1000>; interrupts = , diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi index 7b04dfe67bef..4135246b6e72 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi @@ -543,7 +543,7 @@ reg = <0x00220000 0x28>; }; - dma0: dma@310000 { + dma0: dma-controller@310000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x00310000 0x1000>; interrupts = , -- cgit From 33826e9c6ba76b265d4e26cb95493fa27ed78974 Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Wed, 29 Dec 2021 11:23:14 +0100 Subject: arm64: dts: broadcom: bcm4908: use proper TWD binding MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Block at is a TWD that contains timers, watchdog and reset. Actual timers happen to be at block beginning but they only span across the first 0x28 registers. It means the old block description was incorrect (size 0x3c). Drop timers binding for now and use documented TWD binding. Timers should be properly documented and defined as TWD subnode. Fixes: 2961f69f151c ("arm64: dts: broadcom: add BCM4908 and Asus GT-AC5300 early DTS files") Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi index 984c737fa627..6e738f2a3701 100644 --- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi @@ -273,9 +273,9 @@ #size-cells = <1>; ranges = <0x00 0x00 0xff800000 0x3000>; - timer: timer@400 { - compatible = "brcm,bcm6328-timer", "syscon"; - reg = <0x400 0x3c>; + twd: timer-mfd@400 { + compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon"; + reg = <0x400 0x4c>; }; gpio0: gpio-controller@500 { @@ -330,7 +330,7 @@ reboot { compatible = "syscon-reboot"; - regmap = <&timer>; + regmap = <&twd>; offset = <0x34>; mask = <1>; }; -- cgit From 72b1c5da796ec5266f2012c36470e226cb4f09c9 Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Thu, 30 Dec 2021 12:05:35 +0100 Subject: arm64: dts: broadcom: bcm4908: add pinctrl binding MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Describe pinmux block with its maps. Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 135 ++++++++++++++++++++++ 1 file changed, 135 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi index 6e738f2a3701..255c1ea2add4 100644 --- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi @@ -287,6 +287,141 @@ gpio-controller; }; + pinctrl@560 { + compatible = "brcm,bcm4908-pinctrl"; + reg = <0x560 0x10>; + + pins_led_0_a: led_0-a-pins { + function = "led_0"; + groups = "led_0_grp_a"; + }; + + pins_led_1_a: led_1-a-pins { + function = "led_1"; + groups = "led_1_grp_a"; + }; + + pins_led_2_a: led_2-a-pins { + function = "led_2"; + groups = "led_2_grp_a"; + }; + + pins_led_3_a: led_3-a-pins { + function = "led_3"; + groups = "led_3_grp_a"; + }; + + pins_led_4_a: led_4-a-pins { + function = "led_4"; + groups = "led_4_grp_a"; + }; + + pins_led_5_a: led_5-a-pins { + function = "led_5"; + groups = "led_5_grp_a"; + }; + + pins_led_6_a: led_6-a-pins { + function = "led_6"; + groups = "led_6_grp_a"; + }; + + pins_led_7_a: led_7-a-pins { + function = "led_7"; + groups = "led_7_grp_a"; + }; + + pins_led_8_a: led_8-a-pins { + function = "led_8"; + groups = "led_8_grp_a"; + }; + + pins_led_9_a: led_9-a-pins { + function = "led_9"; + groups = "led_9_grp_a"; + }; + + pins_led_21_a: led_21-a-pins { + function = "led_21"; + groups = "led_21_grp_a"; + }; + + pins_led_22_a: led_22-a-pins { + function = "led_22"; + groups = "led_22_grp_a"; + }; + + pins_led_26_a: led_26-a-pins { + function = "led_26"; + groups = "led_26_grp_a"; + }; + + pins_led_27_a: led_27-a-pins { + function = "led_27"; + groups = "led_27_grp_a"; + }; + + pins_led_28_a: led_28-a-pins { + function = "led_28"; + groups = "led_28_grp_a"; + }; + + pins_led_29_a: led_29-a-pins { + function = "led_29"; + groups = "led_29_grp_a"; + }; + + pins_led_30_a: led_30-a-pins { + function = "led_30"; + groups = "led_30_grp_a"; + }; + + pins_hs_uart: hs_uart-pins { + function = "hs_uart"; + groups = "hs_uart_grp"; + }; + + pins_i2c_a: i2c-a-pins { + function = "i2c"; + groups = "i2c_grp_a"; + }; + + pins_i2c_b: i2c-b-pins { + function = "i2c"; + groups = "i2c_grp_b"; + }; + + pins_i2s: i2s-pins { + function = "i2s"; + groups = "i2s_grp"; + }; + + pins_nand_ctrl: nand_ctrl-pins { + function = "nand_ctrl"; + groups = "nand_ctrl_grp"; + }; + + pins_nand_data: nand_data-pins { + function = "nand_data"; + groups = "nand_data_grp"; + }; + + pins_emmc_ctrl: emmc_ctrl-pins { + function = "emmc_ctrl"; + groups = "emmc_ctrl_grp"; + }; + + pins_usb0_pwr: usb0_pwr-pins { + function = "usb0_pwr"; + groups = "usb0_pwr_grp"; + }; + + pins_usb1_pwr: usb1_pwr-pins { + function = "usb1_pwr"; + groups = "usb1_pwr_grp"; + }; + }; + uart0: serial@640 { compatible = "brcm,bcm6345-uart"; reg = <0x640 0x18>; -- cgit From e4a4fdcf70854de2bd9bb774a0985aa9dafd2e1c Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Fri, 7 Jan 2022 18:24:38 +0530 Subject: arm64: dts: qcom: ipq8074: add the reserved-memory node On IPQ8074, 4MB of memory is needed for TZ. So mark that region as reserved. Signed-off-by: Kathiravan T [bjorn: Squash with existing reserved-memory node] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1641560078-860-1-git-send-email-quic_kathirav@quicinc.com --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index bd70092b7156..27624f5a56ba 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -88,6 +88,11 @@ hwlocks = <&tcsr_mutex 0>; }; + + memory@4ac00000 { + no-map; + reg = <0x0 0x4ac00000 0x0 0x00400000>; + }; }; firmware { -- cgit From 17ac8af678b6da6a8f1df7da8ebf2c5198741827 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Sun, 9 Jan 2022 22:54:58 +0530 Subject: arm64: dts: qcom: sm8150: Correct TCS configuration for apps rsc Correct the TCS config by updating the number of TCSes for each type. Cc: devicetree@vger.kernel.org Fixes: d8cf9372b654 ("arm64: dts: qcom: sm8150: Add apps shared nodes") Signed-off-by: Maulik Shah Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1641749107-31979-2-git-send-email-quic_mkshah@quicinc.com --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 901c25a6c9c5..d15fee495238 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -3676,9 +3676,9 @@ qcom,tcs-offset = <0xd00>; qcom,drv-id = <2>; qcom,tcs-config = , - , - , - ; + , + , + ; rpmhcc: clock-controller { compatible = "qcom,sm8150-rpmh-clk"; -- cgit From 32bc936d732171d48c9c8f96c4fa25ac3ed7e1c7 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Sun, 9 Jan 2022 22:54:59 +0530 Subject: arm64: dts: qcom: sm8250: Add cpuidle states This change adds various idle states and add devices to power domains. Cc: devicetree@vger.kernel.org Signed-off-by: Maulik Shah Reviewed-by: Ulf Hansson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1641749107-31979-3-git-send-email-quic_mkshah@quicinc.com --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 105 +++++++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 88cd82ed75b7..3c92097324c3 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -98,6 +98,8 @@ capacity-dmips-mhz = <448>; dynamic-power-coefficient = <205>; next-level-cache = <&L2_0>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, @@ -120,6 +122,8 @@ capacity-dmips-mhz = <448>; dynamic-power-coefficient = <205>; next-level-cache = <&L2_100>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, @@ -139,6 +143,8 @@ capacity-dmips-mhz = <448>; dynamic-power-coefficient = <205>; next-level-cache = <&L2_200>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, @@ -158,6 +164,8 @@ capacity-dmips-mhz = <448>; dynamic-power-coefficient = <205>; next-level-cache = <&L2_300>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, @@ -177,6 +185,8 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <379>; next-level-cache = <&L2_400>; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, @@ -196,6 +206,8 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <379>; next-level-cache = <&L2_500>; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, @@ -216,6 +228,8 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <379>; next-level-cache = <&L2_600>; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, @@ -235,6 +249,8 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <444>; next-level-cache = <&L2_700>; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 2>; operating-points-v2 = <&cpu7_opp_table>; interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, @@ -281,6 +297,42 @@ }; }; }; + + idle-states { + entry-method = "psci"; + + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "silver-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <360>; + exit-latency-us = <531>; + min-residency-us = <3934>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "gold-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <702>; + exit-latency-us = <1061>; + min-residency-us = <4488>; + local-timer-stop; + }; + }; + + domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + idle-state-name = "cluster-llcc-off"; + arm,psci-suspend-param = <0x4100c244>; + entry-latency-us = <3264>; + exit-latency-us = <6562>; + min-residency-us = <9987>; + local-timer-stop; + }; + }; }; cpu0_opp_table: cpu0_opp_table { @@ -594,6 +646,59 @@ psci { compatible = "arm,psci-1.0"; method = "smc"; + + CPU_PD0: cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD1: cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD2: cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD3: cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD4: cpu4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD5: cpu5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD6: cpu6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD7: cpu7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CLUSTER_PD: cpu-cluster0 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_0>; + }; }; reserved-memory { -- cgit From a131255e4ad1ef8d4873ecba21561ba272b2547a Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Sun, 9 Jan 2022 22:55:00 +0530 Subject: arm64: dts: qcom: sm8350: Correct TCS configuration for apps rsc Correct the TCS config by updating the number of TCSes for each type. Cc: devicetree@vger.kernel.org Fixes: b7e8f433a673 ("arm64: dts: qcom: Add basic devicetree support for SM8350 SoC") Signed-off-by: Maulik Shah Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1641749107-31979-4-git-send-email-quic_mkshah@quicinc.com --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index abd15999773c..8166b5f5bb9e 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1802,7 +1802,7 @@ qcom,tcs-offset = <0xd00>; qcom,drv-id = <2>; qcom,tcs-config = , , - , ; + , ; rpmhcc: clock-controller { compatible = "qcom,sm8350-rpmh-clk"; -- cgit From 6574702b0d394d2acc9ff808c4a79df8b9999173 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Sun, 9 Jan 2022 22:55:01 +0530 Subject: arm64: dts: qcom: sm8450: Update cpuidle states parameters This change updates/corrects below cpuidle parameters 1. entry-latency, exit-latency and residency for various idle states. 2. arm,psci-suspend-param which is same for CLUSTER_SLEEP_0/1 states. 3. Add CLUSTER_SLEEP_1 in CLUSTER_PD. Cc: devicetree@vger.kernel.org Fixes: 5188049c9b36 ("arm64: dts: qcom: Add base SM8450 DTSI") Signed-off-by: Maulik Shah Reviewed-by: Ulf Hansson [bjorn: Split domain-idle-states, per Ulf's request] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1641749107-31979-5-git-send-email-quic_mkshah@quicinc.com --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 10c25ad2d0c7..dbc5eea2ebba 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -203,9 +203,9 @@ compatible = "arm,idle-state"; idle-state-name = "silver-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <274>; - exit-latency-us = <480>; - min-residency-us = <3934>; + entry-latency-us = <800>; + exit-latency-us = <750>; + min-residency-us = <4090>; local-timer-stop; }; @@ -213,9 +213,9 @@ compatible = "arm,idle-state"; idle-state-name = "gold-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <327>; - exit-latency-us = <1502>; - min-residency-us = <4488>; + entry-latency-us = <600>; + exit-latency-us = <1550>; + min-residency-us = <4791>; local-timer-stop; }; }; @@ -224,10 +224,10 @@ CLUSTER_SLEEP_0: cluster-sleep-0 { compatible = "domain-idle-state"; idle-state-name = "cluster-l3-off"; - arm,psci-suspend-param = <0x4100c344>; - entry-latency-us = <584>; - exit-latency-us = <2332>; - min-residency-us = <6118>; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <1050>; + exit-latency-us = <2500>; + min-residency-us = <5309>; local-timer-stop; }; @@ -235,9 +235,9 @@ compatible = "domain-idle-state"; idle-state-name = "cluster-power-collapse"; arm,psci-suspend-param = <0x4100c344>; - entry-latency-us = <2893>; - exit-latency-us = <4023>; - min-residency-us = <9987>; + entry-latency-us = <2700>; + exit-latency-us = <3500>; + min-residency-us = <13959>; local-timer-stop; }; }; @@ -315,7 +315,7 @@ CLUSTER_PD: cpu-cluster0 { #power-domain-cells = <0>; - domain-idle-states = <&CLUSTER_SLEEP_0>; + domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; }; }; -- cgit From 1b7101e8124b450f2d6a35591e9cbb478c143ace Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 12 Jan 2022 09:25:56 +0530 Subject: arm64: dts: qcom: sm8250: Fix MSI IRQ for PCIe1 and PCIe2 Fix the MSI IRQ used for PCIe instances 1 and 2. Cc: stable@vger.kernel.org Fixes: e53bdfc00977 ("arm64: dts: qcom: sm8250: Add PCIe support") Reported-by: Jordan Crouse Signed-off-by: Manivannan Sadhasivam Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220112035556.5108-1-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 3c92097324c3..fdaf303ba047 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1906,7 +1906,7 @@ ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; - interrupts = ; + interrupts = ; interrupt-names = "msi"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; @@ -2012,7 +2012,7 @@ ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>, <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; - interrupts = ; + interrupts = ; interrupt-names = "msi"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; -- cgit From 4dd1ad6192748523878463a285346db408b34a02 Mon Sep 17 00:00:00 2001 From: Petr Vorel Date: Fri, 14 Jan 2022 00:33:55 +0100 Subject: arm64: dts: qcom: msm8994: Provide missing "xo_board" and "sleep_clk" to GCC This is needed due changes in commit 0519d1d0bf33 ("clk: qcom: gcc-msm8994: Modernize the driver"), which removed struct clk_fixed_factor. Preparation for next commit for enabling SD/eMMC. Inspired by 2c2f64ae36d9. This is required for both msm8994-huawei-angler (sdhc1 will be enabled in next commit) and msm8992-lg-bullhead (where actually fixes sdhc1 - tested on bullhead rev 1.01). Fixes: 0519d1d0bf33 ("clk: qcom: gcc-msm8994: Modernize the driver") Signed-off-by: Petr Vorel Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220113233358.17972-4-petr.vorel@gmail.com --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 955bdb0639fe..8c1dc5155b71 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -713,6 +713,9 @@ #reset-cells = <1>; #power-domain-cells = <1>; reg = <0xfc400000 0x2000>; + + clock-names = "xo", "sleep_clk"; + clocks = <&xo_board>, <&sleep_clk>; }; rpm_msg_ram: sram@fc428000 { -- cgit From 8af90d6daa36a7180a2cd6aad874136aade27412 Mon Sep 17 00:00:00 2001 From: Petr Vorel Date: Fri, 14 Jan 2022 00:33:56 +0100 Subject: arm64: dts: qcom: msm8994-huawei-angler: Add vendor name huawei to follow the naming convention used by other DTS files. Signed-off-by: Petr Vorel Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220113233358.17972-5-petr.vorel@gmail.com --- arch/arm64/boot/dts/qcom/Makefile | 2 +- .../arm64/boot/dts/qcom/msm8994-angler-rev-101.dts | 43 ---------------------- .../dts/qcom/msm8994-huawei-angler-rev-101.dts | 43 ++++++++++++++++++++++ 3 files changed, 44 insertions(+), 44 deletions(-) delete mode 100644 arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts create mode 100644 arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 596e5df1c92b..5a1ca5500cee 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -22,7 +22,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8992-lg-bullhead-rev-10.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-lg-bullhead-rev-101.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-msft-lumia-octagon-talkman.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-xiaomi-libra.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8994-huawei-angler-rev-101.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8994-msft-lumia-octagon-cityman.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-ivy.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-karin.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts deleted file mode 100644 index 0e3dd48f0dbf..000000000000 --- a/arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2015, Huawei Inc. All rights reserved. - * Copyright (c) 2016, The Linux Foundation. All rights reserved. - * Copyright (c) 2021, Petr Vorel - */ - -/dts-v1/; - -#include "msm8994.dtsi" - -/* Angler's firmware does not report where the memory is allocated */ -/delete-node/ &cont_splash_mem; - -/ { - model = "Huawei Nexus 6P"; - compatible = "huawei,angler", "qcom,msm8994"; - chassis-type = "handset"; - /* required for bootloader to select correct board */ - qcom,msm-id = <207 0x20000>; - qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>; - qcom,board-id = <8026 0>; - - aliases { - serial0 = &blsp1_uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - soc { - serial@f991e000 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart2_default>; - pinctrl-1 = <&blsp1_uart2_sleep>; - }; - }; -}; - -&tlmm { - gpio-reserved-ranges = <85 4>; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts new file mode 100644 index 000000000000..0e3dd48f0dbf --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2015, Huawei Inc. All rights reserved. + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * Copyright (c) 2021, Petr Vorel + */ + +/dts-v1/; + +#include "msm8994.dtsi" + +/* Angler's firmware does not report where the memory is allocated */ +/delete-node/ &cont_splash_mem; + +/ { + model = "Huawei Nexus 6P"; + compatible = "huawei,angler", "qcom,msm8994"; + chassis-type = "handset"; + /* required for bootloader to select correct board */ + qcom,msm-id = <207 0x20000>; + qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>; + qcom,board-id = <8026 0>; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + soc { + serial@f991e000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_uart2_default>; + pinctrl-1 = <&blsp1_uart2_sleep>; + }; + }; +}; + +&tlmm { + gpio-reserved-ranges = <85 4>; +}; -- cgit From d1c10ab1494f09eb12fa6e58fc78bb28d44922ae Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Thu, 20 Jan 2022 20:43:41 +0200 Subject: arm64: dts: qcom: ipq6018: fix usb reference period Reference clock period for rate of 24MHz is 41ns (0x29). Link: https://lore.kernel.org/r/1965fc315525b8ab26cf9f71f939c24d@codeaurora.org Link: https://lore.kernel.org/r/a1932eba-564c-fe32-f220-53aa75250105@seco.com Fixes: 20bb9e3dd2e4 ("arm64: dts: qcom: ipq6018: add usb3 DT description") Reported-by: Kathiravan T Signed-off-by: Baruch Siach Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/4f4df55cf44cd0fd7d773aca171d4f48662fb1a5.1642704221.git.baruch@tkos.co.il --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index c25156a8ce6f..aa8068193ccb 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -749,7 +749,7 @@ snps,hird-threshold = /bits/ 8 <0x0>; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; - snps,ref-clock-period-ns = <0x32>; + snps,ref-clock-period-ns = <0x29>; dr_mode = "host"; }; }; -- cgit From 12dfb002ca01feceac9eaa2cc8a55fdc9be4a9ae Mon Sep 17 00:00:00 2001 From: Caleb Connolly Date: Thu, 20 Jan 2022 18:46:28 +0000 Subject: arm64: dts: qcom: sdm845-oneplus-*: add fuel gauge The OnePlus 6 and 6T feature a BQ27411 fuel gauge for reading the battery stats. Enable it and add a simple battery to document the battery specs of each device. Signed-off-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220120184546.499030-1-caleb@connolly.tech --- arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 11 +++++++++++ arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts | 12 ++++++++++++ arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts | 12 ++++++++++++ 3 files changed, 35 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 511ca72f465e..1084d5ce9ac7 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -376,6 +376,17 @@ }; }; +&i2c10 { + status = "okay"; + clock-frequency = <100000>; + + bq27441_fg: bq27441-battery@55 { + compatible = "ti,bq27411"; + status = "okay"; + reg = <0x55>; + }; +}; + &i2c12 { status = "okay"; clock-frequency = <400000>; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts index 5936b47dee5f..bf2cf92e8976 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts @@ -13,6 +13,14 @@ chassis-type = "handset"; qcom,msm-id = <0x141 0x20001>; qcom,board-id = <8 0 17819 22>; + + battery: battery { + compatible = "simple-battery"; + + charge-full-design-microamp-hours = <3300000>; + voltage-min-design-microvolt = <3400000>; + voltage-max-design-microvolt = <4400000>; + }; }; &display_panel { @@ -20,3 +28,7 @@ compatible = "samsung,sofef00"; }; + +&bq27441_fg { + monitored-battery = <&battery>; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts index 78a0b99144e6..1b6b5bf368df 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts @@ -13,6 +13,14 @@ chassis-type = "handset"; qcom,msm-id = <0x141 0x20001>; qcom,board-id = <8 0 18801 41>; + + battery: battery { + compatible = "simple-battery"; + + charge-full-design-microamp-hours = <3700000>; + voltage-min-design-microvolt = <3400000>; + voltage-max-design-microvolt = <4400000>; + }; }; &display_panel { @@ -21,6 +29,10 @@ compatible = "samsung,s6e3fc2x01"; }; +&bq27441_fg { + monitored-battery = <&battery>; +}; + &rmi4_f12 { touchscreen-y-mm = <148>; }; -- cgit From 45882459159deb792718786514bc677c8a6b1f53 Mon Sep 17 00:00:00 2001 From: Alexander Martinz Date: Sun, 23 Jan 2022 17:38:15 +0000 Subject: arm64: dts: qcom: sdm845: add device tree for SHIFT6mq Add initial support for the SHIFT SHIFT6mq (axolotl) based on the sdm845-mtp DT. Currently supported features: * Buttons (power, volume) * Bluetooth, DSPs and modem * Display and GPU * Touch * UART * USB peripheral mode * WLAN Co-developed-by: Caleb Connolly Signed-off-by: Caleb Connolly Signed-off-by: Alexander Martinz Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220123173650.290349-7-caleb@connolly.tech --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts | 736 ++++++++++++++++++++++ 2 files changed, 737 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 5a1ca5500cee..8aa3b3f1a292 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -104,6 +104,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-akari.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-akatsuki.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-apollo.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm845-shift-axolotl.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts new file mode 100644 index 000000000000..8553c8bf79bd --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -0,0 +1,736 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022, Alexander Martinz + * Copyright (c) 2022, Caleb Connolly + */ + +/dts-v1/; + +#include +#include +#include "sdm845.dtsi" +#include "pm8998.dtsi" +#include "pmi8998.dtsi" + +/ { + model = "SHIFT SHIFT6mq"; + compatible = "shift,axolotl", "qcom,sdm845"; + qcom,msm-id = <321 0x20001>; + qcom,board-id = <11 0>; + + aliases { + display0 = &framebuffer0; + serial0 = &uart9; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "serial0"; + + /* Use framebuffer setup by the bootloader. */ + framebuffer0: framebuffer@9d400000 { + compatible = "simple-framebuffer"; + reg = <0x0 0x9d400000 0x0 (1080 * 2160 * 4)>; + width = <1080>; + height = <2160>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&volume_up_gpio>; + + vol-up { + label = "volume_up"; + linux,code = ; + gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + }; + }; + + reserved-memory { + framebuffer_region@9d400000 { + reg = <0x0 0x9d400000 0x0 (1080 * 2160 * 4)>; + no-map; + }; + + ramoops: ramoops@b0000000 { + compatible = "ramoops"; + reg = <0 0xb0000000 0 0x00400000>; + record-size = <0x40000>; + console-size = <0x40000>; + ftrace-size = <0x40000>; + pmsg-size = <0x200000>; + ecc-size = <0x0>; + }; + }; + + battery: battery { + compatible = "simple-battery"; + + charge-full-design-microamp-hours = <3850000>; + voltage-min-design-microvolt = <3600000>; + voltage-max-design-microvolt = <4400000>; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + vreg_s4a_1p8: pm8998-smps4 { + compatible = "regulator-fixed"; + regulator-name = "vreg_s4a_1p8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&vph_pwr>; + }; +}; + +&adsp_pas { + status = "okay"; + firmware-name = "qcom/sdm845/axolotl/adsp.mbn"; +}; + +&apps_rsc { + pm8998-rpmh-regulators { + compatible = "qcom,pm8998-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-s11-supply = <&vph_pwr>; + vdd-s12-supply = <&vph_pwr>; + vdd-s13-supply = <&vph_pwr>; + vdd-l1-l27-supply = <&vreg_s7a_1p025>; + vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>; + vdd-l3-l11-supply = <&vreg_s7a_1p025>; + vdd-l4-l5-supply = <&vreg_s7a_1p025>; + vdd-l6-supply = <&vph_pwr>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; + vdd-l9-supply = <&vreg_bob>; + vdd-l10-l23-l25-supply = <&vreg_bob>; + vdd-l13-l19-l21-supply = <&vreg_bob>; + vdd-l16-l28-supply = <&vreg_bob>; + vdd-l18-l22-supply = <&vreg_bob>; + vdd-l20-l24-supply = <&vreg_bob>; + vdd-l26-supply = <&vreg_s3a_1p35>; + vin-lvs-1-2-supply = <&vreg_s4a_1p8>; + + vreg_s2a_1p125: smps2 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + vreg_s3a_1p35: smps3 { + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_s5a_2p04: smps5 { + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s7a_1p025: smps7 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1028000>; + }; + + vdd_qusb_hs0: + vdda_hp_pcie_core: + vdda_mipi_csi0_0p9: + vdda_mipi_csi1_0p9: + vdda_mipi_csi2_0p9: + vdda_mipi_dsi0_pll: + vdda_mipi_dsi1_pll: + vdda_qlink_lv: + vdda_qlink_lv_ck: + vdda_qrefs_0p875: + vdda_pcie_core: + vdda_pll_cc_ebi01: + vdda_pll_cc_ebi23: + vdda_sp_sensor: + vdda_ufs1_core: + vdda_ufs2_core: + vdda_usb1_ss_core: + vdda_usb2_ss_core: + vreg_l1a_0p875: ldo1 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vddpx_10: + vreg_l2a_1p2: ldo2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l3a_1p0: ldo3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = ; + }; + + vdd_wcss_cx: + vdd_wcss_mx: + vdda_wcss_pll: + vreg_l5a_0p8: ldo5 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vddpx_13: + vreg_l6a_1p8: ldo6 { + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <1856000>; + regulator-initial-mode = ; + }; + + vreg_l7a_1p8: ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l8a_1p2: ldo8 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1248000>; + regulator-initial-mode = ; + }; + + vreg_l9a_1p8: ldo9 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + vreg_l10a_1p8: ldo10 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + vreg_l11a_1p0: ldo11 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1048000>; + regulator-initial-mode = ; + }; + + vdd_qfprom: + vdd_qfprom_sp: + vdda_apc1_cs_1p8: + vdda_gfx_cs_1p8: + vdda_qrefs_1p8: + vdda_qusb_hs0_1p8: + vddpx_11: + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vddpx_2: + vreg_l13a_2p95: ldo13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l14a_1p88: ldo14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l15a_1p8: ldo15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l16a_2p7: ldo16 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + regulator-initial-mode = ; + }; + + vreg_l17a_1p3: ldo17 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l18a_2p7: ldo18 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l19a_3p0: ldo19 { + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = ; + }; + + vreg_l20a_2p95: ldo20 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l21a_2p95: ldo21 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l22a_2p85: ldo22 { + regulator-min-microvolt = <2864000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vreg_l23a_3p3: ldo23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vdda_qusb_hs0_3p1: + vreg_l24a_3p075: ldo24 { + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3088000>; + regulator-initial-mode = ; + }; + + vreg_l25a_3p3: ldo25 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vdda_hp_pcie_1p2: + vdda_hv_ebi0: + vdda_hv_ebi1: + vdda_hv_ebi2: + vdda_hv_ebi3: + vdda_mipi_csi_1p25: + vdda_mipi_dsi0_1p2: + vdda_mipi_dsi1_1p2: + vdda_pcie_1p2: + vdda_ufs1_1p2: + vdda_ufs2_1p2: + vdda_usb1_ss_1p2: + vdda_usb2_ss_1p2: + vreg_l26a_1p2: ldo26 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l28a_3p0: ldo28 { + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_lvs1a_1p8: lvs1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_lvs2a_1p8: lvs2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + pmi8998-rpmh-regulators { + compatible = "qcom,pmi8998-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob-supply = <&vph_pwr>; + + vreg_bob: bob { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3600000>; + regulator-initial-mode = ; + regulator-allow-bypass; + }; + }; + + pm8005-rpmh-regulators { + compatible = "qcom,pm8005-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s3c_0p6: smps3 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <600000>; + }; + }; +}; + +&cdsp_pas { + status = "okay"; + firmware-name = "qcom/sdm845/axolotl/cdsp.mbn"; +}; + +&dsi0 { + status = "okay"; + vdda-supply = <&vdda_mipi_dsi0_1p2>; + + panel@0 { + compatible = "visionox,rm69299-shift"; + status = "okay"; + reg = <0>; + vdda-supply = <&vreg_l14a_1p88>; + vdd3p3-supply = <&vreg_l28a_3p0>; + + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + + port { + panel_in_0: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; +}; + +&dsi0_out { + remote-endpoint = <&panel_in_0>; + data-lanes = <0 1 2 3>; +}; + +&dsi0_phy { + status = "okay"; + vdds-supply = <&vdda_mipi_dsi0_pll>; +}; + +&gcc { + protected-clocks = , + , + , + , + ; +}; + +&gmu { + status = "okay"; +}; + +&gpu { + status = "okay"; + + zap-shader { + memory-region = <&gpu_mem>; + firmware-name = "qcom/sdm845/axolotl/a630_zap.mbn"; + }; +}; + +&i2c5 { + status="okay"; + + touchscreen@38 { + compatible = "focaltech,fts8719"; + reg = <0x38>; + wakeup-source; + interrupt-parent = <&tlmm>; + interrupts = <125 0x2>; + vdd-supply = <&vreg_l28a_3p0>; + vcc-i2c-supply = <&vreg_l14a_1p88>; + + pinctrl-names = "default", "suspend"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + + reset-gpio = <&tlmm 99 GPIO_ACTIVE_HIGH>; + irq-gpio = <&tlmm 125 GPIO_TRANSITORY>; + touchscreen-size-x = <1080>; + touchscreen-size-y = <2160>; + focaltech,max-touch-number = <5>; + }; +}; + +&ipa { + status = "okay"; + + memory-region = <&ipa_fw_mem>; + firmware-name = "qcom/sdm845/axolotl/ipa_fws.mbn"; +}; + +&mdss { + status = "okay"; +}; + +&mss_pil { + status = "okay"; + firmware-name = "qcom/sdm845/axolotl/mba.mbn", "qcom/sdm845/axolotl/modem.mbn"; +}; + +&pm8998_gpio { + volume_up_gpio: pm8998_gpio6 { + pinconf { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,drive-strength = <0>; + }; + }; +}; + +&pm8998_pon { + volume_down_resin: resin { + compatible = "qcom,pm8941-resin"; + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = ; + }; +}; + +&qup_uart9_default { + pinconf-rx { + pins = "gpio5"; + drive-strength = <2>; + bias-pull-up; + }; + + pinconf-tx { + pins = "gpio4"; + drive-strength = <2>; + bias-disable; + }; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <81 4>; + + sde_dsi_active: sde-dsi-active { + mux { + pins = "gpio6", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio11"; + drive-strength = <8>; + bias-disable = <0>; + }; + }; + + sde_dsi_suspend: sde-dsi-suspend { + mux { + pins = "gpio6", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio11"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + sde_te_active: sde-te-active { + mux { + pins = "gpio10"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + sde_te_suspend: sde-te-suspend { + mux { + pins = "gpio10"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + ts_int_active: ts-int-active { + mux { + pins = "gpio125"; + function = "gpio"; + }; + + config { + pins = "gpio125"; + drive-strength = <8>; + bias-pull-up; + input-enable; + }; + }; + + ts_int_suspend: ts-int-suspend { + mux { + pins = "gpio125"; + function = "gpio"; + }; + + config { + pins = "gpio125"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + }; + + ts_reset_active: ts-reset-active { + mux { + pins = "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio99"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + ts_reset_suspend: ts-reset-suspend { + mux { + pins = "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio99"; + drive-strength = <2>; + bias-pull-down; + }; + }; +}; + +&uart6 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3990-bt"; + + vddio-supply = <&vreg_s4a_1p8>; + vddxo-supply = <&vreg_l7a_1p8>; + vddrf-supply = <&vreg_l17a_1p3>; + vddch0-supply = <&vreg_l25a_3p3>; + max-speed = <3200000>; + }; +}; + +&uart9 { + status = "okay"; +}; + +&ufs_mem_hc { + status = "okay"; + + reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l20a_2p95>; + vcc-max-microamp = <600000>; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vdda_ufs1_core>; + vdda-pll-supply = <&vdda_ufs1_1p2>; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + status = "okay"; + + vdd-supply = <&vreg_l1a_0p875>; + vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; + vdda-pll-supply = <&vreg_l12a_1p8>; +}; + +&usb_1_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vreg_l26a_1p2>; + vdda-pll-supply = <&vreg_l1a_0p875>; +}; + +&venus { + status = "okay"; + firmware-name = "qcom/sdm845/axolotl/venus.mbn"; +}; + +&wifi { + status = "okay"; + + vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; + vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; + vdd-3.3-ch1-supply = <&vreg_l23a_3p3>; + + qcom,snoc-host-cap-8bit-quirk; +}; -- cgit From a0d5455330ece6f50ddf9e71d530f91c302803e9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 29 Jan 2022 20:36:39 +0100 Subject: arm64: dts: exynos: adjust USB DRD clocks with dtschema in Exynos7 Use the same order of USB 3.0 DRD controller clocks as in Exynos5433. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220129193646.372481-1-krzysztof.kozlowski@canonical.com --- arch/arm64/boot/dts/exynos/exynos7.dtsi | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index 3364b09c3158..e38bb02a2152 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -684,11 +684,10 @@ reg = <0x15500000 0x100>; clocks = <&clock_fsys0 ACLK_USBDRD300>, <&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>, - <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>, <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>, + <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>, <&clock_fsys0 SCLK_USBDRD300_REFCLK>; - clock-names = "phy", "ref", "phy_pipe", - "phy_utmi", "itp"; + clock-names = "phy", "ref", "phy_utmi", "phy_pipe", "itp"; samsung,pmu-syscon = <&pmu_system_controller>; #phy-cells = <1>; }; -- cgit From 7c2b8198f4f321df03e285a931fab2a33668c88d Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 10 Jan 2022 13:46:57 +0000 Subject: arm64: dts: renesas: Add initial DTSI for RZ/V2L SoC The RZ/V2L SoC is package- and pin-compatible with RZ/G2L, the only difference being that the RZ/V2L SoC has additional DRP-AI IP (AI accelerator). Add initial DTSI for the RZ/V2L SoC with below SoC specific dtsi files for supporting single core and dual core devices: r9a07g054l1.dtsi => RZ/V2L R9A07G054L1 SoC specific parts r9a07g054l2.dtsi => RZ/V2L R9A07G054L2 SoC specific parts Both the RZ/G2L and RZ/V2L SMARC EVK SoMs are identical apart from the SoCs used, hence the common dtsi files (rzg2l-smarc*.dtsi) are shared between the RZ/G2L and RZ/V2L SMARC EVKs. Place holders are added in device nodes to avoid compilation errors for devices which have not been enabled yet on the RZ/V2L SoC. Signed-off-by: Biju Das Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220110134659.30424-11-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 491 +++++++++++++++++++++++++++ arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi | 25 ++ arch/arm64/boot/dts/renesas/r9a07g054l2.dtsi | 13 + 3 files changed, 529 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a07g054.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r9a07g054l2.dtsi (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi new file mode 100644 index 000000000000..5d39e765c291 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -0,0 +1,491 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/V2L SoC + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include +#include + +/ { + compatible = "renesas,r9a07g054"; + #address-cells = <2>; + #size-cells = <2>; + + audio_clk1: audio_clk1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by boards that provide it */ + clock-frequency = <0>; + }; + + audio_clk2: audio_clk2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by boards that provide it */ + clock-frequency = <0>; + }; + + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a55"; + reg = <0>; + device_type = "cpu"; + #cooling-cells = <2>; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A07G054_CLK_I>; + }; + + cpu1: cpu@100 { + compatible = "arm,cortex-a55"; + reg = <0x100>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A07G054_CLK_I>; + }; + + L3_CA55: cache-controller-0 { + compatible = "cache"; + cache-unified; + cache-size = <0x40000>; + }; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ssi0: ssi@10049c00 { + reg = <0 0x10049c00 0 0x400>; + #sound-dai-cells = <0>; + /* place holder */ + }; + + spi1: spi@1004b000 { + reg = <0 0x1004b000 0 0x400>; + #address-cells = <1>; + #size-cells = <0>; + /* place holder */ + }; + + scif0: serial@1004b800 { + compatible = "renesas,scif-r9a07g054", + "renesas,scif-r9a07g044"; + reg = <0 0x1004b800 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G054_SCIF0_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_SCIF0_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif1: serial@1004bc00 { + compatible = "renesas,scif-r9a07g054", + "renesas,scif-r9a07g044"; + reg = <0 0x1004bc00 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G054_SCIF1_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_SCIF1_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif2: serial@1004c000 { + compatible = "renesas,scif-r9a07g054", + "renesas,scif-r9a07g044"; + reg = <0 0x1004c000 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G054_SCIF2_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_SCIF2_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif3: serial@1004c400 { + compatible = "renesas,scif-r9a07g054", + "renesas,scif-r9a07g044"; + reg = <0 0x1004c400 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G054_SCIF3_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_SCIF3_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif4: serial@1004c800 { + compatible = "renesas,scif-r9a07g054", + "renesas,scif-r9a07g044"; + reg = <0 0x1004c800 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G054_SCIF4_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_SCIF4_RST_SYSTEM_N>; + status = "disabled"; + }; + + sci0: serial@1004d000 { + compatible = "renesas,r9a07g054-sci", "renesas,sci"; + reg = <0 0x1004d000 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD R9A07G054_SCI0_CLKP>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_SCI0_RST>; + status = "disabled"; + }; + + sci1: serial@1004d400 { + compatible = "renesas,r9a07g054-sci", "renesas,sci"; + reg = <0 0x1004d400 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD R9A07G054_SCI1_CLKP>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_SCI1_RST>; + status = "disabled"; + }; + + canfd: can@10050000 { + reg = <0 0x10050000 0 0x8000>; + /* place holder */ + }; + + i2c0: i2c@10058000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x10058000 0 0x400>; + /* place holder */ + }; + + i2c1: i2c@10058400 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x10058400 0 0x400>; + /* place holder */ + }; + + i2c3: i2c@10058c00 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x10058c00 0 0x400>; + /* place holder */ + }; + + adc: adc@10059000 { + reg = <0 0x10059000 0 0x400>; + /* place holder */ + }; + + sbc: spi@10060000 { + reg = <0 0x10060000 0 0x10000>, + <0 0x20000000 0 0x10000000>, + <0 0x10070000 0 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + /* place holder */ + }; + + cpg: clock-controller@11010000 { + compatible = "renesas,r9a07g054-cpg"; + reg = <0 0x11010000 0 0x10000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + sysc: system-controller@11020000 { + compatible = "renesas,r9a07g054-sysc"; + reg = <0 0x11020000 0 0x10000>; + interrupts = , + , + , + ; + interrupt-names = "lpm_int", "ca55stbydone_int", + "cm33stbyr_int", "ca55_deny"; + status = "disabled"; + }; + + pinctrl: pinctrl@11030000 { + compatible = "renesas,r9a07g054-pinctrl", + "renesas,r9a07g044-pinctrl"; + reg = <0 0x11030000 0 0x10000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 392>; + clocks = <&cpg CPG_MOD R9A07G054_GPIO_HCLK>; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_GPIO_RSTN>, + <&cpg R9A07G054_GPIO_PORT_RESETN>, + <&cpg R9A07G054_GPIO_SPARE_RESETN>; + }; + + dmac: dma-controller@11820000 { + compatible = "renesas,r9a07g054-dmac", + "renesas,rz-dmac"; + reg = <0 0x11820000 0 0x10000>, + <0 0x11830000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD R9A07G054_DMAC_ACLK>, + <&cpg CPG_MOD R9A07G054_DMAC_PCLK>; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_DMAC_ARESETN>, + <&cpg R9A07G054_DMAC_RST_ASYNC>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + gpu: gpu@11840000 { + reg = <0x0 0x11840000 0x0 0x10000>; + /* place holder */ + }; + + gic: interrupt-controller@11900000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x11900000 0 0x40000>, + <0x0 0x11940000 0 0x60000>; + interrupts = ; + }; + + sdhi0: mmc@11c00000 { + reg = <0x0 0x11c00000 0 0x10000>; + /* place holder */ + }; + + sdhi1: mmc@11c10000 { + reg = <0x0 0x11c10000 0 0x10000>; + /* place holder */ + }; + + eth0: ethernet@11c20000 { + compatible = "renesas,r9a07g054-gbeth", + "renesas,rzg2l-gbeth"; + reg = <0 0x11c20000 0 0x10000>; + interrupts = , + , + ; + interrupt-names = "mux", "fil", "arp_ns"; + phy-mode = "rgmii"; + clocks = <&cpg CPG_MOD R9A07G054_ETH0_CLK_AXI>, + <&cpg CPG_MOD R9A07G054_ETH0_CLK_CHI>, + <&cpg CPG_CORE R9A07G054_CLK_HP>; + clock-names = "axi", "chi", "refclk"; + resets = <&cpg R9A07G054_ETH0_RST_HW_N>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + eth1: ethernet@11c30000 { + compatible = "renesas,r9a07g054-gbeth", + "renesas,rzg2l-gbeth"; + reg = <0 0x11c30000 0 0x10000>; + interrupts = , + , + ; + interrupt-names = "mux", "fil", "arp_ns"; + phy-mode = "rgmii"; + clocks = <&cpg CPG_MOD R9A07G054_ETH1_CLK_AXI>, + <&cpg CPG_MOD R9A07G054_ETH1_CLK_CHI>, + <&cpg CPG_CORE R9A07G054_CLK_HP>; + clock-names = "axi", "chi", "refclk"; + resets = <&cpg R9A07G054_ETH1_RST_HW_N>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + phyrst: usbphy-ctrl@11c40000 { + reg = <0 0x11c40000 0 0x10000>; + /* place holder */ + }; + + ohci0: usb@11c50000 { + reg = <0 0x11c50000 0 0x100>; + /* place holder */ + }; + + ohci1: usb@11c70000 { + reg = <0 0x11c70000 0 0x100>; + /* place holder */ + }; + + ehci0: usb@11c50100 { + reg = <0 0x11c50100 0 0x100>; + /* place holder */ + }; + + ehci1: usb@11c70100 { + reg = <0 0x11c70100 0 0x100>; + /* place holder */ + }; + + usb2_phy0: usb-phy@11c50200 { + reg = <0 0x11c50200 0 0x700>; + /* place holder */ + }; + + usb2_phy1: usb-phy@11c70200 { + reg = <0 0x11c70200 0 0x700>; + /* place holder */ + }; + + hsusb: usb@11c60000 { + reg = <0 0x11c60000 0 0x10000>; + /* place holder */ + }; + + wdt0: watchdog@12800800 { + reg = <0 0x12800800 0 0x400>; + /* place holder */ + }; + + wdt1: watchdog@12800c00 { + reg = <0 0x12800C00 0 0x400>; + /* place holder */ + }; + + wdt2: watchdog@12800400 { + reg = <0 0x12800400 0 0x400>; + /* place holder */ + }; + + ostm0: timer@12801000 { + reg = <0x0 0x12801000 0x0 0x400>; + /* place holder */ + }; + + ostm1: timer@12801400 { + reg = <0x0 0x12801400 0x0 0x400>; + /* place holder */ + }; + + ostm2: timer@12801800 { + reg = <0x0 0x12801800 0x0 0x400>; + /* place holder */ + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi new file mode 100644 index 000000000000..c448cc6634c1 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/V2L R9A07G054L1 SoC specific parts + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a07g054.dtsi" + +/ { + compatible = "renesas,r9a07g054l1", "renesas,r9a07g054"; + + cpus { + /delete-node/ cpu-map; + /delete-node/ cpu@100; + }; + + timer { + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l2.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054l2.dtsi new file mode 100644 index 000000000000..4d5914bc95d3 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g054l2.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/V2L R9A07G054L2 SoC specific parts + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a07g054.dtsi" + +/ { + compatible = "renesas,r9a07g054l2", "renesas,r9a07g054"; +}; -- cgit From f91c4c74796acca0a5a3bde747948a844eb2c30b Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 10 Jan 2022 13:46:58 +0000 Subject: arm64: dts: renesas: Add initial device tree for RZ/V2L SMARC EVK Add basic support for the RZ/V2L SMARC EVK (based on R9A07G054L2): - memory - External input clock - CPG - Pin controller - SCIF - GbEthernet - Audio Clock It shares the same carrier board with RZ/G2L with the same pin mapping. Delete the gpio-hog nodes from pinctrl as they will be added later when the functionality has been tested. Signed-off-by: Biju Das Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220110134659.30424-12-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 2 ++ arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts | 25 ++++++++++++++++++++++ .../boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi | 2 +- arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi | 2 +- arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 2 +- 5 files changed, 30 insertions(+), 3 deletions(-) create mode 100644 arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index f1ab09486bab..d000f6b131dc 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -77,3 +77,5 @@ dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs.dtb dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb + +dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc.dtb diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts new file mode 100644 index 000000000000..39ef55bfe0c3 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2L SMARC EVK board + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a07g054l2.dtsi" +#include "rzg2l-smarc-som.dtsi" +#include "rzg2l-smarc-pinfunction.dtsi" +#include "rzg2l-smarc.dtsi" + +/ { + model = "Renesas SMARC EVK based on r9a07g054l2"; + compatible = "renesas,smarc-evk", "renesas,r9a07g054l2", "renesas,r9a07g054"; +}; + +&pinctrl { + /delete-node/ can0-stb; + /delete-node/ can1-stb; + /delete-node/ gpio-sd0-pwr-en-hog; + /delete-node/ sd0-dev-sel-hog; + /delete-node/ sd1-pwr-en-hog; +}; diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi index 71d83e447670..2ef217445f72 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* - * Device Tree Source for the RZ/G2L SMARC pincontrol parts + * Device Tree Source for the RZ/{G2L,V2L} SMARC pincontrol parts * * Copyright (C) 2021 Renesas Electronics Corp. */ diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi index 9112e79079a1..aeacd22e9eb0 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* - * Device Tree Source for the RZ/G2L SMARC SOM common parts + * Device Tree Source for the RZ/{G2L,V2L} SMARC SOM common parts * * Copyright (C) 2021 Renesas Electronics Corp. */ diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index 46abb29718cc..78034f36156d 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* - * Device Tree Source for the RZ/G2L SMARC EVK common parts + * Device Tree Source for the RZ/{G2L,V2L} SMARC EVK common parts * * Copyright (C) 2021 Renesas Electronics Corp. */ -- cgit From 7ca0ce6478c6803c9f86e7366f5634de9c096207 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 17 Jan 2022 07:51:29 +0000 Subject: arm64: dts: renesas: rzg2lc-smarc-som: Enable eMMC on SMARC platform RZ/G2LC SoM has both 64 GB eMMC and microSD connected to SDHI0. Both these interfaces are mutually exclusive and the SD0 device selection is based on the XOR between GPIO_SD0_DEV_SEL and SW1[2] switch position. This patch sets GPIO_SD0_DEV_SEL to high in DT. Use the below switch setting logic for device selection between eMMC and microSD slot connected to SDHI0. Set SW1[2] to position OFF for selecting eMMC Set SW1[2] to position ON for selecting microSD This patch enables eMMC on RZ/G2LC SMARC platform by default. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220117075130.6198-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi | 142 ++++++++++++++++++++++ 1 file changed, 142 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi index e1d7a3a689c6..6ebda3724f2c 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi @@ -8,6 +8,16 @@ #include #include +/* SW1[2] should be at OFF position to enable 64 GB eMMC */ +#define EMMC 1 + +/* + * To enable uSD card on CN3, + * SW1[2] should be at ON position. + * Disable eMMC by setting "#define EMMC 0" above. + */ +#define SDHI (!EMMC) + / { aliases { ethernet0 = ð0; @@ -22,6 +32,36 @@ /* first 128MB is reserved for secure area. */ reg = <0x0 0x48000000 0x0 0x38000000>; }; + + reg_1p8v: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + states = <3300000 1>, <1800000 0>; + regulator-boot-on; + gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>; + regulator-always-on; + }; }; ð0 { @@ -72,5 +112,107 @@ , /* ET0_RXD2 */ ; /* ET0_RXD3 */ }; + + gpio-sd0-pwr-en-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "gpio_sd0_pwr_en"; + }; + + /* + * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2] + * The below switch logic can be used to select the device between + * eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT. + * SW1[2] should be at OFF position to enable 64 GB eMMC + * SW1[2] should be at position ON to enable uSD card CN3 + */ + gpio-sd0-dev-sel-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "gpio_sd0_dev_sel"; + }; + + sdhi0_emmc_pins: sd0emmc { + sd0_emmc_data { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", + "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7"; + power-source = <1800>; + }; + + sd0_emmc_ctrl { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <1800>; + }; + + sd0_emmc_rst { + pins = "SD0_RST#"; + power-source = <1800>; + }; + }; + + sdhi0_pins: sd0 { + sd0_data { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; + power-source = <3300>; + }; + + sd0_ctrl { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <3300>; + }; + + sd0_mux { + pinmux = ; /* SD0_CD */ + }; + }; + + sdhi0_pins_uhs: sd0_uhs { + sd0_data_uhs { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; + power-source = <1800>; + }; + + sd0_ctrl_uhs { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <1800>; + }; + + sd0_mux_uhs { + pinmux = ; /* SD0_CD */ + }; + }; +}; + +#if SDHI +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vccq_sdhi0>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; +#endif + +#if EMMC +&sdhi0 { + pinctrl-0 = <&sdhi0_emmc_pins>; + pinctrl-1 = <&sdhi0_emmc_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + fixed-emmc-driver-type = <1>; + status = "okay"; }; +#endif -- cgit From 81a27b1f69022174567e8237d3de2534821671ba Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 17 Jan 2022 07:51:30 +0000 Subject: arm64: dts: renesas: rzg2lc-smarc: Enable microSD on SMARC platform Enable the microSD card slot connected to SDHI1 on the RZ/G2LC SMARC platform by removing the sdhi1 override which disabled it, and by adding the necessary pinmux required for SDHI1. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220117075130.6198-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts | 8 ----- .../boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 39 ++++++++++++++++++++++ 2 files changed, 39 insertions(+), 8 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts index 728a2275ea8d..8d671111d973 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts @@ -81,14 +81,6 @@ status = "disabled"; }; -&sdhi1 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-1; - /delete-property/ pinctrl-names; - /delete-property/ vmmc-supply; - status = "disabled"; -}; - &spi1 { /delete-property/ pinctrl-0; /delete-property/ pinctrl-names; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi index 5333a1f9a0e7..1032f6563515 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi @@ -17,6 +17,45 @@ ; /* RxD */ }; + sd1-pwr-en-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "sd1_pwr_en"; + }; + + sdhi1_pins: sd1 { + sd1_data { + pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; + power-source = <3300>; + }; + + sd1_ctrl { + pins = "SD1_CLK", "SD1_CMD"; + power-source = <3300>; + }; + + sd1_mux { + pinmux = ; /* SD1_CD */ + }; + }; + + sdhi1_pins_uhs: sd1_uhs { + sd1_data_uhs { + pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; + power-source = <1800>; + }; + + sd1_ctrl_uhs { + pins = "SD1_CLK", "SD1_CMD"; + power-source = <1800>; + }; + + sd1_mux_uhs { + pinmux = ; /* SD1_CD */ + }; + }; + sound_clk_pins: sound_clk { pins = "AUDIO_CLK1", "AUDIO_CLK2"; input-enable; -- cgit From 73419e4d2fd1b838fcb1df6a978d67b3ae1c5c01 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Tue, 1 Feb 2022 08:07:23 -0600 Subject: arm64: dts: qcom: add IPA qcom,qmp property At least three platforms require the "qcom,qmp" property to be specified, so the IPA driver can request register retention across power collapse. Update DTS files accordingly. Signed-off-by: Alex Elder Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220201140723.467431-1-elder@linaro.org --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 ++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 ++ arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 ++ 3 files changed, 6 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 2151cd8c8c7a..e1c46b80f14a 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1459,6 +1459,8 @@ "imem", "config"; + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&ipa_smp2p_out 0>, <&ipa_smp2p_out 1>; qcom,smem-state-names = "ipa-clock-enabled-valid", diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index d4009cc0bb78..a7c9b167840e 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -1715,6 +1715,8 @@ interconnect-names = "memory", "config"; + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&ipa_smp2p_out 0>, <&ipa_smp2p_out 1>; qcom,smem-state-names = "ipa-clock-enabled-valid", diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 8166b5f5bb9e..4fb835e8f54d 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1425,6 +1425,8 @@ interconnect-names = "memory", "config"; + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&ipa_smp2p_out 0>, <&ipa_smp2p_out 1>; qcom,smem-state-names = "ipa-clock-enabled-valid", -- cgit From 6dd8457dc20693e2ba9054c171499b22664fd4e7 Mon Sep 17 00:00:00 2001 From: Christian Gmeiner Date: Tue, 11 Jan 2022 14:45:48 +0100 Subject: arm64: dts: ti: k3-am64-main: Add RTI watchdog nodes Add the needed bus mappings for the two main RTI memory ranges and the required device tree nodes in the main domain. Signed-off-by: Christian Gmeiner Signed-off-by: Nishanth Menon Acked-By: Hari Nagalla Link: https://lore.kernel.org/r/20220111134552.800704-1-christian.gmeiner@gmail.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 18 ++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am64.dtsi | 2 ++ 2 files changed, 20 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 012011dc619a..0c9f3bce8418 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -982,6 +982,24 @@ clock-names = "fck"; }; + main_rti0: watchdog@e000000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0xe000000 0x00 0x100>; + clocks = <&k3_clks 125 0>; + power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 125 0>; + assigned-clock-parents = <&k3_clks 125 2>; + }; + + main_rti1: watchdog@e010000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0xe010000 0x00 0x100>; + clocks = <&k3_clks 126 0>; + power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 126 0>; + assigned-clock-parents = <&k3_clks 126 2>; + }; + icssg0: icssg@30000000 { compatible = "ti,am642-icssg"; reg = <0x00 0x30000000 0x00 0x80000>; diff --git a/arch/arm64/boot/dts/ti/k3-am64.dtsi b/arch/arm64/boot/dts/ti/k3-am64.dtsi index 120974726be8..84bd07cd1824 100644 --- a/arch/arm64/boot/dts/ti/k3-am64.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64.dtsi @@ -71,6 +71,8 @@ <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */ <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */ + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x00000100>, /* Main RTI0 */ + <0x00 0x0e010000 0x00 0x0e010000 0x00 0x00000100>, /* Main RTI1 */ <0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, /* Second peripheral window */ <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ <0x00 0x30000000 0x00 0x30000000 0x00 0x000bc100>, /* ICSSG0/1 */ -- cgit From 1172729576fbbe2936f3f9cd03ad9317c6a04eab Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Thu, 27 Jan 2022 18:55:12 -0800 Subject: arm64: dts: qcom: sm8450: Add remoteproc enablers and instances The Qualcomm SM8450 carries the familiar set of audio, compute, sensor and modem remoteprocs. Add these and their dependencies. Signed-off-by: Bjorn Andersson Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20220128025513.97188-13-bjorn.andersson@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 297 +++++++++++++++++++++++++++++++++++ 1 file changed, 297 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index dbc5eea2ebba..a2ed8ed9929d 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include #include @@ -460,6 +461,15 @@ no-map; }; + rmtfs_mem: memory@9fd00000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0x9fd00000 0x0 0x280000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <15>; + }; + global_sync_mem: memory@a6f00000 { reg = <0x0 0xa6f00000 0x0 0x100000>; no-map; @@ -540,6 +550,113 @@ }; }; + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + smp2p_cdsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_cdsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + smp2p_modem_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_modem_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + ipa_smp2p_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + ipa_smp2p_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-slpi { + compatible = "qcom,smp2p"; + qcom,smem = <481>, <430>; + interrupts-extended = <&ipcc IPCC_CLIENT_SLPI + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_SLPI + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <3>; + + smp2p_slpi_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_slpi_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc@0 { #address-cells = <2>; #size-cells = <2>; @@ -672,6 +789,167 @@ }; }; + remoteproc_slpi: remoteproc@2400000 { + compatible = "qcom,sm8450-slpi-pas"; + reg = <0 0x02400000 0 0x4000>; + + interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SM8450_LCX>, + <&rpmhpd SM8450_LMX>; + power-domain-names = "lcx", "lmx"; + + memory-region = <&slpi_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_slpi_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_SLPI + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_SLPI + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "slpi"; + qcom,remote-pid = <3>; + }; + }; + + remoteproc_adsp: remoteproc@30000000 { + compatible = "qcom,sm8450-adsp-pas"; + reg = <0 0x030000000 0 0x100>; + + interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SM8450_LCX>, + <&rpmhpd SM8450_LMX>; + power-domain-names = "lcx", "lmx"; + + memory-region = <&adsp_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + remoteproc_adsp_glink: glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "lpass"; + qcom,remote-pid = <2>; + }; + }; + + remoteproc_cdsp: remoteproc@32300000 { + compatible = "qcom,sm8450-cdsp-pas"; + reg = <0 0x032300000 0 0x1400000>; + + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SM8450_CX>, + <&rpmhpd SM8450_MXC>; + power-domain-names = "cx", "mxc"; + + memory-region = <&cdsp_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_cdsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "cdsp"; + qcom,remote-pid = <5>; + }; + }; + + remoteproc_mpss: remoteproc@4080000 { + compatible = "qcom,sm8450-mpss-pas"; + reg = <0x0 0x04080000 0x0 0x4040>; + + interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", + "stop-ack", "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd 0>, + <&rpmhpd 12>; + power-domain-names = "cx", "mss"; + + memory-region = <&mpss_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_modem_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + interrupts = ; + label = "modem"; + qcom,remote-pid = <1>; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8450-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; @@ -682,6 +960,25 @@ interrupt-controller; }; + aoss_qmp: power-controller@c300000 { + compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp"; + reg = <0 0x0c300000 0 0x400>; + interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells = <0>; + }; + + ipcc: mailbox@ed18000 { + compatible = "qcom,sm8450-ipcc", "qcom,ipcc"; + reg = <0 0x0ed18000 0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + tlmm: pinctrl@f100000 { compatible = "qcom,sm8450-tlmm"; reg = <0 0x0f100000 0 0x300000>; -- cgit From 72c370dfbd58b1fe3a7faecabafd6d91213d9ecc Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Thu, 27 Jan 2022 18:55:13 -0800 Subject: arm64: dts: qcom: sm8450-qrd: Enable remoteproc instances Enable the audio, compute, sensor and modem remoteproc and specify firmware path for these on the Qualcomm SM8450 QRD. Signed-off-by: Bjorn Andersson Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20220128025513.97188-14-bjorn.andersson@linaro.org --- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index b68ab247e6ae..9526632d4029 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -346,6 +346,26 @@ status = "okay"; }; +&remoteproc_adsp { + status = "okay"; + firmware-name = "qcom/sm8450/adsp.mbn"; +}; + +&remoteproc_cdsp { + status = "okay"; + firmware-name = "qcom/sm8450/cdsp.mbn"; +}; + +&remoteproc_mpss { + status = "okay"; + firmware-name = "qcom/sm8450/modem.mbn"; +}; + +&remoteproc_slpi { + status = "okay"; + firmware-name = "qcom/sm8450/slpi.mbn"; +}; + &tlmm { gpio-reserved-ranges = <28 4>, <36 4>; }; -- cgit From 171bac46700fcdb2310209dffb382533fe54522a Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Wed, 2 Feb 2022 13:23:35 -0800 Subject: arm64: dts: qcom: sc7180-trogdor: Add "-regulator" suffix to pp3300_hub All of the other fixed regulators have the "-regulator" suffix. Add it to pp3300_hub to match. Signed-off-by: Douglas Anderson Reviewed-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220202132301.v3.1.I7b284531f1c992932f7eef8abaf7cc5548064f33@changeid --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 7d8bf66e8ffe..78296ed6fd29 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -284,7 +284,7 @@ vin-supply = <&pp3300_a>; }; - pp3300_hub: pp3300-hub { + pp3300_hub: pp3300-hub-regulator { compatible = "regulator-fixed"; regulator-name = "pp3300_hub"; -- cgit From 7a86ac04056569bf5ec663fbb02d79c5e304545a Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Wed, 2 Feb 2022 13:23:36 -0800 Subject: arm64: dts: qcom: sc7280-herobrine: Consistently add "-regulator" suffix Some of the fixed regulators were missing the "-regulator" suffix. Add it to be consistent within the file and consistent with the fixed regulators in sc7180-trogdor. Signed-off-by: Douglas Anderson Reviewed-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220202132301.v3.2.I627e60c5488d54a45fd1482ca19f0f6e45192db2@changeid --- arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts index ad4fe288b53c..f159b5a6d7ef 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts @@ -177,7 +177,7 @@ vin-supply = <&pp3300_z1>; }; - pp2850_uf_cam: pp2850-uf-cam { + pp2850_uf_cam: pp2850-uf-cam-regulator { compatible = "regulator-fixed"; regulator-name = "pp2850_uf_cam"; @@ -192,7 +192,7 @@ vin-supply = <&pp3300_cam>; }; - pp2850_vcm_wf_cam: pp2850-vcm-wf-cam { + pp2850_vcm_wf_cam: pp2850-vcm-wf-cam-regulator { compatible = "regulator-fixed"; regulator-name = "pp2850_vcm_wf_cam"; @@ -207,7 +207,7 @@ vin-supply = <&pp3300_cam>; }; - pp2850_wf_cam: pp2850-wf-cam { + pp2850_wf_cam: pp2850-wf-cam-regulator { compatible = "regulator-fixed"; regulator-name = "pp2850_wf_cam"; @@ -251,7 +251,7 @@ status = "disabled"; }; - pp1800_uf_cam: pp1800-uf-cam { + pp1800_uf_cam: pp1800-uf-cam-regulator { compatible = "regulator-fixed"; regulator-name = "pp1800_uf_cam"; @@ -271,7 +271,7 @@ vin-supply = <&pp1800_l19b>; }; - pp1800_wf_cam: pp1800-wf-cam { + pp1800_wf_cam: pp1800-wf-cam-regulator { compatible = "regulator-fixed"; regulator-name = "pp1800_wf_cam"; @@ -291,7 +291,7 @@ vin-supply = <&pp1800_l19b>; }; - pp1200_wf_cam: pp1200-wf-cam { + pp1200_wf_cam: pp1200-wf-cam-regulator { compatible = "regulator-fixed"; regulator-name = "pp1200_wf_cam"; -- cgit From b1969bc522187dc6f436301eb71051b24135b607 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Wed, 2 Feb 2022 13:23:37 -0800 Subject: arm64: dts: qcom: sc7280: Properly sort sdc pinctrl lines The sdc1 / sdc2 pinctrl lines were randomly stuffed in the middle of the qup pinctrl lines. Sort them properly. This is a no-op change. Just code movement. Signed-off-by: Douglas Anderson Reviewed-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220202132301.v3.3.I6ae594129a8ad3d18af9f5ebffd895b4f6353a0a@changeid --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 154 +++++++++++++++++------------------ 1 file changed, 77 insertions(+), 77 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index a7c9b167840e..4a0e574802a7 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3785,83 +3785,6 @@ function = "qup07"; }; - sdc1_on: sdc1-on { - clk { - pins = "sdc1_clk"; - }; - - cmd { - pins = "sdc1_cmd"; - }; - - data { - pins = "sdc1_data"; - }; - - rclk { - pins = "sdc1_rclk"; - }; - }; - - sdc1_off: sdc1-off { - clk { - pins = "sdc1_clk"; - drive-strength = <2>; - bias-bus-hold; - }; - - cmd { - pins = "sdc1_cmd"; - drive-strength = <2>; - bias-bus-hold; - }; - - data { - pins = "sdc1_data"; - drive-strength = <2>; - bias-bus-hold; - }; - - rclk { - pins = "sdc1_rclk"; - bias-bus-hold; - }; - }; - - sdc2_on: sdc2-on { - clk { - pins = "sdc2_clk"; - }; - - cmd { - pins = "sdc2_cmd"; - }; - - data { - pins = "sdc2_data"; - }; - }; - - sdc2_off: sdc2-off { - clk { - pins = "sdc2_clk"; - drive-strength = <2>; - bias-bus-hold; - }; - - cmd { - pins ="sdc2_cmd"; - drive-strength = <2>; - bias-bus-hold; - }; - - data { - pins ="sdc2_data"; - drive-strength = <2>; - bias-bus-hold; - }; - }; - qup_uart8_cts: qup-uart8-cts { pins = "gpio32"; function = "qup10"; @@ -4021,6 +3944,83 @@ pins = "gpio63"; function = "qup17"; }; + + sdc1_on: sdc1-on { + clk { + pins = "sdc1_clk"; + }; + + cmd { + pins = "sdc1_cmd"; + }; + + data { + pins = "sdc1_data"; + }; + + rclk { + pins = "sdc1_rclk"; + }; + }; + + sdc1_off: sdc1-off { + clk { + pins = "sdc1_clk"; + drive-strength = <2>; + bias-bus-hold; + }; + + cmd { + pins = "sdc1_cmd"; + drive-strength = <2>; + bias-bus-hold; + }; + + data { + pins = "sdc1_data"; + drive-strength = <2>; + bias-bus-hold; + }; + + rclk { + pins = "sdc1_rclk"; + bias-bus-hold; + }; + }; + + sdc2_on: sdc2-on { + clk { + pins = "sdc2_clk"; + }; + + cmd { + pins = "sdc2_cmd"; + }; + + data { + pins = "sdc2_data"; + }; + }; + + sdc2_off: sdc2-off { + clk { + pins = "sdc2_clk"; + drive-strength = <2>; + bias-bus-hold; + }; + + cmd { + pins ="sdc2_cmd"; + drive-strength = <2>; + bias-bus-hold; + }; + + data { + pins ="sdc2_data"; + drive-strength = <2>; + bias-bus-hold; + }; + }; }; imem@146a5000 { -- cgit From f9800dde34e678d7ed1de9e95b4b65a257fd0f93 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Wed, 2 Feb 2022 13:23:38 -0800 Subject: arm64: dts: qcom: sc7280: Clean up sdc1 / sdc2 pinctrl This patch makes a few improvements to the way that sdc1 / sdc2 pinctrl is specified on sc7280: 1. There's no reason to "group" the sdc pins into one overarching node and there's a downside: we have to replicate the hierarchy in the board device tree files. Let's clean this up. 2. There's really not a lot of reason not to list the "pinctrl" for sdc1 (eMMC) in the SoC dtsi file. These aren't GPIO pins and everyone's going to specify the same pins. 3. Even though it's likely that boards will need to override pinctrl for sdc2 (SD card) to add the card detect GPIO, we can be symmetric and add it to the SoC dsti file. 4. Let's get rid of the word "on" from the normal config and add a "sleep" suffix to the sleep config. This looks cleaner to me. This is intended to be a no-op change but it could plausibly change behavior depending on how the pinctrl code parses things. One thing to note is that "SD card detect" is explicitly listed now as keeping its pull enabled in sleep since we still want to detect card insertions even if the controller is suspended (because no card is inserted). The pinctrl framework likely did this anyway, but it's nice to see it explicit. Signed-off-by: Douglas Anderson Reviewed-by: Stephen Boyd Reviewed-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220202132301.v3.4.I79baad7f52351aafb470f8b21a9fa79d7031ad6a@changeid --- .../dts/qcom/sc7280-herobrine-herobrine-r0.dts | 73 ++++++------- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 91 ++++++++-------- arch/arm64/boot/dts/qcom/sc7280.dtsi | 117 ++++++++++----------- 3 files changed, 133 insertions(+), 148 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts index f159b5a6d7ef..918352c097bc 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts @@ -676,9 +676,6 @@ ap_ts_pen: &i2c13 { &sdhc_1 { status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_on>; - pinctrl-1 = <&sdc1_off>; vmmc-supply = <&pp2950_l7b>; vqmmc-supply = <&pp1800_l19b>; }; @@ -686,9 +683,8 @@ ap_ts_pen: &i2c13 { &sdhc_2 { status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_on>; - pinctrl-1 = <&sdc2_off>; + pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>, <&sd_cd>; + pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>, <&sd_cd>; vmmc-supply = <&pp2950_l9c>; vqmmc-supply = <&ppvar_l6c>; @@ -883,47 +879,38 @@ ap_ec_spi: &spi8 { bias-pull-up; }; -&sdc1_on { - clk { - bias-disable; - drive-strength = <16>; - }; - - cmd { - bias-pull-up; - drive-strength = <10>; - }; +&sdc1_clk { + bias-disable; + drive-strength = <16>; +}; - data { - bias-pull-up; - drive-strength = <10>; - }; +&sdc1_cmd { + bias-pull-up; + drive-strength = <10>; +}; - rclk { - bias-pull-down; - }; +&sdc1_data { + bias-pull-up; + drive-strength = <10>; }; -&sdc2_on { - clk { - bias-disable; - drive-strength = <16>; - }; +&sdc1_rclk { + bias-pull-down; +}; - cmd { - bias-pull-up; - drive-strength = <10>; - }; +&sdc2_clk { + bias-disable; + drive-strength = <16>; +}; - data { - bias-pull-up; - drive-strength = <10>; - }; +&sdc2_cmd { + bias-pull-up; + drive-strength = <10>; +}; - sd-cd { - pins = "gpio91"; - bias-pull-up; - }; +&sdc2_data { + bias-pull-up; + drive-strength = <10>; }; /* PINCTRL - board-specific pinctrl */ @@ -1311,6 +1298,12 @@ ap_ec_spi: &spi8 { bias-pull-up; }; + sd_cd: sd-cd { + pins = "gpio91"; + function = "gpio"; + bias-pull-up; + }; + tp_int_odl: tp-int-odl { pins = "gpio102"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 78da9ac983db..7a987bc9b758 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -278,10 +278,6 @@ &sdhc_1 { status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_on>; - pinctrl-1 = <&sdc1_off>; - non-removable; no-sd; no-sdio; @@ -293,9 +289,8 @@ &sdhc_2 { status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_on>; - pinctrl-1 = <&sdc2_off>; + pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>, <&sd_cd>; + pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>, <&sd_cd>; vmmc-supply = <&vreg_l9c_2p9>; vqmmc-supply = <&vreg_l6c_2p9>; @@ -424,6 +419,40 @@ bias-pull-up; }; +&sdc1_clk { + bias-disable; + drive-strength = <16>; +}; + +&sdc1_cmd { + bias-pull-up; + drive-strength = <10>; +}; + +&sdc1_data { + bias-pull-up; + drive-strength = <10>; +}; + +&sdc1_rclk { + bias-pull-down; +}; + +&sdc2_clk { + bias-disable; + drive-strength = <16>; +}; + +&sdc2_cmd { + bias-pull-up; + drive-strength = <10>; +}; + +&sdc2_data { + bias-pull-up; + drive-strength = <10>; +}; + &tlmm { bt_en: bt-en { pins = "gpio85"; @@ -496,53 +525,17 @@ bias-pull-up; }; - sw_ctrl: sw-ctrl { - pins = "gpio86"; + sd_cd: sd-cd { + pins = "gpio91"; function = "gpio"; - input-enable; - bias-pull-down; - }; -}; - -&sdc1_on { - clk { - bias-disable; - drive-strength = <16>; - }; - - cmd { bias-pull-up; - drive-strength = <10>; }; - data { - bias-pull-up; - drive-strength = <10>; - }; - - rclk { + sw_ctrl: sw-ctrl { + pins = "gpio86"; + function = "gpio"; + input-enable; bias-pull-down; }; }; -&sdc2_on { - clk { - bias-disable; - drive-strength = <16>; - }; - - cmd { - bias-pull-up; - drive-strength = <10>; - }; - - data { - bias-pull-up; - drive-strength = <10>; - }; - - sd-cd { - pins = "gpio91"; - bias-pull-up; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 4a0e574802a7..3f07ebc49b62 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -616,6 +616,9 @@ sdhc_1: sdhci@7c4000 { compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; + pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; status = "disabled"; reg = <0 0x007c4000 0 0x1000>, @@ -2427,6 +2430,9 @@ sdhc_2: sdhci@8804000 { compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; + pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; status = "disabled"; reg = <0 0x08804000 0 0x1000>; @@ -3945,81 +3951,74 @@ function = "qup17"; }; - sdc1_on: sdc1-on { - clk { - pins = "sdc1_clk"; - }; + sdc1_clk: sdc1-clk { + pins = "sdc1_clk"; + }; - cmd { - pins = "sdc1_cmd"; - }; + sdc1_cmd: sdc1-cmd { + pins = "sdc1_cmd"; + }; - data { - pins = "sdc1_data"; - }; + sdc1_data: sdc1-data { + pins = "sdc1_data"; + }; - rclk { - pins = "sdc1_rclk"; - }; + sdc1_rclk: sdc1-rclk { + pins = "sdc1_rclk"; }; - sdc1_off: sdc1-off { - clk { - pins = "sdc1_clk"; - drive-strength = <2>; - bias-bus-hold; - }; + sdc1_clk_sleep: sdc1-clk-sleep { + pins = "sdc1_clk"; + drive-strength = <2>; + bias-bus-hold; + }; - cmd { - pins = "sdc1_cmd"; - drive-strength = <2>; - bias-bus-hold; - }; + sdc1_cmd_sleep: sdc1-cmd-sleep { + pins = "sdc1_cmd"; + drive-strength = <2>; + bias-bus-hold; + }; - data { - pins = "sdc1_data"; - drive-strength = <2>; - bias-bus-hold; - }; + sdc1_data_sleep: sdc1-data-sleep { + pins = "sdc1_data"; + drive-strength = <2>; + bias-bus-hold; + }; - rclk { - pins = "sdc1_rclk"; - bias-bus-hold; - }; + sdc1_rclk_sleep: sdc1-rclk-sleep { + pins = "sdc1_rclk"; + drive-strength = <2>; + bias-bus-hold; }; - sdc2_on: sdc2-on { - clk { - pins = "sdc2_clk"; - }; + sdc2_clk: sdc2-clk { + pins = "sdc2_clk"; + }; - cmd { - pins = "sdc2_cmd"; - }; + sdc2_cmd: sdc2-cmd { + pins = "sdc2_cmd"; + }; - data { - pins = "sdc2_data"; - }; + sdc2_data: sdc2-data { + pins = "sdc2_data"; }; - sdc2_off: sdc2-off { - clk { - pins = "sdc2_clk"; - drive-strength = <2>; - bias-bus-hold; - }; + sdc2_clk_sleep: sdc2-clk-sleep { + pins = "sdc2_clk"; + drive-strength = <2>; + bias-bus-hold; + }; - cmd { - pins ="sdc2_cmd"; - drive-strength = <2>; - bias-bus-hold; - }; + sdc2_cmd_sleep: sdc2-cmd-sleep { + pins = "sdc2_cmd"; + drive-strength = <2>; + bias-bus-hold; + }; - data { - pins ="sdc2_data"; - drive-strength = <2>; - bias-bus-hold; - }; + sdc2_data_sleep: sdc2-data-sleep { + pins = "sdc2_data"; + drive-strength = <2>; + bias-bus-hold; }; }; -- cgit From 8fdedd6c64643884dc6bbf6d9a7aabda1713354f Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Wed, 2 Feb 2022 13:23:39 -0800 Subject: arm64: dts: qcom: sc7280-idp: No need for "input-enable" on sw_ctrl Specifying "input-enable" on a MSM GPIO is a no-op for the most part. The only thing it really does is to explicitly force the output of a GPIO to be disabled right at the point of a pinctrl transition. We don't need to do this and we don't typically specify "input-enable" unless there's a good reason to. Remove it. Signed-off-by: Douglas Anderson Reviewed-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220202132301.v3.5.Ibaf8a803802beb089cc6266b37e6156cff3ddaec@changeid --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 7a987bc9b758..23e656e51904 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -534,7 +534,6 @@ sw_ctrl: sw-ctrl { pins = "gpio86"; function = "gpio"; - input-enable; bias-pull-down; }; }; -- cgit From bbef2a9ca08749c89925d2bb49f4ce1c945acc90 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Wed, 2 Feb 2022 13:23:40 -0800 Subject: arm64: dts: qcom: sc7280: Fix sort order of dp_hot_plug_det / pcie1_clkreq_n The two nodes were mis-sorted. Reorder. This is a no-op change. Signed-off-by: Douglas Anderson Reviewed-by: Stephen Boyd Reviewed-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220202132301.v3.6.I874c6f2a62b7922a33e10d390a8983219a76250b@changeid --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 3f07ebc49b62..19d990b06e8e 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3273,6 +3273,12 @@ gpio-ranges = <&tlmm 0 0 175>; wakeup-parent = <&pdc>; + dp_hot_plug_det: dp-hot-plug-det { + pins = "gpio47"; + function = "dp_hot"; + bias-disable; + }; + pcie1_clkreq_n: pcie1-clkreq-n { pins = "gpio79"; function = "pcie1_clkreqn"; @@ -3280,12 +3286,6 @@ bias-pull-up; }; - dp_hot_plug_det: dp-hot-plug-det { - pins = "gpio47"; - function = "dp_hot"; - bias-disable; - }; - qspi_clk: qspi-clk { pins = "gpio14"; function = "qspi_clk"; -- cgit From 118cd3b8ec0db02eb7306c30c1551ef9af885689 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Wed, 2 Feb 2022 13:23:41 -0800 Subject: arm64: dts: qcom: sc7280: Add edp_out port and HPD lines Like dp_out, we should have defined edp_out in sc7280.dtsi so we don't need to do this in the board files. Like dp_hot_plug_det, we should define edp_hot_plug_det in sc7280.dtsi. We should set the default pinctrl for edp_hot_plug_det in sc7280.dtsi. NOTE: this is _unlike_ the dp_hot_plug_det. It is reasonable that in some boards the dedicated DP Hot Plug Detect will not be hooked up in favor of Type C mechanisms. This is unlike eDP where the Hot Plug Detect line (which functions as "panel ready" in eDP) is highly likely to be used by boards. Signed-off-by: Douglas Anderson Reviewed-by: Stephen Boyd Reviewed-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220202132301.v3.7.Ic84bb69c45be2fccf50e3bd17b845fe20eec624c@changeid --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 19d990b06e8e..269cf722d20f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3012,6 +3012,8 @@ mdss_edp: edp@aea0000 { compatible = "qcom,sc7280-edp"; + pinctrl-names = "default"; + pinctrl-0 = <&edp_hot_plug_det>; reg = <0 0xaea0000 0 0x200>, <0 0xaea0200 0 0x200>, @@ -3054,12 +3056,18 @@ ports { #address-cells = <1>; #size-cells = <0>; + port@0 { reg = <0>; edp_in: endpoint { remote-endpoint = <&dpu_intf5_out>; }; }; + + port@1 { + reg = <1>; + edp_out: endpoint { }; + }; }; edp_opp_table: opp-table { @@ -3279,6 +3287,11 @@ bias-disable; }; + edp_hot_plug_det: edp-hot-plug-det { + pins = "gpio60"; + function = "edp_hot"; + }; + pcie1_clkreq_n: pcie1-clkreq-n { pins = "gpio79"; function = "pcie1_clkreqn"; -- cgit From 376e9183c1d1dde6972257a823cf484cc5124b7b Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Wed, 2 Feb 2022 13:23:42 -0800 Subject: arm64: dts: qcom: sc7280: Move pcie1_clkreq pull / drive str to boards Pullups and drive strength don't belong in the SoC dtsi file. Move to the board file. Signed-off-by: Douglas Anderson Reviewed-by: Stephen Boyd Reviewed-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220202132301.v3.8.Iffff0c12440a047212a164601e637b03b9d2fc78@changeid --- arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts | 5 +++++ arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 5 +++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 -- 3 files changed, 10 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts index 918352c097bc..82c3c8f0342b 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts @@ -826,6 +826,11 @@ ap_ec_spi: &spi8 { /* PINCTRL - additions to nodes defined in sc7280.dtsi */ +&pcie1_clkreq_n { + bias-pull-up; + drive-strength = <2>; +}; + &qspi_cs0 { bias-disable; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 23e656e51904..6e20e8c07402 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -366,6 +366,11 @@ }; }; +&pcie1_clkreq_n { + bias-pull-up; + drive-strength = <2>; +}; + &qspi_cs0 { bias-disable; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 269cf722d20f..5b20cd40d896 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3295,8 +3295,6 @@ pcie1_clkreq_n: pcie1-clkreq-n { pins = "gpio79"; function = "pcie1_clkreqn"; - drive-strength = <2>; - bias-pull-up; }; qspi_clk: qspi-clk { -- cgit From ad4152d6e2599c62ef012e528acc5e77ca6765c1 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Wed, 2 Feb 2022 13:23:44 -0800 Subject: arm64: dts: qcom: sc7280: Move dp_hot_plug_det pull from SoC dtsi file Pulls should be in the board files, not in the SoC dtsi file. Remove. Even though the sc7280 boards don't currently refer to dp_hot_plug_det, let's re-add the pulls there just to keep this as a no-op change. If boards don't need this / don't want it later then we can remove it from them. Signed-off-by: Douglas Anderson Reviewed-by: Stephen Boyd Reviewed-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220202132301.v3.10.Id346b23642f91e16d68d75f44bcdb5b9fbd155ea@changeid --- arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts | 4 ++++ arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 4 ++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 1 - 3 files changed, 8 insertions(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts index 82c3c8f0342b..b36d12f8f4a0 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts @@ -826,6 +826,10 @@ ap_ec_spi: &spi8 { /* PINCTRL - additions to nodes defined in sc7280.dtsi */ +&dp_hot_plug_det { + bias-disable; +}; + &pcie1_clkreq_n { bias-pull-up; drive-strength = <2>; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 6e20e8c07402..ecbf2b89d896 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -355,6 +355,10 @@ /* PINCTRL - additions to nodes defined in sc7280.dtsi */ +&dp_hot_plug_det { + bias-disable; +}; + &pm7325_gpios { key_vol_up_default: key-vol-up-default { pins = "gpio6"; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 5b20cd40d896..54995212280d 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3284,7 +3284,6 @@ dp_hot_plug_det: dp-hot-plug-det { pins = "gpio47"; function = "dp_hot"; - bias-disable; }; edp_hot_plug_det: edp-hot-plug-det { -- cgit From 96b34a6ea7d03876fb9b82ac8db5648a24fc7b2e Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Wed, 2 Feb 2022 13:23:45 -0800 Subject: arm64: dts: qcom: sc7280: Add a blank line in the dp node It's weird that there's a blank line between the two port nodes but not between the attributes and the first port node. Add an extra blank line to make it look right. Signed-off-by: Douglas Anderson Reviewed-by: Stephen Boyd Reviewed-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220202132301.v3.11.Iecb7267402e697a5cfef4cd517116ea5b308ac9e@changeid --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 54995212280d..3572399282d8 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3149,6 +3149,7 @@ ports { #address-cells = <1>; #size-cells = <0>; + port@0 { reg = <0>; dp_in: endpoint { -- cgit From 067b2b3616cd5ed924b51064bcaab23ea1ffd18b Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 3 Feb 2022 14:30:31 +0530 Subject: arm64: dts: qcom: Add SM8450 HDK DTS This adds the base HDK DTS along with the usb, ufs and regulators found in this board Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220203090031.3128702-2-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 405 ++++++++++++++++++++++++++++++++ 2 files changed, 406 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8450-hdk.dts (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 8aa3b3f1a292..4625b82d116c 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -123,4 +123,5 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8350-microsoft-surface-duo2.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx214.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx215.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8450-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8450-qrd.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts new file mode 100644 index 000000000000..f0fcb1428449 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -0,0 +1,405 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +/dts-v1/; + +#include +#include "sm8450.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8450 HDK"; + compatible = "qcom,sm8450-hdk", "qcom,sm8450"; + + aliases { + serial0 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; +}; + +&apps_rsc { + pm8350-rpmh-regulators { + compatible = "qcom,pm8350-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-s11-supply = <&vph_pwr>; + vdd-s12-supply = <&vph_pwr>; + + vdd-l1-l4-supply = <&vreg_s11b_0p95>; + vdd-l2-l7-supply = <&vreg_bob>; + vdd-l3-l5-supply = <&vreg_bob>; + vdd-l6-l9-l10-supply = <&vreg_s12b_1p25>; + vdd-l8-supply = <&vreg_s2h_0p95>; + + vreg_s10b_1p8: smps10 { + regulator-name = "vreg_s10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_s11b_0p95: smps11 { + regulator-name = "vreg_s11b_0p95"; + regulator-min-microvolt = <966000>; + regulator-max-microvolt = <1104000>; + }; + + vreg_s12b_1p25: smps12 { + regulator-name = "vreg_s12b_1p25"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1400000>; + }; + + vreg_l1b_0p91: ldo1 { + regulator-name = "vreg_l1b_0p91"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p07: ldo2 { + regulator-name = "vreg_l2b_3p07"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l3b_0p9: ldo3 { + regulator-name = "vreg_l3b_0p9"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <904000>; + regulator-initial-mode = ; + }; + + vreg_l5b_0p88: ldo5 { + regulator-name = "vreg_l5b_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <888000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p2: ldo6 { + regulator-name = "vreg_l6b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l7b_2p5: ldo7 { + regulator-name = "vreg_l7b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + }; + + vreg_l9b_1p2: ldo9 { + regulator-name = "vreg_l9b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + pm8350c-rpmh-regulators { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + + vdd-l1-l12-supply = <&vreg_bob>; + vdd-l2-l8-supply = <&vreg_bob>; + vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>; + vdd-l6-l9-l11-supply = <&vreg_bob>; + vdd-l10-supply = <&vreg_s12b_1p25>; + + vdd-bob-supply = <&vph_pwr>; + + vreg_s1c_1p86: smps1 { + regulator-name = "vreg_s1c_1p86"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2024000>; + }; + + vreg_s10c_1p05: smps10 { + regulator-name = "vreg_s10c_1p05"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + }; + + vreg_bob: bob { + regulator-name = "vreg_bob"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l3c_3p0: ldo3 { + regulator-name = "vreg_l3c_3p0"; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l4c_1p8: ldo4 { + regulator-name = "vreg_l4c_1p8"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l5c_1p8: ldo5 { + regulator-name = "vreg_l5c_1p8"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l6c_1p8: ldo6 { + regulator-name = "vreg_l6c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l7c_3p0: ldo7 { + regulator-name = "vreg_l7c_3p0"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p8: ldo8 { + regulator-name = "vreg_l8c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l9c_2p96: ldo9 { + regulator-name = "vreg_l9c_2p96"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l12c_1p8: ldo12 { + regulator-name = "vreg_l12c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1968000>; + regulator-initial-mode = ; + }; + + vreg_l13c_3p0: ldo13 { + regulator-name = "vreg_l13c_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + }; + + pm8450-rpmh-regulators { + compatible = "qcom,pm8450-rpmh-regulators"; + qcom,pmic-id = "h"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + + vdd-l2-supply = <&vreg_bob>; + vdd-l3-supply = <&vreg_bob>; + vdd-l4-supply = <&vreg_bob>; + + vreg_s2h_0p95: smps2 { + regulator-name = "vreg_s2h_0p95"; + regulator-min-microvolt = <848000>; + regulator-max-microvolt = <1104000>; + }; + + vreg_s3h_0p5: smps3 { + regulator-name = "vreg_s3h_0p5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <500000>; + }; + + vreg_l2h_0p91: ldo2 { + regulator-name = "vreg_l2h_0p91"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l3h_0p91: ldo3 { + regulator-name = "vreg_l3h_0p91"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + }; + + pmr735a-rpmh-regulators { + compatible = "qcom,pmr735a-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + + vdd-l1-l2-supply = <&vreg_s2e_0p85>; + vdd-l3-supply = <&vreg_s1e_1p25>; + vdd-l4-supply = <&vreg_s1c_1p86>; + vdd-l5-l6-supply = <&vreg_s1c_1p86>; + vdd-l7-bob-supply = <&vreg_bob>; + + vreg_s1e_1p25: smps1 { + regulator-name = "vreg_s1e_1p25"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1296000>; + }; + + vreg_s2e_0p85: smps2 { + regulator-name = "vreg_s2e_0p85"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1040000>; + }; + + vreg_l1e_0p8: ldo1 { + regulator-name = "vreg_l1e_0p8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + }; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_l4e_1p7: ldo4 { + regulator-name = "vreg_l4e_1p7"; + regulator-min-microvolt = <1776000>; + regulator-max-microvolt = <1776000>; + }; + + vreg_l5e_0p88: ldo5 { + regulator-name = "vreg_l5e_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + }; + + vreg_l6e_1p2: ldo6 { + regulator-name = "vreg_l6e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_l7e_2p8: ldo7 { + regulator-name = "vreg_l7e_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + }; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <28 4>, <36 4>; +}; + +&uart7 { + status = "okay"; +}; + +&ufs_mem_hc { + status = "okay"; + + reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l7b_2p5>; + vcc-max-microamp = <1100000>; + vccq-supply = <&vreg_l9b_1p2>; + vccq-max-microamp = <1200000>; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l5b_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + vdda-max-microamp = <173000>; + vdda-pll-max-microamp = <24900>; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + status = "okay"; + + vdda-pll-supply = <&vreg_l5b_0p88>; + vdda18-supply = <&vreg_l1c_1p8>; + vdda33-supply = <&vreg_l2b_3p07>; +}; + +&usb_1_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vreg_l6b_1p2>; + vdda-pll-supply = <&vreg_l1b_0p91>; +}; -- cgit From 116f7cc43d28ccd621ff1fecc9526c65dde28dcd Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Fri, 4 Feb 2022 14:06:07 -0800 Subject: arm64: dts: qcom: sc7280: Add herobrine-r1 Add the new herobrine-r1. Note that this is pretty much a re-design compared to herobrine-r0 so we don't attempt any dtsi to share stuff between them. This patch attempts to define things at 3 levels: 1. The Qcard level. Herobrine includes a Qcard PCB and the Qcard PCB is supposed to be the same (modulo stuffing options) across multiple boards, so trying to define what's there hopefully makes sense. NOTE that newer "CRD" boards from Qualcomm also use Qcard. When support for CRD3 is added hopefully it can use the Qcard include (and perhaps we should even evaluate it using herobrine.dtsi?) 2. The herobrine "baseboard" level. Right now most stuff is here with the exception of things that we _know_ will be different per board. We know that not all boards will have the same set of eMMC, nvme, and SD. We also know that the exact pin names are likely to be different. 3. The actual "board" level, AKA herobrine-rev1. NOTES: - This boots to command prompt. We're still waiting on the PWM driver. - This assumes LTE for now. Once it's clear how WiFi-only SKUs will work we expect some small changes. Signed-off-by: Douglas Anderson Reviewed-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220204140550.v4.1.I5604b7af908e8bbe709ac037a6a8a6ba8a2bfa94@changeid --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../dts/qcom/sc7280-herobrine-herobrine-r0.dts | 3 +- .../dts/qcom/sc7280-herobrine-herobrine-r1.dts | 313 ++++++++ arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 785 +++++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi | 547 ++++++++++++++ 5 files changed, 1647 insertions(+), 2 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi create mode 100644 arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 4625b82d116c..bcdc9abf0c42 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -84,6 +84,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r0.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp2.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-crd.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts index b36d12f8f4a0..af46a60b4b98 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts @@ -25,8 +25,7 @@ / { model = "Google Herobrine (rev0)"; - compatible = "google,herobrine", - "qcom,sc7280"; + compatible = "google,herobrine-rev0", "qcom,sc7280"; }; / { diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts new file mode 100644 index 000000000000..f95273052da0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts @@ -0,0 +1,313 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Herobrine board device tree source + * + * Copyright 2022 Google LLC. + */ + +/dts-v1/; + +#include "sc7280-herobrine.dtsi" + +/ { + model = "Google Herobrine (rev1+)"; + compatible = "google,herobrine", "qcom,sc7280"; +}; + +/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ + +&ap_spi_fp { + status = "okay"; +}; + +/* + * Although the trackpad is really part of the herobrine baseboard, we'll + * put the actual definition in the board device tree since different boards + * might hook up different trackpads (or no i2c trackpad at all in the case + * of tablets / detachables). + */ +ap_tp_i2c: &i2c0 { + status = "okay"; + clock-frequency = <400000>; + + trackpad: trackpad@15 { + compatible = "elan,ekth3000"; + reg = <0x15>; + pinctrl-names = "default"; + pinctrl-0 = <&tp_int_odl>; + + interrupt-parent = <&tlmm>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + + vcc-supply = <&pp3300_z1>; + + wakeup-source; + }; +}; + +/* + * The touchscreen connector might come off the Qcard, at least in the case of + * eDP. Like the trackpad, we'll put it in the board device tree file since + * different boards have different touchscreens. + */ +ts_i2c: &i2c13 { + status = "okay"; + clock-frequency = <400000>; + + ap_ts: touchscreen@5c { + compatible = "hid-over-i2c"; + reg = <0x5c>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_conn>, <&ts_rst_conn>; + + interrupt-parent = <&tlmm>; + interrupts = <55 IRQ_TYPE_LEVEL_LOW>; + + post-power-on-delay-ms = <500>; + hid-descr-addr = <0x0000>; + + vdd-supply = <&ts_avdd>; + }; +}; + +/* For nvme */ +&pcie1 { + status = "okay"; +}; + +/* For nvme */ +&pcie1_phy { + status = "okay"; +}; + +/* For eMMC */ +&sdhc_1 { + status = "okay"; +}; + +/* For SD Card */ +&sdhc_2 { + status = "okay"; +}; + +/* PINCTRL - BOARD-SPECIFIC */ + +/* + * Methodology for gpio-line-names: + * - If a pin goes to herobrine board and is named it gets that name. + * - If a pin goes to herobrine board and is not named, it gets no name. + * - If a pin is totally internal to Qcard then it gets Qcard name. + * - If a pin is not hooked up on Qcard, it gets no name. + */ + +&pm8350c_gpios { + gpio-line-names = "FLASH_STROBE_1", /* 1 */ + "AP_SUSPEND", + "PM8008_1_RST_N", + "", + "", + "", + "PMIC_EDP_BL_EN", + "PMIC_EDP_BL_PWM", + ""; +}; + +&tlmm { + gpio-line-names = "AP_TP_I2C_SDA", /* 0 */ + "AP_TP_I2C_SCL", + "SSD_RST_L", + "PE_WAKE_ODL", + "AP_SAR_SDA", + "AP_SAR_SCL", + "PRB_SC_GPIO_6", + "TP_INT_ODL", + "HP_I2C_SDA", + "HP_I2C_SCL", + + "GNSS_L1_EN", /* 10 */ + "GNSS_L5_EN", + "SPI_AP_MOSI", + "SPI_AP_MISO", + "SPI_AP_CLK", + "SPI_AP_CS0_L", + /* + * AP_FLASH_WP is crossystem ABI. Schematics + * call it BIOS_FLASH_WP_OD. + */ + "AP_FLASH_WP", + "", + "AP_EC_INT_L", + "", + + "UF_CAM_RST_L", /* 20 */ + "WF_CAM_RST_L", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "", + "PM8008_IRQ_1", + "HOST2WLAN_SOL", + "WLAN2HOST_SOL", + "MOS_BT_UART_CTS", + "MOS_BT_UART_RFR", + + "MOS_BT_UART_TX", /* 30 */ + "MOS_BT_UART_RX", + "PRB_SC_GPIO_32", + "HUB_RST_L", + "", + "", + "AP_SPI_FP_MISO", + "AP_SPI_FP_MOSI", + "AP_SPI_FP_CLK", + "AP_SPI_FP_CS_L", + + "AP_EC_SPI_MISO", /* 40 */ + "AP_EC_SPI_MOSI", + "AP_EC_SPI_CLK", + "AP_EC_SPI_CS_L", + "LCM_RST_L", + "EARLY_EUD_N", + "", + "DP_HOT_PLUG_DET", + "IO_BRD_MLB_ID0", + "IO_BRD_MLB_ID1", + + "IO_BRD_MLB_ID2", /* 50 */ + "SSD_EN", + "TS_I2C_SDA_CONN", + "TS_I2C_CLK_CONN", + "TS_RST_CONN", + "TS_INT_CONN", + "AP_I2C_TPM_SDA", + "AP_I2C_TPM_SCL", + "PRB_SC_GPIO_58", + "PRB_SC_GPIO_59", + + "EDP_HOT_PLUG_DET_N", /* 60 */ + "FP_TO_AP_IRQ_L", + "", + "AMP_EN", + "CAM0_MCLK_GPIO_64", + "CAM1_MCLK_GPIO_65", + "WF_CAM_MCLK", + "PRB_SC_GPIO_67", + "FPMCU_BOOT0", + "UF_CAM_SDA", + + "UF_CAM_SCL", /* 70 */ + "", + "", + "WF_CAM_SDA", + "WF_CAM_SCL", + "", + "", + "EN_FP_RAILS", + "FP_RST_L", + "PCIE1_CLKREQ_ODL", + + "EN_PP3300_DX_EDP", /* 80 */ + "SC_GPIO_81", + "FORCED_USB_BOOT", + "WCD_RESET_N", + "MOS_WLAN_EN", + "MOS_BT_EN", + "MOS_SW_CTRL", + "MOS_PCIE0_RST", + "MOS_PCIE0_CLKREQ_N", + "MOS_PCIE0_WAKE_N", + + "MOS_LAA_AS_EN", /* 90 */ + "SD_CD_ODL", + "", + "", + "MOS_BT_WLAN_SLIMBUS_CLK", + "MOS_BT_WLAN_SLIMBUS_DAT0", + "HP_MCLK", + "HP_BCLK", + "HP_DOUT", + "HP_DIN", + + "HP_LRCLK", /* 100 */ + "HP_IRQ", + "", + "", + "GSC_AP_INT_ODL", + "EN_PP3300_CODEC", + "AMP_BCLK", + "AMP_DIN", + "AMP_LRCLK", + "UIM1_DATA_GPIO_109", + + "UIM1_CLK_GPIO_110", /* 110 */ + "UIM1_RESET_GPIO_111", + "PRB_SC_GPIO_112", + "UIM0_DATA", + "UIM0_CLK", + "UIM0_RST", + "UIM0_PRESENT_ODL", + "SDM_RFFE0_CLK", + "SDM_RFFE0_DATA", + "WF_CAM_EN", + + "FASTBOOT_SEL_0", /* 120 */ + "SC_GPIO_121", + "FASTBOOT_SEL_1", + "SC_GPIO_123", + "FASTBOOT_SEL_2", + "SM_RFFE4_CLK_GRFC_8", + "SM_RFFE4_DATA_GRFC_9", + "WLAN_COEX_UART1_RX", + "WLAN_COEX_UART1_TX", + "PRB_SC_GPIO_129", + + "LCM_ID0", /* 130 */ + "LCM_ID1", + "", + "SDR_QLINK_REQ", + "SDR_QLINK_EN", + "QLINK0_WMSS_RESET_N", + "SMR526_QLINK1_REQ", + "SMR526_QLINK1_EN", + "SMR526_QLINK1_WMSS_RESET_N", + "PRB_SC_GPIO_139", + + "SAR1_IRQ_ODL", /* 140 */ + "SAR0_IRQ_ODL", + "PRB_SC_GPIO_142", + "", + "WCD_SWR_TX_CLK", + "WCD_SWR_TX_DATA0", + "WCD_SWR_TX_DATA1", + "WCD_SWR_RX_CLK", + "WCD_SWR_RX_DATA0", + "WCD_SWR_RX_DATA1", + + "DMIC01_CLK", /* 150 */ + "DMIC01_DATA", + "DMIC23_CLK", + "DMIC23_DATA", + "", + "", + "EC_IN_RW_ODL", + "HUB_EN", + "WCD_SWR_TX_DATA2", + "", + + "", /* 160 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + + "", /* 170 */ + "MOS_BLE_UART_TX", + "MOS_BLE_UART_RX", + "", + "", + ""; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi new file mode 100644 index 000000000000..7c22f0b062be --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -0,0 +1,785 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Herobrine baseboard device tree source + * + * The set of things in this file is a bit loosely defined. It's roughly + * defined as the set of things that the child boards happen to have in + * common. Since all of the child boards started from the same original + * design this is hopefully a large set of things but as more derivatives + * appear things may "bubble down" out of this file. For things that are + * part of the reference design but might not exist on child nodes we will + * follow the lead of the SoC dtsi files and leave their status as "disabled". + * + * Copyright 2022 Google LLC. + */ + +#include +#include + +#include "sc7280-qcard.dtsi" +#include "sc7280-chrome-common.dtsi" + +/ { + chosen { + stdout-path = "serial0:115200n8"; + }; + + /* + * FIXED REGULATORS + * + * Sort order: + * 1. parents above children. + * 2. higher voltage above lower voltage. + * 3. alphabetically by node name. + */ + + /* This is the top level supply and variable voltage */ + ppvar_sys: ppvar-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "ppvar_sys"; + regulator-always-on; + regulator-boot-on; + }; + + /* This divides ppvar_sys by 2, so voltage is variable */ + src_vph_pwr: src-vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "src_vph_pwr"; + + /* EC turns on with switchcap_on; always on for AP */ + regulator-always-on; + regulator-boot-on; + + vin-supply = <&ppvar_sys>; + }; + + pp5000_s5: pp5000-s5-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp5000_s5"; + + /* EC turns on with en_pp5000_s5; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + vin-supply = <&ppvar_sys>; + }; + + pp3300_z1: pp3300-z1-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp3300_z1"; + + /* EC turns on with en_pp3300_z1; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + vin-supply = <&ppvar_sys>; + }; + + pp3300_codec: pp3300-codec-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp3300_codec"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 105 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&en_pp3300_codec>; + + vin-supply = <&pp3300_z1>; + }; + + pp3300_left_in_mlb: pp3300-left-in-mlb-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp3300_left_in_mlb"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 80 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&en_pp3300_dx_edp>; + + vin-supply = <&pp3300_z1>; + }; + + pp3300_mcu_fp: + pp3300_fp_ls: + pp3300_fp_mcu: pp3300-fp-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp3300_fp"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-boot-on; + regulator-always-on; + + /* + * WARNING: it is intentional that GPIO 77 isn't listed here. + * The userspace script for updating the fingerprint firmware + * needs to control the FP regulators during a FW update, + * hence the signal can't be owned by the kernel regulator. + */ + + pinctrl-names = "default"; + pinctrl-0 = <&en_fp_rails>; + + vin-supply = <&pp3300_z1>; + }; + + pp3300_hub: pp3300-hub-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp3300_hub"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-boot-on; + regulator-always-on; + + gpio = <&tlmm 157 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&hub_en>; + + vin-supply = <&pp3300_z1>; + }; + + pp3300_tp: pp3300-tp-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp3300_tp"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + /* AP turns on with PP1800_L18B_S0; always on for AP */ + regulator-always-on; + regulator-boot-on; + + vin-supply = <&pp3300_z1>; + }; + + pp3300_ssd: pp3300-ssd-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp3300_ssd"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 51 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&ssd_en>; + + vin-supply = <&pp3300_z1>; + }; + + pp2850_vcm_wf_cam: pp2850-vcm-wf-cam-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp2850_vcm_wf_cam"; + + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + + gpio = <&tlmm 119 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&wf_cam_en>; + + vin-supply = <&pp3300_z1>; + }; + + pp2850_wf_cam: pp2850-wf-cam-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp2850_wf_cam"; + + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + + gpio = <&tlmm 119 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * The pinconf can only be referenced once so we put it on the + * first regulator and comment it out here. + * + * pinctrl-names = "default"; + * pinctrl-0 = <&wf_cam_en>; + */ + + vin-supply = <&pp3300_z1>; + }; + + pp1800_fp: pp1800-fp-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp1800_fp"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-boot-on; + regulator-always-on; + + /* + * WARNING: it is intentional that GPIO 77 isn't listed here. + * The userspace script for updating the fingerprint firmware + * needs to control the FP regulators during a FW update, + * hence the signal can't be owned by the kernel regulator. + */ + + pinctrl-names = "default"; + pinctrl-0 = <&en_fp_rails>; + + vin-supply = <&pp1800_l18b_s0>; + status = "disabled"; + }; + + pp1800_wf_cam: pp1800-wf-cam-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp1800_wf_cam"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 119 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * The pinconf can only be referenced once so we put it on the + * first regulator and comment it out here. + * + * pinctrl-names = "default"; + * pinctrl-0 = <&wf_cam_en>; + */ + + vin-supply = <&vreg_l19b_s0>; + }; + + pp1200_wf_cam: pp1200-wf-cam-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp1200_wf_cam"; + + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + gpio = <&tlmm 119 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * The pinconf can only be referenced once so we put it on the + * first regulator and comment it out here. + * + * pinctrl-names = "default"; + * pinctrl-0 = <&wf_cam_en>; + */ + + vin-supply = <&pp3300_z1>; + }; + + /* BOARD-SPECIFIC TOP LEVEL NODES */ + + pwmleds { + compatible = "pwm-leds"; + status = "disabled"; + keyboard_backlight: keyboard-backlight { + status = "disabled"; + label = "cros_ec::kbd_backlight"; + pwms = <&cros_ec_pwm 0>; + max-brightness = <1023>; + }; + }; +}; + +/* + * BOARD-LOCAL NAMES FOR REGULATORS THAT CONNECT TO QCARD + * + * Names are only listed here if regulators go somewhere other than a + * testpoint. + */ + +/* From Qcard to our board; ordered by PMIC-ID / rail number */ + +pp1256_s8b: &vreg_s8b_1p256 {}; + +pp1800_l18b_s0: &vreg_l18b_1p8 {}; +pp1800_l18b: &vreg_l18b_1p8 {}; + +vreg_l19b_s0: &vreg_l19b_1p8 {}; + +pp1800_alc5682: &vreg_l2c_1p8 {}; +pp1800_l2c: &vreg_l2c_1p8 {}; + +vreg_l4c: &vreg_l4c_1p8_3p0 {}; + +ppvar_l6c: &vreg_l6c_2p96 {}; + +pp3000_l7c: &vreg_l7c_3p0 {}; + +pp1800_prox: &vreg_l8c_1p8 {}; +pp1800_l8c: &vreg_l8c_1p8 {}; + +pp2950_l9c: &vreg_l9c_2p96 {}; + +pp1800_lcm: &vreg_l12c_1p8 {}; +pp1800_mipi: &vreg_l12c_1p8 {}; +pp1800_l12c: &vreg_l12c_1p8 {}; + +pp3300_lcm: &vreg_l13c_3p0 {}; +pp3300_mipi: &vreg_l13c_3p0 {}; +pp3300_l13c: &vreg_l13c_3p0 {}; + +/* From our board to Qcard; ordered same as node definition above */ + +vreg_edp_bl: &ppvar_sys {}; + +ts_avdd: &pp3300_left_in_mlb {}; +vreg_edp_3p3: &pp3300_left_in_mlb {}; + +/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ + +ap_i2c_tpm: &i2c14 { + status = "okay"; + clock-frequency = <400000>; + + tpm@50 { + compatible = "google,cr50"; + reg = <0x50>; + + pinctrl-names = "default"; + pinctrl-0 = <&gsc_ap_int_odl>; + + interrupt-parent = <&tlmm>; + interrupts = <104 IRQ_TYPE_EDGE_RISING>; + }; +}; + +/* NVMe drive, enabled on a per-board basis */ +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_clkreq_n>, <&ssd_rst_l>, <&pe_wake_odl>; + + perst-gpio = <&tlmm 2 GPIO_ACTIVE_LOW>; + vddpe-3v3-supply = <&pp3300_ssd>; +}; + +&pmk8350_rtc { + status = "disabled"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +/* SD Card, enabled on a per-board basis */ +&sdhc_2 { + pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>, <&sd_cd_odl>; + pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>, <&sd_cd_odl>; + + vmmc-supply = <&pp2950_l9c>; + vqmmc-supply = <&ppvar_l6c>; + + cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; +}; + +/* Fingerprint, enabled on a per-board basis */ +ap_spi_fp: &spi9 { + pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs_gpio_init_high>, <&qup_spi9_cs_gpio>; + + cs-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>; + + cros_ec_fp: ec@0 { + compatible = "google,cros-ec-spi"; + reg = <0>; + interrupt-parent = <&tlmm>; + interrupts = <61 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&fp_to_ap_irq_l>, <&fp_rst_l>, <&fpmcu_boot0>; + spi-max-frequency = <3000000>; + }; +}; + +ap_ec_spi: &spi10 { + status = "okay"; + pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs_gpio_init_high>, <&qup_spi10_cs_gpio>; + + cs-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>; + + cros_ec: ec@0 { + compatible = "google,cros-ec-spi"; + reg = <0>; + interrupt-parent = <&tlmm>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ap_ec_int_l>; + spi-max-frequency = <3000000>; + + cros_ec_pwm: ec-pwm { + compatible = "google,cros-ec-pwm"; + #pwm-cells = <1>; + }; + + i2c_tunnel: i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + google,remote-bus = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + typec { + compatible = "google,cros-ec-typec"; + #address-cells = <1>; + #size-cells = <0>; + + usb_c0: connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + label = "left"; + power-role = "dual"; + data-role = "host"; + try-power-role = "source"; + }; + + usb_c1: connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + label = "right"; + power-role = "dual"; + data-role = "host"; + try-power-role = "source"; + }; + }; + }; +}; + +#include +#include + +&keyboard_controller { + function-row-physmap = < + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + >; + linux,keymap = < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + + CROS_STD_MAIN_KEYMAP + >; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "host"; +}; + +&usb_1_hsphy { + status = "okay"; +}; + +&usb_1_qmpphy { + status = "okay"; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; + +&usb_2_hsphy { + status = "okay"; +}; + +/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */ + +&dp_hot_plug_det { + bias-disable; +}; + +&pcie1_clkreq_n { + bias-pull-up; + drive-strength = <2>; +}; + +&qspi_cs0 { + bias-disable; + drive-strength = <8>; +}; + +&qspi_clk { + bias-disable; + drive-strength = <8>; +}; + +&qspi_data01 { + /* High-Z when no transfers; nice to park the lines */ + bias-pull-up; + drive-strength = <8>; +}; + +/* For ap_tp_i2c */ +&qup_i2c0_data_clk { + /* Has external pull */ + bias-disable; + drive-strength = <2>; +}; + +/* For ap_i2c_tpm */ +&qup_i2c14_data_clk { + /* Has external pull */ + bias-disable; + drive-strength = <2>; +}; + +/* For ap_spi_fp */ +&qup_spi9_data_clk { + bias-disable; + drive-strength = <2>; +}; + +/* For ap_spi_fp */ +&qup_spi9_cs_gpio { + bias-disable; + drive-strength = <2>; +}; + +/* For ap_ec_spi */ +&qup_spi10_data_clk { + bias-disable; + drive-strength = <2>; +}; + +/* For ap_ec_spi */ +&qup_spi10_cs_gpio { + bias-disable; + drive-strength = <2>; +}; + +/* For uart_dbg */ +&qup_uart5_rx { + bias-pull-up; +}; + +/* For uart_dbg */ +&qup_uart5_tx { + bias-disable; + drive-strength = <2>; +}; + +&sdc2_clk { + bias-disable; + drive-strength = <16>; +}; + +&sdc2_cmd { + bias-pull-up; + drive-strength = <10>; +}; + +&sdc2_data { + bias-pull-up; + drive-strength = <10>; +}; + +/* PINCTRL - board-specific pinctrl */ + +&pm7325_gpios { + /* + * On a quick glance it might look like KYPD_VOL_UP_N is used, but + * that only passes through to a debug connector and not to the actual + * volume up key. + */ + status = "disabled"; /* No GPIOs are connected */ +}; + +&pmk8350_gpios { + status = "disabled"; /* No GPIOs are connected */ +}; + +&tlmm { + /* pinctrl settings for pins that have no real owners. */ + pinctrl-names = "default"; + pinctrl-0 = <&bios_flash_wp_od>; + + amp_en: amp-en { + pins = "gpio63"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + + ap_ec_int_l: ap-ec-int-l { + pins = "gpio18"; + function = "gpio"; + bias-pull-up; + }; + + bios_flash_wp_od: bios-flash-wp-od { + pins = "gpio16"; + function = "gpio"; + /* Has external pull */ + bias-disable; + }; + + en_fp_rails: en-fp-rails { + pins = "gpio77"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + output-high; + }; + + en_pp3300_codec: en-pp3300-codec { + pins = "gpio105"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + + en_pp3300_dx_edp: en-pp3300-dx-edp { + pins = "gpio80"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + + fp_rst_l: fp-rst-l { + pins = "gpio78"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + output-high; + }; + + fp_to_ap_irq_l: fp-to-ap-irq-l { + pins = "gpio61"; + function = "gpio"; + /* Has external pullup */ + bias-disable; + }; + + fpmcu_boot0: fpmcu-boot0 { + pins = "gpio68"; + function = "gpio"; + bias-disable; + output-low; + }; + + gsc_ap_int_odl: gsc-ap-int-odl { + pins = "gpio104"; + function = "gpio"; + bias-pull-up; + }; + + hp_irq: hp-irq { + pins = "gpio101"; + function = "gpio"; + bias-pull-up; + }; + + hub_en: hub-en { + pins = "gpio157"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + + pe_wake_odl: pe-wake-odl { + pins = "gpio3"; + function = "gpio"; + /* Has external pull */ + bias-disable; + drive-strength = <2>; + }; + + /* For ap_spi_fp */ + qup_spi9_cs_gpio_init_high: qup-spi9-cs-gpio-init-high { + pins = "gpio39"; + function = "gpio"; + output-high; + }; + + /* For ap_ec_spi */ + qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high { + pins = "gpio43"; + function = "gpio"; + output-high; + }; + + sar0_irq_odl: sar0-irq-odl { + pins = "gpio141"; + function = "gpio"; + bias-pull-up; + }; + + sar1_irq_odl: sar0-irq-odl { + pins = "gpio140"; + function = "gpio"; + bias-pull-up; + }; + + sd_cd_odl: sd-cd-odl { + pins = "gpio91"; + function = "gpio"; + bias-pull-up; + }; + + ssd_en: ssd-en { + pins = "gpio51"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + + ssd_rst_l: ssd-rst-l { + pins = "gpio2"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + output-low; + }; + + tp_int_odl: tp-int-odl { + pins = "gpio7"; + function = "gpio"; + /* Has external pullup */ + bias-disable; + }; + + wf_cam_en: wf-cam-en { + pins = "gpio119"; + function = "gpio"; + /* Has external pulldown */ + bias-disable; + drive-strength = <2>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi new file mode 100644 index 000000000000..b833ba1e8f4a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi @@ -0,0 +1,547 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * sc7280 Qcard device tree source + * + * Qcard PCB has the processor, RAM, eMMC (if stuffed), and eDP connector (if + * stuffed) on it. This device tree tries to encapsulate all the things that + * all boards using Qcard will have in common. Given that there are stuffing + * options, some things may be left with status "disabled" and enabled in + * the actual board device tree files. + * + * Copyright 2022 Google LLC. + */ + +#include +#include +#include +#include + +#include "sc7280.dtsi" + +/* PMICs depend on spmi_bus label and so must come after SoC */ +#include "pm7325.dtsi" +#include "pm8350c.dtsi" +#include "pmk8350.dtsi" + +/ { + aliases { + bluetooth0 = &bluetooth; + serial0 = &uart5; + serial1 = &uart7; + }; +}; + +&apps_rsc { + /* + * Regulators are given labels corresponding to the various names + * they are referred to on schematics. They are also given labels + * corresponding to named voltage inputs on the SoC or components + * bundled with the SoC (like radio companion chips). We totally + * ignore it when one regulator is the input to another regulator. + * That's handled automatically by the initial config given to + * RPMH by the firmware. + * + * Regulators that the HLOS (High Level OS) doesn't touch at all + * are left out of here since they are managed elsewhere. + */ + + pm7325-regulators { + compatible = "qcom,pm7325-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd19_pmu_pcie_i: + vdd19_pmu_rfa_i: + vreg_s1b_1p856: smps1 { + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2040000>; + }; + + vdd_pmu_aon_i: + vdd09_pmu_rfa_i: + vdd095_mx_pmu: + vdd095_pmu: + vreg_s7b_0p952: smps7 { + regulator-min-microvolt = <535000>; + regulator-max-microvolt = <1120000>; + }; + + vdd13_pmu_rfa_i: + vdd13_pmu_pcie_i: + vreg_s8b_1p256: smps8 { + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1500000>; + }; + + vdd_a_usbssdp_0_core: + vreg_l1b_0p912: ldo1 { + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <925000>; + regulator-initial-mode = ; + }; + + vdd_a_usbhs_3p1: + vreg_l2b_3p072: ldo2 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vdd_a_csi_0_1_1p2: + vdd_a_csi_2_3_1p2: + vdd_a_csi_4_1p2: + vdd_a_dsi_0_1p2: + vdd_a_edp_0_1p2: + vdd_a_qlink_0_1p2: + vdd_a_qlink_1_1p2: + vdd_a_pcie_0_1p2: + vdd_a_pcie_1_1p2: + vdd_a_ufs_0_1p2: + vdd_a_usbssdp_0_1p2: + vreg_l6b_1p2: ldo6 { + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + }; + + /* + * Despite the fact that this is named to be 2.5V on the + * schematic, it powers eMMC which doesn't accept 2.5V + */ + vreg_l7b_2p5: ldo7 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vdd_px_wcd9385: + vdd_txrx: + vddpx_0: + vddpx_3: + vddpx_7: + vreg_l18b_1p8: ldo18 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vdd_1p8: + vdd_px_sdr735: + vdd_pxm: + vdd18_io: + vddio_px_1: + vddio_px_2: + vddio_px_3: + vddpx_ts: + vddpx_wl4otp: + vreg_l19b_1p8: ldo19 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + pm8350c-regulators { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd22_wlbtpa_ch0: + vdd22_wlbtpa_ch1: + vdd22_wlbtppa_ch0: + vdd22_wlbtppa_ch1: + vdd22_wlpa5g_ch0: + vdd22_wlpa5g_ch1: + vdd22_wlppa5g_ch0: + vdd22_wlppa5g_ch1: + vreg_s1c_2p2: smps1 { + regulator-min-microvolt = <2190000>; + regulator-max-microvolt = <2210000>; + }; + + lp4_vdd2_1p052: + vreg_s9c_0p676: smps9 { + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + }; + + vdda_apc_cs_1p8: + vdda_gfx_cs_1p8: + vdda_turing_q6_cs_1p8: + vdd_a_cxo_1p8: + vdd_a_qrefs_1p8: + vdd_a_usbhs_1p8: + vdd_qfprom: + vreg_l1c_1p8: ldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = ; + }; + + vreg_l2c_1p8: ldo2 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = ; + }; + + vreg_l3c_3p0: ldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3540000>; + regulator-initial-mode = ; + }; + + vddpx_5: + vreg_l4c_1p8_3p0: ldo4 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vddpx_6: + vreg_l5c_1p8_3p0: ldo5 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vddpx_2: + vreg_l6c_2p96: ldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-initial-mode = ; + }; + + vreg_l7c_3p0: ldo7 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p8: ldo8 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l9c_2p96: ldo9 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vdd_a_csi_0_1_0p9: + vdd_a_csi_2_3_0p9: + vdd_a_csi_4_0p9: + vdd_a_dsi_0_0p9: + vdd_a_dsi_0_pll_0p9: + vdd_a_edp_0_0p9: + vdd_a_gnss_0p9: + vdd_a_pcie_0_core: + vdd_a_pcie_1_core: + vdd_a_qlink_0_0p9: + vdd_a_qlink_0_0p9_ck: + vdd_a_qlink_1_0p9: + vdd_a_qlink_1_0p9_ck: + vdd_a_qrefs_0p875_0: + vdd_a_qrefs_0p875_1: + vdd_a_qrefs_0p875_2: + vdd_a_qrefs_0p875_3: + vdd_a_qrefs_0p875_4_5: + vdd_a_qrefs_0p875_6: + vdd_a_qrefs_0p875_7: + vdd_a_qrefs_0p875_8: + vdd_a_qrefs_0p875_9: + vdd_a_ufs_0_core: + vdd_a_usbhs_core: + vreg_l10c_0p88: ldo10 { + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1050000>; + regulator-initial-mode = ; + }; + + vreg_l11c_2p8: ldo11 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l12c_1p8: ldo12 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l13c_3p0: ldo13 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vdd_flash: + vdd_iris_rgb: + vdd_mic_bias: + vreg_bob: bob { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + }; +}; + +/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ + +&ipa { + status = "okay"; + modem-init; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; +}; + +&pmk8350_vadc { + pmk8350-die-temp@3 { + reg = ; + label = "pmk8350_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + pmr735a-die-temp@403 { + reg = ; + label = "pmr735a_die_temp"; + qcom,pre-scaling = <1 1>; + }; +}; + +&qfprom { + vcc-supply = <&vdd_qfprom>; +}; + +/* For eMMC. NOTE: not all Qcards have eMMC stuffed */ +&sdhc_1 { + vmmc-supply = <&vreg_l7b_2p5>; + vqmmc-supply = <&vreg_l19b_1p8>; + + non-removable; + no-sd; + no-sdio; +}; + +uart_dbg: &uart5 { + compatible = "qcom,geni-debug-uart"; + status = "okay"; +}; + +mos_bt_uart: &uart7 { + status = "okay"; + + /delete-property/ interrupts; + interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 31 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default", "sleep"; + pinctrl-1 = <&qup_uart7_sleep_cts>, <&qup_uart7_sleep_rts>, <&qup_uart7_sleep_tx>, <&qup_uart7_sleep_rx>; + + bluetooth: bluetooth { + compatible = "qcom,wcn6750-bt"; + pinctrl-names = "default"; + pinctrl-0 = <&mos_bt_en>; + enable-gpios = <&tlmm 85 GPIO_ACTIVE_HIGH>; + swctrl-gpios = <&tlmm 86 GPIO_ACTIVE_HIGH>; + vddaon-supply = <&vreg_s7b_0p952>; + vddbtcxmx-supply = <&vreg_s7b_0p952>; + vddrfacmn-supply = <&vreg_s7b_0p952>; + vddrfa0p8-supply = <&vreg_s7b_0p952>; + vddrfa1p7-supply = <&vdd19_pmu_rfa_i>; + vddrfa1p2-supply = <&vdd13_pmu_rfa_i>; + vddrfa2p2-supply = <&vreg_s1c_2p2>; + vddasd-supply = <&vreg_l11c_2p8>; + vddio-supply = <&vreg_l18b_1p8>; + max-speed = <3200000>; + }; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vdd_a_usbhs_core>; + vdda33-supply = <&vdd_a_usbhs_3p1>; + vdda18-supply = <&vdd_a_usbhs_1p8>; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vdd_a_usbssdp_0_1p2>; + vdda-pll-supply = <&vdd_a_usbssdp_0_core>; +}; + +&usb_2_hsphy { + vdda-pll-supply = <&vdd_a_usbhs_core>; + vdda33-supply = <&vdd_a_usbhs_3p1>; + vdda18-supply = <&vdd_a_usbhs_1p8>; +}; + +/* + * PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES + * + * NOTE: In general if pins leave the Qcard then the pinctrl goes in the + * baseboard or board device tree, not here. + */ + +/* + * For ts_i2c + * + * Technically this i2c bus actually leaves the Qcard, but it leaves directly + * via the eDP connector (it doesn't hit the baseboard). The external pulls + * are on Qcard. + */ +&qup_i2c13_data_clk { + /* Has external pull */ + bias-disable; + drive-strength = <2>; +}; + +/* For mos_bt_uart */ +&qup_uart7_cts { + /* Configure a pull-down on CTS to match the pull of the Bluetooth module. */ + bias-pull-down; +}; + +/* For mos_bt_uart */ +&qup_uart7_rts { + /* We'll drive RTS, so no pull */ + bias-disable; + drive-strength = <2>; +}; + +/* For mos_bt_uart */ +&qup_uart7_tx { + /* We'll drive TX, so no pull */ + bias-disable; + drive-strength = <2>; +}; + +/* For mos_bt_uart */ +&qup_uart7_rx { + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module is + * in tri-state (module powered off or not driving the + * signal yet). + */ + bias-pull-up; +}; + +/* eMMC, if stuffed, is straight on the Qcard */ +&sdc1_clk { + bias-disable; + drive-strength = <16>; +}; + +&sdc1_cmd { + bias-pull-up; + drive-strength = <10>; +}; + +&sdc1_data { + bias-pull-up; + drive-strength = <10>; +}; + +&sdc1_rclk { + bias-pull-down; +}; + +/* + * PINCTRL - QCARD + * + * This has entries that are defined by Qcard even if they go to the main + * board. In cases where the pulls may be board dependent we defer those + * settings to the board device tree. Drive strengths tend to be assinged here + * but could conceivably be overwridden by board device trees. + */ + +&pm8350c_gpios { + pmic_edp_bl_en: pmic-edp-bl-en { + pins = "gpio7"; + function = "normal"; + bias-disable; + qcom,drive-strength = ; + + /* Force backlight to be disabled to match state at boot. */ + output-low; + }; + + pmic_edp_bl_pwm: pmic-edp-bl-pwm { + pins = "gpio8"; + function = "func1"; + bias-disable; + qcom,drive-strength = ; + output-low; + power-source = <0>; + }; +}; + +&tlmm { + mos_bt_en: mos-bt-en { + pins = "gpio85"; + function = "gpio"; + drive-strength = <2>; + output-low; + }; + + /* For mos_bt_uart */ + qup_uart7_sleep_cts: qup-uart7-sleep-cts { + pins = "gpio28"; + function = "gpio"; + /* + * Configure a pull-down on CTS to match the pull of + * the Bluetooth module. + */ + bias-pull-down; + }; + + /* For mos_bt_uart */ + qup_uart7_sleep_rts: qup-uart7-sleep-rts { + pins = "gpio29"; + function = "gpio"; + /* + * Configure pull-down on RTS. As RTS is active low + * signal, pull it low to indicate the BT SoC that it + * can wakeup the system anytime from suspend state by + * pulling RX low (by sending wakeup bytes). + */ + bias-pull-down; + }; + + /* For mos_bt_uart */ + qup_uart7_sleep_rx: qup-uart7-sleep-rx { + pins = "gpio31"; + function = "gpio"; + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module + * is floating which may cause spurious wakeups. + */ + bias-pull-up; + }; + + /* For mos_bt_uart */ + qup_uart7_sleep_tx: qup-uart7-sleep-tx { + pins = "gpio30"; + function = "gpio"; + /* + * Configure pull-up on TX when it isn't actively driven + * to prevent BT SoC from receiving garbage during sleep. + */ + bias-pull-up; + }; + + ts_int_conn: ts-int-conn { + pins = "gpio55"; + function = "gpio"; + bias-pull-up; + }; + + ts_rst_conn: ts-rst-conn { + pins = "gpio54"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; +}; -- cgit From 726fd781195dc99cdcb60b2678694bfa5ccd1825 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 3 Feb 2022 17:06:33 +0000 Subject: arm64: dts: renesas: rzg2l-smarc: Add common dtsi file RZ/{G2L,V2L} and G2LC SoC use the same carrier board, but the SoM is different. Different pin mapping is possible on SoM. For eg:- RZ/G2L SMARC EVK uses SCIF2, whereas RZ/G2LC uses SCIF1 for the serial interface available on PMOD1. This patch adds support for handling the pin mapping differences by moving definitions common to RZ/G2L and RZ/G2LC to a common dtsi file. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220203170636.7747-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts | 9 +- arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts | 1 + arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts | 1 + arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi | 207 ++++++++++++++++++++++ arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 193 -------------------- 5 files changed, 210 insertions(+), 201 deletions(-) create mode 100644 arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts index 8d671111d973..af84fd6c8a81 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts @@ -9,12 +9,11 @@ #include "r9a07g044c2.dtsi" #include "rzg2lc-smarc-som.dtsi" #include "rzg2lc-smarc-pinfunction.dtsi" -#include "rzg2l-smarc.dtsi" +#include "rz-smarc-common.dtsi" / { model = "Renesas SMARC EVK based on r9a07g044c2"; compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044"; - }; &canfd { @@ -75,12 +74,6 @@ status = "disabled"; }; -&scif2 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - &spi1 { /delete-property/ pinctrl-0; /delete-property/ pinctrl-names; diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts index 886d38886d05..bc2af6c92ccd 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts @@ -9,6 +9,7 @@ #include "r9a07g044l2.dtsi" #include "rzg2l-smarc-som.dtsi" #include "rzg2l-smarc-pinfunction.dtsi" +#include "rz-smarc-common.dtsi" #include "rzg2l-smarc.dtsi" / { diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts index 39ef55bfe0c3..49d141db53f7 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts @@ -9,6 +9,7 @@ #include "r9a07g054l2.dtsi" #include "rzg2l-smarc-som.dtsi" #include "rzg2l-smarc-pinfunction.dtsi" +#include "rz-smarc-common.dtsi" #include "rzg2l-smarc.dtsi" / { diff --git a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi new file mode 100644 index 000000000000..588117aafaca --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/{G2L,G2LC,V2L} SMARC EVK common parts + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include +#include + +/* + * SSI-WM8978 + * + * This command is required when Playback/Capture + * + * amixer cset name='Left Input Mixer L2 Switch' on + * amixer cset name='Right Input Mixer R2 Switch' on + * amixer cset name='Headphone Playback Volume' 100 + * amixer cset name='PCM Volume' 100% + * amixer cset name='Input PGA Volume' 25 + * + */ + +/ { + aliases { + serial0 = &scif0; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c3 = &i2c3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + audio_mclock: audio_mclock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <11289600>; + }; + + snd_rzg2l: sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&cpu_dai>; + simple-audio-card,frame-master = <&cpu_dai>; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,widgets = "Microphone", "Microphone Jack"; + simple-audio-card,routing = + "L2", "Mic Bias", + "R2", "Mic Bias", + "Mic Bias", "Microphone Jack"; + + cpu_dai: simple-audio-card,cpu { + sound-dai = <&ssi0>; + }; + + codec_dai: simple-audio-card,codec { + clocks = <&audio_mclock>; + sound-dai = <&wm8978>; + }; + }; + + usb0_vbus_otg: regulator-usb0-vbus-otg { + compatible = "regulator-fixed"; + + regulator-name = "USB0_VBUS_OTG"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vccq_sdhi1: regulator-vccq-sdhi1 { + compatible = "regulator-gpio"; + regulator-name = "SDHI1 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; + }; +}; + +&audio_clk1{ + clock-frequency = <11289600>; +}; + +&audio_clk2{ + clock-frequency = <12288000>; +}; + +&canfd { + pinctrl-0 = <&can0_pins &can1_pins>; + pinctrl-names = "default"; + status = "okay"; + + channel0 { + status = "okay"; + }; + + channel1 { + status = "okay"; + }; +}; + +&ehci0 { + dr_mode = "otg"; + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&hsusb { + dr_mode = "otg"; + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + + status = "okay"; + + wm8978: codec@1a { + compatible = "wlf,wm8978"; + #sound-dai-cells = <0>; + reg = <0x1a>; + }; +}; + +&ohci0 { + dr_mode = "otg"; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&phyrst { + status = "okay"; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdhi1 { + pinctrl-0 = <&sdhi1_pins>; + pinctrl-1 = <&sdhi1_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vccq_sdhi1>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&spi1 { + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&ssi0 { + pinctrl-0 = <&ssi0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&usb2_phy0 { + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + + vbus-supply = <&usb0_vbus_otg>; + status = "okay"; +}; + +&usb2_phy1 { + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index 78034f36156d..33ddfd18bd56 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -8,164 +8,13 @@ #include #include -/* - * SSI-WM8978 - * - * This command is required when Playback/Capture - * - * amixer cset name='Left Input Mixer L2 Switch' on - * amixer cset name='Right Input Mixer R2 Switch' on - * amixer cset name='Headphone Playback Volume' 100 - * amixer cset name='PCM Volume' 100% - * amixer cset name='Input PGA Volume' 25 - * - */ - /* comment the #define statement to disable SCIF2 (SER0) on PMOD1 (CN7) */ #define PMOD1_SER0 1 / { aliases { - serial0 = &scif0; serial1 = &scif2; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c3 = &i2c3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - audio_mclock: audio_mclock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <11289600>; - }; - - snd_rzg2l: sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&cpu_dai>; - simple-audio-card,frame-master = <&cpu_dai>; - simple-audio-card,mclk-fs = <256>; - - simple-audio-card,widgets = "Microphone", "Microphone Jack"; - simple-audio-card,routing = - "L2", "Mic Bias", - "R2", "Mic Bias", - "Mic Bias", "Microphone Jack"; - - cpu_dai: simple-audio-card,cpu { - sound-dai = <&ssi0>; - }; - - codec_dai: simple-audio-card,codec { - clocks = <&audio_mclock>; - sound-dai = <&wm8978>; - }; - }; - - usb0_vbus_otg: regulator-usb0-vbus-otg { - compatible = "regulator-fixed"; - - regulator-name = "USB0_VBUS_OTG"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vccq_sdhi1: regulator-vccq-sdhi1 { - compatible = "regulator-gpio"; - regulator-name = "SDHI1 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; -}; - -&audio_clk1{ - clock-frequency = <11289600>; -}; - -&audio_clk2{ - clock-frequency = <12288000>; -}; - -&canfd { - pinctrl-0 = <&can0_pins &can1_pins>; - pinctrl-names = "default"; - status = "okay"; - - channel0 { - status = "okay"; }; - - channel1 { - status = "okay"; - }; -}; - -&ehci0 { - dr_mode = "otg"; - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&hsusb { - dr_mode = "otg"; - status = "okay"; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&i2c3 { - pinctrl-0 = <&i2c3_pins>; - pinctrl-names = "default"; - clock-frequency = <400000>; - - status = "okay"; - - wm8978: codec@1a { - compatible = "wlf,wm8978"; - #sound-dai-cells = <0>; - reg = <0x1a>; - }; -}; - -&ohci0 { - dr_mode = "otg"; - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&phyrst { - status = "okay"; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - status = "okay"; }; /* @@ -184,45 +33,3 @@ status = "okay"; }; #endif - -&sdhi1 { - pinctrl-0 = <&sdhi1_pins>; - pinctrl-1 = <&sdhi1_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <&vccq_sdhi1>; - bus-width = <4>; - sd-uhs-sdr50; - sd-uhs-sdr104; - status = "okay"; -}; - -&spi1 { - pinctrl-0 = <&spi1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&ssi0 { - pinctrl-0 = <&ssi0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&usb2_phy0 { - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; - - vbus-supply = <&usb0_vbus_otg>; - status = "okay"; -}; - -&usb2_phy1 { - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; -- cgit From 2ed3b5d9540b246d7a1ec98971914ee810b40086 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 3 Feb 2022 17:06:34 +0000 Subject: arm64: dts: renesas: rzg2lc-smarc: Add macros for DIP-Switch settings RZ/G2LC SoM uses DIP-SWitch SW1 for various pin multiplexing functions. This patch describes DIP-SWitch SW1 settings on SoM and adds the corresponding macros for enabling pinmux functionality on RZ/G2LC SMARC EVK. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220203170636.7747-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts | 4 +-- arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 36 +++++++++++++++++++++++ 2 files changed, 37 insertions(+), 3 deletions(-) create mode 100644 arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts index af84fd6c8a81..50abdabc374a 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts @@ -7,9 +7,7 @@ /dts-v1/; #include "r9a07g044c2.dtsi" -#include "rzg2lc-smarc-som.dtsi" -#include "rzg2lc-smarc-pinfunction.dtsi" -#include "rz-smarc-common.dtsi" +#include "rzg2lc-smarc.dtsi" / { model = "Renesas SMARC EVK based on r9a07g044c2"; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi new file mode 100644 index 000000000000..ca5ca7ce6692 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2LC SMARC EVK parts + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include +#include + +/* + * DIP-Switch SW1 setting on SoM + * 1 : High; 0: Low + * SW1-2 : SW_SD0_DEV_SEL (1: eMMC; 0: uSD) + * SW1-3 : SW_SCIF_CAN (1: CAN1; 0: SCIF1) + * SW1-4 : SW_RSPI_CAN (1: CAN1; 0: RSPI1) + * SW1-5 : SW_I2S0_I2S1 (1: I2S2 (HDMI audio); 0: I2S0) + * Please change below macros according to SW1 setting + */ + +#define SW_SCIF_CAN 0 +#if (SW_SCIF_CAN) +/* Due to HW routing, SW_RSPI_CAN is always 0 when SW_SCIF_CAN is set to 1 */ +#define SW_RSPI_CAN 0 +#else +/* Please set SW_RSPI_CAN. Default value is 1 */ +#define SW_RSPI_CAN 1 +#endif + +#if (SW_SCIF_CAN & SW_RSPI_CAN) +#error "Can not set 1 to both SW_SCIF_CAN and SW_RSPI_CAN due to HW routing" +#endif + +#include "rzg2lc-smarc-som.dtsi" +#include "rzg2lc-smarc-pinfunction.dtsi" +#include "rz-smarc-common.dtsi" -- cgit From fa00d6dc19283bee13f0390546f741293f6d2d9a Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 3 Feb 2022 17:06:35 +0000 Subject: arm64: dts: renesas: rzg2lc-smarc: Enable SCIF1 on carrier board SCIF1 interface is available on PMOD1 connector (CN7) on carrier board. This patch adds pinmux and scif1 node to carrier board dtsi file for RZ/G2LC SMARC EVK. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220203170636.7747-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 7 ++++++ arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 26 ++++++++++++++++++++++ 2 files changed, 33 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi index 1032f6563515..ec9e08ec0822 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi @@ -17,6 +17,13 @@ ; /* RxD */ }; + scif1_pins: scif1 { + pinmux = , /* TxD */ + , /* RxD */ + , /* CTS# */ + ; /* RTS# */ + }; + sd1-pwr-en-hog { gpio-hog; gpios = ; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi index ca5ca7ce6692..1b59ef376296 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -34,3 +34,29 @@ #include "rzg2lc-smarc-som.dtsi" #include "rzg2lc-smarc-pinfunction.dtsi" #include "rz-smarc-common.dtsi" + +/* comment the #define statement to disable SCIF1 (SER0) on PMOD1 (CN7) */ +#define PMOD1_SER0 1 + +/ { + aliases { + serial1 = &scif1; + }; +}; + +/* + * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board + * SW1 should be at position 2->3 so that SER0_CTS# line is activated + * SW2 should be at position 2->3 so that SER0_TX line is activated + * SW3 should be at position 2->3 so that SER0_RX line is activated + * SW4 should be at position 2->3 so that SER0_RTS# line is activated + */ +#if (!SW_SCIF_CAN && PMOD1_SER0) +&scif1 { + pinctrl-0 = <&scif1_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; +#endif -- cgit From 46da632734a5979090ef588d9da40367581fd400 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 3 Feb 2022 17:06:36 +0000 Subject: arm64: dts: renesas: rzg2lc-smarc: Enable CANFD channel 1 On RZ/G2LC SMARC EVK, CAN0 is not populated. CAN1 is multiplexed with SCIF1 using SW1[3] or RSPI using SW1[4]. This patch adds support for the CAN1 interface on RZ/G2LC SMARC EVK. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220203170636.7747-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts | 6 ------ .../boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 23 ++++++++++++++++++++++ arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 13 ++++++++++++ 3 files changed, 36 insertions(+), 6 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts index 50abdabc374a..5a5cea82a5d9 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts @@ -14,12 +14,6 @@ compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044"; }; -&canfd { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - &ehci0 { /delete-property/ pinctrl-0; /delete-property/ pinctrl-names; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi index ec9e08ec0822..bff56d696936 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi @@ -17,6 +17,14 @@ ; /* RxD */ }; +#if SW_SCIF_CAN + /* SW8 should be at position 2->1 */ + can1_pins: can1 { + pinmux = , /* TxD */ + ; /* RxD */ + }; +#endif + scif1_pins: scif1 { pinmux = , /* TxD */ , /* RxD */ @@ -24,6 +32,21 @@ ; /* RTS# */ }; +#if SW_RSPI_CAN + /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */ + can1-stb { + gpio-hog; + gpios = ; + output-low; + line-name = "can1_stb"; + }; + + can1_pins: can1 { + pinmux = , /* TxD */ + ; /* RxD */ + }; +#endif + sd1-pwr-en-hog { gpio-hog; gpios = ; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi index 1b59ef376296..28f21c287ba3 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -44,6 +44,19 @@ }; }; +#if (SW_SCIF_CAN || SW_RSPI_CAN) +&canfd { + pinctrl-0 = <&can1_pins>; + /delete-node/ channel@0; +}; +#else +&canfd { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; +#endif + /* * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board * SW1 should be at position 2->3 so that SER0_CTS# line is activated -- cgit From 5c65ad12785205d5c57bd92e19d0296f93c19e33 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 4 Feb 2022 14:31:32 +0000 Subject: arm64: dts: renesas: rzg2lc-smarc: Use SW_SD0_DEV_SEL macro for eMMC/SDHI device selection This patch replaces EMMC/SDHI macros with SW_SD0_DEV_SEL DIP-Switch macro for eMMC/SDHI device selection. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220204143132.3608-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi | 14 ++------------ arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 2 ++ 2 files changed, 4 insertions(+), 12 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi index 6ebda3724f2c..90cb7ec45751 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi @@ -8,16 +8,6 @@ #include #include -/* SW1[2] should be at OFF position to enable 64 GB eMMC */ -#define EMMC 1 - -/* - * To enable uSD card on CN3, - * SW1[2] should be at ON position. - * Disable eMMC by setting "#define EMMC 0" above. - */ -#define SDHI (!EMMC) - / { aliases { ethernet0 = ð0; @@ -185,7 +175,7 @@ }; }; -#if SDHI +#if (!SW_SD0_DEV_SEL) &sdhi0 { pinctrl-0 = <&sdhi0_pins>; pinctrl-1 = <&sdhi0_pins_uhs>; @@ -200,7 +190,7 @@ }; #endif -#if EMMC +#if SW_SD0_DEV_SEL &sdhi0 { pinctrl-0 = <&sdhi0_emmc_pins>; pinctrl-1 = <&sdhi0_emmc_pins>; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi index 28f21c287ba3..df7631fe5fac 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -18,6 +18,8 @@ * Please change below macros according to SW1 setting */ +#define SW_SD0_DEV_SEL 1 + #define SW_SCIF_CAN 0 #if (SW_SCIF_CAN) /* Due to HW routing, SW_RSPI_CAN is always 0 when SW_SCIF_CAN is set to 1 */ -- cgit From 0601fbed40594e620e2f335d1945e5a102dca6b3 Mon Sep 17 00:00:00 2001 From: Michael Saunders Date: Mon, 7 Feb 2022 17:06:19 +0930 Subject: arm64: dts: rockchip: enable the mali GPU on rk3399-firefly The Firefly RK3399 device tree had the GPU status set to disabled as per the default from the rk3399.dtsi. This patch sets the status in the firefly dts to enable it for use. Tested successfully on a 2GB Firefly RK3399 board. Signed-off-by: Michael Saunders Link: https://lore.kernel.org/r/20220207073617.7386-1-mick.saunders@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-firefly.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts index c4dd2a6b4836..65d659d56041 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts @@ -298,6 +298,11 @@ status = "okay"; }; +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + &hdmi { ddc-i2c-bus = <&i2c3>; pinctrl-names = "default"; -- cgit From f901aaadaa2ac758521c82e38154fe2a58f18db2 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Sun, 23 Jan 2022 14:51:16 +0100 Subject: arm64: dts: rockchip: Add Bananapi R2 Pro This patch adds Devicetree for Bananapi R2 Pro based on RK3568. Add uart/sd/emmc/i2c/rk809/tsadc nodes for basic function. Gmac0 is directly connected to wan-port so usable without additional driver. On gmac1 there is a switch (rtl8367rb) connected which have not yet a driver in mainline. Patch also prepares nodes for GPIO header. Co-developed-by: Peter Geis Signed-off-by: Peter Geis Signed-off-by: Frank Wunderlich Link: https://lore.kernel.org/r/20220123135116.136846-3-linux@fw-web.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 457 +++++++++++++++++++++ 2 files changed, 458 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 479906f3ad7b..70007b370d87 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -58,3 +58,4 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts new file mode 100644 index 000000000000..a01886b467ed --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts @@ -0,0 +1,457 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Author: Frank Wunderlich + * + */ + +/dts-v1/; +#include +#include +#include +#include "rk3568.dtsi" + +/ { + model = "Bananapi-R2 Pro (RK3568) DDR4 Board"; + compatible = "rockchip,rk3568-bpi-r2pro", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; + mmc0 = &sdmmc0; + mmc1 = &sdhci; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&blue_led_pin &green_led_pin>; + + blue_led: led-0 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; + }; + + green_led: led-1 { + color = ; + default-state = "on"; + function = LED_FUNCTION_POWER; + gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + }; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; +}; + +&gmac0 { + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; + clock_in_out = "input"; + phy-handle = <&rgmii_phy0>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + tx_delay = <0x3c>; + rx_delay = <0x2f>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + #clock-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + wakeup-source; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c5 { + /* pin 3 (SDA) + 4 (SCL) of header con2 */ + status = "disabled"; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&pinctrl { + leds { + blue_led_pin: blue-led-pin { + rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + green_led_pin: green-led-pin { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pwm8 { + /* fan 5v - gnd - pwm */ + status = "okay"; +}; + +&pwm10 { + /* pin 7 of header con2 */ + status = "disabled"; +}; + +&pwm11 { + /* pin 15 of header con2 */ + status = "disabled"; +}; + +&pwm12 { + /* pin 21 of header con2 */ + /* shared with uart9 + spi3 */ + pinctrl-0 = <&pwm12m1_pins>; + status = "disabled"; +}; + +&pwm13 { + /* pin 24 of header con2 */ + /* shared with uart9 */ + pinctrl-0 = <&pwm13m1_pins>; + status = "disabled"; +}; + +&pwm14 { + /* pin 23 of header con2 */ + /* shared with spi3 */ + pinctrl-0 = <&pwm14m1_pins>; + status = "disabled"; +}; + +&pwm15 { + /* pin 19 of header con2 */ + /* shared with spi3 */ + pinctrl-0 = <&pwm15m1_pins>; + status = "disabled"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&spi3 { + /* pin 19 (MO) + 21 (MI) + 23 (CK) of header con2 */ + /* shared with pwm12/14/15 and uart9 */ + pinctrl-0 = <&spi3m1_pins>; + status = "disabled"; +}; + +&tsadc { + status = "okay"; +}; + +&uart0 { + /* pin 8 (TX) + 10 (RX) (RTS:16, CTS:18) of header con2 */ + status = "disabled"; +}; + +&uart2 { + /* debug-uart */ + status = "okay"; +}; + +&uart7 { + /* pin 11 (TX) + 13 (RX) of header con2 */ + pinctrl-0 = <&uart7m1_xfer>; + status = "disabled"; +}; + +&uart9 { + /* pin 21 (TX) + 24 (RX) of header con2 */ + /* shared with pwm13 and pwm12/spi3 */ + pinctrl-0 = <&uart9m1_xfer>; + status = "disabled"; +}; -- cgit From ad14de0638903b530cc6f45e5c19027177cf983c Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Mon, 31 Jan 2022 16:34:57 +0100 Subject: arm64: dts: rockchip: add the i2s3_2ch node to rk356x Add the two-channel I2S controller I2S3_2CH to the rk356x device tree. Signed-off-by: Michael Riesch Link: https://lore.kernel.org/r/20220131153457.391460-1-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 8ee2fab676f4..00fcf1c19682 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -705,6 +705,22 @@ status = "disabled"; }; + i2s3_2ch: i2s@fe430000 { + compatible = "rockchip,rk3568-i2s-tdm"; + reg = <0x0 0xfe430000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>, + <&cru HCLK_I2S3_2CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + dmas = <&dmac1 6>, <&dmac1 7>; + dma-names = "tx", "rx"; + resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>; + reset-names = "tx-m", "rx-m"; + rockchip,grf = <&grf>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + dmac0: dmac@fe530000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xfe530000 0x0 0x4000>; -- cgit From 78f7186095db5a64009d44c18843a03dbc72d896 Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Thu, 27 Jan 2022 20:04:55 +0100 Subject: arm64: dts: rockchip: rename and sort the rk356x usb2 phy handles All nodes and handles related to USB have the prefix usb or usb2, whereas the phy handles are prefixed with u2phy. Rename for consistency reasons and to facilitate sorting. This patch also updates the handles in the only board file that uses them (rk3566-quartz64-a.dts). Signed-off-by: Michael Riesch Link: https://lore.kernel.org/r/20220127190456.2195527-1-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 18 +++++++++--------- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 20 ++++++++++---------- 2 files changed, 19 insertions(+), 19 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts index 8332627f483b..868ddac96433 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts @@ -653,32 +653,32 @@ status = "okay"; }; -&u2phy1_host { - phy-supply = <&vcc5v0_usb20_host>; +&usb_host0_ehci { status = "okay"; }; -&u2phy1_otg { - phy-supply = <&vcc5v0_usb20_host>; +&usb_host0_ohci { status = "okay"; }; -&u2phy1 { +&usb_host1_ehci { status = "okay"; }; -&usb_host0_ehci { +&usb_host1_ohci { status = "okay"; }; -&usb_host0_ohci { +&usb2phy1 { status = "okay"; }; -&usb_host1_ehci { +&usb2phy1_host { + phy-supply = <&vcc5v0_usb20_host>; status = "okay"; }; -&usb_host1_ohci { +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb20_host>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 00fcf1c19682..ff1689283996 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -214,7 +214,7 @@ interrupts = ; clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, <&cru PCLK_USB>; - phys = <&u2phy1_otg>; + phys = <&usb2phy1_otg>; phy-names = "usb"; status = "disabled"; }; @@ -225,7 +225,7 @@ interrupts = ; clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, <&cru PCLK_USB>; - phys = <&u2phy1_otg>; + phys = <&usb2phy1_otg>; phy-names = "usb"; status = "disabled"; }; @@ -236,7 +236,7 @@ interrupts = ; clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, <&cru PCLK_USB>; - phys = <&u2phy1_host>; + phys = <&usb2phy1_host>; phy-names = "usb"; status = "disabled"; }; @@ -247,7 +247,7 @@ interrupts = ; clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, <&cru PCLK_USB>; - phys = <&u2phy1_host>; + phys = <&usb2phy1_host>; phy-names = "usb"; status = "disabled"; }; @@ -1211,7 +1211,7 @@ status = "disabled"; }; - u2phy0: usb2phy@fe8a0000 { + usb2phy0: usb2phy@fe8a0000 { compatible = "rockchip,rk3568-usb2phy"; reg = <0x0 0xfe8a0000 0x0 0x10000>; clocks = <&pmucru CLK_USBPHY0_REF>; @@ -1222,18 +1222,18 @@ #clock-cells = <0>; status = "disabled"; - u2phy0_host: host-port { + usb2phy0_host: host-port { #phy-cells = <0>; status = "disabled"; }; - u2phy0_otg: otg-port { + usb2phy0_otg: otg-port { #phy-cells = <0>; status = "disabled"; }; }; - u2phy1: usb2phy@fe8b0000 { + usb2phy1: usb2phy@fe8b0000 { compatible = "rockchip,rk3568-usb2phy"; reg = <0x0 0xfe8b0000 0x0 0x10000>; clocks = <&pmucru CLK_USBPHY1_REF>; @@ -1244,12 +1244,12 @@ #clock-cells = <0>; status = "disabled"; - u2phy1_host: host-port { + usb2phy1_host: host-port { #phy-cells = <0>; status = "disabled"; }; - u2phy1_otg: otg-port { + usb2phy1_otg: otg-port { #phy-cells = <0>; status = "disabled"; }; -- cgit From e49e24d7a85ba553d3d8868eb2b63846e872e853 Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Thu, 27 Jan 2022 20:04:56 +0100 Subject: arm64: dts: rockchip: add usb2 support to rk3568-evb1-v10 Activate the USB2 controller and phy nodes in the device tree of the RK3568 EVB1. Signed-off-by: Michael Riesch Link: https://lore.kernel.org/r/20220127190456.2195527-2-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts | 58 ++++++++++++++++++++++++ 1 file changed, 58 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts index d8c20a23e856..d8a4f7a9f562 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts @@ -53,6 +53,28 @@ vin-supply = <&dc_12v>; }; + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb_host: vcc5v0-usb-host { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_host_en>; + regulator-name = "vcc5v0_usb_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + vcc3v3_lcd0_n: vcc3v3-lcd0-n { compatible = "regulator-fixed"; regulator-name = "vcc3v3_lcd0_n"; @@ -392,6 +414,12 @@ rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + usb { + vcc5v0_usb_host_en: vcc5v0_usb_host_en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &pmu_io_domains { @@ -437,3 +465,33 @@ &uart2 { status = "okay"; }; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; -- cgit From a28106a2734f602d852a9269526f5880df352b51 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 7 Feb 2022 22:16:05 -0600 Subject: arm64: dts: qcom: c630: Add backlight controller The Lenovo Yoga C630 uses the PWM controller in the TI SN65DSI86 bridge chip to provide a signal for the backlight control and has TLMM GPIO 11 attached to some regulator that drives the backlight. Unfortunately the regulator attached to this gpio is also powering the camera, so turning off backlight result in the detachment of the camera as well. Signed-off-by: Bjorn Andersson Tested-by: Steev Klimaszewski Link: https://lore.kernel.org/r/20220208041606.144039-1-bjorn.andersson@linaro.org --- arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index 58845a14805f..55fb7302245b 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -59,6 +59,7 @@ panel { compatible = "boe,nv133fhm-n61"; no-hpd; + backlight = <&backlight>; ports { port { @@ -98,6 +99,12 @@ clock-frequency = <19200000>; }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&sn65dsi86 1000000>; + enable-gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>; + }; }; &adsp_pas { @@ -419,6 +426,7 @@ clock-names = "refclk"; no-hpd; + #pwm-cells = <1>; ports { #address-cells = <1>; -- cgit From ff899133fdae9c4d63a59e544c821b1ee438dbd6 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 7 Feb 2022 22:16:06 -0600 Subject: arm64: dts: qcom: c630: Move panel to aux-bus With the newly introduced aux-bus under the TI SN65DSI86 the panel node should be described as a child instead of a standalone node, move it there. Signed-off-by: Bjorn Andersson Tested-by: Steev Klimaszewski Link: https://lore.kernel.org/r/20220208041606.144039-2-bjorn.andersson@linaro.org --- .../boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 27 +++++++++++----------- 1 file changed, 13 insertions(+), 14 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index 55fb7302245b..fd1261901ab5 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -56,20 +56,6 @@ }; }; - panel { - compatible = "boe,nv133fhm-n61"; - no-hpd; - backlight = <&backlight>; - - ports { - port { - panel_in_edp: endpoint { - remote-endpoint = <&sn65dsi86_out>; - }; - }; - }; - }; - /* Reserved memory changes for IPA */ reserved-memory { wlan_msa_mem: memory@8c400000 { @@ -446,6 +432,19 @@ }; }; }; + + aux-bus { + panel: panel { + compatible = "boe,nv133fhm-n61"; + backlight = <&backlight>; + + port { + panel_in_edp: endpoint { + remote-endpoint = <&sn65dsi86_out>; + }; + }; + }; + }; }; }; -- cgit From 1c0bd03532507afb9c185eee376306477d44a053 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 27 Dec 2021 14:35:52 +0100 Subject: arm64: dts: stratix10: add board compatible for SoCFPGA DK The Altera SoCFPGA Stratix 10 SoC Development Kit is a board with Stratix 10, so it needs its own compatible. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 1 + arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts | 1 + 2 files changed, 2 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts index 46e558ab7729..12392292c62c 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts @@ -7,6 +7,7 @@ / { model = "SoCFPGA Stratix 10 SoCDK"; + compatible = "altr,socfpga-stratix10-socdk", "altr,socfpga-stratix10"; aliases { serial0 = &uart0; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts index bbc3db42d6e8..2d53a06deab5 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts @@ -7,6 +7,7 @@ / { model = "SoCFPGA Stratix 10 SoCDK"; + compatible = "altr,socfpga-stratix10-socdk", "altr,socfpga-stratix10"; aliases { serial0 = &uart0; -- cgit From 79f1db278f82301b940e91d1b47da3b71b0b3d68 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 27 Dec 2021 14:35:53 +0100 Subject: arm64: dts: stratix10: move ARM timer out of SoC node The ARM timer is usually considered not part of SoC node, just like other ARM designed blocks (PMU, PSCI). This fixes dtbs_check warning: arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dt.yaml: soc: timer: {'compatible': ['arm,armv8-timer'], 'interrupts': [[1, 13, 3848], [1, 14, 3848], [1, 11, 3848], [1, 10, 3848]]} should not be valid under {'type': 'object'} From schema: dtschema/schemas/simple-bus.yaml Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 3ec301bd08a9..505542b75a36 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -77,6 +77,16 @@ method = "smc"; }; + /* Local timer */ + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + interrupt-parent = <&intc>; + }; + intc: interrupt-controller@fffc1000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; @@ -406,15 +416,6 @@ reg = <0xffd12000 0x228>; }; - /* Local timer */ - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - }; - timer0: timer0@ffc03000 { compatible = "snps,dw-apb-timer"; interrupts = <0 113 4>; -- cgit From 8b794ab20780b09ec0384c03ef02169fa35d40dd Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 27 Dec 2021 14:35:54 +0100 Subject: arm64: dts: stratix10: align mmc node names with dtschema The Synopsys DW MSHC bindings require node name to be 'mmc': dwmmc0@ff808000: $nodename:0: 'dwmmc0@ff808000' does not match '^mmc(@.*)?$' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 505542b75a36..4124021768b1 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -296,7 +296,7 @@ status = "disabled"; }; - mmc: dwmmc0@ff808000 { + mmc: mmc@ff808000 { #address-cells = <1>; #size-cells = <0>; compatible = "altr,socfpga-dw-mshc"; -- cgit From 327a96a1cb26b8674aac9863b016f6110fb44fa0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 27 Dec 2021 14:35:55 +0100 Subject: arm64: dts: stratix10: align regulator node names with dtschema The devicetree specification requires that node name should be generic. The dtschema complains if name does not match pattern, so make the 0.33 V regulator node name more generic. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 2 +- arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts index 12392292c62c..5159cd5771dc 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts @@ -44,7 +44,7 @@ reg = <0 0 0 0>; }; - ref_033v: 033-v-ref { + ref_033v: regulator-v-ref { compatible = "regulator-fixed"; regulator-name = "0.33V"; regulator-min-microvolt = <330000>; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts index 2d53a06deab5..0ab676c639a1 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts @@ -44,7 +44,7 @@ reg = <0 0 0 0>; }; - ref_033v: 033-v-ref { + ref_033v: regulator-v-ref { compatible = "regulator-fixed"; regulator-name = "0.33V"; regulator-min-microvolt = <330000>; -- cgit From 50ae688a08a77260249cb5022a441b8a87903405 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 27 Dec 2021 14:35:56 +0100 Subject: arm64: dts: agilex: add board compatible for SoCFPGA DK The Intel SoCFPGA Agilex 10 SoC Development Kit is a board with Agilex, so it needs its own compatible. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts | 1 + arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts | 1 + 2 files changed, 2 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts index 0f7a0ba344be..ea37ba7ccff9 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts @@ -6,6 +6,7 @@ / { model = "SoCFPGA Agilex SoCDK"; + compatible = "intel,socfpga-agilex-socdk", "intel,socfpga-agilex"; aliases { serial0 = &uart0; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts index 57f83481f551..51f83f96ec65 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts @@ -6,6 +6,7 @@ / { model = "SoCFPGA Agilex SoCDK"; + compatible = "intel,socfpga-agilex-socdk", "intel,socfpga-agilex"; aliases { serial0 = &uart0; -- cgit From fae3aa6c82f588214e3ffaf4408dd99d4894048b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 27 Dec 2021 14:35:57 +0100 Subject: arm64: dts: agilex: add board compatible for N5X DK The Intel SoCFPGA N5X SoC Development Kit is a board with Agilex, so it needs its own compatible. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts index f3c1310dae0a..5609d8df6729 100644 --- a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts @@ -6,6 +6,7 @@ / { model = "eASIC N5X SoCDK"; + compatible = "intel,n5x-socdk", "intel,socfpga-agilex"; aliases { serial0 = &uart0; -- cgit From 9ffc4e03dce02be1275b5577275426a48696502d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 27 Dec 2021 14:35:58 +0100 Subject: arm64: dts: agilex: align mmc node names with dtschema The Synopsys DW MSHC bindings require node name to be 'mmc': dwmmc0@ff808000: $nodename:0: 'dwmmc0@ff808000' does not match '^mmc(@.*)?$' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index 0dd2d2ee765a..63dd4e69c962 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -300,7 +300,7 @@ status = "disabled"; }; - mmc: dwmmc0@ff808000 { + mmc: mmc@ff808000 { #address-cells = <1>; #size-cells = <0>; compatible = "altr,socfpga-dw-mshc"; -- cgit From 814927744e4e401d938ea8dc036cb048721ac32b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 26 Jan 2022 18:41:57 +0100 Subject: arm64: dts: intel: socfpga_agilex_socdk: align LED node names with dtschema Align the LED node names with dtschema to silence dtbs_check warnings like: leds: 'hps0', 'hps1', 'hps2' do not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts index ea37ba7ccff9..26cd3c121757 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts @@ -21,17 +21,17 @@ leds { compatible = "gpio-leds"; - hps0 { + led0 { label = "hps_led0"; gpios = <&portb 20 GPIO_ACTIVE_HIGH>; }; - hps1 { + led1 { label = "hps_led1"; gpios = <&portb 19 GPIO_ACTIVE_HIGH>; }; - hps2 { + led2 { label = "hps_led2"; gpios = <&portb 21 GPIO_ACTIVE_HIGH>; }; -- cgit From 180be1b7a387af184d9eabd14fde82cd932219c3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 29 Jan 2022 18:55:34 +0100 Subject: arm64: dts: stratix10: align pl330 node name with dtschema Fixes dtbs_check warnings like: pdma@ffda0000: $nodename:0: 'pdma@ffda0000' does not match '^dma-controller(@.*)?$' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 4124021768b1..da032a6f71da 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -333,7 +333,7 @@ reg = <0xffe00000 0x100000>; }; - pdma: pdma@ffda0000 { + pdma: dma-controller@ffda0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xffda0000 0x1000>; interrupts = <0 81 4>, -- cgit From e3e4ffe1139fffbe10c2ee060aa7fa438c9baf47 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 29 Jan 2022 18:55:35 +0100 Subject: arm64: dts: agilex: align pl330 node name with dtschema Fixes dtbs_check warnings like: pdma@ffda0000: $nodename:0: 'pdma@ffda0000' does not match '^dma-controller(@.*)?$' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index 63dd4e69c962..1f4618c1062e 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -337,7 +337,7 @@ reg = <0xffe00000 0x40000>; }; - pdma: pdma@ffda0000 { + pdma: dma-controller@ffda0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xffda0000 0x1000>; interrupts = , -- cgit From 59892de947f0ca1d65426f7a6c6e258863fa65d7 Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Tue, 8 Feb 2022 21:05:24 +0530 Subject: arm64: dts: qcom: ipq8074: enable the GICv2m support GIC used in the IPQ8074 SoCs has one instance of the GICv2m extension, which supports upto 32 MSI interrupts. Lets add support for the same. Signed-off-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1644334525-11577-2-git-send-email-quic_kathirav@quicinc.com --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 27624f5a56ba..642f9e71dbcf 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -634,9 +634,18 @@ intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; + #address-cells = <1>; + #size-cells = <1>; interrupt-controller; #interrupt-cells = <0x3>; reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; + ranges = <0 0xb00a000 0xffd>; + + v2m@0 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0xffd>; + }; }; timer { -- cgit From 3d44861d006b18649306cbade242c865e9068b6e Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Tue, 8 Feb 2022 21:05:25 +0530 Subject: arm64: dts: qcom: ipq6018: enable the GICv2m support GIC used in the IPQ6018 SoCs has one instance of the GICv2m extension, which supports upto 32 MSI interrupts. Lets add support for the same. Signed-off-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1644334525-11577-3-git-send-email-quic_kathirav@quicinc.com --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index aa8068193ccb..f8b6d6263c61 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -373,6 +373,8 @@ intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; + #address-cells = <2>; + #size-cells = <2>; interrupt-controller; #interrupt-cells = <0x3>; reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/ @@ -380,6 +382,13 @@ <0x0 0x0b001000 0x0 0x1000>, /*GICH*/ <0x0 0x0b004000 0x0 0x1000>; /*GICV*/ interrupts = ; + ranges = <0 0 0 0xb00a000 0 0xffd>; + + v2m@0 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0x0 0x0 0xffd>; + }; }; pcie_phy: phy@84000 { -- cgit From 3431a7f5bbf276eeefd0693883e3754b08ffc0fe Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Thu, 3 Feb 2022 07:25:32 +0000 Subject: arm64: dts: qcom: msm8996-mtp: Add msm8996 compatible Add qcom,msm8996 compatible to match DT schema. Signed-off-by: Yassine Oudjana Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220203072226.51482-3-y.oudjana@protonmail.com --- arch/arm64/boot/dts/qcom/msm8996-mtp.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/msm8996-mtp.dts b/arch/arm64/boot/dts/qcom/msm8996-mtp.dts index 7d9fc35bc7a0..6a1699a96c99 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-mtp.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-mtp.dts @@ -9,7 +9,7 @@ / { model = "Qualcomm Technologies, Inc. MSM 8996 MTP"; - compatible = "qcom,msm8996-mtp"; + compatible = "qcom,msm8996-mtp", "qcom,msm8996"; aliases { serial0 = &blsp2_uart2; -- cgit From f55dda2157313d65662c1e51e9a4b1cc1318511f Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Thu, 3 Feb 2022 07:26:24 +0000 Subject: arm64: dts: qcom: msm8996: Rename cluster OPP tables Rename cluster OPP table node names to match the nodename pattern defined in the opp-v2-base DT schema. Signed-off-by: Yassine Oudjana Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220203072226.51482-6-y.oudjana@protonmail.com --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 5646195ba0a1..c85825ea1623 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -134,7 +134,7 @@ }; }; - cluster0_opp: opp_table0 { + cluster0_opp: opp-table-cluster0 { compatible = "operating-points-v2-kryo-cpu"; nvmem-cells = <&speedbin_efuse>; opp-shared; @@ -222,7 +222,7 @@ }; }; - cluster1_opp: opp_table1 { + cluster1_opp: opp-table-cluster1 { compatible = "operating-points-v2-kryo-cpu"; nvmem-cells = <&speedbin_efuse>; opp-shared; -- cgit From b7072cc5704d0b8a76a41bf60eb5add07aa2b949 Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Thu, 3 Feb 2022 07:26:44 +0000 Subject: arm64: dts: qcom: qcs404: Rename CPU and CPR OPP tables Rename CPU and CPR OPP table node names to match the nodename pattern defined in the opp-v2-base DT schema. Signed-off-by: Yassine Oudjana Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220203072226.51482-7-y.oudjana@protonmail.com --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 6db753b49326..3f06f7cd3cf2 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -110,7 +110,7 @@ }; }; - cpu_opp_table: cpu-opp-table { + cpu_opp_table: opp-table-cpu { compatible = "operating-points-v2-kryo-cpu"; opp-shared; @@ -128,7 +128,7 @@ }; }; - cpr_opp_table: cpr-opp-table { + cpr_opp_table: opp-table-cpr { compatible = "operating-points-v2-qcom-level"; cpr_opp1: opp1 { -- cgit From aa2d0bf04a3c976f5f91ce56915d45e7f8459885 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 3 Feb 2022 05:59:36 +0530 Subject: arm64: dts: qcom: sm8450: add interconnect nodes And the various interconnect nodes found in SM8450 SoC and use it for UFS controller. Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220203002936.3009402-1-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 85 ++++++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index a2ed8ed9929d..eccbfeea943b 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include / { @@ -251,6 +252,18 @@ }; }; + clk_virt: interconnect@0 { + compatible = "qcom,sm8450-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect@1 { + compatible = "qcom,sm8450-mc-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + memory@a0000000 { device_type = "memory"; /* We expect the bootloader to fill in the size */ @@ -737,6 +750,54 @@ }; }; + config_noc: interconnect@1500000 { + compatible = "qcom,sm8450-config-noc"; + reg = <0 0x01500000 0 0x1c000>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1680000 { + compatible = "qcom,sm8450-system-noc"; + reg = <0 0x01680000 0 0x1e200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + pcie_noc: interconnect@16c0000 { + compatible = "qcom,sm8450-pcie-anoc"; + reg = <0 0x016c0000 0 0xe280>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,sm8450-aggre1-noc"; + reg = <0 0x016e0000 0 0x1c080>; + #interconnect-cells = <2>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + compatible = "qcom,sm8450-aggre2-noc"; + reg = <0 0x01700000 0 0x31080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&rpmhcc RPMH_IPA_CLK>; + }; + + mmss_noc: interconnect@1740000 { + compatible = "qcom,sm8450-mmss-noc"; + reg = <0 0x01740000 0 0x1f080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>; @@ -1285,6 +1346,13 @@ #freq-domain-cells = <1>; }; + gem_noc: interconnect@19100000 { + compatible = "qcom,sm8450-gem-noc"; + reg = <0 0x19100000 0 0xbb800>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sm8450-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; @@ -1301,6 +1369,9 @@ iommus = <&apps_smmu 0xe0 0x0>; + interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>; + interconnect-names = "ufs-ddr", "cpu-ufs"; clock-names = "core_clk", "bus_aggr_clk", @@ -1399,6 +1470,20 @@ phy-names = "usb2-phy", "usb3-phy"; }; }; + + nsp_noc: interconnect@320c0000 { + compatible = "qcom,sm8450-nsp-noc"; + reg = <0 0x320c0000 0 0x10000>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + lpass_ag_noc: interconnect@3c40000 { + compatible = "qcom,sm8450-lpass-ag-noc"; + reg = <0 0x3c40000 0 0x17200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; }; timer { -- cgit From 555ab09c78968e7c5b7172bf7237093dfac7aeaf Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Wed, 2 Feb 2022 22:05:08 +0530 Subject: arm64: dts: qcom: ipq8074: drop the clock-frequency property Drop the clock-frequency property from the MMIO timer node, since it is already configured by the bootloader. Signed-off-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1643819709-5410-2-git-send-email-quic_kathirav@quicinc.com --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 642f9e71dbcf..d80b1cefab10 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -670,7 +670,6 @@ ranges; compatible = "arm,armv7-timer-mem"; reg = <0x0b120000 0x1000>; - clock-frequency = <19200000>; frame@b120000 { frame-number = <0>; -- cgit From 01b8c4aff332ecc13fbafc16550e621ba969c167 Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Wed, 2 Feb 2022 22:05:09 +0530 Subject: arm64: dts: qcom: ipq6018: drop the clock-frequency property clock-frequency for IPQ6018 SoCs should be 24MHz, not 19.2MHz. Rather than correcting it, drop the property itself since its already configured by the bootloader. Signed-off-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1643819709-5410-3-git-send-email-quic_kathirav@quicinc.com --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index f8b6d6263c61..4e7efa97724b 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -530,7 +530,6 @@ ranges; compatible = "arm,armv7-timer-mem"; reg = <0x0 0x0b120000 0x0 0x1000>; - clock-frequency = <19200000>; frame@b120000 { frame-number = <0>; -- cgit From 1dc3e50eb68031bc8fc56829c7ac46c89dfbe237 Mon Sep 17 00:00:00 2001 From: Sai Prakash Ranjan Date: Fri, 28 Jan 2022 13:17:16 +0530 Subject: arm64: dts: qcom: sm8450: Add LLCC/system-cache-controller node Add a DT node for Last level cache (aka. system cache) controller which provides control over the last level cache present on SM8450 SoC. Signed-off-by: Sai Prakash Ranjan Tested-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/7995d003b77d5e066658af5b2cfa22ccb40b6cf7.1643355594.git.quic_saipraka@quicinc.com --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index eccbfeea943b..0cd5af8c03bd 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1353,6 +1353,13 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + system-cache-controller@19200000 { + compatible = "qcom,sm8450-llcc"; + reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + interrupts = ; + }; + ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sm8450-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; -- cgit From cfc5078432ca66dec56dadcaf8fb22d09f0c78dc Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Thu, 2 Dec 2021 16:02:34 +0800 Subject: arm64: dts: imx8mm: Add the pcie phy support Add the PCIe PHY support on iMX8MM platforms. Signed-off-by: Richard Zhu Tested-by: Marcel Ziswiler Reviewed-by: Tim Harvey Tested-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index f77f90ed416f..ef6a383a05d6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1211,6 +1211,19 @@ reg = <0x32e50200 0x200>; }; + pcie_phy: pcie-phy@32f00000 { + compatible = "fsl,imx8mm-pcie-phy"; + reg = <0x32f00000 0x10000>; + clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; + clock-names = "ref"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; + assigned-clock-rates = <100000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>; + resets = <&src IMX8MQ_RESET_PCIEPHY>; + reset-names = "pciephy"; + #phy-cells = <0>; + status = "disabled"; + }; }; dma_apbh: dma-controller@33000000 { -- cgit From aaeba6a8e226bf7fa1e3547f33c1577665c4d874 Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Thu, 2 Dec 2021 16:02:36 +0800 Subject: arm64: dts: imx8mm: Add the pcie support Add the PCIe support on i.MX8MM platforms. Signed-off-by: Richard Zhu Tested-by: Marcel Ziswiler Reviewed-by: Tim Harvey Tested-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 33 ++++++++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index ef6a383a05d6..01d4cecdd9e3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -548,7 +548,7 @@ }; gpr: iomuxc-gpr@30340000 { - compatible = "fsl,imx8mm-iomuxc-gpr", "syscon"; + compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon"; reg = <0x30340000 0x10000>; }; @@ -1255,6 +1255,37 @@ status = "disabled"; }; + pcie0: pcie@33800000 { + compatible = "fsl,imx8mm-pcie"; + reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ + 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ + num-lanes = <1>; + num-viewport = <4>; + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + fsl,max-link-speed = <2>; + linux,pci-domain = <0>; + power-domains = <&pgc_pcie>; + resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "apps", "turnoff"; + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + status = "disabled"; + }; + gpu_3d: gpu@38000000 { compatible = "vivante,gc"; reg = <0x38000000 0x8000>; -- cgit From b4d36c10bf173ab430df89ed28a22237d3df1b5e Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Thu, 2 Dec 2021 16:02:37 +0800 Subject: arm64: dts: imx8mm-evk: Add the pcie support on imx8mm evk board Add the PCIe support on iMX8MM EVK boards. And set the default reference clock mode. Signed-off-by: Richard Zhu Tested-by: Marcel Ziswiler Reviewed-by: Tim Harvey Tested-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 55 +++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index 3bac87b7e142..6d67df7692f1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -5,6 +5,7 @@ /dts-v1/; +#include #include #include "imx8mm.dtsi" @@ -30,6 +31,23 @@ }; }; + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + reg_pcie0: regulator-pcie { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0_reg>; + regulator-name = "MPCIE_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -296,6 +314,30 @@ }; }; +&pcie_phy { + fsl,refclk-pad-mode = ; + fsl,tx-deemph-gen1 = <0x2d>; + fsl,tx-deemph-gen2 = <0xf>; + clocks = <&pcie0_refclk>; + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + vpcie-supply = <®_pcie0>; + status = "okay"; +}; + &sai3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; @@ -413,6 +455,19 @@ >; }; + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 + MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41 + >; + }; + + pinctrl_pcie0_reg: pcie0reggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41 + >; + }; + pinctrl_pmic: pmicirqgrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 -- cgit From 8b8ebec67360989faa04fcef9feb1d6e7d9a81f5 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 14 Dec 2021 18:46:23 -0600 Subject: arm64: dts: imx8mn: add GPC node Add the DT node for the GPC, including all the PGC power domains, some of them are not fully functional yet, as they require interaction with the blk-ctrls to properly power up/down the peripherals. Signed-off-by: Adam Ford Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 49 +++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index b8d49d5f2668..52bf32be994f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -4,6 +4,8 @@ */ #include +#include +#include #include #include #include @@ -640,6 +642,53 @@ interrupts = ; #reset-cells = <1>; }; + + gpc: gpc@303a0000 { + compatible = "fsl,imx8mn-gpc"; + reg = <0x303a0000 0x10000>; + interrupt-parent = <&gic>; + interrupts = ; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + pgc_hsiomix: power-domain@0 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MN_CLK_USB_BUS>; + }; + + pgc_otg1: power-domain@1 { + #power-domain-cells = <0>; + reg = ; + power-domains = <&pgc_hsiomix>; + }; + + pgc_gpumix: power-domain@2 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>, + <&clk IMX8MN_CLK_GPU_SHADER>, + <&clk IMX8MN_CLK_GPU_BUS_ROOT>, + <&clk IMX8MN_CLK_GPU_AHB>; + resets = <&src IMX8MQ_RESET_GPU_RESET>; + }; + + pgc_dispmix: power-domain@3 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>; + }; + + pgc_mipi: power-domain@4 { + #power-domain-cells = <0>; + reg = ; + power-domains = <&pgc_dispmix>; + }; + }; + }; }; aips2: bus@30400000 { -- cgit From ea2b5af58ab24659205e07b6373c5987a46e4792 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 14 Dec 2021 18:46:24 -0600 Subject: arm64: dts: imx8mn: put USB controller into power-domains Now that we have support for the power domain controller on the i.MX8MN, we can put the USB controller in the respective power domain to allow it to power down the PHY when possible. Signed-off-by: Adam Ford Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 52bf32be994f..5d851420254b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -1048,6 +1048,7 @@ assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>; phys = <&usbphynop1>; fsl,usbmisc = <&usbmisc1 0>; + power-domains = <&pgc_otg1>; status = "disabled"; }; -- cgit From 18d4a6c9f2809102a30470de74e37dffbc82c76c Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 14 Dec 2021 18:46:25 -0600 Subject: arm64: dts: imx8mn: add DISP blk-ctrl Add the DT node for the DISP blk-ctrl. With this in place the display/mipi power domains should be functional. Signed-off-by: Adam Ford Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 5d851420254b..dc3f66d284e5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -1038,6 +1038,34 @@ #size-cells = <1>; ranges; + disp_blk_ctrl: blk-ctrl@32e28000 { + compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon"; + reg = <0x32e28000 0x100>; + power-domains = <&pgc_dispmix>, <&pgc_dispmix>, + <&pgc_dispmix>, <&pgc_mipi>, + <&pgc_mipi>; + power-domain-names = "bus", "isi", + "lcdif", "mipi-dsi", + "mipi-csi"; + clocks = <&clk IMX8MN_CLK_DISP_AXI>, + <&clk IMX8MN_CLK_DISP_APB>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>, + <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, + <&clk IMX8MN_CLK_DSI_CORE>, + <&clk IMX8MN_CLK_DSI_PHY_REF>, + <&clk IMX8MN_CLK_CSI1_PHY_REF>, + <&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>; + clock-names = "disp_axi", "disp_apb", + "disp_axi_root", "disp_apb_root", + "lcdif-axi", "lcdif-apb", "lcdif-pix", + "dsi-pclk", "dsi-ref", + "csi-aclk", "csi-pclk"; + #power-domain-cells = <1>; + }; + usbotg1: usb@32e40000 { compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb"; reg = <0x32e40000 0x200>; -- cgit From 9a0f3b157e22eb4a5f5bddd3ba820b2bee5407b0 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 14 Dec 2021 18:46:26 -0600 Subject: arm64: dts: imx8mn: Enable GPU The i.MX8M-Nano features a GC7000. The Etnaviv driver detects it as: etnaviv-gpu 38000000.gpu: model: GC7000, revision: 6203 Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index dc3f66d284e5..99f0f5026674 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -1116,6 +1116,32 @@ status = "disabled"; }; + gpu: gpu@38000000 { + compatible = "vivante,gc"; + reg = <0x38000000 0x8000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_GPU_AHB>, + <&clk IMX8MN_CLK_GPU_BUS_ROOT>, + <&clk IMX8MN_CLK_GPU_CORE_ROOT>, + <&clk IMX8MN_CLK_GPU_SHADER>; + clock-names = "reg", "bus", "core", "shader"; + assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE>, + <&clk IMX8MN_CLK_GPU_SHADER>, + <&clk IMX8MN_CLK_GPU_AXI>, + <&clk IMX8MN_CLK_GPU_AHB>, + <&clk IMX8MN_GPU_PLL>; + assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>, + <&clk IMX8MN_GPU_PLL_OUT>, + <&clk IMX8MN_SYS_PLL1_800M>, + <&clk IMX8MN_SYS_PLL1_800M>; + assigned-clock-rates = <400000000>, + <400000000>, + <800000000>, + <400000000>, + <1200000000>; + power-domains = <&pgc_gpumix>; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, -- cgit From afb424b99e0f556bf1324c73570028cb56d5cadb Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Thu, 16 Dec 2021 08:41:49 -0800 Subject: arm64: dts: imx8mm-venice*: add PCIe support Add PCIe support to GW71xx/GW72xx/GW73xx/GW7901/GW7902 Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mm-venice-gw71xx.dtsi | 35 ++++++++++++ .../boot/dts/freescale/imx8mm-venice-gw72xx.dtsi | 62 ++++++++++++++++++++++ .../boot/dts/freescale/imx8mm-venice-gw73xx.dtsi | 62 ++++++++++++++++++++++ .../boot/dts/freescale/imx8mm-venice-gw7901.dts | 36 +++++++++++++ .../boot/dts/freescale/imx8mm-venice-gw7902.dts | 50 +++++++++++++++++ 5 files changed, 245 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi index 28012279f6f6..506335efc391 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi @@ -5,6 +5,7 @@ #include #include +#include / { aliases { @@ -33,6 +34,12 @@ }; }; + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + pps { compatible = "pps-gpio"; pinctrl-names = "default"; @@ -87,6 +94,28 @@ status = "okay"; }; +&pcie_phy { + fsl,refclk-pad-mode = ; + fsl,clkreq-unsupported; + clocks = <&pcie0_refclk>; + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + status = "okay"; +}; + /* GPS */ &uart1 { pinctrl-names = "default"; @@ -148,6 +177,12 @@ >; }; + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41 + >; + }; + pinctrl_pps: ppsgrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi index 27afa46a253a..72a3a3aa8fcd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi @@ -5,9 +5,11 @@ #include #include +#include / { aliases { + ethernet1 = ð1; usb0 = &usbotg1; usb1 = &usbotg2; }; @@ -33,6 +35,12 @@ }; }; + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + pps { compatible = "pps-gpio"; pinctrl-names = "default"; @@ -106,6 +114,54 @@ status = "okay"; }; +&pcie_phy { + fsl,refclk-pad-mode = ; + fsl,clkreq-unsupported; + clocks = <&pcie0_refclk>; + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + status = "okay"; + + pcie@0,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; + + pcie@1,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; + + pcie@2,3 { + reg = <0x1800 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; + + eth1: pcie@5,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; + + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; + }; +}; + /* off-board header */ &sai3 { pinctrl-names = "default"; @@ -198,6 +254,12 @@ >; }; + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41 + >; + }; + pinctrl_pps: ppsgrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi index a59e849c7be2..7b00b6b5bb38 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi @@ -5,9 +5,11 @@ #include #include +#include / { aliases { + ethernet1 = ð1; usb0 = &usbotg1; usb1 = &usbotg2; }; @@ -33,6 +35,12 @@ }; }; + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + pps { compatible = "pps-gpio"; pinctrl-names = "default"; @@ -126,6 +134,54 @@ status = "okay"; }; +&pcie_phy { + fsl,refclk-pad-mode = ; + fsl,clkreq-unsupported; + clocks = <&pcie0_refclk>; + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + status = "okay"; + + pcie@0,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; + + pcie@1,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; + + pcie@2,4 { + reg = <0x2000 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; + + eth1: pcie@6,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; + + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; + }; +}; + /* off-board header */ &sai3 { pinctrl-names = "default"; @@ -241,6 +297,12 @@ >; }; + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41 + >; + }; + pinctrl_pps: ppsgrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts index 21c546c4628d..ca754dff918d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts @@ -8,6 +8,7 @@ #include #include #include +#include #include "imx8mm.dtsi" @@ -179,6 +180,12 @@ }; }; + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "3P3V"; @@ -644,6 +651,28 @@ status = "okay"; }; +&pcie_phy { + fsl,refclk-pad-mode = ; + fsl,clkreq-unsupported; + clocks = <&pcie0_refclk>; + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio5 2 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + status = "okay"; +}; + &pgc_gpu { status = "disabled"; }; @@ -820,6 +849,13 @@ >; }; + pinctrl_pcie0: pciegrp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x40000041 /* WDIS# */ + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x41 + >; + }; + pinctrl_pmic: pmicgrp { fsl,pins = < MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts index d52686f4c059..1b2aaf299b24 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts @@ -9,6 +9,7 @@ #include #include #include +#include #include "imx8mm.dtsi" @@ -17,6 +18,7 @@ compatible = "gw,imx8mm-gw7902", "fsl,imx8mm"; aliases { + ethernet1 = ð1; usb0 = &usbotg1; usb1 = &usbotg2; }; @@ -128,6 +130,12 @@ }; }; + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + pps { compatible = "pps-gpio"; pinctrl-names = "default"; @@ -547,6 +555,42 @@ status = "okay"; }; +&pcie_phy { + fsl,refclk-pad-mode = ; + fsl,clkreq-unsupported; + clocks = <&clk IMX8MM_CLK_DUMMY>; + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_DUMMY>, <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + status = "okay"; + + pcie@0,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; + + eth1: pcie@1,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; + + local-mac-address = [00 00 00 00 00 00]; + }; + }; +}; + /* off-board header */ &sai3 { pinctrl-names = "default"; @@ -737,6 +781,12 @@ >; }; + pinctrl_pcie0: pciegrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x41 + >; + }; + pinctrl_pmic: pmicgrp { fsl,pins = < MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41 -- cgit From 84a7f5a98346e14831025e0f86c809924816424a Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 17 Dec 2021 11:39:08 -0600 Subject: arm64: dts: imx8qm: Drop CPU 'arm,armv8' compatible The CPU 'arm,armv8' compatible is only for s/w models, so remove it from i.MX8QM CPU nodes. Cc: Shawn Guo Cc: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Rob Herring Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qm.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index 4a7c017b5f31..405cff7d942d 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -54,7 +54,7 @@ A53_0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x0>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -68,7 +68,7 @@ A53_1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x1>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -82,7 +82,7 @@ A53_2: cpu@2 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x2>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -96,7 +96,7 @@ A53_3: cpu@3 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x3>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -110,7 +110,7 @@ A72_0: cpu@100 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x0 0x100>; enable-method = "psci"; i-cache-size = <0xC000>; @@ -124,7 +124,7 @@ A72_1: cpu@101 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x0 0x101>; enable-method = "psci"; next-level-cache = <&A72_L2>; -- cgit From 58497d7a13ede30b1b2dea3ba7446472f9d4f411 Mon Sep 17 00:00:00 2001 From: David Jander Date: Fri, 17 Dec 2021 22:36:17 +0100 Subject: arm64: dts: imx: add Protonic PRT8MM board The Protonic PRT8MM is a low-cost agricultural Virtual Terminal. This commit adds most of the board functionality sans the display output, as the i.MX8MM display support isn't ready yet. Signed-off-by: David Jander Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-prt8mm.dts | 304 ++++++++++++++++++++++++ 1 file changed, 304 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-prt8mm.dts (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-prt8mm.dts b/arch/arm64/boot/dts/freescale/imx8mm-prt8mm.dts new file mode 100644 index 000000000000..9fbbbb556c0b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-prt8mm.dts @@ -0,0 +1,304 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 Protonic Holland + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include +#include "imx8mm.dtsi" + +/ { + model = "Protonic PRT8MM"; + compatible = "prt,prt8mm", "fsl,imx8mm"; + + chosen { + stdout-path = &uart4; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x40000000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + debug-led0 { + label = "DEBUG_LED0"; + gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + debug-led1 { + label = "DEBUG_LED1"; + gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "cpu"; + }; + }; + + sound-ssm2518 { + compatible = "simple-audio-card"; + simple-audio-card,name = "ssm2518-audio"; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&cpudai>; + simple-audio-card,bitclock-master = <&cpudai>; + + cpudai: simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + + simple-audio-card,codec { + sound-dai = <&ssm2518>; + clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + ssm2518: audio-codec@34 { + compatible = "adi,ssm2518"; + reg = <0x34>; + #sound-dai-cells = <0>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + regulator@60 { + compatible = "fcs,fan53555"; + reg = <0x60>; + regulator-name = "0V9_CORE"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <980000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + rtc@51 { + compatible = "nxp,pcf85363"; + reg = <0x51>; + }; + + touchscreeen@5d { + compatible = "goodix,gt911"; + reg = <0x5d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touchscreen>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_NONE>; + irq-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + }; + + temp-sense@70 { + compatible = "ti,tmp103"; + reg = <0x70>; + }; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MM_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + fsl,sai-asynchronous; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + dr_mode = "host"; + disable-over-current; + power-active-high; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; + assigned-clock-rates = <100000000>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_gpio_leds: ledsgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x00 + MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x00 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400000c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400000c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400000c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400000c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400000c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400000c3 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 + MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 + >; + }; + + pinctrl_touchscreen: tsgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x80 + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x80 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x040 + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x040 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x000 + MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x000 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0d4 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; -- cgit From 0bcc4bf063b2843a2e9897c0477f7ad4609ae06d Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Sat, 18 Dec 2021 19:18:08 +0100 Subject: arm64: dts: imx8mq: disable DDRC node by default MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Without a OPP table or a downstream TF-A running on the system the DDRC will fail to probe, as it has no means to scale the DRAM frequency in that case. This however will block the bus scaling driver to come up and this in turn prevents other devices that hook into the interconnect from probing. If the DDRC is disabled, the interconnect driver will simply ignore it. As most systems don't want to scale the DRAM frequency, disable the node by default and only enable it on the systems that actually uses this capability and provides a valid OPP table in the DT. Signed-off-by: Lucas Stach Reviewed-by: Fabio Estevam Acked-by: Martin Kepplinger Reviewed-by: Guido Günther Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 1 + arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 1 + arch/arm64/boot/dts/freescale/imx8mq.dtsi | 1 + 3 files changed, 3 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index a1b7582f3ecf..e7f521aac400 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -123,6 +123,7 @@ &ddrc { operating-points-v2 = <&ddrc_opp_table>; + status = "okay"; ddrc_opp_table: opp-table { compatible = "operating-points-v2"; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index f3e3418f7edc..4429a0471bad 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -278,6 +278,7 @@ &ddrc { operating-points-v2 = <&ddrc_opp_table>; + status = "okay"; ddrc_opp_table: opp-table { compatible = "operating-points-v2"; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 2df2510d0118..94d09dcf09b0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1579,6 +1579,7 @@ <&clk IMX8MQ_DRAM_PLL_OUT>, <&clk IMX8MQ_CLK_DRAM_ALT>, <&clk IMX8MQ_CLK_DRAM_APB>; + status = "disabled"; }; ddr-pmu@3d800000 { -- cgit From eb893e34309ce2153003f3f2a13cdbfdea939e00 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Sat, 18 Dec 2021 19:20:20 +0100 Subject: arm64: dts: mnt-reform2: add internal display support This adds support for the internal display of the Reform2 Laptop, which is connected to the i.MX8MQ via a MIPI-DSI->eDP bridge chip. Clocking is derived from a system PLL, which provides quite good rate matching for the single supported display mode and keeps the video PLL free for usage with the external display, which isn't supported yet. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mq-mnt-reform2.dts | 140 +++++++++++++++++++++ 1 file changed, 140 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts index fa721a13de20..e2d69b9ed442 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts @@ -14,6 +14,30 @@ compatible = "mntre,reform2", "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq"; chassis-type = "laptop"; + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + pwms = <&pwm2 0 10000>; + power-supply = <®_main_usb>; + enable-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + brightness-levels = <0 32 64 128 160 200 255>; + default-brightness-level = <6>; + }; + + panel { + compatible = "innolux,n125hce-gn1", "simple-panel"; + power-supply = <®_main_3v3>; + backlight = <&backlight>; + no-hpd; + + port { + panel_in: endpoint { + remote-endpoint = <&edp_bridge_out>; + }; + }; + }; + pcie1_refclk: clock-pcie1-refclk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -42,6 +66,22 @@ vin-supply = <®_main_5v>; }; + reg_main_1v8: regulator-main-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <®_main_3v3>; + }; + + reg_main_1v2: regulator-main-1v2 { + compatible = "regulator-fixed"; + regulator-name = "1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <®_main_5v>; + }; + sound { compatible = "fsl,imx-audio-wm8960"; audio-cpu = <&sai2>; @@ -61,6 +101,13 @@ }; }; +&dphy { + assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>; + assigned-clock-rates = <25000000>; + status = "okay"; +}; + &fec1 { status = "okay"; }; @@ -84,6 +131,67 @@ }; }; +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + clock-frequency = <400000>; + status = "okay"; + + edp_bridge: bridge@2c { + compatible = "ti,sn65dsi86"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_edp_bridge>; + reg = <0x2c>; + enable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; + vccio-supply = <®_main_1v8>; + vpll-supply = <®_main_1v8>; + vcca-supply = <®_main_1v2>; + vcc-supply = <®_main_1v2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + edp_bridge_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + edp_bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; +}; + +&lcdif { + assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>; + /delete-property/assigned-clock-rates; + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + mipi_dsi_out: endpoint { + remote-endpoint = <&edp_bridge_in>; + }; + }; + }; +}; + &pcie1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie1>; @@ -96,6 +204,13 @@ status = "okay"; }; +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + + ®_1p8v { vin-supply = <®_main_5v>; }; @@ -169,6 +284,18 @@ }; &iomuxc { + pinctrl_backlight: backlightgrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x3 + >; + }; + + pinctrl_edp_bridge: edpbridgegrp { + fsl,pins = < + MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x1 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f @@ -176,12 +303,25 @@ >; }; + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000022 + MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000022 + >; + }; + pinctrl_pcie1: pcie1grp { fsl,pins = < MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x16 >; }; + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x3 + >; + }; + pinctrl_sai2: sai2grp { fsl,pins = < MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 -- cgit From 0c84549ab5c46bc0ad711799b792b8094d036edf Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Sat, 18 Dec 2021 19:20:21 +0100 Subject: arm64: dts: mnt-reform2: correct i2c3 pad-ctrl The slew rate and drive-strength of the i2c3 pads were much too high. Bring them down to avoid signal quality issues. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts index e2d69b9ed442..94a13cb500e6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts @@ -298,8 +298,8 @@ pinctrl_i2c3: i2c3grp { fsl,pins = < - MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f - MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f + MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000022 + MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000022 >; }; -- cgit From 75e4493e881dc79cb8373c136d1e7a5d32297948 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Tue, 4 Jan 2022 00:49:00 +0200 Subject: arm64: dts: imx8qm: Add SCU RTC node Add SCU RTC node to support SC RTC driver. Signed-off-by: Abel Vesa Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qm.dtsi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index 405cff7d942d..a6ffdc92a520 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -201,6 +201,9 @@ compatible = "fsl,imx8qm-iomuxc"; }; + rtc: rtc { + compatible = "fsl,imx8qxp-sc-rtc"; + }; }; /* sorted in register address */ -- cgit From 591de9fb73b7c9924800a8d1192789d8c2625160 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 11 Jan 2022 14:20:13 +0800 Subject: arm64: dts: imx8: add mu5/6 node Add mu5/6 for i.MX8QXP/QM, these two mu will be used for communicating with general purpose Cortex-M4 cores. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi | 16 ++++++++++++++++ arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi | 8 ++++++++ arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi | 8 ++++++++ 3 files changed, 32 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi index ee4e585a9c39..6446e6df7a9a 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi @@ -141,6 +141,22 @@ lsio_subsys: bus@5d000000 { status = "disabled"; }; + lsio_mu5: mailbox@5d200000 { + reg = <0x5d200000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_MU_5A>; + status = "disabled"; + }; + + lsio_mu6: mailbox@5d210000 { + reg = <0x5d210000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_MU_6A>; + status = "disabled"; + }; + lsio_mu13: mailbox@5d280000 { reg = <0x5d280000 0x10000>; interrupts = ; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi index 30896610c654..669aa14ce9f7 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi @@ -56,6 +56,14 @@ compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu"; }; +&lsio_mu5 { + compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu"; +}; + +&lsio_mu6 { + compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu"; +}; + &lsio_mu13 { compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi index 11395479ffc0..8e2152c6eb88 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi @@ -56,6 +56,14 @@ compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; }; +&lsio_mu5 { + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; +}; + +&lsio_mu6 { + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; +}; + &lsio_mu13 { compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; }; -- cgit From 5c87d6cbebc33adf521f1c446a41d7af66db329b Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Tue, 18 Jan 2022 15:59:18 +0200 Subject: arm64: dts: imx8qxp-ss-adma: Drop fsl,imx7ulp-lpuart comaptible The driver differs from clocks point of view, so the i.MX8QXP is not backwards compatible with i.MX7ULP. Signed-off-by: Abel Vesa Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi index dc1daa8dc72f..7bae516004bf 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi @@ -5,19 +5,19 @@ */ &lpuart0 { - compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx8qxp-lpuart"; }; &lpuart1 { - compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx8qxp-lpuart"; }; &lpuart2 { - compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx8qxp-lpuart"; }; &lpuart3 { - compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx8qxp-lpuart"; }; &i2c0 { -- cgit From b2d67d7bdf746b2c5a26f6822100b32e35669c59 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Wed, 19 Jan 2022 14:23:48 +0100 Subject: arm64: dts: imx8mp: disable usb3_phy1 Like usb3_phy0 the default state of the usb3_phy1 should be disabled, so it is only enabled on boards exposing this USB port. Signed-off-by: Lucas Stach Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 6b840c05dd77..3f8703f3ba5b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -958,6 +958,7 @@ assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; assigned-clock-parents = <&clk IMX8MP_CLK_24M>; #phy-cells = <0>; + status = "disabled"; }; usb3_1: usb@32f10108 { -- cgit From b10e940f8a814d187fada5849b5db091a66889d5 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 25 Jan 2022 03:54:09 +0100 Subject: arm64: dts: imx8mm: Add missing MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B The i.MX8M Mini Application Processor Reference Manual, Rev. 3, 11/2020 documents AF MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B , add it into the pinmux tables. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: NXP Linux Team Cc: Peng Fan Cc: Shawn Guo Reviewed-by: Peng Fan Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h index a003e6af3353..a7411c800bef 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h +++ b/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h @@ -248,6 +248,7 @@ #define MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0 #define MX8MM_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0 #define MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x134 0x39C 0x000 0x2 0x0 #define MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0 #define MX8MM_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0 #define MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0 -- cgit From 8cd449d73d82feb13905ad950887d95a74f581e1 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Thu, 16 Dec 2021 08:12:27 -0800 Subject: arm64: dts: imx8mn-venice-gw7902: disable gpu Since commit 9a0f3b157e22 ("arm64: dts: imx8mn: Enable GPU") imx8mn-venice-gw7902 will hang during kernel init because it uses a MIMX8MN5CVTI which does not have a GPU. Disable pgc_gpumix to work around this. We also disable the GPU devices that depend on the gpumix power domain and pgc_gpu to avoid them staying in a probe deferred state forever. Cc: Adam Ford Cc: Lucas Stach Signed-off-by: Tim Harvey Fixes: 9a0f3b157e22 ("arm64: dts: imx8mn: Enable GPU") Reviewed-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts index 236f425e1570..2d58005d20e4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts @@ -220,6 +220,10 @@ }; }; +&disp_blk_ctrl { + status = "disabled"; +}; + /* off-board header */ &ecspi2 { pinctrl-names = "default"; @@ -251,6 +255,10 @@ }; }; +&gpu { + status = "disabled"; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -546,6 +554,10 @@ status = "okay"; }; +&pgc_gpumix { + status = "disabled"; +}; + /* off-board header */ &sai3 { pinctrl-names = "default"; -- cgit From 9d46d9f7821ee66b0b83098e058d579e7b2e57ec Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Thu, 27 Jan 2022 17:06:03 -0800 Subject: arm64: dts: imx8m{m,n}_venice*: add gpio-line-names Add gpio-line-names for the various GPIO's used on Gateworks Venice boards. Note that these GPIO's are typically 'configured' in Boot Firmware via gpio-hog therefore we only configure line names to keep the boot firmware configuration from changing on kernel init. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mm-venice-gw71xx.dtsi | 14 ++++++++ .../boot/dts/freescale/imx8mm-venice-gw72xx.dtsi | 16 +++++++++ .../boot/dts/freescale/imx8mm-venice-gw73xx.dtsi | 16 +++++++++ .../boot/dts/freescale/imx8mm-venice-gw7901.dts | 23 +++++++++++++ .../boot/dts/freescale/imx8mm-venice-gw7902.dts | 39 +++++++++++++++++++++- .../boot/dts/freescale/imx8mn-venice-gw7902.dts | 39 +++++++++++++++++++++- 6 files changed, 145 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi index 506335efc391..73addc0b8e57 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi @@ -68,6 +68,20 @@ status = "okay"; }; +&gpio1 { + gpio-line-names = "", "", "", "", "", "", "pci_usb_sel", "dio0", + "", "dio1", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = "", "", "", "dio2", "dio3", "", "", "pci_wdis#", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + &i2c2 { clock-frequency = <400000>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi index 72a3a3aa8fcd..1e7badb2a82e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi @@ -88,6 +88,22 @@ status = "okay"; }; +&gpio1 { + gpio-line-names = "rs485_term", "mipi_gpio4", "", "", + "", "", "pci_usb_sel", "dio0", + "", "dio1", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2", + "mipi_gpio1", "", "", "pci_wdis#", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + &i2c2 { clock-frequency = <400000>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi index 7b00b6b5bb38..426483ec1f88 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi @@ -108,6 +108,22 @@ status = "okay"; }; +&gpio1 { + gpio-line-names = "rs485_term", "mipi_gpio4", "", "", + "", "", "pci_usb_sel", "dio0", + "", "dio1", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2", + "mipi_gpio1", "", "", "pci_wdis#", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + &i2c2 { clock-frequency = <400000>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts index ca754dff918d..7e7231046215 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts @@ -293,6 +293,29 @@ }; }; +&gpio1 { + gpio-line-names = "uart1_rs422#", "", "", "uart1_rs485#", + "", "uart1_rs232#", "dig1_in", "dig1_out", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = "", "", "", "", + "", "", "uart3_rs232#", "uart3_rs422#", + "uart3_rs485#", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "uart4_rs485#", "", "sim1det#", "sim2det#", ""; +}; + +&gpio5 { + gpio-line-names = "", "", "", "dig2_out", "dig2_in", "sim2sel", "", "", + "", "", "uart4_rs232#", "", "", "uart4_rs422#", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + &gpu_2d { status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts index 1b2aaf299b24..edf0c7aaaef0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts @@ -260,6 +260,43 @@ }; }; +&gpio1 { + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", "", "", "", "m2_reset", "", "m2_wdis#", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = "", "", "", "", "", "", "", "", + "uart2_en#", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", "", "amp_gpio3", "amp_gpio2", "", "amp_gpio1", "", + "", "", "", "", "amp_gpio4", "app_gpio1", "", "uart1_rs485", + "", "uart1_term", "uart1_half", "app_gpio2", + "mipi_gpio1", "", "", ""; +}; + +&gpio5 { + gpio-line-names = "", "", "", "mipi_gpio4", + "mipi_gpio3", "mipi_gpio2", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -691,7 +728,7 @@ pinctrl_hog: hoggrp { fsl,pins = < MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */ - MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RST# */ + MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */ MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */ MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */ MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */ diff --git a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts index 2d58005d20e4..3c0e63d2e82d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts @@ -255,6 +255,43 @@ }; }; +&gpio1 { + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", "", "", "", "m2_reset", "", "m2_wdis#", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = "", "", "", "", "", "", "", "", + "uart2_en#", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "app_gpio1", "", "uart1_rs485", + "", "uart1_term", "uart1_half", "app_gpio2", + "mipi_gpio1", "", "", ""; +}; + +&gpio5 { + gpio-line-names = "", "", "", "mipi_gpio4", + "mipi_gpio3", "mipi_gpio2", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + &gpu { status = "disabled"; }; @@ -645,7 +682,7 @@ pinctrl_hog: hoggrp { fsl,pins = < MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */ - MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RST# */ + MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */ MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */ MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */ MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */ -- cgit From 34b13d121344ea6bd6f6eda41bec145654735905 Mon Sep 17 00:00:00 2001 From: Li Yang Date: Wed, 26 Jan 2022 03:26:50 -0600 Subject: arm64: dts: ls1028a-qds: define mdio slots for networking options The ls1028a QDS board support different pluggable PHY cards. Define the nodes for these slots to be updated at boot time with overlay according to board setup. Signed-off-by: Alex Marginean Signed-off-by: Li Yang Reviewed-by: Andrew Lunn Tested-by: Vladimir Oltean Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 24 +++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts index 177bc1405f0f..19d3952dbffe 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts @@ -107,6 +107,30 @@ reg = <5>; }; }; + + mdio_slot1: mdio@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + mdio_slot2: mdio@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + mdio_slot3: mdio@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + mdio_slot4: mdio@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; }; }; -- cgit From 30e5d233682fc97c9720308043621feeda974b8c Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 25 Jan 2022 11:11:18 -0600 Subject: arm64: dts: imx8mq-tqma8mq: Remove redundant vpu reference The vpu is enabled by default, so there is no need to manually enable it. Signed-off-by: Adam Ford Reviewed-by: Lucas Stach Reviewed-by: Ezequiel Garcia Reviewed-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi index 8aedcddfeab8..38ffcd145b33 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi @@ -272,10 +272,6 @@ status = "okay"; }; -&vpu { - status = "okay"; -}; - /* Attention: wdog reset forcing POR needs baseboard support */ &wdog1 { status = "okay"; -- cgit From 4ac7e4a81272ca4ccc6bcc387b372ddc7b588f9f Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 25 Jan 2022 11:11:24 -0600 Subject: arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl With the Hantro G1 and G2 now setup to run independently, update the device tree to allow both to operate. This requires the vpu-blk-ctrl node to be configured. Since vpu-blk-ctrl needs certain clock enabled to handle the gating of the G1 and G2 fuses, the clock-parents and clock-rates for the various VPU's to be moved into the pgc_vpu because they cannot get re-parented once enabled, and the pgc_vpu is the highest in the chain. Signed-off-by: Adam Ford Reviewed-by: Ezequiel Garcia Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 63 +++++++++++++++++++------------ 1 file changed, 39 insertions(+), 24 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 94d09dcf09b0..c4d48952b3b8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -737,7 +737,21 @@ pgc_vpu: power-domain@6 { #power-domain-cells = <0>; reg = ; - clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; + clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>, + <&clk IMX8MQ_CLK_VPU_G1_ROOT>, + <&clk IMX8MQ_CLK_VPU_G2_ROOT>; + assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, + <&clk IMX8MQ_CLK_VPU_G2>, + <&clk IMX8MQ_CLK_VPU_BUS>, + <&clk IMX8MQ_VPU_PLL_BYPASS>; + assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, + <&clk IMX8MQ_VPU_PLL_OUT>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_VPU_PLL>; + assigned-clock-rates = <600000000>, + <600000000>, + <800000000>, + <0>; }; pgc_disp: power-domain@7 { @@ -1457,30 +1471,31 @@ status = "disabled"; }; - vpu: video-codec@38300000 { - compatible = "nxp,imx8mq-vpu"; - reg = <0x38300000 0x10000>, - <0x38310000 0x10000>, - <0x38320000 0x10000>; - reg-names = "g1", "g2", "ctrl"; - interrupts = , - ; - interrupt-names = "g1", "g2"; + vpu_g1: video-codec@38300000 { + compatible = "nxp,imx8mq-vpu-g1"; + reg = <0x38300000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>; + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>; + }; + + vpu_g2: video-codec@38310000 { + compatible = "nxp,imx8mq-vpu-g2"; + reg = <0x38310000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>; + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>; + }; + + vpu_blk_ctrl: blk-ctrl@38320000 { + compatible = "fsl,imx8mq-vpu-blk-ctrl"; + reg = <0x38320000 0x100>; + power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>; + power-domain-names = "bus", "g1", "g2"; clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, - <&clk IMX8MQ_CLK_VPU_G2_ROOT>, - <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; - clock-names = "g1", "g2", "bus"; - assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, - <&clk IMX8MQ_CLK_VPU_G2>, - <&clk IMX8MQ_CLK_VPU_BUS>, - <&clk IMX8MQ_VPU_PLL_BYPASS>; - assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, - <&clk IMX8MQ_VPU_PLL_OUT>, - <&clk IMX8MQ_SYS1_PLL_800M>, - <&clk IMX8MQ_VPU_PLL>; - assigned-clock-rates = <600000000>, <600000000>, - <800000000>, <0>; - power-domains = <&pgc_vpu>; + <&clk IMX8MQ_CLK_VPU_G2_ROOT>; + clock-names = "g1", "g2"; + #power-domain-cells = <1>; }; pcie0: pcie@33800000 { -- cgit From 9cbe605b8e3fc99d58c491865170443b12d180b4 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 25 Jan 2022 11:11:28 -0600 Subject: arm64: dts: imx8mm: Enable Hantro G1 and G2 video decoders There are two decoders on the i.MX8M Mini controlled by the vpu-blk-ctrl. The G1 supports H264 and VP8 while the G2 support HEVC and VP9. Signed-off-by: Adam Ford Reviewed-by: Ezequiel Garcia Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 01d4cecdd9e3..2692f3a497e4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1317,6 +1317,22 @@ power-domains = <&pgc_gpu>; }; + vpu_g1: video-codec@38300000 { + compatible = "nxp,imx8mm-vpu-g1"; + reg = <0x38300000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>; + power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>; + }; + + vpu_g2: video-codec@38310000 { + compatible = "nxp,imx8mq-vpu-g2"; + reg = <0x38310000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>; + power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>; + }; + vpu_blk_ctrl: blk-ctrl@38330000 { compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon"; reg = <0x38330000 0x100>; @@ -1327,6 +1343,12 @@ <&clk IMX8MM_CLK_VPU_G2_ROOT>, <&clk IMX8MM_CLK_VPU_H1_ROOT>; clock-names = "g1", "g2", "h1"; + assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>, + <&clk IMX8MM_CLK_VPU_G2>; + assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, + <&clk IMX8MM_VPU_PLL_OUT>; + assigned-clock-rates = <600000000>, + <600000000>; #power-domain-cells = <1>; }; -- cgit From 1d84283101fcbe3e60c64b05ef05918648d262cf Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Wed, 26 Jan 2022 14:23:38 +0100 Subject: arm64: dts: tqma8mqml: add PCIe support Add PCIe support to TQMa8MxML series. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts | 19 +++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi | 5 +++++ arch/arm64/boot/dts/freescale/mba8mx.dtsi | 6 ++++++ 3 files changed, 30 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts index 7844878788f4..286d2df01cfa 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include #include "imx8mm-tqma8mqml.dtsi" #include "mba8mx.dtsi" @@ -58,6 +59,24 @@ }; }; +&pcie_phy { + clocks = <&pcie0_refclk>; + status = "okay"; +}; + +&pcie0 { + reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + status = "okay"; +}; + &sai3 { assigned-clocks = <&clk IMX8MM_CLK_SAI3>; assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi index 284e62acc0b4..16ee9b5179e6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi @@ -227,6 +227,11 @@ }; }; +&pcie_phy { + fsl,refclk-pad-mode = ; + fsl,clkreq-unsupported; +}; + &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; diff --git a/arch/arm64/boot/dts/freescale/mba8mx.dtsi b/arch/arm64/boot/dts/freescale/mba8mx.dtsi index f27e3c8de916..3ea34b3a55f8 100644 --- a/arch/arm64/boot/dts/freescale/mba8mx.dtsi +++ b/arch/arm64/boot/dts/freescale/mba8mx.dtsi @@ -66,6 +66,12 @@ }; }; + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + reg_hub_vbus: regulator-hub-vbus { compatible = "regulator-fixed"; regulator-name = "MBA8MX_HUB_VBUS"; -- cgit From 2449d0440a2b70dd4793c2e9e6a71d0e538e0778 Mon Sep 17 00:00:00 2001 From: Reinhold Mueller Date: Thu, 27 Jan 2022 16:35:00 +0100 Subject: arm64: dts: imx8mm: Add support for emtrion emCON-MX8M Mini This patch adds support for the emtrion GmbH emCON-MX8M Mini modules. They are available with NXP i.MX 8M Mini equipped with 2 or 4 GB Memory. The devicetree imx8mm-emcon.dtsi is the common part providing all module components and the basic support for the SoC. The support for the avari baseboard in the developer-kit configuration is provided by the emcon-avari dts files. Signed-off-by: Reinhold Mueller Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 3 +- .../boot/dts/freescale/imx8mm-emcon-avari.dts | 23 + .../boot/dts/freescale/imx8mm-emcon-avari.dtsi | 139 +++++ arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi | 627 +++++++++++++++++++++ 4 files changed, 791 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 6d8f0a532587..9a5570025a54 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -50,8 +50,9 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-qds.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-emcon-avari.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n801x-s.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dts b/arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dts new file mode 100644 index 000000000000..b2e8967e9687 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +// +// Copyright (c) 2021 emtrion GmbH +// Author: Frank Erdrich +// + +/dts-v1/; + +#include "imx8mm-emcon.dtsi" +#include "imx8mm-emcon-avari.dtsi" + +/ { + model = "emtrion SoM emCON-MX8M mini on Avari"; + compatible = "emtrion,emcon-mx8mm-avari", "fsl,imx8mm"; +}; + +&lvds_backlight { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dtsi new file mode 100644 index 000000000000..5028f232b6bd --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dtsi @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +// +// Copyright (C) 2021 emtrion GmbH +// Author: Frank Erdrich +// + +/ { + aliases { + boardid = &boardID; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + }; + + chosen { + stdout-path = &uart1; + }; + + reg_wall_5p0: regulator-wall5p0 { + compatible = "regulator-fixed"; + regulator-name = "Main-Supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_base3p3: regulator-base3p3 { + compatible = "regulator-fixed"; + vin-supply = <®_wall_5p0>; + regulator-name = "3V3-avari"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_base1p5: regulator-base1p5 { + compatible = "regulator-fixed"; + vin-supply = <®_base3p3>; + regulator-name = "1V5-avari"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_usb_otg: regulator-otgvbus { + compatible = "regulator-fixed"; + vin-supply = <®_wall_5p0>; + regulator-name = "OTG_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + + clk_codec: clock-codec { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "SGTL5000-Card"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,widgets = "Headphone", "Headphone Jack"; + simple-audio-card,routing = "Headphone Jack", "HP_OUT"; + + cpu_dai: simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + + codec_dai: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + }; + }; +}; + +&ecspi1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + status = "okay"; + + sgtl5000: audio-codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + clocks = <&clk_codec>; + VDDA-supply = <®_base3p3>; + VDDIO-supply = <®_base3p3>; + }; + + boardID: gpio@3a { + compatible = "nxp,pca8574"; + reg = <0x3a>; + gpio-controller; + #gpio-cells = <1>; + }; +}; + +&sai2 { + status = "okay"; +}; + +&uart2 { + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&usbotg1 { + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + status = "disabled"; +}; + +&usdhc2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi new file mode 100644 index 000000000000..7c4af71baab9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi @@ -0,0 +1,627 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +// +// Copyright 2018 NXP +// Copyright (C) 2021 emtrion GmbH +// + +/dts-v1/; + +#include "imx8mm.dtsi" + +/ { + chosen { + stdout-path = &uart1; + }; + + som_leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + green { + label = "som:green"; + gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + red { + label = "som:red"; + gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + lvds_backlight: lvds-backlight { + compatible = "pwm-backlight"; + enable-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; + pwms = <&pwm1 0 50000 0>; + brightness-levels = < + 0 4 8 16 32 64 80 96 112 + 128 144 160 176 250 + >; + default-brightness-level = <9>; + status = "disabled"; + }; + + reg_usdhc1_vmmc: regulator-emmc { + compatible = "regulator-fixed"; + regulator-name = "eMMC"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "sdcard_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, + <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + }; + }; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + pinctrl-1 = <&pinctrl_flexspi1>; + status = "okay"; + + flash0: spi-flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <40000000>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_csi_pwn: csi-pwn-grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + >; + }; + + pinctrl_ecspi1: ecspi1-grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 + >; + }; + + pinctrl_ecspi1_cs: ecspi1-cs { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000 + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000 + >; + }; + + pinctrl_fec1: fec1-grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + >; + }; + + pinctrl_flexspi0: flexspi0-grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x82 + >; + }; + + pinctrl_flexspi1: flexspi1-grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x1c2 + MX8MM_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x82 + MX8MM_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x82 + MX8MM_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x82 + MX8MM_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x82 + MX8MM_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x82 + >; + }; + + pinctrl_gpio_led: gpio-led-grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x19 + MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 + >; + }; + + pinctrl_i2c1: i2c1-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_lvds: lvds-grp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x06 + >; + }; + + pinctrl_pcie0: pcie0-grp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41 + MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x41 + >; + }; + + pinctrl_pmic: pmic-irq { + fsl,pins = < + MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x41 + >; + }; + + pinctrl_pwm1: pwm1-grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x06 + >; + }; + + pinctrl_sai2: sai2-grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 + MX8MM_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0xd6 + MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 + MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0xd6 + MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 + >; + }; + + pinctrl_spdif1: spdif1-grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 + MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 + >; + }; + + pinctrl_uart1: uart1-grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + >; + }; + + pinctrl_uart2: uart2-grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + + /* rts and cts */ + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 + >; + }; + + pinctrl_uart3: uart3-grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 + >; + }; + + pinctrl_uart4: uart4-grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1-grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1-gpio-grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x41 + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c4 + >; + }; + + pinctrl_usdhc2: usdhc2-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + /* no reset for sdhc2 interface */ + pinctrl_usdhc2_gpio: usdhc2-gpio-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 + MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x1c4 + >; + }; + + pinctrl_wdog: wdog-grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + bd71847: pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio3>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + rohm,reset-snvs-powered; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; + }; + + buck3_reg: BUCK3 { + // BUCK5 in datasheet + regulator-name = "BUCK3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + // BUCK6 in datasheet + regulator-name = "BUCK4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + // BUCK7 in datasheet + regulator-name = "BUCK5"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + // BUCK8 in datasheet + regulator-name = "BUCK6"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "LDO6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + rv1805: rtc@69 { + compatible = "abracon,ab1805"; + reg = <0x69>; + }; +}; + +&mu { + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; +}; + +&sai2 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clk IMX8MM_CLK_SAI2>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12000000>; + status = "disabled"; +}; + +&spdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif1>; + assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>, + <&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", + "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; + status = "disabled"; +}; + +&uart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MM_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + assigned-clocks = <&clk IMX8MM_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MM_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + assigned-clocks = <&clk IMX8MM_CLK_UART4>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + over-current-active-low; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "disabled"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; + bus-width = <8>; + vmmc-supply = <®_usdhc1_vmmc>; + keep-power-in-suspend; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + no-1-8-v; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; -- cgit From 708756e1972ebf817e1f9fb694df17d4c704a25f Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 28 Jan 2022 17:00:49 +0100 Subject: arm64: dts: imx8mm: fix strange hex notation Fix strange hex notation with mixed lower-case and upper-case letters. Signed-off-by: Marcel Ziswiler Reviewed-by: Laurent Pinchart Acked-by: Rob Herring Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h index a7411c800bef..83c8f715cd90 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h +++ b/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h @@ -280,7 +280,7 @@ #define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x150 0x3B8 0x000 0x1 0x0 #define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x150 0x3B8 0x4CC 0x2 0x1 #define MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0 -#define MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0x150 0x3B8 0x53c 0x4 0x0 +#define MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0x150 0x3B8 0x53C 0x4 0x0 #define MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0 #define MX8MM_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0 #define MX8MM_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x154 0x3BC 0x000 0x1 0x0 @@ -487,7 +487,7 @@ #define MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0 #define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x1D8 0x440 0x000 0x1 0x0 #define MX8MM_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2 -#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x1D8 0x440 0x4Fc 0x4 0x2 +#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x1D8 0x440 0x4FC 0x4 0x2 #define MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x1D8 0x440 0x000 0x4 0x0 #define MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0 #define MX8MM_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0 @@ -495,7 +495,7 @@ #define MX8MM_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0 #define MX8MM_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2 #define MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x1DC 0x444 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x1DC 0x444 0x4Fc 0x4 0x3 +#define MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x1DC 0x444 0x4FC 0x4 0x3 #define MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0 #define MX8MM_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0 #define MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0 -- cgit From d7a385660e242e9e22f68089ff036775dd742132 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Wed, 26 Jan 2022 16:49:40 +0800 Subject: arm64: dts: fsl-ls1028a-qds: Drop overlay syntax hard coding As suggested by commit 9ae8578b517a ("of: Documentation: change overlay example to use current syntax"), there is no need to have overlay syntax be hard coded in the device tree source file any more. Signed-off-by: Shawn Guo Reviewed-by: Vladimir Oltean --- .../boot/dts/freescale/fsl-ls1028a-qds-13bb.dts | 146 +++++++++------------ .../boot/dts/freescale/fsl-ls1028a-qds-65bb.dts | 138 ++++++++----------- .../boot/dts/freescale/fsl-ls1028a-qds-7777.dts | 99 ++++++-------- .../boot/dts/freescale/fsl-ls1028a-qds-85bb.dts | 134 ++++++++----------- .../boot/dts/freescale/fsl-ls1028a-qds-899b.dts | 86 +++++------- .../boot/dts/freescale/fsl-ls1028a-qds-9999.dts | 97 ++++++-------- 6 files changed, 298 insertions(+), 402 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts index f748a2c12a70..f826392c23fa 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts @@ -12,102 +12,80 @@ /dts-v1/; /plugin/; -/ { - fragment@0 { - target = <&mdio_slot1>; - - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - - slot1_sgmii: ethernet-phy@2 { - /* AQR112 */ - reg = <0x2>; - compatible = "ethernet-phy-ieee802.3-c45"; - }; - }; - }; - - fragment@1 { - target = <&enetc_port0>; - - __overlay__ { - phy-handle = <&slot1_sgmii>; - phy-mode = "usxgmii"; - managed = "in-band-status"; - status = "okay"; - }; +&mdio_slot1 { + #address-cells = <1>; + #size-cells = <0>; + + slot1_sgmii: ethernet-phy@2 { + /* AQR112 */ + reg = <0x2>; + compatible = "ethernet-phy-ieee802.3-c45"; }; +}; - fragment@2 { - target = <&mdio_slot2>; - - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - - /* 4 ports on AQR412 */ - slot2_qxgmii0: ethernet-phy@0 { - reg = <0x0>; - compatible = "ethernet-phy-ieee802.3-c45"; - }; - - slot2_qxgmii1: ethernet-phy@1 { - reg = <0x1>; - compatible = "ethernet-phy-ieee802.3-c45"; - }; +&enetc_port0 { + phy-handle = <&slot1_sgmii>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + status = "okay"; +}; - slot2_qxgmii2: ethernet-phy@2 { - reg = <0x2>; - compatible = "ethernet-phy-ieee802.3-c45"; - }; +&mdio_slot2 { + #address-cells = <1>; + #size-cells = <0>; - slot2_qxgmii3: ethernet-phy@3 { - reg = <0x3>; - compatible = "ethernet-phy-ieee802.3-c45"; - }; - }; + /* 4 ports on AQR412 */ + slot2_qxgmii0: ethernet-phy@0 { + reg = <0x0>; + compatible = "ethernet-phy-ieee802.3-c45"; }; - fragment@3 { - target = <&mscc_felix_ports>; + slot2_qxgmii1: ethernet-phy@1 { + reg = <0x1>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; - __overlay__ { - port@0 { - status = "okay"; - phy-handle = <&slot2_qxgmii0>; - phy-mode = "usxgmii"; - managed = "in-band-status"; - }; + slot2_qxgmii2: ethernet-phy@2 { + reg = <0x2>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; - port@1 { - status = "okay"; - phy-handle = <&slot2_qxgmii1>; - phy-mode = "usxgmii"; - managed = "in-band-status"; - }; + slot2_qxgmii3: ethernet-phy@3 { + reg = <0x3>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; +}; - port@2 { - status = "okay"; - phy-handle = <&slot2_qxgmii2>; - phy-mode = "usxgmii"; - managed = "in-band-status"; - }; +&mscc_felix_ports { + port@0 { + status = "okay"; + phy-handle = <&slot2_qxgmii0>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + }; - port@3 { - status = "okay"; - phy-handle = <&slot2_qxgmii3>; - phy-mode = "usxgmii"; - managed = "in-band-status"; - }; - }; + port@1 { + status = "okay"; + phy-handle = <&slot2_qxgmii1>; + phy-mode = "usxgmii"; + managed = "in-band-status"; }; - fragment@4 { - target = <&mscc_felix>; + port@2 { + status = "okay"; + phy-handle = <&slot2_qxgmii2>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + }; - __overlay__ { - status = "okay"; - }; + port@3 { + status = "okay"; + phy-handle = <&slot2_qxgmii3>; + phy-mode = "usxgmii"; + managed = "in-band-status"; }; }; + +&mscc_felix { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts index 8ffb707a1576..40d34c8384a5 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts @@ -11,98 +11,76 @@ /dts-v1/; /plugin/; -/ { - fragment@0 { - target = <&mdio_slot1>; - - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - - slot1_sgmii: ethernet-phy@2 { - /* AQR112 */ - reg = <0x2>; - compatible = "ethernet-phy-ieee802.3-c45"; - }; - }; - }; - - fragment@1 { - target = <&enetc_port0>; - - __overlay__ { - phy-handle = <&slot1_sgmii>; - phy-mode = "2500base-x"; - managed = "in-band-status"; - status = "okay"; - }; +&mdio_slot1 { + #address-cells = <1>; + #size-cells = <0>; + + slot1_sgmii: ethernet-phy@2 { + /* AQR112 */ + reg = <0x2>; + compatible = "ethernet-phy-ieee802.3-c45"; }; +}; - fragment@2 { - target = <&mdio_slot2>; - - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - - /* 4 ports on VSC8514 */ - slot2_qsgmii0: ethernet-phy@8 { - reg = <0x8>; - }; - - slot2_qsgmii1: ethernet-phy@9 { - reg = <0x9>; - }; +&enetc_port0 { + phy-handle = <&slot1_sgmii>; + phy-mode = "2500base-x"; + managed = "in-band-status"; + status = "okay"; +}; - slot2_qsgmii2: ethernet-phy@a { - reg = <0xa>; - }; +&mdio_slot2 { + #address-cells = <1>; + #size-cells = <0>; - slot2_qsgmii3: ethernet-phy@b { - reg = <0xb>; - }; - }; + /* 4 ports on VSC8514 */ + slot2_qsgmii0: ethernet-phy@8 { + reg = <0x8>; }; - fragment@3 { - target = <&mscc_felix_ports>; + slot2_qsgmii1: ethernet-phy@9 { + reg = <0x9>; + }; - __overlay__ { - port@0 { - status = "okay"; - phy-handle = <&slot2_qsgmii0>; - phy-mode = "qsgmii"; - managed = "in-band-status"; - }; + slot2_qsgmii2: ethernet-phy@a { + reg = <0xa>; + }; - port@1 { - status = "okay"; - phy-handle = <&slot2_qsgmii1>; - phy-mode = "qsgmii"; - managed = "in-band-status"; - }; + slot2_qsgmii3: ethernet-phy@b { + reg = <0xb>; + }; +}; - port@2 { - status = "okay"; - phy-handle = <&slot2_qsgmii2>; - phy-mode = "qsgmii"; - managed = "in-band-status"; - }; +&mscc_felix_ports { + port@0 { + status = "okay"; + phy-handle = <&slot2_qsgmii0>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; - port@3 { - status = "okay"; - phy-handle = <&slot2_qsgmii3>; - phy-mode = "qsgmii"; - managed = "in-band-status"; - }; - }; + port@1 { + status = "okay"; + phy-handle = <&slot2_qsgmii1>; + phy-mode = "qsgmii"; + managed = "in-band-status"; }; - fragment@4 { - target = <&mscc_felix>; + port@2 { + status = "okay"; + phy-handle = <&slot2_qsgmii2>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; - __overlay__ { - status = "okay"; - }; + port@3 { + status = "okay"; + phy-handle = <&slot2_qsgmii3>; + phy-mode = "qsgmii"; + managed = "in-band-status"; }; }; + +&mscc_felix { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts index eb6a1e674f10..1dff68d7484b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts @@ -12,71 +12,58 @@ /dts-v1/; /plugin/; -/ { - fragment@0 { - target = <&mdio_slot1>; +&mdio_slot1 { + #address-cells = <1>; + #size-cells = <0>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - - /* 4 ports on AQR412 */ - slot1_sxgmii0: ethernet-phy@0 { - reg = <0x0>; - compatible = "ethernet-phy-ieee802.3-c45"; - }; - - slot1_sxgmii1: ethernet-phy@1 { - reg = <0x1>; - compatible = "ethernet-phy-ieee802.3-c45"; - }; - - slot1_sxgmii2: ethernet-phy@2 { - reg = <0x2>; - compatible = "ethernet-phy-ieee802.3-c45"; - }; + /* 4 ports on AQR412 */ + slot1_sxgmii0: ethernet-phy@0 { + reg = <0x0>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; - slot1_sxgmii3: ethernet-phy@3 { - reg = <0x3>; - compatible = "ethernet-phy-ieee802.3-c45"; - }; - }; + slot1_sxgmii1: ethernet-phy@1 { + reg = <0x1>; + compatible = "ethernet-phy-ieee802.3-c45"; }; - fragment@1 { - target = <&mscc_felix_ports>; + slot1_sxgmii2: ethernet-phy@2 { + reg = <0x2>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; - __overlay__ { - port@0 { - status = "okay"; - phy-handle = <&slot1_sxgmii0>; - phy-mode = "2500base-x"; - }; + slot1_sxgmii3: ethernet-phy@3 { + reg = <0x3>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; +}; - port@1 { - status = "okay"; - phy-handle = <&slot1_sxgmii1>; - phy-mode = "2500base-x"; - }; +&mscc_felix_ports { + port@0 { + status = "okay"; + phy-handle = <&slot1_sxgmii0>; + phy-mode = "2500base-x"; + }; - port@2 { - status = "okay"; - phy-handle = <&slot1_sxgmii2>; - phy-mode = "2500base-x"; - }; + port@1 { + status = "okay"; + phy-handle = <&slot1_sxgmii1>; + phy-mode = "2500base-x"; + }; - port@3 { - status = "okay"; - phy-handle = <&slot1_sxgmii3>; - phy-mode = "2500base-x"; - }; - }; + port@2 { + status = "okay"; + phy-handle = <&slot1_sxgmii2>; + phy-mode = "2500base-x"; }; - fragment@2 { - target = <&mscc_felix>; - __overlay__ { - status = "okay"; - }; + port@3 { + status = "okay"; + phy-handle = <&slot1_sxgmii3>; + phy-mode = "2500base-x"; }; }; + +&mscc_felix { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts index 8e90c3088ba1..19424d349713 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts @@ -11,97 +11,75 @@ /dts-v1/; /plugin/; -/ { - fragment@0 { - target = <&mdio_slot1>; +&mdio_slot1 { + #address-cells = <1>; + #size-cells = <0>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - - slot1_sgmii: ethernet-phy@1c { - /* 1st port on VSC8234 */ - reg = <0x1c>; - }; - }; + slot1_sgmii: ethernet-phy@1c { + /* 1st port on VSC8234 */ + reg = <0x1c>; }; +}; - fragment@1 { - target = <&enetc_port0>; - - __overlay__ { - phy-handle = <&slot1_sgmii>; - phy-mode = "sgmii"; - managed = "in-band-status"; - status = "okay"; - }; - }; - - fragment@2 { - target = <&mdio_slot2>; - - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - - /* 4 ports on VSC8514 */ - slot2_qsgmii0: ethernet-phy@8 { - reg = <0x8>; - }; - - slot2_qsgmii1: ethernet-phy@9 { - reg = <0x9>; - }; +&enetc_port0 { + phy-handle = <&slot1_sgmii>; + phy-mode = "sgmii"; + managed = "in-band-status"; + status = "okay"; +}; - slot2_qsgmii2: ethernet-phy@a { - reg = <0xa>; - }; +&mdio_slot2 { + #address-cells = <1>; + #size-cells = <0>; - slot2_qsgmii3: ethernet-phy@b { - reg = <0xb>; - }; - }; + /* 4 ports on VSC8514 */ + slot2_qsgmii0: ethernet-phy@8 { + reg = <0x8>; }; - fragment@3 { - target = <&mscc_felix_ports>; + slot2_qsgmii1: ethernet-phy@9 { + reg = <0x9>; + }; - __overlay__ { - port@0 { - status = "okay"; - phy-handle = <&slot2_qsgmii0>; - phy-mode = "qsgmii"; - managed = "in-band-status"; - }; + slot2_qsgmii2: ethernet-phy@a { + reg = <0xa>; + }; - port@1 { - status = "okay"; - phy-handle = <&slot2_qsgmii1>; - phy-mode = "qsgmii"; - managed = "in-band-status"; - }; + slot2_qsgmii3: ethernet-phy@b { + reg = <0xb>; + }; +}; - port@2 { - status = "okay"; - phy-handle = <&slot2_qsgmii2>; - phy-mode = "qsgmii"; - managed = "in-band-status"; - }; +&mscc_felix_ports { + port@0 { + status = "okay"; + phy-handle = <&slot2_qsgmii0>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; - port@3 { - status = "okay"; - phy-handle = <&slot2_qsgmii3>; - phy-mode = "qsgmii"; - managed = "in-band-status"; - }; - }; + port@1 { + status = "okay"; + phy-handle = <&slot2_qsgmii1>; + phy-mode = "qsgmii"; + managed = "in-band-status"; }; - fragment@4 { - target = <&mscc_felix>; + port@2 { + status = "okay"; + phy-handle = <&slot2_qsgmii2>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; - __overlay__ { - status = "okay"; - }; + port@3 { + status = "okay"; + phy-handle = <&slot2_qsgmii3>; + phy-mode = "qsgmii"; + managed = "in-band-status"; }; }; + +&mscc_felix { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts index 5d0a094e6c44..fb85847f778f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts @@ -11,65 +11,51 @@ /dts-v1/; /plugin/; -/ { - fragment@0 { - target = <&mdio_slot1>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; +&mdio_slot1 { + #address-cells = <1>; + #size-cells = <0>; - /* VSC8234 */ - slot1_sgmii0: ethernet-phy@1c { - reg = <0x1c>; - }; - - slot1_sgmii1: ethernet-phy@1d { - reg = <0x1d>; - }; + /* VSC8234 */ + slot1_sgmii0: ethernet-phy@1c { + reg = <0x1c>; + }; - slot1_sgmii2: ethernet-phy@1e { - reg = <0x1e>; - }; + slot1_sgmii1: ethernet-phy@1d { + reg = <0x1d>; + }; - slot1_sgmii3: ethernet-phy@1f { - reg = <0x1f>; - }; - }; + slot1_sgmii2: ethernet-phy@1e { + reg = <0x1e>; }; - fragment@1 { - target = <&enetc_port0>; - __overlay__ { - phy-handle = <&slot1_sgmii0>; - phy-mode = "sgmii"; - managed = "in-band-status"; - status = "okay"; - }; + slot1_sgmii3: ethernet-phy@1f { + reg = <0x1f>; }; +}; - fragment@2 { - target = <&mscc_felix_ports>; - __overlay__ { - port@1 { - status = "okay"; - phy-handle = <&slot1_sgmii1>; - phy-mode = "sgmii"; - managed = "in-band-status"; - }; +&enetc_port0 { + phy-handle = <&slot1_sgmii0>; + phy-mode = "sgmii"; + managed = "in-band-status"; + status = "okay"; +}; - port@2 { - status = "okay"; - phy-handle = <&slot1_sgmii2>; - phy-mode = "sgmii"; - managed = "in-band-status"; - }; - }; +&mscc_felix_ports { + port@1 { + status = "okay"; + phy-handle = <&slot1_sgmii1>; + phy-mode = "sgmii"; + managed = "in-band-status"; }; - fragment@3 { - target = <&mscc_felix>; - __overlay__ { - status = "okay"; - }; + port@2 { + status = "okay"; + phy-handle = <&slot1_sgmii2>; + phy-mode = "sgmii"; + managed = "in-band-status"; }; }; + +&mscc_felix { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts index 1ef743c48e84..63e46fad22bd 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts @@ -11,69 +11,58 @@ /dts-v1/; /plugin/; -/ { - fragment@0 { - target = <&mdio_slot1>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; +&mdio_slot1 { + #address-cells = <1>; + #size-cells = <0>; - /* VSC8234 */ - slot1_sgmii0: ethernet-phy@1c { - reg = <0x1c>; - }; - - slot1_sgmii1: ethernet-phy@1d { - reg = <0x1d>; - }; + /* VSC8234 */ + slot1_sgmii0: ethernet-phy@1c { + reg = <0x1c>; + }; - slot1_sgmii2: ethernet-phy@1e { - reg = <0x1e>; - }; + slot1_sgmii1: ethernet-phy@1d { + reg = <0x1d>; + }; - slot1_sgmii3: ethernet-phy@1f { - reg = <0x1f>; - }; - }; + slot1_sgmii2: ethernet-phy@1e { + reg = <0x1e>; }; - fragment@1 { - target = <&mscc_felix_ports>; - __overlay__ { - port@0 { - status = "okay"; - phy-handle = <&slot1_sgmii0>; - phy-mode = "sgmii"; - managed = "in-band-status"; - }; + slot1_sgmii3: ethernet-phy@1f { + reg = <0x1f>; + }; +}; - port@1 { - status = "okay"; - phy-handle = <&slot1_sgmii1>; - phy-mode = "sgmii"; - managed = "in-band-status"; - }; +&mscc_felix_ports { + port@0 { + status = "okay"; + phy-handle = <&slot1_sgmii0>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; - port@2 { - status = "okay"; - phy-handle = <&slot1_sgmii2>; - phy-mode = "sgmii"; - managed = "in-band-status"; - }; + port@1 { + status = "okay"; + phy-handle = <&slot1_sgmii1>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; - port@3 { - status = "okay"; - phy-handle = <&slot1_sgmii3>; - phy-mode = "sgmii"; - managed = "in-band-status"; - }; - }; + port@2 { + status = "okay"; + phy-handle = <&slot1_sgmii2>; + phy-mode = "sgmii"; + managed = "in-band-status"; }; - fragment@2 { - target = <&mscc_felix>; - __overlay__ { - status = "okay"; - }; + port@3 { + status = "okay"; + phy-handle = <&slot1_sgmii3>; + phy-mode = "sgmii"; + managed = "in-band-status"; }; }; + +&mscc_felix { + status = "okay"; +}; -- cgit From 6f112d0fcf78226212f10350b372c8cd0bfaf919 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Wed, 26 Jan 2022 16:54:20 +0800 Subject: arm64: dts: freescale: Use overlay target for simplicity With commit 15d16d6dadf6 ("kbuild: Add generic rule to apply fdtoverlay"), overlay target can be used to simplify the build of DTB overlays. It also performs a cross check to ensure base DT and overlay actually match. Signed-off-by: Shawn Guo Reviewed-by: Vladimir Oltean --- arch/arm64/boot/dts/freescale/Makefile | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 9a5570025a54..f2785ce0781e 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -1,14 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 -# required for overlay support -DTC_FLAGS_fsl-ls1028a-qds := -@ -DTC_FLAGS_fsl-ls1028a-qds-13bb := -@ -DTC_FLAGS_fsl-ls1028a-qds-65bb := -@ -DTC_FLAGS_fsl-ls1028a-qds-7777 := -@ -DTC_FLAGS_fsl-ls1028a-qds-85bb := -@ -DTC_FLAGS_fsl-ls1028a-qds-899b := -@ -DTC_FLAGS_fsl-ls1028a-qds-9999 := -@ - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-oxalis.dtb @@ -21,12 +12,6 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var2.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var3-ads2.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var4.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-13bb.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-65bb.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-7777.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-85bb.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-899b.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-9999.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb @@ -49,6 +34,20 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-qds.dtb +fsl-ls1028a-qds-13bb-dtbs := fsl-ls1028a-qds.dtb fsl-ls1028a-qds-13bb.dtbo +fsl-ls1028a-qds-65bb-dtbs := fsl-ls1028a-qds.dtb fsl-ls1028a-qds-65bb.dtbo +fsl-ls1028a-qds-7777-dtbs := fsl-ls1028a-qds.dtb fsl-ls1028a-qds-7777.dtbo +fsl-ls1028a-qds-85bb-dtbs := fsl-ls1028a-qds.dtb fsl-ls1028a-qds-85bb.dtbo +fsl-ls1028a-qds-899b-dtbs := fsl-ls1028a-qds.dtb fsl-ls1028a-qds-899b.dtbo +fsl-ls1028a-qds-9999-dtbs := fsl-ls1028a-qds.dtb fsl-ls1028a-qds-9999.dtbo + +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-13bb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-65bb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-7777.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-85bb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-899b.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-9999.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-emcon-avari.dtb -- cgit From 9fb35e0d4d548a43adc7a31f212182ebd1dba187 Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Sat, 29 Jan 2022 15:26:17 -0500 Subject: arm64: dts: imx8mp-evk: add PCA6416 interrupt controller mode Add interrupt controller mode for the pca6416 on i.MX8MP EVK board's. Signed-off-by: Hugo Villeneuve Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 2eb943210678..9055ce32aecc 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -294,6 +294,12 @@ reg = <0x20>; gpio-controller; #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pca6416_int>; + interrupt-parent = <&gpio1>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; }; }; @@ -448,6 +454,12 @@ >; }; + pinctrl_pca6416_int: pca6416_int_grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* Input pull-up. */ + >; + }; + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 -- cgit From 6a57f224f7346c8d23596f2ef1ce360669926f54 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 11 Feb 2022 10:23:22 +0100 Subject: arm64: dts: freescale: add initial support for verdin imx8m mini This patch adds the device tree to support Toradex Verdin iMX8M Mini a computer on module which can be used on different carrier boards. The module consists of an NXP i.MX 8M Mini family SoC (either i.MX 8M Mini Quad or 8M Mini DualLite), a PCA9450A PMIC, a Gigabit Ethernet PHY, 1 or 2 GB of LPDDR4 RAM, an eMMC, a TLA2024 ADC, an I2C EEPROM, an RX8130 RTC, an optional SPI CAN controller plus an optional Bluetooth/ Wi-Fi module. Anything that is not self-contained on the module is disabled by default. The device tree for the Dahlia includes the module's device tree and enables the supported peripherals of the carrier board. The device tree for the Verdin Development Board includes the module's device tree as well as the Dahlia one as it is a superset and supports almost all peripherals available. So far there is no display functionality supported at all but basic console UART, PCIe, USB host, eMMC and Ethernet and PCIe functionality work fine. Signed-off-by: Marcel Ziswiler Acked-by: Krzysztof Kozlowski Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 4 + .../boot/dts/freescale/imx8mm-verdin-dahlia.dtsi | 150 +++ .../boot/dts/freescale/imx8mm-verdin-dev.dtsi | 67 ++ .../dts/freescale/imx8mm-verdin-nonwifi-dahlia.dts | 18 + .../dts/freescale/imx8mm-verdin-nonwifi-dev.dts | 18 + .../boot/dts/freescale/imx8mm-verdin-nonwifi.dtsi | 75 ++ .../dts/freescale/imx8mm-verdin-wifi-dahlia.dts | 18 + .../boot/dts/freescale/imx8mm-verdin-wifi-dev.dts | 18 + .../boot/dts/freescale/imx8mm-verdin-wifi.dtsi | 94 ++ arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 1264 ++++++++++++++++++++ 10 files changed, 1726 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dahlia.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dev.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dev.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index f2785ce0781e..d96eb4cbd990 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -63,6 +63,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7901.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7902.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dahlia.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dev.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-bsh-smm-s2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-bsh-smm-s2pro.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi new file mode 100644 index 000000000000..aca5ae0d307d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/ { + sound_card: sound-card { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,name = "imx8mm-wm8904"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "Headphone Jack", "MICBIAS", + "IN1L", "Headphone Jack"; + simple-audio-card,widgets = + "Microphone", "Headphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + dailink_master: simple-audio-card,codec { + clocks = <&clk IMX8MM_CLK_SAI2_ROOT>; + sound-dai = <&wm8904_1a>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + }; +}; + +/* Verdin SPI_1 */ +&ecspi2 { + status = "okay"; +}; + +/* EEPROM on display adapter boards */ +&eeprom_display_adapter { + status = "okay"; +}; + +/* EEPROM on Verdin Development board */ +&eeprom_carrier_board { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +/* Verdin QSPI_1 */ +&flexspi { + status = "okay"; +}; + +/* Current measurement into module VCC */ +&hwmon { + status = "okay"; +}; + +&hwmon_temp { + vs-supply = <®_1p8v>; + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +/* Verdin I2C_1 */ +&i2c4 { + status = "okay"; + + /* Audio Codec */ + wm8904_1a: audio-codec@1a { + compatible = "wlf,wm8904"; + AVDD-supply = <®_3p3v>; + clocks = <&clk IMX8MM_CLK_SAI2_ROOT>; + clock-names = "mclk"; + CPVDD-supply = <®_3p3v>; + DBVDD-supply = <®_3p3v>; + DCVDD-supply = <®_3p3v>; + MICVDD-supply = <®_3p3v>; + reg = <0x1a>; + #sound-dai-cells = <0>; + }; +}; + +/* Verdin PCIE_1 */ +&pcie0 { + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +/* Verdin PWM_3_DSI */ +&pwm1 { + status = "okay"; +}; + +/* Verdin PWM_1 */ +&pwm2 { + status = "okay"; +}; + +/* Verdin PWM_2 */ +&pwm3 { + status = "okay"; +}; + +/* VERDIN I2S_1 */ +&sai2 { + status = "okay"; +}; + +/* Verdin UART_3 */ +&uart1 { + status = "okay"; +}; + +/* Verdin UART_1 */ +&uart2 { + status = "okay"; +}; + +/* Verdin UART_2 */ +&uart3 { + status = "okay"; +}; + +/* Verdin USB_1 */ +&usbotg1 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usbotg2 { + status = "okay"; +}; + +/* Verdin SD_1 */ +&usdhc2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi new file mode 100644 index 000000000000..73cc3fafa018 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +#include "imx8mm-verdin-dahlia.dtsi" + +/ { + sound_card: sound-card { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,name = "imx8mm-nau8822"; + simple-audio-card,routing = + "Headphones", "LHP", + "Headphones", "RHP", + "Speaker", "LSPK", + "Speaker", "RSPK", + "Line Out", "AUXOUT1", + "Line Out", "AUXOUT2", + "LAUX", "Line In", + "RAUX", "Line In", + "LMICP", "Mic In", + "RMICP", "Mic In"; + simple-audio-card,widgets = + "Headphones", "Headphones", + "Line Out", "Line Out", + "Speaker", "Speaker", + "Microphone", "Mic In", + "Line", "Line In"; + + dailink_master: simple-audio-card,codec { + clocks = <&clk IMX8MM_CLK_SAI2_ROOT>; + sound-dai = <&nau8822_1a>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + }; +}; + +&gpio_expander_21 { + status = "okay"; +}; + +/* Verdin I2C_1 */ +&i2c4 { + /* Audio Codec */ + nau8822_1a: audio-codec@1a { + compatible = "nuvoton,nau8822"; + reg = <0x1a>; + }; +}; + +/* Verdin UART_1, connector X50 through RS485 transceiver */ +&uart2 { + linux,rs485-enabled-at-boot-time; + rs485-rts-active-low; + rs485-rx-during-tx; +}; + +/* Limit frequency on dev board due to long traces and bad signal integrity */ +&usdhc2 { + max-frequency = <100000000>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dahlia.dts b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dahlia.dts new file mode 100644 index 000000000000..d64ff378a152 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dahlia.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx8mm-verdin.dtsi" +#include "imx8mm-verdin-nonwifi.dtsi" +#include "imx8mm-verdin-dahlia.dtsi" + +/ { + model = "Toradex Verdin iMX8M Mini on Dahlia Board"; + compatible = "toradex,verdin-imx8mm-nonwifi-dahlia", + "toradex,verdin-imx8mm-nonwifi", + "toradex,verdin-imx8mm", + "fsl,imx8mm"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dev.dts b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dev.dts new file mode 100644 index 000000000000..6ae71ecac8de --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dev.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx8mm-verdin.dtsi" +#include "imx8mm-verdin-nonwifi.dtsi" +#include "imx8mm-verdin-dev.dtsi" + +/ { + model = "Toradex Verdin iMX8M Mini on Verdin Development Board"; + compatible = "toradex,verdin-imx8mm-nonwifi-dev", + "toradex,verdin-imx8mm-nonwifi", + "toradex,verdin-imx8mm", + "fsl,imx8mm"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi.dtsi new file mode 100644 index 000000000000..1e0f87c7a609 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +&gpio3 { + gpio-line-names = "SODIMM_52", + "SODIMM_54", + "SODIMM_64", + "SODIMM_21", + "SODIMM_206", + "SODIMM_76", + "SODIMM_56", + "SODIMM_58", + "SODIMM_60", + "SODIMM_62", + "SODIMM_162", + "SODIMM_164", + "SODIMM_166", + "SODIMM_168", + "SODIMM_66", + "SODIMM_17", + "", + "SODIMM_156", + "SODIMM_160", + "SODIMM_244", + "", + "SODIMM_48", + "SODIMM_44", + "SODIMM_42", + "SODIMM_46"; +}; + +&gpio4 { + gpio-line-names = "SODIMM_102", + "SODIMM_90", + "SODIMM_92", + "SODIMM_94", + "SODIMM_96", + "SODIMM_100", + "SODIMM_148", + "SODIMM_152", + "SODIMM_154", + "SODIMM_174", + "SODIMM_120", + "SODIMM_104", + "SODIMM_106", + "SODIMM_108", + "SODIMM_112", + "SODIMM_114", + "SODIMM_116", + "SODIMM_150", + "SODIMM_118", + "", + "SODIMM_88", + "SODIMM_149", + "SODIMM_147", + "SODIMM_36", + "SODIMM_32", + "SODIMM_30", + "SODIMM_34", + "SODIMM_38", + "SODIMM_252", + "SODIMM_133", + "SODIMM_135", + "SODIMM_129"; +}; + +&usdhc3 { + bus-width = <4>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dts b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dts new file mode 100644 index 000000000000..d424c475cba1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx8mm-verdin.dtsi" +#include "imx8mm-verdin-wifi.dtsi" +#include "imx8mm-verdin-dahlia.dtsi" + +/ { + model = "Toradex Verdin iMX8M Mini WB on Dahlia Board"; + compatible = "toradex,verdin-imx8mm-wifi-dahlia", + "toradex,verdin-imx8mm-wifi", + "toradex,verdin-imx8mm", + "fsl,imx8mm"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dev.dts b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dev.dts new file mode 100644 index 000000000000..ef952021832e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dev.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx8mm-verdin.dtsi" +#include "imx8mm-verdin-wifi.dtsi" +#include "imx8mm-verdin-dev.dtsi" + +/ { + model = "Toradex Verdin iMX8M Mini WB on Verdin Development Board"; + compatible = "toradex,verdin-imx8mm-wifi-dev", + "toradex,verdin-imx8mm-wifi", + "toradex,verdin-imx8mm", + "fsl,imx8mm"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi new file mode 100644 index 000000000000..3e06a6ce3406 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/ { + reg_wifi_en: regulator-wifi-en { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_pwr_en>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "PDn_AW-CM276NF"; + startup-delay-us = <2000>; + }; +}; + +/* On-module Wi-Fi */ +&usdhc3 { + bus-width = <4>; + keep-power-in-suspend; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wifi_ctrl>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_wifi_ctrl>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_wifi_ctrl>; + vmmc-supply = <®_wifi_en>; + status = "okay"; +}; + +&gpio3 { + gpio-line-names = "SODIMM_52", + "SODIMM_54", + "SODIMM_64", + "SODIMM_21", + "SODIMM_206", + "SODIMM_76", + "SODIMM_56", + "SODIMM_58", + "SODIMM_60", + "SODIMM_62", + "", + "", + "", + "", + "SODIMM_66", + "SODIMM_17", + "", + "", + "", + "SODIMM_244", + "", + "SODIMM_48", + "SODIMM_44", + "SODIMM_42", + "SODIMM_46"; +}; + +&gpio4 { + gpio-line-names = "SODIMM_102", + "SODIMM_90", + "SODIMM_92", + "SODIMM_94", + "SODIMM_96", + "SODIMM_100", + "", + "", + "", + "", + "SODIMM_120", + "SODIMM_104", + "SODIMM_106", + "SODIMM_108", + "SODIMM_112", + "SODIMM_114", + "SODIMM_116", + "", + "SODIMM_118", + "", + "SODIMM_88", + "SODIMM_149", + "SODIMM_147", + "SODIMM_36", + "SODIMM_32", + "SODIMM_30", + "SODIMM_34", + "SODIMM_38", + "SODIMM_252", + "SODIMM_133", + "SODIMM_135", + "SODIMM_129"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi new file mode 100644 index 000000000000..0d84d29e70f1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -0,0 +1,1264 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +#include "dt-bindings/phy/phy-imx8-pcie.h" +#include "dt-bindings/pwm/pwm.h" +#include "imx8mm.dtsi" + +/ { + chosen { + stdout-path = &uart1; + }; + + aliases { + rtc0 = &rtc_i2c; + rtc1 = &snvs_rtc; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */ + enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>; + power-supply = <®_3p3v>; + /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */ + pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>; + status = "disabled"; + }; + + /* Fixed clock dedicated to SPI CAN controller */ + clk20m: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + wakeup { + debounce-interval = <10>; + /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ + gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; + label = "Wake-Up"; + linux,code = ; + wakeup-source; + }; + }; + + /* Carrier Board Supplies */ + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8_SW"; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_SW"; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "+V5_SW"; + }; + + /* Non PMIC On-module Supplies */ + reg_ethphy: regulator-ethphy { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */ + off-on-delay = <500000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_eth>; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_ETH"; + startup-delay-us = <200000>; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1 { + compatible = "regulator-fixed"; + enable-active-high; + /* Verdin USB_1_EN (SODIMM 155) */ + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb1_en>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "usb_otg1_vbus"; + }; + + reg_usb_otg2_vbus: regulator-usb-otg2 { + compatible = "regulator-fixed"; + enable-active-high; + /* Verdin USB_2_EN (SODIMM 185) */ + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb2_en>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "usb_otg2_vbus"; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + enable-active-high; + /* Verdin SD_1_PWR_EN (SODIMM 76) */ + gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; + off-on-delay = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_SD"; + startup-delay-us = <2000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Use the kernel configuration settings instead */ + /delete-node/ linux,cma; + }; +}; + +&A53_0 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_1 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_2 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_3 { + cpu-supply = <®_vdd_arm>; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-750M { + opp-hz = /bits/ 64 <750000000>; + }; + }; +}; + +/* Verdin SPI_1 */ +&ecspi2 { + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; +}; + +/* Verdin CAN_1 (On-module) */ +&ecspi3 { + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; + + can1: can@0 { + compatible = "microchip,mcp251xfd"; + clocks = <&clk20m>; + interrupts-extended = <&gpio1 6 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_int>; + reg = <0>; + spi-max-frequency = <8500000>; + }; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&fec1 { + fsl,magic-packet; + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + phy-supply = <®_ethphy>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_fec1>; + pinctrl-1 = <&pinctrl_fec1_sleep>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <0>; + reg = <7>; + }; + }; +}; + +/* Verdin QSPI_1 */ +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; +}; + +&gpio1 { + gpio-line-names = "SODIMM_216", + "SODIMM_19", + "", + "", + "", + "", + "", + "", + "SODIMM_220", + "SODIMM_222", + "", + "SODIMM_218", + "SODIMM_155", + "SODIMM_157", + "SODIMM_185", + "SODIMM_187"; +}; + +&gpio2 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_84", + "SODIMM_78", + "SODIMM_74", + "SODIMM_80", + "SODIMM_82", + "SODIMM_70", + "SODIMM_72"; +}; + +&gpio5 { + gpio-line-names = "SODIMM_131", + "", + "SODIMM_91", + "SODIMM_16", + "SODIMM_15", + "SODIMM_208", + "SODIMM_137", + "SODIMM_139", + "SODIMM_141", + "SODIMM_143", + "SODIMM_196", + "SODIMM_200", + "SODIMM_198", + "SODIMM_202", + "", + "", + "SODIMM_55", + "SODIMM_53", + "SODIMM_95", + "SODIMM_93", + "SODIMM_14", + "SODIMM_12", + "", + "", + "", + "", + "SODIMM_210", + "SODIMM_212", + "SODIMM_151", + "SODIMM_153"; + + ctrl_sleep_moci-hog { + gpio-hog; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpios = <1 GPIO_ACTIVE_HIGH>; + line-name = "CTRL_SLEEP_MOCI#"; + output-high; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; + }; +}; + +/* On-module I2C */ +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pca9450: pmic@25 { + compatible = "nxp,pca9450a"; + interrupt-parent = <&gpio1>; + /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + reg = <0x25>; + sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + + regulators { + reg_vdd_soc: BUCK1 { + nxp,dvs-run-voltage = <850000>; + nxp,dvs-standby-voltage = <800000>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <850000>; + regulator-min-microvolt = <800000>; + regulator-name = "+VDD_SOC"; + regulator-ramp-delay = <3125>; + }; + + reg_vdd_arm: BUCK2 { + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <950000>; + regulator-min-microvolt = <850000>; + regulator-name = "+VDD_ARM"; + regulator-ramp-delay = <3125>; + }; + + reg_vdd_dram: BUCK3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <950000>; + regulator-min-microvolt = <850000>; + regulator-name = "+VDD_GPU_VPU_DDR"; + }; + + reg_vdd_3v3: BUCK4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3"; + }; + + reg_vdd_1v8: BUCK5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "PWR_1V8_MOCI"; + }; + + reg_nvcc_dram: BUCK6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1100000>; + regulator-min-microvolt = <1100000>; + regulator-name = "+VDD_DDR"; + }; + + reg_nvcc_snvs: LDO1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8_SNVS"; + }; + + reg_vdd_snvs: LDO2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <900000>; + regulator-min-microvolt = <800000>; + regulator-name = "+V0.8_SNVS"; + }; + + reg_vdda: LDO3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8A"; + }; + + reg_vdd_phy: LDO4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <900000>; + regulator-min-microvolt = <900000>; + regulator-name = "+V0.9_MIPI"; + }; + + reg_nvcc_sd: LDO5 { + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V3.3_1.8_SD"; + }; + }; + }; + + rtc_i2c: rtc@32 { + compatible = "epson,rx8130"; + reg = <0x32>; + }; + + adc@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + /* Verdin I2C_1 (ADC_4 - ADC_3) */ + channel@0 { + reg = <0>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin I2C_1 (ADC_4 - ADC_1) */ + channel@1 { + reg = <1>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin I2C_1 (ADC_3 - ADC_1) */ + channel@2 { + reg = <2>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin I2C_1 (ADC_2 - ADC_1) */ + channel@3 { + reg = <3>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin I2C_1 ADC_4 */ + channel@4 { + reg = <4>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin I2C_1 ADC_3 */ + channel@5 { + reg = <5>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin I2C_1 ADC_2 */ + channel@6 { + reg = <6>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin I2C_1 ADC_1 */ + channel@7 { + reg = <7>; + ti,datarate = <4>; + ti,gain = <2>; + }; + }; + + eeprom@50 { + compatible = "st,24c02"; + pagesize = <16>; + reg = <0x50>; + }; +}; + +/* Verdin I2C_2_DSI */ +&i2c2 { + clock-frequency = <10000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "disabled"; +}; + +/* Verdin I2C_3_HDMI N/A */ + +/* Verdin I2C_4_CSI */ +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +/* Verdin I2C_1 */ +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + gpio_expander_21: gpio-expander@21 { + compatible = "nxp,pcal6416"; + #gpio-cells = <2>; + gpio-controller; + reg = <0x21>; + vcc-supply = <®_3p3v>; + status = "disabled"; + }; + + lvds_ti_sn65dsi83: bridge@2c { + compatible = "ti,sn65dsi83"; + /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */ + /* Verdin GPIO_10_DSI (SODIMM 21) */ + enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_10_dsi>; + reg = <0x2c>; + status = "disabled"; + }; + + /* Current measurement into module VCC */ + hwmon: hwmon@40 { + compatible = "ti,ina219"; + reg = <0x40>; + shunt-resistor = <10000>; + status = "disabled"; + }; + + hdmi_lontium_lt8912: hdmi@48 { + compatible = "lontium,lt8912b"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>; + reg = <0x48>; + /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */ + /* Verdin GPIO_10_DSI (SODIMM 21) */ + reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>; + status = "disabled"; + }; + + atmel_mxt_ts: touch@4a { + compatible = "atmel,maxtouch"; + /* Verdin GPIO_9_DSI */ + /* (TOUCH_INT#, SODIMM 17, also routed to SN65dsi83 IRQ albeit currently unused) */ + interrupt-parent = <&gpio3>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>; + reg = <0x4a>; + /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */ + reset-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + /* Temperature sensor on carrier board */ + hwmon_temp: sensor@4f { + compatible = "ti,tmp75c"; + reg = <0x4f>; + status = "disabled"; + }; + + /* EEPROM on display adapter (MIPI DSI Display Adapter) */ + eeprom_display_adapter: eeprom@50 { + compatible = "st,24c02"; + pagesize = <16>; + reg = <0x50>; + status = "disabled"; + }; + + /* EEPROM on carrier board */ + eeprom_carrier_board: eeprom@57 { + compatible = "st,24c02"; + pagesize = <16>; + reg = <0x57>; + status = "disabled"; + }; +}; + +/* Verdin PCIE_1 */ +&pcie0 { + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + assigned-clock-rates = <10000000>, <250000000>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_PHY>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + /* PCIE_1_RESET# (SODIMM 244) */ + reset-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; +}; + +&pcie_phy { + clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; + fsl,clkreq-unsupported; + fsl,refclk-pad-mode = ; + fsl,tx-deemph-gen1 = <0x2d>; + fsl,tx-deemph-gen2 = <0xf>; +}; + +/* Verdin PWM_3_DSI */ +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_1>; + #pwm-cells = <3>; +}; + +/* Verdin PWM_1 */ +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_2>; + #pwm-cells = <3>; +}; + +/* Verdin PWM_2 */ +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_3>; + #pwm-cells = <3>; +}; + +/* VERDIN I2S_1 */ +&sai2 { + #sound-dai-cells = <0>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + assigned-clocks = <&clk IMX8MM_CLK_SAI2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +/* Verdin UART_3, used as the Linux console */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; + +/* Verdin UART_1 */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; +}; + +/* Verdin UART_2 */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; +}; + +/* Verdin UART_4 */ +/* + * Resource allocated to M4 by default, must not be accessed from Cortex-A35 or you get an OOPS + */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; +}; + +/* Verdin USB_1 */ +&usbotg1 { + adp-disable; + dr_mode = "otg"; + hnp-disable; + over-current-active-low; + samsung,picophy-dc-vol-level-adjust = <7>; + samsung,picophy-pre-emp-curr-control = <3>; + srp-disable; + vbus-supply = <®_usb_otg1_vbus>; +}; + +/* Verdin USB_2 */ +&usbotg2 { + dr_mode = "host"; + over-current-active-low; + samsung,picophy-dc-vol-level-adjust = <7>; + samsung,picophy-pre-emp-curr-control = <3>; + vbus-supply = <®_usb_otg2_vbus>; +}; + +&usbphynop1 { + vcc-supply = <®_vdd_3v3>; +}; + +&usbphynop2 { + vcc-supply = <®_vdd_3v3>; +}; + +/* On-module eMMC */ +&usdhc1 { + bus-width = <8>; + keep-power-in-suspend; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + status = "okay"; +}; + +/* Verdin SD_1 */ +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; + vmmc-supply = <®_usdhc2_vmmc>; +}; + +&wdog1 { + fsl,ext-reset-output; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, + <&pinctrl_gpio3>, <&pinctrl_gpio4>, + <&pinctrl_gpio7>, <&pinctrl_gpio8>, + <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>, + <&pinctrl_pmic_tpm_ena>; + + pinctrl_can1_int: can1intgrp { + fsl,pins = + ; /* CAN_1_SPI_INT#_1.8V */ + }; + + pinctrl_can2_int: can2intgrp { + fsl,pins = + ; /* CAN_2_SPI_INT#_1.8V */ + }; + + pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { + fsl,pins = + ; /* SODIMM 256 */ + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = + , /* SODIMM 196 */ + , /* SODIMM 200 */ + , /* SODIMM 198 */ + ; /* SODIMM 202 */ + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = + , /* CAN_SPI_SCK_1.8V */ + , /* CAN_SPI_MOSI_1.8V */ + , /* CAN_SPI_MISO_1.8V */ + , /* CAN_1_SPI_CS_1.8V# */ + ; /* CAN_2_SPI_CS#_1.8V */ + }; + + pinctrl_fec1: fec1grp { + fsl,pins = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_fec1_sleep: fec1-sleepgrp { + fsl,pins = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = + , /* SODIMM 52 */ + , /* SODIMM 54 */ + , /* SODIMM 64 */ + , /* SODIMM 66 */ + , /* SODIMM 56 */ + , /* SODIMM 58 */ + , /* SODIMM 60 */ + ; /* SODIMM 62 */ + }; + + pinctrl_gpio1: gpio1grp { + fsl,pins = + ; /* SODIMM 206 */ + }; + + pinctrl_gpio2: gpio2grp { + fsl,pins = + ; /* SODIMM 208 */ + }; + + pinctrl_gpio3: gpio3grp { + fsl,pins = + ; /* SODIMM 210 */ + }; + + pinctrl_gpio4: gpio4grp { + fsl,pins = + ; /* SODIMM 212 */ + }; + + pinctrl_gpio5: gpio5grp { + fsl,pins = + ; /* SODIMM 216 */ + }; + + pinctrl_gpio6: gpio6grp { + fsl,pins = + ; /* SODIMM 218 */ + }; + + pinctrl_gpio7: gpio7grp { + fsl,pins = + ; /* SODIMM 220 */ + }; + + pinctrl_gpio8: gpio8grp { + fsl,pins = + ; /* SODIMM 222 */ + }; + + /* Verdin GPIO_9_DSI (pulled-up as active-low) */ + pinctrl_gpio_9_dsi: gpio9dsigrp { + fsl,pins = + ; /* SODIMM 17 */ + }; + + /* Verdin GPIO_10_DSI */ + pinctrl_gpio_10_dsi: gpio10dsigrp { + fsl,pins = + ; /* SODIMM 21 */ + }; + + pinctrl_gpio_hog1: gpiohog1grp { + fsl,pins = + , /* SODIMM 88 */ + , /* SODIMM 90 */ + , /* SODIMM 92 */ + , /* SODIMM 94 */ + , /* SODIMM 96 */ + , /* SODIMM 100 */ + , /* SODIMM 102 */ + , /* SODIMM 104 */ + , /* SODIMM 106 */ + , /* SODIMM 108 */ + , /* SODIMM 112 */ + , /* SODIMM 114 */ + , /* SODIMM 116 */ + , /* SODIMM 118 */ + ; /* SODIMM 120 */ + }; + + pinctrl_gpio_hog2: gpiohog2grp { + fsl,pins = + ; /* SODIMM 91 */ + }; + + pinctrl_gpio_hog3: gpiohog3grp { + fsl,pins = + , /* SODIMM 157 */ + ; /* SODIMM 187 */ + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = + ; /* SODIMM 252 */ + }; + + /* On-module I2C */ + pinctrl_i2c1: i2c1grp { + fsl,pins = + , /* PMIC_I2C_SCL */ + ; /* PMIC_I2C_SDA */ + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = + , /* PMIC_I2C_SCL */ + ; /* PMIC_I2C_SDA */ + }; + + /* Verdin I2C_4_CSI */ + pinctrl_i2c2: i2c2grp { + fsl,pins = + , /* SODIMM 55 */ + ; /* SODIMM 53 */ + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = + , /* SODIMM 55 */ + ; /* SODIMM 53 */ + }; + + /* Verdin I2C_2_DSI */ + pinctrl_i2c3: i2c3grp { + fsl,pins = + , /* SODIMM 95 */ + ; /* SODIMM 93 */ + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = + , /* SODIMM 95 */ + ; /* SODIMM 93 */ + }; + + /* Verdin I2C_1 */ + pinctrl_i2c4: i2c4grp { + fsl,pins = + , /* SODIMM 14 */ + ; /* SODIMM 12 */ + }; + + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = + , /* SODIMM 14 */ + ; /* SODIMM 12 */ + }; + + /* Verdin I2S_2_BCLK (TOUCH_RESET#) */ + pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp { + fsl,pins = + ; /* SODIMM 42 */ + }; + + /* Verdin I2S_2_D_OUT shared with SAI5 */ + pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp { + fsl,pins = + ; /* SODIMM 46 */ + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = + , /* SODIMM 244 */ + /* PMIC_EN_PCIe_CLK, unused */ + ; + }; + + pinctrl_pmic: pmicirqgrp { + fsl,pins = + ; /* PMIC_INT# */ + }; + + /* Verdin PWM_3_DSI shared with GPIO1_IO1 */ + pinctrl_pwm_1: pwm1grp { + fsl,pins = + ; /* SODIMM 19 */ + }; + + pinctrl_pwm_2: pwm2grp { + fsl,pins = + ; /* SODIMM 15 */ + }; + + pinctrl_pwm_3: pwm3grp { + fsl,pins = + ; /* SODIMM 16 */ + }; + + /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */ + pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp { + fsl,pins = + ; /* SODIMM 19 */ + }; + + pinctrl_reg_eth: regethgrp { + fsl,pins = + ; /* PMIC_EN_ETH */ + }; + + pinctrl_reg_usb1_en: regusb1engrp { + fsl,pins = + ; /* SODIMM 155 */ + }; + + pinctrl_reg_usb2_en: regusb2engrp { + fsl,pins = + ; /* SODIMM 185 */ + }; + + pinctrl_sai2: sai2grp { + fsl,pins = + , /* SODIMM 32 */ + , /* SODIMM 30 */ + , /* SODIMM 38 */ + , /* SODIMM 36 */ + ; /* SODIMM 34 */ + }; + + pinctrl_sai5: sai5grp { + fsl,pins = + , /* SODIMM 48 */ + , /* SODIMM 44 */ + , /* SODIMM 42 */ + ; /* SODIMM 46 */ + }; + + /* control signal for optional ATTPM20P or SE050 */ + pinctrl_pmic_tpm_ena: pmictpmenagrp { + fsl,pins = + ; /* PMIC_TPM_ENA */ + }; + + pinctrl_tsp: tspgrp { + fsl,pins = + , /* SODIMM 148 */ + , /* SODIMM 152 */ + , /* SODIMM 154 */ + , /* SODIMM 174 */ + ; /* SODIMM 150 */ + }; + + pinctrl_uart1: uart1grp { + fsl,pins = + , /* SODIMM 149 */ + ; /* SODIMM 147 */ + }; + + pinctrl_uart2: uart2grp { + fsl,pins = + , /* SODIMM 129 */ + , /* SODIMM 131 */ + , /* SODIMM 133 */ + ; /* SODIMM 135 */ + }; + + pinctrl_uart3: uart3grp { + fsl,pins = + , /* SODIMM 137 */ + , /* SODIMM 139 */ + , /* SODIMM 141 */ + ; /* SODIMM 143 */ + }; + + pinctrl_uart4: uart4grp { + fsl,pins = + , /* SODIMM 151 */ + ; /* SODIMM 153 */ + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_cd: usdhc2cdgrp { + fsl,pins = + ; /* SODIMM 84 */ + }; + + pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { + fsl,pins = + ; /* SODIMM 76 */ + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = + , /* SODIMM 78 */ + , /* SODIMM 74 */ + , /* SODIMM 80 */ + , /* SODIMM 82 */ + , /* SODIMM 70 */ + , /* SODIMM 72 */ + ; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = + , + , + , + , + , + , + ; + }; + + /* On-module Wi-Fi/BT or type specific SDHC interface */ + /* (e.g. on X52 extension slot of Verdin Development Board) */ + pinctrl_usdhc3: usdhc3grp { + fsl,pins = + , + , + , + , + , + ; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = + , + , + , + , + , + ; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = + , + , + , + , + , + ; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = + ; /* PMIC_WDI */ + }; + + pinctrl_wifi_ctrl: wifictrlgrp { + fsl,pins = + , /* WIFI_WKUP_BT */ + , /* WIFI_W_WKUP_HOST */ + ; /* WIFI_WKUP_WLAN */ + }; + + pinctrl_wifi_i2s: bti2sgrp { + fsl,pins = + , /* WIFI_TX_BCLK */ + , /* WIFI_TX_DATA0 */ + , /* WIFI_TX_SYNC */ + ; /* WIFI_RX_DATA0 */ + }; + + pinctrl_wifi_pwr_en: wifipwrengrp { + fsl,pins = + ; /* PMIC_EN_WIFI */ + }; +}; -- cgit From 810028668c6d9da25664195d6b906c98a8169f72 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Wed, 9 Feb 2022 22:55:46 +0100 Subject: arm64: dts: rockchip: add gpu node to rk356x Rockchip SoCs RK3566 and RK3568 have a Mali Gondul core which is based on the Bifrost architecture. It has one shader core and two execution engines. Quoting the datasheet: Mali-G52 1-Core-2EE * Support 1600Mpix/s fill rate when 800MHz clock frequency * Support 38.4GLOPs when 800MHz clock frequency Signed-off-by: Ezequiel Garcia Signed-off-by: Alex Bee Signed-off-by: Michael Riesch Link: https://lore.kernel.org/r/20220209215549.94524-3-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 49 ++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index ff1689283996..50bbea862a6a 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -144,6 +144,40 @@ }; }; + gpu_opp_table: opp-table-1 { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <825000>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <825000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <825000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <825000>; + }; + + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <900000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1000000>; + }; + }; + pmu { compatible = "arm,cortex-a55-pmu"; interrupts = , @@ -444,6 +478,21 @@ }; }; + gpu: gpu@fde60000 { + compatible = "rockchip,rk3568-mali", "arm,mali-bifrost"; + reg = <0x0 0xfde60000 0x0 0x4000>; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + clocks = <&scmi_clk 1>, <&cru CLK_GPU>; + clock-names = "gpu", "bus"; + #cooling-cells = <2>; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&power RK3568_PD_GPU>; + status = "disabled"; + }; + sdmmc2: mmc@fe000000 { compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe000000 0x0 0x4000>; -- cgit From c0a7259fad2df72469b602418083516c2cb3a7af Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Wed, 9 Feb 2022 22:55:47 +0100 Subject: arm64: dts: rockchip: add cooling map and trip points for gpu to rk356x RK356x SoCs have a second thermal sensor for the GPU. This adds the cooling map and trip points for it to make use of its contribution as a cooling device. Signed-off-by: Alex Bee Signed-off-by: Michael Riesch Link: https://lore.kernel.org/r/20220209215549.94524-4-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 50bbea862a6a..80e3a3a2ab0f 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -1093,6 +1093,32 @@ polling-delay = <1000>; /* milliseconds */ thermal-sensors = <&tsadc 1>; + + trips { + gpu_threshold: gpu-threshold { + temperature = <70000>; + hysteresis = <2000>; + type = "passive"; + }; + gpu_target: gpu-target { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + gpu_crit: gpu-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_target>; + cooling-device = + <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; }; -- cgit From 6ac383456452378de07e55fc687069d1898a567d Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Wed, 9 Feb 2022 22:55:48 +0100 Subject: arm64: dts: rockchip: enable the gpu on quartz64-a Enable the GPU core on the Pine64 Quartz64 Model A. Signed-off-by: Ezequiel Garcia Signed-off-by: Alex Bee Signed-off-by: Michael Riesch Link: https://lore.kernel.org/r/20220209215549.94524-5-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts index 868ddac96433..6af09d2df600 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts @@ -243,6 +243,11 @@ status = "okay"; }; +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + &i2c0 { status = "okay"; -- cgit From 0f546cd635ee802429c87b47fffc45d856580fcd Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Wed, 9 Feb 2022 22:55:49 +0100 Subject: arm64: dts: rockchip: enable the gpu on rk3568-evb1-v10 Enable the GPU core on the Rockchip RK3568 EVB1. Signed-off-by: Michael Riesch [moved tsadc into a separate patch] Link: https://lore.kernel.org/r/20220209215549.94524-6-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts index d8a4f7a9f562..ea18303f6532 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts @@ -140,6 +140,11 @@ status = "okay"; }; +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + &i2c0 { status = "okay"; -- cgit From 679f048a10d8322d79010e0e52f18a6c17bdf306 Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Wed, 9 Feb 2022 22:55:49 +0100 Subject: arm64: dts: rockchip: enable the tsadc on rk3568-evb1-v10 Enable the thermal adc on the Rockchip RK3568 EVB1. Signed-off-by: Michael Riesch Link: https://lore.kernel.org/r/20220209215549.94524-6-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts index ea18303f6532..39c495ff0157 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts @@ -467,6 +467,12 @@ status = "okay"; }; +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + &uart2 { status = "okay"; }; -- cgit From eae8273f9bddc5c5dd466fdc6ced852f08e8f36c Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Tue, 1 Feb 2022 18:27:47 +0100 Subject: arm64: dts: broadcom: Add reference to RPi Zero 2 W This adds a reference to the dts of the Raspberry Pi Zero 2 W, so we don't need to maintain the content in arm64. Signed-off-by: Stefan Wahren Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/Makefile | 3 ++- arch/arm64/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile index c6882032a428..5082fcd1fea5 100644 --- a/arch/arm64/boot/dts/broadcom/Makefile +++ b/arch/arm64/boot/dts/broadcom/Makefile @@ -5,7 +5,8 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-400.dtb \ bcm2837-rpi-3-a-plus.dtb \ bcm2837-rpi-3-b.dtb \ bcm2837-rpi-3-b-plus.dtb \ - bcm2837-rpi-cm3-io3.dtb + bcm2837-rpi-cm3-io3.dtb \ + bcm2837-rpi-zero-2-w.dtb subdir-y += bcm4908 subdir-y += northstar2 diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts new file mode 100644 index 000000000000..307ae693e4a0 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts @@ -0,0 +1,2 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "arm/bcm2837-rpi-zero-2-w.dts" -- cgit From 47513f6dd93b5b7d91143219c2c1fb883664ed13 Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Wed, 9 Feb 2022 21:14:17 +0100 Subject: arm64: dts: broadcom: bcm4908: add watchdog block MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit BCM4908 has the same watchdog as BCM63xx devices. Use "brcm,bcm6345-wdt" binding which matches the first SoC with that block. Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi index 255c1ea2add4..f76b3dbf67ac 100644 --- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi @@ -276,6 +276,15 @@ twd: timer-mfd@400 { compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon"; reg = <0x400 0x4c>; + ranges = <0x0 0x400 0x4c>; + + #address-cells = <1>; + #size-cells = <1>; + + watchdog@28 { + compatible = "brcm,bcm6345-wdt"; + reg = <0x28 0x8>; + }; }; gpio0: gpio-controller@500 { -- cgit From 79c5f0e52d29a688a951fc818394b529e7e77e3e Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sat, 29 Jan 2022 23:38:02 -0600 Subject: arm64: dts: rockchip: Add pdm node to rk356x rk356x contains a PDM microphone controller which is compatible with the existing rockchip,pdm binding. Add its node. Signed-off-by: Samuel Holland Link: https://lore.kernel.org/r/20220130053803.43660-2-samuel@sholland.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 80e3a3a2ab0f..e20ee3968b5a 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -770,6 +770,27 @@ status = "disabled"; }; + pdm: pdm@fe440000 { + compatible = "rockchip,rk3568-pdm"; + reg = <0x0 0xfe440000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; + clock-names = "pdm_clk", "pdm_hclk"; + dmas = <&dmac1 9>; + dma-names = "rx"; + pinctrl-0 = <&pdmm0_clk + &pdmm0_clk1 + &pdmm0_sdi0 + &pdmm0_sdi1 + &pdmm0_sdi2 + &pdmm0_sdi3>; + pinctrl-names = "default"; + resets = <&cru SRST_M_PDM>; + reset-names = "pdm-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + dmac0: dmac@fe530000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xfe530000 0x0 0x4000>; -- cgit From d449121e5e8addcee654250cec298c887ecafb32 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sat, 29 Jan 2022 23:38:03 -0600 Subject: arm64: dts: rockchip: Add Pine64 PineNote board The PineNote is a tablet from Pine64 based on the RK3566 SoC, featuring 4G/128G of storage, a 10.3" electrophoretic display (EPD) with two-color frontlight, both EMR and capacitive digitizers, dual-band wireless, quad-channel digital microphones, and stereo speakers. There are two existing variants of the board. v1.1 was contained in some early samples, and v1.2 was sold as the "PineNote Developer Edition". Signed-off-by: Samuel Holland Link: https://lore.kernel.org/r/20220130053803.43660-3-samuel@sholland.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 2 + .../boot/dts/rockchip/rk3566-pinenote-v1.1.dts | 18 + .../boot/dts/rockchip/rk3566-pinenote-v1.2.dts | 18 + arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi | 639 +++++++++++++++++++++ 4 files changed, 677 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-pinenote-v1.1.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-pinenote-v1.2.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 70007b370d87..4ae9f35434b8 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -56,6 +56,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pinenote-v1.1.dts b/arch/arm64/boot/dts/rockchip/rk3566-pinenote-v1.1.dts new file mode 100644 index 000000000000..5b0b7ebf9fee --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-pinenote-v1.1.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-pinenote.dtsi" + +/ { + model = "Pine64 PineNote v1.1"; + compatible = "pine64,pinenote-v1.1", "pine64,pinenote", "rockchip,rk3566"; +}; + +&pmu_io_domains { + vccio7-supply = <&vcc_1v8>; +}; + +&spk_amp { + VCC-supply = <&dcdc_boost>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pinenote-v1.2.dts b/arch/arm64/boot/dts/rockchip/rk3566-pinenote-v1.2.dts new file mode 100644 index 000000000000..6bbc4c675d64 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-pinenote-v1.2.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-pinenote.dtsi" + +/ { + model = "Pine64 PineNote v1.2"; + compatible = "pine64,pinenote-v1.2", "pine64,pinenote", "rockchip,rk3566"; +}; + +&pmu_io_domains { + vccio7-supply = <&vcc_3v3>; +}; + +&spk_amp { + VCC-supply = <&vcc_bat>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi new file mode 100644 index 000000000000..fea748adfa90 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi @@ -0,0 +1,639 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include +#include +#include +#include +#include + +#include "rk3566.dtsi" + +/ { + aliases { + mmc0 = &sdhci; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1750000>; + + recovery { + label = "recovery"; + linux,code = ; + press-threshold-microvolt = <0>; + }; + }; + + spk_amp: audio-amplifier { + compatible = "simple-audio-amplifier"; + enable-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&spk_amp_enable_h>; + pinctrl-names = "default"; + sound-name-prefix = "Speaker Amp"; + }; + + dmic_codec: dmic-codec { + compatible = "dmic-codec"; + num-channels = <6>; + #sound-dai-cells = <0>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&hall_int_l>; + pinctrl-names = "default"; + + cover { + label = "cover"; + gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + linux,can-disable; + wakeup-event-action = ; + wakeup-source; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pin>; + pinctrl-names = "default"; + + led-0 { + color = ; + function = LED_FUNCTION_CHARGING; + gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + pinctrl-0 = <&wifi_enable_h>; + pinctrl-names = "default"; + reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "PineNote"; + simple-audio-card,aux-devs = <&spk_amp>; + simple-audio-card,widgets = "Headphone", "Headphones", + "Speaker", "Internal Speakers"; + simple-audio-card,routing = "Headphones", "HPOL", + "Headphones", "HPOR", + "Internal Speakers", "Speaker Amp OUTL", + "Internal Speakers", "Speaker Amp OUTR", + "Speaker Amp INL", "HPOL", + "Speaker Amp INR", "HPOR"; + simple-audio-card,pin-switches = "Internal Speakers"; + #address-cells = <1>; + #size-cells = <0>; + + simple-audio-card,dai-link@0 { + reg = <0>; + bitclock-master = <&link0_cpu>; + format = "i2s"; + frame-master = <&link0_cpu>; + mclk-fs = <256>; + + link0_cpu: cpu { + sound-dai = <&i2s1_8ch>; + }; + + link0_codec: codec { + sound-dai = <&rk817>; + }; + }; + + simple-audio-card,dai-link@1 { + reg = <1>; + bitclock-master = <&link1_cpu>; + format = "pdm"; + frame-master = <&link1_cpu>; + + link1_cpu: cpu { + sound-dai = <&pdm>; + }; + + link1_codec: codec { + sound-dai = <&dmic_codec>; + }; + }; + }; + + vbat_4g: vbat-4g { + compatible = "regulator-fixed"; + regulator-name = "vbat_4g"; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + /* powered by vcc_bat, enabled by vbat_4g_en */ + vin-supply = <&vbat_4g_en>; + }; + + vcc_1v8: vcc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + /* powered by vcc_sys, enabled by vcc_1v8_en */ + vin-supply = <&vcc_1v8_en>; + }; + + vcc_bat: vcc-bat { + compatible = "regulator-fixed"; + regulator-name = "vcc_bat"; + regulator-always-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; + + vcc_hall_3v3: vcc-hall-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_hall_3v3"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + vin-supply = <&vcc_bat>; + }; + + vcc_wl: vcc-wl { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vcc_wl_pin>; + pinctrl-names = "default"; + regulator-name = "vcc_wl"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_bat>; + }; + + vdda_0v9: vdda-0v9 { + compatible = "regulator-fixed"; + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + /* powered by vcc_sys, enabled by vcc_1v8_en */ + vin-supply = <&vcc_1v8_en>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <0>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-ramp-delay = <2300>; + regulator-always-on; + vin-supply = <&vcc_sys>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + clocks = <&cru I2S1_MCLKOUT_TX>; + clock-names = "mclk"; + #clock-cells = <1>; + pinctrl-0 = <&i2s1m0_mclk>, <&pmic_int_l>, <&pmic_sleep>; + pinctrl-names = "default"; + rockchip,system-power-controller; + #sound-dai-cells = <0>; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_sys>; + vcc9-supply = <&dcdc_boost>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_gpu_npu: DCDC_REG2 { + regulator-name = "vdd_gpu_npu"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3: DCDC_REG4 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8_pmu: LDO_REG1 { + regulator-name = "vcca_1v8_pmu"; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + /* unused */ + vdda_0v9_ldo: LDO_REG2 { + regulator-name = "vdda_0v9_ldo"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9_pmu: LDO_REG3 { + regulator-name = "vdda_0v9_pmu"; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* unused */ + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_pmu: LDO_REG6 { + regulator-name = "vcc_3v3_pmu"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8_en: LDO_REG7 { + regulator-name = "vcc_1v8_en"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vbat_4g_en: LDO_REG8 { + regulator-name = "vbat_4g_en"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + sleep_sta_ctl: LDO_REG9 { + regulator-name = "sleep_sta_ctl"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + dcdc_boost: BOOST { + regulator-name = "boost"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + otg_switch: OTG_SWITCH { + regulator-name = "otg_switch"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + + digitizer@9 { + compatible = "wacom,w9013", "hid-over-i2c"; + reg = <0x09>; + interrupt-parent = <&gpio0>; + interrupts = ; + hid-descr-addr = <0x1>; + pinctrl-0 = <&pen_fwe>, <&pen_irq_l>, <&pen_rst_l>; + pinctrl-names = "default"; + vdd-supply = <&vcc_3v3_pmu>; + }; +}; + +&i2c3 { + pinctrl-0 = <&i2c3m1_xfer>; + status = "okay"; + + led-controller@36 { + compatible = "ti,lm3630a"; + reg = <0x36>; + enable-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&backlight_hwen_h>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + label = "backlight_cool"; + default-brightness = <0>; + }; + + led@1 { + reg = <1>; + label = "backlight_warm"; + default-brightness = <0>; + }; + }; +}; + +&i2s1_8ch { + pinctrl-0 = <&i2s1m0_lrcktx>, <&i2s1m0_sclktx>, <&i2s1m0_sdi0>, <&i2s1m0_sdo0>; + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&pdm { + pinctrl-0 = <&pdmm0_clk1>, <&pdmm0_sdi1>, <&pdmm0_sdi2>; + /* microphones are on channels 1 and 2 */ + rockchip,path-map = <1>, <2>, <0>, <3>; + status = "okay"; +}; + +&pinctrl { + audio-amplifier { + spk_amp_enable_h: spk-amp-enable-h { + rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + backlight { + backlight_hwen_h: backlight-hwen-h { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + bt_wake_h: bt-wake-h { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + led { + led_pin: led-pin { + rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hall { + hall_int_l: hall-int-l { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pen { + pen_fwe: pen-fwe { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + pen_irq_l: pen-irq-l { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pen_rst_l: pen-rst-l { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pmic_sleep: pmic-sleep { + rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + vcc-wl { + vcc_wl_pin: vcc-wl-pin { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_host_wake_l: wifi-host-wake-l { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc_3v3_pmu>; + pmuio2-supply = <&vcc_3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vcc_3v3>; + vccio4-supply = <&vcca_1v8_pmu>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>, <&emmc_datastrobe>, <&emmc_rstnout>; + pinctrl-names = "default"; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-0 = <&sdmmc1_bus4>, <&sdmmc1_clk>, <&sdmmc1_cmd>; + pinctrl-names = "default"; + sd-uhs-sdr104; + vmmc-supply = <&vcc_wl>; + vqmmc-supply = <&vcca_1v8_pmu>; + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart1 { + pinctrl-0 = <&uart1m0_ctsn>, <&uart1m0_rtsn>, <&uart1m0_xfer>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk817 1>; + clock-names = "lpo"; + device-wake-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + host-wake-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&bt_enable_h>, <&bt_host_wake_l>, <&bt_wake_h>; + pinctrl-names = "default"; + vbat-supply = <&vcc_wl>; + vddio-supply = <&vcca_1v8_pmu>; + }; +}; + +&uart2 { + status = "okay"; +}; -- cgit From f471b9a5267941b8121e3cdee29fb207f79f38ec Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sat, 5 Feb 2022 11:31:01 -0600 Subject: arm64: dts: imx8mm-beacon: Enable PCIe The baseboard supports a PCIe slot with a 100MHz reference clock, but it's controlled by a different GPIO, so a gated clock is required. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mm-beacon-baseboard.dtsi | 57 ++++++++++++++++++++++ 1 file changed, 57 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi index 0da311898e01..ec3f2c177035 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi @@ -3,6 +3,8 @@ * Copyright 2020 Compass Electronics Group, LLC */ +#include + / { leds { compatible = "gpio-leds"; @@ -34,6 +36,19 @@ }; }; + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + pcie0_refclk_gated: pcie0-refclk-gated { + compatible = "gpio-gate-clock"; + clocks = <&pcie0_refclk>; + #clock-cells = <0>; + enable-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>; + }; + reg_audio: regulator-audio { compatible = "regulator-fixed"; regulator-name = "3v3_aud"; @@ -64,6 +79,16 @@ startup-delay-us = <100000>; }; + reg_pcie0: regulator-pcie { + compatible = "regulator-fixed"; + regulator-name = "pci_pwr_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pca6416_1 1 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100000>; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; regulator-name = "VSD_3V3"; @@ -202,6 +227,32 @@ }; }; +&pcie_phy { + fsl,refclk-pad-mode = ; + fsl,tx-deemph-gen1 = <0x2d>; + fsl,tx-deemph-gen2 = <0xf>; + fsl,clkreq-unsupported; + clocks = <&pcie0_refclk_gated>; + clock-names = "ref"; + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, + <&pcie0_refclk_gated>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + vpcie-supply = <®_pcie0>; + status = "okay"; +}; + &sai3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; @@ -308,6 +359,12 @@ >; }; + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41 + >; + }; + pinctrl_sai3: sai3grp { fsl,pins = < MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 -- cgit From daeb1c2b50fb98118d6318b5fdbd9ef9bdfaeaf5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 30 Dec 2021 20:53:25 +0100 Subject: arm64: dts: exynos: drop incorrectly placed wakeup interrupts in Exynos850 The pin controller device node is expected to have one (optional) interrupt. Its pin banks capable of external interrupts, should define interrupts for each pin, unless a muxed interrupt is used. Exynos850 defined the second part - interrupt for each pin in wake-up pin controller - but also added these interrupts in main device node, which is not correct. Fixes: e3493220fd3e ("arm64: dts: exynos: Add initial Exynos850 SoC support") Signed-off-by: Krzysztof Kozlowski Tested-by: Sam Protsenko Reviewed-by: Sam Protsenko Link: https://lore.kernel.org/r/20211230195325.328220-3-krzysztof.kozlowski@canonical.com --- arch/arm64/boot/dts/exynos/exynos850.dtsi | 40 ------------------------------- 1 file changed, 40 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi index c9457593f6cc..bb3a7aec6208 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -326,38 +326,6 @@ pinctrl_alive: pinctrl@11850000 { compatible = "samsung,exynos850-pinctrl"; reg = <0x11850000 0x1000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; wakeup-interrupt-controller { compatible = "samsung,exynos7-wakeup-eint"; @@ -367,14 +335,6 @@ pinctrl_cmgp: pinctrl@11c30000 { compatible = "samsung,exynos850-pinctrl"; reg = <0x11c30000 0x1000>; - interrupts = , - , - , - , - , - , - , - ; wakeup-interrupt-controller { compatible = "samsung,exynos7-wakeup-eint"; -- cgit From 75a0c6a505802085394e102b37408ce73b4404ae Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 11 Jan 2022 21:17:13 +0100 Subject: arm64: dts: exynos: align pinctrl with dtschema in Exynos850 Align the pin controller related nodes with dtschema. No functional change expected. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Sam Protsenko Link: https://lore.kernel.org/r/20220111201722.327219-13-krzysztof.kozlowski@canonical.com --- arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi | 56 +++++++++++------------ 1 file changed, 28 insertions(+), 28 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi index 6c31da70e223..f43e4a206282 100644 --- a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi @@ -13,7 +13,7 @@ #include &pinctrl_alive { - gpa0: gpa0 { + gpa0: gpa0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -30,7 +30,7 @@ ; }; - gpa1: gpa1 { + gpa1: gpa1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -47,7 +47,7 @@ ; }; - gpa2: gpa2 { + gpa2: gpa2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -64,7 +64,7 @@ ; }; - gpa3: gpa3 { + gpa3: gpa3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -81,7 +81,7 @@ ; }; - gpa4: gpa4 { + gpa4: gpa4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -94,7 +94,7 @@ ; }; - gpq0: gpq0 { + gpq0: gpq0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -134,7 +134,7 @@ }; &pinctrl_cmgp { - gpm0: gpm0 { + gpm0: gpm0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -144,7 +144,7 @@ interrupts = ; }; - gpm1: gpm1 { + gpm1: gpm1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -154,7 +154,7 @@ interrupts = ; }; - gpm2: gpm2 { + gpm2: gpm2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -164,7 +164,7 @@ interrupts = ; }; - gpm3: gpm3 { + gpm3: gpm3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -174,7 +174,7 @@ interrupts = ; }; - gpm4: gpm4 { + gpm4: gpm4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -184,7 +184,7 @@ interrupts = ; }; - gpm5: gpm5 { + gpm5: gpm5-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -194,7 +194,7 @@ interrupts = ; }; - gpm6: gpm6 { + gpm6: gpm6-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -204,7 +204,7 @@ interrupts = ; }; - gpm7: gpm7 { + gpm7: gpm7-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -276,7 +276,7 @@ }; &pinctrl_aud { - gpb0: gpb0 { + gpb0: gpb0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -284,7 +284,7 @@ #interrupt-cells = <2>; }; - gpb1: gpb1 { + gpb1: gpb1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -342,7 +342,7 @@ }; &pinctrl_hsi { - gpf2: gpf2 { + gpf2: gpf2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -387,7 +387,7 @@ }; &pinctrl_core { - gpf0: gpf0 { + gpf0: gpf0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -395,7 +395,7 @@ #interrupt-cells = <2>; }; - gpf1: gpf1 { + gpf1: gpf1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -454,7 +454,7 @@ }; &pinctrl_peri { - gpc0: gpc0 { + gpc0: gpc0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -462,7 +462,7 @@ #interrupt-cells = <2>; }; - gpc1: gpc1 { + gpc1: gpc1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -470,7 +470,7 @@ #interrupt-cells = <2>; }; - gpg0: gpg0 { + gpg0: gpg0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -478,7 +478,7 @@ #interrupt-cells = <2>; }; - gpg1: gpg1 { + gpg1: gpg1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -486,7 +486,7 @@ #interrupt-cells = <2>; }; - gpg2: gpg2 { + gpg2: gpg2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -494,7 +494,7 @@ #interrupt-cells = <2>; }; - gpg3: gpg3 { + gpg3: gpg3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -502,14 +502,14 @@ #interrupt-cells = <2>; }; - gpp0: gpp0 { + gpp0: gpp0-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpp1: gpp1 { + gpp1: gpp1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -517,7 +517,7 @@ #interrupt-cells = <2>; }; - gpp2: gpp2 { + gpp2: gpp2-gpio-bank { gpio-controller; #gpio-cells = <2>; -- cgit From f377d4d4beafca755d2b6e6368895b1f3fb383c6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 11 Jan 2022 21:17:21 +0100 Subject: arm64: dts: exynos: use dedicated wake-up pinctrl compatible in Exynos850 Older Samsung Exynos SoC pin controller nodes (Exynos3250, Exynos4, Exynos5, Exynos5433) with external wake-up interrupts, expected to have one interrupt for multiplexing these wake-up interrupts. Also they expected to have exactly one pin controller capable of external wake-up interrupts. It seems however that newer ARMv8 Exynos SoC like Exynos850 and ExynosAutov9 have differences: 1. No multiplexed external wake-up interrupt, only direct, 2. More than one pin controller capable of external wake-up interrupts. Use dedicated Exynos850 compatible for its external wake-up interrupts controller to indicate the differences. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Sam Protsenko Link: https://lore.kernel.org/r/20220111201722.327219-21-krzysztof.kozlowski@canonical.com --- arch/arm64/boot/dts/exynos/exynos850.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi index bb3a7aec6208..d1700e96fee2 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -328,7 +328,7 @@ reg = <0x11850000 0x1000>; wakeup-interrupt-controller { - compatible = "samsung,exynos7-wakeup-eint"; + compatible = "samsung,exynos850-wakeup-eint"; }; }; @@ -337,7 +337,7 @@ reg = <0x11c30000 0x1000>; wakeup-interrupt-controller { - compatible = "samsung,exynos7-wakeup-eint"; + compatible = "samsung,exynos850-wakeup-eint"; }; }; -- cgit From 5edaa224645b17266a8b8037e97fcad1275c49cf Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Wed, 9 Feb 2022 10:06:48 +0800 Subject: arm64: dts: imx8mq-evk: Add second PCIe port support Enable the second PCIe port support on i.MX8MQ EVK board. Signed-off-by: Richard Zhu Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 38 ++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index e7f521aac400..99fed35168eb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -27,6 +27,17 @@ clock-frequency = <100000000>; }; + reg_pcie1: regulator-pcie { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1_reg>; + regulator-name = "MPCIE_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_usdhc2_vmmc: regulator-vsd-3v3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_usdhc2>; @@ -328,6 +339,20 @@ status = "okay"; }; +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1>; + reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + vpcie-supply = <®_pcie1>; + vph-supply = <&vgen5_reg>; + status = "okay"; +}; + &pgc_gpu { power-supply = <&sw1a_reg>; }; @@ -483,6 +508,19 @@ >; }; + pinctrl_pcie1: pcie1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x76 + MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16 + >; + }; + + pinctrl_pcie1_reg: pcie1reggrp { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x16 + >; + }; + pinctrl_qspi: qspigrp { fsl,pins = < MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 -- cgit From ba5dfa2fd8d0aed4e4b6f650ba9e8ea7cdd6ead1 Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Tue, 15 Feb 2022 07:36:39 +0100 Subject: arm64: dts: broadcom: bcm4908: add I2C block MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit BCM4908 uses the same I2C hw as BCM63xx / BCM67xx / BCM68xx SoCs. Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi index f76b3dbf67ac..a4be040a00c0 100644 --- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi @@ -456,6 +456,15 @@ }; }; + i2c@2100 { + compatible = "brcm,brcmper-i2c"; + reg = <0x2100 0x58>; + clock-frequency = <97500>; + pinctrl-names = "default"; + pinctrl-0 = <&pins_i2c_a>; + status = "disabled"; + }; + misc@2600 { compatible = "brcm,misc", "simple-mfd"; reg = <0x2600 0xe4>; -- cgit From 292b0dd7cdc1b00a8acb199605ecf73bb253c5b5 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Thu, 3 Feb 2022 15:02:40 +0100 Subject: arm64: dts: ti: k3-am65*: Remove #address-cells/#size-cells from flash nodes Specifying partitions directly in the flash node is deprecated, a fixed-partitions node should be used instead. Therefore, it doesn't make sense to have these properties in the flash nodes. Signed-off-by: Matthias Schiffer Signed-off-by: Nishanth Menon Acked-by: Jan Kiszka Link: https://lore.kernel.org/r/20220203140240.973690-2-matthias.schiffer@ew.tq-group.com --- arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 2 -- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 8 ++------ 2 files changed, 2 insertions(+), 8 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index 3079eaee01c0..6e41f2fa044a 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -603,8 +603,6 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <2>; - #address-cells = <1>; - #size-cells = <1>; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 9043f91c9bec..57497cb1ed68 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -333,14 +333,12 @@ #size-cells= <0>; ti,pindir-d0-out-d1-in; - flash@0{ + flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; spi-max-frequency = <48000000>; - #address-cells = <1>; - #size-cells= <1>; }; }; @@ -498,7 +496,7 @@ pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; - flash@0{ + flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <8>; @@ -509,8 +507,6 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <0>; - #address-cells = <1>; - #size-cells = <1>; }; }; -- cgit From 2aeb0696b8e801c20c2176d9dbe512b6a5aa2f79 Mon Sep 17 00:00:00 2001 From: Hari Nagalla Date: Thu, 10 Feb 2022 11:22:46 -0600 Subject: arm64: dts: ti: k3-am64: Add ESM0 to device memory map AM64x SoCs have two ESM modules, with one in MAIN voltage domain and the other in MCU voltage domain. The error output from Main ESM module can be routed to the MCU ESM module. The error output of MCU ESM can be configured to reset the device. The MCU ESM configuration address space is already opened and this patch opens the MAIN ESM configuration address space. For ESM details please refer technical reference manual at https://www.ti.com/lit/pdf/spruim2 Signed-off-by: Hari Nagalla Signed-off-by: Nishanth Menon Reviewed-by: Christian Gmeiner Link: https://lore.kernel.org/r/20220210172246.27871-1-hnagalla@ti.com --- arch/arm64/boot/dts/ti/k3-am64.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/ti/k3-am64.dtsi b/arch/arm64/boot/dts/ti/k3-am64.dtsi index 84bd07cd1824..09ff14643ee6 100644 --- a/arch/arm64/boot/dts/ti/k3-am64.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64.dtsi @@ -66,6 +66,7 @@ #address-cells = <2>; #size-cells = <2>; ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */ + <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */ -- cgit From e6bbf0d53ae1060ee6403bafcc4d1fd25d088e40 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 28 Dec 2021 00:45:28 +0100 Subject: arm64: dts: rockchip: define vdd_log on rk3399-puma vdd_log supplied a lot of the logic parts of the soc and is supplied through pwm2. Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20211227234529.1970281-1-heiko@sntech.de --- arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi index fb67db4619ea..b91fb0b078b9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi @@ -71,6 +71,17 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + pwm-supply = <&vcc5v0_sys>; + regulator-name = "vdd_log"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; }; &cpu_b0 { -- cgit From dc570e8e1a7036eaaeede71b55e14739710ea0a4 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 28 Dec 2021 00:45:29 +0100 Subject: arm64: dts: rockchip: fix supplies for pwm regulators The supply-name for pwm-regualators is "pwm", so the property needs to be pwm-supply, not vin-supply as in a number of boards. In all cases changed here, the supplying regulator is always an always-on fixed-regulator, so there will be no functional change and only a change in the regulator hirarchy, as can be seen for example in the regulator-summary. Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20211227234529.1970281-2-heiko@sntech.de --- arch/arm64/boot/dts/rockchip/rk3399-firefly.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi | 2 +- arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 2 +- arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi | 2 +- arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts index 65d659d56041..19683f1dbf93 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts @@ -245,12 +245,12 @@ vdd_log: vdd-log { compatible = "pwm-regulator"; pwms = <&pwm2 0 25000 1>; + pwm-supply = <&vcc_sys>; regulator-name = "vdd_log"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <430000>; regulator-max-microvolt = <1400000>; - vin-supply = <&vcc_sys>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi index f1fcc6b5b402..7ba3ed24084b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi @@ -80,12 +80,12 @@ vdd_log: vdd-log { compatible = "pwm-regulator"; pwms = <&pwm2 0 25000 1>; + pwm-supply = <&vsys_3v3>; regulator-name = "vdd_log"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1400000>; - vin-supply = <&vsys_3v3>; }; vsys: vsys { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts b/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts index e890166e7fd4..5bbe74bed0ea 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts @@ -102,12 +102,12 @@ vdd_log: vdd-log { compatible = "pwm-regulator"; pwms = <&pwm2 0 25000 1>; + pwm-supply = <&vcc5v0_sys>; regulator-name = "vdd_log"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1400000>; - vin-supply = <&vcc5v0_sys>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts index 04b54abea3cc..9d3a718f66f6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts @@ -166,12 +166,12 @@ vdd_log: vdd-log { compatible = "pwm-regulator"; pwms = <&pwm2 0 25000 1>; + pwm-supply = <&vcc_sys>; regulator-name = "vdd_log"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1400000>; - vin-supply = <&vcc_sys>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts index c2f021a1a18f..8a048ddc9505 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts @@ -243,12 +243,12 @@ vdd_log: vdd-log { compatible = "pwm-regulator"; pwms = <&pwm2 0 25000 1>; + pwm-supply = <&vcc_sysin>; regulator-name = "vdd_log"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1400000>; - vin-supply = <&vcc_sysin>; regulator-state-mem { regulator-on-in-suspend; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi index 92acf6ea299b..401e1ae9d944 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi @@ -144,12 +144,12 @@ vdd_log: vdd-log { compatible = "pwm-regulator"; pwms = <&pwm2 0 25000 1>; + pwm-supply = <&vcc5v0_sys>; regulator-name = "vdd_log"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1400000>; - vin-supply = <&vcc5v0_sys>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi index 83db4ca67334..45e77f86d329 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi @@ -213,12 +213,12 @@ vdd_log: vdd-log { compatible = "pwm-regulator"; pwms = <&pwm2 0 25000 1>; + pwm-supply = <&vcc5v0_sys>; regulator-name = "vdd_log"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1700000>; - vin-supply = <&vcc5v0_sys>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi index 46b0f97a0b1c..2aa0fad8f893 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi @@ -133,12 +133,12 @@ vdd_log: vdd-log { compatible = "pwm-regulator"; pwms = <&pwm2 0 25000 1>; + pwm-supply = <&vcc_sys>; regulator-name = "vdd_log"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1400000>; - vin-supply = <&vcc_sys>; }; }; -- cgit From c4eda826deb6178d9a097ef048361d378c21c5d3 Mon Sep 17 00:00:00 2001 From: Oliver Graute Date: Wed, 9 Feb 2022 16:42:23 +0100 Subject: arm64: dts: imx8qm: add compatible string for usdhc3 add compatible string for usdhc3 Cc: Rob Herring Cc: Sascha Hauer Cc: Mark Rutland Cc: devicetree@vger.kernel.org Cc: Fabio Estevam Cc: Dong Aisheng Signed-off-by: Oliver Graute Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi index 42637a45701c..ec1639174e2e 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi @@ -19,3 +19,7 @@ &usdhc2 { compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; }; + +&usdhc3 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; +}; -- cgit From df6182e662cae4011927c0ffa99a3b13bfe62f35 Mon Sep 17 00:00:00 2001 From: Oliver Graute Date: Wed, 9 Feb 2022 16:50:55 +0100 Subject: arm64: dts: imx8qm: added more serial alias to dts Add more serial alias to imx8qm.dtsi file Cc: Rob Herring Cc: Sascha Hauer Cc: Fabio Estevam Cc: Dong Aisheng Signed-off-by: Oliver Graute Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qm.dtsi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index a6ffdc92a520..be8c76a0554c 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -20,6 +20,9 @@ mmc1 = &usdhc2; mmc2 = &usdhc3; serial0 = &lpuart0; + serial1 = &lpuart1; + serial2 = &lpuart2; + serial3 = &lpuart3; }; cpus { -- cgit From 6bb691f2cf3d3c40535e4bc2988faacbe993c588 Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Fri, 11 Feb 2022 10:38:17 -0500 Subject: arm64: dts: imx8mp-evk: add PCA6416 gpio line names Add gpio-line-names for the various GPIO's connected to the PCA6416 I/O expander on the imx8mp EVK. This helps when using the new gpiod interface to find the GPIOs by name. Signed-off-by: Hugo Villeneuve Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 9055ce32aecc..a82c31dbdbf3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -300,6 +300,22 @@ pinctrl-0 = <&pinctrl_pca6416_int>; interrupt-parent = <&gpio1>; interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + gpio-line-names = "EXT_PWREN1", + "EXT_PWREN2", + "CAN1/I2C5_SEL", + "PDM/CAN2_SEL", + "FAN_EN", + "PWR_MEAS_IO1", + "PWR_MEAS_IO2", + "EXP_P0_7", + "EXP_P1_0", + "EXP_P1_1", + "EXP_P1_2", + "EXP_P1_3", + "EXP_P1_4", + "EXP_P1_5", + "EXP_P1_6", + "EXP_P1_7"; }; }; -- cgit From 8134822db08dcbb6a01538d04f65446289e573b5 Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Fri, 11 Feb 2022 10:38:43 -0500 Subject: arm64: dts: imx8mp-evk: add support for I2C5 Add support for i2c5, which is used to access the external I2C bus on connector J22 of the imx8mp-evk. Limit the speed to 100kHz since this is an external I2C bus. Disabled by default, since it is shared with the CAN1 bus. To enable i2c5, you need to disable the CAN1 function, enable the i2c5 function and also configure the CAN1/I2C5_SEL GPIO to HIGH to select i2c5 instead of CAN1. This can be done by defining a gpio-hog inside the pca6416 node, in your board device tree, like in this example: &flexcan1 { status = "disabled"; }; &i2c5 { status = "okay"; }; &pca6416 { can1-i2c5-sel-hog { gpio-hog; gpios = <2 GPIO_ACTIVE_HIGH>; output-high; line-name = "can1-i2c5-sel"; }; }; Signed-off-by: Hugo Villeneuve Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index a82c31dbdbf3..4c3ac4214a2c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -319,6 +319,21 @@ }; }; +/* I2C on expansion connector J22. */ +&i2c5 { + clock-frequency = <100000>; /* Lower clock speed for external bus. */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c5>; + status = "disabled"; /* can1 pins conflict with i2c5 */ + + /* GPIO 2 of PCA6416 is used to switch between CAN1 and I2C5 functions: + * LOW: CAN1 (default, pull-down) + * HIGH: I2C5 + * You need to set it to high to enable I2C5 (for example, add gpio-hog + * in pca6416 node). + */ +}; + &snvs_pwrkey { status = "okay"; }; @@ -464,6 +479,13 @@ >; }; + pinctrl_i2c5: i2c5grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c3 + MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c3 + >; + }; + pinctrl_pmic: pmicgrp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0 -- cgit From eba5bea8f37fe8a3a65cf8015ea041070042b421 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 14 Feb 2022 12:55:29 +0100 Subject: arm64: dts: ls1028a: add efuse node Layerscape SoCs contain a Security Fuse Processor which is basically a efuse controller. Add the node, so userspace can read the efuses. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 5bb8c26e0825..088271d49139 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -224,6 +224,17 @@ little-endian; }; + efuse@1e80000 { + compatible = "fsl,ls1028a-sfp"; + reg = <0x0 0x1e80000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + ls1028a_uid: unique-id@1c { + reg = <0x1c 0x8>; + }; + }; + scfg: syscon@1fc0000 { compatible = "fsl,ls1028a-scfg", "syscon"; reg = <0x0 0x1fc0000 0x0 0x10000>; -- cgit From a72ba91e5bc78d2b1b4712839399bbc41a629682 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 11 Feb 2022 11:04:18 -0800 Subject: arm64: dts: imx: Add i.mx8mm Gateworks gw7903 dts support The GW7903 is based on the i.MX 8M Mini SoC featuring: - LPDDR4 DRAM - eMMC FLASH - microSD connector with UHS support - LIS2DE12 3-axis accelerometer - Gateworks System Controller - IMX8M FEC - software selectable RS232/RS485/RS422 serial transceiver - PMIC - 2x off-board bi-directional opto-isolated digital I/O - 1x M.2 A-E Key Socket and 1x MiniPCIe socket with USB2.0 and PCIe (resistor loading to route PCIe/USB2 between M.2 and MiniPCIe socket) Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx8mm-venice-gw7903.dts | 836 +++++++++++++++++++++ 2 files changed, 837 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index d96eb4cbd990..55b47cc11490 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -63,6 +63,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7901.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7902.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7903.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dahlia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts new file mode 100644 index 000000000000..1deb2ea8fcc9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts @@ -0,0 +1,836 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Gateworks Corporation + */ + +/dts-v1/; + +#include +#include +#include +#include + +#include "imx8mm.dtsi" + +/ { + model = "Gateworks Venice GW7903 i.MX8MM board"; + compatible = "gw,imx8mm-gw7903", "fsl,imx8mm"; + + aliases { + ethernet0 = &fec1; + usb0 = &usbotg1; + }; + + chosen { + stdout-path = &uart2; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + user-pb { + label = "user_pb"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key_erased"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + + led-controller { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-0 { + function = LED_FUNCTION_STATUS; + color = ; + label = "led01_red"; + gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = ; + label = "led01_grn"; + gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-2 { + function = LED_FUNCTION_STATUS; + color = ; + label = "led02_red"; + gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-3 { + function = LED_FUNCTION_STATUS; + color = ; + label = "led02_grn"; + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-4 { + function = LED_FUNCTION_STATUS; + color = ; + label = "led03_red"; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-5 { + function = LED_FUNCTION_STATUS; + color = ; + label = "led03_grn"; + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-6 { + function = LED_FUNCTION_STATUS; + color = ; + label = "led04_red"; + gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-7 { + function = LED_FUNCTION_STATUS; + color = ; + label = "led04_grn"; + gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-8 { + function = LED_FUNCTION_STATUS; + color = ; + label = "led05_red"; + gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-9 { + function = LED_FUNCTION_STATUS; + color = ; + label = "led05_grn"; + gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-a { + function = LED_FUNCTION_STATUS; + color = ; + label = "led06_red"; + gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-b { + function = LED_FUNCTION_STATUS; + color = ; + label = "led06_grn"; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-750M { + opp-hz = /bits/ 64 <750000000>; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + local-mac-address = [00 00 00 00 00 00]; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + rx-internal-delay-ps = <2000>; + tx-internal-delay-ps = <2500>; + }; + }; +}; + +&gpio1 { + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", "rs422_en#", "rs485_en#", "rs232_en#", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = "dig2_in", "dig2_out#", "", "", "", "", "", "", + "dig1_out#", "dig1_in", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio5 { + gpio-line-names = "", "", "", "", "", "", "", "sim1_det#", + "sim2_det#", "sim2_sel", "", "", "pci_wdis#", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + pinctrl-0 = <&pinctrl_gsc>; + interrupt-parent = <&gpio4>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <1>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@6 { + gw,mode = <0>; + reg = <0x06>; + label = "temp"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@82 { + gw,mode = <2>; + reg = <0x82>; + label = "vin"; + gw,voltage-divider-ohms = <22100 1000>; + gw,voltage-offset-microvolt = <700000>; + }; + + channel@84 { + gw,mode = <2>; + reg = <0x84>; + label = "vdd_5p0"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@86 { + gw,mode = <2>; + reg = <0x86>; + label = "vdd_3p3"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@88 { + gw,mode = <2>; + reg = <0x88>; + label = "vdd_0p9"; + }; + + channel@8c { + gw,mode = <2>; + reg = <0x8c>; + label = "vdd_soc"; + }; + + channel@8e { + gw,mode = <2>; + reg = <0x8e>; + label = "vdd_arm"; + }; + + channel@90 { + gw,mode = <2>; + reg = <0x90>; + label = "vdd_1p8"; + }; + + channel@92 { + gw,mode = <2>; + reg = <0x92>; + label = "vdd_dram"; + }; + + channel@a2 { + gw,mode = <2>; + reg = <0xa2>; + label = "vdd_gsc"; + gw,voltage-divider-ohms = <10000 10000>; + }; + }; + }; + + gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + rtc@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio3>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + rohm,reset-snvs-powered; + #clock-cells = <0>; + clocks = <&osc_32k 0>; + clock-output-names = "clk-32k-out"; + + regulators { + /* vdd_soc: 0.805-0.900V (typ=0.8V) */ + BUCK1 { + regulator-name = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + /* vdd_arm: 0.805-1.0V (typ=0.9V) */ + buck2: BUCK2 { + regulator-name = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; + }; + + /* vdd_0p9: 0.805-1.0V (typ=0.9V) */ + BUCK3 { + regulator-name = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + /* vdd_3p3 */ + BUCK4 { + regulator-name = "buck4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + /* vdd_1p8 */ + BUCK5 { + regulator-name = "buck5"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + /* vdd_dram */ + BUCK6 { + regulator-name = "buck6"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + /* nvcc_snvs_1p8 */ + LDO1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1900000>; + regulator-boot-on; + regulator-always-on; + }; + + /* vdd_snvs_0p8 */ + LDO2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + /* vdda_1p8 */ + LDO3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO6 { + regulator-name = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + accelerometer@19 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_accel>; + compatible = "st,lis2de12"; + reg = <0x19>; + st,drdy-int-pin = <1>; + interrupt-parent = <&gpio1>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "INT1"; + }; +}; + +&pcie_phy { + fsl,refclk-pad-mode = ; + fsl,clkreq-unsupported; + clocks = <&pcie0_refclk>; + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + status = "okay"; +}; + +&pgc_mipi { + status = "disabled"; +}; + +/* off-board RS232/RS485/RS422 */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + cts-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; + rts-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + dtr-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + dcd-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; + uart-has-rtscts; + status = "okay"; +}; + +/* console */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +/* microSD */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000041 /* RS422# */ + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000041 /* RS485# */ + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x40000041 /* RS232# */ + MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x40000041 /* DIG1_IN */ + MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* DIG1_OUT */ + MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x40000041 /* DIG2_IN */ + MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x40000041 /* DIG2_OUT */ + MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x40000041 /* SIM1DET# */ + MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x40000041 /* SIM2DET# */ + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000041 /* SIM2SEL */ + MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x40000041 /* PCI_WDIS# */ + >; + }; + + pinctrl_accel: accelgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x159 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x19 /* IRQ# */ + MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* RST# */ + >; + }; + + pinctrl_gsc: gscgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x159 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_gpio_leds: gpioledgrp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19 + MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x19 + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 + MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x19 + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x19 + MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 + MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19 + MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x19 + MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19 + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 + >; + }; + + pinctrl_pcie0: pciegrp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x41 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x140 + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140 + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x140 + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x140 + MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; -- cgit From 665f7f1ce8a7e121abb289aa6791ad0855a80008 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 14 Feb 2022 15:14:21 -0800 Subject: arm64: dts: imx8mm-venice-gw73xx-0x: add dt overlays for serial modes The imx8mm-venice-gw73xx-0x som+baseboard combination has a multi-protocol RS-232/RS-485/RS-422 transceiver to an off-board connector which can be configured in a number of ways via UART and GPIO configuration. The default configuration per the imx8mm-venice-gw73xx-0x dts is for UART2 TX/RX and UART4 TX/RX to be available as RS-232: J15.1 UART2 TX out J15.2 UART2 RX in J15.3 UART4 TX out J15.4 UART4 RX in J15.5 GND Add dt overlays to allow additional the modes of operation: rs232-rts (UART2 RS-232 with RTS/CTS hardware flow control) J15.1 TX out J15.2 RX in J15.3 RTS out J15.4 CTS in J15.5 GND rs485 (UART2 RS-485 half duplex) J15.1 TXRX- J15.2 N/C J15.3 TXRX+ J15.4 N/C J15.5 GND rs422 (UART2 RS-422 full duplex) J15.1 TX- J15.2 RX+ J15.3 TX+ J15.4 RX- J15.5 GND Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 8 +++ .../imx8mm-venice-gw73xx-0x-rs232-rts.dts | 53 +++++++++++++++++++ .../freescale/imx8mm-venice-gw73xx-0x-rs422.dts | 61 ++++++++++++++++++++++ .../freescale/imx8mm-venice-gw73xx-0x-rs485.dts | 61 ++++++++++++++++++++++ 4 files changed, 183 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dts (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 55b47cc11490..ea798b7bb286 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -99,6 +99,14 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb +imx8mm-venice-gw73xx-0x-rs232-rts-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs232-rts.dtbo +imx8mm-venice-gw73xx-0x-rs422-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs422.dtbo +imx8mm-venice-gw73xx-0x-rs485-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs485.dtbo + +dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs232-rts.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs422.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs485.dtb + dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb dtb-$(CONFIG_ARCH_S32) += s32g274a-rdb2.dtb dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dts new file mode 100644 index 000000000000..2fa635e1c1a8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dts @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Gateworks Corporation + * + * GW73xx RS232 with RTS/CTS hardware flow control: + * - GPIO4_0 rs485_en needs to be driven low (in-active) + * - UART4_TX becomes RTS + * - UART4_RX becomes CTS + */ + +#include + +#include "imx8mm-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "gw,imx8mm-gw73xx-0x"; +}; + +&gpio4 { + rs485_en { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "rs485_en"; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + rts-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; + cts-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140 + MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 0x140 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dts new file mode 100644 index 000000000000..3e6404340d52 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dts @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 Gateworks Corporation + * + * GW73xx RS422 (RS485 full duplex): + * - GPIO1_0 rs485_term selects on-chip termination + * - GPIO4_0 rs485_en needs to be driven high (active) + * - GPIO4_2 rs485_hd needs to be driven low (in-active) + * - UART4_TX is DE for RS485 transmitter + * - RS485_EN needs to be pulled high + * - RS485_HALF needs to be low + */ + +#include + +#include "imx8mm-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "gw,imx8mm-gw73xx-0x"; +}; + +&gpio4 { + rs485_en { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "rs485_en"; + }; + + rs485_hd { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "rs485_hd"; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +&uart4 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dts new file mode 100644 index 000000000000..2c71ab9854cb --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dts @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 Gateworks Corporation + * + * GW73xx RS485 HD: + * - GPIO1_0 rs485_term selects on-chip termination + * - GPIO4_0 rs485_en needs to be driven high (active) + * - GPIO4_2 rs485_hd needs to be driven high (active) + * - UART4_TX is DE for RS485 transmitter + * - RS485_EN needs to be pulled high + * - RS485_HALF needs to be pulled high + */ + +#include + +#include "imx8mm-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "gw,imx8mm-gw73xx-0x"; +}; + +&gpio4 { + rs485_en { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "rs485_en"; + }; + + rs485_hd { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "rs485_hd"; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +&uart4 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140 + >; + }; +}; -- cgit From 27c8f4ccc1b9ee2f52a62580fd7631c3025bdbfb Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 14 Feb 2022 15:14:22 -0800 Subject: arm64: dts: imx8mm-venice-gw72xx-0x: add dt overlays for serial modes The imx8mm-venice-gw72xx-0x som+baseboard combination has a multi-protocol RS-232/RS-485/RS-422 transceiver to an off-board connector which can be configured in a number of ways via UART and GPIO configuration. The default configuration per the imx8mm-venice-gw72xx-0x dts is for UART2 TX/RX and UART4 TX/RX to be available as RS-232: J15.1 UART2 TX out J15.2 UART2 RX in J15.3 UART4 TX out J15.4 UART4 RX in J15.5 GND Add dt overlays to allow additional the modes of operation: rs232-rts (UART2 RS-232 with RTS/CTS hardware flow control) J15.1 TX out J15.2 RX in J15.3 RTS out J15.4 CTS in J15.5 GND rs485 (UART2 RS-485 half duplex) J15.1 TXRX- J15.2 N/C J15.3 TXRX+ J15.4 N/C J15.5 GND rs422 (UART2 RS-422 full duplex) J15.1 TX- J15.2 RX+ J15.3 TX+ J15.4 RX- J15.5 GND Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 6 +++ .../imx8mm-venice-gw72xx-0x-rs232-rts.dts | 53 +++++++++++++++++++ .../freescale/imx8mm-venice-gw72xx-0x-rs422.dts | 61 ++++++++++++++++++++++ .../freescale/imx8mm-venice-gw72xx-0x-rs485.dts | 61 ++++++++++++++++++++++ 4 files changed, 181 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dts (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index ea798b7bb286..1753f787a609 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -99,10 +99,16 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb +imx8mm-venice-gw72xx-0x-rs232-rts-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rs232-rts.dtbo +imx8mm-venice-gw72xx-0x-rs422-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rs422.dtbo +imx8mm-venice-gw72xx-0x-rs485-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rs485.dtbo imx8mm-venice-gw73xx-0x-rs232-rts-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs232-rts.dtbo imx8mm-venice-gw73xx-0x-rs422-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs422.dtbo imx8mm-venice-gw73xx-0x-rs485-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs485.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rs232-rts.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rs422.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rs485.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs232-rts.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs422.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs485.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dts new file mode 100644 index 000000000000..3ea73a6886ff --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dts @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Gateworks Corporation + * + * GW72xx RS232 with RTS/CTS hardware flow control: + * - GPIO4_0 rs485_en needs to be driven low (in-active) + * - UART4_TX becomes RTS + * - UART4_RX becomes CTS + */ + +#include + +#include "imx8mm-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "gw,imx8mm-gw72xx-0x"; +}; + +&gpio4 { + rs485_en { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "rs485_en"; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + rts-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; + cts-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140 + MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 0x140 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dts new file mode 100644 index 000000000000..c3cd9f2b0db3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dts @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Gateworks Corporation + * + * GW72xx RS422 (RS485 full duplex): + * - GPIO1_0 rs485_term selects on-chip termination + * - GPIO4_0 rs485_en needs to be driven high (active) + * - GPIO4_2 rs485_hd needs to be driven low (in-active) + * - UART4_TX is DE for RS485 transmitter + * - RS485_EN needs to be pulled high + * - RS485_HALF needs to be low + */ + +#include + +#include "imx8mm-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "gw,imx8mm-gw72xx-0x"; +}; + +&gpio4 { + rs485_en { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "rs485_en"; + }; + + rs485_hd { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "rs485_hd"; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +&uart4 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dts new file mode 100644 index 000000000000..cc0a287226ab --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dts @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Gateworks Corporation + * + * GW72xx RS485 HD: + * - GPIO1_0 rs485_term selects on-chip termination + * - GPIO4_0 rs485_en needs to be driven high (active) + * - GPIO4_2 rs485_hd needs to be driven high (active) + * - UART4_TX is DE for RS485 transmitter + * - RS485_EN needs to be pulled high + * - RS485_HALF needs to be pulled high + */ + +#include + +#include "imx8mm-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "gw,imx8mm-gw72xx-0x"; +}; + +&gpio4 { + rs485_en { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "rs485_en"; + }; + + rs485_hd { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "rs485_hd"; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +&uart4 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140 + >; + }; +}; -- cgit From 37840653e8a3f733fbf0beec795e14b738c8ab65 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 14 Feb 2022 15:14:23 -0800 Subject: arm64: dts: imx8mm-venice-gw73xx-0x: add dt overlay for imx219 rpi v2 camera Add support for the RaspberryPi Camera v2 which is an IMX219 8MP module: - https://datasheets.raspberrypi.com/camera/camera-v2-schematics.pdf - has its own on-board 24MHz osc so no clock required from baseboard - pin 11 enables 1.8V and 2.8V LDO which is connected to GW73xx MIPI_GPIO4 (IMX8MM GPIO1_IO1) so we use this as a gpio controlled regulator enable. Support is added via a device-tree overlay. The IMX219 supports RAW8/RAW10 image formats. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../freescale/imx8mm-venice-gw73xx-0x-imx219.dts | 93 ++++++++++++++++++++++ 2 files changed, 95 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dts (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 1753f787a609..a84463bea15c 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -102,6 +102,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb imx8mm-venice-gw72xx-0x-rs232-rts-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rs232-rts.dtbo imx8mm-venice-gw72xx-0x-rs422-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rs422.dtbo imx8mm-venice-gw72xx-0x-rs485-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rs485.dtbo +imx8mm-venice-gw73xx-0x-imx219-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-imx219.dtbo imx8mm-venice-gw73xx-0x-rs232-rts-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs232-rts.dtbo imx8mm-venice-gw73xx-0x-rs422-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs422.dtbo imx8mm-venice-gw73xx-0x-rs485-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs485.dtbo @@ -109,6 +110,7 @@ imx8mm-venice-gw73xx-0x-rs485-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice- dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rs232-rts.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rs422.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rs485.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-imx219.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs232-rts.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs422.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs485.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dts new file mode 100644 index 000000000000..f3ece4b7fbbd --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dts @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Gateworks Corporation + */ + +#include + +#include "imx8mm-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "gw,imx8mm-gw73xx-0x", "fsl,imx8mm"; + + reg_cam: regulator-cam { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_cam>; + compatible = "regulator-fixed"; + regulator-name = "reg_cam"; + gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + cam24m: cam24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "cam24m"; + }; +}; + +&csi { + status = "okay"; +}; + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + + imx219: sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + clocks = <&cam24m>; + VDIG-supply = <®_cam>; + + port { + /* MIPI CSI-2 bus endpoint */ + imx219_to_mipi_csi2: endpoint { + remote-endpoint = <&imx8mm_mipi_csi_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <456000000>; + }; + }; + }; +}; + +&mipi_csi { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + imx8mm_mipi_csi_in: endpoint { + remote-endpoint = <&imx219_to_mipi_csi2>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + + imx8mm_mipi_csi_out: endpoint { + remote-endpoint = <&csi_in>; + }; + }; + }; +}; + +&iomuxc { + pinctrl_reg_cam: regcamgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x41 + >; + }; +}; -- cgit From 037d4d885ad8ac02d358f88d5606322f9dd2c80f Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 14 Feb 2022 15:14:24 -0800 Subject: arm64: dts: imx8mm-venice-gw72xx-0x: add dt overlay for imx219 rpi v2 camera Add support for the RaspberryPi Camera v2 which is an IMX219 8MP module: - https://datasheets.raspberrypi.com/camera/camera-v2-schematics.pdf - has its own on-board 24MHz osc so no clock required from baseboard - pin 11 enables 1.8V and 2.8V LDO which is connected to GW73xx MIPI_GPIO4 (IMX8MM GPIO1_IO1) so we use this as a gpio Support is added via a device-tree overlay. The IMX219 supports RAW8/RAW10 image formats. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../freescale/imx8mm-venice-gw72xx-0x-imx219.dts | 93 ++++++++++++++++++++++ 2 files changed, 95 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dts (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index a84463bea15c..7f51b537df40 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -99,6 +99,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb +imx8mm-venice-gw72xx-0x-imx219-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-imx219.dtbo imx8mm-venice-gw72xx-0x-rs232-rts-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rs232-rts.dtbo imx8mm-venice-gw72xx-0x-rs422-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rs422.dtbo imx8mm-venice-gw72xx-0x-rs485-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rs485.dtbo @@ -107,6 +108,7 @@ imx8mm-venice-gw73xx-0x-rs232-rts-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-ven imx8mm-venice-gw73xx-0x-rs422-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs422.dtbo imx8mm-venice-gw73xx-0x-rs485-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs485.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-imx219.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rs232-rts.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rs422.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rs485.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dts new file mode 100644 index 000000000000..4eaf8aabcbff --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dts @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Gateworks Corporation + */ + +#include + +#include "imx8mm-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "gw,imx8mm-gw72xx-0x", "fsl,imx8mm"; + + reg_cam: regulator-cam { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_cam>; + compatible = "regulator-fixed"; + regulator-name = "reg_cam"; + gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + cam24m: cam24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "cam24m"; + }; +}; + +&csi { + status = "okay"; +}; + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + + imx219: sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + clocks = <&cam24m>; + VDIG-supply = <®_cam>; + + port { + /* MIPI CSI-2 bus endpoint */ + imx219_to_mipi_csi2: endpoint { + remote-endpoint = <&imx8mm_mipi_csi_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <456000000>; + }; + }; + }; +}; + +&mipi_csi { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + imx8mm_mipi_csi_in: endpoint { + remote-endpoint = <&imx219_to_mipi_csi2>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + + imx8mm_mipi_csi_out: endpoint { + remote-endpoint = <&csi_in>; + }; + }; + }; +}; + +&iomuxc { + pinctrl_reg_cam: regcamgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x41 + >; + }; +}; -- cgit From 4fab14f01efab40685f0d7ef66760393258ca279 Mon Sep 17 00:00:00 2001 From: Teresa Remmet Date: Fri, 18 Feb 2022 13:04:52 +0100 Subject: arm64: dts: imx8mp-phycore-som: Set minimum output impedance for eth phy To fit spec requirements set minimum output impedance for dp83867 ethernet phy. Signed-off-by: Teresa Remmet Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi index fc178eebf8aa..778f601a0119 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi @@ -60,6 +60,7 @@ ti,tx-internal-delay = ; ti,fifo-depth = ; ti,clk-output-sel = ; + ti,min-output-impedance; enet-phy-lane-no-swap; }; }; -- cgit From c173a181719e7412821a357da0dc97244bf0c52d Mon Sep 17 00:00:00 2001 From: Teresa Remmet Date: Fri, 18 Feb 2022 13:04:53 +0100 Subject: arm64: dts: imx8mp-phycore-som: Adapt eMMC drive strength Set eMMC drive strength for USDHC3_DATA lines (200Mhz) to X4 for signal improvement. Signed-off-by: Teresa Remmet Reviewed-by: Haibo Chen Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi index 778f601a0119..927290990d02 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi @@ -299,14 +299,14 @@ fsl,pins = < MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 >; }; -- cgit From 97c8800e3fe2a3add3fd6d78274b2b5bc0087ba5 Mon Sep 17 00:00:00 2001 From: Teresa Remmet Date: Fri, 18 Feb 2022 13:04:54 +0100 Subject: arm64: dts: imx8mp-phycore-som: Reduce drive strength for fec tx lines Reduce drive strength on fec tx lines for signal quality improvements. Measurements showed that TD0 and TD1 require X4 and the other lines X2 for optimized settings. Signed-off-by: Teresa Remmet Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi index 927290990d02..06e94f6e1702 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi @@ -222,12 +222,12 @@ MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 - MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f - MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f - MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f - MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f - MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f - MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12 + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12 + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x14 + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x14 + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x14 + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14 MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x11 >; }; -- cgit From 2aeded997117b4fa8a113d94ccb2621fc16eda3f Mon Sep 17 00:00:00 2001 From: Teresa Remmet Date: Fri, 18 Feb 2022 13:04:55 +0100 Subject: arm64: dts: imx8mp-phycore-som: Update WDOG muxing To be able to trigger a reset also from an external source we need to configure the WDOG pin as open drain. Signed-off-by: Teresa Remmet Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi index 06e94f6e1702..fb84032e529f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi @@ -313,7 +313,7 @@ pinctrl_wdog: wdoggrp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xe6 >; }; }; -- cgit From 8c0d17856a8778fe49dbb2c1615347ea9bad7a0e Mon Sep 17 00:00:00 2001 From: Teresa Remmet Date: Fri, 18 Feb 2022 13:04:56 +0100 Subject: arm64: dts: imx8mp-phycore-som: Set VDD_ARM run and standby voltage Add bindings for VDD_ARM (BUCK2) run and standby voltage. Signed-off-by: Teresa Remmet Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi index fb84032e529f..4855bfc9e6a3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi @@ -114,6 +114,8 @@ regulator-boot-on; regulator-always-on; regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; }; buck4: BUCK4 { -- cgit From b00e3e03cfa2c8a2d783076ea433e5172e0a958b Mon Sep 17 00:00:00 2001 From: Teresa Remmet Date: Fri, 18 Feb 2022 13:04:57 +0100 Subject: arm64: dts: imx8mp-phycore-som: LDO5 needs to be enabled instead of LDO4 LDO4 is not connected so disable it. And LDO5 is used for VSEL of the NVCC_SD2 SD-Card bus. Having it disabled seems not to have an impact on the functionality. We enable it, as it is used. Signed-off-by: Teresa Remmet Reviewed-by: Haibo Chen Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi index 4855bfc9e6a3..c471ab252a69 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi @@ -170,14 +170,14 @@ regulator-compatible = "LDO4"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; }; ldo5: LDO5 { regulator-compatible = "LDO5"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; }; }; }; -- cgit From 59f5ae05c18a2f4a3f0494ec814155bb44a08dd7 Mon Sep 17 00:00:00 2001 From: Jonas Kuenstler Date: Fri, 18 Feb 2022 13:04:58 +0100 Subject: arm64: dts: imx8mp-phycore-som: Set usdhc root clock for eMMC Set the usdhc root clock to 400MHz to be able to support HS400/HS400ES modes for eMMC on phyCORE-i.MX8MP SoM. Signed-off-by: Jonas Kuenstler Signed-off-by: Teresa Remmet Reviewed-by: Haibo Chen Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi index c471ab252a69..79b290a002c1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi @@ -197,6 +197,8 @@ /* eMMC */ &usdhc3 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>; + assigned-clock-rates = <400000000>; pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; pinctrl-1 = <&pinctrl_usdhc3_100mhz>; -- cgit From d926a4fe25338e120ab49547de9707dc6e5e5824 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Fri, 11 Feb 2022 10:53:11 +0000 Subject: arm64: dts: meson: add support for OSMC Vero 4K+ The OSMC Vero 4K+ device is based on the Amlogic S905D (P230) reference design with the following specifications: - 2GB DDR4 RAM - 16GB eMMC - HDMI 2.1 video - S/PDIF optical output - AV output - 10/100/1000 Ethernet - AP6255 Wireless (802.11 a/b/g/n/ac, BT 4.2) - 2x USB 2.0 ports (1x OTG) - IR receiver (internal) - IR extender port (external) - 1x micro SD card slot - 1x Power LED (red) - 1x Reset button (in AV jack) Signed-off-by: Christian Hewitt Tested-by: Chad Wagner Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220211105311.30320-4-christianshewitt@gmail.com --- arch/arm64/boot/dts/amlogic/Makefile | 1 + .../dts/amlogic/meson-gxl-s905d-vero4k-plus.dts | 117 +++++++++++++++++++++ 2 files changed, 118 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905d-vero4k-plus.dts (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index 13f73ca700ef..0eec18678311 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -36,6 +36,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-phicomm-n1.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-sml5442tw.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-vero4k-plus.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805x-p241.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-p281.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-tx3-mini.dtb diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-vero4k-plus.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-vero4k-plus.dts new file mode 100644 index 000000000000..4b0ff707e21b --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-vero4k-plus.dts @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Author: Christian Hewitt + */ + +/dts-v1/; + +#include "meson-gxl-s905d.dtsi" +#include "meson-gx-p23x-q20x.dtsi" +#include +#include + +/ { + compatible = "osmc,vero4k-plus", "amlogic,s905d", "amlogic,meson-gxl"; + model = "OSMC Vero 4K Plus"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + + button@0 { + label = "power"; + linux,code = ; + gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-standby { + color = ; + function = LED_FUNCTION_POWER; + gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_LOW>; + default-state = "off"; + panic-indicator; + }; + }; +}; + +ðmac { + pinctrl-0 = <ð_pins>; + pinctrl-names = "default"; + + phy-mode = "rgmii-txid"; + phy-handle = <&external_phy>; + + amlogic,tx-delay-ns = <0>; +}; + +&external_mdio { + external_phy: ethernet-phy@0 { + /* Realtek RTL8211F (0x001cc916) */ + pinctrl-0 = <ð_phy_irq_pin>; + pinctrl-names = "default"; + + reg = <0>; + max-speed = <1000>; + + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; + + interrupt-parent = <&gpio_intc>; + interrupts = <25 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&pinctrl_periphs { + /* Ensure the phy irq pin is properly configured as input */ + eth_phy_irq_pin: eth-phy-irq { + mux { + groups = "GPIOZ_15"; + function = "gpio_periphs"; + bias-disable; + output-disable; + }; + }; +}; + +&sd_emmc_a { + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&uart_A { + status = "okay"; + pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + max-speed = <2000000>; + clocks = <&wifi32k>; + clock-names = "lpo"; + }; +}; + +&usb { + dr_mode = "host"; +}; + +&usb2_phy0 { + /* HDMI_5V also supplies the USB VBUS */ + phy-supply = <&hdmi_5v>; +}; + +&usb2_phy0 { + /* HDMI_5V also supplies the USB VBUS */ + phy-supply = <&hdmi_5v>; +}; -- cgit From b90d10da84e3bc58ea12c0298a0dda040a06e9a8 Mon Sep 17 00:00:00 2001 From: Nikita Yushchenko Date: Wed, 16 Feb 2022 21:10:04 +0300 Subject: arm64: dts: renesas: ulcb-kf: fix wrong comment Fix comment referencing salvator board, likely a copy-paste leftover. ulcb-kf.dtsi has nothing to do with salvator. Signed-off-by: Nikita Yushchenko Fixes: 80c07701d5918928 ("arm64: dts: renesas: ulcb-kf: add pcm3168 sound codec") Link: https://lore.kernel.org/r/20220216181003.114049-1-nikita.yoush@cogentembedded.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi index 889d117dadf5..ae532cd21708 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi @@ -414,7 +414,7 @@ &sound_pcm_pins>; ports { - /* rsnd_port0/1 are on salvator-common */ + /* rsnd_port0/1 are defined in ulcb.dtsi */ rsnd_port2: port@2 { reg = <2>; rsnd_for_pcm3168a_play: endpoint { -- cgit From 96bb0954860a4c8b8c77d59fc53cd4cafac914f5 Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Thu, 17 Feb 2022 19:11:03 +0000 Subject: arm64: dts: juno: Add separate SCMI variants While Juno's SCP firmware initially spoke the SCPI protocol, binary releases since 2018, and the newer open-source codebase, only speak SCMI and thus aren't particularly compatibile with the DTs we currently have upstream. Add a parallel set of variant DTs for boards with up-to-date firmware, replacing the SCPI parts with their new SCMI equivalents. Link: https://lore.kernel.org/r/f3516815104f951a05fc0f799681f77d7968f6ac.1645125063.git.robin.murphy@arm.com Signed-off-by: Robin Murphy Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/Makefile | 2 +- arch/arm64/boot/dts/arm/juno-r1-scmi.dts | 23 ++++ arch/arm64/boot/dts/arm/juno-r2-scmi.dts | 23 ++++ arch/arm64/boot/dts/arm/juno-scmi.dts | 9 ++ arch/arm64/boot/dts/arm/juno-scmi.dtsi | 199 +++++++++++++++++++++++++++++++ 5 files changed, 255 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/arm/juno-r1-scmi.dts create mode 100644 arch/arm64/boot/dts/arm/juno-r2-scmi.dts create mode 100644 arch/arm64/boot/dts/arm/juno-scmi.dts create mode 100644 arch/arm64/boot/dts/arm/juno-scmi.dtsi (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile index 800da2e84f3f..4382b73baef5 100644 --- a/arch/arm64/boot/dts/arm/Makefile +++ b/arch/arm64/boot/dts/arm/Makefile @@ -2,7 +2,7 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += \ foundation-v8.dtb foundation-v8-psci.dtb \ foundation-v8-gicv3.dtb foundation-v8-gicv3-psci.dtb -dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb juno-scmi.dtb juno-r1-scmi.dtb juno-r2-scmi.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb diff --git a/arch/arm64/boot/dts/arm/juno-r1-scmi.dts b/arch/arm64/boot/dts/arm/juno-r1-scmi.dts new file mode 100644 index 000000000000..190a0fba4ad6 --- /dev/null +++ b/arch/arm64/boot/dts/arm/juno-r1-scmi.dts @@ -0,0 +1,23 @@ +#include "juno-r1.dts" +#include "juno-scmi.dtsi" + +/ { + funnel@20130000 { + power-domains = <&scmi_devpd 8>; + }; + + etf@20140000 { + power-domains = <&scmi_devpd 0>; + }; + + funnel@20150000 { + power-domains = <&scmi_devpd 0>; + }; +}; + +&A57_0 { + clocks = <&scmi_dvfs 0>; +}; +&A57_1 { + clocks = <&scmi_dvfs 0>; +}; diff --git a/arch/arm64/boot/dts/arm/juno-r2-scmi.dts b/arch/arm64/boot/dts/arm/juno-r2-scmi.dts new file mode 100644 index 000000000000..dbf13770084f --- /dev/null +++ b/arch/arm64/boot/dts/arm/juno-r2-scmi.dts @@ -0,0 +1,23 @@ +#include "juno-r2.dts" +#include "juno-scmi.dtsi" + +/ { + funnel@20130000 { + power-domains = <&scmi_devpd 8>; + }; + + etf@20140000 { + power-domains = <&scmi_devpd 0>; + }; + + funnel@20150000 { + power-domains = <&scmi_devpd 0>; + }; +}; + +&A72_0 { + clocks = <&scmi_dvfs 0>; +}; +&A72_1 { + clocks = <&scmi_dvfs 0>; +}; diff --git a/arch/arm64/boot/dts/arm/juno-scmi.dts b/arch/arm64/boot/dts/arm/juno-scmi.dts new file mode 100644 index 000000000000..41588fa46d31 --- /dev/null +++ b/arch/arm64/boot/dts/arm/juno-scmi.dts @@ -0,0 +1,9 @@ +#include "juno.dts" +#include "juno-scmi.dtsi" + +&A57_0 { + clocks = <&scmi_dvfs 0>; +}; +&A57_1 { + clocks = <&scmi_dvfs 0>; +}; diff --git a/arch/arm64/boot/dts/arm/juno-scmi.dtsi b/arch/arm64/boot/dts/arm/juno-scmi.dtsi new file mode 100644 index 000000000000..d72dcff9bf06 --- /dev/null +++ b/arch/arm64/boot/dts/arm/juno-scmi.dtsi @@ -0,0 +1,199 @@ +/ { + etf@20010000 { + power-domains = <&scmi_devpd 8>; + }; + + tpiu@20030000 { + power-domains = <&scmi_devpd 8>; + }; + + funnel@20040000 { + power-domains = <&scmi_devpd 8>; + }; + + etr@20070000 { + power-domains = <&scmi_devpd 8>; + }; + + stm@20100000 { + power-domains = <&scmi_devpd 8>; + }; + + replicator@20120000 { + power-domains = <&scmi_devpd 8>; + }; + + funnel@220c0000 { + power-domains = <&scmi_devpd 8>; + }; + + funnel@230c0000 { + power-domains = <&scmi_devpd 8>; + }; + + hdlcd@7ff50000 { + clocks = <&scmi_clk 3>; + }; + + hdlcd@7ff60000 { + clocks = <&scmi_clk 3>; + }; + + /delete-node/ scpi; + + firmware { + scmi { + compatible = "arm,scmi"; + mbox-names = "tx", "rx"; + mboxes = <&mailbox 0 0 &mailbox 0 1>; + shmem = <&cpu_scp_lpri0 &cpu_scp_lpri1>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_devpd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi_dvfs: protocol@13 { + reg = <0x13>; + #clock-cells = <1>; + mbox-names = "tx", "rx"; + mboxes = <&mailbox 1 0 &mailbox 1 1>; + shmem = <&cpu_scp_hpri0 &cpu_scp_hpri1>; + }; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_sensors0: protocol@15 { + reg = <0x15>; + #thermal-sensor-cells = <1>; + }; + }; + }; + + thermal-zones { + pmic { + thermal-sensors = <&scmi_sensors0 0>; + }; + + soc { + thermal-sensors = <&scmi_sensors0 3>; + }; + + big-cluster { + thermal-sensors = <&scmi_sensors0 21>; + }; + + little-cluster { + thermal-sensors = <&scmi_sensors0 22>; + }; + + gpu0 { + thermal-sensors = <&scmi_sensors0 23>; + }; + + gpu1 { + thermal-sensors = <&scmi_sensors0 24>; + }; + }; + +}; + +&A53_0 { + clocks = <&scmi_dvfs 1>; +}; +&A53_1 { + clocks = <&scmi_dvfs 1>; +}; +&A53_2 { + clocks = <&scmi_dvfs 1>; +}; +&A53_3 { + clocks = <&scmi_dvfs 1>; +}; + +&cpu_debug0 { + power-domains = <&scmi_devpd 8>; +}; +&cpu_debug1 { + power-domains = <&scmi_devpd 8>; +}; +&cpu_debug2 { + power-domains = <&scmi_devpd 8>; +}; +&cpu_debug3 { + power-domains = <&scmi_devpd 8>; +}; +&cpu_debug4 { + power-domains = <&scmi_devpd 8>; +}; +&cpu_debug5 { + power-domains = <&scmi_devpd 8>; +}; + +&etm0 { + power-domains = <&scmi_devpd 8>; +}; +&etm1 { + power-domains = <&scmi_devpd 8>; +}; +&etm2 { + power-domains = <&scmi_devpd 8>; +}; +&etm3 { + power-domains = <&scmi_devpd 8>; +}; +&etm4 { + power-domains = <&scmi_devpd 8>; +}; +&etm5 { + power-domains = <&scmi_devpd 8>; +}; + +&gpu { + clocks = <&scmi_dvfs 2>; + power-domains = <&scmi_devpd 9>; +}; + +&mailbox { + compatible = "arm,mhu-doorbell", "arm,primecell"; + #mbox-cells = <2>; + mbox-name = "ARM-MHU"; +}; + +&smmu_etr { + power-domains = <&scmi_devpd 8>; +}; + +&smmu_gpu { + power-domains = <&scmi_devpd 9>; +}; + +&sram { + /delete-node/ scp-sram@0; + /delete-node/ scp-sram@200; + + cpu_scp_lpri0: scp-sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x80>; + }; + + cpu_scp_lpri1: scp-sram@80 { + compatible = "arm,scmi-shmem"; + reg = <0x80 0x80>; + }; + + cpu_scp_hpri0: scp-sram@100 { + compatible = "arm,scmi-shmem"; + reg = <0x100 0x80>; + }; + + cpu_scp_hpri1: scp-sram@180 { + compatible = "arm,scmi-shmem"; + reg = <0x180 0x80>; + }; +}; -- cgit From 8ca367e26ad9f86f56a08d0988e28375e388bb97 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 18 Jan 2022 18:09:04 +0100 Subject: arm64: dts: renesas: r8a779f0: Add RWDT node Add a device node for the RCLK Watchdog Timer (RWDT) on the Renesas R-Car S4-8 (R8A779F0) SoC. Extracted from a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven Acked-by: Guenter Roeck Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/556a7f41bdadceecbe8b59b79ac7e9f592ca17a2.1642525158.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index 5426532d10e2..0ac8c345558e 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -59,6 +59,16 @@ #size-cells = <2>; ranges; + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a779f0-wdt", + "renesas,rcar-gen4-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 907>; + status = "disabled"; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a779f0-cpg-mssr"; reg = <0 0xe6150000 0 0x4000>; -- cgit From 1069050467d8c4e91a49d0e95d776c905afb5b03 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 18 Jan 2022 18:09:05 +0100 Subject: arm64: dts: renesas: spider-cpu: Enable watchdog timer Enable the watchdog timer on the Spider board. Extracted from a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven Acked-by: Guenter Roeck Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/b36b2bb5770e10d906571721a3d73ca205b6f56e.1642525158.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi index 156586532c84..3a90932fe85c 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi @@ -31,6 +31,11 @@ clock-frequency = <32768>; }; +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + &scif3 { status = "okay"; }; -- cgit From 223d9ac45efb9311e7b2b0494c3ed25c701c6a5d Mon Sep 17 00:00:00 2001 From: Keerthy Date: Thu, 3 Feb 2022 18:56:47 +0530 Subject: arm64: dts: ti: k3-j721s2-mcu-wakeup: Fix the interrupt-parent for wkup_gpioX instances The interrupt-parent for wkup_gpioX instances are wrongly assigned as main_gpio_intr instead of wkup_gpio_intr. Fix it. Fixes: b8545f9d3a54 ("arm64: dts: ti: Add initial support for J721S2 SoC") Signed-off-by: Keerthy Signed-off-by: Aswath Govindraju Signed-off-by: Nishanth Menon Reviewed-by: Kishon Vijay Abraham I Link: https://lore.kernel.org/r/20220203132647.11314-1-a-govindraju@ti.com --- arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 7521963719ff..6c5c02edb375 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -108,7 +108,7 @@ reg = <0x00 0x42110000 0x00 0x100>; gpio-controller; #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; + interrupt-parent = <&wkup_gpio_intr>; interrupts = <103>, <104>, <105>, <106>, <107>, <108>; interrupt-controller; #interrupt-cells = <2>; @@ -124,7 +124,7 @@ reg = <0x00 0x42100000 0x00 0x100>; gpio-controller; #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; + interrupt-parent = <&wkup_gpio_intr>; interrupts = <112>, <113>, <114>, <115>, <116>, <117>; interrupt-controller; #interrupt-cells = <2>; -- cgit From 8cae268b70f387ff9e697ccd62fb2384079124e7 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 15 Feb 2022 14:10:04 -0600 Subject: arm64: dts: ti: k3-am65: Fix gic-v3 compatible regs Though GIC ARE option is disabled for no GIC-v2 compatibility, Cortex-A53 is free to implement the CPU interface as long as it communicates with the GIC using the stream protocol. This requires that the SoC integration mark out the PERIPHBASE[1] as reserved area within the SoC. See longer discussion in [2] for further information. Update the GIC register map to indicate offsets from PERIPHBASE based on [3]. Without doing this, systems like kvm will not function with gic-v2 emulation. [1] https://developer.arm.com/documentation/ddi0500/e/system-control/aarch64-register-descriptions/configuration-base-address-register--el1 [2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/ [3] https://developer.arm.com/documentation/ddi0500/e/generic-interrupt-controller-cpu-interface/gic-programmers-model/memory-map Cc: stable@vger.kernel.org # 5.10+ Fixes: ea47eed33a3f ("arm64: dts: ti: Add Support for AM654 SoC") Reported-by: Marc Zyngier Signed-off-by: Nishanth Menon Acked-by: Marc Zyngier Link: https://lore.kernel.org/r/20220215201008.15235-2-nm@ti.com --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 5 ++++- arch/arm64/boot/dts/ti/k3-am65.dtsi | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index ce8bb4a61011..e749343acced 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -35,7 +35,10 @@ #interrupt-cells = <3>; interrupt-controller; reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ - <0x00 0x01880000 0x00 0x90000>; /* GICR */ + <0x00 0x01880000 0x00 0x90000>, /* GICR */ + <0x00 0x6f000000 0x00 0x2000>, /* GICC */ + <0x00 0x6f010000 0x00 0x1000>, /* GICH */ + <0x00 0x6f020000 0x00 0x2000>; /* GICV */ /* * vcpumntirq: * virtual CPU interface maintenance interrupt diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi index a58a39fa42db..c538a0bf3cdd 100644 --- a/arch/arm64/boot/dts/ti/k3-am65.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi @@ -86,6 +86,7 @@ <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>, + <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A53 PERIPHBASE */ <0x00 0x70000000 0x00 0x70000000 0x00 0x200000>, <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; -- cgit From a06ed27f3bc63ab9e10007dc0118d910908eb045 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 15 Feb 2022 14:10:05 -0600 Subject: arm64: dts: ti: k3-j721e: Fix gic-v3 compatible regs Though GIC ARE option is disabled for no GIC-v2 compatibility, Cortex-A72 is free to implement the CPU interface as long as it communicates with the GIC using the stream protocol. This requires that the SoC integration mark out the PERIPHBASE[1] as reserved area within the SoC. See longer discussion in [2] for further information. Update the GIC register map to indicate offsets from PERIPHBASE based on [3]. Without doing this, systems like kvm will not function with gic-v2 emulation. [1] https://developer.arm.com/documentation/100095/0002/system-control/aarch64-register-descriptions/configuration-base-address-register--el1 [2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/ [3] https://developer.arm.com/documentation/100095/0002/way1382452674438 Cc: stable@vger.kernel.org # 5.10+ Fixes: 2d87061e70de ("arm64: dts: ti: Add Support for J721E SoC") Reported-by: Marc Zyngier Signed-off-by: Nishanth Menon Acked-by: Marc Zyngier Link: https://lore.kernel.org/r/20220215201008.15235-3-nm@ti.com --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 5 ++++- arch/arm64/boot/dts/ti/k3-j721e.dtsi | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 599861259a30..db0669985e42 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -76,7 +76,10 @@ #interrupt-cells = <3>; interrupt-controller; reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ - <0x00 0x01900000 0x00 0x100000>; /* GICR */ + <0x00 0x01900000 0x00 0x100000>, /* GICR */ + <0x00 0x6f000000 0x00 0x2000>, /* GICC */ + <0x00 0x6f010000 0x00 0x1000>, /* GICH */ + <0x00 0x6f020000 0x00 0x2000>; /* GICV */ /* vcpumntirq: virtual CPU interface maintenance interrupt */ interrupts = ; diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi index 4a3872fce533..0e23886c9fd1 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -139,6 +139,7 @@ <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/ <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */ <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */ + <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */ <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */ <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */ <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */ -- cgit From 1a307cc299430dd7139d351a3b8941f493dfa885 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 15 Feb 2022 14:10:06 -0600 Subject: arm64: dts: ti: k3-j7200: Fix gic-v3 compatible regs Though GIC ARE option is disabled for no GIC-v2 compatibility, Cortex-A72 is free to implement the CPU interface as long as it communicates with the GIC using the stream protocol. This requires that the SoC integration mark out the PERIPHBASE[1] as reserved area within the SoC. See longer discussion in [2] for further information. Update the GIC register map to indicate offsets from PERIPHBASE based on [3]. Without doing this, systems like kvm will not function with gic-v2 emulation. [1] https://developer.arm.com/documentation/100095/0002/system-control/aarch64-register-descriptions/configuration-base-address-register--el1 [2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/ [3] https://developer.arm.com/documentation/100095/0002/way1382452674438 Cc: stable@vger.kernel.org Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC") Reported-by: Marc Zyngier Signed-off-by: Nishanth Menon Acked-by: Marc Zyngier Link: https://lore.kernel.org/r/20220215201008.15235-4-nm@ti.com --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 5 ++++- arch/arm64/boot/dts/ti/k3-j7200.dtsi | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 05a627ad6cdc..16684a2f054d 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -54,7 +54,10 @@ #interrupt-cells = <3>; interrupt-controller; reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ - <0x00 0x01900000 0x00 0x100000>; /* GICR */ + <0x00 0x01900000 0x00 0x100000>, /* GICR */ + <0x00 0x6f000000 0x00 0x2000>, /* GICC */ + <0x00 0x6f010000 0x00 0x1000>, /* GICH */ + <0x00 0x6f020000 0x00 0x2000>; /* GICV */ /* vcpumntirq: virtual CPU interface maintenance interrupt */ interrupts = ; diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi index 64fef4e67d76..b6da0454cc5b 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi @@ -129,6 +129,7 @@ <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */ <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ + <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */ <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */ <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */ -- cgit From de60edf1be3d42d4a1b303b41c7c53b2f865726e Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 15 Feb 2022 14:10:07 -0600 Subject: arm64: dts: ti: k3-am64: Fix gic-v3 compatible regs Though GIC ARE option is disabled for no GIC-v2 compatibility, Cortex-A53 is free to implement the CPU interface as long as it communicates with the GIC using the stream protocol. This requires that the SoC integration mark out the PERIPHBASE[1] as reserved area within the SoC. See longer discussion in [2] for further information. Update the GIC register map to indicate offsets from PERIPHBASE based on [3]. Without doing this, systems like kvm will not function with gic-v2 emulation. [1] https://developer.arm.com/documentation/ddi0500/e/system-control/aarch64-register-descriptions/configuration-base-address-register--el1 [2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/ [3] https://developer.arm.com/documentation/ddi0500/e/generic-interrupt-controller-cpu-interface/gic-programmers-model/memory-map Cc: stable@vger.kernel.org Fixes: 8abae9389bdb ("arm64: dts: ti: Add support for AM642 SoC") Reported-by: Marc Zyngier Signed-off-by: Nishanth Menon Acked-by: Marc Zyngier Link: https://lore.kernel.org/r/20220215201008.15235-5-nm@ti.com --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 5 ++++- arch/arm64/boot/dts/ti/k3-am64.dtsi | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 0c9f3bce8418..f64b368c6c37 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -59,7 +59,10 @@ #interrupt-cells = <3>; interrupt-controller; reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ - <0x00 0x01840000 0x00 0xC0000>; /* GICR */ + <0x00 0x01840000 0x00 0xC0000>, /* GICR */ + <0x01 0x00000000 0x00 0x2000>, /* GICC */ + <0x01 0x00010000 0x00 0x1000>, /* GICH */ + <0x01 0x00020000 0x00 0x2000>; /* GICV */ /* * vcpumntirq: * virtual CPU interface maintenance interrupt diff --git a/arch/arm64/boot/dts/ti/k3-am64.dtsi b/arch/arm64/boot/dts/ti/k3-am64.dtsi index 09ff14643ee6..016dd8511ca6 100644 --- a/arch/arm64/boot/dts/ti/k3-am64.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64.dtsi @@ -90,6 +90,7 @@ <0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe DAT0 */ <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* OC SRAM */ <0x00 0x78000000 0x00 0x78000000 0x00 0x00800000>, /* Main R5FSS */ + <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ <0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe DAT1 */ <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ -- cgit From a966803781fc5e1875511db9392b0d16174c5dd2 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 15 Feb 2022 14:10:08 -0600 Subject: arm64: dts: ti: k3-j721s2: Fix gic-v3 compatible regs Though GIC ARE option is disabled for no GIC-v2 compatibility, Cortex-A72 is free to implement the CPU interface as long as it communicates with the GIC using the stream protocol. This requires that the SoC integration mark out the PERIPHBASE[1] as reserved area within the SoC. See longer discussion in [2] for further information. Update the GIC register map to indicate offsets from PERIPHBASE based on [3]. Without doing this, systems like kvm will not function with gic-v2 emulation. [1] https://developer.arm.com/documentation/100095/0002/system-control/aarch64-register-descriptions/configuration-base-address-register--el1 [2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/ [3] https://developer.arm.com/documentation/100095/0002/way1382452674438 Cc: stable@vger.kernel.org Fixes: b8545f9d3a54 ("arm64: dts: ti: Add initial support for J721S2 SoC") Reported-by: Marc Zyngier Signed-off-by: Nishanth Menon Acked-by: Marc Zyngier Link: https://lore.kernel.org/r/20220215201008.15235-6-nm@ti.com --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 5 ++++- arch/arm64/boot/dts/ti/k3-j721s2.dtsi | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index b04db1d3ab61..be7f39299894 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -34,7 +34,10 @@ #interrupt-cells = <3>; interrupt-controller; reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */ - <0x00 0x01900000 0x00 0x100000>; /* GICR */ + <0x00 0x01900000 0x00 0x100000>, /* GICR */ + <0x00 0x6f000000 0x00 0x2000>, /* GICC */ + <0x00 0x6f010000 0x00 0x1000>, /* GICH */ + <0x00 0x6f020000 0x00 0x2000>; /* GICV */ /* vcpumntirq: virtual CPU interface maintenance interrupt */ interrupts = ; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi index fe5234c40f6c..7b930a85a29d 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi @@ -119,6 +119,7 @@ <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ <0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */ <0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */ + <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */ <0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */ <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */ -- cgit From 672e89d731c46b1f4118a070366dc117afed0f7c Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Thu, 17 Feb 2022 23:40:24 +0530 Subject: arm64: dts: ti: k3-*: Fix whitespace around flash@0 nodes The OSPI flash nodes are missing a space before the opening brace. Fix that. Signed-off-by: Pratyush Yadav Signed-off-by: Nishanth Menon Reviewed-by: Apurva Nandan Link: https://lore.kernel.org/r/20220217181025.1815118-1-p.yadav@ti.com --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 2 +- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 2 +- arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 2 +- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index e94ae178b1ae..edf80e277267 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -498,7 +498,7 @@ pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; - flash@0{ + flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <8>; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index a9785bec12df..30b956276060 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -369,7 +369,7 @@ pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; - flash@0{ + flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <8>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi index 34724440171a..7d819f0db8df 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -256,7 +256,7 @@ pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; - flash@0{ + flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <8>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 2d7596911b27..2ecc4541f6d8 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -482,7 +482,7 @@ pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; - flash@0{ + flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <1>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index 2fee2906183d..990dfcd61018 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -171,7 +171,7 @@ pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; - flash@0{ + flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <8>; -- cgit From cd9342109a7a901a115227978b86a3db6ee3d7a9 Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Thu, 17 Feb 2022 23:40:25 +0530 Subject: arm64: dts: ti: k3-*: Drop address and size cells from flash nodes Specifying partitions directly under the flash nodes is deprecated. A partitions node should used instead. The address and size cells are not needed. Remove them. Signed-off-by: Pratyush Yadav Signed-off-by: Nishanth Menon Reviewed-by: Apurva Nandan Link: https://lore.kernel.org/r/20220217181025.1815118-2-p.yadav@ti.com --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 2 -- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 2 -- arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 2 -- arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 2 -- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 2 -- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 2 -- 6 files changed, 12 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index edf80e277267..8e7893e58b03 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -509,8 +509,6 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; - #address-cells = <1>; - #size-cells = <1>; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 30b956276060..1d7db8bf3a5c 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -380,8 +380,6 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; - #address-cells = <1>; - #size-cells = <1>; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi index 7d819f0db8df..2d615c3e9fa1 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -267,7 +267,5 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; - #address-cells = <1>; - #size-cells = <1>; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 2ecc4541f6d8..f5ca8e26ed99 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -493,8 +493,6 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <2>; - #address-cells = <1>; - #size-cells = <1>; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index b726310d867c..f25d85169e0d 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -475,8 +475,6 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; - #address-cells = <1>; - #size-cells = <1>; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index 990dfcd61018..e36335232cf8 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -182,8 +182,6 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <0>; - #address-cells = <1>; - #size-cells = <1>; }; }; -- cgit From 06874015327ba7bf6aae49ca825a492a2679237f Mon Sep 17 00:00:00 2001 From: David Virag Date: Mon, 21 Feb 2022 20:49:56 +0100 Subject: arm64: dts: exynos: Add initial device tree support for Exynos7885 SoC Add initial Exynos7885 device tree nodes with dts for the Samsung Galaxy A8 (2018), a.k.a. "jackpotlte", with model number "SM-A530F". Currently this includes some clock support, UART support, and I2C nodes. Signed-off-by: David Virag Reviewed-by: Sam Protsenko Link: https://lore.kernel.org/r/20220221194958.117361-2-virag.david003@gmail.com Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/Makefile | 9 +- .../boot/dts/exynos/exynos7885-jackpotlte.dts | 92 +++ arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi | 855 +++++++++++++++++++++ arch/arm64/boot/dts/exynos/exynos7885.dtsi | 423 ++++++++++ 4 files changed, 1375 insertions(+), 4 deletions(-) create mode 100644 arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts create mode 100644 arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/exynos/exynos7885.dtsi (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile index be9df8e85c59..6e4ba69268e5 100644 --- a/arch/arm64/boot/dts/exynos/Makefile +++ b/arch/arm64/boot/dts/exynos/Makefile @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_EXYNOS) += \ - exynos5433-tm2.dtb \ - exynos5433-tm2e.dtb \ - exynos7-espresso.dtb \ - exynos850-e850-96.dtb \ + exynos5433-tm2.dtb \ + exynos5433-tm2e.dtb \ + exynos7-espresso.dtb \ + exynos7885-jackpotlte.dtb \ + exynos850-e850-96.dtb \ exynosautov9-sadk.dtb diff --git a/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts new file mode 100644 index 000000000000..4cf9aa25f618 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung Galaxy A8 2018 (jackpotlte/SM-A530F) device tree source + * + * Copyright (c) 2021 Samsung Electronics Co., Ltd. + * Copyright (c) 2021 Dávid Virág + */ + +/dts-v1/; +#include "exynos7885.dtsi" +#include +#include +#include + +/ { + model = "Samsung Galaxy A8 (2018)"; + compatible = "samsung,jackpotlte", "samsung,exynos7885"; + chassis-type = "handset"; + + aliases { + serial0 = &serial_0; + serial1 = &serial_1; + serial2 = &serial_2; + }; + + chosen { + stdout-path = &serial_2; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x3da00000>, + <0x0 0xc0000000 0x40000000>, + <0x8 0x80000000 0x40000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key_volup &key_voldown &key_power>; + + volup-key { + label = "Volume Up"; + linux,code = ; + gpios = <&gpa1 5 GPIO_ACTIVE_LOW>; + }; + + voldown-key { + label = "Volume Down"; + linux,code = ; + gpios = <&gpa1 6 GPIO_ACTIVE_LOW>; + }; + + power-key { + label = "Power"; + linux,code = ; + gpios = <&gpa1 7 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; +}; + +&oscclk { + clock-frequency = <26000000>; +}; + +&pinctrl_alive { + key_volup: key-volup-pins { + samsung,pins = "gpa1-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + key_voldown: key-voldown-pins { + samsung,pins = "gpa1-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + key_power: key-power-pins { + samsung,pins = "gpa1-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&serial_2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi new file mode 100644 index 000000000000..a50c1dbd5545 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi @@ -0,0 +1,855 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung Exynos7885 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2017 Samsung Electronics Co., Ltd. + * Copyright (c) 2021 Dávid Virág + * + * Samsung's Exynos7885 SoC pin-mux and pin-config options are listed as + * device tree nodes in this file. + */ + +#include +#include + +&pinctrl_alive { + etc0: etc0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + etc1: etc1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa0: gpa0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + gpa1: gpa1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + gpa2: gpa2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpq0: gpq0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sim1_det_gpio: sim1-det-gpio-pins { + samsung,pins = "gpa2-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + sim0_det_gpio: sim0-det-gpio-pins { + samsung,pins = "gpa2-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + speedy_bus: speedy-bus-pins { + samsung,pins = "gpq0-2"; + samsung,pin-function = ; + samsung,pin-con-pdn = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* UART_DEBUG */ + uart2_bus: uart2-bus-pins { + samsung,pins = "gpq0-4", "gpq0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + +&pinctrl_dispaud { + gpb0: gpb0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb1: gpb1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb2: gpb2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + aud_codec_mclk: aud-codec-mclk-pins { + samsung,pins = "gpb0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_codec_mclk_idle: aud-codec-mclk-idle-pins { + samsung,pins = "gpb0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_codec_bus: aud-codec-bus-pins { + samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_codec_bus_idle: aud-codec-bus-idle-pins { + samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_loopback_bus: aud-loopback-bus-pins { + samsung,pins = "gpb1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_loopback_bus_idle: aud-loopback-bus-idle-pins { + samsung,pins = "gpb1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_fm_bus: aud-fm-bus-pins { + samsung,pins = "gpb1-1", "gpb1-2", "gpb1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_fm_bus_idle: aud-fm-bus-idle-pins { + samsung,pins = "gpb1-1", "gpb1-2", "gpb1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_spk_bus: aud-spk-bus-pins { + samsung,pins = "gpb2-0", "gpb2-1", "gpb2-2", "gpb2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_spk_bus_idle: aud-spk-bus-idle-pins { + samsung,pins = "gpb2-0", "gpb2-1", "gpb2-2", "gpb2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + +&pinctrl_fsys { + gpf0: gpf0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf2: gpf2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf3: gpf3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf4: gpf4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sd0_clk: sd0-clk-pins { + samsung,pins = "gpf0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_clk_fast_slew_rate_1x: sd0-clk-fast-slew-rate-1x-pins { + samsung,pins = "gpf0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_clk_fast_slew_rate_2x: sd0-clk-fast-slew-rate-2x-pins { + samsung,pins = "gpf0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_clk_fast_slew_rate_3x: sd0-clk-fast-slew-rate-3x-pins { + samsung,pins = "gpf0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_clk_fast_slew_rate_4x: sd0-clk-fast-slew-rate-4x-pins { + samsung,pins = "gpf0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_cmd: sd0-cmd-pins { + samsung,pins = "gpf0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_rdqs: sd0-rdqs-pins { + samsung,pins = "gpf0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus1: sd0-bus-width1-pins { + samsung,pins = "gpf2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus4: sd0-bus-width4-pins { + samsung,pins = "gpf2-1", "gpf2-2", "gpf2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus8: sd0-bus-width8-pins { + samsung,pins = "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_clk: sd1-clk-pins { + samsung,pins = "gpf3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_clk_fast_slew_rate_1x: sd1-clk-fast-slew-rate-1x-pins { + samsung,pins = "gpf3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_clk_fast_slew_rate_2x: sd1-clk-fast-slew-rate-2x-pins { + samsung,pins = "gpf3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_clk_fast_slew_rate_3x: sd1-clk-fast-slew-rate-3x-pins { + samsung,pins = "gpf3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_clk_fast_slew_rate_4x: sd1-clk-fast-slew-rate-4x-pins { + samsung,pins = "gpf3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_cmd: sd1-cmd-pins { + samsung,pins = "gpf3-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_bus1: sd1-bus-width1-pins { + samsung,pins = "gpf3-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_bus4: sd1-bus-width4-pins { + samsung,pins = "gpf3-3", "gpf3-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_clk: sd2-clk-pins { + samsung,pins = "gpf4-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_clk_fast_slew_rate_1x: sd2-clk-fast-slew-rate-1x-pins { + samsung,pins = "gpf4-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_clk_fast_slew_rate_2x: sd2-clk-fast-slew-rate-2x-pins { + samsung,pins = "gpf4-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_clk_fast_slew_rate_3x: sd2-clk-fast-slew-rate-3x-pins { + samsung,pins = "gpf4-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_clk_fast_slew_rate_4x: sd2-clk-fast-slew-rate-4x-pins { + samsung,pins = "gpf4-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_cmd: sd2-cmd-pins { + samsung,pins = "gpf4-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_bus1: sd2-bus-width1-pins { + samsung,pins = "gpf4-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_bus4: sd2-bus-width4-pins { + samsung,pins = "gpf4-3", "gpf4-4", "gpf4-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_top { + gpc0: gpc0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc2: gpc2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg0: gpg0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg1: gpg1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg2: gpg2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg3: gpg3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg4: gpg4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp0: gpp0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp1: gpp1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp2: gpp2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp3: gpp3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp4: gpp4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp5: gpp5-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp6: gpp6-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp7: gpp7-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp8: gpp8-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + hs_i2c0_bus: hs-i2c0-bus-pins { + samsung,pins = "gpc1-1", "gpc1-0"; + samsung,pin-function = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hs_i2c1_bus: hs-i2c1-bus-pins { + samsung,pins = "gpc1-3", "gpc1-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + hs_i2c2_bus: hs-i2c2-bus-pins { + samsung,pins = "gpc1-5", "gpc1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + hs_i2c3_bus: hs-i2c3-bus-pins { + samsung,pins = "gpc1-7", "gpc1-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + /* USI0 UART */ + uart3_bus_single: uart3-bus-single-pins { + samsung,pins = "gpc2-3", "gpc2-2", "gpc2-1", "gpc2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI0 UART_HSI2C1 */ + uart3_bus_dual: uart3-bus-dual-pins { + samsung,pins = "gpc2-1", "gpc2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI0 HSI2C0 */ + hs_i2c4_bus: hs-i2c4-bus-pins { + samsung,pins = "gpc2-1", "gpc2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + /* USI0 HSI2C1 */ + hs_i2c5_bus: hs-i2c5-bus-pins { + samsung,pins = "gpc2-3", "gpc2-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + /* USI0 SPI */ + spi2_bus: spi2-bus-pins { + samsung,pins = "gpc2-1", "gpc2-0", "gpc2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi2_cs: spi2-cs-pins { + samsung,pins = "gpc2-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* USI1 UART */ + uart4_bus_single: uart4-bus-single-pins { + samsung,pins = "gpc2-7", "gpc2-6", "gpc2-5", "gpc2-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI1 UART_HSI2C1*/ + uart4_bus_dual: uart4-bus-dual-pins { + samsung,pins = "gpc2-5", "gpc2-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI1 HSI2C0 */ + hs_i2c6_bus: hs-i2c6-bus-pins { + samsung,pins = "gpc2-5", "gpc2-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + /* USI1 HSI2C1 */ + hs_i2c7_bus: hs-i2c7-bus-pins { + samsung,pins = "gpc2-7", "gpc2-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + /* USI1 SPI */ + spi3_bus: spi3-bus-pins { + samsung,pins = "gpc2-5", "gpc2-4", "gpc2-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi3_cs: spi3-cs-pins { + samsung,pins = "gpc2-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + fm_lna_en: fm-lna-en-pins { + samsung,pins = "gpg0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + samsung,pin-val = <1>; + }; + + uart1_bus: uart1-bus-pins { + samsung,pins = "gpg1-3", "gpg1-2", "gpg1-1", "gpg1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + i2c7_bus: i2c7-bus-pins { + samsung,pins = "gpg1-5", "gpg1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + aud_dmic_on: aud-dmic-on-pins { + samsung,pins = "gpg2-1"; + samsung,pin-function = ; + samsung,pin-con-pdn = ; + samsung,pin-val = <1>; + }; + + aud_dmic_off: aud-dmic-off-pins { + samsung,pins = "gpg2-1"; + samsung,pin-function = ; + samsung,pin-con-pdn = ; + samsung,pin-val = <0>; + }; + + /* UART_HEALTH */ + uart0_bus: uart0-bus-pins { + samsung,pins = "gpp0-3", "gpp0-2", "gpp0-1", "gpp0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + i2c0_bus: i2c0-bus-pins { + samsung,pins = "gpp1-1", "gpp1-0"; + samsung,pin-function = ; + samsung,pin-con-pdn = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c1_bus: i2c1-bus-pins { + samsung,pins = "gpp1-3", "gpp1-2"; + samsung,pin-function = ; + samsung,pin-con-pdn = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c2_bus: i2c2-bus-pins { + samsung,pins = "gpp2-1", "gpp2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c3_bus: i2c3-bus-pins { + samsung,pins = "gpp3-1", "gpp3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c4_bus: i2c4-bus-pins { + samsung,pins = "gpp4-1", "gpp4-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c5_bus: i2c5-bus-pins { + samsung,pins = "gpp4-3", "gpp4-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c6_bus: i2c6-bus-pins { + samsung,pins = "gpp4-5", "gpp4-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* SPI_ESE */ + spi0_bus: spi0-bus-pins { + samsung,pins = "gpp5-3", "gpp5-2", "gpp5-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi0_cs: spi0-cs-pins { + samsung,pins = "gpp5-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* SPI_FP */ + spi1_bus: spi1-bus-pins { + samsung,pins = "gpp6-3", "gpp6-2", "gpp6-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi1_cs: spi1-cs-pins { + samsung,pins = "gpp6-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* USI2 UART */ + uart5_bus_single: uart5-bus-single-pins { + samsung,pins = "gpp8-1", "gpp8-0", "gpp7-1", "gpp7-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI2 UART_HSI2C1 */ + uart5_bus_dual: uart5-bus-dual-pins { + samsung,pins = "gpp7-1", "gpp7-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI2 HSI2C0 */ + hs_i2c8_bus: hs-i2c8-bus-pins { + samsung,pins = "gpp7-1", "gpp7-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + /* USI2 HSI2C1 */ + hs_i2c9_bus: hs-i2c9-bus-pins { + samsung,pins = "gpp8-1", "gpp8-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + /* USI2 SPI */ + spi4_bus: spi4-bus-pins { + samsung,pins = "gpp7-1", "gpp7-0", "gpp8-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi4_cs: spi4-cs-pins { + samsung,pins = "gpp8-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; diff --git a/arch/arm64/boot/dts/exynos/exynos7885.dtsi b/arch/arm64/boot/dts/exynos/exynos7885.dtsi new file mode 100644 index 000000000000..3170661f5b67 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos7885.dtsi @@ -0,0 +1,423 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung Exynos7885 SoC device tree source + * + * Copyright (c) 2021 Samsung Electronics Co., Ltd. + * Copyright (c) 2021 Dávid Virág + */ + +#include +#include + +/ { + compatible = "samsung,exynos7885"; + #address-cells = <2>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + aliases { + pinctrl0 = &pinctrl_alive; + pinctrl1 = &pinctrl_dispaud; + pinctrl2 = &pinctrl_fsys; + pinctrl3 = &pinctrl_top; + }; + + arm-a53-pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = , + , + , + , + , + ; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>, + <&cpu4>, + <&cpu5>; + }; + + arm-a73-pmu { + compatible = "arm,cortex-a73-pmu"; + interrupts = , + ; + interrupt-affinity = <&cpu6>, + <&cpu7>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + core4 { + cpu = <&cpu4>; + }; + core5 { + cpu = <&cpu5>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu6>; + }; + core1 { + cpu = <&cpu7>; + }; + }; + }; + + cpu0: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x100>; + enable-method = "psci"; + }; + + cpu1: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x101>; + enable-method = "psci"; + }; + + cpu2: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x102>; + enable-method = "psci"; + }; + + cpu3: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x103>; + enable-method = "psci"; + }; + + cpu4: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x200>; + enable-method = "psci"; + }; + + cpu5: cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x201>; + enable-method = "psci"; + }; + + cpu6: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x0>; + enable-method = "psci"; + }; + + cpu7: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x1>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci"; + method = "smc"; + cpu_suspend = <0xc4000001>; + cpu_off = <0x84000002>; + cpu_on = <0xc4000003>; + }; + + timer { + compatible = "arm,armv8-timer"; + /* Hypervisor Virtual Timer interrupt is not wired to GIC */ + interrupts = , + , + , + ; + }; + + fixed-rate-clocks { + oscclk: osc-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "oscclk"; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x20000000>; + + chipid@10000000 { + compatible = "samsung,exynos850-chipid"; + reg = <0x10000000 0x24>; + }; + + gic: interrupt-controller@12301000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x12301000 0x1000>, + <0x12302000 0x2000>, + <0x12304000 0x2000>, + <0x12306000 0x2000>; + interrupts = ; + }; + + cmu_peri: clock-controller@10010000 { + compatible = "samsung,exynos7885-cmu-peri"; + reg = <0x10010000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_PERI_BUS>, + <&cmu_top CLK_DOUT_PERI_SPI0>, + <&cmu_top CLK_DOUT_PERI_SPI1>, + <&cmu_top CLK_DOUT_PERI_UART0>, + <&cmu_top CLK_DOUT_PERI_UART1>, + <&cmu_top CLK_DOUT_PERI_UART2>, + <&cmu_top CLK_DOUT_PERI_USI0>, + <&cmu_top CLK_DOUT_PERI_USI1>, + <&cmu_top CLK_DOUT_PERI_USI2>; + clock-names = "oscclk", + "dout_peri_bus", + "dout_peri_spi0", + "dout_peri_spi1", + "dout_peri_uart0", + "dout_peri_uart1", + "dout_peri_uart2", + "dout_peri_usi0", + "dout_peri_usi1", + "dout_peri_usi2"; + }; + + cmu_core: clock-controller@12000000 { + compatible = "samsung,exynos7885-cmu-core"; + reg = <0x12000000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_CORE_BUS>, + <&cmu_top CLK_DOUT_CORE_CCI>, + <&cmu_top CLK_DOUT_CORE_G3D>; + clock-names = "oscclk", + "dout_core_bus", + "dout_core_cci", + "dout_core_g3d"; + }; + + cmu_top: clock-controller@12060000 { + compatible = "samsung,exynos7885-cmu-top"; + reg = <0x12060000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>; + clock-names = "oscclk"; + }; + + pinctrl_alive: pinctrl@11cb0000 { + compatible = "samsung,exynos7885-pinctrl"; + reg = <0x11cb0000 0x1000>; + + wakeup-interrupt-controller { + compatible = "samsung,exynos7-wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + + pinctrl_fsys: pinctrl@13430000 { + compatible = "samsung,exynos7885-pinctrl"; + reg = <0x13430000 0x1000>; + interrupts = ; + }; + + pinctrl_top: pinctrl@139b0000 { + compatible = "samsung,exynos7885-pinctrl"; + reg = <0x139b0000 0x1000>; + interrupts = ; + }; + + pinctrl_dispaud: pinctrl@148f0000 { + compatible = "samsung,exynos7885-pinctrl"; + reg = <0x148f0000 0x1000>; + interrupts = ; + }; + + pmu_system_controller: system-controller@11c80000 { + compatible = "samsung,exynos7-pmu", "syscon"; + reg = <0x11c80000 0x10000>; + }; + + serial_0: serial@13800000 { + compatible = "samsung,exynos5433-uart"; + reg = <0x13800000 0x100>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_bus>; + clocks = <&cmu_peri CLK_GOUT_UART0_EXT_UCLK>, + <&cmu_peri CLK_GOUT_UART0_PCLK>; + clock-names = "uart", "clk_uart_baud0"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + serial_1: serial@13810000 { + compatible = "samsung,exynos5433-uart"; + reg = <0x13810000 0x100>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_bus>; + clocks = <&cmu_peri CLK_GOUT_UART1_EXT_UCLK>, + <&cmu_peri CLK_GOUT_UART1_PCLK>; + clock-names = "uart", "clk_uart_baud0"; + samsung,uart-fifosize = <256>; + status = "disabled"; + }; + + serial_2: serial@13820000 { + compatible = "samsung,exynos5433-uart"; + reg = <0x13820000 0x100>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_bus>; + clocks = <&cmu_peri CLK_GOUT_UART2_EXT_UCLK>, + <&cmu_peri CLK_GOUT_UART2_PCLK>; + clock-names = "uart", "clk_uart_baud0"; + samsung,uart-fifosize = <256>; + status = "disabled"; + }; + + i2c_0: i2c@13830000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13830000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_bus>; + clocks = <&cmu_peri CLK_GOUT_I2C0_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + i2c_1: i2c@13840000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13840000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_bus>; + clocks = <&cmu_peri CLK_GOUT_I2C1_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + i2c_2: i2c@13850000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13850000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_bus>; + clocks = <&cmu_peri CLK_GOUT_I2C2_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + i2c_3: i2c@13860000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13860000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_bus>; + clocks = <&cmu_peri CLK_GOUT_I2C3_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + i2c_4: i2c@13870000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13870000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_bus>; + clocks = <&cmu_peri CLK_GOUT_I2C4_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + i2c_5: i2c@13880000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13880000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_bus>; + clocks = <&cmu_peri CLK_GOUT_I2C5_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + i2c_6: i2c@13890000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13890000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_bus>; + clocks = <&cmu_peri CLK_GOUT_I2C6_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + i2c_7: i2c@11cd0000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x11cd0000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_bus>; + clocks = <&cmu_peri CLK_GOUT_I2C7_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + }; +}; + +#include "exynos7885-pinctrl.dtsi" +#include "arm/exynos-syscon-restart.dtsi" -- cgit From 8b93fbd95ed46bb0d57e63c65cef155a09a75bb9 Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Thu, 21 Oct 2021 16:10:57 +0530 Subject: arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280 SoCs. Signed-off-by: Odelu Kukatla Acked-by: Georgi Djakov Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1634812857-10676-4-git-send-email-okukatla@codeaurora.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 3572399282d8..c6d26ea805d8 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -4296,6 +4296,14 @@ }; }; + epss_l3: interconnect@18590000 { + compatible = "qcom,sc7280-epss-l3"; + reg = <0 0x18590000 0 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + #interconnect-cells = <1>; + }; + cpufreq_hw: cpufreq@18591000 { compatible = "qcom,cpufreq-epss"; reg = <0 0x18591000 0 0x1000>, -- cgit From 1e8853c698276d20cdee99a8019f9f5e54c5c0a1 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Wed, 9 Feb 2022 23:15:57 +0530 Subject: arm64: dts: qcom: sc7280: Add cpu OPP tables Add OPP tables required to scale DDR/L3 per freq-domain on SC7280 SoCs. Reviewed-by: Douglas Anderson Reviewed-by: Matthias Kaehlcke Signed-off-by: Sibi Sankar Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1644428757-25575-1-git-send-email-quic_sibis@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 230 +++++++++++++++++++++++++++++++++++ 1 file changed, 230 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index c6d26ea805d8..f0b64be63c21 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -163,6 +164,9 @@ &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_0: l2-cache { @@ -183,6 +187,9 @@ &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_100>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_100: l2-cache { @@ -200,6 +207,9 @@ &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_200>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_200: l2-cache { @@ -217,6 +227,9 @@ &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_300>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_300: l2-cache { @@ -234,6 +247,9 @@ &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_400>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; L2_400: l2-cache { @@ -251,6 +267,9 @@ &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_500>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; L2_500: l2-cache { @@ -268,6 +287,9 @@ &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_600>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; L2_600: l2-cache { @@ -285,6 +307,9 @@ &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_700>; + operating-points-v2 = <&cpu7_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 2>; #cooling-cells = <2>; L2_700: l2-cache { @@ -384,6 +409,211 @@ }; }; + cpu0_opp_table: cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + cpu0_opp_300mhz: opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-peak-kBps = <800000 9600000>; + }; + + cpu0_opp_691mhz: opp-691200000 { + opp-hz = /bits/ 64 <691200000>; + opp-peak-kBps = <800000 17817600>; + }; + + cpu0_opp_806mhz: opp-806400000 { + opp-hz = /bits/ 64 <806400000>; + opp-peak-kBps = <800000 20889600>; + }; + + cpu0_opp_941mhz: opp-940800000 { + opp-hz = /bits/ 64 <940800000>; + opp-peak-kBps = <1804000 24576000>; + }; + + cpu0_opp_1152mhz: opp-1152000000 { + opp-hz = /bits/ 64 <1152000000>; + opp-peak-kBps = <2188000 27033600>; + }; + + cpu0_opp_1325mhz: opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + opp-peak-kBps = <2188000 33792000>; + }; + + cpu0_opp_1517mhz: opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + opp-peak-kBps = <3072000 38092800>; + }; + + cpu0_opp_1651mhz: opp-1651200000 { + opp-hz = /bits/ 64 <1651200000>; + opp-peak-kBps = <3072000 41779200>; + }; + + cpu0_opp_1805mhz: opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; + opp-peak-kBps = <4068000 48537600>; + }; + + cpu0_opp_1958mhz: opp-1958400000 { + opp-hz = /bits/ 64 <1958400000>; + opp-peak-kBps = <4068000 48537600>; + }; + + cpu0_opp_2016mhz: opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-peak-kBps = <6220000 48537600>; + }; + }; + + cpu4_opp_table: cpu4-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + cpu4_opp_691mhz: opp-691200000 { + opp-hz = /bits/ 64 <691200000>; + opp-peak-kBps = <1804000 9600000>; + }; + + cpu4_opp_941mhz: opp-940800000 { + opp-hz = /bits/ 64 <940800000>; + opp-peak-kBps = <2188000 17817600>; + }; + + cpu4_opp_1229mhz: opp-1228800000 { + opp-hz = /bits/ 64 <1228800000>; + opp-peak-kBps = <4068000 24576000>; + }; + + cpu4_opp_1344mhz: opp-1344000000 { + opp-hz = /bits/ 64 <1344000000>; + opp-peak-kBps = <4068000 24576000>; + }; + + cpu4_opp_1517mhz: opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + opp-peak-kBps = <4068000 24576000>; + }; + + cpu4_opp_1651mhz: opp-1651200000 { + opp-hz = /bits/ 64 <1651200000>; + opp-peak-kBps = <6220000 38092800>; + }; + + cpu4_opp_1901mhz: opp-1900800000 { + opp-hz = /bits/ 64 <1900800000>; + opp-peak-kBps = <6220000 44851200>; + }; + + cpu4_opp_2054mhz: opp-2054400000 { + opp-hz = /bits/ 64 <2054400000>; + opp-peak-kBps = <6220000 44851200>; + }; + + cpu4_opp_2112mhz: opp-2112000000 { + opp-hz = /bits/ 64 <2112000000>; + opp-peak-kBps = <6220000 44851200>; + }; + + cpu4_opp_2131mhz: opp-2131200000 { + opp-hz = /bits/ 64 <2131200000>; + opp-peak-kBps = <6220000 44851200>; + }; + + cpu4_opp_2208mhz: opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-peak-kBps = <6220000 44851200>; + }; + + cpu4_opp_2400mhz: opp-2400000000 { + opp-hz = /bits/ 64 <2400000000>; + opp-peak-kBps = <8532000 48537600>; + }; + + cpu4_opp_2611mhz: opp-2611200000 { + opp-hz = /bits/ 64 <2611200000>; + opp-peak-kBps = <8532000 48537600>; + }; + }; + + cpu7_opp_table: cpu7-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + cpu7_opp_806mhz: opp-806400000 { + opp-hz = /bits/ 64 <806400000>; + opp-peak-kBps = <1804000 9600000>; + }; + + cpu7_opp_1056mhz: opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-peak-kBps = <2188000 17817600>; + }; + + cpu7_opp_1325mhz: opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + opp-peak-kBps = <4068000 24576000>; + }; + + cpu7_opp_1517mhz: opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + opp-peak-kBps = <4068000 24576000>; + }; + + cpu7_opp_1766mhz: opp-1766400000 { + opp-hz = /bits/ 64 <1766400000>; + opp-peak-kBps = <6220000 38092800>; + }; + + cpu7_opp_1862mhz: opp-1862400000 { + opp-hz = /bits/ 64 <1862400000>; + opp-peak-kBps = <6220000 38092800>; + }; + + cpu7_opp_2035mhz: opp-2035200000 { + opp-hz = /bits/ 64 <2035200000>; + opp-peak-kBps = <6220000 38092800>; + }; + + cpu7_opp_2112mhz: opp-2112000000 { + opp-hz = /bits/ 64 <2112000000>; + opp-peak-kBps = <6220000 44851200>; + }; + + cpu7_opp_2208mhz: opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-peak-kBps = <6220000 44851200>; + }; + + cpu7_opp_2381mhz: opp-2380800000 { + opp-hz = /bits/ 64 <2380800000>; + opp-peak-kBps = <6832000 44851200>; + }; + + cpu7_opp_2400mhz: opp-2400000000 { + opp-hz = /bits/ 64 <2400000000>; + opp-peak-kBps = <8532000 48537600>; + }; + + cpu7_opp_2515mhz: opp-2515200000 { + opp-hz = /bits/ 64 <2515200000>; + opp-peak-kBps = <8532000 48537600>; + }; + + cpu7_opp_2707mhz: opp-2707200000 { + opp-hz = /bits/ 64 <2707200000>; + opp-peak-kBps = <8532000 48537600>; + }; + + cpu7_opp_3014mhz: opp-3014400000 { + opp-hz = /bits/ 64 <3014400000>; + opp-peak-kBps = <8532000 48537600>; + }; + }; + memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the size */ -- cgit From 406c607eccea71386e0eb9ee2d61b0113609f1da Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Tue, 22 Feb 2022 18:50:03 +0100 Subject: arm64: dts: rockchip: enable work led on rk3568-evb1-v10 Enable the blue work LED on the Rockchip RK3568 EVB1-V10. Signed-off-by: Michael Riesch Link: https://lore.kernel.org/r/20220222175004.1308990-1-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts index 39c495ff0157..848e8f908b3f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include #include "rk3568.dtsi" @@ -33,6 +34,19 @@ regulator-max-microvolt = <12000000>; }; + leds { + compatible = "gpio-leds"; + + led_work: led-0 { + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_HEARTBEAT; + color = ; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&led_work_en>; + }; + }; + vcc3v3_sys: vcc3v3-sys { compatible = "regulator-fixed"; regulator-name = "vcc3v3_sys"; @@ -404,6 +418,12 @@ }; }; + leds { + led_work_en: led_work_en { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { pmic_int: pmic_int { rockchip,pins = -- cgit From 738bbac5612236bd8734f12bdc0122a591b0cb25 Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Wed, 23 Feb 2022 17:20:54 +0100 Subject: arm64: dts: rockchip: add the vdd_cpu regulator to rk3568-evb1-v10 The TCS4525 voltage regulator provides the vdd_cpu on the Rockchip RK3568 EVB1. Add the device tree node and connect it to the CPU nodes. Signed-off-by: Michael Riesch Link: https://lore.kernel.org/r/20220223162054.1626257-1-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts | 33 ++++++++++++++++++++++++ 1 file changed, 33 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts index 848e8f908b3f..8a2c0917213c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts @@ -122,6 +122,22 @@ }; }; +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + &gmac0 { assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; @@ -162,6 +178,23 @@ &i2c0 { status = "okay"; + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + rk809: pmic@20 { compatible = "rockchip,rk809"; reg = <0x20>; -- cgit From bbe5d394c76bd534a0819f78a900ac1a83f3ee9e Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Wed, 23 Feb 2022 12:20:08 +0100 Subject: arm64: dts: rockchip: set vdd_gpu regulator on rk3568-evb1-v10 to always on As discussed in [0], the Rockchip power domain driver does not consider the external supplies (such as VDD_GPU on the RK3568 EVB1). In the scope of this discussion it has been pointed out that turning this voltage on/off on the fly is not explicitly supported. This patch follows the other RK356x boards by example and sets the vdd_gpu regulator to always on. [0] https://lore.kernel.org/linux-rockchip/20211217130919.3035788-1-s.hauer@pengutronix.de/ Signed-off-by: Michael Riesch Link: https://lore.kernel.org/r/20220223112008.1316132-1-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts index 8a2c0917213c..66866f9d0943 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts @@ -233,6 +233,7 @@ vdd_gpu: DCDC_REG2 { regulator-name = "vdd_gpu"; + regulator-always-on; regulator-init-microvolt = <900000>; regulator-initial-mode = <0x2>; regulator-min-microvolt = <500000>; -- cgit From 3e4c629ca680785af2cd6bfd688e958b03db921e Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Tue, 22 Feb 2022 18:50:04 +0100 Subject: arm64: dts: rockchip: enable rk809 audio codec on the rk3568 evb1-v10 Enable the Rockchip RK809 audio codec on the Rockchip RK3568 EVB1-V10. This requires the VCCIO_ACODEC voltage regulator to be set to always on. Signed-off-by: Michael Riesch Link: https://lore.kernel.org/r/20220222175004.1308990-2-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts | 31 +++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts index 66866f9d0943..a794a0ea5c70 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts @@ -47,6 +47,20 @@ }; }; + rk809-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "Analog RK809"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&rk809>; + }; + }; + vcc3v3_sys: vcc3v3-sys { compatible = "regulator-fixed"; regulator-name = "vcc3v3_sys"; @@ -200,10 +214,15 @@ reg = <0x20>; interrupt-parent = <&gpio0>; interrupts = ; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; #clock-cells = <1>; + clock-names = "mclk"; + clocks = <&cru I2S1_MCLKOUT_TX>; pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; + pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>; rockchip,system-power-controller; + #sound-dai-cells = <0>; vcc1-supply = <&vcc3v3_sys>; vcc2-supply = <&vcc3v3_sys>; vcc3-supply = <&vcc3v3_sys>; @@ -318,6 +337,7 @@ vccio_acodec: LDO_REG4 { regulator-name = "vccio_acodec"; + regulator-always-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -402,6 +422,10 @@ }; }; }; + + codec { + mic-in-differential; + }; }; }; @@ -422,6 +446,11 @@ }; }; +&i2s1_8ch { + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + &mdio0 { rgmii_phy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; -- cgit From a0024f55eb5b741b76a0b950f1222ddbab6a9fc9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 14 Feb 2022 09:19:16 +0100 Subject: arm64: dts: rockchip: align Google CROS EC PWM node name with dtschema dtschema expects PWM node name to be a generic "pwm". This also matches Devicetree specification requirements about generic node names. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Douglas Anderson Link: https://lore.kernel.org/r/20220214081916.162014-5-krzysztof.kozlowski@canonical.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi index 9b2c679f5eca..3355fb90fa54 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi @@ -462,7 +462,7 @@ ap_i2c_tp: &i2c5 { }; &cros_ec { - cros_ec_pwm: ec-pwm { + cros_ec_pwm: pwm { compatible = "google,cros-ec-pwm"; #pwm-cells = <1>; }; -- cgit From 29aed4b4eb992966f6f29a6a9885fe4357d604da Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Tue, 22 Feb 2022 09:49:50 +0530 Subject: arm64: dts: qcom: sdm845: Add gsi dma node This add the device node for gsi dma0 instances found in sdm845. Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220222041951.1185186-1-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 46 ++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 0d6286d27dd4..00dd1661f7f3 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1125,6 +1125,29 @@ }; }; + gpi_dma0: dma-controller@800000 { + #dma-cells = <3>; + compatible = "qcom,sdm845-gpi-dma"; + reg = <0 0x00800000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <13>; + dma-channel-mask = <0xfa>; + iommus = <&apps_smmu 0x0016 0x0>; + status = "disabled"; + }; + qupv3_id_0: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x008c0000 0 0x6000>; @@ -1544,6 +1567,29 @@ }; }; + gpi_dma1: dma-controller@0xa00000 { + #dma-cells = <3>; + compatible = "qcom,sdm845-gpi-dma"; + reg = <0 0x00a00000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <13>; + dma-channel-mask = <0xfa>; + iommus = <&apps_smmu 0x06d6 0x0>; + status = "disabled"; + }; + qupv3_id_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x00ac0000 0 0x6000>; -- cgit From 8f6e20adaaf34cfe1101f1b1bc9d2af01d05ee1f Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Tue, 22 Feb 2022 09:49:51 +0530 Subject: arm64: dts: qcom: sdm845: enable dma for spi Add dmas property for spi@880000 and pinconf setting so that we can use dma for this spi device. Also, add iommu properties for qup and spi. Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220222041951.1185186-2-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 4 ++++ arch/arm64/boot/dts/qcom/sdm845.dtsi | 11 +++++++++++ 2 files changed, 15 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 2cf4b932aee2..28fe45c5d516 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -425,6 +425,10 @@ status = "okay"; }; +&gpi_dma0 { + status = "okay"; +}; + &gpu { status = "okay"; zap-shader { diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 00dd1661f7f3..1438711b6476 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -1194,6 +1195,9 @@ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -2633,6 +2637,13 @@ "gpio2", "gpio3"; function = "qup0"; }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <6>; + bias-disable; + }; }; qup_spi1_default: qup-spi1-default { -- cgit From cfc090a0c960688944f2561cdedc8a07d6c9a3c3 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 15 Feb 2022 23:15:37 +0300 Subject: arm64: dts: qcom: sdm845: add bi_tcxo to camcc Declare TCXO clock used for the Camera Clock Controller on SDM845. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220215201539.3970459-4-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 1438711b6476..c2a22e4c9523 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4196,6 +4196,8 @@ #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; }; dsi_opp_table: dsi-opp-table { -- cgit From 79b9ced5652912ce50d7f8dda33d8c9e2052b73c Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 15 Feb 2022 23:15:38 +0300 Subject: arm64: dts: qcom: msm8996: add cxo and sleep-clk to gcc node Supply proper cxo (RPM_SMD_BB_CLK1) and sleep_clk to the gcc clock controller node. Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220215201539.3970459-5-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index c85825ea1623..0c1f6db13521 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -679,8 +679,10 @@ #power-domain-cells = <1>; reg = <0x00300000 0x90000>; - clocks = <&rpmcc RPM_SMD_LN_BB_CLK>; - clock-names = "cxo2"; + clocks = <&rpmcc RPM_SMD_BB_CLK1>, + <&rpmcc RPM_SMD_LN_BB_CLK>, + <&sleep_clk>; + clock-names = "cxo", "cxo2", "sleep_clk"; }; tsens0: thermal-sensor@4a9000 { -- cgit From 2b8c9c77c268c7806e8c0149e23e00fbf8862687 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 15 Feb 2022 23:15:39 +0300 Subject: arm64: dts: qcom: msm8996: convert xo_board to RPM_SMD_BB_CLK1 Convert all device tree xo_board users to the RPM_SMD_BB_CLK1 clock. Note, that xo_board can not be removed (yet), as clk-smd-rpm uses xo_board internally as the parent for all the clocks. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220215201539.3970459-6-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 0c1f6db13521..f0f81c23c16f 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -889,7 +889,7 @@ #clock-cells = <1>; #phy-cells = <0>; - clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; + clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>; clock-names = "iface", "ref"; status = "disabled"; }; @@ -2595,7 +2595,7 @@ reg = <0x06400000 0x90000>; clock-names = "xo"; - clocks = <&xo_board>; + clocks = <&rpmcc RPM_SMD_BB_CLK1>; #clock-cells = <1>; }; @@ -2706,7 +2706,7 @@ clock-names = "iface", "core", "xo"; clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, - <&xo_board>; + <&rpmcc RPM_SMD_BB_CLK1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc1_state_on>; @@ -2729,7 +2729,7 @@ clock-names = "iface", "core", "xo"; clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>, - <&xo_board>; + <&rpmcc RPM_SMD_BB_CLK1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc2_state_on>; @@ -3030,7 +3030,7 @@ interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - clocks = <&xo_board>; + clocks = <&rpmcc RPM_SMD_BB_CLK1>; clock-names = "xo"; memory-region = <&adsp_region>; -- cgit From d4b341269efb3c7fb37747064f7381c21dd7b983 Mon Sep 17 00:00:00 2001 From: Xilin Wu Date: Wed, 23 Feb 2022 22:51:32 +0800 Subject: arm64: dts: qcom: Add support for Samsung Galaxy Book2 Add support for Samsung Galaxy Book2 (W737) tablets. Currently working features: - Bootloader preconfigured display at 1280p - UFS - Wacom Digitizer - Two USB 3 ports - Sound - Bluetooth - Wi-Fi Signed-off-by: Xilin Wu Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220223145130.544586-1-wuxilin123@gmail.com --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts | 748 +++++++++++++++++++++++ 3 files changed, 750 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index bcdc9abf0c42..06e7b87a4ad0 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -107,6 +107,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-apollo.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-shift-axolotl.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb dtb-$(CONFIG_ARCH_QCOM) += sm7225-fairphone-fp4.dtb diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index c2a22e4c9523..41f4e46e1f85 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2017,7 +2017,7 @@ }; }; - system-cache-controller@1100000 { + llcc: system-cache-controller@1100000 { compatible = "qcom,sdm845-llcc"; reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>; reg-names = "llcc_base", "llcc_broadcast_base"; diff --git a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts new file mode 100644 index 000000000000..2a552d817b03 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts @@ -0,0 +1,748 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Samsung Galaxy Book2 + * + * Copyright (c) 2022, Xilin Wu + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include "sdm850.dtsi" +#include "pm8998.dtsi" + +/* + * Update following upstream (sdm845.dtsi) reserved + * memory mappings for firmware loading to succeed + */ +/delete-node/ &qseecom_mem; +/delete-node/ &wlan_msa_mem; +/delete-node/ &slpi_mem; +/delete-node/ &ipa_fw_mem; +/delete-node/ &ipa_gsi_mem; +/delete-node/ &gpu_mem; +/delete-node/ &mpss_region; +/delete-node/ &adsp_mem; +/delete-node/ &cdsp_mem; +/delete-node/ &venus_mem; +/delete-node/ &mba_region; +/delete-node/ &spss_mem; + +/ { + model = "Samsung Galaxy Book2"; + compatible = "samsung,w737", "qcom,sdm845"; + chassis-type = "convertible"; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + // Firmware initialized the display at 1280p instead of 1440p + framebuffer0: framebuffer@80400000 { + compatible = "simple-framebuffer"; + reg = <0 0x80400000 0 (1920 * 1280 * 4)>; + width = <1920>; + height = <1280>; + stride = <(1920 * 4)>; + format = "a8r8g8b8"; + }; + }; + + aliases { + hsuart0 = &uart6; + }; + + /* Reserved memory changes */ + reserved-memory { + /* Bootloader display framebuffer region */ + cont_splash_mem: memory@80400000 { + reg = <0x0 0x80400000 0x0 0x960000>; + no-map; + }; + + qseecom_mem: memory@8b500000 { + reg = <0 0x8b500000 0 0xa00000>; + no-map; + }; + + wlan_msa_mem: memory@8c400000 { + reg = <0 0x8c400000 0 0x100000>; + no-map; + }; + + slpi_mem: memory@8c500000 { + reg = <0 0x8c500000 0 0x1200000>; + no-map; + }; + + ipa_fw_mem: memory@8d700000 { + reg = <0 0x8d700000 0 0x100000>; + no-map; + }; + + gpu_mem: memory@8d800000 { + reg = <0 0x8d800000 0 0x5000>; + no-map; + }; + + mpss_region: memory@8e000000 { + reg = <0 0x8e000000 0 0x8000000>; + no-map; + }; + + adsp_mem: memory@96000000 { + reg = <0 0x96000000 0 0x2000000>; + no-map; + }; + + cdsp_mem: memory@98000000 { + reg = <0 0x98000000 0 0x800000>; + no-map; + }; + + venus_mem: memory@98800000 { + reg = <0 0x98800000 0 0x500000>; + no-map; + }; + + mba_region: memory@98d00000 { + reg = <0 0x98d00000 0 0x200000>; + no-map; + }; + + spss_mem: memory@98f00000 { + reg = <0 0x98f00000 0 0x100000>; + no-map; + }; + }; +}; + +&adsp_pas { + firmware-name = "qcom/samsung/w737/qcadsp850.mbn"; + status = "okay"; +}; + +&apps_rsc { + pm8998-rpmh-regulators { + compatible = "qcom,pm8998-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; + + vreg_s2a_1p125: smps2 { + }; + + vreg_s3a_1p35: smps3 { + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + regulator-initial-mode = ; + }; + + vreg_s4a_1p8: smps4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_s5a_2p04: smps5 { + regulator-min-microvolt = <2040000>; + regulator-max-microvolt = <2040000>; + regulator-initial-mode = ; + }; + + vreg_s7a_1p025: smps7 { + }; + + vdd_qusb_hs0: + vdda_hp_pcie_core: + vdda_mipi_csi0_0p9: + vdda_mipi_csi1_0p9: + vdda_mipi_csi2_0p9: + vdda_mipi_dsi0_pll: + vdda_mipi_dsi1_pll: + vdda_qlink_lv: + vdda_qlink_lv_ck: + vdda_qrefs_0p875: + vdda_pcie_core: + vdda_pll_cc_ebi01: + vdda_pll_cc_ebi23: + vdda_sp_sensor: + vdda_ufs1_core: + vdda_ufs2_core: + vdda_usb1_ss_core: + vdda_usb2_ss_core: + vreg_l1a_0p875: ldo1 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vddpx_10: + vreg_l2a_1p2: ldo2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l3a_1p0: ldo3 { + }; + + vdd_wcss_cx: + vdd_wcss_mx: + vdda_wcss_pll: + vreg_l5a_0p8: ldo5 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vddpx_13: + vreg_l6a_1p8: ldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l7a_1p8: ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l8a_1p2: ldo8 { + }; + + vreg_l9a_1p8: ldo9 { + }; + + vreg_l10a_1p8: ldo10 { + }; + + vreg_l11a_1p0: ldo11 { + }; + + vdd_qfprom: + vdd_qfprom_sp: + vdda_apc1_cs_1p8: + vdda_gfx_cs_1p8: + vdda_qrefs_1p8: + vdda_qusb_hs0_1p8: + vddpx_11: + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vddpx_2: + vreg_l13a_2p95: ldo13 { + }; + + vreg_l14a_1p88: ldo14 { + regulator-min-microvolt = <1880000>; + regulator-max-microvolt = <1880000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l15a_1p8: ldo15 { + }; + + vreg_l16a_2p7: ldo16 { + }; + + vreg_l17a_1p3: ldo17 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l18a_1p8: ldo18 { + }; + + vreg_l19a_3p0: ldo19 { + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3108000>; + regulator-initial-mode = ; + }; + + vreg_l20a_2p95: ldo20 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l21a_2p95: ldo21 { + }; + + vreg_l22a_2p85: ldo22 { + }; + + vreg_l23a_3p3: ldo23 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vdda_qusb_hs0_3p1: + vreg_l24a_3p075: ldo24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3083000>; + regulator-initial-mode = ; + }; + + vreg_l25a_3p3: ldo25 { + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3112000>; + regulator-initial-mode = ; + }; + + vdda_hp_pcie_1p2: + vdda_hv_ebi0: + vdda_hv_ebi1: + vdda_hv_ebi2: + vdda_hv_ebi3: + vdda_mipi_csi_1p25: + vdda_mipi_dsi0_1p2: + vdda_mipi_dsi1_1p2: + vdda_pcie_1p2: + vdda_ufs1_1p2: + vdda_ufs2_1p2: + vdda_usb1_ss_1p2: + vdda_usb2_ss_1p2: + vreg_l26a_1p2: ldo26 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1208000>; + regulator-initial-mode = ; + }; + + vreg_l28a_3p0: ldo28 { + }; + + vreg_lvs1a_1p8: lvs1 { + }; + + vreg_lvs2a_1p8: lvs2 { + }; + }; +}; + +&cdsp_pas { + firmware-name = "qcom/samsung/w737/qccdsp850.mbn"; + status = "okay"; +}; + +&gcc { + protected-clocks = , + , + , + , + ; +}; + +&i2c10 { + status = "okay"; + clock-frequency = <400000>; + + /* SN65DSI86 @ 0x2c */ + /* The panel requires dual DSI, which is not supported by the bridge driver */ +}; + +&i2c11 { + status = "okay"; + clock-frequency = <400000>; + + /* HID-I2C Touchscreen @ 0x20 */ +}; + +&i2c15 { + status = "okay"; + clock-frequency = <400000>; + + digitizer@9 { + compatible = "wacom,w9013", "hid-over-i2c"; + reg = <0x9>; + pinctrl-names = "default"; + pinctrl-0 = <&pen_irq_l>, <&pen_pdct_l>, <&pen_rst_l>; + + post-power-on-delay-ms = <120>; + + interrupt-parent = <&tlmm>; + interrupts = <119 IRQ_TYPE_LEVEL_LOW>; + + hid-descr-addr = <0x1>; + }; +}; + +&ipa { + status = "okay"; + memory-region = <&ipa_fw_mem>; + firmware-name = "qcom/samsung/w737/ipa_fws.elf"; +}; + +/* No idea why it causes an SError when enabled */ +&llcc { + status = "disabled"; +}; + +&mss_pil { + status = "okay"; + firmware-name = "qcom/samsung/w737/qcdsp1v2850.mbn", "qcom/samsung/w737/qcdsp2850.mbn"; +}; + +&qup_i2c10_default { + pinconf { + pins = "gpio55", "gpio56"; + drive-strength = <2>; + bias-disable; + }; +}; + +&qup_i2c11_default { + pinconf { + pins = "gpio31", "gpio32"; + drive-strength = <2>; + bias-disable; + }; +}; + +&qup_i2c12_default { + drive-strength = <2>; + bias-disable; +}; + +&qup_uart6_default { + pinmux { + pins = "gpio45", "gpio46", "gpio47", "gpio48"; + function = "qup6"; + }; + + cts { + pins = "gpio45"; + bias-pull-down; + }; + + rts-tx { + pins = "gpio46", "gpio47"; + drive-strength = <2>; + bias-disable; + }; + + rx { + pins = "gpio48"; + bias-pull-up; + }; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&q6asmdai { + dai@0 { + reg = <0>; + }; + + dai@1 { + reg = <1>; + }; + + dai@2 { + reg = <2>; + }; +}; + +&sound { + compatible = "qcom,sdm845-sndcard"; + model = "Samsung-W737"; + + audio-routing = + "RX_BIAS", "MCLK", + "AMIC2", "MIC BIAS2", + "SpkrLeft IN", "SPK1 OUT", + "SpkrRight IN", "SPK2 OUT", + "MM_DL1", "MultiMedia1 Playback", + "MM_DL3", "MultiMedia3 Playback", + "MultiMedia2 Capture", "MM_UL2"; + + mm1-dai-link { + link-name = "MultiMedia1"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; + }; + }; + + mm2-dai-link { + link-name = "MultiMedia2"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; + }; + }; + + mm3-dai-link { + link-name = "MultiMedia3"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; + }; + }; + + slim-dai-link { + link-name = "SLIM Playback"; + cpu { + sound-dai = <&q6afedai SLIMBUS_0_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9340 0>; + }; + }; + + slimcap-dai-link { + link-name = "SLIM Capture"; + cpu { + sound-dai = <&q6afedai SLIMBUS_0_TX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&wcd9340 1>; + }; + }; + + slim-wcd-dai-link { + link-name = "SLIM WCD Playback"; + cpu { + sound-dai = <&q6afedai SLIMBUS_1_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&wcd9340 2>; + }; + }; +}; + +&tlmm { + gpio-reserved-ranges = <0 6>, <85 4>; + + pen_irq_l: pen-irq-l { + pinmux { + pins = "gpio119"; + function = "gpio"; + }; + + pinconf { + pins = "gpio119"; + bias-disable; + }; + }; + + pen_pdct_l: pen-pdct-l { + pinmux { + pins = "gpio124"; + function = "gpio"; + }; + + pinconf { + pins = "gpio124"; + bias-disable; + drive-strength = <2>; + output-high; + }; + }; + + pen_rst_l: pen-rst-l { + pinmux { + pins = "gpio21"; + function = "gpio"; + }; + + pinconf { + pins = "gpio21"; + bias-disable; + drive-strength = <2>; + + /* + * The pen driver doesn't currently support + * driving this reset line. By specifying + * output-high here we're relying on the fact + * that this pin has a default pulldown at boot + * (which makes sure the pen was in reset if it + * was powered) and then we set it high here to + * take it out of reset. Better would be if the + * pen driver could control this and we could + * remove "output-high" here. + */ + output-high; + }; + }; + + wcd_intr_default: wcd_intr_default { + pins = "gpio54"; + function = "gpio"; + + input-enable; + bias-pull-down; + drive-strength = <2>; + }; +}; + +&uart6 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3990-bt"; + + vddio-supply = <&vreg_s4a_1p8>; + vddxo-supply = <&vreg_l7a_1p8>; + vddrf-supply = <&vreg_l17a_1p3>; + vddch0-supply = <&vreg_l25a_3p3>; + vddch1-supply = <&vreg_l23a_3p3>; + max-speed = <3200000>; + }; +}; + +&ufs_mem_hc { + status = "okay"; + + reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l20a_2p95>; + vcc-max-microamp = <600000>; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vdda_ufs1_core>; + vdda-pll-supply = <&vdda_ufs1_1p2>; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "host"; +}; + +&usb_1_hsphy { + status = "okay"; + + vdd-supply = <&vdda_usb1_ss_core>; + vdda-pll-supply = <&vdda_qusb_hs0_1p8>; + vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; + + qcom,imp-res-offset-value = <8>; + qcom,hstx-trim-value = ; + qcom,preemphasis-level = ; + qcom,preemphasis-width = ; +}; + +&usb_1_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vdda_usb1_ss_1p2>; + vdda-pll-supply = <&vdda_usb1_ss_core>; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; + +&usb_2_hsphy { + status = "okay"; + + vdd-supply = <&vdda_usb2_ss_core>; + vdda-pll-supply = <&vdda_qusb_hs0_1p8>; + vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; + + qcom,imp-res-offset-value = <8>; + qcom,hstx-trim-value = ; +}; + +&usb_2_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vdda_usb2_ss_1p2>; + vdda-pll-supply = <&vdda_usb2_ss_core>; +}; + +&venus { + status = "okay"; + firmware-name = "qcom/samsung/w737/qcvss850.mbn"; +}; + +&wcd9340{ + pinctrl-0 = <&wcd_intr_default>; + pinctrl-names = "default"; + clock-names = "extclk"; + clocks = <&rpmhcc RPMH_LN_BB_CLK2>; + reset-gpios = <&tlmm 64 0>; + vdd-buck-supply = <&vreg_s4a_1p8>; + vdd-buck-sido-supply = <&vreg_s4a_1p8>; + vdd-tx-supply = <&vreg_s4a_1p8>; + vdd-rx-supply = <&vreg_s4a_1p8>; + vdd-io-supply = <&vreg_s4a_1p8>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + + swm: swm@c85 { + left_spkr: wsa8810-left{ + compatible = "sdw10217211000"; + reg = <0 3>; + powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>; + #thermal-sensor-cells = <0>; + sound-name-prefix = "SpkrLeft"; + #sound-dai-cells = <0>; + }; + + right_spkr: wsa8810-right{ + compatible = "sdw10217211000"; + powerdown-gpios = <&wcdgpio 2 GPIO_ACTIVE_HIGH>; + reg = <0 4>; + #thermal-sensor-cells = <0>; + sound-name-prefix = "SpkrRight"; + #sound-dai-cells = <0>; + }; + }; +}; + +&wifi { + status = "okay"; + + vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; + vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; + vdd-3.3-ch1-supply = <&vreg_l23a_3p3>; + + qcom,snoc-host-cap-8bit-quirk; +}; -- cgit From d05e409e4a66f62e863b140bd1c784f2d93f2562 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 23 Feb 2022 16:58:13 +0000 Subject: arm64: dts: renesas: rzg2lc-smarc-som: Enable watchdog Enable watchdog{0, 1, 2} interfaces on RZ/G2LC SMARC EVK. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220223165813.24833-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi index 90cb7ec45751..88a7938017aa 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi @@ -206,3 +206,17 @@ }; #endif +&wdt0 { + status = "okay"; + timeout-sec = <60>; +}; + +&wdt1 { + status = "okay"; + timeout-sec = <60>; +}; + +&wdt2 { + status = "okay"; + timeout-sec = <60>; +}; -- cgit From 48d8ee5b831ec8b6dbe3b4313fed0adcd752e20b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 24 Feb 2022 13:33:40 +0100 Subject: arm64: dts: renesas: Align GPIO hog names with dtschema Dtschema expects GPIO hogs to end with a "hog" suffix. Also, the convention for node names is to use hyphens, not underscores. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/baee4b9980576ffbab24122fce7147c9cbc2ea59.1645705998.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi | 2 +- arch/arm64/boot/dts/renesas/hihope-common.dtsi | 2 +- arch/arm64/boot/dts/renesas/hihope-rzg2-ex-lvds.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a774c0-ek874-idk-2121wr.dts | 2 +- arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts | 4 ++-- arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi | 4 ++-- arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 2 +- 7 files changed, 9 insertions(+), 9 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi index 17d5c4501bbe..877d076ffcc9 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi @@ -77,7 +77,7 @@ }; &gpio6 { - usb_hub_reset { + usb-hub-reset-hog { gpio-hog; gpios = <10 GPIO_ACTIVE_HIGH>; output-high; diff --git a/arch/arm64/boot/dts/renesas/hihope-common.dtsi b/arch/arm64/boot/dts/renesas/hihope-common.dtsi index 0c7e6f790590..935d06515aa6 100644 --- a/arch/arm64/boot/dts/renesas/hihope-common.dtsi +++ b/arch/arm64/boot/dts/renesas/hihope-common.dtsi @@ -140,7 +140,7 @@ }; &gpio6 { - usb1-reset { + usb1-reset-hog { gpio-hog; gpios = <10 GPIO_ACTIVE_LOW>; output-low; diff --git a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex-lvds.dtsi b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex-lvds.dtsi index 40c5e8d6d841..d66d17e34694 100644 --- a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex-lvds.dtsi +++ b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex-lvds.dtsi @@ -20,7 +20,7 @@ * When GP1_20 is LOW LVDS0 is connected to the LVDS connector * When GP1_20 is HIGH LVDS0 is connected to the LT8918L */ - lvds-connector-en-gpio { + lvds-connector-en-hog { gpio-hog; gpios = <20 GPIO_ACTIVE_HIGH>; output-low; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-ek874-idk-2121wr.dts b/arch/arm64/boot/dts/renesas/r8a774c0-ek874-idk-2121wr.dts index a7b27d09f6c2..c1812d1ef06a 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0-ek874-idk-2121wr.dts +++ b/arch/arm64/boot/dts/renesas/r8a774c0-ek874-idk-2121wr.dts @@ -68,7 +68,7 @@ * When GP0_17 is low LVDS[01] are connected to the LVDS connector * When GP0_17 is high LVDS[01] are connected to the LT8918L */ - lvds-connector-en-gpio{ + lvds-connector-en-hog { gpio-hog; gpios = <17 GPIO_ACTIVE_HIGH>; output-low; diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts index 49d141db53f7..fc334b4c2aa4 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts @@ -18,8 +18,8 @@ }; &pinctrl { - /delete-node/ can0-stb; - /delete-node/ can1-stb; + /delete-node/ can0-stb-hog; + /delete-node/ can1-stb-hog; /delete-node/ gpio-sd0-pwr-en-hog; /delete-node/ sd0-dev-sel-hog; /delete-node/ sd1-pwr-en-hog; diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi index 2ef217445f72..9085d8c76ce1 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi @@ -18,7 +18,7 @@ }; /* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */ - can0-stb { + can0-stb-hog { gpio-hog; gpios = ; output-low; @@ -31,7 +31,7 @@ }; /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */ - can1-stb { + can1-stb-hog { gpio-hog; gpios = ; output-low; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi index bff56d696936..37ff2091582e 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi @@ -34,7 +34,7 @@ #if SW_RSPI_CAN /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */ - can1-stb { + can1-stb-hog { gpio-hog; gpios = ; output-low; -- cgit From 156af9de093289f98d4625b874c19f40262b2423 Mon Sep 17 00:00:00 2001 From: Akhil R Date: Mon, 24 Jan 2022 16:48:15 +0530 Subject: arm64: tegra: Add Tegra234 I2C devicetree nodes Add device tree nodes for Tegra234 I2C controllers Signed-off-by: Akhil R Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 121 +++++++++++++++++++++++++++++++ 1 file changed, 121 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 6b6f15804a1a..c686827b8183 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -144,6 +144,96 @@ status = "disabled"; }; + gen1_i2c: i2c@3160000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0x3160000 0x100>; + status = "disabled"; + interrupts = ; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA234_CLK_I2C1 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C1>; + reset-names = "i2c"; + }; + + cam_i2c: i2c@3180000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0x3180000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA234_CLK_I2C3 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C3>; + reset-names = "i2c"; + }; + + dp_aux_ch1_i2c: i2c@3190000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0x3190000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <100000>; + clocks = <&bpmp TEGRA234_CLK_I2C4 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C4>; + reset-names = "i2c"; + }; + + dp_aux_ch0_i2c: i2c@31b0000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0x31b0000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <100000>; + clocks = <&bpmp TEGRA234_CLK_I2C6 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C6>; + reset-names = "i2c"; + }; + + dp_aux_ch2_i2c: i2c@31c0000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0x31c0000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <100000>; + clocks = <&bpmp TEGRA234_CLK_I2C7 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C7>; + reset-names = "i2c"; + }; + + dp_aux_ch3_i2c: i2c@31e0000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0x31e0000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <100000>; + clocks = <&bpmp TEGRA234_CLK_I2C9 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C9>; + reset-names = "i2c"; + }; + mmc@3460000 { compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; reg = <0x03460000 0x20000>; @@ -212,6 +302,37 @@ #mbox-cells = <2>; }; + gen2_i2c: i2c@c240000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0xc240000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <100000>; + clocks = <&bpmp TEGRA234_CLK_I2C2 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA234_RESET_I2C2>; + reset-names = "i2c"; + }; + + gen8_i2c: i2c@c250000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0xc250000 0x100>; + nvidia,hw-instance-id = <0x7>; + interrupts = ; + status = "disabled"; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA234_CLK_I2C8 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA234_RESET_I2C8>; + reset-names = "i2c"; + }; + rtc@c2a0000 { compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; reg = <0x0c2a0000 0x10000>; -- cgit From 5e69088d70d519da9987bc39e210ae2758dbe2a8 Mon Sep 17 00:00:00 2001 From: Akhil R Date: Mon, 24 Jan 2022 16:48:17 +0530 Subject: arm64: tegra: Add Tegra234 PWM devicetree nodes Add device tree nodes for Tegra234 PWM Signed-off-by: Akhil R Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index c686827b8183..cbebf1ee5958 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -234,6 +234,18 @@ reset-names = "i2c"; }; + pwm1: pwm@3280000 { + compatible = "nvidia,tegra194-pwm", + "nvidia,tegra186-pwm"; + reg = <0x3280000 0x10000>; + clocks = <&bpmp TEGRA234_CLK_PWM1>; + clock-names = "pwm"; + resets = <&bpmp TEGRA234_RESET_PWM1>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + mmc@3460000 { compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; reg = <0x03460000 0x20000>; -- cgit From 835553b3c64e2443e09f1043b1dbe871271e6f9a Mon Sep 17 00:00:00 2001 From: Akhil R Date: Mon, 7 Feb 2022 20:31:34 +0530 Subject: arm64: tegra: Add GPCDMA node for tegra186 and tegra194 Add device tree node for GPCDMA controller on Tegra186 target and Tegra194 target. Signed-off-by: Rajesh Gumasta Signed-off-by: Akhil R Reviewed-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 42 +++++++++++++++++++++++++++++++ arch/arm64/boot/dts/nvidia/tegra194.dtsi | 43 ++++++++++++++++++++++++++++++++ 2 files changed, 85 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index c91afff1b757..899d7b1cb780 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -73,6 +73,48 @@ snps,rxpbl = <8>; }; + gpcdma: dma-controller@2600000 { + compatible = "nvidia,tegra186-gpcdma"; + reg = <0x0 0x2600000 0x0 0x210000>; + resets = <&bpmp TEGRA186_RESET_GPCDMA>; + reset-names = "gpcdma"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + #dma-cells = <1>; + iommus = <&smmu TEGRA186_SID_GPCDMA_0>; + dma-coherent; + status = "okay"; + }; + aconnect@2900000 { compatible = "nvidia,tegra186-aconnect", "nvidia,tegra210-aconnect"; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 2d48c3715fc6..8b58f5cb3186 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -115,6 +115,49 @@ snps,rxpbl = <8>; }; + gpcdma: dma-controller@2600000 { + compatible = "nvidia,tegra194-gpcdma", + "nvidia,tegra186-gpcdma"; + reg = <0x2600000 0x210000>; + resets = <&bpmp TEGRA194_RESET_GPCDMA>; + reset-names = "gpcdma"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + #dma-cells = <1>; + iommus = <&smmu TEGRA194_SID_GPCDMA_0>; + dma-coherent; + status = "okay"; + }; + aconnect@2900000 { compatible = "nvidia,tegra194-aconnect", "nvidia,tegra210-aconnect"; -- cgit From 699349e09be0216875f209e736beebba88cfc1ea Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 8 Nov 2021 13:22:00 +0100 Subject: arm64: tegra: Enable gpio-keys on Jetson AGX Orin Developer Kit Expose power, force-recovery and sleep buttons via a gpio-keys device so that userspace can receive events from them. Signed-off-by: Thierry Reding --- .../dts/nvidia/tegra234-p3737-0000+p3701-0000.dts | 31 ++++++++++++++++++++++ arch/arm64/boot/dts/nvidia/tegra234.dtsi | 1 + 2 files changed, 32 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts index efbbb878ba5a..cf9acabdc50a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts @@ -1,6 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; +#include +#include + #include "tegra234-p3701-0000.dtsi" #include "tegra234-p3737-0000.dtsi" @@ -18,6 +21,34 @@ stdout-path = "serial0:115200n8"; }; + gpio-keys { + compatible = "gpio-keys"; + status = "okay"; + + force-recovery { + label = "Force Recovery"; + gpios = <&gpio TEGRA234_MAIN_GPIO(G, 0) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + }; + + power-key { + label = "Power"; + gpios = <&gpio_aon TEGRA234_AON_GPIO(EE, 4) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + wakeup-event-action = ; + wakeup-source; + }; + + suspend { + label = "Suspend"; + gpios = <&gpio TEGRA234_MAIN_GPIO(G, 2) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + }; + }; + serial { status = "okay"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index cbebf1ee5958..02d4d7862f7f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include +#include #include #include #include -- cgit From 5710e16afa6cd385d3bd2becb47635dabbc050e7 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 8 Nov 2021 13:35:23 +0100 Subject: arm64: tegra: Add Tegra234 IOMMUs The NVIDIA Tegra234 SoC comes with one single-instance ARM SMMU used by isochronous memory clients and two dual-instance ARM SMMUs used by non- isochronous memory clients. Add the corresponding device tree nodes and hook up existing memory clients (SDHCI and BPMP). Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 426 +++++++++++++++++++++++++++++++ 1 file changed, 426 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 02d4d7862f7f..7786fd8e3cc6 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -262,6 +262,7 @@ interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>; nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; @@ -300,6 +301,148 @@ #mbox-cells = <2>; }; + smmu_niso1: iommu@8000000 { + compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; + reg = <0x8000000 0x1000000>, + <0x7000000 0x1000000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + stream-match-mask = <0x7f80>; + #global-interrupts = <2>; + #iommu-cells = <1>; + + nvidia,memory-controller = <&mc>; + status = "okay"; + }; + hsp_aon: hsp@c150000 { compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; reg = <0x0c150000 0x90000>; @@ -395,6 +538,288 @@ #interrupt-cells = <3>; interrupt-controller; }; + + smmu_iso: iommu@10000000{ + compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; + reg = <0x10000000 0x1000000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + stream-match-mask = <0x7f80>; + #global-interrupts = <1>; + #iommu-cells = <1>; + + nvidia,memory-controller = <&mc>; + status = "okay"; + }; + + smmu_niso0: iommu@12000000 { + compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; + reg = <0x12000000 0x1000000>, + <0x11000000 0x1000000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + stream-match-mask = <0x7f80>; + #global-interrupts = <2>; + #iommu-cells = <1>; + + nvidia,memory-controller = <&mc>; + status = "okay"; + }; }; sram@40000000 { @@ -430,6 +855,7 @@ <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; interconnect-names = "read", "write", "dma-mem", "dma-write"; + iommus = <&smmu_niso1 TEGRA234_SID_BPMP>; bpmp_i2c: i2c { compatible = "nvidia,tegra186-bpmp-i2c"; -- cgit From cd0c2edf20f0307098fc2be668ecdb533ab3e248 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 8 Jul 2021 12:34:32 +0200 Subject: arm64: tegra: Move audio IOMMU properties to ADMAIF node The ADMAIF node represents the device that accesses memory in the Tegra audio subsystem, so that's where the iommus and interconnects properties should reside. Move them out of the sound card node and into the ADMAIF node to properly reflect the memory data path. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 8b58f5cb3186..db26a5741e48 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -286,6 +286,10 @@ "rx19", "tx19", "rx20", "tx20"; status = "disabled"; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, + <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA194_SID_APE>; }; tegra_i2s1: i2s@2901000 { @@ -2919,11 +2923,6 @@ * for 8x and 11.025x sample rate streams. */ assigned-clock-rates = <258000000>; - - interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, - <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; - interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_APE>; }; tcu: serial { -- cgit From dc94a94daa39131163a5444c6fd9c5e3ed3e7fe0 Mon Sep 17 00:00:00 2001 From: Sameer Pujar Date: Thu, 27 Jan 2022 12:57:34 +0530 Subject: arm64: tegra: Add audio devices on Tegra234 Add following devices which are part of APE subsystem * ACONNECT, AGIC and ADMA * AHUB and children (ADMAIF, I2S, DMIC, DSPK, MVC, SFC, AMX, ADX and Mixer) Signed-off-by: Sameer Pujar Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 419 +++++++++++++++++++++++++++++++ 1 file changed, 419 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 7786fd8e3cc6..d20da6af7172 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -5,6 +5,7 @@ #include #include #include +#include #include / { @@ -20,6 +21,424 @@ ranges = <0x0 0x0 0x0 0x40000000>; + aconnect@2900000 { + compatible = "nvidia,tegra234-aconnect", + "nvidia,tegra210-aconnect"; + clocks = <&bpmp TEGRA234_CLK_APE>, + <&bpmp TEGRA234_CLK_APB2APE>; + clock-names = "ape", "apb2ape"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x02900000 0x02900000 0x200000>; + status = "disabled"; + + tegra_ahub: ahub@2900800 { + compatible = "nvidia,tegra234-ahub"; + reg = <0x02900800 0x800>; + clocks = <&bpmp TEGRA234_CLK_AHUB>; + clock-names = "ahub"; + assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x02900800 0x02900800 0x11800>; + status = "disabled"; + + tegra_i2s1: i2s@2901000 { + compatible = "nvidia,tegra234-i2s", + "nvidia,tegra210-i2s"; + reg = <0x2901000 0x100>; + clocks = <&bpmp TEGRA234_CLK_I2S1>, + <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S1"; + status = "disabled"; + }; + + tegra_i2s2: i2s@2901100 { + compatible = "nvidia,tegra234-i2s", + "nvidia,tegra210-i2s"; + reg = <0x2901100 0x100>; + clocks = <&bpmp TEGRA234_CLK_I2S2>, + <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S2"; + status = "disabled"; + }; + + tegra_i2s3: i2s@2901200 { + compatible = "nvidia,tegra234-i2s", + "nvidia,tegra210-i2s"; + reg = <0x2901200 0x100>; + clocks = <&bpmp TEGRA234_CLK_I2S3>, + <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S3"; + status = "disabled"; + }; + + tegra_i2s4: i2s@2901300 { + compatible = "nvidia,tegra234-i2s", + "nvidia,tegra210-i2s"; + reg = <0x2901300 0x100>; + clocks = <&bpmp TEGRA234_CLK_I2S4>, + <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S4"; + status = "disabled"; + }; + + tegra_i2s5: i2s@2901400 { + compatible = "nvidia,tegra234-i2s", + "nvidia,tegra210-i2s"; + reg = <0x2901400 0x100>; + clocks = <&bpmp TEGRA234_CLK_I2S5>, + <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S5"; + status = "disabled"; + }; + + tegra_i2s6: i2s@2901500 { + compatible = "nvidia,tegra234-i2s", + "nvidia,tegra210-i2s"; + reg = <0x2901500 0x100>; + clocks = <&bpmp TEGRA234_CLK_I2S6>, + <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S6"; + status = "disabled"; + }; + + tegra_sfc1: sfc@2902000 { + compatible = "nvidia,tegra234-sfc", + "nvidia,tegra210-sfc"; + reg = <0x2902000 0x200>; + sound-name-prefix = "SFC1"; + status = "disabled"; + }; + + tegra_sfc2: sfc@2902200 { + compatible = "nvidia,tegra234-sfc", + "nvidia,tegra210-sfc"; + reg = <0x2902200 0x200>; + sound-name-prefix = "SFC2"; + status = "disabled"; + }; + + tegra_sfc3: sfc@2902400 { + compatible = "nvidia,tegra234-sfc", + "nvidia,tegra210-sfc"; + reg = <0x2902400 0x200>; + sound-name-prefix = "SFC3"; + status = "disabled"; + }; + + tegra_sfc4: sfc@2902600 { + compatible = "nvidia,tegra234-sfc", + "nvidia,tegra210-sfc"; + reg = <0x2902600 0x200>; + sound-name-prefix = "SFC4"; + status = "disabled"; + }; + + tegra_amx1: amx@2903000 { + compatible = "nvidia,tegra234-amx", + "nvidia,tegra194-amx"; + reg = <0x2903000 0x100>; + sound-name-prefix = "AMX1"; + status = "disabled"; + }; + + tegra_amx2: amx@2903100 { + compatible = "nvidia,tegra234-amx", + "nvidia,tegra194-amx"; + reg = <0x2903100 0x100>; + sound-name-prefix = "AMX2"; + status = "disabled"; + }; + + tegra_amx3: amx@2903200 { + compatible = "nvidia,tegra234-amx", + "nvidia,tegra194-amx"; + reg = <0x2903200 0x100>; + sound-name-prefix = "AMX3"; + status = "disabled"; + }; + + tegra_amx4: amx@2903300 { + compatible = "nvidia,tegra234-amx", + "nvidia,tegra194-amx"; + reg = <0x2903300 0x100>; + sound-name-prefix = "AMX4"; + status = "disabled"; + }; + + tegra_adx1: adx@2903800 { + compatible = "nvidia,tegra234-adx", + "nvidia,tegra210-adx"; + reg = <0x2903800 0x100>; + sound-name-prefix = "ADX1"; + status = "disabled"; + }; + + tegra_adx2: adx@2903900 { + compatible = "nvidia,tegra234-adx", + "nvidia,tegra210-adx"; + reg = <0x2903900 0x100>; + sound-name-prefix = "ADX2"; + status = "disabled"; + }; + + tegra_adx3: adx@2903a00 { + compatible = "nvidia,tegra234-adx", + "nvidia,tegra210-adx"; + reg = <0x2903a00 0x100>; + sound-name-prefix = "ADX3"; + status = "disabled"; + }; + + tegra_adx4: adx@2903b00 { + compatible = "nvidia,tegra234-adx", + "nvidia,tegra210-adx"; + reg = <0x2903b00 0x100>; + sound-name-prefix = "ADX4"; + status = "disabled"; + }; + + + tegra_dmic1: dmic@2904000 { + compatible = "nvidia,tegra234-dmic", + "nvidia,tegra210-dmic"; + reg = <0x2904000 0x100>; + clocks = <&bpmp TEGRA234_CLK_DMIC1>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC1"; + status = "disabled"; + }; + + tegra_dmic2: dmic@2904100 { + compatible = "nvidia,tegra234-dmic", + "nvidia,tegra210-dmic"; + reg = <0x2904100 0x100>; + clocks = <&bpmp TEGRA234_CLK_DMIC2>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC2"; + status = "disabled"; + }; + + tegra_dmic3: dmic@2904200 { + compatible = "nvidia,tegra234-dmic", + "nvidia,tegra210-dmic"; + reg = <0x2904200 0x100>; + clocks = <&bpmp TEGRA234_CLK_DMIC3>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC3"; + status = "disabled"; + }; + + tegra_dmic4: dmic@2904300 { + compatible = "nvidia,tegra234-dmic", + "nvidia,tegra210-dmic"; + reg = <0x2904300 0x100>; + clocks = <&bpmp TEGRA234_CLK_DMIC4>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC4"; + status = "disabled"; + }; + + tegra_dspk1: dspk@2905000 { + compatible = "nvidia,tegra234-dspk", + "nvidia,tegra186-dspk"; + reg = <0x2905000 0x100>; + clocks = <&bpmp TEGRA234_CLK_DSPK1>; + clock-names = "dspk"; + assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; + assigned-clock-rates = <12288000>; + sound-name-prefix = "DSPK1"; + status = "disabled"; + }; + + tegra_dspk2: dspk@2905100 { + compatible = "nvidia,tegra234-dspk", + "nvidia,tegra186-dspk"; + reg = <0x2905100 0x100>; + clocks = <&bpmp TEGRA234_CLK_DSPK2>; + clock-names = "dspk"; + assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; + assigned-clock-rates = <12288000>; + sound-name-prefix = "DSPK2"; + status = "disabled"; + }; + + tegra_mvc1: mvc@290a000 { + compatible = "nvidia,tegra234-mvc", + "nvidia,tegra210-mvc"; + reg = <0x290a000 0x200>; + sound-name-prefix = "MVC1"; + status = "disabled"; + }; + + tegra_mvc2: mvc@290a200 { + compatible = "nvidia,tegra234-mvc", + "nvidia,tegra210-mvc"; + reg = <0x290a200 0x200>; + sound-name-prefix = "MVC2"; + status = "disabled"; + }; + + tegra_amixer: amixer@290bb00 { + compatible = "nvidia,tegra234-amixer", + "nvidia,tegra210-amixer"; + reg = <0x290bb00 0x800>; + sound-name-prefix = "MIXER1"; + status = "disabled"; + }; + + tegra_admaif: admaif@290f000 { + compatible = "nvidia,tegra234-admaif", + "nvidia,tegra186-admaif"; + reg = <0x0290f000 0x1000>; + dmas = <&adma 1>, <&adma 1>, + <&adma 2>, <&adma 2>, + <&adma 3>, <&adma 3>, + <&adma 4>, <&adma 4>, + <&adma 5>, <&adma 5>, + <&adma 6>, <&adma 6>, + <&adma 7>, <&adma 7>, + <&adma 8>, <&adma 8>, + <&adma 9>, <&adma 9>, + <&adma 10>, <&adma 10>, + <&adma 11>, <&adma 11>, + <&adma 12>, <&adma 12>, + <&adma 13>, <&adma 13>, + <&adma 14>, <&adma 14>, + <&adma 15>, <&adma 15>, + <&adma 16>, <&adma 16>, + <&adma 17>, <&adma 17>, + <&adma 18>, <&adma 18>, + <&adma 19>, <&adma 19>, + <&adma 20>, <&adma 20>; + dma-names = "rx1", "tx1", + "rx2", "tx2", + "rx3", "tx3", + "rx4", "tx4", + "rx5", "tx5", + "rx6", "tx6", + "rx7", "tx7", + "rx8", "tx8", + "rx9", "tx9", + "rx10", "tx10", + "rx11", "tx11", + "rx12", "tx12", + "rx13", "tx13", + "rx14", "tx14", + "rx15", "tx15", + "rx16", "tx16", + "rx17", "tx17", + "rx18", "tx18", + "rx19", "tx19", + "rx20", "tx20"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso0 TEGRA234_SID_APE>; + status = "disabled"; + }; + }; + + adma: dma-controller@2930000 { + compatible = "nvidia,tegra234-adma", + "nvidia,tegra186-adma"; + reg = <0x02930000 0x20000>; + interrupt-parent = <&agic>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + #dma-cells = <1>; + clocks = <&bpmp TEGRA234_CLK_AHUB>; + clock-names = "d_audio"; + status = "disabled"; + }; + + agic: interrupt-controller@2a40000 { + compatible = "nvidia,tegra234-agic", + "nvidia,tegra210-agic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x02a41000 0x1000>, + <0x02a42000 0x2000>; + interrupts = ; + clocks = <&bpmp TEGRA234_CLK_APE>; + clock-names = "clk"; + status = "disabled"; + }; + }; + misc@100000 { compatible = "nvidia,tegra234-misc"; reg = <0x00100000 0xf000>, -- cgit From 09614acd87e6b47253112f5d2d9603b878092c57 Mon Sep 17 00:00:00 2001 From: Sameer Pujar Date: Thu, 27 Jan 2022 12:57:35 +0530 Subject: arm64: tegra: APE sound card for Jetson AGX Orin Add audio-graph based sound card support on Jetson AGX Orin platform. The sound card binds following modules: * I/O interfaces such as I2S and DMIC (to be specific I2S1, I2S2, I2S4, I2S6 and DMIC3 instances). * HW accelerators such as MVC, SFC, AMX, ADX and Mixer (all the available instances). Signed-off-by: Sameer Pujar Signed-off-by: Thierry Reding --- .../dts/nvidia/tegra234-p3737-0000+p3701-0000.dts | 1783 ++++++++++++++++++++ arch/arm64/boot/dts/nvidia/tegra234.dtsi | 14 + 2 files changed, 1797 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts index cf9acabdc50a..e8c3def36e00 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts @@ -16,6 +16,1734 @@ serial0 = &tcu; }; + bus@0 { + aconnect@2900000 { + status = "okay"; + + ahub@2900800 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + xbar_admaif0: endpoint { + remote-endpoint = <&admaif0>; + }; + }; + + port@1 { + reg = <0x1>; + + xbar_admaif1: endpoint { + remote-endpoint = <&admaif1>; + }; + }; + + port@2 { + reg = <0x2>; + + xbar_admaif2: endpoint { + remote-endpoint = <&admaif2>; + }; + }; + + port@3 { + reg = <0x3>; + + xbar_admaif3: endpoint { + remote-endpoint = <&admaif3>; + }; + }; + + port@4 { + reg = <0x4>; + + xbar_admaif4: endpoint { + remote-endpoint = <&admaif4>; + }; + }; + + port@5 { + reg = <0x5>; + + xbar_admaif5: endpoint { + remote-endpoint = <&admaif5>; + }; + }; + + port@6 { + reg = <0x6>; + + xbar_admaif6: endpoint { + remote-endpoint = <&admaif6>; + }; + }; + + port@7 { + reg = <0x7>; + + xbar_admaif7: endpoint { + remote-endpoint = <&admaif7>; + }; + }; + + port@8 { + reg = <0x8>; + + xbar_admaif8: endpoint { + remote-endpoint = <&admaif8>; + }; + }; + + port@9 { + reg = <0x9>; + + xbar_admaif9: endpoint { + remote-endpoint = <&admaif9>; + }; + }; + + port@a { + reg = <0xa>; + + xbar_admaif10: endpoint { + remote-endpoint = <&admaif10>; + }; + }; + + port@b { + reg = <0xb>; + + xbar_admaif11: endpoint { + remote-endpoint = <&admaif11>; + }; + }; + + port@c { + reg = <0xc>; + + xbar_admaif12: endpoint { + remote-endpoint = <&admaif12>; + }; + }; + + port@d { + reg = <0xd>; + + xbar_admaif13: endpoint { + remote-endpoint = <&admaif13>; + }; + }; + + port@e { + reg = <0xe>; + + xbar_admaif14: endpoint { + remote-endpoint = <&admaif14>; + }; + }; + + port@f { + reg = <0xf>; + + xbar_admaif15: endpoint { + remote-endpoint = <&admaif15>; + }; + }; + + port@10 { + reg = <0x10>; + + xbar_admaif16: endpoint { + remote-endpoint = <&admaif16>; + }; + }; + + port@11 { + reg = <0x11>; + + xbar_admaif17: endpoint { + remote-endpoint = <&admaif17>; + }; + }; + + port@12 { + reg = <0x12>; + + xbar_admaif18: endpoint { + remote-endpoint = <&admaif18>; + }; + }; + + port@13 { + reg = <0x13>; + + xbar_admaif19: endpoint { + remote-endpoint = <&admaif19>; + }; + }; + + xbar_i2s1_port: port@14 { + reg = <0x14>; + + xbar_i2s1: endpoint { + remote-endpoint = <&i2s1_cif>; + }; + }; + + xbar_i2s2_port: port@15 { + reg = <0x15>; + + xbar_i2s2: endpoint { + remote-endpoint = <&i2s2_cif>; + }; + }; + + xbar_i2s4_port: port@17 { + reg = <0x17>; + + xbar_i2s4: endpoint { + remote-endpoint = <&i2s4_cif>; + }; + }; + + xbar_i2s6_port: port@19 { + reg = <0x19>; + + xbar_i2s6: endpoint { + remote-endpoint = <&i2s6_cif>; + }; + }; + + xbar_dmic3_port: port@1c { + reg = <0x1c>; + + xbar_dmic3: endpoint { + remote-endpoint = <&dmic3_cif>; + }; + }; + + xbar_sfc1_in_port: port@20 { + reg = <0x20>; + + xbar_sfc1_in: endpoint { + remote-endpoint = <&sfc1_cif_in>; + }; + }; + + port@21 { + reg = <0x21>; + + xbar_sfc1_out: endpoint { + remote-endpoint = <&sfc1_cif_out>; + }; + }; + + xbar_sfc2_in_port: port@22 { + reg = <0x22>; + + xbar_sfc2_in: endpoint { + remote-endpoint = <&sfc2_cif_in>; + }; + }; + + port@23 { + reg = <0x23>; + + xbar_sfc2_out: endpoint { + remote-endpoint = <&sfc2_cif_out>; + }; + }; + + xbar_sfc3_in_port: port@24 { + reg = <0x24>; + + xbar_sfc3_in: endpoint { + remote-endpoint = <&sfc3_cif_in>; + }; + }; + + port@25 { + reg = <0x25>; + + xbar_sfc3_out: endpoint { + remote-endpoint = <&sfc3_cif_out>; + }; + }; + + xbar_sfc4_in_port: port@26 { + reg = <0x26>; + + xbar_sfc4_in: endpoint { + remote-endpoint = <&sfc4_cif_in>; + }; + }; + + port@27 { + reg = <0x27>; + + xbar_sfc4_out: endpoint { + remote-endpoint = <&sfc4_cif_out>; + }; + }; + + xbar_mvc1_in_port: port@28 { + reg = <0x28>; + + xbar_mvc1_in: endpoint { + remote-endpoint = <&mvc1_cif_in>; + }; + }; + + port@29 { + reg = <0x29>; + + xbar_mvc1_out: endpoint { + remote-endpoint = <&mvc1_cif_out>; + }; + }; + + xbar_mvc2_in_port: port@2a { + reg = <0x2a>; + + xbar_mvc2_in: endpoint { + remote-endpoint = <&mvc2_cif_in>; + }; + }; + + port@2b { + reg = <0x2b>; + + xbar_mvc2_out: endpoint { + remote-endpoint = <&mvc2_cif_out>; + }; + }; + + xbar_amx1_in1_port: port@2c { + reg = <0x2c>; + + xbar_amx1_in1: endpoint { + remote-endpoint = <&amx1_in1>; + }; + }; + + xbar_amx1_in2_port: port@2d { + reg = <0x2d>; + + xbar_amx1_in2: endpoint { + remote-endpoint = <&amx1_in2>; + }; + }; + + xbar_amx1_in3_port: port@2e { + reg = <0x2e>; + + xbar_amx1_in3: endpoint { + remote-endpoint = <&amx1_in3>; + }; + }; + + xbar_amx1_in4_port: port@2f { + reg = <0x2f>; + + xbar_amx1_in4: endpoint { + remote-endpoint = <&amx1_in4>; + }; + }; + + port@30 { + reg = <0x30>; + + xbar_amx1_out: endpoint { + remote-endpoint = <&amx1_out>; + }; + }; + + xbar_amx2_in1_port: port@31 { + reg = <0x31>; + + xbar_amx2_in1: endpoint { + remote-endpoint = <&amx2_in1>; + }; + }; + + xbar_amx2_in2_port: port@32 { + reg = <0x32>; + + xbar_amx2_in2: endpoint { + remote-endpoint = <&amx2_in2>; + }; + }; + + xbar_amx2_in3_port: port@33 { + reg = <0x33>; + + xbar_amx2_in3: endpoint { + remote-endpoint = <&amx2_in3>; + }; + }; + + xbar_amx2_in4_port: port@34 { + reg = <0x34>; + + xbar_amx2_in4: endpoint { + remote-endpoint = <&amx2_in4>; + }; + }; + + port@35 { + reg = <0x35>; + + xbar_amx2_out: endpoint { + remote-endpoint = <&amx2_out>; + }; + }; + + xbar_amx3_in1_port: port@36 { + reg = <0x36>; + + xbar_amx3_in1: endpoint { + remote-endpoint = <&amx3_in1>; + }; + }; + + xbar_amx3_in2_port: port@37 { + reg = <0x37>; + + xbar_amx3_in2: endpoint { + remote-endpoint = <&amx3_in2>; + }; + }; + + xbar_amx3_in3_port: port@38 { + reg = <0x38>; + + xbar_amx3_in3: endpoint { + remote-endpoint = <&amx3_in3>; + }; + }; + + xbar_amx3_in4_port: port@39 { + reg = <0x39>; + + xbar_amx3_in4: endpoint { + remote-endpoint = <&amx3_in4>; + }; + }; + + port@3a { + reg = <0x3a>; + + xbar_amx3_out: endpoint { + remote-endpoint = <&amx3_out>; + }; + }; + + xbar_amx4_in1_port: port@3b { + reg = <0x3b>; + + xbar_amx4_in1: endpoint { + remote-endpoint = <&amx4_in1>; + }; + }; + + xbar_amx4_in2_port: port@3c { + reg = <0x3c>; + + xbar_amx4_in2: endpoint { + remote-endpoint = <&amx4_in2>; + }; + }; + + xbar_amx4_in3_port: port@3d { + reg = <0x3d>; + + xbar_amx4_in3: endpoint { + remote-endpoint = <&amx4_in3>; + }; + }; + + xbar_amx4_in4_port: port@3e { + reg = <0x3e>; + + xbar_amx4_in4: endpoint { + remote-endpoint = <&amx4_in4>; + }; + }; + + port@3f { + reg = <0x3f>; + + xbar_amx4_out: endpoint { + remote-endpoint = <&amx4_out>; + }; + }; + + xbar_adx1_in_port: port@40 { + reg = <0x40>; + + xbar_adx1_in: endpoint { + remote-endpoint = <&adx1_in>; + }; + }; + + port@41 { + reg = <0x41>; + + xbar_adx1_out1: endpoint { + remote-endpoint = <&adx1_out1>; + }; + }; + + port@42 { + reg = <0x42>; + + xbar_adx1_out2: endpoint { + remote-endpoint = <&adx1_out2>; + }; + }; + + port@43 { + reg = <0x43>; + + xbar_adx1_out3: endpoint { + remote-endpoint = <&adx1_out3>; + }; + }; + + port@44 { + reg = <0x44>; + + xbar_adx1_out4: endpoint { + remote-endpoint = <&adx1_out4>; + }; + }; + + xbar_adx2_in_port: port@45 { + reg = <0x45>; + + xbar_adx2_in: endpoint { + remote-endpoint = <&adx2_in>; + }; + }; + + port@46 { + reg = <0x46>; + + xbar_adx2_out1: endpoint { + remote-endpoint = <&adx2_out1>; + }; + }; + + port@47 { + reg = <0x47>; + + xbar_adx2_out2: endpoint { + remote-endpoint = <&adx2_out2>; + }; + }; + + port@48 { + reg = <0x48>; + + xbar_adx2_out3: endpoint { + remote-endpoint = <&adx2_out3>; + }; + }; + + port@49 { + reg = <0x49>; + + xbar_adx2_out4: endpoint { + remote-endpoint = <&adx2_out4>; + }; + }; + + xbar_adx3_in_port: port@4a { + reg = <0x4a>; + + xbar_adx3_in: endpoint { + remote-endpoint = <&adx3_in>; + }; + }; + + port@4b { + reg = <0x4b>; + + xbar_adx3_out1: endpoint { + remote-endpoint = <&adx3_out1>; + }; + }; + + port@4c { + reg = <0x4c>; + + xbar_adx3_out2: endpoint { + remote-endpoint = <&adx3_out2>; + }; + }; + + port@4d { + reg = <0x4d>; + + xbar_adx3_out3: endpoint { + remote-endpoint = <&adx3_out3>; + }; + }; + + port@4e { + reg = <0x4e>; + + xbar_adx3_out4: endpoint { + remote-endpoint = <&adx3_out4>; + }; + }; + + xbar_adx4_in_port: port@4f { + reg = <0x4f>; + + xbar_adx4_in: endpoint { + remote-endpoint = <&adx4_in>; + }; + }; + + port@50 { + reg = <0x50>; + + xbar_adx4_out1: endpoint { + remote-endpoint = <&adx4_out1>; + }; + }; + + port@51 { + reg = <0x51>; + + xbar_adx4_out2: endpoint { + remote-endpoint = <&adx4_out2>; + }; + }; + + port@52 { + reg = <0x52>; + + xbar_adx4_out3: endpoint { + remote-endpoint = <&adx4_out3>; + }; + }; + + port@53 { + reg = <0x53>; + + xbar_adx4_out4: endpoint { + remote-endpoint = <&adx4_out4>; + }; + }; + + xbar_mix_in1_port: port@54 { + reg = <0x54>; + + xbar_mix_in1: endpoint { + remote-endpoint = <&mix_in1>; + }; + }; + + xbar_mix_in2_port: port@55 { + reg = <0x55>; + + xbar_mix_in2: endpoint { + remote-endpoint = <&mix_in2>; + }; + }; + + xbar_mix_in3_port: port@56 { + reg = <0x56>; + + xbar_mix_in3: endpoint { + remote-endpoint = <&mix_in3>; + }; + }; + + xbar_mix_in4_port: port@57 { + reg = <0x57>; + + xbar_mix_in4: endpoint { + remote-endpoint = <&mix_in4>; + }; + }; + + xbar_mix_in5_port: port@58 { + reg = <0x58>; + + xbar_mix_in5: endpoint { + remote-endpoint = <&mix_in5>; + }; + }; + + xbar_mix_in6_port: port@59 { + reg = <0x59>; + + xbar_mix_in6: endpoint { + remote-endpoint = <&mix_in6>; + }; + }; + + xbar_mix_in7_port: port@5a { + reg = <0x5a>; + + xbar_mix_in7: endpoint { + remote-endpoint = <&mix_in7>; + }; + }; + + xbar_mix_in8_port: port@5b { + reg = <0x5b>; + + xbar_mix_in8: endpoint { + remote-endpoint = <&mix_in8>; + }; + }; + + xbar_mix_in9_port: port@5c { + reg = <0x5c>; + + xbar_mix_in9: endpoint { + remote-endpoint = <&mix_in9>; + }; + }; + + xbar_mix_in10_port: port@5d { + reg = <0x5d>; + + xbar_mix_in10: endpoint { + remote-endpoint = <&mix_in10>; + }; + }; + + port@5e { + reg = <0x5e>; + + xbar_mix_out1: endpoint { + remote-endpoint = <&mix_out1>; + }; + }; + + port@5f { + reg = <0x5f>; + + xbar_mix_out2: endpoint { + remote-endpoint = <&mix_out2>; + }; + }; + + port@60 { + reg = <0x60>; + + xbar_mix_out3: endpoint { + remote-endpoint = <&mix_out3>; + }; + }; + + port@61 { + reg = <0x61>; + + xbar_mix_out4: endpoint { + remote-endpoint = <&mix_out4>; + }; + }; + + port@62 { + reg = <0x62>; + + xbar_mix_out5: endpoint { + remote-endpoint = <&mix_out5>; + }; + }; + }; + + i2s@2901000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s1_cif: endpoint { + remote-endpoint = <&xbar_i2s1>; + }; + }; + + i2s1_port: port@1 { + reg = <1>; + + i2s1_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; + }; + + i2s@2901100 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s2_cif: endpoint { + remote-endpoint = <&xbar_i2s2>; + }; + }; + + i2s2_port: port@1 { + reg = <1>; + + i2s2_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; + }; + + i2s@2901300 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s4_cif: endpoint { + remote-endpoint = <&xbar_i2s4>; + }; + }; + + i2s4_port: port@1 { + reg = <1>; + + i2s4_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; + }; + + i2s@2901500 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s6_cif: endpoint { + remote-endpoint = <&xbar_i2s6>; + }; + }; + + i2s6_port: port@1 { + reg = <1>; + + i2s6_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; + }; + + sfc@2902000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc1_cif_in: endpoint { + remote-endpoint = <&xbar_sfc1_in>; + }; + }; + + sfc1_out_port: port@1 { + reg = <1>; + + sfc1_cif_out: endpoint { + remote-endpoint = <&xbar_sfc1_out>; + }; + }; + }; + }; + + sfc@2902200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc2_cif_in: endpoint { + remote-endpoint = <&xbar_sfc2_in>; + }; + }; + + sfc2_out_port: port@1 { + reg = <1>; + + sfc2_cif_out: endpoint { + remote-endpoint = <&xbar_sfc2_out>; + }; + }; + }; + }; + + sfc@2902400 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc3_cif_in: endpoint { + remote-endpoint = <&xbar_sfc3_in>; + }; + }; + + sfc3_out_port: port@1 { + reg = <1>; + + sfc3_cif_out: endpoint { + remote-endpoint = <&xbar_sfc3_out>; + }; + }; + }; + }; + + sfc@2902600 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc4_cif_in: endpoint { + remote-endpoint = <&xbar_sfc4_in>; + }; + }; + + sfc4_out_port: port@1 { + reg = <1>; + + sfc4_cif_out: endpoint { + remote-endpoint = <&xbar_sfc4_out>; + }; + }; + }; + }; + + amx@2903000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx1_in1: endpoint { + remote-endpoint = <&xbar_amx1_in1>; + }; + }; + + port@1 { + reg = <1>; + + amx1_in2: endpoint { + remote-endpoint = <&xbar_amx1_in2>; + }; + }; + + port@2 { + reg = <2>; + + amx1_in3: endpoint { + remote-endpoint = <&xbar_amx1_in3>; + }; + }; + + port@3 { + reg = <3>; + + amx1_in4: endpoint { + remote-endpoint = <&xbar_amx1_in4>; + }; + }; + + amx1_out_port: port@4 { + reg = <4>; + + amx1_out: endpoint { + remote-endpoint = <&xbar_amx1_out>; + }; + }; + }; + }; + + amx@2903100 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx2_in1: endpoint { + remote-endpoint = <&xbar_amx2_in1>; + }; + }; + + port@1 { + reg = <1>; + + amx2_in2: endpoint { + remote-endpoint = <&xbar_amx2_in2>; + }; + }; + + port@2 { + reg = <2>; + + amx2_in3: endpoint { + remote-endpoint = <&xbar_amx2_in3>; + }; + }; + + port@3 { + reg = <3>; + + amx2_in4: endpoint { + remote-endpoint = <&xbar_amx2_in4>; + }; + }; + + amx2_out_port: port@4 { + reg = <4>; + + amx2_out: endpoint { + remote-endpoint = <&xbar_amx2_out>; + }; + }; + }; + }; + + amx@2903200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx3_in1: endpoint { + remote-endpoint = <&xbar_amx3_in1>; + }; + }; + + port@1 { + reg = <1>; + + amx3_in2: endpoint { + remote-endpoint = <&xbar_amx3_in2>; + }; + }; + + port@2 { + reg = <2>; + + amx3_in3: endpoint { + remote-endpoint = <&xbar_amx3_in3>; + }; + }; + + port@3 { + reg = <3>; + + amx3_in4: endpoint { + remote-endpoint = <&xbar_amx3_in4>; + }; + }; + + amx3_out_port: port@4 { + reg = <4>; + + amx3_out: endpoint { + remote-endpoint = <&xbar_amx3_out>; + }; + }; + }; + }; + + amx@2903300 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx4_in1: endpoint { + remote-endpoint = <&xbar_amx4_in1>; + }; + }; + + port@1 { + reg = <1>; + + amx4_in2: endpoint { + remote-endpoint = <&xbar_amx4_in2>; + }; + }; + + port@2 { + reg = <2>; + + amx4_in3: endpoint { + remote-endpoint = <&xbar_amx4_in3>; + }; + }; + + port@3 { + reg = <3>; + + amx4_in4: endpoint { + remote-endpoint = <&xbar_amx4_in4>; + }; + }; + + amx4_out_port: port@4 { + reg = <4>; + + amx4_out: endpoint { + remote-endpoint = <&xbar_amx4_out>; + }; + }; + }; + }; + + adx@2903800 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx1_in: endpoint { + remote-endpoint = <&xbar_adx1_in>; + }; + }; + + adx1_out1_port: port@1 { + reg = <1>; + + adx1_out1: endpoint { + remote-endpoint = <&xbar_adx1_out1>; + }; + }; + + adx1_out2_port: port@2 { + reg = <2>; + + adx1_out2: endpoint { + remote-endpoint = <&xbar_adx1_out2>; + }; + }; + + adx1_out3_port: port@3 { + reg = <3>; + + adx1_out3: endpoint { + remote-endpoint = <&xbar_adx1_out3>; + }; + }; + + adx1_out4_port: port@4 { + reg = <4>; + + adx1_out4: endpoint { + remote-endpoint = <&xbar_adx1_out4>; + }; + }; + }; + }; + + adx@2903900 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx2_in: endpoint { + remote-endpoint = <&xbar_adx2_in>; + }; + }; + + adx2_out1_port: port@1 { + reg = <1>; + + adx2_out1: endpoint { + remote-endpoint = <&xbar_adx2_out1>; + }; + }; + + adx2_out2_port: port@2 { + reg = <2>; + + adx2_out2: endpoint { + remote-endpoint = <&xbar_adx2_out2>; + }; + }; + + adx2_out3_port: port@3 { + reg = <3>; + + adx2_out3: endpoint { + remote-endpoint = <&xbar_adx2_out3>; + }; + }; + + adx2_out4_port: port@4 { + reg = <4>; + + adx2_out4: endpoint { + remote-endpoint = <&xbar_adx2_out4>; + }; + }; + }; + }; + + adx@2903a00 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx3_in: endpoint { + remote-endpoint = <&xbar_adx3_in>; + }; + }; + + adx3_out1_port: port@1 { + reg = <1>; + + adx3_out1: endpoint { + remote-endpoint = <&xbar_adx3_out1>; + }; + }; + + adx3_out2_port: port@2 { + reg = <2>; + + adx3_out2: endpoint { + remote-endpoint = <&xbar_adx3_out2>; + }; + }; + + adx3_out3_port: port@3 { + reg = <3>; + + adx3_out3: endpoint { + remote-endpoint = <&xbar_adx3_out3>; + }; + }; + + adx3_out4_port: port@4 { + reg = <4>; + + adx3_out4: endpoint { + remote-endpoint = <&xbar_adx3_out4>; + }; + }; + }; + }; + + adx@2903b00 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx4_in: endpoint { + remote-endpoint = <&xbar_adx4_in>; + }; + }; + + adx4_out1_port: port@1 { + reg = <1>; + + adx4_out1: endpoint { + remote-endpoint = <&xbar_adx4_out1>; + }; + }; + + adx4_out2_port: port@2 { + reg = <2>; + + adx4_out2: endpoint { + remote-endpoint = <&xbar_adx4_out2>; + }; + }; + + adx4_out3_port: port@3 { + reg = <3>; + + adx4_out3: endpoint { + remote-endpoint = <&xbar_adx4_out3>; + }; + }; + + adx4_out4_port: port@4 { + reg = <4>; + + adx4_out4: endpoint { + remote-endpoint = <&xbar_adx4_out4>; + }; + }; + }; + }; + + dmic@2904200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic3_cif: endpoint { + remote-endpoint = <&xbar_dmic3>; + }; + }; + + dmic3_port: port@1 { + reg = <1>; + + dmic3_dap: endpoint { + /* placeholder for external codec */ + }; + }; + }; + }; + + mvc@290a000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mvc1_cif_in: endpoint { + remote-endpoint = <&xbar_mvc1_in>; + }; + }; + + mvc1_out_port: port@1 { + reg = <1>; + + mvc1_cif_out: endpoint { + remote-endpoint = <&xbar_mvc1_out>; + }; + }; + }; + }; + + mvc@290a200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mvc2_cif_in: endpoint { + remote-endpoint = <&xbar_mvc2_in>; + }; + }; + + mvc2_out_port: port@1 { + reg = <1>; + + mvc2_cif_out: endpoint { + remote-endpoint = <&xbar_mvc2_out>; + }; + }; + }; + }; + + amixer@290bb00 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + mix_in1: endpoint { + remote-endpoint = <&xbar_mix_in1>; + }; + }; + + port@1 { + reg = <0x1>; + + mix_in2: endpoint { + remote-endpoint = <&xbar_mix_in2>; + }; + }; + + port@2 { + reg = <0x2>; + + mix_in3: endpoint { + remote-endpoint = <&xbar_mix_in3>; + }; + }; + + port@3 { + reg = <0x3>; + + mix_in4: endpoint { + remote-endpoint = <&xbar_mix_in4>; + }; + }; + + port@4 { + reg = <0x4>; + + mix_in5: endpoint { + remote-endpoint = <&xbar_mix_in5>; + }; + }; + + port@5 { + reg = <0x5>; + + mix_in6: endpoint { + remote-endpoint = <&xbar_mix_in6>; + }; + }; + + port@6 { + reg = <0x6>; + + mix_in7: endpoint { + remote-endpoint = <&xbar_mix_in7>; + }; + }; + + port@7 { + reg = <0x7>; + + mix_in8: endpoint { + remote-endpoint = <&xbar_mix_in8>; + }; + }; + + port@8 { + reg = <0x8>; + + mix_in9: endpoint { + remote-endpoint = <&xbar_mix_in9>; + }; + }; + + port@9 { + reg = <0x9>; + + mix_in10: endpoint { + remote-endpoint = <&xbar_mix_in10>; + }; + }; + + mix_out1_port: port@a { + reg = <0xa>; + + mix_out1: endpoint { + remote-endpoint = <&xbar_mix_out1>; + }; + }; + + mix_out2_port: port@b { + reg = <0xb>; + + mix_out2: endpoint { + remote-endpoint = <&xbar_mix_out2>; + }; + }; + + mix_out3_port: port@c { + reg = <0xc>; + + mix_out3: endpoint { + remote-endpoint = <&xbar_mix_out3>; + }; + }; + + mix_out4_port: port@d { + reg = <0xd>; + + mix_out4: endpoint { + remote-endpoint = <&xbar_mix_out4>; + }; + }; + + mix_out5_port: port@e { + reg = <0xe>; + + mix_out5: endpoint { + remote-endpoint = <&xbar_mix_out5>; + }; + }; + }; + }; + + admaif@290f000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + admaif0_port: port@0 { + reg = <0x0>; + + admaif0: endpoint { + remote-endpoint = <&xbar_admaif0>; + }; + }; + + admaif1_port: port@1 { + reg = <0x1>; + + admaif1: endpoint { + remote-endpoint = <&xbar_admaif1>; + }; + }; + + admaif2_port: port@2 { + reg = <0x2>; + + admaif2: endpoint { + remote-endpoint = <&xbar_admaif2>; + }; + }; + + admaif3_port: port@3 { + reg = <0x3>; + + admaif3: endpoint { + remote-endpoint = <&xbar_admaif3>; + }; + }; + + admaif4_port: port@4 { + reg = <0x4>; + + admaif4: endpoint { + remote-endpoint = <&xbar_admaif4>; + }; + }; + + admaif5_port: port@5 { + reg = <0x5>; + + admaif5: endpoint { + remote-endpoint = <&xbar_admaif5>; + }; + }; + + admaif6_port: port@6 { + reg = <0x6>; + + admaif6: endpoint { + remote-endpoint = <&xbar_admaif6>; + }; + }; + + admaif7_port: port@7 { + reg = <0x7>; + + admaif7: endpoint { + remote-endpoint = <&xbar_admaif7>; + }; + }; + + admaif8_port: port@8 { + reg = <0x8>; + + admaif8: endpoint { + remote-endpoint = <&xbar_admaif8>; + }; + }; + + admaif9_port: port@9 { + reg = <0x9>; + + admaif9: endpoint { + remote-endpoint = <&xbar_admaif9>; + }; + }; + + admaif10_port: port@a { + reg = <0xa>; + + admaif10: endpoint { + remote-endpoint = <&xbar_admaif10>; + }; + }; + + admaif11_port: port@b { + reg = <0xb>; + + admaif11: endpoint { + remote-endpoint = <&xbar_admaif11>; + }; + }; + + admaif12_port: port@c { + reg = <0xc>; + + admaif12: endpoint { + remote-endpoint = <&xbar_admaif12>; + }; + }; + + admaif13_port: port@d { + reg = <0xd>; + + admaif13: endpoint { + remote-endpoint = <&xbar_admaif13>; + }; + }; + + admaif14_port: port@e { + reg = <0xe>; + + admaif14: endpoint { + remote-endpoint = <&xbar_admaif14>; + }; + }; + + admaif15_port: port@f { + reg = <0xf>; + + admaif15: endpoint { + remote-endpoint = <&xbar_admaif15>; + }; + }; + + admaif16_port: port@10 { + reg = <0x10>; + + admaif16: endpoint { + remote-endpoint = <&xbar_admaif16>; + }; + }; + + admaif17_port: port@11 { + reg = <0x11>; + + admaif17: endpoint { + remote-endpoint = <&xbar_admaif17>; + }; + }; + + admaif18_port: port@12 { + reg = <0x12>; + + admaif18: endpoint { + remote-endpoint = <&xbar_admaif18>; + }; + }; + + admaif19_port: port@13 { + reg = <0x13>; + + admaif19: endpoint { + remote-endpoint = <&xbar_admaif19>; + }; + }; + }; + }; + }; + + dma-controller@2930000 { + status = "okay"; + }; + + interrupt-controller@2a40000 { + status = "okay"; + }; + }; + }; + chosen { bootargs = "console=ttyS0,115200n8"; stdout-path = "serial0:115200n8"; @@ -52,4 +1780,59 @@ serial { status = "okay"; }; + + sound { + status = "okay"; + + compatible = "nvidia,tegra186-audio-graph-card"; + + dais = /* ADMAIF (FE) Ports */ + <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>, + <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>, + <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>, + <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>, + <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>, + /* XBAR Ports */ + <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s4_port>, + <&xbar_i2s6_port>, <&xbar_dmic3_port>, + <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>, + <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>, + <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>, + <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>, + <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>, + <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>, + <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>, + <&xbar_amx3_in1_port>, <&xbar_amx3_in2_port>, + <&xbar_amx3_in3_port>, <&xbar_amx3_in4_port>, + <&xbar_amx4_in1_port>, <&xbar_amx4_in2_port>, + <&xbar_amx4_in3_port>, <&xbar_amx4_in4_port>, + <&xbar_adx1_in_port>, <&xbar_adx2_in_port>, + <&xbar_adx3_in_port>, <&xbar_adx4_in_port>, + <&xbar_mix_in1_port>, <&xbar_mix_in2_port>, + <&xbar_mix_in3_port>, <&xbar_mix_in4_port>, + <&xbar_mix_in5_port>, <&xbar_mix_in6_port>, + <&xbar_mix_in7_port>, <&xbar_mix_in8_port>, + <&xbar_mix_in9_port>, <&xbar_mix_in10_port>, + /* HW accelerators */ + <&sfc1_out_port>, <&sfc2_out_port>, + <&sfc3_out_port>, <&sfc4_out_port>, + <&mvc1_out_port>, <&mvc2_out_port>, + <&amx1_out_port>, <&amx2_out_port>, + <&amx3_out_port>, <&amx4_out_port>, + <&adx1_out1_port>, <&adx1_out2_port>, + <&adx1_out3_port>, <&adx1_out4_port>, + <&adx2_out1_port>, <&adx2_out2_port>, + <&adx2_out3_port>, <&adx2_out4_port>, + <&adx3_out1_port>, <&adx3_out2_port>, + <&adx3_out3_port>, <&adx3_out4_port>, + <&adx4_out1_port>, <&adx4_out2_port>, + <&adx4_out3_port>, <&adx4_out4_port>, + <&mix_out1_port>, <&mix_out2_port>, <&mix_out3_port>, + <&mix_out4_port>, <&mix_out5_port>, + /* BE I/O Ports */ + <&i2s1_port>, <&i2s2_port>, <&i2s4_port>, <&i2s6_port>, + <&dmic3_port>; + + label = "NVIDIA Jetson AGX Orin APE"; + }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index d20da6af7172..59ae26c35104 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -1671,6 +1671,20 @@ status = "disabled"; }; + sound { + status = "disabled"; + + clocks = <&bpmp TEGRA234_CLK_PLLA>, + <&bpmp TEGRA234_CLK_PLLA_OUT0>; + clock-names = "pll_a", "plla_out0"; + assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>, + <&bpmp TEGRA234_CLK_PLLA_OUT0>, + <&bpmp TEGRA234_CLK_AUD_MCLK>; + assigned-clock-parents = <0>, + <&bpmp TEGRA234_CLK_PLLA>, + <&bpmp TEGRA234_CLK_PLLA_OUT0>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , -- cgit From b7e70391a5451a53b3791fc006a33714aa52ccfd Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Thu, 3 Feb 2022 18:43:27 +0000 Subject: arm64: tegra: Enable device-tree overlay support Add the '-@' DTC option for the Jetson TX1, Jetson Nano, Jetson TX2, Jetson TX2 NX, Jetson AGX Xavier, Jetson Xavier NX and Jetson AGX Orin platforms. This option populates the '__symbols__' node that contains all the necessary symbols for supporting device-tree overlays on these platforms. These Jetson platforms have various expansion headers, including a 40-pin GPIO header, that allow various add-on modules to be connected and this permits users to create device-tree overlays for these modules. Please note that this change does increase the size of the resulting DTB from between 30-50%. For example, with v5.17-rc1 increase in size is as follows: tegra210-p2371-2180.dtb: 79580 -> 105744 bytes tegra210-p3450-0000.dtb: 57465 -> 81357 bytes tegra186-p2771-0000.dtb: 64763 -> 99553 bytes tegra186-p3509-0000+p3636-0001.dtb: 48078 -> 62464 bytes tegra194-p2972-0000.dtb: 75303 -> 111545 bytes tegra194-p3509-0000+p3668-0000.dtb: 74762 -> 111995 bytes tegra194-p3509-0000+p3668-0001.dtb: 74578 -> 111748 bytes tegra234-p3737-0000+p3701-0000.dtb: 11229 -> 12917 bytes Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/Makefile | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile index ea3f338fd013..bc34c9d8846a 100644 --- a/arch/arm64/boot/dts/nvidia/Makefile +++ b/arch/arm64/boot/dts/nvidia/Makefile @@ -1,4 +1,15 @@ # SPDX-License-Identifier: GPL-2.0 + +# Enables support for device-tree overlays +DTC_FLAGS_tegra210-p2371-2180 := -@ +DTC_FLAGS_tegra210-p3450-0000 := -@ +DTC_FLAGS_tegra186-p2771-0000 := -@ +DTC_FLAGS_tegra186-p3509-0000+p3636-0001 := -@ +DTC_FLAGS_tegra194-p2972-0000 := -@ +DTC_FLAGS_tegra194-p3509-0000+p3668-0000 := -@ +DTC_FLAGS_tegra194-p3509-0000+p3668-0001 := -@ +DTC_FLAGS_tegra234-p3737-0000+p3701-0000 := -@ + dtb-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra132-norrin.dtb dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-0000.dtb dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-2180.dtb -- cgit From 621e12a138f7f3162a2453b853e8ce176ce1f3bc Mon Sep 17 00:00:00 2001 From: Mohan Kumar Date: Wed, 16 Feb 2022 14:52:40 +0530 Subject: arm64: tegra: Add HDA device tree node for Tegra234 Add HDA device tree node for Tegra234 chip and for Jetson AGX Orin platform. Signed-off-by: Mohan Kumar Signed-off-by: Thierry Reding --- .../boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts | 4 ++++ arch/arm64/boot/dts/nvidia/tegra234.dtsi | 17 +++++++++++++++++ 2 files changed, 21 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts index e8c3def36e00..85335c57c820 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts @@ -1742,6 +1742,10 @@ status = "okay"; }; }; + + hda@3510000 { + nvidia,model = "NVIDIA Jetson AGX Orin HDA"; + }; }; chosen { diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 59ae26c35104..aaace605bdaa 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -695,6 +695,23 @@ status = "disabled"; }; + hda@3510000 { + compatible = "nvidia,tegra234-hda", "nvidia,tegra30-hda"; + reg = <0x3510000 0x10000>; + interrupts = ; + clocks = <&bpmp TEGRA234_CLK_AZA_BIT>, + <&bpmp TEGRA234_CLK_AZA_2XBIT>; + clock-names = "hda", "hda2codec_2x"; + resets = <&bpmp TEGRA234_RESET_HDA>, + <&bpmp TEGRA234_RESET_HDACODEC>; + reset-names = "hda", "hda2codec_2x"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>; + interconnect-names = "dma-mem", "write"; + status = "disabled"; + }; + fuse@3810000 { compatible = "nvidia,tegra234-efuse"; reg = <0x03810000 0x10000>; -- cgit From ff578db7b69374fb632ed76e8fd5406f9466c5bd Mon Sep 17 00:00:00 2001 From: kartik Date: Thu, 20 Jan 2022 15:41:51 +0530 Subject: arm64: tegra: Enable UART instance on 40-pin header On P3737 board, UART-A is available on 40-pin header. Enable UART-A for P3737 and change the compatible string to "nvidia,tegra194-hsuart". This allows supporting HW flow control and is the preferred choice for higher baud rates. Signed-off-by: kartik Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts index 85335c57c820..34d6a01ee1c6 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts @@ -14,6 +14,7 @@ aliases { mmc3 = "/bus@0/mmc@3460000"; serial0 = &tcu; + serial1 = &uarta; }; bus@0 { @@ -1743,6 +1744,11 @@ }; }; + serial@3100000 { + compatible = "nvidia,tegra194-hsuart"; + status = "okay"; + }; + hda@3510000 { nvidia,model = "NVIDIA Jetson AGX Orin HDA"; }; -- cgit From c6489c30fcbcfda963c79f003adcdf7a69e33b8a Mon Sep 17 00:00:00 2001 From: Wayne Chang Date: Wed, 22 Dec 2021 15:15:28 +0800 Subject: arm64: tegra: Enable Jetson Xavier NX USB device mode This commit enables USB device mode at J5 micro-B USB port of Jetson Xavier NX. Signed-off-by: Wayne Chang Signed-off-by: Thierry Reding --- .../arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi index 1323fa9b8301..32ce7904f44f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi @@ -1826,6 +1826,10 @@ pads { usb2 { lanes { + usb2-0 { + status = "okay"; + }; + usb2-1 { status = "okay"; }; @@ -1846,6 +1850,20 @@ }; ports { + usb2-0 { + mode = "otg"; + status = "okay"; + usb-role-switch; + connector { + compatible = "gpio-usb-b-connector", + "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + vbus-gpio = <&gpio TEGRA194_MAIN_GPIO(Z, 1) + GPIO_ACTIVE_LOW>; + }; + }; + usb2-1 { mode = "host"; status = "okay"; @@ -1874,6 +1892,13 @@ phy-names = "usb2-1", "usb2-2", "usb3-2"; }; + usb@3550000 { + status = "okay"; + + phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>; + phy-names = "usb2-0"; + }; + spi@3270000 { status = "okay"; -- cgit From 1e49defb863638cde53e48805747271f80f9abec Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 14 Feb 2022 09:19:15 +0100 Subject: arm64: dts: qcom: align Google CROS EC PWM node name with dtschema dtschema expects PWM node name to be a generic "pwm". This also matches Devicetree specification requirements about generic node names. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220214081916.162014-4-krzysztof.kozlowski@canonical.com --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 2 +- arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts | 2 +- arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 2 +- arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 78296ed6fd29..732e1181af48 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -637,7 +637,7 @@ pinctrl-0 = <&ap_ec_int_l>; spi-max-frequency = <3000000>; - cros_ec_pwm: ec-pwm { + cros_ec_pwm: pwm { compatible = "google,cros-ec-pwm"; #pwm-cells = <1>; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts index af46a60b4b98..1779d96c30f6 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts @@ -705,7 +705,7 @@ ap_ec_spi: &spi8 { pinctrl-0 = <&ap_ec_int_l>; spi-max-frequency = <3000000>; - cros_ec_pwm: ec-pwm { + cros_ec_pwm: pwm { compatible = "google,cros-ec-pwm"; #pwm-cells = <1>; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index 7c22f0b062be..dc17f2079695 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -421,7 +421,7 @@ ap_ec_spi: &spi10 { pinctrl-0 = <&ap_ec_int_l>; spi-max-frequency = <3000000>; - cros_ec_pwm: ec-pwm { + cros_ec_pwm: pwm { compatible = "google,cros-ec-pwm"; #pwm-cells = <1>; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi index 0896a6151817..a7c346aa3b02 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi @@ -20,7 +20,7 @@ ap_ec_spi: &spi10 { pinctrl-0 = <&ap_ec_int_l>; spi-max-frequency = <3000000>; - cros_ec_pwm: ec-pwm { + cros_ec_pwm: pwm { compatible = "google,cros-ec-pwm"; #pwm-cells = <1>; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi index 4a6285a25f77..e7e4cc5936aa 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -708,7 +708,7 @@ ap_ts_i2c: &i2c14 { pinctrl-0 = <&ec_ap_int_l>; spi-max-frequency = <3000000>; - cros_ec_pwm: ec-pwm { + cros_ec_pwm: pwm { compatible = "google,cros-ec-pwm"; #pwm-cells = <1>; }; -- cgit From 3016af34ef8d3e3b802693c8d3878906c886621c Mon Sep 17 00:00:00 2001 From: Nikita Travkin Date: Sat, 19 Feb 2022 19:51:40 +0500 Subject: arm64: dts: qcom: msm8916-longcheer-l8150: Add light and proximity sensor L8150 uses LTR559 as a light and proximity sensor. Add it to the devicetree. Reviewed-by: Stephan Gerhold Signed-off-by: Nikita Travkin Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220219145140.84712-1-nikita@trvn.ru --- .../boot/dts/qcom/msm8916-longcheer-l8150.dts | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index 852de624f5af..b3836dde8a54 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -151,6 +151,21 @@ vddio-supply = <&pm8916_l6>; }; + light-sensor@23 { + compatible = "liteon,ltr559"; + reg = <0x23>; + proximity-near-level = <75>; + + interrupt-parent = <&msmgpio>; + interrupts = <115 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&light_int_default>; + + vdd-supply = <&pm8916_l17>; + vio-supply = <&pm8916_l6>; + }; + gyroscope@68 { compatible = "bosch,bmg160"; reg = <0x68>; @@ -392,6 +407,14 @@ bias-disable; }; + light_int_default: light-int-default { + pins = "gpio115"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + magn_int_default: magn-int-default { pins = "gpio113"; function = "gpio"; -- cgit From 9fb08c8019234a0759aab66914f01bc0971e4eed Mon Sep 17 00:00:00 2001 From: Vladimir Lypak Date: Sun, 20 Feb 2022 21:18:59 +0100 Subject: arm64: dts: qcom: Add MSM8953 device tree Add a base DT for MSM8953 SoC. Signed-off-by: Vladimir Lypak Co-developed-by: Luca Weiss Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220220201909.445468-7-luca@z3ntu.xyz --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 1326 +++++++++++++++++++++++++++++++++ 1 file changed, 1326 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8953.dtsi (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi new file mode 100644 index 000000000000..431228faacdd --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -0,0 +1,1326 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* Copyright (c) 2022, The Linux Foundation. All rights reserved. */ + +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + clock-output-names = "xo"; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_0>; + #cooling-cells = <2>; + + l1-icache { + compatible = "cache"; + }; + l1-dcache { + compatible = "cache"; + }; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_0>; + #cooling-cells = <2>; + + l1-icache { + compatible = "cache"; + }; + l1-dcache { + compatible = "cache"; + }; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_0>; + #cooling-cells = <2>; + + l1-icache { + compatible = "cache"; + }; + l1-dcache { + compatible = "cache"; + }; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_0>; + #cooling-cells = <2>; + + l1-icache { + compatible = "cache"; + }; + l1-dcache { + compatible = "cache"; + }; + }; + + CPU4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + + l1-icache { + compatible = "cache"; + }; + l1-dcache { + compatible = "cache"; + }; + }; + + CPU5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x101>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + + l1-icache { + compatible = "cache"; + }; + l1-dcache { + compatible = "cache"; + }; + }; + + CPU6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x102>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + + l1-icache { + compatible = "cache"; + }; + l1-dcache { + compatible = "cache"; + }; + }; + + CPU7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x103>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + + l1-icache { + compatible = "cache"; + }; + l1-dcache { + compatible = "cache"; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + core1 { + cpu = <&CPU5>; + }; + core2 { + cpu = <&CPU6>; + }; + core3 { + cpu = <&CPU7>; + }; + }; + }; + + L2_0: l2-cache_0 { + compatible = "cache"; + cache-level = <2>; + }; + + L2_1: l2-cache_1 { + compatible = "cache"; + cache-level = <2>; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-msm8953"; + clocks = <&gcc GCC_CRYPTO_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_AHB_CLK>; + clock-names = "core", "bus", "iface"; + #reset-cells = <1>; + }; + }; + + memory { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0 0 0 0>; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + zap_shader_region: memory@81800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x81800000 0x0 0x2000>; + no-map; + }; + + memory@85b00000 { + reg = <0x0 0x85b00000 0x0 0x800000>; + no-map; + }; + + smem_mem: memory@86300000 { + compatible = "qcom,smem"; + reg = <0x0 0x86300000 0x0 0x100000>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + hwlocks = <&tcsr_mutex 3>; + no-map; + }; + + memory@86400000 { + reg = <0x0 0x86400000 0x0 0x400000>; + no-map; + }; + + mpss_mem: memory@86c00000 { + reg = <0x0 0x86c00000 0x0 0x6a00000>; + no-map; + }; + + adsp_fw_mem: memory@8d600000 { + reg = <0x0 0x8d600000 0x0 0x1100000>; + no-map; + }; + + wcnss_fw_mem: memory@8e700000 { + reg = <0x0 0x8e700000 0x0 0x700000>; + no-map; + }; + + memory@90000000 { + reg = <0 0x90000000 0 0x1000>; + no-map; + }; + + memory@90001000 { + reg = <0x0 0x90001000 0x0 0x13ff000>; + no-map; + }; + + venus_mem: memory@91400000 { + reg = <0x0 0x91400000 0x0 0x700000>; + no-map; + }; + + mba_mem: memory@92000000 { + reg = <0x0 0x92000000 0x0 0x100000>; + no-map; + }; + + memory@f2d00000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0xf2d00000 0x0 0x180000>; + no-map; + + qcom,client-id = <1>; + }; + }; + + smd { + compatible = "qcom,smd"; + + rpm { + interrupts = ; + qcom,ipc = <&apcs 8 0>; + qcom,smd-edge = <15>; + + rpm_requests: rpm_requests { + compatible = "qcom,rpm-msm8953"; + qcom,smd-channels = "rpm_requests"; + + rpmcc: rpmcc { + compatible = "qcom,rpmcc-msm8953"; + clocks = <&xo_board>; + clock-names = "xo"; + #clock-cells = <1>; + }; + + rpmpd: power-controller { + compatible = "qcom,msm8953-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + clocks = <&xo_board>; + clock-names = "ref"; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmpd_opp_ret_plus: opp2 { + opp-level = ; + }; + + rpmpd_opp_min_svs: opp3 { + opp-level = ; + }; + + rpmpd_opp_low_svs: opp4 { + opp-level = ; + }; + + rpmpd_opp_svs: opp5 { + opp-level = ; + }; + + rpmpd_opp_svs_plus: opp6 { + opp-level = ; + }; + + rpmpd_opp_nom: opp7 { + opp-level = ; + }; + + rpmpd_opp_nom_plus: opp8 { + opp-level = ; + }; + + rpmpd_opp_turbo: opp9 { + opp-level = ; + }; + }; + }; + }; + }; + }; + + smsm { + compatible = "qcom,smsm"; + + #address-cells = <1>; + #size-cells = <0>; + + qcom,ipc-1 = <&apcs 8 13>; + qcom,ipc-3 = <&apcs 8 19>; + + apps_smsm: apps@0 { + reg = <0>; + + #qcom,smem-state-cells = <1>; + }; + }; + + soc: soc@0 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + rpm_msg_ram: sram@60000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x60000 0x8000>; + }; + + hsusb_phy: phy@79000 { + compatible = "qcom,msm8953-qusb2-phy"; + reg = <0x79000 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>, + <&gcc GCC_QUSB_REF_CLK>; + clock-names = "cfg_ahb", "ref"; + + qcom,tcsr-syscon = <&tcsr_phy_clk_scheme_sel>; + + resets = <&gcc GCC_QUSB2_PHY_BCR>; + + status = "disabled"; + }; + + rng@e3000 { + compatible = "qcom,prng"; + reg = <0x000e3000 0x1000>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + }; + + tsens0: thermal-sensor@4a9000 { + compatible = "qcom,msm8953-tsens", "qcom,tsens-v2"; + reg = <0x4a9000 0x1000>, /* TM */ + <0x4a8000 0x1000>; /* SROT */ + #qcom,sensors = <16>; + interrupts = , + ; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + restart@4ab000 { + compatible = "qcom,pshold"; + reg = <0x4ab000 0x4>; + }; + + tlmm: pinctrl@1000000 { + compatible = "qcom,msm8953-pinctrl"; + reg = <0x1000000 0x300000>; + interrupts = ; + gpio-controller; + gpio-ranges = <&tlmm 0 0 155>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + uart_console_active: uart-console-active-pins { + pins = "gpio4", "gpio5"; + function = "blsp_uart2"; + drive-strength = <2>; + bias-disable; + }; + + uart_console_sleep: uart-console-sleep-pins { + pins = "gpio4", "gpio5"; + function = "blsp_uart2"; + drive-strength = <2>; + bias-pull-down; + }; + + sdc1_clk_on: sdc1-clk-on-pins { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + sdc1_clk_off: sdc1-clk-off-pins { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + sdc1_cmd_on: sdc1-cmd-on-pins { + pins = "sdc1_cmd"; + bias-disable; + drive-strength = <10>; + }; + + sdc1_cmd_off: sdc1-cmd-off-pins { + pins = "sdc1_cmd"; + bias-disable; + drive-strength = <2>; + }; + + sdc1_data_on: sdc1-data-on-pins { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sdc1_data_off: sdc1-data-off-pins { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + sdc1_rclk_on: sdc1-rclk-on-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + + sdc1_rclk_off: sdc1-rclk-off-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + + sdc2_clk_on: sdc2-clk-on-pins { + pins = "sdc2_clk"; + drive-strength = <16>; + bias-disable; + }; + + sdc2_clk_off: sdc2-clk-off-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + sdc2_cmd_on: sdc2-cmd-on-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + sdc2_cmd_off: sdc2-cmd-off-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + sdc2_data_on: sdc2-data-on-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sdc2_data_off: sdc2-data-off-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + + sdc2_cd_on: cd-on-pins { + pins = "gpio133"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + sdc2_cd_off: cd-off-pins { + pins = "gpio133"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + gpio_key_default: gpio-key-default-pins { + pins = "gpio85"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + i2c_1_default: i2c-1-default-pins { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + drive-strength = <2>; + bias-disable; + }; + + i2c_1_sleep: i2c-1-sleep-pins { + pins = "gpio2", "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + i2c_2_default: i2c-2-default-pins { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + drive-strength = <2>; + bias-disable; + }; + + i2c_2_sleep: i2c-2-sleep-pins { + pins = "gpio6", "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + i2c_3_default: i2c-3-default-pins { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + drive-strength = <2>; + bias-disable; + }; + + i2c_3_sleep: i2c-3-sleep-pins { + pins = "gpio10", "gpio11"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + i2c_4_default: i2c-4-default-pins { + pins = "gpio14", "gpio15"; + function = "blsp_i2c4"; + drive-strength = <2>; + bias-disable; + }; + + i2c_4_sleep: i2c-4-sleep-pins { + pins = "gpio14", "gpio15"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + i2c_5_default: i2c-5-default-pins { + pins = "gpio18", "gpio19"; + function = "blsp_i2c5"; + drive-strength = <2>; + bias-disable; + }; + + i2c_5_sleep: i2c-5-sleep-pins { + pins = "gpio18", "gpio19"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + i2c_6_default: i2c-6-default-pins { + pins = "gpio22", "gpio23"; + function = "blsp_i2c6"; + drive-strength = <2>; + bias-disable; + }; + + i2c_6_sleep: i2c-6-sleep-pins { + pins = "gpio22", "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + i2c_7_default: i2c-7-default-pins { + pins = "gpio135", "gpio136"; + function = "blsp_i2c7"; + drive-strength = <2>; + bias-disable; + }; + + i2c_7_sleep: i2c-7-sleep-pins { + pins = "gpio135", "gpio136"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + i2c_8_default: i2c-8-default-pins { + pins = "gpio98", "gpio99"; + function = "blsp_i2c8"; + drive-strength = <2>; + bias-disable; + }; + + i2c_8_sleep: i2c-8-sleep-pins { + pins = "gpio98", "gpio99"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + + gcc: clock-controller@1800000 { + compatible = "qcom,gcc-msm8953"; + reg = <0x1800000 0x80000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clocks = <&xo_board>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>; + clock-names = "xo", + "sleep", + "dsi0pll", + "dsi0pllbyte", + "dsi1pll", + "dsi1pllbyte"; + }; + + tcsr_mutex: hwlock@1905000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x1905000 0x20000>; + #hwlock-cells = <1>; + }; + + tcsr: syscon@1937000 { + compatible = "qcom,tcsr-msm8953", "syscon"; + reg = <0x1937000 0x30000>; + }; + + tcsr_phy_clk_scheme_sel: syscon@193f044 { + compatible = "syscon"; + reg = <0x193f044 0x4>; + }; + + spmi_bus: spmi@200f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x200f000 0x1000>, + <0x2400000 0x800000>, + <0x2c00000 0x800000>, + <0x3800000 0x200000>, + <0x200a000 0x2100>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + interrupt-controller; + + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + }; + + usb3: usb@70f8800 { + compatible = "qcom,msm8953-dwc3", "qcom,dwc3"; + reg = <0x70f8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts = , + ; + interrupt-names = "hs_phy_irq", "ss_phy_irq"; + + clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB30_MASTER_CLK>, + <&gcc GCC_PCNOC_USB3_AXI_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SLEEP_CLK>; + clock-names = "cfg_noc", "core", "iface", + "mock_utmi", "sleep"; + + assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MASTER_CLK>; + assigned-clock-rates = <19200000>, <133330000>; + + power-domains = <&gcc USB30_GDSC>; + + qcom,select-utmi-as-pipe-clk; + + status = "disabled"; + + usb3_dwc3: usb@7000000 { + compatible = "snps,dwc3"; + reg = <0x07000000 0xcc00>; + interrupts = ; + phys = <&hsusb_phy>; + phy-names = "usb2-phy"; + + snps,usb2-gadget-lpm-disable; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,hird-threshold = /bits/ 8 <0x00>; + + maximum-speed = "high-speed"; + phy_mode = "utmi"; + }; + }; + + sdhc_1: sdhci@7824900 { + compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; + + reg = <0x7824900 0x500>, <0x7824000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board>; + clock-names = "iface", "core", "xo"; + + power-domains = <&rpmpd MSM8953_VDDCX>; + operating-points-v2 = <&sdhc1_opp_table>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; + + mmc-hs400-1_8v; + mmc-hs200-1_8v; + mmc-ddr-1_8v; + bus-width = <8>; + non-removable; + + status = "disabled"; + + sdhc1_opp_table: opp-table-sdhc1 { + compatible = "operating-points-v2"; + + opp-25000000 { + opp-hz = /bits/ 64 <25000000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-192000000 { + opp-hz = /bits/ 64 <192000000>; + required-opps = <&rpmpd_opp_nom>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + }; + + sdhc_2: sdhci@7864900 { + compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; + + reg = <0x7864900 0x500>, <0x7864000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&xo_board>; + clock-names = "iface", "core", "xo"; + + power-domains = <&rpmpd MSM8953_VDDCX>; + operating-points-v2 = <&sdhc2_opp_table>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + + bus-width = <4>; + + status = "disabled"; + + sdhc2_opp_table: opp-table-sdhc2 { + compatible = "operating-points-v2"; + + opp-25000000 { + opp-hz = /bits/ 64 <25000000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-177770000 { + opp-hz = /bits/ 64 <177770000>; + required-opps = <&rpmpd_opp_nom>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + }; + + uart_0: serial@78af000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x78af000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + + status = "disabled"; + }; + + i2c_1: i2c@78b5000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x78b5000 0x600>; + interrupts = ; + clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c_1_default>; + pinctrl-1 = <&i2c_1_sleep>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c_2: i2c@78b6000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x78b6000 0x600>; + interrupts = ; + clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c_2_default>; + pinctrl-1 = <&i2c_2_sleep>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c_3: i2c@78b7000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x78b7000 0x600>; + interrupts = ; + clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c_3_default>; + pinctrl-1 = <&i2c_3_sleep>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c_4: i2c@78b8000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x78b8000 0x600>; + interrupts = ; + clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c_4_default>; + pinctrl-1 = <&i2c_4_sleep>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c_5: i2c@7af5000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x7af5000 0x600>; + interrupts = ; + clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP2_AHB_CLK>, + <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c_5_default>; + pinctrl-1 = <&i2c_5_sleep>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c_6: i2c@7af6000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x7af6000 0x600>; + interrupts = ; + clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP2_AHB_CLK>, + <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c_6_default>; + pinctrl-1 = <&i2c_6_sleep>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c_7: i2c@7af7000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x7af7000 0x600>; + interrupts = ; + clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP2_AHB_CLK>, + <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c_7_default>; + pinctrl-1 = <&i2c_7_sleep>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c_8: i2c@7af8000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x7af8000 0x600>; + interrupts = ; + clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP2_AHB_CLK>, + <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c_8_default>; + pinctrl-1 = <&i2c_8_sleep>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; + }; + + apcs: mailbox@b011000 { + compatible = "qcom,msm8953-apcs-kpss-global", "syscon"; + reg = <0xb011000 0x1000>; + #mbox-cells = <1>; + }; + + timer@b120000 { + compatible = "arm,armv7-timer-mem"; + reg = <0xb120000 0x1000>; + #address-cells = <0x01>; + #size-cells = <0x01>; + ranges; + + frame@b121000 { + frame-number = <0>; + interrupts = , + ; + reg = <0xb121000 0x1000>, + <0xb122000 0x1000>; + }; + + frame@b123000 { + frame-number = <1>; + interrupts = ; + reg = <0xb123000 0x1000>; + status = "disabled"; + }; + + frame@b124000 { + frame-number = <2>; + interrupts = ; + reg = <0xb124000 0x1000>; + status = "disabled"; + }; + + frame@b125000 { + frame-number = <3>; + interrupts = ; + reg = <0xb125000 0x1000>; + status = "disabled"; + }; + + frame@b126000 { + frame-number = <4>; + interrupts = ; + reg = <0xb126000 0x1000>; + status = "disabled"; + }; + + frame@b127000 { + frame-number = <5>; + interrupts = ; + reg = <0xb127000 0x1000>; + status = "disabled"; + }; + + frame@b128000 { + frame-number = <6>; + interrupts = ; + reg = <0xb128000 0x1000>; + status = "disabled"; + }; + }; + }; + + thermal-zones { + cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens0 9>; + trips { + cpu0_alert: trip-point0 { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu0_crit: crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu0_alert>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + cpu1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens0 10>; + trips { + cpu1_alert: trip-point0 { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu1_crit: crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu1_alert>; + cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + cpu2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens0 11>; + trips { + cpu2_alert: trip-point0 { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu2_crit: crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu2_alert>; + cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + cpu3-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens0 12>; + trips { + cpu3_alert: trip-point0 { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu3_crit: crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu3_alert>; + cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + cpu4-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens0 4>; + trips { + cpu4_alert: trip-point0 { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu4_crit: crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu4_alert>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + cpu5-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens0 5>; + trips { + cpu5_alert: trip-point0 { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu5_crit: crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu5_alert>; + cooling-device = <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + cpu6-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens0 6>; + trips { + cpu6_alert: trip-point0 { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu6_crit: crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu6_alert>; + cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + cpu7-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens0 7>; + trips { + cpu7_alert: trip-point0 { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu7_crit: crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu7_alert>; + cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; -- cgit From 06ea71e42975cdd43cc1e2dacd3e56c8693ac733 Mon Sep 17 00:00:00 2001 From: Vladimir Lypak Date: Sun, 20 Feb 2022 21:19:00 +0100 Subject: arm64: dts: qcom: Add PM8953 PMIC Add a base DT for PM8953 PMIC, commonly used with MSM8953. Signed-off-by: Vladimir Lypak Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Reviewed-by: Rayyan Ansari Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220220201909.445468-8-luca@z3ntu.xyz --- arch/arm64/boot/dts/qcom/pm8953.dtsi | 90 ++++++++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pm8953.dtsi (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/pm8953.dtsi b/arch/arm64/boot/dts/qcom/pm8953.dtsi new file mode 100644 index 000000000000..741c538a9cee --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8953.dtsi @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* Copyright (c) 2022, The Linux Foundation. All rights reserved. */ + +#include +#include +#include +#include + +&spmi_bus { + pmic@0 { + compatible = "qcom,pm8953", "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8953_pon: pon@800 { + compatible = "qcom,pm8916-pon"; + reg = <0x800>; + mode-bootloader = <0x2>; + mode-recovery = <0x1>; + + pwrkey { + compatible = "qcom,pm8941-pwrkey"; + interrupts = <0x00 0x08 0 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = ; + }; + + pm8953_resin: resin { + compatible = "qcom,pm8941-resin"; + interrupts = <0x00 0x08 1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + status = "disabled"; + }; + }; + + temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pm8953_vadc VADC_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pm8953_vadc: vadc@3100 { + compatible = "qcom,spmi-vadc"; + reg = <0x3100>; + interrupts = <0x00 0x31 0x00 0x01>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + adc-chan@8 { + reg = ; + }; + adc-chan@9 { + reg = ; + }; + adc-chan@a { + reg = ; + }; + adc-chan@c { + reg = ; + }; + adc-chan@e { + reg = ; + }; + adc-chan@f { + reg = ; + }; + }; + + rtc@6000 { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>, <0x6100>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; + }; + }; + + pmic@1 { + compatible = "qcom,pm8953", "qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; -- cgit From 24af02271ca7cf095186963002d1d98349d9e5e5 Mon Sep 17 00:00:00 2001 From: Vladimir Lypak Date: Sun, 20 Feb 2022 21:19:01 +0100 Subject: arm64: dts: qcom: Add SDM632 device tree Snapdragon 632 is based on msm8953 with some minor differences, mostly in the CPUs. SDM632 is using Kryo 250 instead of ARM Cortex A53 and has some differences in the thermal zones, mainly there being only one thermal zones for the first 4 cores (efficiency cores) but keeps one thermal zone per core for the remaining 4 cores (performance cores). Co-developed-by: Gabriel David Signed-off-by: Gabriel David Signed-off-by: Vladimir Lypak Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220220201909.445468-9-luca@z3ntu.xyz --- arch/arm64/boot/dts/qcom/sdm632.dtsi | 81 ++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdm632.dtsi (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sdm632.dtsi b/arch/arm64/boot/dts/qcom/sdm632.dtsi new file mode 100644 index 000000000000..645b9f6a801f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm632.dtsi @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* Copyright (c) 2022, The Linux Foundation. All rights reserved. */ + +#include "msm8953.dtsi" + +/ { + thermal-zones { + /delete-node/cpu1-thermal; + /delete-node/cpu2-thermal; + /delete-node/cpu3-thermal; + + cpu0-thermal { + thermal-sensors = <&tsens0 13>; + + cooling-maps { + map0 { + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu4-thermal { + thermal-sensors = <&tsens0 5>; + }; + + cpu5-thermal { + thermal-sensors = <&tsens0 6>; + }; + + cpu6-thermal { + thermal-sensors = <&tsens0 7>; + }; + + cpu7-thermal { + thermal-sensors = <&tsens0 8>; + }; + }; +}; + +/* + * SDM632 uses Kryo 250 instead of Cortex A53 + * CPU0-3 are efficiency cores, CPU4-7 are performance cores + */ +&CPU0 { + compatible = "qcom,kryo250"; +}; + +&CPU1 { + compatible = "qcom,kryo250"; +}; + +&CPU2 { + compatible = "qcom,kryo250"; +}; + +&CPU3 { + compatible = "qcom,kryo250"; +}; + +&CPU4 { + compatible = "qcom,kryo250"; + capacity-dmips-mhz = <1980>; +}; + +&CPU5 { + compatible = "qcom,kryo250"; + capacity-dmips-mhz = <1980>; +}; + +&CPU6 { + compatible = "qcom,kryo250"; + capacity-dmips-mhz = <1980>; +}; + +&CPU7 { + compatible = "qcom,kryo250"; + capacity-dmips-mhz = <1980>; +}; -- cgit From 308b26cddb04afc7776de1cbbe07172eeccc7c98 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Sun, 20 Feb 2022 21:19:03 +0100 Subject: arm64: dts: qcom: sdm632: Add device tree for Fairphone 3 Add device tree for the Fairphone 3 smartphone which is based on Snapdragon 632 (sdm632). Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220220201909.445468-11-luca@z3ntu.xyz --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts | 183 ++++++++++++++++++++++ 2 files changed, 184 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 06e7b87a4ad0..f9e6343acd03 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -92,6 +92,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-ganges-kirin.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-discovery.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-pioneer.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-voyager.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm632-fairphone-fp3.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm636-sony-xperia-ganges-mermaid.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-lavender.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb diff --git a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts new file mode 100644 index 000000000000..8b815b2a60a7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts @@ -0,0 +1,183 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Luca Weiss + */ +/dts-v1/; + +#include "sdm632.dtsi" +#include "pm8953.dtsi" + +/ { + model = "Fairphone 3"; + compatible = "fairphone,fp3", "qcom,sdm632"; + chassis-type = "handset"; + qcom,msm-id = <349 0>; + qcom,board-id = <8 0x10000>; + + aliases { + mmc0 = &sdhc_1; + mmc1 = &sdhc_2; + serial0 = &uart_0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + volume-up { + label = "volume_up"; + linux,code = ; + gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-always-on; + regulator-boot-on; + }; +}; + +&hsusb_phy { + status = "okay"; + vdd-supply = <&pm8953_l3>; + vdda-pll-supply = <&pm8953_l7>; + vdda-phy-dpdm-supply = <&pm8953_l13>; +}; + +&pm8953_resin { + status = "okay"; + linux,code = ; +}; + +&sdhc_1 { + status = "okay"; + vmmc-supply = <&pm8953_l8>; + vqmmc-supply = <&pm8953_l5>; +}; + +&sdhc_2 { + status = "okay"; + vmmc-supply = <&pm8953_l11>; + vqmmc-supply = <&pm8953_l12>; + + cd-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; +}; + +&rpm_requests { + pm8953-regulators { + compatible = "qcom,rpm-pm8953-regulators"; + + vdd_l1-supply = <&pm8953_s3>; + vdd_l2_l3-supply = <&pm8953_s3>; + vdd_l4_l5_l6_l7_l16_l19-supply = <&pm8953_s4>; + vdd_l8_l11_l12_l13_l14_l15-supply = <&vph_pwr>; + vdd_l9_l10_l17_l18_l22-supply = <&vph_pwr>; + + pm8953_s3: s3 { + regulator-min-microvolt = <984000>; + regulator-max-microvolt = <1240000>; + }; + pm8953_s4: s4 { + regulator-min-microvolt = <1036000>; + regulator-max-microvolt = <2040000>; + }; + pm8953_s5: s5 { + regulator-min-microvolt = <1036000>; + regulator-max-microvolt = <2040000>; + }; + + pm8953_l1: l1 { + regulator-min-microvolt = <975000>; + regulator-max-microvolt = <1050000>; + }; + pm8953_l2: l2 { + regulator-min-microvolt = <975000>; + regulator-max-microvolt = <1175000>; + }; + pm8953_l3: l3 { + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <925000>; + }; + pm8953_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + pm8953_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + pm8953_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + }; + pm8953_l8: l8 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + }; + pm8953_l9: l9 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + pm8953_l10: l10 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + }; + pm8953_l11: l11 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + pm8953_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + pm8953_l13: l13 { + regulator-min-microvolt = <3125000>; + regulator-max-microvolt = <3125000>; + }; + pm8953_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + pm8953_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + pm8953_l19: l19 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + }; + pm8953_l22: l22 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + pm8953_l23: l23 { + regulator-min-microvolt = <975000>; + regulator-max-microvolt = <1225000>; + }; + }; +}; + +&tlmm { + /* + * 0-3: unused but protected by TZ + * 135-138: fingerprint reader (SPI) + */ + gpio-reserved-ranges = <0 4>, <135 4>; +}; + +&uart_0 { + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "peripheral"; +}; -- cgit From 3cc8cd2d25954ed5794df2d190b81c7325c584e3 Mon Sep 17 00:00:00 2001 From: Yifeng Zhao Date: Tue, 8 Feb 2022 17:13:26 +0800 Subject: arm64: dts: rockchip: add naneng combo phy nodes for rk3568 Add the core dt-node for the rk3568's naneng combo phys. Signed-off-by: Yifeng Zhao Signed-off-by: Johan Jonker Tested-by: Frank Wunderlich Link: https://lore.kernel.org/r/20220208091326.12495-5-yifeng.zhao@rock-chips.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568.dtsi | 21 ++++++++++++++ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 47 ++++++++++++++++++++++++++++++++ 2 files changed, 68 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index 2fd313a295f8..91a0b798b857 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -8,6 +8,11 @@ / { compatible = "rockchip,rk3568"; + pipe_phy_grf0: syscon@fdc70000 { + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc70000 0x0 0x1000>; + }; + qos_pcie3x1: qos@fe190080 { compatible = "rockchip,rk3568-qos", "syscon"; reg = <0x0 0xfe190080 0x0 0x20>; @@ -71,6 +76,22 @@ queue0 {}; }; }; + + combphy0: phy@fe820000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe820000 0x0 0x100>; + clocks = <&pmucru CLK_PCIEPHY0_REF>, + <&cru PCLK_PIPEPHY0>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PIPEPHY0>; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf0>; + #phy-cells = <1>; + status = "disabled"; + }; }; &cpu0_opp_table { diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index e20ee3968b5a..5c6cae76c180 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -296,11 +296,26 @@ }; }; + pipegrf: syscon@fdc50000 { + compatible = "rockchip,rk3568-pipe-grf", "syscon"; + reg = <0x0 0xfdc50000 0x0 0x1000>; + }; + grf: syscon@fdc60000 { compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; reg = <0x0 0xfdc60000 0x0 0x10000>; }; + pipe_phy_grf1: syscon@fdc80000 { + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc80000 0x0 0x1000>; + }; + + pipe_phy_grf2: syscon@fdc90000 { + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc90000 0x0 0x1000>; + }; + usb2phy0_grf: syscon@fdca0000 { compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; reg = <0x0 0xfdca0000 0x0 0x8000>; @@ -1307,6 +1322,38 @@ status = "disabled"; }; + combphy1: phy@fe830000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe830000 0x0 0x100>; + clocks = <&pmucru CLK_PCIEPHY1_REF>, + <&cru PCLK_PIPEPHY1>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PIPEPHY1>; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf1>; + #phy-cells = <1>; + status = "disabled"; + }; + + combphy2: phy@fe840000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe840000 0x0 0x100>; + clocks = <&pmucru CLK_PCIEPHY2_REF>, + <&cru PCLK_PIPEPHY2>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PIPEPHY2>; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf2>; + #phy-cells = <1>; + status = "disabled"; + }; + usb2phy0: usb2phy@fe8a0000 { compatible = "rockchip,rk3568-usb2phy"; reg = <0x0 0xfe8a0000 0x0 0x10000>; -- cgit From cfcccc9126a7aece5596bb4cba45ba566fd00f0e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 21 Feb 2022 16:48:53 +0100 Subject: arm64: dts: renesas: r8a779f0: Add pinctrl device node Add a device node for the Pin Function Controller on the Renesas R-Car S4-8 (R8A779F0) SoC. Note that the register block does not include registers for banks 4-7, as they can only be accessed from the Control Domain. Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/cf4d261ba1253879e117f1598b9f47798cbda635.1645458249.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index 0ac8c345558e..f4e549867371 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -69,6 +69,12 @@ status = "disabled"; }; + pfc: pinctrl@e6050000 { + compatible = "renesas,pfc-r8a779f0"; + reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, + <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a779f0-cpg-mssr"; reg = <0 0xe6150000 0 0x4000>; -- cgit From 1ef36224ad6283cb1430cd5029470f9c53f6a915 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 21 Feb 2022 16:48:54 +0100 Subject: arm64: dts: renesas: spider: Complete SCIF3 description Complete the description of the serial console by adding RTS/CTS, the external clock crystal, and pin control. Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/8e5701ca2a5f5925918217ab79e8489535339e7b.1645458249.git.geert+renesas@glider.be --- .../boot/dts/renesas/r8a779f0-spider-cpu.dtsi | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi index 3a90932fe85c..6e07c54148e7 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi @@ -31,11 +31,34 @@ clock-frequency = <32768>; }; +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + scif3_pins: scif3 { + groups = "scif3_data", "scif3_ctrl"; + function = "scif3"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk"; + function = "scif_clk"; + }; +}; + &rwdt { timeout-sec = <60>; status = "okay"; }; &scif3 { + pinctrl-0 = <&scif3_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; status = "okay"; }; + +&scif_clk { + clock-frequency = <24000000>; +}; -- cgit From f0a481209d6fa70854673173bf5f8a1cb24bd7f2 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 16:07:46 +0100 Subject: arm64: tegra: Drop arm,armv8-pmuv3 compatible string The arm,armv8-pmuv3 compatible string is meant to be used only for software models and not silicon chips. Drop them and use silicon- specific compatible strings instead. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 4 ++-- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 899d7b1cb780..e9b40f5d79ec 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1980,14 +1980,14 @@ }; pmu_denver { - compatible = "nvidia,denver-pmu", "arm,armv8-pmuv3"; + compatible = "nvidia,denver-pmu"; interrupts = , ; interrupt-affinity = <&denver_0 &denver_1>; }; pmu_a57 { - compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3"; + compatible = "arm,cortex-a57-pmu"; interrupts = , , , diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index db26a5741e48..c28bf4d8eb03 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -2886,7 +2886,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "nvidia,carmel-pmu"; interrupts = , , , -- cgit From d1986fbd56ed5fb4dad3701543c81e19cc433923 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Mon, 7 Feb 2022 17:40:24 +0800 Subject: arm64: dts: mt8192: Add watchdog node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add watchdog device node to MT8192 SoC. Signed-off-by: Allen-KH Cheng Tested-by: AngeloGioacchino Del Regno Reviewed-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20220207094024.22674-1-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index cc3953df0153..c1d4030e7e4b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -301,6 +301,12 @@ #interrupt-cells = <2>; }; + watchdog: watchdog@10007000 { + compatible = "mediatek,mt8192-wdt"; + reg = <0 0x10007000 0 0x100>; + #reset-cells = <1>; + }; + apmixedsys: syscon@1000c000 { compatible = "mediatek,mt8192-apmixedsys", "syscon"; reg = <0 0x1000c000 0 0x1000>; -- cgit From f1d17330a5bedc16c6cd87f0e009dd74d96ab612 Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Fri, 25 Feb 2022 17:32:38 +0530 Subject: arm64: dts: ti: Introduce base support for AM62x SoC This add bare minimum DT for AM62 describing ARM compute clusters, Main, MCU and Wakeup domain and interconnects, UARTs and I2Cs to enable booting using ramdisk. Hierarchy of dts files: am62.dtsi: base SoC skeleton which is common across am62xx family of SoCs, includes am62-main.dtsi, am62-mcu.dtsi and am62-wakeup.dtsi representing 3 domains and peripherals in each of these domain am625.dtsi: describes CPU cluster (Quad A53s). Since, am625 is a current superset device with all peripherals, am625.dtsi includes am62.dtsi completing SoC definition. Individual EVMs using this SoC will just need to include am625.dtsi thus making things easier for Board and SOM Vendors. Future derivative SoCs will have their own am62{1-9}{1-9}.dtsi overriding cluster / peripheral definitions with their own compatibles. More details about the SoCs can be found in the Technical Reference Manual: https://www.ti.com/lit/pdf/spruiv7 Co-developed-by: Suman Anna Signed-off-by: Suman Anna Co-developed-by: Nishanth Menon Signed-off-by: Nishanth Menon Signed-off-by: Vignesh Raghavendra Reviewed-by: Bryan Brattlof Link: https://lore.kernel.org/r/20220225120239.1303821-5-vigneshr@ti.com --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 267 +++++++++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi | 36 ++++ arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 41 +++++ arch/arm64/boot/dts/ti/k3-am62.dtsi | 105 ++++++++++++ arch/arm64/boot/dts/ti/k3-am625.dtsi | 103 +++++++++++ 5 files changed, 552 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62-main.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am62.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am625.dtsi (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi new file mode 100644 index 000000000000..c68472c692f4 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -0,0 +1,267 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM625 SoC Family Main Domain peripherals + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_main { + gic500: interrupt-controller@1800000 { + compatible = "arm,gic-v3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ + <0x00 0x01880000 0x00 0xc0000>, /* GICR */ + <0x00 0x01880000 0x00 0xc0000>, /* GICR */ + <0x01 0x00000000 0x00 0x2000>, /* GICC */ + <0x01 0x00010000 0x00 0x1000>, /* GICH */ + <0x01 0x00020000 0x00 0x2000>; /* GICV */ + /* + * vcpumntirq: + * virtual CPU interface maintenance interrupt + */ + interrupts = ; + + gic_its: msi-controller@1820000 { + compatible = "arm,gic-v3-its"; + reg = <0x00 0x01820000 0x00 0x10000>; + socionext,synquacer-pre-its = <0x1000000 0x400000>; + msi-controller; + #msi-cells = <1>; + }; + }; + + main_conf: syscon@100000 { + compatible = "syscon", "simple-mfd"; + reg = <0x00 0x00100000 0x00 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x00100000 0x20000>; + }; + + dmss: bus@48000000 { + compatible = "simple-mfd"; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges; + ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; + + ti,sci-dev-id = <25>; + + secure_proxy_main: mailbox@4d000000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x4d000000 0x00 0x80000>, + <0x00 0x4a600000 0x00 0x80000>, + <0x00 0x4a400000 0x00 0x80000>; + interrupt-names = "rx_012"; + interrupts = ; + }; + }; + + dmsc: system-controller@44043000 { + compatible = "ti,k2g-sci"; + ti,host-id = <12>; + mbox-names = "rx", "tx"; + mboxes= <&secure_proxy_main 12>, + <&secure_proxy_main 13>; + reg-names = "debug_messages"; + reg = <0x00 0x44043000 0x00 0xfe0>; + + k3_pds: power-controller { + compatible = "ti,sci-pm-domain"; + #power-domain-cells = <2>; + }; + + k3_clks: clock-controller { + compatible = "ti,k2g-sci-clk"; + #clock-cells = <2>; + }; + + k3_reset: reset-controller { + compatible = "ti,sci-reset"; + #reset-cells = <2>; + }; + }; + + main_pmx0: pinctrl@f4000 { + compatible = "pinctrl-single"; + reg = <0x00 0xf4000 0x00 0x2ac>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + main_uart0: serial@2800000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02800000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 146 0>; + clock-names = "fclk"; + }; + + main_uart1: serial@2810000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02810000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 152 0>; + clock-names = "fclk"; + }; + + main_uart2: serial@2820000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02820000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 153 0>; + clock-names = "fclk"; + }; + + main_uart3: serial@2830000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02830000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 154 0>; + clock-names = "fclk"; + }; + + main_uart4: serial@2840000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02840000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 155 0>; + clock-names = "fclk"; + }; + + main_uart5: serial@2850000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02850000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 156 0>; + clock-names = "fclk"; + }; + + main_uart6: serial@2860000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02860000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 158 0>; + clock-names = "fclk"; + }; + + main_i2c0: i2c@20000000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20000000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 102 2>; + clock-names = "fck"; + }; + + main_i2c1: i2c@20010000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20010000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 103 2>; + clock-names = "fck"; + }; + + main_i2c2: i2c@20020000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20020000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 104 2>; + clock-names = "fck"; + }; + + main_i2c3: i2c@20030000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20030000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 105 2>; + clock-names = "fck"; + }; + + main_gpio_intr: interrupt-controller@a00000 { + compatible = "ti,sci-intr"; + reg = <0x00 0x00a00000 0x00 0x800>; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <1>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <3>; + ti,interrupt-ranges = <0 32 16>; + }; + + main_gpio0: gpio@600000 { + compatible = "ti,am64-gpio", "ti,keystone-gpio"; + reg = <0x0 0x00600000 0x0 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <190>, <191>, <192>, + <193>, <194>, <195>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <87>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 77 0>; + clock-names = "gpio"; + }; + + main_gpio1: gpio@601000 { + compatible = "ti,am64-gpio", "ti,keystone-gpio"; + reg = <0x0 0x00601000 0x0 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <180>, <181>, <182>, + <183>, <184>, <185>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <88>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 78 0>; + clock-names = "gpio"; + }; + + hwspinlock: spinlock@2a000000 { + compatible = "ti,am64-hwspinlock"; + reg = <0x00 0x2a000000 0x00 0x1000>; + #hwlock-cells = <1>; + }; + + mailbox0_cluster0: mailbox@29000000 { + compatible = "ti,am64-mailbox"; + reg = <0x00 0x29000000 0x00 0x200>; + interrupts = , + ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi new file mode 100644 index 000000000000..9d210d55fc71 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM625 SoC Family MCU Domain peripherals + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_mcu { + mcu_pmx0: pinctrl@4084000 { + compatible = "pinctrl-single"; + reg = <0x00 0x04084000 0x00 0x88>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + mcu_uart0: serial@4a00000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x04a00000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 149 0>; + clock-names = "fclk"; + }; + + mcu_i2c0: i2c@4900000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x04900000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 106 2>; + clock-names = "fck"; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi new file mode 100644 index 000000000000..4090134676cf --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM625 SoC Family Wakeup Domain peripherals + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_wakeup { + wkup_conf: syscon@43000000 { + compatible = "syscon", "simple-mfd"; + reg = <0x00 0x43000000 0x00 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x43000000 0x20000>; + + chipid: chipid@14 { + compatible = "ti,am654-chipid"; + reg = <0x14 0x4>; + }; + }; + + wkup_uart0: serial@2b300000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x2b300000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 114 0>; + clock-names = "fclk"; + }; + + wkup_i2c0: i2c@2b200000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x02b200000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 107 4>; + clock-names = "fck"; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62.dtsi b/arch/arm64/boot/dts/ti/k3-am62.dtsi new file mode 100644 index 000000000000..bc2997b18556 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62.dtsi @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM62 SoC Family + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include +#include +#include +#include + +/ { + model = "Texas Instruments K3 AM625 SoC"; + compatible = "ti,am625"; + interrupt-parent = <&gic500>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + a53_timer0: timer-cl0-cpu0 { + compatible = "arm,armv8-timer"; + interrupts = , /* cntpsirq */ + , /* cntpnsirq */ + , /* cntvirq */ + ; /* cnthpirq */ + }; + + pmu: pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + cbass_main: bus@f0000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */ + <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ + <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ + <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */ + <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */ + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ + <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */ + <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */ + <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */ + <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ + <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ + <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */ + <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ + <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */ + <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */ + <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ + <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ + <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ + <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */ + <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ + <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */ + <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ + + /* MCU Domain Range */ + <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, + + /* Wakeup Domain Range */ + <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; + + cbass_mcu: bus@4000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */ + }; + + cbass_wakeup: bus@2b000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */ + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; + }; + }; +}; + +/* Now include the peripherals for each bus segments */ +#include "k3-am62-main.dtsi" +#include "k3-am62-mcu.dtsi" +#include "k3-am62-wakeup.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am625.dtsi b/arch/arm64/boot/dts/ti/k3-am625.dtsi new file mode 100644 index 000000000000..887f31c23fef --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625.dtsi @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM625 SoC family in Quad core configuration + * + * TRM: https://www.ti.com/lit/pdf/spruiv7 + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; + +#include "k3-am62.dtsi" + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + reg = <0x000>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + reg = <0x001>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53"; + reg = <0x002>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53"; + reg = <0x003>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x40000>; + cache-line-size = <64>; + cache-sets = <512>; + }; +}; -- cgit From a033588ec66bffd6cb51f946b2e998a9f9bf598d Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 25 Feb 2022 17:32:39 +0530 Subject: arm64: dts: ti: Add support for AM62-SK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit AM62 StarterKit (SK) board is a low cost, small form factor board designed for TI’s AM625 SoC. It supports the following interfaces: * 2 GB DDR4 RAM * x2 Gigabit Ethernet interfaces capable of working in Switch and MAC mode * x1 HDMI Port with audio + x1 OLDI/LVDS Display interface for Dual Display * x1 Headphone Jack * x1 USB2.0 Hub with two Type A host and x1 USB Type-C DRP Port * x1 UHS-1 capable µSD card slot * 2.4/5 GHz WLAN + Bluetooth 4.2 through WL1837 * 512 Mbit OSPI flash * x4 UART through UART-USB bridge * XDS110 for onboard JTAG debug using USB * Temperature sensors, user push buttons and LEDs * 40-pin User Expansion Connector * 24-pin header for peripherals in MCU island (I2C, UART, SPI, IO) * 20-pin header for Programmable Realtime Unit (PRU) IO pins * 15-pin CSI header Add basic support for AM62-SK. Schematics: https://www.ti.com/lit/zip/sprr448 Signed-off-by: Nishanth Menon Signed-off-by: Vignesh Raghavendra Reviewed-by: Bryan Brattlof Link: https://lore.kernel.org/r/20220225120239.1303821-6-vigneshr@ti.com --- arch/arm64/boot/dts/ti/Makefile | 2 + arch/arm64/boot/dts/ti/k3-am625-sk.dts | 206 +++++++++++++++++++++++++++++++++ 2 files changed, 208 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am625-sk.dts (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 90be511bc4d0..02e5d80344d0 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -21,3 +21,5 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721s2-common-proc-board.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-sk.dtb + +dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts new file mode 100644 index 000000000000..0de4113ccd5d --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -0,0 +1,206 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AM625 SK: https://www.ti.com/lit/zip/sprr448 + * + * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; + +#include +#include +#include "k3-am625.dtsi" + +/ { + compatible = "ti,am625-sk", "ti,am625"; + model = "Texas Instruments AM625 SK"; + + aliases { + serial2 = &main_uart0; + }; + + chosen { + stdout-path = "serial2:115200n8"; + bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; + }; + + memory@80000000 { + device_type = "memory"; + /* 2G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + alignment = <0x1000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + alignment = <0x1000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9db00000 0x00 0xc00000>; + no-map; + }; + }; + + vmain_pd: regulator-0 { + /* TPS65988 PD CONTROLLER OUTPUT */ + compatible = "regulator-fixed"; + regulator-name = "vmain_pd"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_5v0: regulator-1 { + /* Output of LM34936 */ + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_3v3_sys: regulator-2 { + /* output of LM61460-Q1 */ + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&usr_led_pins_default>; + + led-0 { + label = "am62-sk:green:heartbeat"; + gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + function = LED_FUNCTION_HEARTBEAT; + default-state = "off"; + }; + }; +}; + +&main_pmx0 { + main_uart0_pins_default: main-uart0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ + AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ + >; + }; + + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ + AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ + >; + }; + + main_i2c1_pins_default: main-i2c1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ + AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ + >; + }; + + usr_led_pins_default: usr-led-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ + >; + }; +}; + +&wkup_uart0 { + /* WKUP UART0 is used by DM firmware */ + status = "reserved"; +}; + +&mcu_uart0 { + status = "disabled"; +}; + +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; +}; + +&main_uart1 { + /* Main UART1 is used by TIFS firmware */ + status = "reserved"; +}; + +&main_uart2 { + status = "disabled"; +}; + +&main_uart3 { + status = "disabled"; +}; + +&main_uart4 { + status = "disabled"; +}; + +&main_uart5 { + status = "disabled"; +}; + +&main_uart6 { + status = "disabled"; +}; + +&mcu_i2c0 { + status = "disabled"; +}; + +&wkup_i2c0 { + status = "disabled"; +}; + +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; +}; + +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <400000>; +}; + +&main_i2c2 { + status = "disabled"; +}; + +&main_i2c3 { + status = "disabled"; +}; + +&mailbox0_cluster0 { + mbox_m4_0: mbox-m4-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; -- cgit From 5344930c64ab7416bc845142dd1367120614b51c Mon Sep 17 00:00:00 2001 From: Marek Behún Date: Sun, 20 Feb 2022 20:33:43 +0100 Subject: arm64: dts: marvell: armada-37xx: Add clock to PCIe node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The clock binding documents PCIe clock for a long time already. Add clock phande into the PCIe node. Signed-off-by: Marek Behún Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 673f4906eef9..c0de8d10e58c 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -489,6 +489,7 @@ bus-range = <0x00 0xff>; interrupts = ; #interrupt-cells = <1>; + clocks = <&sb_periph_clk 13>; msi-parent = <&pcie0>; msi-controller; /* -- cgit From c953c764e505428f59ffe6afb1c73b89b5b1ac35 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Mon, 28 Feb 2022 16:39:03 +0530 Subject: arm64: dts: ns2: Fix spi-cpol and spi-cpha property Broadcom ns2 platform has spi-cpol and spi-cpho properties set incorrectly. As per spi-slave-peripheral-prop.yaml, these properties are of flag or boolean type and not integer type. Fix the values. Fixes: d69dbd9f41a7c (arm64: dts: Add ARM PL022 SPI DT nodes for NS2) Signed-off-by: Kuldeep Singh CC: Ray Jui CC: Scott Branden CC: Florian Fainelli --- arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts index ec19fbf928a1..12a4b1c03390 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts @@ -111,8 +111,8 @@ compatible = "silabs,si3226x"; reg = <0>; spi-max-frequency = <5000000>; - spi-cpha = <1>; - spi-cpol = <1>; + spi-cpha; + spi-cpol; pl022,hierarchy = <0>; pl022,interface = <0>; pl022,slave-tx-disable = <0>; @@ -135,8 +135,8 @@ at25,byte-len = <0x8000>; at25,addr-mode = <2>; at25,page-size = <64>; - spi-cpha = <1>; - spi-cpol = <1>; + spi-cpha; + spi-cpol; pl022,hierarchy = <0>; pl022,interface = <0>; pl022,slave-tx-disable = <0>; -- cgit From 462f6c4a7c082b17a1608807732ab8d818eaf319 Mon Sep 17 00:00:00 2001 From: Maoguang Meng Date: Mon, 6 Dec 2021 21:04:25 +0800 Subject: arm64: dts: mt8183: add jpeg enc node for mt8183 Add jpeg encoder device tree node. Signed-off-by: Maoguang Meng Signed-off-by: Hsin-Yi Wang Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20211206130425.184420-3-hsinyi@chromium.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 00f2ddd245e1..4b08691ed39e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1594,6 +1594,18 @@ power-domains = <&spm MT8183_POWER_DOMAIN_VENC>; }; + venc_jpg: venc_jpg@17030000 { + compatible = "mediatek,mt8183-jpgenc", "mediatek,mtk-jpgenc"; + reg = <0 0x17030000 0 0x1000>; + interrupts = ; + mediatek,larb = <&larb4>; + iommus = <&iommu M4U_PORT_JPGENC_RDMA>, + <&iommu M4U_PORT_JPGENC_BSDMA>; + power-domains = <&spm MT8183_POWER_DOMAIN_VENC>; + clocks = <&vencsys CLK_VENC_JPGENC>; + clock-names = "jpgenc"; + }; + ipu_conn: syscon@19000000 { compatible = "mediatek,mt8183-ipu_conn", "syscon"; reg = <0 0x19000000 0 0x1000>; -- cgit From a97af4b52b63e28550dca16472d707e8d180e0f6 Mon Sep 17 00:00:00 2001 From: Mattijs Korpershoek Date: Fri, 21 Jan 2022 15:03:23 +0100 Subject: arm64: dts: mt6358: add mt6358-keys node This enables the power,home keys on MediaTek boards with a mt6358 pmic. Signed-off-by: Mattijs Korpershoek Link: https://lore.kernel.org/r/20220121140323.4080640-5-mkorpershoek@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt6358.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt6358.dtsi b/arch/arm64/boot/dts/mediatek/mt6358.dtsi index 95145076b7e6..98f3b0e0c9f6 100644 --- a/arch/arm64/boot/dts/mediatek/mt6358.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6358.dtsi @@ -2,6 +2,7 @@ /* * Copyright (c) 2020 MediaTek Inc. */ +#include &pwrap { pmic: mt6358 { @@ -357,5 +358,16 @@ mt6358rtc: mt6358rtc { compatible = "mediatek,mt6358-rtc"; }; + + mt6358keys: mt6358keys { + compatible = "mediatek,mt6358-keys"; + power { + linux,keycodes = ; + wakeup-source; + }; + home { + linux,keycodes = ; + }; + }; }; }; -- cgit From 994a71a3c9110cc906aee2b7066aaecbafdfd989 Mon Sep 17 00:00:00 2001 From: Chun-Jie Chen Date: Wed, 25 Aug 2021 09:04:26 +0800 Subject: arm64: dts: mediatek: Add mt8192 power domains controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add power domains controller node for SoC mt8192 Signed-off-by: Weiyi Lu Signed-off-by: Chun-Jie Chen Reviewed-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20210825010426.30303-1-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 201 +++++++++++++++++++++++++++++++ 1 file changed, 201 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index c1d4030e7e4b..411feb294613 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include / { compatible = "mediatek,mt8192"; @@ -301,6 +302,206 @@ #interrupt-cells = <2>; }; + scpsys: syscon@10006000 { + compatible = "syscon", "simple-mfd"; + reg = <0 0x10006000 0 0x1000>; + #power-domain-cells = <1>; + + /* System Power Manager */ + spm: power-controller { + compatible = "mediatek,mt8192-power-controller"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + /* power domain of the SoC */ + power-domain@MT8192_POWER_DOMAIN_AUDIO { + reg = ; + clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>, + <&infracfg CLK_INFRA_AUDIO_26M_B>, + <&infracfg CLK_INFRA_AUDIO>; + clock-names = "audio", "audio1", "audio2"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_CONN { + reg = ; + clocks = <&infracfg CLK_INFRA_PMIC_CONN>; + clock-names = "conn"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_MFG0 { + reg = ; + clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>; + clock-names = "mfg"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8192_POWER_DOMAIN_MFG1 { + reg = ; + mediatek,infracfg = <&infracfg>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8192_POWER_DOMAIN_MFG2 { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_MFG3 { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_MFG4 { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_MFG5 { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_MFG6 { + reg = ; + #power-domain-cells = <0>; + }; + }; + }; + + power-domain@MT8192_POWER_DOMAIN_DISP { + reg = ; + clocks = <&topckgen CLK_TOP_DISP_SEL>, + <&mmsys CLK_MM_SMI_INFRA>, + <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_GALS>, + <&mmsys CLK_MM_SMI_IOMMU>; + clock-names = "disp", "disp-0", "disp-1", "disp-2", + "disp-3"; + mediatek,infracfg = <&infracfg>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8192_POWER_DOMAIN_IPE { + reg = ; + clocks = <&topckgen CLK_TOP_IPE_SEL>, + <&ipesys CLK_IPE_LARB19>, + <&ipesys CLK_IPE_LARB20>, + <&ipesys CLK_IPE_SMI_SUBCOM>, + <&ipesys CLK_IPE_GALS>; + clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2", + "ipe-3"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_ISP { + reg = ; + clocks = <&topckgen CLK_TOP_IMG1_SEL>, + <&imgsys CLK_IMG_LARB9>, + <&imgsys CLK_IMG_GALS>; + clock-names = "isp", "isp-0", "isp-1"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_ISP2 { + reg = ; + clocks = <&topckgen CLK_TOP_IMG2_SEL>, + <&imgsys2 CLK_IMG2_LARB11>, + <&imgsys2 CLK_IMG2_GALS>; + clock-names = "isp2", "isp2-0", "isp2-1"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_MDP { + reg = ; + clocks = <&topckgen CLK_TOP_MDP_SEL>, + <&mdpsys CLK_MDP_SMI0>; + clock-names = "mdp", "mdp-0"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_VENC { + reg = ; + clocks = <&topckgen CLK_TOP_VENC_SEL>, + <&vencsys CLK_VENC_SET1_VENC>; + clock-names = "venc", "venc-0"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_VDEC { + reg = ; + clocks = <&topckgen CLK_TOP_VDEC_SEL>, + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_LAT>, + <&vdecsys_soc CLK_VDEC_SOC_LARB1>; + clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2"; + mediatek,infracfg = <&infracfg>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8192_POWER_DOMAIN_VDEC2 { + reg = ; + clocks = <&vdecsys CLK_VDEC_VDEC>, + <&vdecsys CLK_VDEC_LAT>, + <&vdecsys CLK_VDEC_LARB1>; + clock-names = "vdec2-0", "vdec2-1", + "vdec2-2"; + #power-domain-cells = <0>; + }; + }; + + power-domain@MT8192_POWER_DOMAIN_CAM { + reg = ; + clocks = <&topckgen CLK_TOP_CAM_SEL>, + <&camsys CLK_CAM_LARB13>, + <&camsys CLK_CAM_LARB14>, + <&camsys CLK_CAM_CCU_GALS>, + <&camsys CLK_CAM_CAM2MM_GALS>; + clock-names = "cam", "cam-0", "cam-1", "cam-2", + "cam-3"; + mediatek,infracfg = <&infracfg>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8192_POWER_DOMAIN_CAM_RAWA { + reg = ; + clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>; + clock-names = "cam_rawa-0"; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_CAM_RAWB { + reg = ; + clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>; + clock-names = "cam_rawb-0"; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_CAM_RAWC { + reg = ; + clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>; + clock-names = "cam_rawc-0"; + #power-domain-cells = <0>; + }; + }; + }; + }; + }; + watchdog: watchdog@10007000 { compatible = "mediatek,mt8192-wdt"; reg = <0 0x10007000 0 0x100>; -- cgit From 1f9986b258c2c6c6d89faad9a9ed5f42daeeca9a Mon Sep 17 00:00:00 2001 From: Sam Shih Date: Wed, 19 Jan 2022 20:36:24 +0800 Subject: arm64: dts: mediatek: add clock support for mt7986a Add clock controller nodes, include 40M clock source, topckgen, infracfg, apmixedsys and ethernet subsystem. Signed-off-by: Sam Shih Link: https://lore.kernel.org/r/20220119123624.10043-2-sam.shih@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 68 ++++++++++++++++++++++++++++--- 1 file changed, 63 insertions(+), 5 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index b8da76b6ba47..694acf8f5b70 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -6,16 +6,18 @@ #include #include +#include / { interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; - system_clk: dummy40m { + clk40m: oscillator@0 { compatible = "fixed-clock"; clock-frequency = <40000000>; #clock-cells = <0>; + clock-output-names = "clkxtal"; }; cpus { @@ -98,6 +100,18 @@ interrupts = ; }; + infracfg: infracfg@10001000 { + compatible = "mediatek,mt7986-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + topckgen: topckgen@1001b000 { + compatible = "mediatek,mt7986-topckgen", "syscon"; + reg = <0 0x1001B000 0 0x1000>; + #clock-cells = <1>; + }; + watchdog: watchdog@1001c000 { compatible = "mediatek,mt7986-wdt", "mediatek,mt6589-wdt"; @@ -107,6 +121,12 @@ status = "disabled"; }; + apmixedsys: apmixedsys@1001e000 { + compatible = "mediatek,mt7986-apmixedsys"; + reg = <0 0x1001E000 0 0x1000>; + #clock-cells = <1>; + }; + pio: pinctrl@1001f000 { compatible = "mediatek,mt7986a-pinctrl"; reg = <0 0x1001f000 0 0x1000>, @@ -128,11 +148,25 @@ #interrupt-cells = <2>; }; + sgmiisys0: syscon@10060000 { + compatible = "mediatek,mt7986-sgmiisys_0", + "syscon"; + reg = <0 0x10060000 0 0x1000>; + #clock-cells = <1>; + }; + + sgmiisys1: syscon@10070000 { + compatible = "mediatek,mt7986-sgmiisys_1", + "syscon"; + reg = <0 0x10070000 0 0x1000>; + #clock-cells = <1>; + }; + trng: trng@1020f000 { compatible = "mediatek,mt7986-rng", "mediatek,mt7623-rng"; reg = <0 0x1020f000 0 0x100>; - clocks = <&system_clk>; + clocks = <&infracfg CLK_INFRA_TRNG_CK>; clock-names = "rng"; status = "disabled"; }; @@ -142,7 +176,13 @@ "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x400>; interrupts = ; - clocks = <&system_clk>; + clocks = <&infracfg CLK_INFRA_UART0_SEL>, + <&infracfg CLK_INFRA_UART0_CK>; + clock-names = "baud", "bus"; + assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_UART0_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, + <&topckgen CLK_TOP_UART_SEL>; status = "disabled"; }; @@ -151,7 +191,11 @@ "mediatek,mt6577-uart"; reg = <0 0x11003000 0 0x400>; interrupts = ; - clocks = <&system_clk>; + clocks = <&infracfg CLK_INFRA_UART1_SEL>, + <&infracfg CLK_INFRA_UART1_CK>; + clock-names = "baud", "bus"; + assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>; status = "disabled"; }; @@ -160,10 +204,24 @@ "mediatek,mt6577-uart"; reg = <0 0x11004000 0 0x400>; interrupts = ; - clocks = <&system_clk>; + clocks = <&infracfg CLK_INFRA_UART2_SEL>, + <&infracfg CLK_INFRA_UART2_CK>; + clock-names = "baud", "bus"; + assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>; status = "disabled"; }; + ethsys: syscon@15000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mediatek,mt7986-ethsys", + "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; }; -- cgit From fbaac5b1057de34d3776df9fc904b7c7e634d945 Mon Sep 17 00:00:00 2001 From: Sam Shih Date: Wed, 19 Jan 2022 20:35:36 +0800 Subject: arm64: dts: mediatek: update mt7986a memory node This patch updates the format of memory node in DT adding the correct device_type. Signed-off-by: Sam Shih Link: https://lore.kernel.org/r/20220119123537.9968-2-sam.shih@mediatek.com [mb: fixed commit message] Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts index 5cd760abff51..21e420829572 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts @@ -19,7 +19,8 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@40000000 { + device_type = "memory"; reg = <0 0x40000000 0 0x40000000>; }; }; -- cgit From 809967d76e919af142028fae0f024b8d6966fac8 Mon Sep 17 00:00:00 2001 From: Sam Shih Date: Wed, 19 Jan 2022 20:35:37 +0800 Subject: arm64: dts: mediatek: update mt7986b memory node This patch updates the format of memory node in DT adding the device_type. Signed-off-by: Sam Shih Link: https://lore.kernel.org/r/20220119123537.9968-3-sam.shih@mediatek.com [mb: fixed commit message] Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts index 5fb752edd754..d73467ea3641 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts @@ -19,7 +19,8 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@40000000 { + device_type = "memory"; reg = <0 0x40000000 0 0x40000000>; }; }; -- cgit From 4b557e171ae7b5c5b69f7a5eee553714f7c52435 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 18 Feb 2022 17:15:22 +0100 Subject: arm64: dts: agilex/stratix10: add clock-names to USB DWC2 node USB DWC2 requires clock-names: arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dt.yaml: usb@ffb00000: 'clock-names' is a required property Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 1 + arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 1 + 2 files changed, 2 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index da032a6f71da..884bda106399 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -485,6 +485,7 @@ resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; reset-names = "dwc2", "dwc2-ecc"; clocks = <&clkmgr STRATIX10_USB_CLK>; + clock-names = "otg"; iommus = <&smmu 6>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index 1f4618c1062e..e593d7797d31 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -510,6 +510,7 @@ resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; reset-names = "dwc2", "dwc2-ecc"; clocks = <&clkmgr AGILEX_USB_CLK>; + clock-names = "otg"; iommus = <&smmu 6>; status = "disabled"; }; -- cgit From ef82c9be844f6b249a69d8fa190d4d686121d55c Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Thu, 24 Feb 2022 10:29:56 -0600 Subject: arm64: dts: n5x: add sdr edac support The N5X platform has the Synopsys DDR controller the includes an EDAC controller. Add the entry for the controller in the DTS file instead of the base Agilex DTSI because the base Agilex does not have the controller. Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts index 5609d8df6729..50b29fa7ee01 100644 --- a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts @@ -24,6 +24,16 @@ /* We expect the bootloader to fill in the reg */ reg = <0 0 0 0>; }; + + soc { + sdram_edac: sdr_edac@f87f8000 { + compatible = "snps,ddrc-3.80a"; + reg = <0xf87f8000 0x400>; + interrupts = <0 175 4>; + intel,sysmgr-syscon = <&sysmgr 0xb8>; + status = "okay"; + }; + }; }; &clkmgr { -- cgit From 55927cb44db43a57699fa652e2437a91620385dc Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Tue, 1 Mar 2022 16:24:18 +0100 Subject: arm64: dts: broadcom: Fix sata nodename After converting ahci-platform txt binding to yaml nodename is reported as not matching the standard: arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dt.yaml: ahci@663f2000: $nodename:0: 'ahci@663f2000' does not match '^sata(@.*)?$' Fix it to match binding. Fixes: ac9aae00f0fc ("arm64: dts: Add SATA3 AHCI and SATA3 PHY DT nodes for NS2") Signed-off-by: Frank Wunderlich Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi index 6da38ac317f2..60c1f64e9617 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi @@ -687,7 +687,7 @@ }; }; - sata: ahci@663f2000 { + sata: sata@663f2000 { compatible = "brcm,iproc-ahci", "generic-ahci"; reg = <0x663f2000 0x1000>; dma-coherent; -- cgit From e7f127b213faf9494b2c4215e72055a824814fac Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 29 Jan 2022 18:56:21 +0100 Subject: arm64: dts: juno: align pl330 node name with dtschema Fixes dtbs_check warning: dma@7ff00000: $nodename:0: 'dma@7ff00000' does not match '^dma-controller(@.*)?$' Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220129175621.299254-1-krzysztof.kozlowski@canonical.com --- arch/arm64/boot/dts/arm/juno-base.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index 6288e104a089..af499049cb00 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -672,7 +672,7 @@ dma-coherent; }; - dma@7ff00000 { + dma-controller@7ff00000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0x7ff00000 0 0x1000>; #dma-cells = <1>; -- cgit From 8ede5890faaa28ac380b040bc933ead56ae9ec28 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 29 Jan 2022 18:55:13 +0100 Subject: arm64: dts: lg: add dma-cells to pl330 node dma-cells property is required for dma-controller. Fixes dtbs_check warnings like: dma@c1128000: '#dma-cells' is a required property Signed-off-by: Krzysztof Kozlowski Acked-by: Chanho Min Link: https://lore.kernel.org/r/20220129175514.298942-1-krzysztof.kozlowski@canonical.com --- arch/arm64/boot/dts/lg/lg1312.dtsi | 1 + arch/arm64/boot/dts/lg/lg1313.dtsi | 1 + 2 files changed, 2 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi b/arch/arm64/boot/dts/lg/lg1312.dtsi index 081fe7a9f605..ef57df716f14 100644 --- a/arch/arm64/boot/dts/lg/lg1312.dtsi +++ b/arch/arm64/boot/dts/lg/lg1312.dtsi @@ -188,6 +188,7 @@ interrupts = ; clocks = <&clk_bus>; clock-names = "apb_pclk"; + #dma-cells = <1>; }; gpio0: gpio@fd400000 { #gpio-cells = <2>; diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi b/arch/arm64/boot/dts/lg/lg1313.dtsi index 604bb6975337..4e6b65939b72 100644 --- a/arch/arm64/boot/dts/lg/lg1313.dtsi +++ b/arch/arm64/boot/dts/lg/lg1313.dtsi @@ -188,6 +188,7 @@ interrupts = ; clocks = <&clk_bus>; clock-names = "apb_pclk"; + #dma-cells = <1>; }; gpio0: gpio@fd400000 { #gpio-cells = <2>; -- cgit From ad3c72b0c6b912a0e917ae8010c62cc98012ab1e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 29 Jan 2022 18:55:14 +0100 Subject: arm64: dts: lg: align pl330 node name with dtschema Fixes dtbs_check warnings like: dma@c1128000: $nodename:0: 'dma@c1128000' does not match '^dma-controller(@.*)?$' Signed-off-by: Krzysztof Kozlowski Acked-by: Chanho Min Link: https://lore.kernel.org/r/20220129175514.298942-2-krzysztof.kozlowski@canonical.com --- arch/arm64/boot/dts/lg/lg1312.dtsi | 2 +- arch/arm64/boot/dts/lg/lg1313.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi b/arch/arm64/boot/dts/lg/lg1312.dtsi index ef57df716f14..bec97480a960 100644 --- a/arch/arm64/boot/dts/lg/lg1312.dtsi +++ b/arch/arm64/boot/dts/lg/lg1312.dtsi @@ -182,7 +182,7 @@ clocks = <&clk_bus>; clock-names = "apb_pclk"; }; - dmac0: dma@c1128000 { + dmac0: dma-controller@c1128000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xc1128000 0x1000>; interrupts = ; diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi b/arch/arm64/boot/dts/lg/lg1313.dtsi index 4e6b65939b72..ada3d4dc6305 100644 --- a/arch/arm64/boot/dts/lg/lg1313.dtsi +++ b/arch/arm64/boot/dts/lg/lg1313.dtsi @@ -182,7 +182,7 @@ clocks = <&clk_bus>; clock-names = "apb_pclk"; }; - dmac0: dma@c1128000 { + dmac0: dma-controller@c1128000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xc1128000 0x1000>; interrupts = ; -- cgit From 37cbd3c522869247ed4525b5042ff4c6a276c813 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 4 Mar 2022 14:25:58 -0600 Subject: arm64: dts: rockchip: Fix SDIO regulator supply properties on rk3399-firefly A label reference without brackets is a path string, not a phandle as intended. Add the missing brackets. Fixes: a5002c41c383 ("arm64: dts: rockchip: add WiFi module support for Firefly-RK3399") Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20220304202559.317749-1-robh@kernel.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-firefly.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts index 19683f1dbf93..c654b6b02f3f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts @@ -775,8 +775,8 @@ sd-uhs-sdr104; /* Power supply */ - vqmmc-supply = &vcc1v8_s3; /* IO line */ - vmmc-supply = &vcc_sdio; /* card's power */ + vqmmc-supply = <&vcc1v8_s3>; /* IO line */ + vmmc-supply = <&vcc_sdio>; /* card's power */ #address-cells = <1>; #size-cells = <0>; -- cgit From 079d76ab304227dd29e7bba76736567b5ac73030 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Thu, 3 Mar 2022 14:39:55 -0600 Subject: arm64: dts: rockchip: Remove vcc13 and vcc14 for rk808 The Rockchip rk808 Power Management IC does not have a vcc13 or a vcc14. The schematics for at least the Pinebook Pro suggest this is actually vcc1 and vcc2, and may be an artifact from the reference design schematic). Signed-off-by: Chris Morgan Reviewed-by: Robin Murphy Link: https://lore.kernel.org/r/20220303203958.4904-2-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts | 2 -- arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi | 2 -- 2 files changed, 4 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts index 8a048ddc9505..d6b68d77d63a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts @@ -472,8 +472,6 @@ vcc10-supply = <&vcc_sysin>; vcc11-supply = <&vcc_sysin>; vcc12-supply = <&vcc3v3_sys>; - vcc13-supply = <&vcc_sysin>; - vcc14-supply = <&vcc_sysin>; regulators { /* rk3399 center logic supply */ diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi index d1aaf8e83391..0e45cc2d195b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi @@ -310,8 +310,6 @@ vcc10-supply = <&vcc3v3_sys>; vcc11-supply = <&vcc3v3_sys>; vcc12-supply = <&vcc3v3_sys>; - vcc13-supply = <&vcc3v3_sys>; - vcc14-supply = <&vcc3v3_sys>; vddio-supply = <&vcc_3v0>; regulators { -- cgit From 9d25aadd55bb8c37c468661b506f932d15492028 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Thu, 3 Mar 2022 14:39:56 -0600 Subject: arm64: dts: rockchip: Add #clock-cells value for rk805 Based on a brief discussion on the mailing list it was determined that clock-cells should be a required parameter in the event that a consumer of the clock gets added in an overlay. Signed-off-by: Chris Morgan Reviewed-by: Robin Murphy Link: https://lore.kernel.org/r/20220303203958.4904-3-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts index de2d3e88e27f..40bf808642b9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts @@ -160,6 +160,7 @@ pinctrl-0 = <&pmic_int_l>; rockchip,system-power-controller; wakeup-source; + #clock-cells = <0>; vcc1-supply = <&vcc_sys>; vcc2-supply = <&vcc_sys>; -- cgit From bb8555fe87154e90dcd5a05082fd499d46c93fb5 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Mon, 7 Mar 2022 23:51:00 +0530 Subject: arm64: dts: ns2: Fix spi clock name SPI clock name for pl022 is "sspclk" and not "spiclk". Also fix below dtc warning: clock-names:0: 'spiclk' is not one of ['SSPCLK', 'sspclk'] Signed-off-by: Kuldeep Singh Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi index 60c1f64e9617..f59fa3979a04 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi @@ -644,7 +644,7 @@ reg = <0x66180000 0x1000>; interrupts = ; clocks = <&iprocslow>, <&iprocslow>; - clock-names = "spiclk", "apb_pclk"; + clock-names = "sspclk", "apb_pclk"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -655,7 +655,7 @@ reg = <0x66190000 0x1000>; interrupts = ; clocks = <&iprocslow>, <&iprocslow>; - clock-names = "spiclk", "apb_pclk"; + clock-names = "sspclk", "apb_pclk"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; -- cgit From 66435063c5f31caa70ecadb3de4fe4d17b141b51 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Mon, 7 Mar 2022 23:51:01 +0530 Subject: arm64: dts: stingray: Fix spi clock name SPI clock name for pl022 is "sspclk" and not "spiclk". Also fix below dtc warning: clock-names:0: 'spiclk' is not one of ['SSPCLK', 'sspclk'] Signed-off-by: Kuldeep Singh Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi index 4135246b6e72..7f1b8efd0883 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi @@ -519,7 +519,7 @@ reg = <0x00180000 0x1000>; interrupts = ; clocks = <&hsls_div2_clk>, <&hsls_div2_clk>; - clock-names = "spiclk", "apb_pclk"; + clock-names = "sspclk", "apb_pclk"; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -531,7 +531,7 @@ reg = <0x00190000 0x1000>; interrupts = ; clocks = <&hsls_div2_clk>, <&hsls_div2_clk>; - clock-names = "spiclk", "apb_pclk"; + clock-names = "sspclk", "apb_pclk"; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; -- cgit From bfb60ede2c3e5ce6281ab3fb3861c333fe131897 Mon Sep 17 00:00:00 2001 From: Alim Akhtar Date: Wed, 16 Mar 2022 16:43:08 +0100 Subject: arm64: dts: fsd: Add the MCT support Add node relevant to support MCT, which is used as one of the system timer on this SoC. Signed-off-by: Alim Akhtar Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220223171858.11384-1-alim.akhtar@samsung.com Link: https://lore.kernel.org/r/20220316154309.436028-2-krzysztof.kozlowski@canonical.com' Signed-off-by: Arnd Bergmann --- arch/arm64/boot/dts/tesla/fsd.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi index da4acd68b976..9a652abcbcac 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -725,6 +725,29 @@ num-cs = <1>; status = "disabled"; }; + + timer@10040000 { + compatible = "samsung,exynos4210-mct"; + reg = <0x0 0x10040000 0x0 0x800>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&fin_pll>, <&clock_imem IMEM_MCT_PCLK>; + clock-names = "fin_pll", "mct"; + }; }; }; -- cgit From bcea9aaa4373f2ee8ea3c758b76c479dffe85822 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 18 Mar 2022 13:10:44 +0100 Subject: arm64: dts: n5x: drop invalid property and fix edac node name The intel,sysmgr-syscon in EDAC/memory controller node is not a recognized and documented property, so drop it to fix error: sdr_edac@f87f8000: 'intel,sysmgr-syscon' does not match any of the regexes: 'pinctrl-[0-9]+' Align also the node name with Devicetree specification (generic, not specific, and EDAC is purely Linux term). Fixes: ef82c9be844f ("arm64: dts: n5x: add sdr edac support") Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220318121044.108750-1-krzysztof.kozlowski@canonical.com' Signed-off-by: Arnd Bergmann --- arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts index 50b29fa7ee01..62c66e52b656 100644 --- a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts @@ -26,11 +26,10 @@ }; soc { - sdram_edac: sdr_edac@f87f8000 { + sdram_edac: memory-controller@f87f8000 { compatible = "snps,ddrc-3.80a"; reg = <0xf87f8000 0x400>; interrupts = <0 175 4>; - intel,sysmgr-syscon = <&sysmgr 0xb8>; status = "okay"; }; }; -- cgit