From c36ad1943f947eb763fb2eb976a5f6f25150113d Mon Sep 17 00:00:00 2001 From: Joey Gouly Date: Tue, 6 Jun 2023 15:58:43 +0100 Subject: arm64/sysreg: add PIR*_ELx registers Add definitions of PIR_EL1, PIR_EL12, PIRE0_EL1, PIRE0_EL12, and PIR_EL2 registers. Signed-off-by: Joey Gouly Cc: Will Deacon Cc: Mark Brown Reviewed-by: Mark Brown Acked-by: Catalin Marinas Link: https://lore.kernel.org/r/20230606145859.697944-5-joey.gouly@arm.com Signed-off-by: Catalin Marinas --- arch/arm64/include/asm/sysreg.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch/arm64/include/asm/sysreg.h') diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index e72d9aaab6b1..11b8ef74f239 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -758,6 +758,25 @@ #define ICH_VTR_TDS_SHIFT 19 #define ICH_VTR_TDS_MASK (1 << ICH_VTR_TDS_SHIFT) +/* + * Permission Indirection Extension (PIE) permission encodings. + * Encodings with the _O suffix, have overlays applied (Permission Overlay Extension). + */ +#define PIE_NONE_O 0x0 +#define PIE_R_O 0x1 +#define PIE_X_O 0x2 +#define PIE_RX_O 0x3 +#define PIE_RW_O 0x5 +#define PIE_RWnX_O 0x6 +#define PIE_RWX_O 0x7 +#define PIE_R 0x8 +#define PIE_GCS 0x9 +#define PIE_RX 0xa +#define PIE_RW 0xc +#define PIE_RWX 0xe + +#define PIRx_ELx_PERM(idx, perm) ((perm) << ((idx) * 4)) + #define ARM64_FEATURE_FIELD_BITS 4 /* Defined for compatibility only, do not add new users. */ -- cgit