From 28ff811f58b1841be63692601dee771a09afc7d6 Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Fri, 15 Mar 2019 13:38:28 +0100 Subject: ARM: dts: sun8i-h3: Add support for the RerVision H3-DVK board This is an H3-based board that sticks close to the reference design. Supported features: * UART * DRAM * MMC * eMMC * Ethernet * USB host * USB peripheral * HDMI Signed-off-by: Paul Kocialkowski Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/sun8i-h3-rervision-dvk.dts | 114 +++++++++++++++++++++++++++ 2 files changed, 115 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-h3-rervision-dvk.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f4f5aeaf3298..dad1202d1d87 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1091,6 +1091,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-h3-orangepi-plus.dtb \ sun8i-h3-orangepi-plus2e.dtb \ sun8i-h3-orangepi-zero-plus2.dtb \ + sun8i-h3-rervision-dvk.dtb \ sun8i-r16-bananapi-m2m.dtb \ sun8i-r16-nintendo-nes-classic.dtb \ sun8i-r16-nintendo-super-nes-classic.dtb \ diff --git a/arch/arm/boot/dts/sun8i-h3-rervision-dvk.dts b/arch/arm/boot/dts/sun8i-h3-rervision-dvk.dts new file mode 100644 index 000000000000..51bd2c00bbae --- /dev/null +++ b/arch/arm/boot/dts/sun8i-h3-rervision-dvk.dts @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Bootlin + * Author: Paul Kocialkowski + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "RerVision H3-DVK"; + compatible = "rervision,h3-dvk", "allwinner,sun8i-h3"; + + aliases { + ethernet0 = &emac; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; +}; + +&de { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ehci3 { + status = "okay"; +}; + +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&mmc0 { + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + status = "okay"; + vmmc-supply = <®_vcc3v3>; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usb_otg { + status = "okay"; + dr_mode = "peripheral"; +}; + +&usbphy { + status = "okay"; +}; -- cgit From de72618cb94f0487bb74eca35749d1f500f8de73 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sun, 10 Mar 2019 16:19:28 +0100 Subject: ARM: dts: rockchip: remove disable-wp from rv1108-elgin-r1 emmc node The mmc.txt didn't explicitly say disable-wp is for SD card slot only, but that is what it was designed for in the first place. Remove all disable-wp from emmc or sdio controllers. Signed-off-by: Johan Jonker Reviewed-by: Shawn Lin Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rv1108-elgin-r1.dts | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rv1108-elgin-r1.dts b/arch/arm/boot/dts/rv1108-elgin-r1.dts index 1c4507b66fdd..b1db924710c8 100644 --- a/arch/arm/boot/dts/rv1108-elgin-r1.dts +++ b/arch/arm/boot/dts/rv1108-elgin-r1.dts @@ -37,7 +37,6 @@ &emmc { bus-width = <8>; cap-mmc-highspeed; - disable-wp; no-sd; no-sdio; non-removable; -- cgit From 61346668325f17444f855b42df673f16d2baa7db Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 24 Feb 2019 20:10:06 +0000 Subject: ARM: dts: rockchip: Enable HDMI CEC on rk3288-tinker-s This patch enables HDMI CEC on Tinker Board S Signed-off-by: Jonas Karlman Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-tinker-s.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3288-tinker-s.dts b/arch/arm/boot/dts/rk3288-tinker-s.dts index d97da89bcd51..970e13859198 100644 --- a/arch/arm/boot/dts/rk3288-tinker-s.dts +++ b/arch/arm/boot/dts/rk3288-tinker-s.dts @@ -23,3 +23,8 @@ mmc-ddr-1_8v; status = "okay"; }; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec_c0>; +}; -- cgit From 494da92d56e45c88966fab4db2bed1a2f300c5f8 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 24 Feb 2019 21:52:00 +0000 Subject: ARM: dts: rockchip: add grf reference in rk3288 tsadc node The following message can be seen during boot: rockchip-thermal ff280000.tsadc: Missing rockchip,grf property Fix this by adding rockchip,grf property to tsadc node. The warning itself is not relevant on rk3288 right now, as the tsadc doesn't need to set GRF-values at this point and only newer variants do. Signed-off-by: Jonas Karlman Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index ca7d52daa8fb..b577f3e41811 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -569,6 +569,7 @@ pinctrl-1 = <&otp_out>; pinctrl-2 = <&otp_gpio>; #thermal-sensor-cells = <1>; + rockchip,grf = <&grf>; rockchip,hw-tshut-temp = <95000>; status = "disabled"; }; -- cgit From a008eae6956ac774a220f96de1af6a731e89ceac Mon Sep 17 00:00:00 2001 From: David Summers Date: Sat, 9 Mar 2019 15:39:22 +0000 Subject: ARM: dts: rockchip: Enable WiFi on rk3288-tinker This patch adds wifi support to the ASUS Tinker Board (S) machines. This is provided by an wifi card (RTL8723BS) wired into the sdio interface. It requires certain pins pulled, to enable the WiFi. The schematics for these board do not show the WiFi connection, so the connections have been taken from: https://github.com/TinkerBoard/debian_kernel/blob/develop/arch/arm/boot/dts/rk3288-miniarm.dts In particular the pulling of two pins. Co-developed-by: Stefan Wahren Signed-off-by: David Summers Signed-off-by: Stefan Wahren Tested-by: Tony McKahan Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-tinker.dtsi | 37 ++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3288-tinker.dtsi b/arch/arm/boot/dts/rk3288-tinker.dtsi index aa107ee41b8b..b053589f8ff8 100644 --- a/arch/arm/boot/dts/rk3288-tinker.dtsi +++ b/arch/arm/boot/dts/rk3288-tinker.dtsi @@ -5,6 +5,7 @@ #include "rk3288.dtsi" #include +#include / { chosen { @@ -61,6 +62,16 @@ }; }; + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 RK808_CLKOUT1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable>; + reset-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_LOW>, + <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; + }; + sound { compatible = "simple-audio-card"; simple-audio-card,format = "i2s"; @@ -337,6 +348,7 @@ status = "okay"; sdcard-supply = <&vccio_sd>; + wifi-supply = <&vcc_18>; }; &pinctrl { @@ -415,6 +427,13 @@ rockchip,pins = <7 8 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + sdio { + wifi_enable: wifi-enable { + rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>, + <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &pwm0 { @@ -439,6 +458,24 @@ vqmmc-supply = <&vccio_sd>; }; +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + max-frequency = <50000000>; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>, <&sdio0_int>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc_18>; + status = "okay"; +}; + &tsadc { rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ -- cgit From b6eac0d06b82712db8ffba36804e7e1225ce5919 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 9 Feb 2019 01:26:40 +0100 Subject: ARM: dts: meson8: add the internal clock measurer The Amlogic Meson8 SoC has an internal clock measurer IP which allows measuring frequencies of various clock paths. Enable it on meson8.dtsi so we can use it. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index a9781243453e..d2ec4af82cc5 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -345,6 +345,11 @@ status = "disabled"; }; + clock-measure@8758 { + compatible = "amlogic,meson8-clk-measure"; + reg = <0x8758 0x1c>; + }; + pinctrl_cbus: pinctrl@9880 { compatible = "amlogic,meson8-cbus-pinctrl"; reg = <0x9880 0x10>; -- cgit From f1975b982a2917f4fadd6af96fd1671e5dc57095 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 9 Feb 2019 01:26:41 +0100 Subject: ARM: dts: meson8b: add the internal clock measurer The Amlogic Meson8b SoC has an internal clock measurer IP which allows measuring frequencies of various clock paths. Enable it on meson8b.dtsi so we can use it. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index fe84a8c3ce81..df42e48f1cc1 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -294,6 +294,11 @@ status = "disabled"; }; + clock-measure@8758 { + compatible = "amlogic,meson8b-clk-measure"; + reg = <0x8758 0x1c>; + }; + pinctrl_cbus: pinctrl@9880 { compatible = "amlogic,meson8b-cbus-pinctrl"; reg = <0x9880 0x10>; -- cgit From d7fa8ed4337235511be39699a5295777cc326257 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 12 Feb 2019 18:45:50 +0100 Subject: ARM: dts: exynos: Use ADC for Exynos4x12 on Exynos4412 Exynos4412 should use "samsung,exynos4212-adc" compatible to report proper number of (four) channels. Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 26ad6ab3c6af..e5c041ec0756 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -274,7 +274,7 @@ }; adc: adc@126c0000 { - compatible = "samsung,exynos-adc-v1"; + compatible = "samsung,exynos4212-adc"; reg = <0x126C0000 0x100>; interrupt-parent = <&combiner>; interrupts = <10 3>; -- cgit From 15b8831f87874c21e431ffa3801781690973c384 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 12 Feb 2019 18:46:38 +0100 Subject: ARM: dts: exynos: Document regulator used by ADC on Odroid U3 Add ADC node to Odroid U3 with its regulator, purely for documentation purposes. The ADC stays disabled because it is not used (all inputs grounded). Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412-odroidu3.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/exynos4412-odroidu3.dts index 2bdf899df436..88891ff5f238 100644 --- a/arch/arm/boot/dts/exynos4412-odroidu3.dts +++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts @@ -66,6 +66,11 @@ }; }; +&adc { + vdd-supply = <&ldo10_reg>; + /* Nothing connected to ADC inputs, keep it disabled */ +}; + /* Supply for LAN9730/SMSC95xx */ &buck8_reg { regulator-name = "BUCK8_P3V3"; -- cgit From f35020b94a45f09b4dd97b4f1d721059f5a20867 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 18 Feb 2019 18:32:56 +0100 Subject: ARM: dts: exynos: Use stdout path property on Arndale Octa board Replacing bootargs with stdout-path property in chosen node allows using early console by adding just 'earlycon' parameter to kernel command line. Suggested-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5420-arndale-octa.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index 3447160e1fbf..832757999e4f 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -24,7 +24,7 @@ }; chosen { - bootargs = "console=ttySAC3,115200"; + stdout-path = "serial3:115200n8"; }; firmware@2073000 { -- cgit From 3619452589d0ea295351c6557061b37341a0cbc3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 18 Feb 2019 18:32:57 +0100 Subject: ARM: dts: exynos: Add unused PMIC regulators on Arndale Octa board Define the LDO14, LDO17, LDO22, LDO25, LDO30, LDO34, LDO36 and LDO37 unused regulators to describe the hardware. Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5420-arndale-octa.dts | 56 +++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index 832757999e4f..308c74ebeacd 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -180,6 +180,13 @@ regulator-max-microvolt = <2800000>; }; + ldo14_reg: LDO14 { + /* Unused */ + regulator-name = "PVDD_LDO14"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + ldo15_reg: LDO15 { regulator-name = "PVDD_PERI_2V8"; regulator-min-microvolt = <3300000>; @@ -192,6 +199,13 @@ regulator-max-microvolt = <2200000>; }; + ldo17_reg: LDO17 { + /* Unused */ + regulator-name = "PVDD_LDO17"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + ldo18_reg: LDO18 { regulator-name = "PVDD_EMMC_1V8"; regulator-min-microvolt = <1800000>; @@ -216,6 +230,13 @@ regulator-max-microvolt = <1800000>; }; + ldo22_reg: LDO22 { + /* Unused */ + regulator-name = "PVDD_LDO22"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <2375000>; + }; + ldo23_reg: LDO23 { regulator-name = "PVDD_MIFS_1V1"; regulator-min-microvolt = <1200000>; @@ -229,6 +250,13 @@ regulator-max-microvolt = <2800000>; }; + ldo25_reg: LDO25 { + /* Unused */ + regulator-name = "PVDD_LDO25"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + ldo26_reg: LDO26 { regulator-name = "PVDD_CAM0_AF_2V8"; regulator-min-microvolt = <3000000>; @@ -253,6 +281,13 @@ regulator-max-microvolt = <1800000>; }; + ldo30_reg: LDO30 { + /* Unused */ + regulator-name = "PVDD_LDO30"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + ldo31_reg: LDO31 { regulator-name = "PVDD_PERI_1V8"; regulator-min-microvolt = <1800000>; @@ -271,12 +306,33 @@ regulator-max-microvolt = <1800000>; }; + ldo34_reg: LDO34 { + /* Unused */ + regulator-name = "PVDD_LDO34"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + ldo35_reg: LDO35 { regulator-name = "PVDD_CAM0_DVDD_1V2"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; }; + ldo36_reg: LDO36 { + /* Unused */ + regulator-name = "PVDD_LDO36"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + ldo37_reg: LDO37 { + /* Unused */ + regulator-name = "PVDD_LDO37"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + ldo38_reg: LDO38 { regulator-name = "PVDD_CAM0_AVDD_2V8"; regulator-min-microvolt = <2800000>; -- cgit From 29a0a2a848ecf5af699f27a46efb39adaa33449f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 18 Feb 2019 20:48:40 +0100 Subject: ARM: dts: exynos: Add CPU cooling on Arndale Octa Arndale Octa board comes without fan so proper CPU cooling is necessary to avoid critical shutdowns when CPUs are busy. Although thermal zones were present but CPU cooling was missing in DTS. Adjust the trip points and add respective cooling nodes for each CPU thermal zone. The CPU throttling will start at 60 degrees of C, intensify at 80 degrees of C and slow down CPUs as much as possible at 110 degrees of C. With this configuration, when running four CPU intensive tasks, the temperatures did not exceed 90 degrees of Celsius mostly oscillating around 88 degrees in hottest thermal zone. Test was however done with only four CPUs online (big cluster, Cortex A15) because of errors when booting secondary CPUs. Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5420-arndale-octa.dts | 264 ++++++++++++++++++++++++++ 1 file changed, 264 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index 308c74ebeacd..889712481c95 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -59,6 +59,270 @@ cpu-supply = <&buck6_reg>; }; +&cpu0_thermal { + trips { + cpu0_alert0: cpu-alert-0 { + temperature = <60000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + cpu0_alert1: cpu-alert-1 { + temperature = <80000>; /* millicelsius */ + hysteresis = <10000>; /* millicelsius */ + type = "passive"; + }; + cpu0_alert2: cpu-alert-2 { + temperature = <110000>; /* millicelsius */ + hysteresis = <10000>; /* millicelsius */ + type = "passive"; + }; + cpu0_crit0: cpu-crit-0 { + temperature = <120000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + /* + * Reduce the CPU speed by 2 steps, down to: 1600 MHz + * and 1100 MHz. + */ + map0 { + trip = <&cpu0_alert0>; + cooling-device = <&cpu0 0 2>, + <&cpu1 0 2>, + <&cpu2 0 2>, + <&cpu3 0 2>, + <&cpu4 0 2>, + <&cpu5 0 2>, + <&cpu6 0 2>, + <&cpu7 0 2>; + }; + + /* + * Reduce the CPU speed down to 1200 MHz big (6 steps) + * and 800 MHz LITTLE (5 steps). + */ + map1 { + trip = <&cpu0_alert1>; + cooling-device = <&cpu0 3 6>, + <&cpu1 3 6>, + <&cpu2 3 6>, + <&cpu3 3 6>, + <&cpu4 3 5>, + <&cpu5 3 5>, + <&cpu6 3 5>, + <&cpu7 3 5>; + }; + + /* + * Reduce the CPU speed as much as possible, down to 700 MHz + * big (11 steps) and 600 MHz LITTLE (7 steps). + */ + map2 { + trip = <&cpu0_alert2>; + cooling-device = <&cpu0 6 11>, + <&cpu1 6 11>, + <&cpu2 6 11>, + <&cpu3 6 11>, + <&cpu4 5 7>, + <&cpu5 5 7>, + <&cpu6 5 7>, + <&cpu7 5 7>; + }; + }; +}; + +&cpu1_thermal { + trips { + cpu1_alert0: cpu-alert-0 { + temperature = <60000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + cpu1_alert1: cpu-alert-1 { + temperature = <80000>; /* millicelsius */ + hysteresis = <10000>; /* millicelsius */ + type = "passive"; + }; + cpu1_alert2: cpu-alert-2 { + temperature = <110000>; /* millicelsius */ + hysteresis = <10000>; /* millicelsius */ + type = "passive"; + }; + cpu1_crit0: cpu-crit-0 { + temperature = <120000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu1_alert0>; + cooling-device = <&cpu0 0 2>, + <&cpu1 0 2>, + <&cpu2 0 2>, + <&cpu3 0 2>, + <&cpu4 0 2>, + <&cpu5 0 2>, + <&cpu6 0 2>, + <&cpu7 0 2>; + }; + + map1 { + trip = <&cpu1_alert1>; + cooling-device = <&cpu0 3 6>, + <&cpu1 3 6>, + <&cpu2 3 6>, + <&cpu3 3 6>, + <&cpu4 3 5>, + <&cpu5 3 5>, + <&cpu6 3 5>, + <&cpu7 3 5>; + }; + + map2 { + trip = <&cpu1_alert2>; + cooling-device = <&cpu0 6 11>, + <&cpu1 6 11>, + <&cpu2 6 11>, + <&cpu3 6 11>, + <&cpu4 5 7>, + <&cpu5 5 7>, + <&cpu6 5 7>, + <&cpu7 5 7>; + }; + }; +}; + +&cpu2_thermal { + trips { + cpu2_alert0: cpu-alert-0 { + temperature = <60000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + cpu2_alert1: cpu-alert-1 { + temperature = <80000>; /* millicelsius */ + hysteresis = <10000>; /* millicelsius */ + type = "passive"; + }; + cpu2_alert2: cpu-alert-2 { + temperature = <110000>; /* millicelsius */ + hysteresis = <10000>; /* millicelsius */ + type = "passive"; + }; + cpu2_crit0: cpu-crit-0 { + temperature = <120000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu2_alert0>; + cooling-device = <&cpu0 0 2>, + <&cpu1 0 2>, + <&cpu2 0 2>, + <&cpu3 0 2>, + <&cpu4 0 2>, + <&cpu5 0 2>, + <&cpu6 0 2>, + <&cpu7 0 2>; + }; + + map1 { + trip = <&cpu2_alert1>; + cooling-device = <&cpu0 3 6>, + <&cpu1 3 6>, + <&cpu2 3 6>, + <&cpu3 3 6>, + <&cpu4 3 5>, + <&cpu5 3 5>, + <&cpu6 3 5>, + <&cpu7 3 5>; + }; + + map2 { + trip = <&cpu2_alert2>; + cooling-device = <&cpu0 6 11>, + <&cpu1 6 11>, + <&cpu2 6 11>, + <&cpu3 6 11>, + <&cpu4 6 7>, + <&cpu5 6 7>, + <&cpu6 6 7>, + <&cpu7 6 7>; + }; + }; +}; + +&cpu3_thermal { + trips { + cpu3_alert0: cpu-alert-0 { + temperature = <60000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + cpu3_alert1: cpu-alert-1 { + temperature = <80000>; /* millicelsius */ + hysteresis = <10000>; /* millicelsius */ + type = "passive"; + }; + cpu3_alert2: cpu-alert-2 { + temperature = <110000>; /* millicelsius */ + hysteresis = <10000>; /* millicelsius */ + type = "passive"; + }; + cpu3_crit0: cpu-crit-0 { + temperature = <120000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu3_alert0>; + cooling-device = <&cpu0 0 2>, + <&cpu1 0 2>, + <&cpu2 0 2>, + <&cpu3 0 2>, + <&cpu4 0 2>, + <&cpu5 0 2>, + <&cpu6 0 2>, + <&cpu7 0 2>; + }; + + map1 { + trip = <&cpu3_alert1>; + cooling-device = <&cpu0 3 6>, + <&cpu1 3 6>, + <&cpu2 3 6>, + <&cpu3 3 6>, + <&cpu4 3 5>, + <&cpu5 3 5>, + <&cpu6 3 5>, + <&cpu7 3 5>; + }; + + map2 { + trip = <&cpu3_alert2>; + cooling-device = <&cpu0 6 11>, + <&cpu1 6 11>, + <&cpu2 6 11>, + <&cpu3 6 11>, + <&cpu4 5 7>, + <&cpu5 5 7>, + <&cpu6 5 7>, + <&cpu7 5 7>; + }; + }; +}; + &usbdrd_dwc3_1 { dr_mode = "host"; }; -- cgit From eb1d0a50f74ce05a06ea150d8b677718f7390920 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 18 Feb 2019 20:48:41 +0100 Subject: ARM: dts: exynos: Order nodes alphabetically in Arndale Octa Having nodes and overrides-by-label ordered alphabetically reduces the possibility of conflicts from simultaneous edits. No functional change. Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5420-arndale-octa.dts | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index 889712481c95..0d4dbd4324a6 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -51,6 +51,10 @@ }; }; +&cci { + status = "disabled"; +}; + &cpu0 { cpu-supply = <&buck2_reg>; }; @@ -323,14 +327,6 @@ }; }; -&usbdrd_dwc3_1 { - dr_mode = "host"; -}; - -&cci { - status = "disabled"; -}; - &hdmi { hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; vdd_osc-supply = <&ldo7_reg>; @@ -724,3 +720,7 @@ clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; clock-names = "rtc", "rtc_src"; }; + +&usbdrd_dwc3_1 { + dr_mode = "host"; +}; -- cgit From 17c130a170f2b6a06b0ad88b6f564f5fe5a2cb79 Mon Sep 17 00:00:00 2001 From: Stuart Menefy Date: Tue, 19 Feb 2019 13:03:34 +0000 Subject: ARM: dts: exynos: Use bustop PLL as the source for MMC clocks on Exynos5260 By default the MMC clock will be derived from mediatop PLL, which usually runs at 666MHz. However as most SD and MMC clocks are multiples or fractions of 100MHz, it makes more sense to use the bustop PLL which runs at 800MHz. This matches the behaviour of the Samsung vendor supplied 3.4 kernel. Signed-off-by: Stuart Menefy Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5260.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi index 55167850619c..14b423de9137 100644 --- a/arch/arm/boot/dts/exynos5260.dtsi +++ b/arch/arm/boot/dts/exynos5260.dtsi @@ -288,6 +288,14 @@ #size-cells = <0>; clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>; clock-names = "biu", "ciu"; + assigned-clocks = + <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A>, + <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B>, + <&clock_top TOP_SCLK_MMC0>; + assigned-clock-parents = + <&clock_top TOP_MOUT_BUSTOP_PLL_USER>, + <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A>; + assigned-clock-rates = <0>, <0>, <800000000>; fifo-depth = <64>; status = "disabled"; }; @@ -300,6 +308,14 @@ #size-cells = <0>; clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>; clock-names = "biu", "ciu"; + assigned-clocks = + <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A>, + <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B>, + <&clock_top TOP_SCLK_MMC1>; + assigned-clock-parents = + <&clock_top TOP_MOUT_BUSTOP_PLL_USER>, + <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A>; + assigned-clock-rates = <0>, <0>, <800000000>; fifo-depth = <64>; status = "disabled"; }; @@ -312,6 +328,14 @@ #size-cells = <0>; clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>; clock-names = "biu", "ciu"; + assigned-clocks = + <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A>, + <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B>, + <&clock_top TOP_SCLK_MMC2>; + assigned-clock-parents = + <&clock_top TOP_MOUT_BUSTOP_PLL_USER>, + <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A>; + assigned-clock-rates = <0>, <0>, <800000000>; fifo-depth = <64>; status = "disabled"; }; -- cgit From c5432b1d44a787ae8e8d8097e05f7ed9cf563535 Mon Sep 17 00:00:00 2001 From: Stuart Menefy Date: Tue, 19 Feb 2019 13:03:35 +0000 Subject: ARM: dts: exynos: Add high speed I2C ports for Exynos5260 Most of the work to support the high speed I2C ports on the Exynos5260 was added in commit 218e1496135e ("i2c: exynos5: add support for HSI2C on Exynos5260 SoC") and the pinctrl nodes have always been available. All that is missing to get them working is the addition of the DT bindings. Signed-off-by: Stuart Menefy Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5260.dtsi | 56 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi index 14b423de9137..a8c7c6e589a0 100644 --- a/arch/arm/boot/dts/exynos5260.dtsi +++ b/arch/arm/boot/dts/exynos5260.dtsi @@ -17,6 +17,10 @@ #size-cells = <1>; aliases { + i2c0 = &hsi2c_0; + i2c1 = &hsi2c_1; + i2c2 = &hsi2c_2; + i2c3 = &hsi2c_3; pinctrl0 = &pinctrl_0; pinctrl1 = &pinctrl_1; pinctrl2 = &pinctrl_2; @@ -339,6 +343,58 @@ fifo-depth = <64>; status = "disabled"; }; + + hsi2c_0: hsi2c@12da0000 { + compatible = "samsung,exynos5260-hsi2c"; + reg = <0x12DA0000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_hs_bus>; + clocks = <&clock_peri PERI_CLK_HSIC0>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_1: hsi2c@12db0000 { + compatible = "samsung,exynos5260-hsi2c"; + reg = <0x12DB0000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_hs_bus>; + clocks = <&clock_peri PERI_CLK_HSIC1>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_2: hsi2c@12dc0000 { + compatible = "samsung,exynos5260-hsi2c"; + reg = <0x12DC0000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_hs_bus>; + clocks = <&clock_peri PERI_CLK_HSIC2>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_3: hsi2c@12dd0000 { + compatible = "samsung,exynos5260-hsi2c"; + reg = <0x12DD0000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_hs_bus>; + clocks = <&clock_peri PERI_CLK_HSIC3>; + clock-names = "hsi2c"; + status = "disabled"; + }; }; }; -- cgit From 7f396393b941e5594d927933175301d0db13f5a6 Mon Sep 17 00:00:00 2001 From: Stuart Menefy Date: Tue, 19 Feb 2019 13:03:36 +0000 Subject: ARM: dts: exynos: Add interrupts for dedicated EINTs on Exynos5260 Add the missing interrupt information for the GPIO lines with dedicated EINT interrupts. Signed-off-by: Stuart Menefy Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5260-pinctrl.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi index b1edb20b789e..17e2f3e0d71e 100644 --- a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi @@ -153,6 +153,14 @@ #gpio-cells = <2>; interrupt-controller; + interrupts = , + , + , + , + , + , + , + ; #interrupt-cells = <2>; }; @@ -161,6 +169,14 @@ #gpio-cells = <2>; interrupt-controller; + interrupts = , + , + , + , + , + , + , + ; #interrupt-cells = <2>; }; -- cgit From 99f698e268786da84dd49bd36176c6d27fa04894 Mon Sep 17 00:00:00 2001 From: Marco Felsch Date: Mon, 4 Feb 2019 16:29:55 +0100 Subject: ARM: dts: pfla02: prepare storage devices to add paritions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Partitions in the NOR and EEPROM are application specific. Prepare the SoM device tree so platform device tree's can add partitions. Signed-off-by: Marco Felsch Acked-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index 433bf09a1954..673711f445b6 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -79,7 +79,7 @@ status = "okay"; cs-gpios = <&gpio4 24 0>; - flash@0 { + som_flash: flash@0 { compatible = "m25p80", "jedec,spi-nor"; spi-max-frequency = <20000000>; reg = <0>; @@ -120,7 +120,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - eeprom@50 { + som_eeprom: eeprom@50 { compatible = "atmel,24c32"; reg = <0x50>; }; -- cgit From 8da0af5d6d39fa8d9f2e230045d93f2677ce089e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 13 Feb 2019 16:24:38 -0200 Subject: ARM: dts: vf610-zii: Disable SNVS RTC None of these vf610-zii boards have a battery or super-capacitor holding up power to the SNVS RTC embedded in the Vybrid SoC, so it is preferable to disable the snvsrtc node. Signed-off-by: Fabio Estevam Reviewed-by: Andrew Lunn Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-zii-cfu1.dts | 4 ++++ arch/arm/boot/dts/vf610-zii-scu4-aib.dts | 4 ++++ arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts | 4 ++++ arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts | 4 ++++ 4 files changed, 16 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/vf610-zii-cfu1.dts b/arch/arm/boot/dts/vf610-zii-cfu1.dts index 445c7dc306b2..440de578d8af 100644 --- a/arch/arm/boot/dts/vf610-zii-cfu1.dts +++ b/arch/arm/boot/dts/vf610-zii-cfu1.dts @@ -236,6 +236,10 @@ }; }; +&snvsrtc { + status = "disabled"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; diff --git a/arch/arm/boot/dts/vf610-zii-scu4-aib.dts b/arch/arm/boot/dts/vf610-zii-scu4-aib.dts index de6dfa57bec5..e3952e9ea0db 100644 --- a/arch/arm/boot/dts/vf610-zii-scu4-aib.dts +++ b/arch/arm/boot/dts/vf610-zii-scu4-aib.dts @@ -671,6 +671,10 @@ }; }; +&snvsrtc { + status = "disabled"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts b/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts index 2b10672fadbd..60dad9c228a9 100644 --- a/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts +++ b/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts @@ -211,6 +211,10 @@ }; }; +&snvsrtc { + status = "disabled"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts index 0d9fe5ac83a3..6df3ef979eb0 100644 --- a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts +++ b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts @@ -219,6 +219,10 @@ }; }; +&snvsrtc { + status = "disabled"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; -- cgit From 96d861c2fd40529ab122626ac27f00722760d800 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 13 Feb 2019 16:24:39 -0200 Subject: ARM: dts: vf610-zii-ssmb-spu3: Disable watchdog On vf610-zii-ssmb-spu3 board there is a supervisory microcontroller that provides the watchdog functionality, so disable the on-chip Vybrid's watchdog. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts index 6df3ef979eb0..2a392e2444ff 100644 --- a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts +++ b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts @@ -254,6 +254,10 @@ }; }; +&wdoga5 { + status = "disabled"; +}; + &iomuxc { pinctrl_dspi1: dspi1grp { fsl,pins = < -- cgit From 3117e851cef1b4e1b4454d3d223a43ccbf3eee20 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 1 Mar 2019 08:28:03 -0800 Subject: ARM: dts: imx: Add TDA19971 HDMI Receiver to GW551x The GW551x has a front-panel microHDMI connector routed to a TDA19971 which is connected the the IPU CSI. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-gw551x.dtsi | 138 ++++++++++++++++++++++++++++++++++ 1 file changed, 138 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi index 8e46a80f57a4..c23ba229fd05 100644 --- a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi @@ -46,6 +46,8 @@ */ #include +#include +#include / { /* these are used by bootloader for disabling nodes */ @@ -99,6 +101,50 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; + + sound-digital { + compatible = "simple-audio-card"; + simple-audio-card,name = "tda1997x-audio"; + + simple-audio-card,dai-link@0 { + format = "i2s"; + + cpu { + sound-dai = <&ssi2>; + }; + + codec { + bitclock-master; + frame-master; + sound-dai = <&hdmi_receiver>; + }; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; /* AUD5<->tda1997x */ + status = "okay"; + + ssi1 { + fsl,audmux-port = <0>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */ + IMX_AUDMUX_V2_PTCR_TCLKDIR | + IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */ + IMX_AUDMUX_V2_PTCR_SYN) + IMX_AUDMUX_V2_PDCR_RXDSEL(4) + >; + }; + + aud5 { + fsl,audmux-port = <4>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(0)>; + }; }; &can1 { @@ -264,6 +310,60 @@ #gpio-cells = <2>; }; + hdmi_receiver: hdmi-receiver@48 { + compatible = "nxp,tda19971"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tda1997x>; + reg = <0x48>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + DOVDD-supply = <®_3p3>; + AVDD-supply = <®_1p8b>; + DVDD-supply = <®_1p8a>; + #sound-dai-cells = <0>; + nxp,audout-format = "i2s"; + nxp,audout-layout = <0>; + nxp,audout-width = <16>; + nxp,audout-mclk-fs = <128>; + /* + * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4] + * and Y[11:4] across 16bits in the same cycle + * which we map to VP[15:08]<->CSI_DATA[19:12] + */ + nxp,vidout-portcfg = + /*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/ + < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >, + /*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/ + < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >, + /*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/ + < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >, + /*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/ + < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >; + + port { + tda1997x_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + bus-width = <16>; + hsync-active = <1>; + vsync-active = <1>; + data-active = <1>; + }; + }; + }; +}; + +&ipu1_csi0_from_ipu1_csi0_mux { + bus-width = <16>; +}; + +&ipu1_csi0_mux_from_parallel_sensor { + remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>; + bus-width = <16>; +}; + +&ipu1_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0>; }; &pcie { @@ -321,6 +421,14 @@ }; &iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 + MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x130b0 + MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x130b0 + >; + }; + pinctrl_flexcan1: flexcan1grp { fsl,pins = < MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 @@ -376,6 +484,30 @@ >; }; + pinctrl_ipu1_csi0: ipu1_csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x1b0b0 + MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x1b0b0 + MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x1b0b0 + MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x1b0b0 + MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x1b0b0 + MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x1b0b0 + MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x1b0b0 + MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x1b0b0 + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 + >; + }; + pinctrl_pcie: pciegrp { fsl,pins = < MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */ @@ -400,6 +532,12 @@ >; }; + pinctrl_tda1997x: tda1997xgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 -- cgit From 7d1446688d2d0c9235d0cd0890db1bb8c173568d Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 1 Mar 2019 08:32:53 -0800 Subject: ARM: dts: imx: Add TDA19971 HDMI Receiver to GW54xx The GW54xx has a front-panel microHDMI connector routed to a TDA19971 which is connected the the IPU CSI when using IMX6Q. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-gw54xx.dts | 105 ++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 29 +++++++++- 2 files changed, 131 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6q-gw54xx.dts b/arch/arm/boot/dts/imx6q-gw54xx.dts index 56e5b5050fcf..cb0a5f7d5a19 100644 --- a/arch/arm/boot/dts/imx6q-gw54xx.dts +++ b/arch/arm/boot/dts/imx6q-gw54xx.dts @@ -12,10 +12,30 @@ /dts-v1/; #include "imx6q.dtsi" #include "imx6qdl-gw54xx.dtsi" +#include / { model = "Gateworks Ventana i.MX6 Dual/Quad GW54XX"; compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q"; + + sound-digital { + compatible = "simple-audio-card"; + simple-audio-card,name = "tda1997x-audio"; + + simple-audio-card,dai-link@0 { + format = "i2s"; + + cpu { + sound-dai = <&ssi2>; + }; + + codec { + bitclock-master; + frame-master; + sound-dai = <&hdmi_receiver>; + }; + }; + }; }; &i2c3 { @@ -35,6 +55,61 @@ }; }; }; + + hdmi_receiver: hdmi-receiver@48 { + compatible = "nxp,tda19971"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tda1997x>; + reg = <0x48>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + DOVDD-supply = <®_3p3v>; + AVDD-supply = <&sw4_reg>; + DVDD-supply = <&sw4_reg>; + #sound-dai-cells = <0>; + nxp,audout-format = "i2s"; + nxp,audout-layout = <0>; + nxp,audout-width = <16>; + nxp,audout-mclk-fs = <128>; + /* + * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4] + * and Y[11:4] across 16bits in the same cycle + * which we map to VP[15:08]<->CSI_DATA[19:12] + */ + nxp,vidout-portcfg = + /*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/ + < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >, + /*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/ + < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >, + /*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/ + < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >, + /*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/ + < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >; + + port { + tda1997x_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + bus-width = <16>; + hsync-active = <1>; + vsync-active = <1>; + data-active = <1>; + }; + }; + }; +}; + +&ipu1_csi0_from_ipu1_csi0_mux { + bus-width = <16>; +}; + +&ipu1_csi0_mux_from_parallel_sensor { + remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>; + bus-width = <16>; +}; + +&ipu1_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0>; }; &ipu2_csi1_from_ipu2_csi1_mux { @@ -63,6 +138,30 @@ >; }; + pinctrl_ipu1_csi0: ipu1_csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x1b0b0 + MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x1b0b0 + MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x1b0b0 + MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x1b0b0 + MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x1b0b0 + MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x1b0b0 + MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x1b0b0 + MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x1b0b0 + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 + >; + }; + pinctrl_ipu2_csi1: ipu2_csi1grp { fsl,pins = < MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0 @@ -78,4 +177,10 @@ MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0 >; }; + + pinctrl_tda1997x: tda1997xgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 + >; + }; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index 81b2fcf6eedf..e4d1c5250d1e 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -10,6 +10,7 @@ */ #include +#include / { /* these are used by bootloader for disabling nodes */ @@ -115,12 +116,12 @@ }; }; - sound { + sound-analog { compatible = "fsl,imx6q-ventana-sgtl5000", "fsl,imx-audio-sgtl5000"; model = "sgtl5000-audio"; ssi-controller = <&ssi1>; - audio-codec = <&codec>; + audio-codec = <&sgtl5000>; audio-routing = "MIC_IN", "Mic Jack", "Mic Jack", "Mic Bias", @@ -134,6 +135,25 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */ status = "okay"; + + ssi2 { + fsl,audmux-port = <1>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */ + IMX_AUDMUX_V2_PTCR_TCLKDIR | + IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */ + IMX_AUDMUX_V2_PTCR_SYN) + IMX_AUDMUX_V2_PDCR_RXDSEL(4) + >; + }; + + aud5 { + fsl,audmux-port = <4>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(1)>; + }; }; &can1 { @@ -332,7 +352,7 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - codec: sgtl5000@a { + sgtl5000: audio-codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; @@ -476,6 +496,9 @@ MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ + MX6QDL_PAD_EIM_D25__AUD5_RXC 0x130b0 + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 + MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x130b0 >; }; -- cgit From 54f6deafd27db3d14ddd75771dbdc5297a24863e Mon Sep 17 00:00:00 2001 From: Yinbo Zhu Date: Tue, 26 Feb 2019 08:40:22 +0000 Subject: ARM: dts: ls1021a-qds: enable esdhc controller This patch is to enable esdhc controller in ls1021aqds Signed-off-by: Yinbo Zhu Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a-qds.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts index ca60730dda40..74a67604876c 100644 --- a/arch/arm/boot/dts/ls1021a-qds.dts +++ b/arch/arm/boot/dts/ls1021a-qds.dts @@ -146,6 +146,10 @@ status = "okay"; }; +&esdhc { + status = "okay"; +}; + &i2c0 { status = "okay"; -- cgit From 72cd625c85e2681bad718b5218bf672d7fa5af80 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 4 Mar 2019 20:59:58 +0100 Subject: ARM: dts: r8a7792: blanche: Add IIC3 and DA9063 PMIC node Add IIC3 node to R8A7792 SoC device tree and a DA9063 PMIC node to V2H Blanche board device tree. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792-blanche.dts | 20 ++++++++++++++++++++ arch/arm/boot/dts/r8a7792.dtsi | 18 ++++++++++++++++++ 2 files changed, 38 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts index f92301290b02..b6fa80c3b07e 100644 --- a/arch/arm/boot/dts/r8a7792-blanche.dts +++ b/arch/arm/boot/dts/r8a7792-blanche.dts @@ -308,6 +308,26 @@ }; }; +&iic3 { + status = "okay"; + + pmic@58 { + compatible = "dlg,da9063"; + reg = <0x58>; + interrupt-parent = <&irqc>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + + rtc { + compatible = "dlg,da9063-rtc"; + }; + + wdt { + compatible = "dlg,da9063-watchdog"; + }; + }; +}; + &du { pinctrl-0 = <&du0_pins &du1_pins>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 8e9eb4b704d3..38fb43d11b27 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -22,6 +22,7 @@ i2c3 = &i2c3; i2c4 = &i2c4; i2c5 = &i2c5; + i2c6 = &iic3; spi0 = &qspi; spi1 = &msiof0; spi2 = &msiof1; @@ -444,6 +445,23 @@ status = "disabled"; }; + iic3: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7792", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 926>; + dmas = <&dmac0 0x77>, <&dmac0 0x78>, + <&dmac1 0x77>, <&dmac1 0x78>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 926>; + status = "disabled"; + }; + dmac0: dma-controller@e6700000 { compatible = "renesas,dmac-r8a7792", "renesas,rcar-dmac"; -- cgit From a8d5fc0be537d49562f3d4b63390584e304ec8dc Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 3 Mar 2019 20:00:59 +0100 Subject: ARM: dts: alt: Add DA9063 PMIC node Add DA9063 PMIC node to the I2C bus. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794-alt.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts index ef7e2a837df6..e0500ec81569 100644 --- a/arch/arm/boot/dts/r8a7794-alt.dts +++ b/arch/arm/boot/dts/r8a7794-alt.dts @@ -377,6 +377,27 @@ pinctrl-names = "i2c-exio4"; }; +&i2c7 { + status = "okay"; + clock-frequency = <100000>; + + pmic@58 { + compatible = "dlg,da9063"; + reg = <0x58>; + interrupt-parent = <&gpio3>; + interrupts = <31 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + + rtc { + compatible = "dlg,da9063-rtc"; + }; + + wdt { + compatible = "dlg,da9063-watchdog"; + }; + }; +}; + &vin0 { status = "okay"; pinctrl-0 = <&vin0_pins>; -- cgit From b7ed69d67ff0788d8463e599dd5dd1b45c701a7e Mon Sep 17 00:00:00 2001 From: Stuart Menefy Date: Tue, 19 Feb 2019 13:03:37 +0000 Subject: ARM: dts: exynos: Fix interrupt for shared EINTs on Exynos5260 Fix the interrupt information for the GPIO lines with a shared EINT interrupt. Fixes: 16d7ff2642e7 ("ARM: dts: add dts files for exynos5260 SoC") Cc: stable@vger.kernel.org Signed-off-by: Stuart Menefy Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5260.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi index a8c7c6e589a0..3581b57fbbf7 100644 --- a/arch/arm/boot/dts/exynos5260.dtsi +++ b/arch/arm/boot/dts/exynos5260.dtsi @@ -227,7 +227,7 @@ wakeup-interrupt-controller { compatible = "samsung,exynos4210-wakeup-eint"; interrupt-parent = <&gic>; - interrupts = ; + interrupts = ; }; }; -- cgit From 23c856787a80efd475c0d82c6e49a65c73561816 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 23 Feb 2019 21:29:32 +0100 Subject: ARM: dts: exynos: Enable ADC on Arndale Octa Arndale Octa (Exynos5420) has two ADC pins (AIN0 and AIN1) exposed on CON6 header pins. Add ADC node to DTS file to enable it. Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5420-arndale-octa.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index 0d4dbd4324a6..d3e024560db4 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -51,6 +51,11 @@ }; }; +&adc { + vdd-supply = <&ldo4_reg>; + status = "okay"; +}; + &cci { status = "disabled"; }; -- cgit From 34dc82257488ccbdfb6ecdd087b3c8b371e03ee3 Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki Date: Wed, 6 Mar 2019 11:40:56 +0100 Subject: ARM: dts: exynos: Fix audio routing on Odroid XU3 Add missing audio routing entry for the capture stream, this change is required to fix audio recording on Odroid XU3/XU3-Lite. Fixes: 885b005d232c ("ARM: dts: exynos: Add support for secondary DAI to Odroid XU3") Cc: stable@vger.kernel.org Signed-off-by: Sylwester Nawrocki Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi index 51a843bd65ed..3a37267e6134 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi @@ -26,7 +26,8 @@ "Speakers", "SPKL", "Speakers", "SPKR", "I2S Playback", "Mixer DAI TX", - "HiFi Playback", "Mixer DAI TX"; + "HiFi Playback", "Mixer DAI TX", + "Mixer DAI RX", "HiFi Capture"; assigned-clocks = <&clock CLK_MOUT_EPLL>, <&clock CLK_MOUT_MAU_EPLL>, -- cgit From 30082e7b3513ff6e8a6d5e97d72af7074bb767ee Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 9 Mar 2019 16:00:37 +0100 Subject: ARM: dts: exynos: Adjust ldo23 and ldo27 to lower levels on Arndale Octa Although on the schematics of Insignal Arndale Octa board the PVDD_MIFS_1V1 (ldo23) and PVDD_G3DS_1V0 (ldo27) are marked as 1.2 V, the vendor v3.4 Android kernel sets them lower. Also name suggests that they should work on 1.1 V and 1.0 V respectively, not 1.2 V. Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5420-arndale-octa.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index d3e024560db4..b12286d545b6 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -504,8 +504,8 @@ ldo23_reg: LDO23 { regulator-name = "PVDD_MIFS_1V1"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; regulator-always-on; }; @@ -530,8 +530,8 @@ ldo27_reg: LDO27 { regulator-name = "PVDD_G3DS_1V0"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; }; ldo28_reg: LDO28 { -- cgit From 3a6a6d0a8b660c9a075c981e40405cc67b145972 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 9 Mar 2019 16:00:38 +0100 Subject: ARM: dts: exynos: Add support for UHS-I SD cards on Arndale Octa The Exynos5420's Mobile Storage Host supports SD cards in UHS-I standard (SD specification v3.0), with 1.8 V signaling in SD UHS DDR50. Adjust the regulator and add necessary capability properties. Change the SDR and DDR timings to match values in Insignal v3.4 Android kernel. Tested with SD UHS-I card in SD UHS DDR50 mode. Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5420-arndale-octa.dts | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index b12286d545b6..de0a6840dfbc 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -441,7 +441,7 @@ ldo13_reg: LDO13 { regulator-name = "PVDD_APIO_MMCOFF_2V8"; - regulator-min-microvolt = <2800000>; + regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2800000>; }; @@ -701,14 +701,17 @@ status = "okay"; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; pinctrl-names = "default"; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; vmmc-supply = <&ldo19_reg>; vqmmc-supply = <&ldo13_reg>; bus-width = <4>; cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + sd-uhs-ddr50; }; &pinctrl_0 { -- cgit From 9a435fb2291d583ae012d4e853bd9987b367bba1 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 9 Mar 2019 16:00:39 +0100 Subject: ARM: dts: exynos: Extend the eMMC node on Arndale Octa Describe properly the MMC0 node (with attached embedded MMC memory) on Arndale Octa by: 1. Adding the regulator for host interface (although it still has to be "always-on" so the board with Linaro U-Boot will boot properly); 2. Using "non-removable" instead of "broken-cd" property, because eMMC is embedded into the board; 3. Adding support for HS200 v1.8 to indicate such support in host controller although this has no practical effect (embedded memory does not support it). Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5420-arndale-octa.dts | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index de0a6840dfbc..74184c6ce3bf 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -378,6 +378,12 @@ regulator-name = "PVDD_APIO_MMCON_1V8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + /* + * Must be always on, even though there is + * a consumer (mmc_0). Otherwise the board + * does not reboot with vendor U-Boot + * (Linaro for Arndale Octa, v2012.07). + */ regulator-always-on; }; @@ -685,7 +691,7 @@ &mmc_0 { status = "okay"; - broken-cd; + non-removable; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; @@ -693,8 +699,10 @@ pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; vmmc-supply = <&ldo10_reg>; + vqmmc-supply = <&ldo3_reg>; bus-width = <8>; cap-mmc-highspeed; + mmc-hs200-1_8v; }; &mmc_2 { -- cgit From 5ab99cf7d5e96e3b727c30e7a8524c976bd3723d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 14 Mar 2019 21:02:17 +0100 Subject: ARM: dts: exynos: Always enable necessary APIO_1V8 and ABB_1V8 regulators on Arndale Octa The PVDD_APIO_1V8 (LDO2) and PVDD_ABB_1V8 (LDO8) regulators were turned off by Linux kernel as unused. However they supply critical parts of SoC so they should be always on: 1. PVDD_APIO_1V8 supplies SYS pins (gpx[0-3], PSHOLD), HDMI level shift, RTC, VDD1_12 (DRAM internal 1.8 V logic), pull-up for PMIC interrupt lines, TTL/UARTR level shift, reset pins and SW-TACT1 button. It also supplies unused blocks like VDDQ_SRAM (for SROM controller) and VDDQ_GPIO (gpm7, gpy7). The LDO2 cannot be turned off (S2MPS11 keeps it on anyway) so marking it "always-on" only reflects its real status. 2. PVDD_ABB_1V8 supplies Adaptive Body Bias Generator for ARM cores, memory and Mali (G3D). Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5420-arndale-octa.dts | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index 74184c6ce3bf..dbf0306896f6 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -372,6 +372,7 @@ regulator-name = "PVDD_APIO_1V8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-always-on; }; ldo3_reg: LDO3 { @@ -416,6 +417,7 @@ regulator-name = "PVDD_ABB_1V8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-always-on; }; ldo9_reg: LDO9 { -- cgit From d058ad0e3856578a9821330edc583cc4349b179d Mon Sep 17 00:00:00 2001 From: Pierre-Jean Texier Date: Sat, 2 Mar 2019 23:32:29 +0100 Subject: ARM: dts: imx7s-warp: PMIC swbst boot-on/always-on PMIC swbst regulator is used for the MikroBUS socket (pin +5V). We have to set the regulator to "boot-on" and "always-on" to output a voltage of 5V on this socket. Signed-off-by: Pierre-Jean Texier Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s-warp.dts | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts index 23431faecaf4..b1e956205e9a 100644 --- a/arch/arm/boot/dts/imx7s-warp.dts +++ b/arch/arm/boot/dts/imx7s-warp.dts @@ -121,6 +121,8 @@ swbst_reg: swbst { regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5150000>; + regulator-boot-on; + regulator-always-on; }; snvs_reg: vsnvs { -- cgit From 574e852f99c36ea867f621b748771d4d8b3c3f98 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Wed, 6 Mar 2019 14:12:47 +0100 Subject: ARM: dts: imx6: RDU2: add switch watchdog device This adds the i2c device node for the ethernet switch watchdog. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi index 69942c7ff89d..7f920e0243ec 100644 --- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi @@ -528,6 +528,11 @@ }; }; + watchdog@38 { + compatible = "zii,rave-wdt"; + reg = <0x38>; + }; + temp-sense@48 { compatible = "national,lm75"; reg = <0x48>; -- cgit From 5252414f7c15c2857d34c093d19ddb3171ac73d0 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Wed, 6 Mar 2019 14:12:48 +0100 Subject: ARM: dts: imx6: RDU2: manage backlight from panel Now that the backlight driver is upstream, we can properly manage the backlight from the panel. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi index 7f920e0243ec..9f664897bf4e 100644 --- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi @@ -210,6 +210,7 @@ panel { power-supply = <®_3p3v_display>; + backlight = <&sp_backlight>; status = "disabled"; port { @@ -327,7 +328,7 @@ compatible = "zii,rave-sp-watchdog"; }; - backlight { + sp_backlight: backlight { compatible = "zii,rave-sp-backlight"; }; -- cgit From 768b525edb4a7ddd6f3f05dada9582b8281c734a Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Thu, 7 Mar 2019 19:01:48 -0600 Subject: ARM: dts: imx6qdl: Enable fsl,sec-v4.0-pwrkey The imx6q Technical reference manual shows the interrupt is available to wake from sleep using the power button. The driver has been available for quite some time, and other variants of the i.MX6 have it enabled, so this implements it much like the others. Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index fe17a3405edc..6b3e48d2e5ec 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -4,6 +4,7 @@ // Copyright 2011 Linaro Ltd. #include +#include #include / { @@ -833,6 +834,14 @@ status = "disabled"; }; + snvs_pwrkey: snvs-powerkey { + compatible = "fsl,sec-v4.0-pwrkey"; + regmap = <&snvs>; + interrupts = ; + linux,keycode = ; + wakeup-source; + }; + snvs_lpgpr: snvs-lpgpr { compatible = "fsl,imx6q-snvs-lpgpr"; }; -- cgit From 9b23e1a3e8fde76e8cc0e366ab1ed4ffb4440feb Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki Date: Wed, 20 Mar 2019 10:59:50 +0100 Subject: ARM: dts: exynos: Fix audio (microphone) routing on Odroid XU3 The name of CODEC input widget to which microphone is connected through the "Headphone" jack is "IN12" not "IN1". This fixes microphone support on Odroid XU3. Cc: # v4.14+ Signed-off-by: Sylwester Nawrocki Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi index 3a37267e6134..c3c2d85267da 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi @@ -22,7 +22,7 @@ "Headphone Jack", "HPL", "Headphone Jack", "HPR", "Headphone Jack", "MICBIAS", - "IN1", "Headphone Jack", + "IN12", "Headphone Jack", "Speakers", "SPKL", "Speakers", "SPKR", "I2S Playback", "Mixer DAI TX", -- cgit From 10ee87d19a5d48cead4ccbe0a2a64956f766ec5c Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Tue, 12 Mar 2019 02:24:12 +0000 Subject: ARM: dts: imx7ulp: add mmdc support i.MX7ULP has a MMDC module to control DDR, it reuses i.MX6Q's MMDC module, add support for it. Signed-off-by: Anson Huang Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7ulp.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi index fca6e50f37c8..eb349fd7f6e4 100644 --- a/arch/arm/boot/dts/imx7ulp.dtsi +++ b/arch/arm/boot/dts/imx7ulp.dtsi @@ -286,6 +286,12 @@ status = "disabled"; }; + memory-controller@40ab0000 { + compatible = "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc"; + reg = <0x40ab0000 0x1000>; + clocks = <&pcc3 IMX7ULP_CLK_MMDC>; + }; + iomuxc1: pinctrl@40ac0000 { compatible = "fsl,imx7ulp-iomuxc1"; reg = <0x40ac0000 0x1000>; -- cgit From 476f6e53a0d0e41697ef611fd28b4a8f6b6711e5 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Tue, 12 Mar 2019 02:24:16 +0000 Subject: ARM: dts: imx: make MMDC node name generic Node name should be generic, so use "memory-controller" instead of "mmdc" for MMDC node name, also remove "mmdc" label for platforms with single MMDC node. Signed-off-by: Anson Huang Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 4 ++-- arch/arm/boot/dts/imx6sl.dtsi | 2 +- arch/arm/boot/dts/imx6sx.dtsi | 2 +- arch/arm/boot/dts/imx6ul.dtsi | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 6b3e48d2e5ec..883e2ff68106 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -1138,13 +1138,13 @@ reg = <0x021ac000 0x4000>; }; - mmdc0: mmdc@21b0000 { /* MMDC0 */ + mmdc0: memory-controller@21b0000 { /* MMDC0 */ compatible = "fsl,imx6q-mmdc"; reg = <0x021b0000 0x4000>; clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>; }; - mmdc1: mmdc@21b4000 { /* MMDC1 */ + mmdc1: memory-controller@21b4000 { /* MMDC1 */ reg = <0x021b4000 0x4000>; }; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 4b4813f176cd..733ea50fc8e3 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -922,7 +922,7 @@ status = "disabled"; }; - mmdc: mmdc@21b0000 { + memory-controller@21b0000 { compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc"; reg = <0x021b0000 0x4000>; clocks = <&clks IMX6SL_CLK_MMDC_P0_IPG>; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 5b16e65f7696..df0c59519886 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -1017,7 +1017,7 @@ status = "disabled"; }; - mmdc: mmdc@21b0000 { + memory-controller@21b0000 { compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc"; reg = <0x021b0000 0x4000>; clocks = <&clks IMX6SX_CLK_MMDC_P0_IPG>; diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index 62ed30c781ed..a77bbcae4571 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -914,7 +914,7 @@ status = "disabled"; }; - mmdc: mmdc@21b0000 { + memory-controller@21b0000 { compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc"; reg = <0x021b0000 0x4000>; clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>; -- cgit From 3a1a67b1ca7b5402e72de48fd63a88ddd4ef2cf8 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Tue, 12 Mar 2019 02:24:20 +0000 Subject: ARM: dts: imx6qdl: Improve mmdc1 node Add MMDC1 compatible string which is missing, and also set it to be disabled by default, as most of the platforms ONLY use single channel MMDC0, if dual MMDC channels are used, it can be enabled in board dts file. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 883e2ff68106..2eb4c779298b 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -1145,7 +1145,9 @@ }; mmdc1: memory-controller@21b4000 { /* MMDC1 */ + compatible = "fsl,imx6q-mmdc"; reg = <0x021b4000 0x4000>; + status = "disabled"; }; weim: weim@21b8000 { -- cgit From f7a6f5f3bb7bd1dca1950c4910e450e9a45c9caa Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 12 Mar 2019 10:19:23 -0300 Subject: ARM: dts: vf610-zii: Remove 'max-brightness' property The 'max-brightness' property is not a valid one as per Documentation/devicetree/bindings/leds/leds-gpio.txt, so remove it. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-zii-cfu1.dts | 5 ----- arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts | 1 - arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts | 1 - 3 files changed, 7 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/vf610-zii-cfu1.dts b/arch/arm/boot/dts/vf610-zii-cfu1.dts index 440de578d8af..6c78122401a1 100644 --- a/arch/arm/boot/dts/vf610-zii-cfu1.dts +++ b/arch/arm/boot/dts/vf610-zii-cfu1.dts @@ -29,35 +29,30 @@ label = "zii:green:debug1"; gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; - max-brightness = <1>; }; led-fail { label = "zii:red:fail"; gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; default-state = "off"; - max-brightness = <1>; }; led-status { label = "zii:green:status"; gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; default-state = "off"; - max-brightness = <1>; }; led-debug-a { label = "zii:green:debug_a"; gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; default-state = "off"; - max-brightness = <1>; }; led-debug-b { label = "zii:green:debug_b"; gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; default-state = "off"; - max-brightness = <1>; }; }; diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts b/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts index 60dad9c228a9..847c5858fea1 100644 --- a/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts +++ b/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts @@ -37,7 +37,6 @@ label = "zii:green:debug1"; gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; - max-brightness = <1>; }; }; diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts index 2a392e2444ff..8366bae632d6 100644 --- a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts +++ b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts @@ -37,7 +37,6 @@ label = "zii:green:debug1"; gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; - max-brightness = <1>; }; }; -- cgit From 152d58234ef41c586e7b268ceea691dc80130a59 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 18 Mar 2019 15:33:54 +0800 Subject: ARM: dts: sunxi: h3/h5: Add device node for SID The device tree binding already lists compatible strings for these two SoCs. Add a device node for them. Acked-by: Maxime Ripard Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-h3.dtsi | 4 ++++ arch/arm/boot/dts/sunxi-h3-h5.dtsi | 5 +++++ 2 files changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 959d265e7254..e37c30e811d3 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -231,3 +231,7 @@ &rtc { compatible = "allwinner,sun8i-h3-rtc"; }; + +&sid { + compatible = "allwinner,sun8i-h3-sid"; +}; diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index d74a6cbbfdf4..395521e83ee7 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -227,6 +227,11 @@ #size-cells = <0>; }; + sid: eeprom@1c14000 { + /* compatible is in per SoC .dtsi file */ + reg = <0x1c14000 0x400>; + }; + usb_otg: usb@1c19000 { compatible = "allwinner,sun8i-h3-musb"; reg = <0x01c19000 0x400>; -- cgit From a2b2012eab25aad00a7dd587d1754115491e59eb Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Wed, 20 Mar 2019 13:13:59 -0700 Subject: ARM: dts: rockchip: Fix gic/efuse sort ordering for rk3288 It can be seen that 0xffb40000 < 0xffc01000, thus efuse comes first. Signed-off-by: Douglas Anderson Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288.dtsi | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index b577f3e41811..743a7d85daf7 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -1379,19 +1379,6 @@ reg = <0x0 0xffaf0080 0x0 0x20>; }; - gic: interrupt-controller@ffc01000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - - reg = <0x0 0xffc01000 0x0 0x1000>, - <0x0 0xffc02000 0x0 0x2000>, - <0x0 0xffc04000 0x0 0x2000>, - <0x0 0xffc06000 0x0 0x2000>; - interrupts = ; - }; - efuse: efuse@ffb40000 { compatible = "rockchip,rk3288-efuse"; reg = <0x0 0xffb40000 0x0 0x20>; @@ -1405,6 +1392,19 @@ }; }; + gic: interrupt-controller@ffc01000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + + reg = <0x0 0xffc01000 0x0 0x1000>, + <0x0 0xffc02000 0x0 0x2000>, + <0x0 0xffc04000 0x0 0x2000>, + <0x0 0xffc06000 0x0 0x2000>; + interrupts = ; + }; + pinctrl: pinctrl { compatible = "rockchip,rk3288-pinctrl"; rockchip,grf = <&grf>; -- cgit From 17808d445b6f32201ebf2f5f4860d8b6fd6c1dab Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Tue, 5 Feb 2019 16:32:47 -0600 Subject: ARM: dts: socfpga: enable MMC highspeed support Add 'cap-mmc-highspeed' property to enable high-speed support for MMC cards. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts index df2bab1624d4..64dc0799f3d7 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts +++ b/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts @@ -9,6 +9,7 @@ &mmc { status = "okay"; cap-sd-highspeed; + cap-mmc-highspeed; broken-cd; bus-width = <4>; }; -- cgit From ad8c096a84a7335ab90f708edea9892f6d88b7b2 Mon Sep 17 00:00:00 2001 From: Alexander Kurz Date: Fri, 15 Mar 2019 21:14:21 +0000 Subject: ARM: dts: i.MX50: Add i2c, mmc and spi aliases Using aliases, the devices will be enumerated properly. Signed-off-by: Alexander Kurz Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx50.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index ee1e3e8bf4ec..9fb22b16159c 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -26,11 +26,21 @@ gpio3 = &gpio4; gpio4 = &gpio5; gpio5 = &gpio6; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + mmc0 = &esdhc1; + mmc1 = &esdhc2; + mmc2 = &esdhc3; + mmc3 = &esdhc4; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; serial3 = &uart4; serial4 = &uart5; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi2 = &cspi; }; cpus { -- cgit From 5da7f749aec3ad637f33934386d0265bc3ee919f Mon Sep 17 00:00:00 2001 From: Alexander Kurz Date: Fri, 15 Mar 2019 21:14:22 +0000 Subject: ARM: dts: i.MX6SL: Add i2c and mmc aliases Using aliases, the devices will be enumerated properly. Signed-off-by: Alexander Kurz Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 733ea50fc8e3..0ad5d507abec 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -23,6 +23,13 @@ gpio2 = &gpio3; gpio3 = &gpio4; gpio4 = &gpio5; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + mmc3 = &usdhc4; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; -- cgit From 67814a9b1b3bb312b31e7da181d488191b4115b6 Mon Sep 17 00:00:00 2001 From: Alexander Kurz Date: Fri, 15 Mar 2019 21:14:23 +0000 Subject: ARM: dts: i.MX35: Add i2c and mmc aliases Using aliases, the devices will be enumerated properly. Signed-off-by: Alexander Kurz Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx35.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi index 59cadeee23ed..9cbdc1a15cda 100644 --- a/arch/arm/boot/dts/imx35.dtsi +++ b/arch/arm/boot/dts/imx35.dtsi @@ -21,6 +21,12 @@ gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + mmc0 = &esdhc1; + mmc1 = &esdhc2; + mmc2 = &esdhc3; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; -- cgit From aed609c40c6f676354bd7cf23a51339e7adc3c4c Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Tue, 19 Mar 2019 16:24:18 +0100 Subject: ARM: dts: imx50: Add PHY node for usbotg and adjust clocks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Even though the ChipIdea USB controller binding[1] doesn't specify the properties that reference a PHY as required, the Linux driver requires[2] such a reference. The clock situation is like on i.MX53: The USB controller is clocked from IMX5_CLK_USBOH3_GATE and the PHY from IMX5_CLK_USB_PHY1_GATE. [1]: Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt [2]: Search for EINVAL in drivers/usb/chipidea/ci_hdrc_imx.c Signed-off-by: Jonathan Neuschäfer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx50.dtsi | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index 9fb22b16159c..5dd61bff3b76 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -86,6 +86,14 @@ }; }; + usbphy0: usbphy-0 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; + clock-names = "main_clk"; + #phy-cells = <0>; + status = "okay"; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -197,7 +205,8 @@ compatible = "fsl,imx50-usb", "fsl,imx27-usb"; reg = <0x53f80000 0x0200>; interrupts = <18>; - clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; + fsl,usbphy = <&usbphy0>; status = "disabled"; }; -- cgit From 26d459398a7ced52ff640bc1cf1cf6fc3f4b5fc8 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Wed, 20 Mar 2019 14:38:02 +0000 Subject: ARM: dts: ls1021a: Remove unused properties from QSPI node After switching to the new FSL QSPI driver the properties 'fsl,qspi-has-second-chip' and 'big-endian' are not used anymore. The driver now uses the 'reg' property to determine the bus and the chipselect. The endianness is selected by the driver depending on which SoC is used. Signed-off-by: Frieder Schrempf Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts | 1 - arch/arm/boot/dts/ls1021a.dtsi | 1 - 2 files changed, 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts b/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts index ba1ddd93b8f8..dcb1d9bd0922 100644 --- a/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts +++ b/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts @@ -204,7 +204,6 @@ }; &qspi { - fsl,qspi-has-second-chip; status = "okay"; flash: flash@0 { diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index b4f2723ecd86..2bcc00de88d4 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -186,7 +186,6 @@ interrupts = ; clock-names = "qspi_en", "qspi"; clocks = <&clockgen 4 1>, <&clockgen 4 1>; - big-endian; status = "disabled"; }; -- cgit From 53239664e5ae353f60f37a566dbd32415a906ee8 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 20 Mar 2019 20:45:22 +0100 Subject: ARM: dts: ape6evm: Add NOR FLASH MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Describe the 128 MiB CFI NOR FLASH, which contains the boot loader and its environment. Signed-off-by: Geert Uytterhoeven Tested-by: Niklas Söderlund Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a73a4-ape6evm.dts | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts index d530f451467e..b1e0d556be0a 100644 --- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts +++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts @@ -166,6 +166,33 @@ }; &bsc { + flash@0 { + compatible = "cfi-flash", "mtd-rom"; + reg = <0x0 0x08000000>; + bank-width = <2>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000000 0x00040000>; + read-only; + }; + partition@40000 { + label = "uboot-env"; + reg = <0x00040000 0x00040000>; + read-only; + }; + partition@80000 { + label = "flash"; + reg = <0x00080000 0x07f80000>; + }; + }; + }; + ethernet@8000000 { compatible = "smsc,lan9220", "smsc,lan9115"; reg = <0x08000000 0x1000>; -- cgit From 4ec778fb0f26692419609d2f39b6f8c829ed1fb5 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Tue, 19 Mar 2019 12:21:38 +0000 Subject: ARM: dts: r8a77470: Add DU support This commit adds DU support to the RZ/G1C (a.k.a. r8a77470) specific device tree. Signed-off-by: Fabrizio Castro Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a77470.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index f4e232bf9d03..493cf2b3f795 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -643,6 +643,38 @@ resets = <&cpg 408>; }; + du: display@feb00000 { + compatible = "renesas,du-r8a77470"; + reg = <0 0xfeb00000 0 0x40000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>; + clock-names = "du.0", "du.1"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb0: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_rgb1: endpoint { + }; + }; + port@2 { + reg = <2>; + du_out_lvds0: endpoint { + }; + }; + }; + }; + prr: chipid@ff000044 { compatible = "renesas,prr"; reg = <0 0xff000044 0 4>; -- cgit From 26c9d79b3730dff03d1c3ea6aee3e2968d36fe15 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Tue, 19 Mar 2019 12:21:39 +0000 Subject: ARM: dts: iwg23s-sbc: Add HDMI support This patch adds HDMI video output support to the iwg23s board from iWave. Due to a problem with the bootloader not dealing with the configuration of one of the pins correctly, we have to use a gpio-hog for the interrupt line to make sure the pin is configured as GPIO-input when requesting the interrupt. Signed-off-by: Fabrizio Castro Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 79 +++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts index 77d18242ef59..9f9eb15a1e65 100644 --- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts +++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts @@ -22,6 +22,17 @@ stdout-path = "serial1:115200n8"; }; + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&bridge_out>; + }; + }; + }; + memory@40000000 { device_type = "memory"; reg = <0 0x40000000 0 0x20000000>; @@ -80,10 +91,34 @@ status = "okay"; }; +&du { + pinctrl-0 = <&du0_pins>; + pinctrl-names = "default"; + + status = "okay"; + + ports { + port@0 { + endpoint { + remote-endpoint = <&bridge_in>; + }; + }; + }; +}; + &extal_clk { clock-frequency = <20000000>; }; +&gpio2 { + interrupt-fixup { + gpio-hog; + gpios = <29 GPIO_ACTIVE_HIGH>; + line-name = "hdmi-hpd-int"; + input; + }; +}; + &i2c3 { pinctrl-0 = <&i2c3_pins>; pinctrl-names = "default"; @@ -97,12 +132,56 @@ }; }; +&i2c4 { + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <100000>; + + hdmi@39 { + compatible = "sil,sii9022"; + reg = <0x39>; + interrupt-parent = <&gpio2>; + interrupts = <29 IRQ_TYPE_LEVEL_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + bridge_in: endpoint { + remote-endpoint = <&du_out_rgb0>; + }; + }; + + port@1 { + reg = <1>; + bridge_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + &pfc { avb_pins: avb { groups = "avb_mdio", "avb_gmii_tx_rx"; function = "avb"; }; + du0_pins: du0 { + groups = "du0_rgb888", "du0_sync", "du0_disp", "du0_clk0_out"; + function = "du0"; + }; + + i2c4_pins: i2c4 { + groups = "i2c4_e"; + function = "i2c4"; + }; + i2c3_pins: i2c3 { groups = "i2c3_c"; function = "i2c3"; -- cgit From 0c4cac5e8f0313a8777055c0c66a2216f78c6054 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Fri, 22 Mar 2019 12:59:24 -0700 Subject: ARM: dts: rockchip: Add rk3288-veyron-jerry rev 10-15 As far as I can tell/remember rev10 was originally created to support making a SKU of jerry that had a different LCD. rev11-rev15 were added to give some wiggle room for future builds. Downstream has a separate device tree for rev10-rev15 (compared to rev3-rev7) with the expectation that differences relating to the LCD would be accounted for there but nothing was ever added to the rev10-rev15 making it identical to the rev3-rev7 one. It's likely nothing actually shipped with rev10-rev15 but they are listed in the downstream kernel's device tree and it seems like it should add a little safety if we match them here just in case something actually shipped with one of these revisions and that device will break if we don't claim support. Signed-off-by: Douglas Anderson Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-veyron-jerry.dts | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3288-veyron-jerry.dts b/arch/arm/boot/dts/rk3288-veyron-jerry.dts index 2ba89895c33a..517c6999a978 100644 --- a/arch/arm/boot/dts/rk3288-veyron-jerry.dts +++ b/arch/arm/boot/dts/rk3288-veyron-jerry.dts @@ -11,7 +11,10 @@ / { model = "Google Jerry"; - compatible = "google,veyron-jerry-rev7", "google,veyron-jerry-rev6", + compatible = "google,veyron-jerry-rev15", "google,veyron-jerry-rev14", + "google,veyron-jerry-rev13", "google,veyron-jerry-rev12", + "google,veyron-jerry-rev11", "google,veyron-jerry-rev10", + "google,veyron-jerry-rev7", "google,veyron-jerry-rev6", "google,veyron-jerry-rev5", "google,veyron-jerry-rev4", "google,veyron-jerry-rev3", "google,veyron-jerry", "google,veyron", "rockchip,rk3288"; -- cgit From 21f843ff948b4283c5d1f309651e90f978f5494e Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Fri, 22 Mar 2019 09:52:09 -0700 Subject: ARM: dts: rockchip: Add dvs-gpios to rk3288-veyron-jerry When the rk3288-jerry device tree was first submitted we left out the dvs-gpios because I pointed out that the property "dvs-gpios" wasn't yet supported upstream [1]. Soon after that the property was added in commit bad47ad2eef3 ("regulator: rk808: fixed the overshoot when adjust voltage"). ...but we forgot to go back and add the property to the jerry device tree file. Let's do so now. NOTE: without this patch, jerry is likely still stable (thanks to the fallback of making many small jumps in the rk808 regulator code) but it'll take quite a bit longer to make voltage transitions. [1] https://lore.kernel.org/linux-arm-kernel/CAD=FV=WwFgjzbk9xF5TU_ie6UnHQMyrZ176D4+jJTWWOoaKC2Q@mail.gmail.com/ Fixes: f3ee390e4ef2 ("ARM: dts: rockchip: add veyron-jerry board") Signed-off-by: Douglas Anderson Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-veyron-jerry.dts | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3288-veyron-jerry.dts b/arch/arm/boot/dts/rk3288-veyron-jerry.dts index 517c6999a978..3e8f700a0d64 100644 --- a/arch/arm/boot/dts/rk3288-veyron-jerry.dts +++ b/arch/arm/boot/dts/rk3288-veyron-jerry.dts @@ -64,7 +64,9 @@ &rk808 { pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; + pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; + dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>, + <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>; regulators { mic_vcc: LDO_REG2 { -- cgit From 864c2fee4ee93f53a8efed206c01ebce546df4e9 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Thu, 21 Mar 2019 13:19:44 -0700 Subject: ARM: dts: rockchip: Add vdd_logic to rk3288-veyron The vdd_logic rail controls the voltage supplied to misc logic on rk3288, including the voltage supplied to the memory controller. The vcc logic is implemented by a PWM regulator. Right now there are no consumers of vdd_logic on veyron but if anyone ever wants to try to add DDR Freq they'd need it. Note that in the downstream Chrome OS kernel the PWM regulator has a voltage table with these points: 1350000 0% 1300000 10% 1250000 20% 1200000 31% 1150000 41% 1125000 46% 1100000 52% 1050000 62% 1000000 72% 950000 83% The DDR Freq driver in the downstream kernel only uses some of those points, namely: DDR3: 1200000, 1150000, 1100000, 1050000 LPDDR: 1150000, 1100000, 1050000 When adapting the downstream kernel to upstream I have opted to switch to using the "continuous" mode of the PWM regulator driver. This was the only way I could get the upstream driver to achieve _exactly_ the same voltages as the downstream driver could. Specifically note that the old driver in downstream Chrome OS 3.14 _didn't_ have the DIV_ROUND_CLOSEST_ULL() in the Rockchip PLL driver. That means if I use the same (downstream) table I might end up with a duty cycle that's 1 larger than was used downstream, leading to a slightly different voltage. Due to the way the rounding worked I couldn't even just adjust the "percent" by 1 for a given voltage level--certain duty cycles just aren't achievable with the upstream math for voltage tables. Using continuous mode you can achieve the exact same duty cycle by simply adjusting the voltage you use by a tad bit. The voltages that are equivalent to the ones used in the downstream kernel's table are: 1350000, 1304472, 1255691, 1200407, 1154878, 1128862, 1099593, 1050813, 1005285, 950000 Note that the top/bottom voltage is exactly the same just due to the way that continuous mode is calculated and the fact that I used those as anchors. I didn't make any attempt to do the resistor math (as was done on rk3399-gru). If anyone ever gets DDRFreq working on veyron upstream they should thus adjust the voltage specified in the DDRFreq operating points slightly (as per the above) to obtain the existing/tested values. AKA you'd use: DDR3: 1200407, 1154878, 1099593, 1050813 LPDDR: 1154878, 1099593, 1050813 A few other notes: - The "period" here (1994) is different than the "period" downstream (2000) for similar reasons: there's a DIV_ROUND_CLOSEST_ULL() that wasn't downstream. With 1994 upstream comes up with the same value (0x94) to program into the hardware that downstream put there. As far as I can tell 0x94 actually means 1993.27. - The duty cycle unit of 0x94 was picked by just matching the period which nicely allows us to insert 0x7b as that value to program into the hardware for 950mV. The 0x7b was found by observing what the downstream kernel calculated (not that the system can actually run with vdd_log at 950 mV). - The downstream kernel can also be seen to program a different value into the CTRL field. Upstream achieves 0x0b and downstream 0x1b. This is because the upstream commit bc834d7b07b4 ("pwm: rockchip: Move the configuration of polarity") fixed a bug by adding "ctrl &= ~PWM_POLARITY_MASK". Downstream accidentally left bit 4 set. Luckily this bit doesn't matter--it's only used when the PWM goes inactive (AKA if it's in oneshot mode or is disabled) and we don't do that for the PWM regulator. I measured the voltage of vdd_log while adjusting it and found that with the upstream kernel voltage difference between requested and actual was 9.2 mV at 950 mV and 13.4 mV at 1350 mV with in-between voltages consistently showing ~1% error. This error is likely expected as voltage can be seen to sag a bit when more load is put on the rail. Signed-off-by: Douglas Anderson Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-veyron.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index 0bc2409f6903..5181d9435fda 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -95,6 +95,23 @@ regulator-boot-on; vin-supply = <&vcc_5v>; }; + + vdd_logic: vdd-logic { + compatible = "pwm-regulator"; + regulator-name = "vdd_logic"; + + pwms = <&pwm1 0 1994 0>; + pwm-supply = <&vcc33_sys>; + + pwm-dutycycle-range = <0x7b 0>; + pwm-dutycycle-unit = <0x94>; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <4000>; + }; }; &cpu0 { -- cgit From 1fb8c97f9d96400cd0a7f5553844da1eae5594e4 Mon Sep 17 00:00:00 2001 From: Benjamin Drung Date: Sun, 3 Feb 2019 21:13:30 +0100 Subject: ARM: dts: exynos: Fix spelling mistake of EXYNOS5420 The SoC name EXYNOS5420 was misspelled. Signed-off-by: Benjamin Drung Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5420.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index aaff15880761..5fb2326875dc 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -5,7 +5,7 @@ * Copyright (c) 2013 Samsung Electronics Co., Ltd. * http://www.samsung.com * - * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file. + * SAMSUNG EXYNOS5420 SoC device nodes are listed in this file. * EXYNOS5420 based board files can include this file and provide * values for board specfic bindings. */ -- cgit From 75f9a058838be9880afd75c4cb14e1bf4fe34a0b Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 25 Mar 2019 14:52:35 +0100 Subject: ARM: dts: sunxi: h3/h5: Remove stale pinctrl-names entry Some nodes still have pinctrl-names entry, yet they don't have any pinctrl group anymore. Drop them. Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts | 3 --- arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 1 - arch/arm/boot/dts/sun8i-h3-orangepi-zero-plus2.dts | 1 - arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi | 3 --- 4 files changed, 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts index 1db2541135a7..c38a806191df 100644 --- a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts +++ b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts @@ -28,7 +28,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; pwr_led { label = "bananapi-m2-zero:red:pwr"; @@ -39,7 +38,6 @@ gpio_keys { compatible = "gpio-keys"; - pinctrl-names = "default"; sw4 { label = "power"; @@ -67,7 +65,6 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ }; }; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts index 4ec94d72f021..aee666b59b01 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts @@ -64,7 +64,6 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ }; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-zero-plus2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-zero-plus2.dts index c834048c325e..f2f7b7a92571 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-zero-plus2.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-zero-plus2.dts @@ -79,7 +79,6 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; reset-gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */ post-power-on-delay-ms = <200>; }; diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi index 3bed375b9c03..f9958c5a5c8c 100644 --- a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi +++ b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi @@ -69,7 +69,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; pwr_led { label = "bananapi-m2-plus:red:pwr"; @@ -80,7 +79,6 @@ gpio_keys { compatible = "gpio-keys"; - pinctrl-names = "default"; sw4 { label = "power"; @@ -101,7 +99,6 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ clocks = <&rtc 1>; clock-names = "ext_clock"; -- cgit From a4dc791974e568a15f7f37131729b1a6912f4811 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 25 Mar 2019 14:52:52 +0100 Subject: ARM: dts: sun8i: h3: Refactor the pinctrl node names The H3 and H5 have never been converted to the new convention we want to have for the pinctrl nodes. Convert them. Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- .../boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts | 2 +- arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 2 +- arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 6 ++-- arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts | 4 +-- arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 2 +- arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts | 2 +- arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts | 2 +- arch/arm/boot/dts/sun8i-h3-nanopi.dtsi | 2 +- arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 4 +-- arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts | 4 +-- arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 2 +- arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 4 +-- arch/arm/boot/dts/sun8i-h3-orangepi-zero-plus2.dts | 2 +- arch/arm/boot/dts/sun8i-h3-rervision-dvk.dts | 2 +- arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi | 4 +-- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 38 +++++++++++----------- arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi | 4 +-- 17 files changed, 43 insertions(+), 43 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts index c38a806191df..0e5f0eec3810 100644 --- a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts +++ b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts @@ -112,7 +112,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pa_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts index 84cd9c061227..4970eda2877e 100644 --- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts +++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts @@ -178,7 +178,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pa_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts index 25540b7694d5..6277f13f3eb3 100644 --- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts +++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts @@ -142,7 +142,7 @@ &ir { pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; + pinctrl-0 = <&r_ir_rx_pin>; status = "okay"; }; @@ -193,13 +193,13 @@ &spdif { pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pins_a>; + pinctrl-0 = <&spdif_tx_pin>; status = "okay"; }; &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pa_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts b/arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts index 2c952eacfef5..6d626ec1f747 100644 --- a/arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts +++ b/arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts @@ -84,7 +84,7 @@ &ir { pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; + pinctrl-0 = <&r_ir_rx_pin>; status = "okay"; }; @@ -120,7 +120,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pa_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts index aee666b59b01..4ba533b0340f 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts @@ -120,7 +120,7 @@ &ir { pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; + pinctrl-0 = <&r_ir_rx_pin>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts index 9412668bb888..69243dcb30a6 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts @@ -93,7 +93,7 @@ &ir { pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; + pinctrl-0 = <&r_ir_rx_pin>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts index 6246d3eff39d..07867a0d569b 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts @@ -105,7 +105,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pa_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi index f110ee382239..660bcf497926 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi +++ b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi @@ -125,7 +125,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pa_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts index f1fc6bdca8be..e22c175bb515 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts @@ -152,7 +152,7 @@ &ir { pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; + pinctrl-0 = <&r_ir_rx_pin>; status = "okay"; }; @@ -210,7 +210,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pa_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts index 476ae8e387ca..ceda02d8e65f 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts @@ -126,7 +126,7 @@ &ir { pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; + pinctrl-0 = <&r_ir_rx_pin>; status = "okay"; }; @@ -181,7 +181,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pa_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts index 245fd658defb..333aebd732b6 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts @@ -192,7 +192,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pa_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts index 46240334128f..3190a8be0073 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts @@ -152,7 +152,7 @@ &ir { pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; + pinctrl-0 = <&r_ir_rx_pin>; status = "okay"; }; @@ -229,7 +229,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pa_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-zero-plus2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-zero-plus2.dts index f2f7b7a92571..b8f46e2802fd 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-zero-plus2.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-zero-plus2.dts @@ -134,6 +134,6 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pa_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-rervision-dvk.dts b/arch/arm/boot/dts/sun8i-h3-rervision-dvk.dts index 51bd2c00bbae..4738f3a9efe4 100644 --- a/arch/arm/boot/dts/sun8i-h3-rervision-dvk.dts +++ b/arch/arm/boot/dts/sun8i-h3-rervision-dvk.dts @@ -100,7 +100,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pa_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi index f9958c5a5c8c..39263e74fbb5 100644 --- a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi +++ b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi @@ -150,7 +150,7 @@ &ir { pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; + pinctrl-0 = <&r_ir_rx_pin>; status = "okay"; }; @@ -207,7 +207,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pa_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 395521e83ee7..8a79d3b04069 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -386,14 +386,14 @@ interrupt-controller; #interrupt-cells = <3>; - csi_pins: csi { + csi_pins: csi-pins { pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7", "PE8", "PE9", "PE10", "PE11"; function = "csi"; }; - emac_rgmii_pins: emac0 { + emac_rgmii_pins: emac-rgmii-pins { pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD7", "PD8", "PD9", "PD10", "PD12", "PD13", "PD15", "PD16", "PD17"; @@ -401,22 +401,22 @@ drive-strength = <40>; }; - i2c0_pins: i2c0 { + i2c0_pins: i2c0-pins { pins = "PA11", "PA12"; function = "i2c0"; }; - i2c1_pins: i2c1 { + i2c1_pins: i2c1-pins { pins = "PA18", "PA19"; function = "i2c1"; }; - i2c2_pins: i2c2 { + i2c2_pins: i2c2-pins { pins = "PE12", "PE13"; function = "i2c2"; }; - mmc0_pins: mmc0 { + mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; function = "mmc0"; @@ -424,7 +424,7 @@ bias-pull-up; }; - mmc1_pins: mmc1 { + mmc1_pins: mmc1-pins { pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; function = "mmc1"; @@ -432,7 +432,7 @@ bias-pull-up; }; - mmc2_8bit_pins: mmc2_8bit { + mmc2_8bit_pins: mmc2-8bit-pins { pins = "PC5", "PC6", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14", @@ -442,47 +442,47 @@ bias-pull-up; }; - spdif_tx_pins_a: spdif { + spdif_tx_pin: spdif-tx-pin { pins = "PA17"; function = "spdif"; }; - spi0_pins: spi0 { + spi0_pins: spi0-pins { pins = "PC0", "PC1", "PC2", "PC3"; function = "spi0"; }; - spi1_pins: spi1 { + spi1_pins: spi1-pins { pins = "PA15", "PA16", "PA14", "PA13"; function = "spi1"; }; - uart0_pins_a: uart0 { + uart0_pa_pins: uart0-pa-pins { pins = "PA4", "PA5"; function = "uart0"; }; - uart1_pins: uart1 { + uart1_pins: uart1-pins { pins = "PG6", "PG7"; function = "uart1"; }; - uart1_rts_cts_pins: uart1_rts_cts { + uart1_rts_cts_pins: uart1-rts-cts-pins { pins = "PG8", "PG9"; function = "uart1"; }; - uart2_pins: uart2 { + uart2_pins: uart2-pins { pins = "PA0", "PA1"; function = "uart2"; }; - uart3_pins: uart3 { + uart3_pins: uart3-pins { pins = "PA13", "PA14"; function = "uart3"; }; - uart3_rts_cts_pins: uart3_rts_cts { + uart3_rts_cts_pins: uart3-rts-cts-pins { pins = "PA15", "PA16"; function = "uart3"; }; @@ -860,12 +860,12 @@ interrupt-controller; #interrupt-cells = <3>; - ir_pins_a: ir { + r_ir_rx_pin: r-ir-rx-pin { pins = "PL11"; function = "s_cir_rx"; }; - r_i2c_pins: r-i2c { + r_i2c_pins: r-i2c-pins { pins = "PL0", "PL1"; function = "s_i2c"; }; diff --git a/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi b/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi index 1eadc132390c..19b3b23cfaa8 100644 --- a/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi +++ b/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi @@ -167,7 +167,7 @@ &ir { pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; + pinctrl-0 = <&r_ir_rx_pin>; status = "okay"; }; @@ -205,7 +205,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pa_pins>; status = "okay"; }; -- cgit From 73b670023327a014688c2d5309a43604cd553f1e Mon Sep 17 00:00:00 2001 From: Mans Rullgard Date: Wed, 20 Feb 2019 12:07:17 +0000 Subject: ARM: dts: sun7i: add pinctrl for missing uart mux options This adds pinctrl settings for various missing uart options. Signed-off-by: Mans Rullgard Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 54 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 641a8fa6d428..8d3bb135e756 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -938,6 +938,36 @@ function = "uart0"; }; + /omit-if-no-ref/ + uart0_pf_pins: uart0-pf-pins { + pins = "PF2", "PF4"; + function = "uart0"; + }; + + /omit-if-no-ref/ + uart1_pa_pins: uart1-pa-pins { + pins = "PA10", "PA11"; + function = "uart1"; + }; + + /omit-if-no-ref/ + uart1_cts_rts_pa_pins: uart1-cts-rts-pa-pins { + pins = "PA12", "PIA13"; + function = "uart2"; + }; + + /omit-if-no-ref/ + uart2_pa_pins: uart2-pa-pins { + pins = "PIA2", "PIA3"; + function = "uart2"; + }; + + /omit-if-no-ref/ + uart2_cts_rts_pa_pins: uart2-cts-rts-pa-pins { + pins = "PA0", "PIA1"; + function = "uart2"; + }; + uart2_pi_pins: uart2-pi-pins { pins = "PI18", "PI19"; function = "uart2"; @@ -963,6 +993,12 @@ function = "uart3"; }; + /omit-if-no-ref/ + uart3_cts_rts_ph_pins: uart3-cts-rts-ph-pins { + pins = "PH2", "PH3"; + function = "uart3"; + }; + uart4_pg_pins: uart4-pg-pins { pins = "PG10", "PG11"; function = "uart4"; @@ -973,16 +1009,34 @@ function = "uart4"; }; + /omit-if-no-ref/ + uart5_ph_pins: uart5-ph-pins { + pins = "PH6", "PH7"; + function = "uart5"; + }; + uart5_pi_pins: uart5-pi-pins { pins = "PI10", "PI11"; function = "uart5"; }; + /omit-if-no-ref/ + uart6_pa_pins: uart6-pa-pins { + pins = "PA12", "PA13"; + function = "uart6"; + }; + uart6_pi_pins: uart6-pi-pins { pins = "PI12", "PI13"; function = "uart6"; }; + /omit-if-no-ref/ + uart7_pa_pins: uart7-pa-pins { + pins = "PA14", "PA15"; + function = "uart7"; + }; + uart7_pi_pins: uart7-pi-pins { pins = "PI20", "PI21"; function = "uart7"; -- cgit From 7a13e1820a6b5dc42fd837a5001bedf552a8f9c9 Mon Sep 17 00:00:00 2001 From: Mans Rullgard Date: Wed, 20 Feb 2019 14:25:34 +0000 Subject: ARM: dts: sun7i: add pinctrl for CAN in PA bank This adds pinctrl settings for the CAN controller using pins PA16 and PA17. Signed-off-by: Mans Rullgard Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 8d3bb135e756..69e1692c842a 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -751,6 +751,12 @@ #interrupt-cells = <3>; #gpio-cells = <3>; + /omit-if-no-ref/ + can_pa_pins: can-pa-pins { + pins = "PA16", "PA17"; + function = "can"; + }; + can_ph_pins: can-ph-pins { pins = "PH20", "PH21"; function = "can"; -- cgit From cfec64e8f2e73cc8167f05eada39510365afcd5b Mon Sep 17 00:00:00 2001 From: Mans Rullgard Date: Wed, 20 Feb 2019 14:25:35 +0000 Subject: ARM: dts: sun7i: add pinctrl for EMAC in PH bank This adds pinctrl settings the EMAC using pins in the PH block. Signed-off-by: Mans Rullgard Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 69e1692c842a..541db8b90ee3 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -781,6 +781,16 @@ function = "emac"; }; + /omit-if-no-ref/ + emac_ph_pins: emac-ph-pins { + pins = "PH8", "PH9", "PH10", "PH11", + "PH14", "PH15", "PH16", "PH17", + "PH18", "PH19", "PH20", "PH21", + "PH22", "PH23", "PH24", "PH25", + "PH26"; + function = "emac"; + }; + gmac_mii_pins: gmac-mii-pins { pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", -- cgit From ff8e860249e8c705d9150e307d81305e66b55d06 Mon Sep 17 00:00:00 2001 From: Mans Rullgard Date: Wed, 20 Feb 2019 14:25:36 +0000 Subject: ARM: dts: sun7i: add /omit-if-no-ref/ tags to pin group nodes Since only one alternative at a time is used, and some functions may not be used at all, this cuts down the size of the board dtb files a bit. Signed-off-by: Mans Rullgard Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 42 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 541db8b90ee3..792897a1a215 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -757,21 +757,25 @@ function = "can"; }; + /omit-if-no-ref/ can_ph_pins: can-ph-pins { pins = "PH20", "PH21"; function = "can"; }; + /omit-if-no-ref/ clk_out_a_pin: clk-out-a-pin { pins = "PI12"; function = "clk_out_a"; }; + /omit-if-no-ref/ clk_out_b_pin: clk-out-b-pin { pins = "PI13"; function = "clk_out_b"; }; + /omit-if-no-ref/ emac_pa_pins: emac-pa-pins { pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", @@ -791,6 +795,7 @@ function = "emac"; }; + /omit-if-no-ref/ gmac_mii_pins: gmac-mii-pins { pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", @@ -800,6 +805,7 @@ function = "gmac"; }; + /omit-if-no-ref/ gmac_rgmii_pins: gmac-rgmii-pins { pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", @@ -814,46 +820,55 @@ drive-strength = <40>; }; + /omit-if-no-ref/ i2c0_pins: i2c0-pins { pins = "PB0", "PB1"; function = "i2c0"; }; + /omit-if-no-ref/ i2c1_pins: i2c1-pins { pins = "PB18", "PB19"; function = "i2c1"; }; + /omit-if-no-ref/ i2c2_pins: i2c2-pins { pins = "PB20", "PB21"; function = "i2c2"; }; + /omit-if-no-ref/ i2c3_pins: i2c3-pins { pins = "PI0", "PI1"; function = "i2c3"; }; + /omit-if-no-ref/ ir0_rx_pin: ir0-rx-pin { pins = "PB4"; function = "ir0"; }; + /omit-if-no-ref/ ir0_tx_pin: ir0-tx-pin { pins = "PB3"; function = "ir0"; }; + /omit-if-no-ref/ ir1_rx_pin: ir1-rx-pin { pins = "PB23"; function = "ir1"; }; + /omit-if-no-ref/ ir1_tx_pin: ir1-tx-pin { pins = "PB22"; function = "ir1"; }; + /omit-if-no-ref/ mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; @@ -862,6 +877,7 @@ bias-pull-up; }; + /omit-if-no-ref/ mmc2_pins: mmc2-pins { pins = "PC6", "PC7", "PC8", "PC9", "PC10", "PC11"; @@ -870,6 +886,7 @@ bias-pull-up; }; + /omit-if-no-ref/ mmc3_pins: mmc3-pins { pins = "PI4", "PI5", "PI6", "PI7", "PI8", "PI9"; @@ -878,77 +895,92 @@ bias-pull-up; }; + /omit-if-no-ref/ ps2_0_pins: ps2-0-pins { pins = "PI20", "PI21"; function = "ps2"; }; + /omit-if-no-ref/ ps2_1_ph_pins: ps2-1-ph-pins { pins = "PH12", "PH13"; function = "ps2"; }; + /omit-if-no-ref/ pwm0_pin: pwm0-pin { pins = "PB2"; function = "pwm"; }; + /omit-if-no-ref/ pwm1_pin: pwm1-pin { pins = "PI3"; function = "pwm"; }; + /omit-if-no-ref/ spdif_tx_pin: spdif-tx-pin { pins = "PB13"; function = "spdif"; bias-pull-up; }; + /omit-if-no-ref/ spi0_pi_pins: spi0-pi-pins { pins = "PI11", "PI12", "PI13"; function = "spi0"; }; + /omit-if-no-ref/ spi0_cs0_pi_pin: spi0-cs0-pi-pin { pins = "PI10"; function = "spi0"; }; + /omit-if-no-ref/ spi0_cs1_pi_pin: spi0-cs1-pi-pin { pins = "PI14"; function = "spi0"; }; + /omit-if-no-ref/ spi1_pi_pins: spi1-pi-pins { pins = "PI17", "PI18", "PI19"; function = "spi1"; }; + /omit-if-no-ref/ spi1_cs0_pi_pin: spi1-cs0-pi-pin { pins = "PI16"; function = "spi1"; }; + /omit-if-no-ref/ spi2_pb_pins: spi2-pb-pins { pins = "PB15", "PB16", "PB17"; function = "spi2"; }; + /omit-if-no-ref/ spi2_cs0_pb_pin: spi2-cs0-pb-pin { pins = "PB14"; function = "spi2"; }; + /omit-if-no-ref/ spi2_pc_pins: spi2-pc-pins { pins = "PC20", "PC21", "PC22"; function = "spi2"; }; + /omit-if-no-ref/ spi2_cs0_pc_pin: spi2-cs0-pc-pin { pins = "PC19"; function = "spi2"; }; + /omit-if-no-ref/ uart0_pb_pins: uart0-pb-pins { pins = "PB22", "PB23"; function = "uart0"; @@ -984,26 +1016,31 @@ function = "uart2"; }; + /omit-if-no-ref/ uart2_pi_pins: uart2-pi-pins { pins = "PI18", "PI19"; function = "uart2"; }; + /omit-if-no-ref/ uart2_cts_rts_pi_pins: uart2-cts-rts-pi-pins { pins = "PI16", "PI17"; function = "uart2"; }; + /omit-if-no-ref/ uart3_pg_pins: uart3-pg-pins { pins = "PG6", "PG7"; function = "uart3"; }; + /omit-if-no-ref/ uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins { pins = "PG8", "PG9"; function = "uart3"; }; + /omit-if-no-ref/ uart3_ph_pins: uart3-ph-pins { pins = "PH0", "PH1"; function = "uart3"; @@ -1015,11 +1052,13 @@ function = "uart3"; }; + /omit-if-no-ref/ uart4_pg_pins: uart4-pg-pins { pins = "PG10", "PG11"; function = "uart4"; }; + /omit-if-no-ref/ uart4_ph_pins: uart4-ph-pins { pins = "PH4", "PH5"; function = "uart4"; @@ -1031,6 +1070,7 @@ function = "uart5"; }; + /omit-if-no-ref/ uart5_pi_pins: uart5-pi-pins { pins = "PI10", "PI11"; function = "uart5"; @@ -1042,6 +1082,7 @@ function = "uart6"; }; + /omit-if-no-ref/ uart6_pi_pins: uart6-pi-pins { pins = "PI12", "PI13"; function = "uart6"; @@ -1053,6 +1094,7 @@ function = "uart7"; }; + /omit-if-no-ref/ uart7_pi_pins: uart7-pi-pins { pins = "PI20", "PI21"; function = "uart7"; -- cgit From cd42ca0515d3952fc78a591618d57dd54f881d1f Mon Sep 17 00:00:00 2001 From: Priit Laes Date: Tue, 26 Feb 2019 16:15:25 +0200 Subject: ARM: dts: sun7i: olimex-lime2: Add regulators for GPIO banks Make sure that A20 Olimex Lime2 pin bank regulators are properly represented. While pin banks A, B and F are connected to 3.3V static regulator, pin banks E and G tied with LDO3 and LDO4 regulators with 2.8V reference. Signed-off-by: Priit Laes Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts index 4e1c590eb098..3de479bfa4cf 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts @@ -174,6 +174,12 @@ }; &pio { + vcc-pa-supply = <®_vcc3v3>; + vcc-pc-supply = <®_vcc3v3>; + vcc-pe-supply = <®_ldo3>; + vcc-pf-supply = <®_vcc3v3>; + vcc-pg-supply = <®_ldo4>; + led_pins_olinuxinolime: led-pins { pins = "PH2"; function = "gpio_out"; -- cgit From 67fec9db606f24fb81809a9a04078cbca0c24fa7 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 14 Mar 2019 21:16:24 +0100 Subject: ARM: dts: sun8i: a83t: Add cross links for the mixers Unlike what the binding for multiple pipeline documents, the A83t doesn't have the cross links between the TCON and the mixers. Let's add them. Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t.dtsi | 30 ++++++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index b099d2fbb5cd..7651b6dcfd0f 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -333,6 +333,11 @@ reg = <0>; remote-endpoint = <&tcon0_in_mixer0>; }; + + mixer0_out_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_in_mixer0>; + }; }; }; }; @@ -351,9 +356,17 @@ #size-cells = <0>; mixer1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; reg = <1>; - mixer1_out_tcon1: endpoint { + mixer1_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_mixer1>; + }; + + mixer1_out_tcon1: endpoint@1 { + reg = <1>; remote-endpoint = <&tcon1_in_mixer1>; }; }; @@ -436,6 +449,11 @@ reg = <0>; remote-endpoint = <&mixer0_out_tcon0>; }; + + tcon0_in_mixer1: endpoint@1 { + reg = <1>; + remote-endpoint = <&mixer1_out_tcon0>; + }; }; tcon0_out: port@1 { @@ -460,9 +478,17 @@ #size-cells = <0>; tcon1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; reg = <0>; - tcon1_in_mixer1: endpoint { + tcon1_in_mixer0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mixer0_out_tcon1>; + }; + + tcon1_in_mixer1: endpoint@1 { + reg = <1>; remote-endpoint = <&mixer1_out_tcon1>; }; }; -- cgit From 9d803c1cf8513e82654210fffd805879325d0e22 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 14 Mar 2019 21:16:26 +0100 Subject: ARM: dts: sun5i: Fix display pipeline endpoint warnings in DTC Since most of the display IPs have a single endpoint, having a reg property, a unit-address and #address-cells and #size-cells will emit a warning. Let's remove those. Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i.dtsi | 25 +++++-------------------- 1 file changed, 5 insertions(+), 20 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index 5497d985c54a..ccd793795e58 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -238,11 +238,8 @@ status = "disabled"; port { - #address-cells = <1>; - #size-cells = <0>; - tve0_in_tcon0: endpoint@0 { - reg = <0>; + tve0_in_tcon0: endpoint { remote-endpoint = <&tcon0_out_tve0>; }; }; @@ -285,12 +282,9 @@ #size-cells = <0>; tcon0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; reg = <0>; - tcon0_in_be0: endpoint@0 { - reg = <0>; + tcon0_in_be0: endpoint { remote-endpoint = <&be0_out_tcon0>; }; }; @@ -734,12 +728,9 @@ #size-cells = <0>; fe0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; reg = <1>; - fe0_out_be0: endpoint@0 { - reg = <0>; + fe0_out_be0: endpoint { remote-endpoint = <&be0_in_fe0>; }; }; @@ -765,23 +756,17 @@ #size-cells = <0>; be0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; reg = <0>; - be0_in_fe0: endpoint@0 { - reg = <0>; + be0_in_fe0: endpoint { remote-endpoint = <&fe0_out_be0>; }; }; be0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; reg = <1>; - be0_out_tcon0: endpoint@0 { - reg = <0>; + be0_out_tcon0: endpoint { remote-endpoint = <&tcon0_in_be0>; }; }; -- cgit From a8735656955994fb75fbc835ede2b46052f86b60 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 14 Mar 2019 21:16:27 +0100 Subject: ARM: dts: sun5i: Fix Display Engine DTC warnings Our display engine endpoints trigger some DTC warnings due to the fact that we're having a single endpoint that doesn't need any reg property, and since we don't have a reg property, we don't need the address-cells and size-cells properties anymore. Fix those Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 2 -- arch/arm/boot/dts/sun5i-a13-q8-tablet.dts | 11 ++--------- 2 files changed, 2 insertions(+), 11 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts index 9409c232d48a..54ca140fc258 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts @@ -74,8 +74,6 @@ bridge { compatible = "dumb-vga-dac"; - #address-cells = <1>; - #size-cells = <0>; ports { #address-cells = <1>; diff --git a/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts b/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts index 7257f39b31ce..fde559a8b61e 100644 --- a/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts +++ b/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts @@ -53,16 +53,9 @@ power-supply = <®_vcc3v3>; enable-gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>; /* AXP GPIO0 */ backlight = <&backlight>; - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - panel_input: endpoint@0 { - reg = <0>; + port { + panel_input: endpoint { remote-endpoint = <&tcon0_out_lcd>; }; }; -- cgit From 73b65f45bc60f16e07e0aad42e6406f2abddc248 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 14 Mar 2019 21:16:28 +0100 Subject: ARM: dts: sun6i: Fix Display Engine DTC warnings Our display engine endpoints trigger some DTC warnings due to the fact that we're having a single endpoint that doesn't need any reg property, and since we don't have a reg property, we don't need the address-cells and size-cells properties anymore. Fix those Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 12 ++---------- arch/arm/boot/dts/sun6i-a31.dtsi | 12 ++---------- 2 files changed, 4 insertions(+), 20 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts index e17a65b3561e..63b84327f4e9 100644 --- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts +++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts @@ -86,31 +86,23 @@ vga-dac { compatible = "dumb-vga-dac"; vdd-supply = <®_vga_3v3>; - #address-cells = <1>; - #size-cells = <0>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { - #address-cells = <1>; - #size-cells = <0>; reg = <0>; - vga_dac_in: endpoint@0 { - reg = <0>; + vga_dac_in: endpoint { remote-endpoint = <&tcon0_out_vga>; }; }; port@1 { - #address-cells = <1>; - #size-cells = <0>; reg = <1>; - vga_dac_out: endpoint@0 { - reg = <0>; + vga_dac_out: endpoint { remote-endpoint = <&vga_con_in>; }; }; diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 13304b8c5139..2445b51dec14 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -491,8 +491,6 @@ }; hdmi_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; reg = <1>; }; }; @@ -1229,12 +1227,9 @@ }; be0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; reg = <1>; - be0_out_drc0: endpoint@0 { - reg = <0>; + be0_out_drc0: endpoint { remote-endpoint = <&drc0_in_be0>; }; }; @@ -1259,12 +1254,9 @@ #size-cells = <0>; drc0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; reg = <0>; - drc0_in_be0: endpoint@0 { - reg = <0>; + drc0_in_be0: endpoint { remote-endpoint = <&be0_out_drc0>; }; }; -- cgit From 5bab80efb750722e8d0cdb8144511a4957b2a1d6 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 14 Mar 2019 21:16:29 +0100 Subject: ARM: dts: sun8i: a23/a33: Fix Display Engine DTC warnings Our display engine endpoints trigger some DTC warnings due to the fact that we're having a single endpoint that doesn't need any reg property, and since we don't have a reg property, we don't need the address-cells and size-cells properties anymore. Fix those Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 32 +++++--------------------- arch/arm/boot/dts/sun8i-a23-q8-tablet.dts | 6 +++++ arch/arm/boot/dts/sun8i-a33-q8-tablet.dts | 7 ++++++ arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 11 ++------- arch/arm/boot/dts/sun8i-a33.dtsi | 18 +++++---------- arch/arm/boot/dts/sun8i-q8-common.dtsi | 18 ++------------- 6 files changed, 29 insertions(+), 63 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index 14a7d0288b45..396d32cfff36 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -194,19 +194,14 @@ #size-cells = <0>; tcon0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; reg = <0>; - tcon0_in_drc0: endpoint@0 { - reg = <0>; + tcon0_in_drc0: endpoint { remote-endpoint = <&drc0_out_tcon0>; }; }; tcon0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; reg = <1>; }; }; @@ -629,12 +624,9 @@ #size-cells = <0>; fe0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; reg = <1>; - fe0_out_be0: endpoint@0 { - reg = <0>; + fe0_out_be0: endpoint { remote-endpoint = <&be0_in_fe0>; }; }; @@ -656,23 +648,17 @@ #size-cells = <0>; be0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; reg = <0>; - be0_in_fe0: endpoint@0 { - reg = <0>; + be0_in_fe0: endpoint { remote-endpoint = <&fe0_out_be0>; }; }; be0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; reg = <1>; - be0_out_drc0: endpoint@0 { - reg = <0>; + be0_out_drc0: endpoint { remote-endpoint = <&drc0_in_be0>; }; }; @@ -696,23 +682,17 @@ #size-cells = <0>; drc0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; reg = <0>; - drc0_in_be0: endpoint@0 { - reg = <0>; + drc0_in_be0: endpoint { remote-endpoint = <&be0_out_drc0>; }; }; drc0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; reg = <1>; - drc0_out_tcon0: endpoint@0 { - reg = <0>; + drc0_out_tcon0: endpoint { remote-endpoint = <&tcon0_in_drc0>; }; }; diff --git a/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts b/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts index d4dab7c28398..5659c63d7d77 100644 --- a/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts +++ b/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts @@ -65,3 +65,9 @@ &panel { compatible = "bananapi,s070wv20-ct16", "simple-panel"; }; + +&tcon0_out { + tcon0_out_lcd: endpoint { + remote-endpoint = <&panel_input>; + }; +}; diff --git a/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts b/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts index b0bc2360f8c4..9c5750c25613 100644 --- a/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts +++ b/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts @@ -48,3 +48,10 @@ model = "Q8 A33 Tablet"; compatible = "allwinner,q8-a33", "allwinner,sun8i-a33"; }; + +&tcon0_out { + tcon0_out_lcd: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_input>; + }; +}; diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts index f3667268adde..785798e3a104 100644 --- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts +++ b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts @@ -63,16 +63,9 @@ panel { compatible = "netron-dy,e231732"; - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - panel_input: endpoint@0 { - reg = <0>; + port { + panel_input: endpoint { remote-endpoint = <&tcon0_out_panel>; }; }; diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index 1111a6498102..4484d76c88b5 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -266,18 +266,9 @@ phy-names = "dphy"; status = "disabled"; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - dsi_in_tcon0: endpoint { - remote-endpoint = <&tcon0_out_dsi>; - }; + port { + dsi_in_tcon0: endpoint { + remote-endpoint = <&tcon0_out_dsi>; }; }; }; @@ -420,6 +411,9 @@ }; &tcon0_out { + #address-cells = <1>; + #size-cells = <0>; + tcon0_out_dsi: endpoint@1 { reg = <1>; remote-endpoint = <&dsi_in_tcon0>; diff --git a/arch/arm/boot/dts/sun8i-q8-common.dtsi b/arch/arm/boot/dts/sun8i-q8-common.dtsi index 53104f4ccacc..3d9a1524e17e 100644 --- a/arch/arm/boot/dts/sun8i-q8-common.dtsi +++ b/arch/arm/boot/dts/sun8i-q8-common.dtsi @@ -54,16 +54,9 @@ backlight = <&backlight>; enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ power-supply = <®_dc1sw>; - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - panel_input: endpoint@0 { - reg = <0>; + port { + panel_input: endpoint { remote-endpoint = <&tcon0_out_lcd>; }; }; @@ -120,13 +113,6 @@ status = "okay"; }; -&tcon0_out { - tcon0_out_lcd: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; -}; - &usbphy { usb1_vbus-supply = <®_dldo1>; }; -- cgit From f79d79534dba544678343275e0459bb1a675cbea Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 14 Mar 2019 21:16:30 +0100 Subject: ARM: dts: sun8i: v3s: Fix Display Engine DTC warnings Our display engine endpoints trigger some DTC warnings due to the fact that we're having a single endpoint that doesn't need any reg property, and since we don't have a reg property, we don't need the address-cells and size-cells properties anymore. Fix those Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-v3s.dtsi | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 21e1806ca509..7918064e0940 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -129,12 +129,9 @@ #size-cells = <0>; mixer0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; reg = <1>; - mixer0_out_tcon0: endpoint@0 { - reg = <0>; + mixer0_out_tcon0: endpoint { remote-endpoint = <&tcon0_in_mixer0>; }; }; @@ -159,12 +156,9 @@ #size-cells = <0>; tcon0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; reg = <0>; - tcon0_in_mixer0: endpoint@0 { - reg = <0>; + tcon0_in_mixer0: endpoint { remote-endpoint = <&mixer0_out_tcon0>; }; }; -- cgit From 56975bfbb7fbdfaacd79e3522576302c07956593 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 14 Mar 2019 21:16:31 +0100 Subject: ARM: dts: sun8i: a83t: Fix Display Engine DTC warnings Our display engine endpoints trigger some DTC warnings due to the fact that we're having a single endpoint that doesn't need any reg property, and since we don't have a reg property, we don't need the address-cells and size-cells properties anymore. Fix those Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 3 +-- arch/arm/boot/dts/sun8i-a83t.dtsi | 2 -- 2 files changed, 1 insertion(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts index 98e8cea26dbe..4bda2f9372cb 100644 --- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts +++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts @@ -391,8 +391,7 @@ }; &tcon0_out { - tcon0_out_lcd: endpoint@0 { - reg = <0>; + tcon0_out_lcd: endpoint { remote-endpoint = <&panel_input>; }; }; diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 7651b6dcfd0f..7340b01c1994 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -457,8 +457,6 @@ }; tcon0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; reg = <1>; }; }; -- cgit From 109b7bfa777b513bb751bb208f9d9286ffc6a4d3 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 14 Mar 2019 21:16:32 +0100 Subject: ARM: dts: sun8i: r40: Fix Display Engine DTC warnings Our display engine endpoints trigger some DTC warnings due to the fact that we're having a single endpoint that doesn't need any reg property, and since we don't have a reg property, we don't need the address-cells and size-cells properties anymore. Fix those Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-r40.dtsi | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index 06b685869f52..1061d46efafd 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -614,12 +614,9 @@ #size-cells = <0>; tcon_top_mixer0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; reg = <0>; - tcon_top_mixer0_in_mixer0: endpoint@0 { - reg = <0>; + tcon_top_mixer0_in_mixer0: endpoint { remote-endpoint = <&mixer0_out_tcon_top>; }; }; -- cgit From c4953ba1eddde084ddca25ec7cec994b4f3b7e42 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 14 Mar 2019 21:16:33 +0100 Subject: ARM: dts: sun9i: Fix Display Engine DTC warnings Our display engine endpoints trigger some DTC warnings due to the fact that we're having a single endpoint that doesn't need any reg property, and since we don't have a reg property, we don't need the address-cells and size-cells properties anymore. Fix those Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80-cubieboard4.dts | 15 ++----- arch/arm/boot/dts/sun9i-a80.dtsi | 64 ++++++----------------------- 2 files changed, 15 insertions(+), 64 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts index 28c034928d67..18156ffa3ce9 100644 --- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts +++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts @@ -89,31 +89,23 @@ vga-dac { compatible = "corpro,gm7123", "adi,adv7123", "dumb-vga-dac"; vdd-supply = <®_dcdc1>; - #address-cells = <1>; - #size-cells = <0>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { - #address-cells = <1>; - #size-cells = <0>; reg = <0>; - vga_dac_in: endpoint@0 { - reg = <0>; + vga_dac_in: endpoint { remote-endpoint = <&tcon0_out_vga>; }; }; port@1 { - #address-cells = <1>; - #size-cells = <0>; reg = <1>; - vga_dac_out: endpoint@0 { - reg = <0>; + vga_dac_out: endpoint { remote-endpoint = <&vga_con_in>; }; }; @@ -502,8 +494,7 @@ }; &tcon0_out { - tcon0_out_vga: endpoint@0 { - reg = <0>; + tcon0_out_vga: endpoint { remote-endpoint = <&vga_dac_in>; }; }; diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index 6fb292e0b662..9b15f272e5f5 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -596,12 +596,9 @@ #size-cells = <0>; fe0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; reg = <1>; - fe0_out_deu0: endpoint@0 { - reg = <0>; + fe0_out_deu0: endpoint { remote-endpoint = <&deu0_in_fe0>; }; }; @@ -623,12 +620,9 @@ #size-cells = <0>; fe1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; reg = <1>; - fe1_out_deu1: endpoint@0 { - reg = <0>; + fe1_out_deu1: endpoint { remote-endpoint = <&deu1_in_fe1>; }; }; @@ -666,12 +660,9 @@ }; be0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; reg = <1>; - be0_out_drc0: endpoint@0 { - reg = <0>; + be0_out_drc0: endpoint { remote-endpoint = <&drc0_in_be0>; }; }; @@ -709,12 +700,9 @@ }; be1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; reg = <1>; - be1_out_drc1: endpoint@0 { - reg = <0>; + be1_out_drc1: endpoint { remote-endpoint = <&drc1_in_be1>; }; }; @@ -738,12 +726,9 @@ #size-cells = <0>; deu0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; reg = <0>; - deu0_in_fe0: endpoint@0 { - reg = <0>; + deu0_in_fe0: endpoint { remote-endpoint = <&fe0_out_deu0>; }; }; @@ -783,12 +768,9 @@ #size-cells = <0>; deu1_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; reg = <0>; - deu1_in_fe1: endpoint@0 { - reg = <0>; + deu1_in_fe1: endpoint { remote-endpoint = <&fe1_out_deu1>; }; }; @@ -828,23 +810,17 @@ #size-cells = <0>; drc0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; reg = <0>; - drc0_in_be0: endpoint@0 { - reg = <0>; + drc0_in_be0: endpoint { remote-endpoint = <&be0_out_drc0>; }; }; drc0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; reg = <1>; - drc0_out_tcon0: endpoint@0 { - reg = <0>; + drc0_out_tcon0: endpoint { remote-endpoint = <&tcon0_in_drc0>; }; }; @@ -868,23 +844,17 @@ #size-cells = <0>; drc1_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; reg = <0>; - drc1_in_be1: endpoint@0 { - reg = <0>; + drc1_in_be1: endpoint { remote-endpoint = <&be1_out_drc1>; }; }; drc1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; reg = <1>; - drc1_out_tcon1: endpoint@0 { - reg = <0>; + drc1_out_tcon1: endpoint { remote-endpoint = <&tcon1_in_drc1>; }; }; @@ -906,19 +876,14 @@ #size-cells = <0>; tcon0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; reg = <0>; - tcon0_in_drc0: endpoint@0 { - reg = <0>; + tcon0_in_drc0: endpoint { remote-endpoint = <&drc0_out_tcon0>; }; }; tcon0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; reg = <1>; }; }; @@ -938,19 +903,14 @@ #size-cells = <0>; tcon1_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; reg = <0>; - tcon1_in_drc1: endpoint@0 { - reg = <0>; + tcon1_in_drc1: endpoint { remote-endpoint = <&drc1_out_tcon1>; }; }; tcon1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; reg = <1>; }; }; -- cgit From 927489b1570e12803324bf753173e36b82b02be7 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 14 Mar 2019 21:16:34 +0100 Subject: ARM: dts: sun9i: Add missing unit address The soc node in the A80 DTSI has a ranges property, but no matching unit address, which results in a DTC warning. Add the unit address to remove that warning. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index 9b15f272e5f5..7a495c84ab65 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -289,7 +289,7 @@ status = "disabled"; }; - soc { + soc@20000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; -- cgit From 4f6faf7864481b81fe90a5c98c48dbe50cdd9349 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 18 Mar 2019 11:26:02 +0100 Subject: ARM: dts: sun8i: a33: Add default address and size cells to the DSI node The DSI bindings require that an address cell size of 1, and a size cell of 0. Instead of duplicating it in each and every board DTS file, let's put it in the DTSI. Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a33.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index 4484d76c88b5..1532a0e59af4 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -265,6 +265,8 @@ phys = <&dphy>; phy-names = "dphy"; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; port { dsi_in_tcon0: endpoint { -- cgit From ebc42b478b0c9a6d69a0edebc9182d9ec302f603 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 18 Mar 2019 13:56:13 +0100 Subject: ARM: dts: sun8i: a23/a33: Add R_I2C Controller The A23 and A33 both have an I2C controller in the ARISC domain, that share the same pins with the RSB bus. Even if it's an unusual configuration, that device can be used to drive the PMIC, so let's use it. Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index 396d32cfff36..5d2c438e5959 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -781,6 +781,20 @@ status = "disabled"; }; + r_i2c: i2c@1f02400 { + compatible = "allwinner,sun8i-a23-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x01f02400 0x400>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&r_i2c_pins>; + clocks = <&apb0_gates 6>; + resets = <&apb0_rst 6>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + r_pio: pinctrl@1f02c00 { compatible = "allwinner,sun8i-a23-r-pinctrl"; reg = <0x01f02c00 0x400>; @@ -793,6 +807,12 @@ #interrupt-cells = <3>; #gpio-cells = <3>; + r_i2c_pins: r-i2c-pins { + pins = "PL0", "PL1"; + function = "s_i2c"; + bias-pull-up; + }; + r_rsb_pins: r-rsb-pins { pins = "PL0", "PL1"; function = "s_rsb"; -- cgit From c2a5b554751545023056559121a8ecf86aebe541 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 25 Mar 2019 14:52:34 +0100 Subject: ARM: dts: sun9i: optimus: Fix fixed-regulators Commit 1848f3f44444 ("ARM: dts: sun9i: Remove GPIO pinctrl nodes to avoid warnings") was wrong on the optimus, and instead of droping the pinctrl-names property, it dropped the regulator-name one. Obviously, that wasn't what was intended. Reinstate regulator-name and drop pinctrl-names. Fixes: 1848f3f44444 ("ARM: dts: sun9i: Remove GPIO pinctrl nodes to avoid warnings") Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80-optimus.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts index 864715ec3cb0..2ed28d9e2787 100644 --- a/arch/arm/boot/dts/sun9i-a80-optimus.dts +++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts @@ -82,7 +82,7 @@ reg_usb1_vbus: usb1-vbus { compatible = "regulator-fixed"; - pinctrl-names = "default"; + regulator-name = "usb1-vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; @@ -91,7 +91,7 @@ reg_usb3_vbus: usb3-vbus { compatible = "regulator-fixed"; - pinctrl-names = "default"; + regulator-name = "usb3-vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; -- cgit From 1cf0444a23fa690539175bb3fb9c66f27e81a153 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 25 Mar 2019 14:52:36 +0100 Subject: ARM: dts: sun5i: lichee-pi one: Remove stale pinctrl-names entry Some nodes still have pinctrl-names entry, yet they don't have any pinctrl group anymore. Drop them. Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-a13-licheepi-one.dts | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts b/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts index ca8f3fd1ddfe..9231294a8fa1 100644 --- a/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts +++ b/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts @@ -206,7 +206,6 @@ }; &usbphy { - pinctrl-names = "default"; usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ usb0_vbus-supply = <®_usb0_vbus>; -- cgit From 5400cdc1410b25321235d9e52a092a6132168c74 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 25 Mar 2019 14:52:37 +0100 Subject: ARM: dts: sunxi: Fix GIC compatible As can be shown by the YAML schema now, the combination of GIC compatibles we were using has never been an option. Switch to the gic-400 variant, which is the more correct option. Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 2 +- arch/arm/boot/dts/sun7i-a20.dtsi | 2 +- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +- arch/arm/boot/dts/sun8i-a83t.dtsi | 2 +- arch/arm/boot/dts/sun8i-v3s.dtsi | 2 +- arch/arm/boot/dts/sun9i-a80.dtsi | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 2445b51dec14..2bc273ce2fe4 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -1027,7 +1027,7 @@ }; gic: interrupt-controller@1c81000 { - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + compatible = "arm,gic-400"; reg = <0x01c81000 0x1000>, <0x01c82000 0x2000>, <0x01c84000 0x2000>, diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 792897a1a215..c153ded1a275 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -1453,7 +1453,7 @@ }; gic: interrupt-controller@1c81000 { - compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + compatible = "arm,gic-400"; reg = <0x01c81000 0x1000>, <0x01c82000 0x2000>, <0x01c84000 0x2000>, diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index 5d2c438e5959..1c1320cfd546 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -599,7 +599,7 @@ }; gic: interrupt-controller@1c81000 { - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + compatible = "arm,gic-400"; reg = <0x01c81000 0x1000>, <0x01c82000 0x2000>, <0x01c84000 0x2000>, diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 7340b01c1994..2d06070bd2bf 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -931,7 +931,7 @@ }; gic: interrupt-controller@1c81000 { - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + compatible = "arm,gic-400"; reg = <0x01c81000 0x1000>, <0x01c82000 0x2000>, <0x01c84000 0x2000>, diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 7918064e0940..ebb496bc8cf5 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -413,7 +413,7 @@ }; gic: interrupt-controller@1c81000 { - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + compatible = "arm,gic-400"; reg = <0x01c81000 0x1000>, <0x01c82000 0x1000>, <0x01c84000 0x2000>, diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index 7a495c84ab65..7ac1e50808a2 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -527,7 +527,7 @@ }; gic: interrupt-controller@1c41000 { - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + compatible = "arm,gic-400"; reg = <0x01c41000 0x1000>, <0x01c42000 0x2000>, <0x01c44000 0x2000>, -- cgit From 0c64f75d89cb57eb4b9e956251dd87ee8e080563 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 25 Mar 2019 14:52:38 +0100 Subject: ARM: dts: sunxi: Switch to new GPIOs properties for i2c-gpio The i2c-gpio driver uses named gpios now and the array of GPIOs is deprecated. Switch to the new binding. Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-a13-utoo-p66.dts | 6 +++--- arch/arm/boot/dts/sun6i-a31-colombus.dts | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts index 732873cbeedc..379d530ea2a7 100644 --- a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts +++ b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts @@ -58,13 +58,13 @@ /delete-property/stdout-path; }; - i2c_lcd: i2c-gpio { + i2c_lcd: i2c { /* The lcd panel i2c interface is hooked up via gpios */ compatible = "i2c-gpio"; pinctrl-names = "default"; pinctrl-0 = <&i2c_lcd_pins>; - gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>, /* PG12, sda */ - <&pio 6 10 GPIO_ACTIVE_HIGH>; /* PG10, scl */ + sda-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + scl-gpios = <&pio 6 10 GPIO_ACTIVE_HIGH>; /* PG10 */ i2c-gpio,delay-us = <5>; }; }; diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/sun6i-a31-colombus.dts index 0b7bedf85fb9..0e62b4042100 100644 --- a/arch/arm/boot/dts/sun6i-a31-colombus.dts +++ b/arch/arm/boot/dts/sun6i-a31-colombus.dts @@ -65,8 +65,8 @@ compatible = "i2c-gpio"; pinctrl-names = "default"; pinctrl-0 = <&i2c_lcd_pins>; - gpios = <&pio 0 23 GPIO_ACTIVE_HIGH>, /* PA23, sda */ - <&pio 0 24 GPIO_ACTIVE_HIGH>; /* PA24, scl */ + sda-gpios = <&pio 0 23 GPIO_ACTIVE_HIGH>; /* PA23 */ + scl-gpios = <&pio 0 24 GPIO_ACTIVE_HIGH>; /* PA24 */ i2c-gpio,delay-us = <5>; }; }; -- cgit From 2c515b0d05a9894af288a71aa6e6ed7d1d8ef32f Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 25 Mar 2019 14:52:39 +0100 Subject: ARM: sunxi: Fix the USB PHY ID detect GPIO properties While the USB PHY Device Tree mandates that the name of the ID detect pin should be usb0_id_det-gpios, a significant number of device tree use usb0_id_det-gpio instead. This was functional because the GPIO framework falls back to the gpio suffix that is legacy, but we should fix this. Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts | 2 +- arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 2 +- arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts | 2 +- arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts | 2 +- arch/arm/boot/dts/sun4i-a10-inet1.dts | 2 +- arch/arm/boot/dts/sun4i-a10-inet97fv2.dts | 2 +- arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts | 2 +- arch/arm/boot/dts/sun4i-a10-marsboard.dts | 2 +- arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts | 2 +- arch/arm/boot/dts/sun4i-a10-pcduino.dts | 2 +- arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts | 2 +- arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts | 2 +- arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 2 +- arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts | 2 +- arch/arm/boot/dts/sun5i-a13-licheepi-one.dts | 2 +- arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts | 2 +- arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 2 +- arch/arm/boot/dts/sun5i-gr8-chip-pro.dts | 2 +- arch/arm/boot/dts/sun5i-gr8-evb.dts | 2 +- arch/arm/boot/dts/sun5i-r8-chip.dts | 2 +- arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi | 2 +- arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 2 +- arch/arm/boot/dts/sun6i-a31s-primo81.dts | 2 +- arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi | 2 +- arch/arm/boot/dts/sun7i-a20-bananapi.dts | 2 +- arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 2 +- arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts | 2 +- arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts | 2 +- arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts | 2 +- arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts | 2 +- arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 2 +- arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts | 2 +- arch/arm/boot/dts/sun7i-a20-orangepi.dts | 2 +- arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts | 2 +- arch/arm/boot/dts/sun7i-a20-pcduino3.dts | 2 +- arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts | 2 +- arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts | 2 +- arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi | 2 +- arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 2 +- 39 files changed, 39 insertions(+), 39 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts b/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts index cf7b392dff31..9bfd3804b968 100644 --- a/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts +++ b/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts @@ -167,7 +167,7 @@ &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts index 197a1f2b75ff..d5eb2a151b89 100644 --- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts +++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts @@ -256,7 +256,7 @@ &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts b/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts index 896e27a08727..13a49230893c 100644 --- a/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts +++ b/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts @@ -225,7 +225,7 @@ &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts b/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts index f63767cddd8e..aa86e39fa9cc 100644 --- a/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts +++ b/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts @@ -123,7 +123,7 @@ &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun4i-a10-inet1.dts b/arch/arm/boot/dts/sun4i-a10-inet1.dts index 26d0c1d6a02b..574ecfaa8c3d 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet1.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet1.dts @@ -235,7 +235,7 @@ &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; diff --git a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts index 71c27ea0b53e..94ee70f38af5 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts @@ -211,7 +211,7 @@ &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts index 2f0d966f39ad..bfa265b582c6 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts @@ -377,7 +377,7 @@ &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun4i-a10-marsboard.dts b/arch/arm/boot/dts/sun4i-a10-marsboard.dts index 0dbf69576512..cb94e083ea3b 100644 --- a/arch/arm/boot/dts/sun4i-a10-marsboard.dts +++ b/arch/arm/boot/dts/sun4i-a10-marsboard.dts @@ -185,7 +185,7 @@ &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts index b74a61496537..f552304b8593 100644 --- a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts +++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts @@ -231,7 +231,7 @@ &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts index d82a604f3d9c..08f3e385fe63 100644 --- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts +++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts @@ -203,7 +203,7 @@ &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ usb1_vbus-supply = <®_vcc5v0>; /* USB1 VBUS is always on */ usb2_vbus-supply = <®_vcc5v0>; /* USB2 VBUS is always on */ status = "okay"; diff --git a/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts b/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts index 84b25be1ac94..d543db54116d 100644 --- a/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts +++ b/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts @@ -213,7 +213,7 @@ &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; diff --git a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts index c88f08984483..6d7a2f4bd05c 100644 --- a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts +++ b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts @@ -151,7 +151,7 @@ &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts index 262c2ffbdcfa..430caf873fe2 100644 --- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts @@ -273,7 +273,7 @@ &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts index f3cede9beb63..82c89575a1c3 100644 --- a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts +++ b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts @@ -197,7 +197,7 @@ &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ + usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_ldo3>; diff --git a/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts b/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts index 9231294a8fa1..359983d3d59d 100644 --- a/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts +++ b/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts @@ -206,7 +206,7 @@ }; &usbphy { - usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ + usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_vcc5v0>; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts index 943868e495bc..f1b1e6f99777 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts @@ -147,7 +147,7 @@ &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ + usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts index 54ca140fc258..8948ef24616d 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts @@ -253,7 +253,7 @@ &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ + usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; diff --git a/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts b/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts index 3f70b8c53132..533a4ecc05e2 100644 --- a/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts +++ b/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts @@ -233,7 +233,7 @@ }; &usbphy { - usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ + usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ usb0_vbus_power-supply = <&usb_power_supply>; usb1_vbus-supply = <®_vcc5v0>; status = "okay"; diff --git a/arch/arm/boot/dts/sun5i-gr8-evb.dts b/arch/arm/boot/dts/sun5i-gr8-evb.dts index 86e46aa59134..29cadd9576d1 100644 --- a/arch/arm/boot/dts/sun5i-gr8-evb.dts +++ b/arch/arm/boot/dts/sun5i-gr8-evb.dts @@ -325,7 +325,7 @@ }; &usbphy { - usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ + usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ usb0_vbus_power-supply = <&usb_power_supply>; usb1_vbus-supply = <®_usb1_vbus>; diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts index f4298facf9dc..de5e67497f20 100644 --- a/arch/arm/boot/dts/sun5i-r8-chip.dts +++ b/arch/arm/boot/dts/sun5i-r8-chip.dts @@ -279,7 +279,7 @@ &usbphy { status = "okay"; - usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ + usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ usb0_vbus_power-supply = <&usb_power_supply>; usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_vcc5v0>; diff --git a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi index 5b1f0e198eb6..8ed381ada577 100644 --- a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi @@ -200,7 +200,7 @@ &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ + usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ usb0_vbus_power-supply = <&usb_power_supply>; usb0_vbus-supply = <®_usb0_vbus>; diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts index 63b84327f4e9..03ae33acfb01 100644 --- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts +++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts @@ -327,7 +327,7 @@ }; &usbphy { - usb0_id_det-gpio = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */ + usb0_id_det-gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */ usb0_vbus_det-gpio = <&pio 0 16 GPIO_ACTIVE_HIGH>; /* PA16 */ usb0_vbus_power-supply = <&usb_power_supply>; usb0_vbus-supply = <®_drivevbus>; diff --git a/arch/arm/boot/dts/sun6i-a31s-primo81.dts b/arch/arm/boot/dts/sun6i-a31s-primo81.dts index 60b355f7184c..bc3170a0b8b5 100644 --- a/arch/arm/boot/dts/sun6i-a31s-primo81.dts +++ b/arch/arm/boot/dts/sun6i-a31s-primo81.dts @@ -260,7 +260,7 @@ }; &usbphy { - usb0_id_det-gpio = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */ + usb0_id_det-gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */ usb0_vbus_power-supply = <&usb_power_supply>; usb0_vbus-supply = <®_drivevbus>; usb1_vbus-supply = <®_dldo1>; diff --git a/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi index 86143de21c22..1ebc042f5e6c 100644 --- a/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi @@ -175,7 +175,7 @@ &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpio = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */ + usb0_id_det-gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */ usb0_vbus_power-supply = <&usb_power_supply>; usb0_vbus-supply = <®_drivevbus>; usb1_vbus-supply = <®_dldo1>; diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi.dts b/arch/arm/boot/dts/sun7i-a20-bananapi.dts index 81bc85d398c1..76252455d485 100644 --- a/arch/arm/boot/dts/sun7i-a20-bananapi.dts +++ b/arch/arm/boot/dts/sun7i-a20-bananapi.dts @@ -331,7 +331,7 @@ &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ usb0_vbus_power-supply = <&usb_power_supply>; usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts index 200685b0b1cb..365ac2b9bcdf 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts @@ -238,7 +238,7 @@ &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts index f91e1bee44e8..0a87a45787ae 100644 --- a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts +++ b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts @@ -324,7 +324,7 @@ &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ usb0_vbus_power-supply = <&usb_power_supply>; usb0_vbus-supply = <®_usb0_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts index 823aabce0462..cce52699ef3e 100644 --- a/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts +++ b/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts @@ -314,7 +314,7 @@ }; &usbphy { - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ usb0_vbus_power-supply = <&usb_power_supply>; usb0_vbus-supply = <®_usb0_vbus>; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts index 5e411194bf62..53043f31fd39 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts @@ -219,7 +219,7 @@ &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts index 3de479bfa4cf..bd514cb9e8e9 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts @@ -275,7 +275,7 @@ &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts index 840ae1194a66..cfbf7f9feb6d 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts @@ -357,7 +357,7 @@ &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; diff --git a/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts b/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts index 15881081cac4..872f6f35d40d 100644 --- a/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts +++ b/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts @@ -241,7 +241,7 @@ &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ usb0_vbus_power-supply = <&usb_power_supply>; usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; diff --git a/arch/arm/boot/dts/sun7i-a20-orangepi.dts b/arch/arm/boot/dts/sun7i-a20-orangepi.dts index d64de2e73a9f..93fa89b84a88 100644 --- a/arch/arm/boot/dts/sun7i-a20-orangepi.dts +++ b/arch/arm/boot/dts/sun7i-a20-orangepi.dts @@ -200,7 +200,7 @@ &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ usb0_vbus_power-supply = <&usb_power_supply>; usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts index 538ea15fa32f..24781f5c231e 100644 --- a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts +++ b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts @@ -228,7 +228,7 @@ &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb1_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts index a72ed4318d04..606630ac5f3a 100644 --- a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts +++ b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts @@ -228,7 +228,7 @@ &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts b/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts index ffade253d129..80ead52db270 100644 --- a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts +++ b/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts @@ -225,7 +225,7 @@ &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ usb0_vbus_power-supply = <&usb_power_supply>; usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; diff --git a/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts b/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts index c27e56091fb1..57a4d6a5d163 100644 --- a/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts +++ b/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts @@ -208,7 +208,7 @@ &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ usb0_vbus_power-supply = <&usb_power_supply>; usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; diff --git a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi index 189e479eb95a..c773ddf45e66 100644 --- a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi @@ -226,7 +226,7 @@ &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpio = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */ + usb0_id_det-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */ usb0_vbus_power-supply = <&usb_power_supply>; usb0_vbus-supply = <®_drivevbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts index 99c8cf7bb86c..2e4587d26ce5 100644 --- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts +++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts @@ -96,6 +96,6 @@ }; &usbphy { - usb0_id_det-gpio = <&pio 5 6 GPIO_ACTIVE_HIGH>; + usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; status = "okay"; }; -- cgit From 033914f877e8d1febf802242174a62ce566a5901 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 25 Mar 2019 14:52:40 +0100 Subject: ARM: sunxi: Fix the USB PHY VBUS detect GPIO properties While the USB PHY Device Tree mandates that the name of the VBUS detect pin should be usb0_vbus_det-gpios, a significant number of device tree use usb0_vbus_det-gpio instead. This was functional because the GPIO framework falls back to the gpio suffix that is legacy, but we should fix this. Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts | 2 +- arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts | 2 +- arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts | 2 +- arch/arm/boot/dts/sun4i-a10-inet1.dts | 2 +- arch/arm/boot/dts/sun4i-a10-inet97fv2.dts | 2 +- arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts | 2 +- arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts | 2 +- arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts | 2 +- arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts | 2 +- arch/arm/boot/dts/sun5i-a13-licheepi-one.dts | 2 +- arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts | 2 +- arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 2 +- arch/arm/boot/dts/sun5i-gr8-evb.dts | 2 +- arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi | 2 +- arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 2 +- arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts | 2 +- arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts | 2 +- arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts | 2 +- arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 2 +- 19 files changed, 19 insertions(+), 19 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts b/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts index 9bfd3804b968..66555e437ce4 100644 --- a/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts +++ b/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts @@ -168,7 +168,7 @@ pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts b/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts index 13a49230893c..f7af24cb66e7 100644 --- a/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts +++ b/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts @@ -226,7 +226,7 @@ pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts b/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts index aa86e39fa9cc..0cf752a990b9 100644 --- a/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts +++ b/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts @@ -124,7 +124,7 @@ pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun4i-a10-inet1.dts b/arch/arm/boot/dts/sun4i-a10-inet1.dts index 574ecfaa8c3d..2e5c452ca9c6 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet1.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet1.dts @@ -236,7 +236,7 @@ pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts index 94ee70f38af5..c1ff846cb442 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts @@ -212,7 +212,7 @@ pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts index bfa265b582c6..31ba7b93df51 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts @@ -378,7 +378,7 @@ pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts index f552304b8593..4cbc58363caf 100644 --- a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts +++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts @@ -232,7 +232,7 @@ pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts b/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts index d543db54116d..cd516543a9e5 100644 --- a/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts +++ b/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts @@ -214,7 +214,7 @@ pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts index 82c89575a1c3..ac3b2221cdef 100644 --- a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts +++ b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts @@ -198,7 +198,7 @@ pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ - usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ + usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_ldo3>; status = "okay"; diff --git a/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts b/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts index 359983d3d59d..ba8d75b3c716 100644 --- a/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts +++ b/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts @@ -207,7 +207,7 @@ &usbphy { usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ - usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ + usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_vcc5v0>; status = "okay"; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts index f1b1e6f99777..f8dc4bbf249c 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts @@ -148,7 +148,7 @@ pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ - usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ + usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts index 8948ef24616d..e49596c721a9 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts @@ -254,7 +254,7 @@ pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ - usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ + usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun5i-gr8-evb.dts b/arch/arm/boot/dts/sun5i-gr8-evb.dts index 29cadd9576d1..d003b895a696 100644 --- a/arch/arm/boot/dts/sun5i-gr8-evb.dts +++ b/arch/arm/boot/dts/sun5i-gr8-evb.dts @@ -326,7 +326,7 @@ &usbphy { usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ - usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ + usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ usb0_vbus_power-supply = <&usb_power_supply>; usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi index 8ed381ada577..cf33ad09ef1e 100644 --- a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi @@ -201,7 +201,7 @@ pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ - usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ + usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ usb0_vbus_power-supply = <&usb_power_supply>; usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_ldo3>; diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts index 03ae33acfb01..09832b4e8fc8 100644 --- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts +++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts @@ -328,7 +328,7 @@ &usbphy { usb0_id_det-gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */ - usb0_vbus_det-gpio = <&pio 0 16 GPIO_ACTIVE_HIGH>; /* PA16 */ + usb0_vbus_det-gpios = <&pio 0 16 GPIO_ACTIVE_HIGH>; /* PA16 */ usb0_vbus_power-supply = <&usb_power_supply>; usb0_vbus-supply = <®_drivevbus>; usb1_vbus-supply = <®_usb1_vbus>; diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts index cce52699ef3e..c34a83f666c7 100644 --- a/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts +++ b/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts @@ -315,7 +315,7 @@ &usbphy { usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ usb0_vbus_power-supply = <&usb_power_supply>; usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts index 53043f31fd39..fafe01ee5ea0 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts @@ -220,7 +220,7 @@ pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts index bd514cb9e8e9..bdf894c054db 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts @@ -276,7 +276,7 @@ pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts index cfbf7f9feb6d..ba18e14fa229 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts @@ -358,7 +358,7 @@ pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; -- cgit From 09f29dcc22d5d465b52bbe95c09d0315e23c787b Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 25 Mar 2019 14:52:41 +0100 Subject: ARM: dts: sunxi: Fix the TCON output clock Even though we shouldn't really have any external user of the clock provided by the TCON, if clock-output-names is set, then #clock-cells must be there as well. Fix this. Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 2 ++ arch/arm/boot/dts/sun5i.dtsi | 1 + arch/arm/boot/dts/sun6i-a31.dtsi | 2 ++ arch/arm/boot/dts/sun7i-a20.dtsi | 2 ++ arch/arm/boot/dts/sun8i-a23-a33.dtsi | 1 + arch/arm/boot/dts/sun8i-a83t.dtsi | 1 + arch/arm/boot/dts/sun8i-v3s.dtsi | 1 + arch/arm/boot/dts/sun9i-a80.dtsi | 1 + 8 files changed, 11 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 73c3ac42095f..5cd26ad40a26 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -342,6 +342,7 @@ "tcon-ch0", "tcon-ch1"; clock-output-names = "tcon0-pixel-clock"; + #clock-cells = <0>; dmas = <&dma SUN4I_DMA_DEDICATED 14>; ports { @@ -391,6 +392,7 @@ "tcon-ch0", "tcon-ch1"; clock-output-names = "tcon1-pixel-clock"; + #clock-cells = <0>; dmas = <&dma SUN4I_DMA_DEDICATED 15>; ports { diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index ccd793795e58..49ba494400e6 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -275,6 +275,7 @@ "tcon-ch0", "tcon-ch1"; clock-output-names = "tcon-pixel-clock"; + #clock-cells = <0>; status = "disabled"; ports { diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 2bc273ce2fe4..e8eebc60787c 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -292,6 +292,7 @@ "tcon-ch0", "tcon-ch1"; clock-output-names = "tcon0-pixel-clock"; + #clock-cells = <0>; ports { #address-cells = <1>; @@ -340,6 +341,7 @@ "tcon-ch0", "tcon-ch1"; clock-output-names = "tcon1-pixel-clock"; + #clock-cells = <0>; ports { #address-cells = <1>; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index c153ded1a275..767509809d06 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -406,6 +406,7 @@ "tcon-ch0", "tcon-ch1"; clock-output-names = "tcon0-pixel-clock"; + #clock-cells = <0>; dmas = <&dma SUN4I_DMA_DEDICATED 14>; ports { @@ -455,6 +456,7 @@ "tcon-ch0", "tcon-ch1"; clock-output-names = "tcon1-pixel-clock"; + #clock-cells = <0>; dmas = <&dma SUN4I_DMA_DEDICATED 15>; ports { diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index 1c1320cfd546..9be25db7a275 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -185,6 +185,7 @@ clock-names = "ahb", "tcon-ch0"; clock-output-names = "tcon-pixel-clock"; + #clock-cells = <0>; resets = <&ccu RST_BUS_LCD>; reset-names = "lcd"; status = "disabled"; diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 2d06070bd2bf..ad4931b1b19b 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -433,6 +433,7 @@ clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; clock-names = "ahb", "tcon-ch0"; clock-output-names = "tcon-pixel-clock"; + #clock-cells = <0>; resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; reset-names = "lcd", "lvds"; diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index ebb496bc8cf5..df72b1719c34 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -147,6 +147,7 @@ clock-names = "ahb", "tcon-ch0"; clock-output-names = "tcon-pixel-clock"; + #clock-cells = <0>; resets = <&ccu RST_BUS_TCON0>; reset-names = "lcd"; status = "disabled"; diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index 7ac1e50808a2..a991f689b99a 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -870,6 +870,7 @@ resets = <&ccu RST_BUS_LCD0>, <&ccu RST_BUS_EDP>; reset-names = "lcd", "edp"; clock-output-names = "tcon0-pixel-clock"; + #clock-cells = <0>; ports { #address-cells = <1>; -- cgit From 939b6654344c8b37399adfea12018b10a53c67de Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 25 Mar 2019 14:52:42 +0100 Subject: ARM: dts: sun8i: tbs-a711: Fix typo in regulators The regulator properties suffix is -supply, yet a _supply slipped in. This was working because the regulator framework will provide a dummy regulator when none is provided in the device tree, and the regulator itself was always enabled. Fixes: 90c5d7cdae64 ("ARM: dts: sun8i: a711: Add regulator support") Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts index 4bda2f9372cb..1e840ab5a541 100644 --- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts +++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts @@ -417,7 +417,7 @@ &usbphy { usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ usb0_vbus-supply = <®_drivevbus>; - usb1_vbus_supply = <®_vmain>; - usb2_vbus_supply = <®_vmain>; + usb1_vbus-supply = <®_vmain>; + usb2_vbus-supply = <®_vmain>; status = "okay"; }; -- cgit From 655c0f429fff6e17e0d5bde141bc759ed5d1927f Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 25 Mar 2019 14:52:43 +0100 Subject: ARM: sunxi: dts: Split USB PHY cells into an array Even though it doesn't make any difference at the binary level, the reg property is an array of cells, and should be represented as such. Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 2 +- arch/arm/boot/dts/sun5i.dtsi | 2 +- arch/arm/boot/dts/sun7i-a20.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 5cd26ad40a26..f8a67b95c139 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -502,7 +502,7 @@ usbphy: phy@1c13400 { #phy-cells = <1>; compatible = "allwinner,sun4i-a10-usb-phy"; - reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; + reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>; reg-names = "phy_ctrl", "pmu1", "pmu2"; clocks = <&ccu CLK_USB_PHY>; clock-names = "usb_phy"; diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index 49ba494400e6..7dc67cf771c1 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -366,7 +366,7 @@ usbphy: phy@1c13400 { #phy-cells = <1>; compatible = "allwinner,sun5i-a13-usb-phy"; - reg = <0x01c13400 0x10 0x01c14800 0x4>; + reg = <0x01c13400 0x10>, <0x01c14800 0x4>; reg-names = "phy_ctrl", "pmu1"; clocks = <&ccu CLK_USB_PHY0>; clock-names = "usb_phy"; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 767509809d06..f087a7ce95aa 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -594,7 +594,7 @@ usbphy: phy@1c13400 { #phy-cells = <1>; compatible = "allwinner,sun7i-a20-usb-phy"; - reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; + reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>; reg-names = "phy_ctrl", "pmu1", "pmu2"; clocks = <&ccu CLK_USB_PHY>; clock-names = "usb_phy"; -- cgit From b9f6b80e04ad061ff4e12bdb72ea21af3518d79f Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 25 Mar 2019 14:52:44 +0100 Subject: ARM: dts: sun8i: r40: Fix AHCI reset-names property The AHCI node was introduced with a typo in the reset-names property that got written resets-name instead. This was working because the reset is optional for that driver, and the controller was put out of reset by the bootloader. Fixes: 41c64d3318aa ("ARM: dts: sun8i: r40: add sata node") Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-r40.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index 1061d46efafd..9784c23346a8 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -562,7 +562,7 @@ interrupts = ; clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>; resets = <&ccu RST_BUS_SATA>; - resets-name = "ahci"; + reset-names = "ahci"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; -- cgit From 327384569871e7e3ed637d89726abacda3902098 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 25 Mar 2019 14:52:45 +0100 Subject: ARM: dts: sun8i: r40: Remove useless AHCI properties The SATA controller never have any children nodes, so we don't need the address and size cells properties. Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-r40.dtsi | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index 9784c23346a8..56c6885b02d1 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -563,8 +563,6 @@ clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>; resets = <&ccu RST_BUS_SATA>; reset-names = "ahci"; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; -- cgit From 1befb26623737d77f5ed43d5e24a28a7f666088d Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 25 Mar 2019 14:52:47 +0100 Subject: ARM: dts: sunxi: Remove pinctrl size-cells property The children nodes of the pinctrl node hadn't have any reg property for quite some time, so we don't need the size-cells property. Remove it. Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 1 - arch/arm/boot/dts/sun9i-a80.dtsi | 1 - 2 files changed, 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index e8eebc60787c..4d155592a17c 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -1374,7 +1374,6 @@ gpio-controller; interrupt-controller; #interrupt-cells = <3>; - #size-cells = <0>; #gpio-cells = <3>; s_ir_rx_pin: s-ir-rx-pin { diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index a991f689b99a..28ff54d45549 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -958,7 +958,6 @@ gpio-controller; interrupt-controller; #interrupt-cells = <3>; - #size-cells = <0>; #gpio-cells = <3>; gmac_rgmii_pins: gmac-rgmii-pins { -- cgit From 1b97cf4987fb2e3242880d460a530eaccd8c4759 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 25 Mar 2019 14:52:48 +0100 Subject: ARM: dts: sun8i: A23/A33: Fix pinctrl node names The NAND pinctrl nodes names don't follow the pattern we've used and enforced for some time. Make sure they do. Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index 9be25db7a275..6d43e06d8cc5 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -170,7 +170,7 @@ resets = <&ccu RST_BUS_NAND>; reset-names = "ahb"; pinctrl-names = "default"; - pinctrl-0 = <&nand_pins &nand_pins_cs0 &nand_pins_rb0>; + pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -394,25 +394,25 @@ function = "nand0"; }; - nand_pins_cs0: nand-pins-cs0 { + nand_cs0_pin: nand-cs0-pin { pins = "PC4"; function = "nand0"; bias-pull-up; }; - nand_pins_cs1: nand-pins-cs1 { + nand_cs1_pin: nand-cs1-pin { pins = "PC3"; function = "nand0"; bias-pull-up; }; - nand_pins_rb0: nand-pins-rb0 { + nand_rb0_pin: nand-rb0-pin { pins = "PC6"; function = "nand0"; bias-pull-up; }; - nand_pins_rb1: nand-pins-rb1 { + nand_rb1_pin: nand-rb1-pin { pins = "PC7"; function = "nand0"; bias-pull-up; -- cgit From d4fe5b1507dfe0c11cb148712e509db49e7a2571 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 25 Mar 2019 14:52:53 +0100 Subject: ARM: dts: sunxi: Add default dr_mode The USB OTG binding we have mandates to have a dr_mode property, yet not all boards are setting it. Since the generic otg binding states that the default mode should be the OTG mode, let's use that one in our DTSI. Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 1 + arch/arm/boot/dts/sun5i.dtsi | 1 + arch/arm/boot/dts/sun6i-a31.dtsi | 1 + arch/arm/boot/dts/sun7i-a20.dtsi | 1 + arch/arm/boot/dts/sun8i-a23-a33.dtsi | 1 + arch/arm/boot/dts/sun8i-a83t.dtsi | 1 + 6 files changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index f8a67b95c139..b16595a69cba 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -496,6 +496,7 @@ phy-names = "usb"; extcon = <&usbphy 0>; allwinner,sram = <&otg_sram 1>; + dr_mode = "otg"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index 7dc67cf771c1..f69ab288678b 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -360,6 +360,7 @@ phy-names = "usb"; extcon = <&usbphy 0>; allwinner,sram = <&otg_sram 1>; + dr_mode = "otg"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 4d155592a17c..fa983f9ff5f5 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -508,6 +508,7 @@ phys = <&usbphy 0>; phy-names = "usb"; extcon = <&usbphy 0>; + dr_mode = "otg"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index f087a7ce95aa..d2530b05f71e 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -588,6 +588,7 @@ phy-names = "usb"; extcon = <&usbphy 0>; allwinner,sram = <&otg_sram 1>; + dr_mode = "otg"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index 6d43e06d8cc5..a0247b4b5a1e 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -277,6 +277,7 @@ phys = <&usbphy 0>; phy-names = "usb"; extcon = <&usbphy 0>; + dr_mode = "otg"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index ad4931b1b19b..fcb7ef5ce2df 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -582,6 +582,7 @@ phys = <&usbphy 0>; phy-names = "usb"; extcon = <&usbphy 0>; + dr_mode = "otg"; status = "disabled"; }; -- cgit From 37eadb8555c09395e7dd2b6af83ff82ff9a1e990 Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Tue, 5 Feb 2019 10:07:00 +0100 Subject: ARM: dts: stm32: add initial support of stm32mp157a-dk1 board Add support of stm32mp157a discovery1 board (part number: STM32MP157A-DK1). This board embeds a STM32MP157a SOC with AC package (TFBGA361, 148 ios) and 512MB of DDR3. Several connections are available on this boards: 4*USB2.0, 1*USB2.0 typeC, SDcard, RJ45, HDMI, Arduino connector, ... This patch enables basic support for a kernel boot. Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/stm32mp157a-dk1.dts | 77 +++++++++++++++++++++++++++++++++++ 2 files changed, 78 insertions(+) create mode 100644 arch/arm/boot/dts/stm32mp157a-dk1.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f4f5aeaf3298..acaa0e536313 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -964,6 +964,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32746g-eval.dtb \ stm32h743i-eval.dtb \ stm32h743i-disco.dtb \ + stm32mp157a-dk1.dtb \ stm32mp157c-ed1.dtb \ stm32mp157c-ev1.dtb dtb-$(CONFIG_MACH_SUN4I) += \ diff --git a/arch/arm/boot/dts/stm32mp157a-dk1.dts b/arch/arm/boot/dts/stm32mp157a-dk1.dts new file mode 100644 index 000000000000..873a80ef2b71 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157a-dk1.dts @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157c.dtsi" +#include "stm32mp157-pinctrl.dtsi" +#include + +/ { + model = "STMicroelectronics STM32MP157A-DK1 Discovery Board"; + compatible = "st,stm32mp157a-dk1", "st,stm32mp157"; + + aliases { + ethernet0 = ðernet0; + serial0 = &uart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@c0000000 { + reg = <0xc0000000 0x20000000>; + }; + + led { + compatible = "gpio-leds"; + blue { + label = "heartbeat"; + gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rgmii_pins_a>; + pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii"; + max-speed = <1000>; + phy-handle = <&phy0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&rng1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + status = "okay"; +}; -- cgit From a352e2b337b827403b01df2a88059e873cc8c171 Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Tue, 5 Feb 2019 10:07:00 +0100 Subject: ARM: dts: stm32: add initial support of stm32mp157c-dk2 board Add support of stm32mp157c discovery2 board (part number: STM32MP157C-DK2). This board is a "super-set" of stm32mp157a-dk1. It embeds a STM32MP157c SOC with AC package (TFBGA361, 148 ios) and 512MB of DDR3. Same connections than stm32mp157a-dk1 board are available. Display panel (otm8009a) and Murata wifi/BT combo is added. This patch adds basic support for a kernel boot and enable otm8009a display panel. Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/stm32mp157c-dk2.dts | 75 +++++++++++++++++++++++++++++++++++ 2 files changed, 76 insertions(+) create mode 100644 arch/arm/boot/dts/stm32mp157c-dk2.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index acaa0e536313..8a1d0b3f55dd 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -965,6 +965,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32h743i-eval.dtb \ stm32h743i-disco.dtb \ stm32mp157a-dk1.dtb \ + stm32mp157c-dk2.dtb \ stm32mp157c-ed1.dtb \ stm32mp157c-ev1.dtb dtb-$(CONFIG_MACH_SUN4I) += \ diff --git a/arch/arm/boot/dts/stm32mp157c-dk2.dts b/arch/arm/boot/dts/stm32mp157c-dk2.dts new file mode 100644 index 000000000000..363aeb91d1d6 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157c-dk2.dts @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157a-dk1.dts" + +/ { + model = "STMicroelectronics STM32MP157C-DK2 Discovery Board"; + compatible = "st,stm32mp157c-dk2", "st,stm32mp157"; + + reg18: reg18 { + compatible = "regulator-fixed"; + regulator-name = "reg18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; +}; + +&dsi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + phy-dsi-supply = <®18>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <<dc_ep1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + panel@0 { + compatible = "orisetech,otm8009a"; + reg = <0>; + reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>; + status = "okay"; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; + +<dc { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + ltdc_ep1_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi_in>; + }; + }; +}; -- cgit From 811c94f1e866efd02060acdfa697274a9973d5c3 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Wed, 20 Mar 2019 10:12:53 +0100 Subject: ARM: dts: Add devicetree for Eckelmann ci4x10 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is one of two boards that make use of the recently introduced SIOX bus. Apart from the devices described in the dts it features a display with touch that I didn't include here because it needs some non-mainline change to operate correctly. Reviewed-by: Fabio Estevam Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts | 381 ++++++++++++++++++++++++++ 2 files changed, 382 insertions(+) create mode 100644 arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f4f5aeaf3298..3332dbf2a979 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -400,6 +400,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-cubox-i-emmc-som-v15.dtb \ imx6dl-cubox-i-som-v15.dtb \ imx6dl-dfi-fs700-m60.dtb \ + imx6dl-eckelmann-ci4x10.dtb \ imx6dl-emcon-avari.dtb \ imx6dl-gw51xx.dtb \ imx6dl-gw52xx.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts b/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts new file mode 100644 index 000000000000..9eb2b73951b2 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts @@ -0,0 +1,381 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016 Eckelmann AG. + * Copyright (C) 2013 Freescale Semiconductor, Inc. + */ + +/dts-v1/; + +#include + +#include "imx6dl.dtsi" + +/ { + model = "Eckelmann CI 4X10 Board"; + compatible = "eckelmann,imx6dl-ci4x10", "fsl,imx6dl"; + + chosen { + stdout-path = &uart3; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + rmii_clk: clock-rmii { + /* This clock is provided by the phy (KSZ8091RNB) */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb_h1_vbus>; + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + siox { + compatible = "eckelmann,siox-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_siox>; + din-gpios = <&gpio6 11 GPIO_ACTIVE_HIGH>; + dout-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; + dclk-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; + dld-gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 12 GPIO_ACTIVE_HIGH>; + status = "okay"; + + flash@0 { + compatible = "everspin,mr25h256"; + reg = <0>; + spi-max-frequency = <15000000>; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; + status = "okay"; + + tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <10000000>; + }; +}; + +&gpio2 { + gpio-line-names = "buzzer", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = "", "", "", "", "", "", "", "in2", + "prio2", "prio1", "aux", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio6 { + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "in1", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + temperature-sensor@49 { + compatible = "ad,ad7414"; + reg = <0x49>; + }; + + rtc@51 { + compatible = "nxp,pcf2127"; + reg = <0x51>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hog { + fsl,pins = < + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00000018 /* buzzer */ + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x00000018 /* OUT_1 */ + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x00000018 /* OUT_2 */ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x00000018 /* OUT_3 */ + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x00000000 /* In1 */ + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x00000000 /* In2 */ + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x00000018 /* unused watchdog pin */ + MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x00000018 /* unused watchdog pin */ + + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x000100a0 + MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x000100a0 + MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x000100a0 + MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000100a0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x000100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x000100b1 + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x000100b1 + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000100b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x0001b098 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x0001b098 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x0001b098 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x0001b098 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x0001b098 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x0001b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x0001b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x0001b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x0001b0b0 + MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x00000018 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x0001b020 + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x0001b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x0001b020 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x0001b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + /* without SION i2c doesn't detect bus busy */ + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b820 + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b820 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x00000018 + >; + }; + + pinctrl_reg_usb_h1_vbus: reg_usb_h1_vbusgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0001b0b0 + >; + }; + + pinctrl_siox: sioxgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x0001b010 /* DIN */ + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0001b010 /* DOUT */ + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0001b010 /* DCLK */ + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x0001b010 /* DLD */ + >; + }; + + pinctrl_uart1_dte: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x0001b010 + MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x0001b010 + MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x0001b010 + MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x0001b010 + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0001b010 /* DCD */ + MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x0001b010 /* DTR */ + MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x0001b010 /* DSR */ + >; + }; + + pinctrl_uart2_dte: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x0001b010 + MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x0001b010 + MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x0001b010 + MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x0001b010 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001b010 /* DCD */ + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b010 /* DTR */ + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0001b010 /* DSR */ + >; + }; + + pinctrl_uart3_dce: uart3grp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x0001b010 + MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x0001b010 + >; + }; + + pinctrl_uart4_dce: uart4grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x0001b010 + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x0001b010 + MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x0001b010 + >; + }; + + pinctrl_uart5_dce: uart5grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x0001b010 + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x0001b010 + MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x0001b010 /* RTS */ + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x0001b0b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x00017059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x00010059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x00017059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x00017059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x00017059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x00017059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x00017059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x00017059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x00017059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x00017059 + >; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; + phy-handle = <&phy>; + clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 20 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_dte>; + uart-has-rtscts; + fsl,dte-mode; + dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; + dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; + dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_dte>; + uart-has-rtscts; + fsl,dte-mode; + dcd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + dtr-gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; + dsr-gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_dce>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4_dce>; + rts-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5_dce>; + rts-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usbotg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + non-removable; + status = "okay"; +}; -- cgit From 496456058b506233a88ca60dbedbcb0e681d2423 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Fri, 22 Mar 2019 06:31:56 +0000 Subject: ARM: dts: imx7ulp: add ocotp support Add i.MX7ULP OCOTP support, its clock source is from M4 BUS clock which is NOT available in Linux clock tree, but M4 BUS clock is always ON when A7 (Linux) is alive, so just use dummy clock here. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7ulp.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi index eb349fd7f6e4..d6b711011cba 100644 --- a/arch/arm/boot/dts/imx7ulp.dtsi +++ b/arch/arm/boot/dts/imx7ulp.dtsi @@ -365,5 +365,11 @@ compatible = "fsl,imx7ulp-sim", "syscon"; reg = <0x410a3000 0x1000>; }; + + ocotp: ocotp-ctrl@410a6000 { + compatible = "fsl,imx7ulp-ocotp", "syscon"; + reg = <0x410a6000 0x4000>; + clocks = <&scg1 IMX7ULP_CLK_DUMMY>; + }; }; }; -- cgit From 88a20adde5f63407a40fe6907766d9c1ddc8b173 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 25 Mar 2019 14:52:54 +0100 Subject: ARM: dts: sun8i: h3: Add default dr_mode The USB OTG binding we have mandates to have a dr_mode property, yet not all boards are setting it. Since the generic otg binding states that the default mode should be the OTG mode, let's use that one in our DTSI. Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 8a79d3b04069..3b18fd71efc1 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -242,6 +242,7 @@ phys = <&usbphy 0>; phy-names = "usb"; extcon = <&usbphy 0>; + dr_mode = "otg"; status = "disabled"; }; -- cgit From a79668c17684a999200b63a13c4c61132a46a38b Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 25 Mar 2019 14:52:49 +0100 Subject: ARM: dts: sun9i: Remove deprecated pinctrl properties We switched to the generic pinctrl binding some time ago, yet the GMAC pinctrl node apparently slipped through. Fix this. Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80.dtsi | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index 28ff54d45549..c1aa26db44ae 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -961,11 +961,10 @@ #gpio-cells = <3>; gmac_rgmii_pins: gmac-rgmii-pins { - allwinner,pins = "PA0", "PA1", "PA2", "PA3", - "PA4", "PA5", "PA7", "PA8", - "PA9", "PA10", "PA12", "PA13", - "PA15", "PA16", "PA17"; - allwinner,function = "gmac"; + pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", + "PA7", "PA8", "PA9", "PA10", "PA12", + "PA13", "PA15", "PA16", "PA17"; + function = "gmac"; /* * data lines in RGMII mode use DDR mode * and need a higher signal drive strength -- cgit From 0164945de1b88655befa0319e6d0e3fbcf965a63 Mon Sep 17 00:00:00 2001 From: Mans Rullgard Date: Tue, 26 Mar 2019 11:29:02 +0000 Subject: ARM: dts: sun7i: fix typos in uart pin mux MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The recently added uart mux options had a few typos. Fix them. Fixes: 43d0fe112585 ("ARM: dts: sun7i: add pinctrl for missing uart mux options") Reported-by: Werner Böllmann Signed-off-by: Mans Rullgard Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index d2530b05f71e..28e1045853fc 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -1003,19 +1003,19 @@ /omit-if-no-ref/ uart1_cts_rts_pa_pins: uart1-cts-rts-pa-pins { - pins = "PA12", "PIA13"; - function = "uart2"; + pins = "PA12", "PA13"; + function = "uart1"; }; /omit-if-no-ref/ uart2_pa_pins: uart2-pa-pins { - pins = "PIA2", "PIA3"; + pins = "PA2", "PA3"; function = "uart2"; }; /omit-if-no-ref/ uart2_cts_rts_pa_pins: uart2-cts-rts-pa-pins { - pins = "PA0", "PIA1"; + pins = "PA0", "PA1"; function = "uart2"; }; -- cgit From 129ca9e185ab34e939eab91ef8f10c115fc43ba5 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 20 Mar 2019 20:44:09 +0100 Subject: ARM: dts: rskrza1: Add I2C support Enable the I2C bus, and add the following devices: - Two CAT9554 port expanders (8 GPIOs, interrupt not wired by default), - R1EX24016ASAS0A EEPROM. The bus also contains a MAX9856 Audio Codec, which is not yet supported. All devices (incl. the audio codec) are documented to support an I2C bus running at 400 kHz. Pinctrl is based on the RZ/A BSP. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100-rskrza1.dts | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts b/arch/arm/boot/dts/r7s72100-rskrza1.dts index 8ee44a100e9a..60e80ecbbf68 100644 --- a/arch/arm/boot/dts/r7s72100-rskrza1.dts +++ b/arch/arm/boot/dts/r7s72100-rskrza1.dts @@ -47,6 +47,34 @@ clock-frequency = <13330000>; }; +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + status = "okay"; + + clock-frequency = <400000>; + + io_expander1: gpio@20 { + compatible = "onnn,cat9554"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + io_expander2: gpio@21 { + compatible = "onnn,cat9554"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + + eeprom@50 { + compatible = "renesas,r1ex24016", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + }; +}; + &usb_x1_clk { clock-frequency = <48000000>; }; @@ -56,6 +84,11 @@ }; &pinctrl { + /* RIIC ch3 (Port Expander, EEPROM (MAC Addr), Audio Codec) */ + i2c3_pins: i2c3 { + pinmux = , /* RIIC3SCL */ + ; /* RIIC3SDA */ + }; /* Serial Console */ scif2_pins: serial2 { -- cgit From 1792a0f35319af8bf2726ed12bef5194d397d3d1 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 20 Mar 2019 20:44:10 +0100 Subject: ARM: dts: rskrza1: Add remaining LEDs Describe the remaining 3 LEDs, which are driven by the first CAT9554 port expander. Drop the superfluous status property from the leds node while at it. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100-rskrza1.dts | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts b/arch/arm/boot/dts/r7s72100-rskrza1.dts index 60e80ecbbf68..ff24301dc1be 100644 --- a/arch/arm/boot/dts/r7s72100-rskrza1.dts +++ b/arch/arm/boot/dts/r7s72100-rskrza1.dts @@ -34,12 +34,23 @@ }; leds { - status = "okay"; compatible = "gpio-leds"; led0 { gpios = <&port7 1 GPIO_ACTIVE_LOW>; }; + + led1 { + gpios = <&io_expander1 0 GPIO_ACTIVE_LOW>; + }; + + led2 { + gpios = <&io_expander1 1 GPIO_ACTIVE_LOW>; + }; + + led3 { + gpios = <&io_expander1 2 GPIO_ACTIVE_LOW>; + }; }; }; -- cgit From 01b2a2d52169372d73ec3639620b2b3255d5eb53 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Mon, 25 Mar 2019 09:20:05 -0700 Subject: ARM: dts: rockchip: Add device tree for rk3288-veyron-mighty Mighty is basically the same Chromebook as Jaq but it has a full-sized SD slot and some different (slightly more rugged) plastics around it. Like Jaq, Mighty may show up with various different brandings but all of them have the same board inside. In the downstream kernel Mighty and Jaq share a "dtsi" and Mighty just adds the SD write protect (needed for a full-sized SD slot). We'll do this upstream by just including the Jaq dts and make the changes. Signed-off-by: Douglas Anderson Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/rk3288-veyron-mighty.dts | 34 ++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) create mode 100644 arch/arm/boot/dts/rk3288-veyron-mighty.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f4f5aeaf3298..48282ebfb3da 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -909,6 +909,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-veyron-jaq.dtb \ rk3288-veyron-jerry.dtb \ rk3288-veyron-mickey.dtb \ + rk3288-veyron-mighty.dtb \ rk3288-veyron-minnie.dtb \ rk3288-veyron-pinky.dtb \ rk3288-veyron-speedy.dtb \ diff --git a/arch/arm/boot/dts/rk3288-veyron-mighty.dts b/arch/arm/boot/dts/rk3288-veyron-mighty.dts new file mode 100644 index 000000000000..f640857cbdae --- /dev/null +++ b/arch/arm/boot/dts/rk3288-veyron-mighty.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Veyron Mighty Rev 1+ board device tree source + * + * Copyright 2015 Google, Inc + */ + +/dts-v1/; + +#include "rk3288-veyron-jaq.dts" + +/ { + model = "Google Mighty"; + compatible = "google,veyron-mighty-rev5", "google,veyron-mighty-rev4", + "google,veyron-mighty-rev3", "google,veyron-mighty-rev2", + "google,veyron-mighty-rev1", "google,veyron-mighty", + "google,veyron", "rockchip,rk3288"; +}; + +&sdmmc { + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio + &sdmmc_wp_gpio &sdmmc_bus4>; + wp-gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>; + + /delete-property/ disable-wp; +}; + +&pinctrl { + sdmmc { + sdmmc_wp_gpio: sdmmc-wp-gpio { + rockchip,pins = <7 10 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; -- cgit From 1ba8994faa330b8ab80ca41e5ab3f90719050d5d Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Thu, 7 Feb 2019 11:15:47 +0100 Subject: ARM: dts: at91: sama5d2: add labels to soc dtsi for derivative boards This adds labels to commonly used device-tree nodes so that derivative boards can avoid ahb/apb hierarchy. Signed-off-by: Nicolas Ferre Signed-off-by: Alexandre Belloni Signed-off-by: Ludovic Desroches --- arch/arm/boot/dts/sama5d2.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index d159ee42ef29..9519b9d5abca 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -688,13 +688,13 @@ ranges = <0 0xf8044000 0x1420>; }; - rstc@f8048000 { + reset_controller: rstc@f8048000 { compatible = "atmel,sama5d3-rstc"; reg = <0xf8048000 0x10>; clocks = <&clk32k>; }; - shdwc@f8048010 { + shutdown_controller: shdwc@f8048010 { compatible = "atmel,sama5d2-shdwc"; reg = <0xf8048010 0x10>; clocks = <&clk32k>; @@ -710,7 +710,7 @@ clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; }; - watchdog@f8048040 { + watchdog: watchdog@f8048040 { compatible = "atmel,sama5d4-wdt"; reg = <0xf8048040 0x10>; interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; -- cgit From 7784a6eb89d431a5681833d4a6a3c7f01b03ae52 Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Thu, 13 Dec 2018 12:50:06 +0000 Subject: ARM: dts: at91: sama5d2_xplained: Add proper regulator states for suspend-to-mem When entering suspend-to-mem, all PMIC outputs are disabled except VDDIODDR which is put in power saving mode, and whose voltage is increased (probably to counter the poor accuracy of power saving mode). Signed-off-by: Boris Brezillon [claudiu.beznea@microchip.com: use regulator-changeable-in-suspend, regulator-suspend-max-microvolt, regulator-suspend-max-microvolt, use macros for regulators' states, add regulator-inital-state] Signed-off-by: Claudiu Beznea Signed-off-by: Alexandre Belloni Signed-off-by: Ludovic Desroches --- arch/arm/boot/dts/at91-sama5d2_xplained.dts | 54 +++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts index fa54e8866f1e..e62c3b6cde4c 100644 --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts @@ -47,6 +47,7 @@ #include "sama5d2-pinfunc.h" #include #include +#include / { model = "Atmel SAMA5D2 Xplained"; @@ -181,49 +182,102 @@ regulator-name = "VDD_1V35"; regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; + regulator-allowed-modes = , + ; + regulator-initial-mode = ; regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-min-microvolt=<1400000>; + regulator-suspend-max-microvolt=<1400000>; + regulator-changeable-in-suspend; + regulator-mode=; + }; }; vdd_1v2_reg: REG_DCDC2 { regulator-name = "VDD_1V2"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1300000>; + regulator-allowed-modes = , + ; + regulator-initial-mode = ; regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; vdd_3v3_reg: REG_DCDC3 { regulator-name = "VDD_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + regulator-allowed-modes = , + ; + regulator-initial-mode = ; regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; vdd_fuse_reg: REG_LDO1 { regulator-name = "VDD_FUSE"; regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; + regulator-allowed-modes = , + ; + regulator-initial-mode = ; regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; vdd_3v3_lp_reg: REG_LDO2 { regulator-name = "VDD_3V3_LP"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + regulator-allowed-modes = , + ; + regulator-initial-mode = ; regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; vdd_led_reg: REG_LDO3 { regulator-name = "VDD_LED"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + regulator-allowed-modes = , + ; + regulator-initial-mode = ; regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; vdd_sdhc_1v8_reg: REG_LDO4 { regulator-name = "VDD_SDHC_1V8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-allowed-modes = , + ; + regulator-initial-mode = ; regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; }; -- cgit From dae9f076d1c3c5d1e4bb7363d8b1ccd6145200b1 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Mon, 25 Mar 2019 11:22:43 -0700 Subject: ARM: dts: vf610: Add ZII SPB4 board Add Device Tree for VF610 based Zodiac Seat Power Box. Signed-off-by: Andrey Smirnov Reviewed-by: Fabio Estevam Cc: Shawn Guo Cc: Chris Healy Cc: Andrew Lunn Cc: Heiner Kallweit Cc: Fabio Estevam Cc: Rob Herring Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-imx@nxp.com Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/vf610-zii-spb4.dts | 359 +++++++++++++++++++++++++++++++++++ 2 files changed, 360 insertions(+) create mode 100644 arch/arm/boot/dts/vf610-zii-spb4.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 3332dbf2a979..1234bd95d85c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -607,6 +607,7 @@ dtb-$(CONFIG_SOC_VF610) += \ vf610-zii-dev-rev-b.dtb \ vf610-zii-dev-rev-c.dtb \ vf610-zii-scu4-aib.dtb \ + vf610-zii-spb4.dtb \ vf610-zii-ssmb-dtu.dtb \ vf610-zii-ssmb-spu3.dtb dtb-$(CONFIG_ARCH_MXS) += \ diff --git a/arch/arm/boot/dts/vf610-zii-spb4.dts b/arch/arm/boot/dts/vf610-zii-spb4.dts new file mode 100644 index 000000000000..9dde83ccb9d1 --- /dev/null +++ b/arch/arm/boot/dts/vf610-zii-spb4.dts @@ -0,0 +1,359 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/* + * Device tree file for ZII's SPB4 board + * + * SPB - Seat Power Box + * + * Copyright (C) 2019 Zodiac Inflight Innovations + */ + +/dts-v1/; +#include "vf610.dtsi" + +/ { + model = "ZII VF610 SPB4 Board"; + compatible = "zii,vf610spb4", "zii,vf610dev", "fsl,vf610"; + + chosen { + stdout-path = &uart0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pinctrl_leds_debug>; + pinctrl-names = "default"; + + led-debug { + label = "zii:green:debug1"; + gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_mcu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&adc0 { + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&adc1 { + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&dspi1 { + bus-num = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dspi1>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p128", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + }; +}; + +&edma0 { + status = "okay"; +}; + +&edma1 { + status = "okay"; +}; + +&esdhc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc0>; + bus-width = <8>; + non-removable; + no-1-8-v; + keep-power-in-suspend; + no-sdio; + no-sd; + status = "okay"; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + no-sdio; + status = "okay"; +}; + +&fec1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; + + fixed-link { + speed = <100>; + full-duplex; + }; + + mdio1: mdio { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + switch0: switch0@0 { + compatible = "marvell,mv88e6190"; + pinctrl-0 = <&pinctrl_gpio_switch0>; + pinctrl-names = "default"; + reg = <0>; + eeprom-length = <65536>; + reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio3>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&fec1>; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "eth_cu_1000_1"; + }; + + port@2 { + reg = <2>; + label = "eth_cu_1000_2"; + }; + + port@3 { + reg = <3>; + label = "eth_cu_1000_3"; + }; + + port@4 { + reg = <4>; + label = "eth_cu_1000_4"; + }; + + port@5 { + reg = <5>; + label = "eth_cu_1000_5"; + }; + + port@6 { + reg = <6>; + label = "eth_cu_1000_6"; + }; + }; + }; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + status = "okay"; + + io-expander@22 { + compatible = "nxp,pca9554"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + label = "nameplate"; + }; + + eeprom@52 { + compatible = "atmel,24c04"; + reg = <0x52>; + }; +}; + +&snvsrtc { + status = "disabled"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; + + rave-sp { + compatible = "zii,rave-sp-rdu2"; + current-speed = <1000000>; + #address-cells = <1>; + #size-cells = <1>; + + watchdog { + compatible = "zii,rave-sp-watchdog"; + }; + + eeprom@a3 { + compatible = "zii,rave-sp-eeprom"; + reg = <0xa3 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + zii,eeprom-name = "main-eeprom"; + }; + }; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&wdoga5 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_dspi1: dspi1grp { + fsl,pins = < + VF610_PAD_PTD5__DSPI1_CS0 0x1182 + VF610_PAD_PTD4__DSPI1_CS1 0x1182 + VF610_PAD_PTC6__DSPI1_SIN 0x1181 + VF610_PAD_PTC7__DSPI1_SOUT 0x1182 + VF610_PAD_PTC8__DSPI1_SCK 0x1182 + >; + }; + + pinctrl_esdhc0: esdhc0grp { + fsl,pins = < + VF610_PAD_PTC0__ESDHC0_CLK 0x31ef + VF610_PAD_PTC1__ESDHC0_CMD 0x31ef + VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef + VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef + VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef + VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef + VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef + VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef + VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef + VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + VF610_PAD_PTA24__ESDHC1_CLK 0x31ef + VF610_PAD_PTA25__ESDHC1_CMD 0x31ef + VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef + VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef + VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef + VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + VF610_PAD_PTA6__RMII_CLKIN 0x30d1 + VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 + VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 + VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 + VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 + VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 + VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 + VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 + VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 + VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 + >; + }; + + pinctrl_gpio_switch0: pinctrl-gpio-switch0 { + fsl,pins = < + VF610_PAD_PTE2__GPIO_107 0x31c2 + VF610_PAD_PTB28__GPIO_98 0x219d + >; + }; + + pinctrl_i2c0: i2c0grp { + fsl,pins = < + VF610_PAD_PTB14__I2C0_SCL 0x37ff + VF610_PAD_PTB15__I2C0_SDA 0x37ff + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + VF610_PAD_PTB16__I2C1_SCL 0x37ff + VF610_PAD_PTB17__I2C1_SDA 0x37ff + >; + }; + + pinctrl_leds_debug: pinctrl-leds-debug { + fsl,pins = < + VF610_PAD_PTD3__GPIO_82 0x31c2 + >; + }; + + pinctrl_uart0: uart0grp { + fsl,pins = < + VF610_PAD_PTB10__UART0_TX 0x21a2 + VF610_PAD_PTB11__UART0_RX 0x21a1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + VF610_PAD_PTB23__UART1_TX 0x21a2 + VF610_PAD_PTB24__UART1_RX 0x21a1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + VF610_PAD_PTD0__UART2_TX 0x21a2 + VF610_PAD_PTD1__UART2_RX 0x21a1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + VF610_PAD_PTA30__UART3_TX 0x21a2 + VF610_PAD_PTA31__UART3_RX 0x21a1 + >; + }; +}; -- cgit From 5f0a88a1aabb2b332e2fa01598cc24e708552771 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Mon, 25 Mar 2019 11:30:17 -0700 Subject: ARM: dts: vf610-zii-cfu1: Disable NOR flash/SPI controller Only a certain number of CFU1's come with NOR flash populated. Disable it by default to avoid trying to probe NOR flash on devices that don't have it. Devices that do have it can rely on the bootloader to enable this node. Signed-off-by: Andrey Smirnov Cc: Shawn Guo Cc: Chris Healy Cc: Andrew Lunn Cc: Fabio Estevam Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-zii-cfu1.dts | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/vf610-zii-cfu1.dts b/arch/arm/boot/dts/vf610-zii-cfu1.dts index 6c78122401a1..afc25b33bd3b 100644 --- a/arch/arm/boot/dts/vf610-zii-cfu1.dts +++ b/arch/arm/boot/dts/vf610-zii-cfu1.dts @@ -87,7 +87,12 @@ bus-num = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dspi1>; - status = "okay"; + /* + * Some CFU1s come with SPI-NOR chip DNPed, so we leave this + * node disabled by default and rely on bootloader to enable + * it when appropriate. + */ + status = "disabled"; m25p128@0 { #address-cells = <1>; -- cgit From 07f9da2900674e8e7b15b090b878d8defe223277 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Thu, 28 Mar 2019 21:47:21 +0100 Subject: ARM: dts: meson8b: odroidc1: add the GPIO line names This adds the GPIO line names from the schematics to get them displayed in the debugfs output of each GPIO controller. The schematics from Odroid-C1+ PCB revision 0.4 20150615 are used as referenced. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b-odroidc1.dts | 52 ++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts index 3b0e0f8fbc23..0157646e3a89 100644 --- a/arch/arm/boot/dts/meson8b-odroidc1.dts +++ b/arch/arm/boot/dts/meson8b-odroidc1.dts @@ -234,7 +234,59 @@ }; }; +&gpio { + gpio-line-names = /* Bank GPIOX */ + "J2 Header Pin 35", "J2 Header Pin 36", + "J2 Header Pin 32", "J2 Header Pin 31", + "J2 Header Pin 29", "J2 Header Pin 18", + "J2 Header Pin 22", "J2 Header Pin 16", + "J2 Header Pin 23", "J2 Header Pin 21", + "J2 Header Pin 19", "J2 Header Pin 33", + "J2 Header Pin 8", "J2 Header Pin 10", + "J2 Header Pin 15", "J2 Header Pin 13", + "J2 Header Pin 24", "J2 Header Pin 26", + /* Bank GPIOY */ + "Revision (upper)", "Revision (lower)", + "J2 Header Pin 7", "", "J2 Header Pin 12", + "J2 Header Pin 11", "", "", "", + "TFLASH_VDD_EN", "", "", + /* Bank GPIODV */ + "VCCK_PWM (PWM_C)", "I2CA_SDA", "I2CA_SCL", + "I2CB_SDA", "I2CB_SCL", "VDDEE_PWM (PWM_D)", + "", + /* Bank GPIOH */ + "HDMI_HPD", "HDMI_I2C_SDA", "HDMI_I2C_SCL", + "ETH_PHY_INTR", "ETH_PHY_NRST", "ETH_TXD1", + "ETH_TXD0", "ETH_TXD3", "ETH_TXD2", + "ETH_RGMII_TX_CLK", + /* Bank CARD */ + "SD_DATA1 (SDB_D1)", "SD_DATA0 (SDB_D0)", + "SD_CLK", "SD_CMD", "SD_DATA3 (SDB_D3)", + "SD_DATA2 (SDB_D2)", "SD_CDN (SD_DET_N)", + /* Bank BOOT */ + "SDC_D0 (EMMC)", "SDC_D1 (EMMC)", + "SDC_D2 (EMMC)", "SDC_D3 (EMMC)", + "SDC_D4 (EMMC)", "SDC_D5 (EMMC)", + "SDC_D6 (EMMC)", "SDC_D7 (EMMC)", + "SDC_CLK (EMMC)", "SDC_RSTn (EMMC)", + "SDC_CMD (EMMC)", "BOOT_SEL", "", "", "", + "", "", "", "", + /* Bank DIF */ + "ETH_RXD1", "ETH_RXD0", "ETH_RX_DV", + "RGMII_RX_CLK", "ETH_RXD3", "ETH_RXD2", + "ETH_TXEN", "ETH_PHY_REF_CLK_25MOUT", + "ETH_MDC", "ETH_MDIO"; +}; + &gpio_ao { + gpio-line-names = "UART TX", "UART RX", "", + "TF_3V3N_1V8_EN", "USB_HUB_RST_N", + "USB_OTG_PWREN", "J7 Header Pin 2", + "IR_IN", "J7 Header Pin 4", + "J7 Header Pin 6", "J7 Header Pin 5", + "J7 Header Pin 7", "HDMI_CEC", + "SYS_LED", "", ""; + /* * WARNING: The USB Hub on the Odroid-C1/C1+ needs a reset signal * to be turned high in order to be detected by the USB Controller. -- cgit From fadc78062477409afd758525d5c228a0d4d1eaaf Mon Sep 17 00:00:00 2001 From: Zheng Yang Date: Sat, 30 Mar 2019 10:56:37 +0100 Subject: ARM: dts: rockchip: add rk3066 hdmi nodes This patch adds the hdmi nodes to rk3066. Signed-off-by: Zheng Yang Signed-off-by: Johan Jonker Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a.dtsi | 59 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 653127a377fa..d9504fd456a7 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -80,6 +80,11 @@ vop0_out: port { #address-cells = <1>; #size-cells = <0>; + + vop0_out_hdmi: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_in_vop0>; + }; }; }; @@ -101,6 +106,49 @@ vop1_out: port { #address-cells = <1>; #size-cells = <0>; + + vop1_out_hdmi: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_in_vop1>; + }; + }; + }; + + hdmi: hdmi@10116000 { + compatible = "rockchip,rk3066-hdmi"; + reg = <0x10116000 0x2000>; + interrupts = ; + clocks = <&cru HCLK_HDMI>; + clock-names = "hclk"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>; + power-domains = <&power RK3066_PD_VIO>; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in_vop0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vop0_out_hdmi>; + }; + + hdmi_in_vop1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vop1_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + reg = <1>; + }; }; }; @@ -380,6 +428,17 @@ */ }; + hdmi { + hdmi_hpd: hdmi-hpd { + rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>; + }; + + hdmii2c_xfer: hdmii2c-xfer { + rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>, + <0 RK_PA2 1 &pcfg_pull_none>; + }; + }; + i2c0 { i2c0_xfer: i2c0-xfer { rockchip,pins = , -- cgit From 4b028ebd4e3d86c61161b3a937b746043006dcbe Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 30 Mar 2019 10:56:38 +0100 Subject: ARM: dts: rockchip: enable vop0 and hdmi nodes to rk3066a-mk808 This patch enables the vop0 and hdmi nodes for a MK808 with rk3066 processor. Signed-off-by: Johan Jonker Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a-mk808.dts | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3066a-mk808.dts b/arch/arm/boot/dts/rk3066a-mk808.dts index 9d2216d71f70..8bc259d3e450 100644 --- a/arch/arm/boot/dts/rk3066a-mk808.dts +++ b/arch/arm/boot/dts/rk3066a-mk808.dts @@ -30,6 +30,17 @@ }; }; + hdmi_con { + compatible = "hdmi-connector"; + type = "c"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + vcc_io: vcc-io { compatible = "regulator-fixed"; regulator-name = "vcc_io"; @@ -91,6 +102,20 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_in_vop1 { + status = "disabled"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &mmc0 { bus-width = <4>; cap-mmc-highspeed; @@ -150,6 +175,10 @@ status = "okay"; }; +&vop0 { + status = "okay"; +}; + &wdt { status = "okay"; }; -- cgit From 2a63a027ea15ecc0e3a09817b0fe0b33547230fb Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Wed, 27 Mar 2019 01:18:37 +0100 Subject: ARM: dts: sun8i: tbs-a711: Enable bluetooth TBS A711 tablet has a bcm20702a1 bluetooth chip (part of AP6210 WiFi/BT module) connected to UART1. Add node for the blutooth chip. The driver needs brcm/BCM20702A1.hcd firmware file to run. Signed-off-by: Ondrej Jirman Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts index 1e840ab5a541..6aae70c89a1e 100644 --- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts +++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts @@ -406,7 +406,20 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts; status = "okay"; + + bluetooth { + compatible = "brcm,bcm20702a1"; + clocks = <&ac100_rtc 1>; + clock-names = "lpo"; + vbat-supply = <®_vbat>; + vddio-supply = <®_dldo1>; + device-wakeup-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + host-wakeup-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ + shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ + max-speed = <1500000>; + }; }; &usb_otg { -- cgit From 86e2f89075ac0e4f99e051b9bc30b6ce9d0095b3 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Wed, 27 Mar 2019 01:18:39 +0100 Subject: ARM: dts: sun8i: a83t: Add nodes for UART2-UART4 A83T has 5 UART interfaces, but only the first two have their nodes defined in sun8i-a83t.dtsi. Add nodes for the missing interfaces. Signed-off-by: Ondrej Jirman Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t.dtsi | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index fcb7ef5ce2df..e5c39eef1c29 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -873,6 +873,39 @@ status = "disabled"; }; + uart2: serial@1c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; + status = "disabled"; + }; + + uart3: serial@1c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART3>; + resets = <&ccu RST_BUS_UART3>; + status = "disabled"; + }; + + uart4: serial@1c29000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART4>; + resets = <&ccu RST_BUS_UART4>; + status = "disabled"; + }; + i2c0: i2c@1c2ac00 { compatible = "allwinner,sun8i-a83t-i2c", "allwinner,sun6i-a31-i2c"; -- cgit From 261e1a6e4ae5f5bfe8ad8d44580b880da99b81eb Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Thu, 28 Mar 2019 12:31:58 +0100 Subject: ARM: dts: sun8i: a83t: Add missing cooling device properties for CPUs Enable to use CPUs as cooling device in the future, by adding "#cooling-cells" to each CPU node. This property should be present for all the CPUs of a cluster. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device. Signed-off-by: Ondrej Jirman Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index e5c39eef1c29..da25d50ea5d4 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -69,6 +69,7 @@ cci-control-port = <&cci_control0>; enable-method = "allwinner,sun8i-a83t-smp"; reg = <0>; + #cooling-cells = <2>; }; cpu@1 { @@ -78,6 +79,7 @@ cci-control-port = <&cci_control0>; enable-method = "allwinner,sun8i-a83t-smp"; reg = <1>; + #cooling-cells = <2>; }; cpu@2 { @@ -87,6 +89,7 @@ cci-control-port = <&cci_control0>; enable-method = "allwinner,sun8i-a83t-smp"; reg = <2>; + #cooling-cells = <2>; }; cpu@3 { @@ -96,6 +99,7 @@ cci-control-port = <&cci_control0>; enable-method = "allwinner,sun8i-a83t-smp"; reg = <3>; + #cooling-cells = <2>; }; cpu100: cpu@100 { @@ -107,6 +111,7 @@ cci-control-port = <&cci_control1>; enable-method = "allwinner,sun8i-a83t-smp"; reg = <0x100>; + #cooling-cells = <2>; }; cpu@101 { @@ -116,6 +121,7 @@ cci-control-port = <&cci_control1>; enable-method = "allwinner,sun8i-a83t-smp"; reg = <0x101>; + #cooling-cells = <2>; }; cpu@102 { @@ -125,6 +131,7 @@ cci-control-port = <&cci_control1>; enable-method = "allwinner,sun8i-a83t-smp"; reg = <0x102>; + #cooling-cells = <2>; }; cpu@103 { @@ -134,6 +141,7 @@ cci-control-port = <&cci_control1>; enable-method = "allwinner,sun8i-a83t-smp"; reg = <0x103>; + #cooling-cells = <2>; }; }; -- cgit From 2efcca8ae68897a5b4c4994fc9ee4c7366e57e24 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Mon, 1 Apr 2019 13:56:12 +0200 Subject: ARM: dts: sun8i: tbs-a711: Add node for BMA250 accelerometer A711 tablet has BMA250 accelerometer connected to I2C1 bus. Enable both the I2C1 bus and add the accelerometer device to it. Signed-off-by: Ondrej Jirman Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts index 6aae70c89a1e..066d95a7cb78 100644 --- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts +++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts @@ -156,6 +156,18 @@ status = "okay"; }; +&i2c1 { + clock-frequency = <400000>; + status = "okay"; + + accelerometer@18 { + compatible = "bosch,bma250"; + reg = <0x18>; + interrupt-parent = <&pio>; + interrupts = <7 10 IRQ_TYPE_EDGE_RISING>; /* PH10 / EINT10 */ + }; +}; + &mmc0 { vmmc-supply = <®_dcdc1>; pinctrl-names = "default"; -- cgit From 31ec8c14566e2bad88a71daf209d2caf80036a3e Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Mon, 1 Apr 2019 13:56:13 +0200 Subject: ARM: dts: sun8i: a83t: Add UART2 PB pins Add pin definitions for UART2 PB pins. These are used on TBS-A711 tablet. Signed-off-by: Ondrej Jirman Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index da25d50ea5d4..59a48ce26fec 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -776,6 +776,12 @@ pins = "PG8", "PG9"; function = "uart1"; }; + + /omit-if-no-ref/ + uart2_pb_pins: uart2-pb-pins { + pins = "PB0", "PB1"; + function = "uart2"; + }; }; timer@1c20c00 { -- cgit From 3764db4f0b4eefbf4aa97ef7255ae3c29b56ee8c Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Mon, 1 Apr 2019 15:36:10 +0200 Subject: ARM: dts: sun8i: a83t: Add missing CPU clock references A83T DTSI has cpu clocks defined only on the first CPU in each cluster. We can bring down any CPU in the cluster, so we need to define clock for each CPU, so that the system knows what clock to use if the first CPU is down. Also move the clocks property below the compatible on cpus where it is already defined. Property "clock-names" is not needed. Signed-off-by: Ondrej Jirman Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 59a48ce26fec..f739b88efb53 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -61,10 +61,9 @@ #size-cells = <0>; cpu0: cpu@0 { - clocks = <&ccu CLK_C0CPUX>; - clock-names = "cpu"; compatible = "arm,cortex-a7"; device_type = "cpu"; + clocks = <&ccu CLK_C0CPUX>; operating-points-v2 = <&cpu0_opp_table>; cci-control-port = <&cci_control0>; enable-method = "allwinner,sun8i-a83t-smp"; @@ -75,6 +74,7 @@ cpu@1 { compatible = "arm,cortex-a7"; device_type = "cpu"; + clocks = <&ccu CLK_C0CPUX>; operating-points-v2 = <&cpu0_opp_table>; cci-control-port = <&cci_control0>; enable-method = "allwinner,sun8i-a83t-smp"; @@ -85,6 +85,7 @@ cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; + clocks = <&ccu CLK_C0CPUX>; operating-points-v2 = <&cpu0_opp_table>; cci-control-port = <&cci_control0>; enable-method = "allwinner,sun8i-a83t-smp"; @@ -95,6 +96,7 @@ cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; + clocks = <&ccu CLK_C0CPUX>; operating-points-v2 = <&cpu0_opp_table>; cci-control-port = <&cci_control0>; enable-method = "allwinner,sun8i-a83t-smp"; @@ -103,10 +105,9 @@ }; cpu100: cpu@100 { - clocks = <&ccu CLK_C1CPUX>; - clock-names = "cpu"; compatible = "arm,cortex-a7"; device_type = "cpu"; + clocks = <&ccu CLK_C1CPUX>; operating-points-v2 = <&cpu1_opp_table>; cci-control-port = <&cci_control1>; enable-method = "allwinner,sun8i-a83t-smp"; @@ -117,6 +118,7 @@ cpu@101 { compatible = "arm,cortex-a7"; device_type = "cpu"; + clocks = <&ccu CLK_C1CPUX>; operating-points-v2 = <&cpu1_opp_table>; cci-control-port = <&cci_control1>; enable-method = "allwinner,sun8i-a83t-smp"; @@ -127,6 +129,7 @@ cpu@102 { compatible = "arm,cortex-a7"; device_type = "cpu"; + clocks = <&ccu CLK_C1CPUX>; operating-points-v2 = <&cpu1_opp_table>; cci-control-port = <&cci_control1>; enable-method = "allwinner,sun8i-a83t-smp"; @@ -137,6 +140,7 @@ cpu@103 { compatible = "arm,cortex-a7"; device_type = "cpu"; + clocks = <&ccu CLK_C1CPUX>; operating-points-v2 = <&cpu1_opp_table>; cci-control-port = <&cci_control1>; enable-method = "allwinner,sun8i-a83t-smp"; -- cgit From c9d10c3e0e6ccdecf1a2a1e618a04c3d1c4f87e7 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 1 Apr 2019 23:13:55 +0200 Subject: ARM: dts: sunxi: Conform to DT spec for NAND controller The NAND controller node name should be nand-controller and not nand as we used previously according to the devicetree specification. Let's fix our DTs. Reviewed-by: Miquel Raynal Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 2 +- arch/arm/boot/dts/sun5i.dtsi | 2 +- arch/arm/boot/dts/sun7i-a20.dtsi | 2 +- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index b16595a69cba..ef6ec526f394 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -267,7 +267,7 @@ #dma-cells = <2>; }; - nfc: nand@1c03000 { + nfc: nand-controller@1c03000 { compatible = "allwinner,sun4i-a10-nand"; reg = <0x01c03000 0x1000>; interrupts = <37>; diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index f69ab288678b..8dd49016eb1e 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -189,7 +189,7 @@ #dma-cells = <2>; }; - nfc: nand@1c03000 { + nfc: nand-controller@1c03000 { compatible = "allwinner,sun4i-a10-nand"; reg = <0x01c03000 0x1000>; interrupts = <37>; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 28e1045853fc..794c915f504b 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -333,7 +333,7 @@ #dma-cells = <2>; }; - nfc: nand@1c03000 { + nfc: nand-controller@1c03000 { compatible = "allwinner,sun4i-a10-nand"; reg = <0x01c03000 0x1000>; interrupts = ; diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index a0247b4b5a1e..c17bd7677ffb 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -161,7 +161,7 @@ #dma-cells = <1>; }; - nfc: nand@1c03000 { + nfc: nand-controller@1c03000 { compatible = "allwinner,sun4i-a10-nand"; reg = <0x01c03000 0x1000>; interrupts = ; -- cgit From 612625bb96b02c579174e8470eaec289b202001a Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 1 Apr 2019 23:13:56 +0200 Subject: ARM: dts: sunxi: Remove useless address and size cells The NAND chips in our DTs have address and size cells, even though they don't have any child nodes. Remove them. Reviewed-by: Miquel Raynal Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-gr8-chip-pro.dts | 2 -- arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts | 2 -- 2 files changed, 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts b/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts index 533a4ecc05e2..a32cde3e32eb 100644 --- a/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts +++ b/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts @@ -133,8 +133,6 @@ status = "okay"; nand@0 { - #address-cells = <2>; - #size-cells = <2>; reg = <0>; allwinner,rb = <0>; nand-ecc-mode = "hw"; diff --git a/arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts b/arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts index 32cf1ab33aab..246dec5846a4 100644 --- a/arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts +++ b/arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts @@ -34,8 +34,6 @@ /* 2Gb Macronix MX30LF2G18AC (3V) */ nand@0 { - #address-cells = <1>; - #size-cells = <1>; reg = <0>; allwinner,rb = <0>; nand-ecc-mode = "hw"; -- cgit From a7586ad99e4727bcd92df374b88930400635c420 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 30 Mar 2019 08:08:11 +0100 Subject: ARM: dts: alt: Enable USB support Add nodes enabling internal PCI controllers to which the internal USB controllers are connected, add USB PHY node and pinmux nodes. Signed-off-by: Marek Vasut Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794-alt.dts | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts index e0500ec81569..0ab3d8d57f6d 100644 --- a/arch/arm/boot/dts/r8a7794-alt.dts +++ b/arch/arm/boot/dts/r8a7794-alt.dts @@ -199,6 +199,22 @@ }; }; +&pci0 { + status = "okay"; + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; +}; + +&pci1 { + status = "okay"; + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; +}; + +&usbphy { + status = "okay"; +}; + &du { pinctrl-0 = <&du_pins>; pinctrl-names = "default"; @@ -293,6 +309,16 @@ function = "sdhi1"; power-source = <1800>; }; + + usb0_pins: usb0 { + groups = "usb0"; + function = "usb0"; + }; + + usb1_pins: usb1 { + groups = "usb1"; + function = "usb1"; + }; }; &cmt0 { -- cgit From a8ab3547c7b4db9fb58fa3cbf136f3c94948effd Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Tue, 26 Mar 2019 23:38:40 -0700 Subject: ARM: dts: imx7d: Specify viewport count for PCIE block i.MX7D comes with 4 viewports, so configure PCIE node accordingly so that the driver won't assume we only have 2. Signed-off-by: Andrey Smirnov Cc: Richard Zhu Cc: Chris Healy Cc: Lucas Stach Cc: Fabio Estevam Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index 6eb98e7c568d..f33b560821b8 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -154,6 +154,7 @@ ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */ num-lanes = <1>; + num-viewport = <4>; interrupts = ; interrupt-names = "msi"; #interrupt-cells = <1>; -- cgit From 87fd3ce28b4694397692cecba233fe4e12298413 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Tue, 26 Mar 2019 23:38:41 -0700 Subject: ARM: dts: imx6qdl: Specify viewport count for PCIE block i.MX6 comes with 4 viewports, so configure PCIE node accordingly so that the driver won't assume we only have 2. Signed-off-by: Andrey Smirnov Cc: Richard Zhu Cc: Chris Healy Cc: Lucas Stach Cc: Fabio Estevam Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 2eb4c779298b..38b18a007f48 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -280,6 +280,7 @@ ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ num-lanes = <1>; + num-viewport = <4>; interrupts = ; interrupt-names = "msi"; #interrupt-cells = <1>; -- cgit From a9fc10280225443f92df6344ac6313d8a2f88c77 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Mon, 18 Dec 2017 16:46:00 +1030 Subject: ARM: dts: aspeed: ast2500: Update flash layout Move to the openbmc-flash-layout.dtsi file. Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-ast2500-evb.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts index 2375449c02d0..b80664826783 100644 --- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts @@ -27,6 +27,7 @@ status = "okay"; m25p,fast-read; label = "bmc"; +#include "openbmc-flash-layout.dtsi" }; }; -- cgit From e50c667b6432264b3920823facc0853bc15a1fc0 Mon Sep 17 00:00:00 2001 From: Lei YU Date: Fri, 15 Feb 2019 15:47:21 +0800 Subject: ARM: dts: aspeed: palmetto: Fix flash_memory region The flash_memory region was incorrect and exceeds AST2400's RAM range. Fix it by putting it before coldfire region, and aligned with 32MiB. Signed-off-by: Lei YU Acked-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts index b854ac0bae9a..b249da80fb83 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts @@ -32,9 +32,9 @@ no-map; }; - flash_memory: region@98000000 { + flash_memory: region@5c000000 { no-map; - reg = <0x98000000 0x01000000>; /* 16MB */ + reg = <0x5C000000 0x02000000>; /* 32MB */ }; }; -- cgit From a107bd2b6b63d510fecc402657f627dcfb205c89 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 11 Mar 2019 16:09:47 +0100 Subject: ARM: dts: sunxi: Remove pinctrl groups setting bias So far we've enabled pull-up and pull-down resistors on GPIOs using a pinctrl node. Now that the GPIO binding allows for a flag to declare this, let's switch to it. This brings us closer to removing all the GPIO pinctrl nodes, which will in turn allow us to switch the pinctrl strict mode on. Acked-by: Chen-Yu Tsai Reviewed-by: Linus Walleij Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts | 20 +----- arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 10 +-- arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts | 20 +----- arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts | 20 +----- arch/arm/boot/dts/sun4i-a10-inet1.dts | 20 +----- arch/arm/boot/dts/sun4i-a10-inet97fv2.dts | 20 +----- arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts | 72 +++++++--------------- arch/arm/boot/dts/sun4i-a10-marsboard.dts | 12 +--- arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts | 18 +----- arch/arm/boot/dts/sun4i-a10-pcduino.dts | 12 +--- arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts | 19 +----- arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts | 10 +-- arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 10 +-- .../boot/dts/sun5i-a13-empire-electronix-d709.dts | 20 +----- arch/arm/boot/dts/sun5i-a13-hsg-h702.dts | 12 +--- arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts | 18 +----- arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 18 +----- arch/arm/boot/dts/sun5i-a13-utoo-p66.dts | 14 +---- arch/arm/boot/dts/sun5i-r8-chip.dts | 12 +--- .../boot/dts/sun5i-reference-design-tablet.dtsi | 20 +----- arch/arm/boot/dts/sun6i-a31-colombus.dts | 14 +---- .../boot/dts/sun6i-reference-design-tablet.dtsi | 12 +--- arch/arm/boot/dts/sun7i-a20-bananapi.dts | 10 +-- arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 12 +--- arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts | 12 +--- arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts | 18 +----- arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts | 18 +----- arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 18 +----- arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts | 12 +--- arch/arm/boot/dts/sun7i-a20-orangepi.dts | 12 +--- arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts | 12 +--- arch/arm/boot/dts/sun7i-a20-pcduino3.dts | 12 +--- arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts | 12 +--- arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts | 12 +--- arch/arm/boot/dts/sun8i-r16-parrot.dts | 12 +--- .../boot/dts/sun8i-reference-design-tablet.dtsi | 12 +--- 36 files changed, 73 insertions(+), 514 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts b/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts index 66555e437ce4..74262988881c 100644 --- a/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts +++ b/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts @@ -131,20 +131,6 @@ status = "okay"; }; -&pio { - usb0_id_detect_pin: usb0-id-detect-pin { - pins = "PH4"; - function = "gpio_in"; - bias-pull-up; - }; - - usb0_vbus_detect_pin: usb0-vbus-detect-pin { - pins = "PH5"; - function = "gpio_in"; - bias-pull-down; - }; -}; - ®_usb0_vbus { status = "okay"; }; @@ -165,10 +151,8 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ + usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts index d5eb2a151b89..7306c65df88a 100644 --- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts +++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts @@ -184,12 +184,6 @@ function = "gpio_out"; drive-strength = <20>; }; - - usb0_id_detect_pin: usb0-id-detect-pin { - pins = "PH4"; - function = "gpio_in"; - bias-pull-up; - }; }; ®_ahci_5v { @@ -254,9 +248,7 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts b/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts index f7af24cb66e7..8ee3ff42bd55 100644 --- a/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts +++ b/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts @@ -158,20 +158,6 @@ status = "okay"; }; -&pio { - usb0_id_detect_pin: usb0-id-detect-pin { - pins = "PH4"; - function = "gpio_in"; - bias-pull-up; - }; - - usb0_vbus_detect_pin: usb0-vbus-detect-pin { - pins = "PH5"; - function = "gpio_in"; - bias-pull-down; - }; -}; - &pwm { pinctrl-names = "default"; pinctrl-0 = <&pwm0_pin>; @@ -223,10 +209,8 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ + usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts b/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts index 0cf752a990b9..bf2044bac42f 100644 --- a/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts +++ b/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts @@ -86,20 +86,6 @@ status = "okay"; }; -&pio { - usb0_id_detect_pin: usb0-id-detect-pin { - pins = "PH4"; - function = "gpio_in"; - bias-pull-up; - }; - - usb0_vbus_detect_pin: usb0-vbus-detect-pin { - pins = "PH5"; - function = "gpio_in"; - bias-pull-down; - }; -}; - ®_usb0_vbus { status = "okay"; }; @@ -121,10 +107,8 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ + usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun4i-a10-inet1.dts b/arch/arm/boot/dts/sun4i-a10-inet1.dts index 2e5c452ca9c6..ca878384e902 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet1.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet1.dts @@ -164,20 +164,6 @@ status = "okay"; }; -&pio { - usb0_id_detect_pin: usb0-id-detect-pin { - pins = "PH4"; - function = "gpio_in"; - bias-pull-up; - }; - - usb0_vbus_detect_pin: usb0-vbus-detect-pin { - pins = "PH5"; - function = "gpio_in"; - bias-pull-down; - }; -}; - &pwm { pinctrl-names = "default"; pinctrl-0 = <&pwm0_pin>; @@ -233,10 +219,8 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ + usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts index c1ff846cb442..76016f2ca29d 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts @@ -150,20 +150,6 @@ status = "okay"; }; -&pio { - usb0_id_detect_pin: usb0-id-detect-pin { - pins = "PH4"; - function = "gpio_in"; - bias-pull-up; - }; - - usb0_vbus_detect_pin: usb0-vbus-detect-pin { - pins = "PH5"; - function = "gpio_in"; - bias-pull-down; - }; -}; - ®_dcdc2 { regulator-always-on; regulator-min-microvolt = <1000000>; @@ -209,10 +195,8 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ + usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts index 31ba7b93df51..0a562b2cc5bc 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts @@ -61,8 +61,6 @@ gpio-keys { compatible = "gpio-keys-polled"; - pinctrl-names = "default"; - pinctrl-0 = <&key_pins_inet9f>; poll-interval = <20>; left-joystick-left { @@ -70,7 +68,7 @@ linux,code = ; linux,input-type = ; linux,input-value = <0xffffffff>; /* -1 */ - gpios = <&pio 0 6 GPIO_ACTIVE_LOW>; /* PA6 */ + gpios = <&pio 0 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA6 */ }; left-joystick-right { @@ -78,7 +76,7 @@ linux,code = ; linux,input-type = ; linux,input-value = <1>; - gpios = <&pio 0 5 GPIO_ACTIVE_LOW>; /* PA5 */ + gpios = <&pio 0 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA5 */ }; left-joystick-up { @@ -86,7 +84,7 @@ linux,code = ; linux,input-type = ; linux,input-value = <0xffffffff>; /* -1 */ - gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ + gpios = <&pio 0 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA8 */ }; left-joystick-down { @@ -94,7 +92,7 @@ linux,code = ; linux,input-type = ; linux,input-value = <1>; - gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */ + gpios = <&pio 0 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA9 */ }; right-joystick-left { @@ -102,7 +100,7 @@ linux,code = ; linux,input-type = ; linux,input-value = <0xffffffff>; /* -1 */ - gpios = <&pio 0 1 GPIO_ACTIVE_LOW>; /* PA1 */ + gpios = <&pio 0 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA1 */ }; right-joystick-right { @@ -110,7 +108,7 @@ linux,code = ; linux,input-type = ; linux,input-value = <1>; - gpios = <&pio 0 0 GPIO_ACTIVE_LOW>; /* PA0 */ + gpios = <&pio 0 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA0 */ }; right-joystick-up { @@ -118,7 +116,7 @@ linux,code = ; linux,input-type = ; linux,input-value = <0xffffffff>; /* -1 */ - gpios = <&pio 0 3 GPIO_ACTIVE_LOW>; /* PA3 */ + gpios = <&pio 0 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA3 */ }; right-joystick-down { @@ -126,7 +124,7 @@ linux,code = ; linux,input-type = ; linux,input-value = <1>; - gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */ + gpios = <&pio 0 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA4 */ }; dpad-left { @@ -134,7 +132,7 @@ linux,code = ; linux,input-type = ; linux,input-value = <0xffffffff>; /* -1 */ - gpios = <&pio 7 23 GPIO_ACTIVE_LOW>; /* PH23 */ + gpios = <&pio 7 23 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH23 */ }; dpad-right { @@ -142,7 +140,7 @@ linux,code = ; linux,input-type = ; linux,input-value = <1>; - gpios = <&pio 7 24 GPIO_ACTIVE_LOW>; /* PH24 */ + gpios = <&pio 7 24 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH24 */ }; dpad-up { @@ -150,7 +148,7 @@ linux,code = ; linux,input-type = ; linux,input-value = <0xffffffff>; /* -1 */ - gpios = <&pio 7 25 GPIO_ACTIVE_LOW>; /* PH25 */ + gpios = <&pio 7 25 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH25 */ }; dpad-down { @@ -158,55 +156,55 @@ linux,code = ; linux,input-type = ; linux,input-value = <1>; - gpios = <&pio 7 26 GPIO_ACTIVE_LOW>; /* PH26 */ + gpios = <&pio 7 26 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH26 */ }; x { label = "Button X"; linux,code = ; - gpios = <&pio 0 16 GPIO_ACTIVE_LOW>; /* PA16 */ + gpios = <&pio 0 16 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA16 */ }; y { label = "Button Y"; linux,code = ; - gpios = <&pio 0 14 GPIO_ACTIVE_LOW>; /* PA14 */ + gpios = <&pio 0 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA14 */ }; a { label = "Button A"; linux,code = ; - gpios = <&pio 0 17 GPIO_ACTIVE_LOW>; /* PA17 */ + gpios = <&pio 0 17 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA17 */ }; b { label = "Button B"; linux,code = ; - gpios = <&pio 0 15 GPIO_ACTIVE_LOW>; /* PA15 */ + gpios = <&pio 0 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA15 */ }; select { label = "Select Button"; linux,code = ; - gpios = <&pio 0 11 GPIO_ACTIVE_LOW>; /* PA11 */ + gpios = <&pio 0 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA11 */ }; start { label = "Start Button"; linux,code = ; - gpios = <&pio 0 12 GPIO_ACTIVE_LOW>; /* PA12 */ + gpios = <&pio 0 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA12 */ }; top-left { label = "Top Left Button"; linux,code = ; - gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */ + gpios = <&pio 7 22 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH22 */ }; top-right { label = "Top Right Button"; linux,code = ; - gpios = <&pio 0 13 GPIO_ACTIVE_LOW>; /* PA13 */ + gpios = <&pio 0 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA13 */ }; }; }; @@ -306,30 +304,6 @@ status = "okay"; }; -&pio { - key_pins_inet9f: key-pins { - pins = "PA0", "PA1", "PA3", "PA4", - "PA5", "PA6", "PA8", "PA9", - "PA11", "PA12", "PA13", - "PA14", "PA15", "PA16", "PA17", - "PH22", "PH23", "PH24", "PH25", "PH26"; - function = "gpio_in"; - bias-pull-up; - }; - - usb0_id_detect_pin: usb0-id-detect-pin { - pins = "PH4"; - function = "gpio_in"; - bias-pull-up; - }; - - usb0_vbus_detect_pin: usb0-vbus-detect-pin { - pins = "PH5"; - function = "gpio_in"; - bias-pull-down; - }; -}; - ®_dcdc2 { regulator-always-on; regulator-min-microvolt = <1000000>; @@ -375,10 +349,8 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ + usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun4i-a10-marsboard.dts b/arch/arm/boot/dts/sun4i-a10-marsboard.dts index cb94e083ea3b..58ad2ad9041f 100644 --- a/arch/arm/boot/dts/sun4i-a10-marsboard.dts +++ b/arch/arm/boot/dts/sun4i-a10-marsboard.dts @@ -148,14 +148,6 @@ status = "okay"; }; -&pio { - usb0_id_detect_pin: usb0-id-detect-pin { - pins = "PH4"; - function = "gpio_in"; - bias-pull-up; - }; -}; - ®_usb1_vbus { status = "okay"; }; @@ -183,9 +175,7 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts index 4cbc58363caf..7c1f379c3aed 100644 --- a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts +++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts @@ -186,18 +186,6 @@ function = "gpio_out"; drive-strength = <20>; }; - - usb0_id_detect_pin: usb0-id-detect-pin { - pins = "PH4"; - function = "gpio_in"; - bias-pull-up; - }; - - usb0_vbus_detect_pin: usb0-vbus-detect-pin { - pins = "PH5"; - function = "gpio_in"; - bias-pull-down; - }; }; ®_ahci_5v { @@ -229,10 +217,8 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_id_det-gpio = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ + usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts index 08f3e385fe63..0f1e781069e9 100644 --- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts +++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts @@ -154,14 +154,6 @@ status = "okay"; }; -&pio { - usb0_id_detect_pin: usb0-id-detect-pin { - pins = "PH4"; - function = "gpio_in"; - bias-pull-up; - }; -}; - #include "axp209.dtsi" ®_dcdc2 { @@ -201,9 +193,7 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ usb1_vbus-supply = <®_vcc5v0>; /* USB1 VBUS is always on */ usb2_vbus-supply = <®_vcc5v0>; /* USB2 VBUS is always on */ status = "okay"; diff --git a/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts b/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts index cd516543a9e5..bcb2fc0c56b1 100644 --- a/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts +++ b/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts @@ -146,20 +146,6 @@ status = "okay"; }; -&pio { - usb0_id_detect_pin: usb0-id-detect-pin { - pins = "PH4"; - function = "gpio_in"; - bias-pull-up; - }; - - usb0_vbus_detect_pin: usb0-vbus-detect-pin { - pins = "PH5"; - function = "gpio_in"; - bias-pull-down; - }; -}; - &pwm { pinctrl-names = "default"; pinctrl-0 = <&pwm0_pin>; @@ -212,9 +198,8 @@ &usbphy { pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ + usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts index 6d7a2f4bd05c..8af0eae2ddc1 100644 --- a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts +++ b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts @@ -119,12 +119,6 @@ }; &pio { - usb0_id_detect_pin: usb0-id-detect-pin { - pins = "PG12"; - function = "gpio_in"; - bias-pull-up; - }; - led_pins_t004: led-pin { pins = "PB2"; function = "gpio_out"; @@ -149,9 +143,7 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + usb0_id_det-gpios = <&pio 6 12 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG12 */ usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts index 430caf873fe2..5340b4164df2 100644 --- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts @@ -218,12 +218,6 @@ function = "gpio_out"; drive-strength = <20>; }; - - usb0_id_detect_pin: usb0-id-detect-pin { - pins = "PG12"; - function = "gpio_in"; - bias-pull-up; - }; }; ®_usb0_vbus { @@ -271,9 +265,7 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + usb0_id_det-gpios = <&pio 6 12 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG12 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts index ac3b2221cdef..a23bf24792ec 100644 --- a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts +++ b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts @@ -127,20 +127,6 @@ status = "okay"; }; -&pio { - usb0_vbus_detect_pin: usb0-vbus-detect-pin { - pins = "PG1"; - function = "gpio_in"; - bias-pull-down; - }; - - usb0_id_detect_pin: usb0-id-detect-pin { - pins = "PG2"; - function = "gpio_in"; - bias-pull-up; - }; -}; - &pwm { pinctrl-names = "default"; pinctrl-0 = <&pwm0_pin>; @@ -195,10 +181,8 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ - usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ + usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */ + usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_ldo3>; status = "okay"; diff --git a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts index 9369f7453beb..9b9f2a574851 100644 --- a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts +++ b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts @@ -124,14 +124,6 @@ status = "okay"; }; -&pio { - usb0_id_detect_pin: usb0-id-detect-pin { - pins = "PG2"; - function = "gpio_in"; - bias-pull-up; - }; -}; - #include "axp209.dtsi" ®_dcdc2 { @@ -182,9 +174,7 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ + usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */ usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_ldo3>; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts index f8dc4bbf249c..5df398d77238 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts @@ -109,18 +109,6 @@ function = "gpio_out"; drive-strength = <20>; }; - - usb0_id_detect_pin: usb0-id-detect-pin { - pins = "PG2"; - function = "gpio_in"; - bias-pull-up; - }; - - usb0_vbus_detect_pin: usb0-vbus-detect-pin { - pins = "PG1"; - function = "gpio_in"; - bias-pull-down; - }; }; ®_usb0_vbus { @@ -145,10 +133,8 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ - usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ + usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */ + usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts index e49596c721a9..39101228a755 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts @@ -202,18 +202,6 @@ function = "gpio_out"; drive-strength = <20>; }; - - usb0_id_detect_pin: usb0-id-detect-pin { - pins = "PG2"; - function = "gpio_in"; - bias-pull-up; - }; - - usb0_vbus_detect_pin: usb0-vbus-detect-pin { - pins = "PG1"; - function = "gpio_in"; - bias-pull-down; - }; }; ®_usb0_vbus { @@ -251,10 +239,8 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ - usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ + usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */ + usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts index 379d530ea2a7..be486d28d04f 100644 --- a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts +++ b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts @@ -61,10 +61,8 @@ i2c_lcd: i2c { /* The lcd panel i2c interface is hooked up via gpios */ compatible = "i2c-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c_lcd_pins>; - sda-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - scl-gpios = <&pio 6 10 GPIO_ACTIVE_HIGH>; /* PG10 */ + sda-gpios = <&pio 6 12 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG12 */ + scl-gpios = <&pio 6 10 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG10 */ i2c-gpio,delay-us = <5>; }; }; @@ -94,14 +92,6 @@ }; }; -&pio { - i2c_lcd_pins: i2c-lcd-pin { - pins = "PG10", "PG12"; - function = "gpio_out"; - bias-pull-up; - }; -}; - ®_usb0_vbus { gpio = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ }; diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts index de5e67497f20..4bf4943d4eb7 100644 --- a/arch/arm/boot/dts/sun5i-r8-chip.dts +++ b/arch/arm/boot/dts/sun5i-r8-chip.dts @@ -84,9 +84,7 @@ onewire { compatible = "w1-gpio"; - gpios = <&pio 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */ - pinctrl-names = "default"; - pinctrl-0 = <&chip_w1_pin>; + gpios = <&pio 3 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PD2 */ }; }; @@ -173,14 +171,6 @@ status = "okay"; }; -&pio { - chip_w1_pin: chip-w1-pin { - pins = "PD2"; - function = "gpio_in"; - bias-pull-up; - }; -}; - ®_dcdc2 { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1400000>; diff --git a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi index cf33ad09ef1e..1a9926d71410 100644 --- a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi @@ -132,20 +132,6 @@ status = "okay"; }; -&pio { - usb0_vbus_detect_pin: usb0-vbus-detect-pin { - pins = "PG1"; - function = "gpio_in"; - bias-pull-down; - }; - - usb0_id_detect_pin: usb0-id-detect-pin { - pins = "PG2"; - function = "gpio_in"; - bias-pull-up; - }; -}; - ®_dcdc2 { regulator-always-on; regulator-min-microvolt = <1000000>; @@ -198,10 +184,8 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ - usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ + usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */ + usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */ usb0_vbus_power-supply = <&usb_power_supply>; usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_ldo3>; diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/sun6i-a31-colombus.dts index 0e62b4042100..c3d56dc93513 100644 --- a/arch/arm/boot/dts/sun6i-a31-colombus.dts +++ b/arch/arm/boot/dts/sun6i-a31-colombus.dts @@ -63,10 +63,8 @@ i2c_lcd: i2c { /* The lcd panel i2c interface is hooked up via gpios */ compatible = "i2c-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c_lcd_pins>; - sda-gpios = <&pio 0 23 GPIO_ACTIVE_HIGH>; /* PA23 */ - scl-gpios = <&pio 0 24 GPIO_ACTIVE_HIGH>; /* PA24 */ + sda-gpios = <&pio 0 23 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PA23 */ + scl-gpios = <&pio 0 24 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PA24 */ i2c-gpio,delay-us = <5>; }; }; @@ -113,14 +111,6 @@ status = "okay"; }; -&pio { - i2c_lcd_pins: i2c-lcd-pins { - pins = "PA23", "PA24"; - function = "gpio_out"; - bias-pull-up; - }; -}; - ®_usb2_vbus { gpio = <&pio 7 24 GPIO_ACTIVE_HIGH>; status = "okay"; diff --git a/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi index 1ebc042f5e6c..7de2abd541c1 100644 --- a/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi @@ -73,14 +73,6 @@ status = "okay"; }; -&pio { - usb0_id_detect_pin: usb0-id-detect-pin { - pins = "PA15"; - function = "gpio_in"; - bias-pull-up; - }; -}; - &p2wi { status = "okay"; @@ -173,9 +165,7 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */ + usb0_id_det-gpios = <&pio 0 15 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PA15 */ usb0_vbus_power-supply = <&usb_power_supply>; usb0_vbus-supply = <®_drivevbus>; usb1_vbus-supply = <®_dldo1>; diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi.dts b/arch/arm/boot/dts/sun7i-a20-bananapi.dts index 76252455d485..4df921632f7a 100644 --- a/arch/arm/boot/dts/sun7i-a20-bananapi.dts +++ b/arch/arm/boot/dts/sun7i-a20-bananapi.dts @@ -246,12 +246,6 @@ "SPI-MISO", "SPI-CE1", "", "IO-6", "IO-3", "IO-2", "IO-0", "", "", "", "", "", "", "", "", "", "", "", ""; - - usb0_id_detect_pin: usb0-id-detect-pin { - pins = "PH4"; - function = "gpio_in"; - bias-pull-up; - }; }; #include "axp209.dtsi" @@ -329,9 +323,7 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ usb0_vbus_power-supply = <&usb_power_supply>; usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts index 365ac2b9bcdf..08e5a5abf8cc 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts @@ -173,14 +173,6 @@ status = "okay"; }; -&pio { - usb0_id_detect_pin: usb0-id-detect-pin { - pins = "PH4"; - function = "gpio_in"; - bias-pull-up; - }; -}; - ®_ahci_5v { status = "okay"; }; @@ -236,9 +228,7 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts index 0a87a45787ae..3e170cfac86a 100644 --- a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts +++ b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts @@ -229,14 +229,6 @@ status = "okay"; }; -&pio { - usb0_id_detect_pin: usb0-id-detect-pin { - pins = "PH4"; - function = "gpio_in"; - bias-pull-up; - }; -}; - #include "axp209.dtsi" &ac_power_supply { @@ -322,9 +314,7 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ usb0_vbus_power-supply = <&usb_power_supply>; usb0_vbus-supply = <®_usb0_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts index fafe01ee5ea0..e40dd47df8ce 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts @@ -174,18 +174,6 @@ function = "gpio_out"; drive-strength = <20>; }; - - usb0_id_detect_pin: usb0-id-detect-pin { - pins = "PH4"; - function = "gpio_in"; - bias-pull-up; - }; - - usb0_vbus_detect_pin: usb0-vbus-detect-pin { - pins = "PH5"; - function = "gpio_in"; - bias-pull-down; - }; }; ®_ahci_5v { @@ -217,10 +205,8 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ + usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts index bdf894c054db..95c6f8949076 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts @@ -185,18 +185,6 @@ function = "gpio_out"; drive-strength = <20>; }; - - usb0_id_detect_pin: usb0-id-detect-pin { - pins = "PH4"; - function = "gpio_in"; - bias-pull-up; - }; - - usb0_vbus_detect_pin: usb0-vbus-detect-pin { - pins = "PH5"; - function = "gpio_in"; - bias-pull-down; - }; }; ®_ahci_5v { @@ -273,10 +261,8 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ + usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts index ba18e14fa229..0dcba070444a 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts @@ -252,18 +252,6 @@ function = "gpio_out"; drive-strength = <20>; }; - - usb0_id_detect_pin: usb0-id-detect-pin { - pins = "PH4"; - function = "gpio_in"; - bias-pull-up; - }; - - usb0_vbus_detect_pin: usb0-vbus-detect-pin { - pins = "PH5"; - function = "gpio_in"; - bias-pull-down; - }; }; #include "axp209.dtsi" @@ -355,10 +343,8 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ + usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts b/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts index 872f6f35d40d..9628041bb3a3 100644 --- a/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts +++ b/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts @@ -176,14 +176,6 @@ status = "okay"; }; -&pio { - usb0_id_detect_pin: usb0-id-detect-pin { - pins = "PH4"; - function = "gpio_in"; - bias-pull-up; - }; -}; - ®_dcdc2 { regulator-always-on; regulator-min-microvolt = <1000000>; @@ -239,9 +231,7 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ usb0_vbus_power-supply = <&usb_power_supply>; usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; diff --git a/arch/arm/boot/dts/sun7i-a20-orangepi.dts b/arch/arm/boot/dts/sun7i-a20-orangepi.dts index 93fa89b84a88..7b3532665c28 100644 --- a/arch/arm/boot/dts/sun7i-a20-orangepi.dts +++ b/arch/arm/boot/dts/sun7i-a20-orangepi.dts @@ -135,14 +135,6 @@ status = "okay"; }; -&pio { - usb0_id_detect_pin: usb0-id-detect-pin { - pins = "PH4"; - function = "gpio_in"; - bias-pull-up; - }; -}; - ®_dcdc2 { regulator-always-on; regulator-min-microvolt = <1000000>; @@ -198,9 +190,7 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ usb0_vbus_power-supply = <&usb_power_supply>; usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts index 24781f5c231e..173b676436e9 100644 --- a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts +++ b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts @@ -168,14 +168,6 @@ status = "okay"; }; -&pio { - usb0_id_detect_pin: usb0-id-detect-pin { - pins = "PH4"; - function = "gpio_in"; - bias-pull-up; - }; -}; - ®_ahci_5v { gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ status = "okay"; @@ -226,9 +218,7 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb1_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts index 606630ac5f3a..14a88aa16a97 100644 --- a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts +++ b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts @@ -168,14 +168,6 @@ status = "okay"; }; -&pio { - usb0_id_detect_pin: usb0-id-detect-pin { - pins = "PH4"; - function = "gpio_in"; - bias-pull-up; - }; -}; - ®_ahci_5v { gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; status = "okay"; @@ -226,9 +218,7 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts b/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts index 80ead52db270..6a66b0432dfa 100644 --- a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts +++ b/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts @@ -156,14 +156,6 @@ status = "okay"; }; -&pio { - usb0_id_detect_pin: usb0-id-detect-pin { - pins = "PH4"; - function = "gpio_in"; - bias-pull-up; - }; -}; - &pwm { pinctrl-names = "default"; pinctrl-0 = <&pwm0_pin>; @@ -223,9 +215,7 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ usb0_vbus_power-supply = <&usb_power_supply>; usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; diff --git a/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts b/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts index 57a4d6a5d163..f8475a39777b 100644 --- a/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts +++ b/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts @@ -145,14 +145,6 @@ status = "okay"; }; -&pio { - usb0_id_detect_pin: usb0-id-detect-pin { - pins = "PH4"; - function = "gpio_in"; - bias-pull-up; - }; -}; - ®_dcdc2 { regulator-always-on; regulator-min-microvolt = <1000000>; @@ -206,9 +198,7 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ usb0_vbus_power-supply = <&usb_power_supply>; usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; diff --git a/arch/arm/boot/dts/sun8i-r16-parrot.dts b/arch/arm/boot/dts/sun8i-r16-parrot.dts index 316998e9ec5d..4f48eec6b2ef 100644 --- a/arch/arm/boot/dts/sun8i-r16-parrot.dts +++ b/arch/arm/boot/dts/sun8i-r16-parrot.dts @@ -158,14 +158,6 @@ status = "okay"; }; -&pio { - usb0_id_det: usb0-id-detect-pin { - pins = "PD10"; - function = "gpio_in"; - bias-pull-up; - }; -}; - &r_rsb { status = "okay"; @@ -314,10 +306,8 @@ &usbphy { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_det>; usb0_vbus-supply = <®_drivevbus>; - usb0_id_det-gpios = <&pio 3 10 GPIO_ACTIVE_HIGH>; /* PD10 */ + usb0_id_det-gpios = <&pio 3 10 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PD10 */ usb0_vbus_power-supply = <&usb_power_supply>; usb1_vbus-supply = <®_usb1_vbus>; }; diff --git a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi index c773ddf45e66..b3d8b8f056cd 100644 --- a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi @@ -86,14 +86,6 @@ status = "okay"; }; -&pio { - usb0_id_detect_pin: usb0-id-detect-pin { - pins = "PH8"; - function = "gpio_in"; - bias-pull-up; - }; -}; - &r_rsb { status = "okay"; @@ -224,9 +216,7 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */ + usb0_id_det-gpios = <&pio 7 8 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH8 */ usb0_vbus_power-supply = <&usb_power_supply>; usb0_vbus-supply = <®_drivevbus>; status = "okay"; -- cgit From 18009b802bd1c577b7bb2ad9b506d4a186bac72d Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 11 Mar 2019 16:14:50 +0100 Subject: ARM: dts: sunxi: Remove useless pinctrl nodes We have for the H3 boards some kind of cargo cult apparently, where we would have a pinctrl node even for GPIOs without any particular settings. This is pretty much useless, so let's remove them. Acked-by: Chen-Yu Tsai Reviewed-by: Linus Walleij Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3-nanopi.dtsi | 23 --------------------- arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 30 ---------------------------- arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts | 23 --------------------- arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 23 --------------------- arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 23 --------------------- arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 9 --------- 6 files changed, 131 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi index f110ee382239..ec2a05ff4b96 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi +++ b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi @@ -59,8 +59,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&leds_npi>, <&leds_r_npi>; status { label = "nanopi:blue:status"; @@ -78,8 +76,6 @@ r_gpio_keys { compatible = "gpio-keys"; input-name = "k1"; - pinctrl-names = "default"; - pinctrl-0 = <&sw_r_npi>; k1 { label = "k1"; @@ -104,25 +100,6 @@ status = "okay"; }; -&pio { - leds_npi: led_pins { - pins = "PA10"; - function = "gpio_out"; - }; -}; - -&r_pio { - leds_r_npi: led_pins { - pins = "PL10"; - function = "gpio_out"; - }; - - sw_r_npi: key_pins { - pins = "PL3"; - function = "gpio_in"; - }; -}; - &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts index f1fc6bdca8be..aa994e4a4abc 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts @@ -75,8 +75,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&leds_opc>, <&leds_r_opc>; status_led { label = "orangepi:red:status"; @@ -92,8 +90,6 @@ r_gpio_keys { compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&sw_r_opc>; sw2 { label = "sw2"; @@ -110,8 +106,6 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_pwrseq_pin_orangepi>; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 WIFI_EN */ }; }; @@ -179,30 +173,6 @@ }; }; -&pio { - leds_opc: led_pins { - pins = "PA15"; - function = "gpio_out"; - }; -}; - -&r_pio { - leds_r_opc: led_pins { - pins = "PL10"; - function = "gpio_out"; - }; - - sw_r_opc: key_pins { - pins = "PL3", "PL4"; - function = "gpio_in"; - }; - - wifi_pwrseq_pin_orangepi: wifi_pwrseq_pin { - pins = "PL7"; - function = "gpio_out"; - }; -}; - ®_usb1_vbus { gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; status = "okay"; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts index 476ae8e387ca..34d8e5d236c9 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts @@ -74,8 +74,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&leds_opc>, <&leds_r_opc>; pwr_led { label = "orangepi:green:pwr"; @@ -91,8 +89,6 @@ r_gpio_keys { compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&sw_r_opc>; sw4 { label = "sw4"; @@ -160,25 +156,6 @@ status = "okay"; }; -&pio { - leds_opc: led_pins { - pins = "PA15"; - function = "gpio_out"; - }; -}; - -&r_pio { - leds_r_opc: led_pins { - pins = "PL10"; - function = "gpio_out"; - }; - - sw_r_opc: key_pins { - pins = "PL3"; - function = "gpio_in"; - }; -}; - &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts index 245fd658defb..a0026e03c295 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts @@ -73,8 +73,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&leds_opc>, <&leds_r_opc>; pwr_led { label = "orangepi:green:pwr"; @@ -90,8 +88,6 @@ r_gpio_keys { compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&sw_r_opc>; sw4 { label = "sw4"; @@ -166,25 +162,6 @@ status = "okay"; }; -&pio { - leds_opc: led_pins { - pins = "PA15"; - function = "gpio_out"; - }; -}; - -&r_pio { - leds_r_opc: led_pins { - pins = "PL10"; - function = "gpio_out"; - }; - - sw_r_opc: key_pins { - pins = "PL3"; - function = "gpio_in"; - }; -}; - ®_usb0_vbus { gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ status = "okay"; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts index 46240334128f..22393c135f06 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts @@ -73,8 +73,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&leds_opc>, <&leds_r_opc>; pwr_led { label = "orangepi:green:pwr"; @@ -90,8 +88,6 @@ r_gpio_keys { compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&sw_r_opc>; sw4 { label = "sw4"; @@ -179,13 +175,6 @@ status = "okay"; }; -&pio { - leds_opc: led_pins { - pins = "PA15"; - function = "gpio_out"; - }; -}; - &r_i2c { status = "okay"; @@ -210,18 +199,6 @@ }; }; -&r_pio { - leds_r_opc: led_pins { - pins = "PL10"; - function = "gpio_out"; - }; - - sw_r_opc: key_pins { - pins = "PL3"; - function = "gpio_in"; - }; -}; - ®_usb0_vbus { gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ status = "okay"; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts index ac8438c2cff1..97f497854e05 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts @@ -63,8 +63,6 @@ reg_usb3_vbus: usb3-vbus { compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&usb3_vbus_pin_a>; regulator-name = "usb3-vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -116,13 +114,6 @@ bias-pull-up; }; -&pio { - usb3_vbus_pin_a: usb3_vbus_pin { - pins = "PG11"; - function = "gpio_out"; - }; -}; - &r_i2c { status = "okay"; -- cgit From 66e7ff850f5213fb0a20fc28ddfd8b07604eaff6 Mon Sep 17 00:00:00 2001 From: Eddie James Date: Thu, 21 Mar 2019 14:30:09 -0500 Subject: ARM: dts: aspeed: witherspoon: Enable vhub Enable the virtual USB hub. Signed-off-by: Eddie James Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts index ad54117c075e..63977adaf4ba 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts @@ -592,3 +592,7 @@ &adc { status = "okay"; }; + +&vhub { + status = "okay"; +}; -- cgit From e1920e704829f00cdfe6131f51f23dbe590b217f Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Thu, 19 Apr 2018 13:50:02 +0930 Subject: ARM: dts: aspeed-g5: Add resets and clocks to GFX node The ast2500 has a reset for the CRT device that must be deasserted before it can be used. Similarly it has a clock gate for a clock called D1CLK that must be set to running. Reviewed-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g5.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index 85ed9dbec196..04221188b64a 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -232,6 +232,10 @@ compatible = "aspeed,ast2500-gfx", "syscon"; reg = <0x1e6e6000 0x1000>; reg-io-width = <4>; + clocks = <&syscon ASPEED_CLK_GATE_D1CLK>; + resets = <&syscon ASPEED_RESET_CRT1>; + status = "disabled"; + interrupts = <0x19>; }; adc: adc@1e6e9000 { -- cgit From 5de3b03173f8054e2fd52420452dbc46568f3f2e Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Thu, 19 Apr 2018 13:50:03 +0930 Subject: ARM: dts: aspeed: Enable the GFX IP The GFX controller is the internal graphics device used by the SoC (opposed to the one connected via the PCIe device and used by the host). This configures it with a framebuffer region and adds it to the command line so kernel boot messages appear on the display. Enabled for Romulus, Witherspoon, and the ASPEED AST2500 EVB. Reviewed-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-ast2500-evb.dts | 20 +++++++++++++++++++- arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts | 8 ++++++++ arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts | 8 ++++++++ 3 files changed, 35 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts index b80664826783..556ed469830c 100644 --- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts @@ -13,12 +13,25 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=tty0 console=ttyS4,115200 earlyprintk"; }; memory@80000000 { reg = <0x80000000 0x20000000>; }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; }; &fmc { @@ -98,3 +111,8 @@ &uhci { status = "okay"; }; + +&gfx { + status = "okay"; + memory-region = <&gfx_memory>; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts index 76fe994f2ba4..418a1988b262 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts @@ -35,6 +35,13 @@ reg = <0x9ef00000 0x00100000>; no-map; }; + + gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; }; leds { @@ -238,6 +245,7 @@ &gfx { status = "okay"; + memory-region = <&gfx_memory>; }; &pinctrl { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts index 63977adaf4ba..fc7e6432eb2c 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts @@ -26,6 +26,13 @@ no-map; reg = <0x98000000 0x04000000>; /* 64M */ }; + + gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; }; gpio-keys { @@ -565,6 +572,7 @@ &gfx { status = "okay"; + memory-region = <&gfx_memory>; }; &pinctrl { -- cgit From 796b440701995445c0365cfa3f6e558c9a9e76f7 Mon Sep 17 00:00:00 2001 From: Eddie James Date: Tue, 2 Apr 2019 18:25:04 +0000 Subject: ARM: dts: aspeed-g5: Add video engine Add a node to describe the video engine on the AST2500. Signed-off-by: Eddie James Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g5.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index 04221188b64a..733cac9eeef4 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -247,6 +247,16 @@ status = "disabled"; }; + video: video@1e700000 { + compatible = "aspeed,ast2500-video-engine"; + reg = <0x1e700000 0x1000>; + clocks = <&syscon ASPEED_CLK_GATE_VCLK>, + <&syscon ASPEED_CLK_GATE_ECLK>; + clock-names = "vclk", "eclk"; + interrupts = <7>; + status = "disabled"; + }; + sram: sram@1e720000 { compatible = "mmio-sram"; reg = <0x1e720000 0x9000>; // 36K -- cgit From ffdbf494821dd81de0c625f3fcfbed8a0f2d9f51 Mon Sep 17 00:00:00 2001 From: Vijay Khemka Date: Wed, 30 Jan 2019 10:14:26 -0800 Subject: ARM: dts: aspeed: tiogapass: Enable VUART Enabling vuart for Facebook tiogapass Signed-off-by: Vijay Khemka Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts index 4c2dcac738e8..c4521eda787c 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts @@ -64,6 +64,11 @@ status = "okay"; }; +&vuart { + // VUART Host Console + status = "okay"; +}; + &uart1 { // Host Console status = "okay"; -- cgit From 972f0e069d11f7b217033f92f89af1309a29736b Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Tue, 5 Feb 2019 14:46:19 -0800 Subject: ARM: dts: aspeed: cmm: enable iio-hwmon-adc Bind aspeed ADC channels 0-7 to "iio-hwmon" driver so the data of these voltage sensing channels can be accessed by "lm_sensors". Channels 8-15 are not used on CMM BMC. Signed-off-by: Tao Ren Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts index 9f194b5eeba4..43aba4071a5c 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts @@ -56,6 +56,12 @@ memory@80000000 { reg = <0x80000000 0x20000000>; }; + + ast-adc-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>; + }; }; &pinctrl { -- cgit From 780726f996551a23bcf34f9980f14375abda073e Mon Sep 17 00:00:00 2001 From: "Edward A. James" Date: Wed, 3 Apr 2019 11:59:11 -0500 Subject: ARM: dts: aspeed: witherspoon: Update BMC partitioning MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add simplified partitions for BMC and alternate flash. Include these by default in Witherspoon. Signed-off-by: Edward A. James Signed-off-by: Adriana Kobylak Reviewed-by: Cédric Le Goater Reviewed-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts | 40 ++++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts index fc7e6432eb2c..f1356ca794d8 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts @@ -193,13 +193,49 @@ status = "okay"; label = "bmc"; m25p,fast-read; -#include "openbmc-flash-layout.dtsi" + + partitions { + #address-cells = < 1 >; + #size-cells = < 1 >; + compatible = "fixed-partitions"; + u-boot@0 { + reg = < 0 0x60000 >; + label = "u-boot"; + }; + u-boot-env@60000 { + reg = < 0x60000 0x20000 >; + label = "u-boot-env"; + }; + obmc-ubi@80000 { + reg = < 0x80000 0x1F80000 >; + label = "obmc-ubi"; + }; + }; }; flash@1 { status = "okay"; - label = "alt"; + label = "alt-bmc"; m25p,fast-read; + + partitions { + #address-cells = < 1 >; + #size-cells = < 1 >; + compatible = "fixed-partitions"; + u-boot@0 { + reg = < 0 0x60000 >; + label = "alt-u-boot"; + }; + u-boot-env@60000 { + reg = < 0x60000 0x20000 >; + label = "alt-u-boot-env"; + }; + obmc-ubi@80000 { + reg = < 0x80000 0x1F80000 >; + label = "alt-obmc-ubi"; + }; + }; + }; }; -- cgit From 6d00c6f8d2e781e3c821fc9c614f404cc981804d Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 3 Oct 2018 14:35:07 +0200 Subject: ARM: dts: aspeed: Add RTC node The ASPEED ast2400 and ast2500 both contain an on board RTC device. Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g4.dtsi | 6 ++++++ arch/arm/boot/dts/aspeed-g5.dtsi | 6 ++++++ 2 files changed, 12 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index 9549f867aa1e..5d7050d00874 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -209,6 +209,12 @@ clock-names = "PCLK"; }; + rtc: rtc@1e781000 { + compatible = "aspeed,ast2400-rtc"; + reg = <0x1e781000 0x18>; + status = "disabled"; + }; + uart1: serial@1e783000 { compatible = "ns16550a"; reg = <0x1e783000 0x20>; diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index 733cac9eeef4..4345c3153ca7 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -274,6 +274,12 @@ #interrupt-cells = <2>; }; + rtc: rtc@1e781000 { + compatible = "aspeed,ast2500-rtc"; + reg = <0x1e781000 0x18>; + status = "disabled"; + }; + timer: timer@1e782000 { /* This timer is a Faraday FTTMR010 derivative */ compatible = "aspeed,ast2400-timer"; -- cgit From 41eb0df1926aa7e8cbd621e66533d8bc35e82a26 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Mon, 1 Apr 2019 13:56:16 +0200 Subject: ARM: dts: sun8i: tbs-a711: Enable UART2 (for NEO-6M GPS module) TBS A711 tablet contains u-blox NEO-6M module connected to UART2. Enable UART2 to gain access to the module from userspace. Signed-off-by: Ondrej Jirman Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts index 066d95a7cb78..87c04d4b6ba3 100644 --- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts +++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts @@ -98,6 +98,13 @@ }; }; + reg_gps: reg-gps { + compatible = "regulator-fixed"; + regulator-name = "gps"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + reg_vbat: reg-vbat { compatible = "regulator-fixed"; regulator-name = "vbat"; @@ -434,6 +441,20 @@ }; }; +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pb_pins>; + status = "okay"; + + gnss { + compatible = "u-blox,neo-6m"; + + v-bckp-supply = <®_rtc_ldo>; + vcc-supply = <®_gps>; + current-speed = <9600>; + }; +}; + &usb_otg { dr_mode = "otg"; status = "okay"; -- cgit From dccd30ea59922d1eacff925400acd66afcd05cff Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Mon, 8 Apr 2019 09:41:47 +0200 Subject: ARM: dts: sunxi: Improve A33 NAND transfers by using DMA In the current state, A33 NAND controllers use PIO during transfers. Throughput can be increased thanks to the use of DMA (mostly during reads, because of the ECC pipelining feature). Besides the usual addition of DMA DT properties, because the A33 NAND DMA handling is different than for older SoCs, we must also update the compatible which has recently been introduced for this purpose. Signed-off-by: Miquel Raynal Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index c17bd7677ffb..f76aad0c5d4d 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -162,13 +162,15 @@ }; nfc: nand-controller@1c03000 { - compatible = "allwinner,sun4i-a10-nand"; + compatible = "allwinner,sun8i-a23-nand-controller"; reg = <0x01c03000 0x1000>; interrupts = ; clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>; clock-names = "ahb", "mod"; resets = <&ccu RST_BUS_NAND>; reset-names = "ahb"; + dmas = <&dma 5>; + dma-names = "rxtx"; pinctrl-names = "default"; pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>; status = "disabled"; -- cgit From c848f3ba0029414da9147310afa727c50d6005cd Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 3 Apr 2019 22:52:16 +0200 Subject: ARM: dts: sama5d{2,4}: use SPDX-License-Identifier External E-Mail The X11 license text [1] is explicitly for the X Consortium and has a couple of extra clauses. The MIT license text [2] is actually what the current DT files claim. [1] https://spdx.org/licenses/X11.html [2] https://spdx.org/licenses/MIT.html Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre Signed-off-by: Ludovic Desroches --- arch/arm/boot/dts/sama5d2.dtsi | 39 +-------------------------------------- arch/arm/boot/dts/sama5d4.dtsi | 39 +-------------------------------------- 2 files changed, 2 insertions(+), 76 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 9519b9d5abca..2e2c1a7b1d1d 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -1,46 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC * * Copyright (C) 2015 Atmel, * 2015 Ludovic Desroches - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index 6c1e41f94549..6ab27a7b388d 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -1,46 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC * * Copyright (C) 2014 Atmel, * 2014 Nicolas Ferre - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include -- cgit From 7015533ee0e964b061656ccd9ac476cbd2b23b26 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 3 Apr 2019 22:52:17 +0200 Subject: ARM: dts: at91sam9xe: use SPDX-License-Identifier External E-Mail The X11 license text [1] is explicitly for the X Consortium and has a couple of extra clauses. The MIT license text [2] is actually what the current DT files claim. [1] https://spdx.org/licenses/X11.html [2] https://spdx.org/licenses/MIT.html Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre Signed-off-by: Ludovic Desroches --- arch/arm/boot/dts/at91sam9xe.dtsi | 39 +-------------------------------------- 1 file changed, 1 insertion(+), 38 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91sam9xe.dtsi b/arch/arm/boot/dts/at91sam9xe.dtsi index 1304452f0fae..3f9d8caf8b0a 100644 --- a/arch/arm/boot/dts/at91sam9xe.dtsi +++ b/arch/arm/boot/dts/at91sam9xe.dtsi @@ -1,46 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * at91sam9xe.dtsi - Device Tree Include file for AT91SAM9XE family SoC * * Copyright (C) 2015 Atmel, * 2015 Alexandre Belloni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include "at91sam9260.dtsi" -- cgit From 43216d05eda5792cb43651c5c4a5689dd70efbc3 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 3 Apr 2019 22:52:18 +0200 Subject: ARM: dts: atmel boards: use SPDX-License-Identifier External E-Mail The X11 license text [1] is explicitly for the X Consortium and has a couple of extra clauses. The MIT license text [2] is actually what the current DT files claim. [1] https://spdx.org/licenses/X11.html [2] https://spdx.org/licenses/MIT.html Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre Signed-off-by: Ludovic Desroches --- arch/arm/boot/dts/at91-sama5d27_som1.dtsi | 39 +---------------------------- arch/arm/boot/dts/at91-sama5d27_som1_ek.dts | 39 +---------------------------- arch/arm/boot/dts/at91-sama5d2_xplained.dts | 39 +---------------------------- arch/arm/boot/dts/at91-sama5d4_xplained.dts | 39 +---------------------------- arch/arm/boot/dts/at91-sama5d4ek.dts | 39 +---------------------------- arch/arm/boot/dts/at91sam9260ek.dts | 39 +---------------------------- arch/arm/boot/dts/sama5d36ek_cmp.dts | 39 +---------------------------- arch/arm/boot/dts/sama5d3xcm_cmp.dtsi | 39 +---------------------------- arch/arm/boot/dts/sama5d3xmb_cmp.dtsi | 39 +---------------------------- 9 files changed, 9 insertions(+), 342 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi index 33a159c0163f..7788d5db65c2 100644 --- a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi +++ b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi @@ -1,47 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * at91-sama5d27_som1.dtsi - Device Tree file for SAMA5D27 SoM1 board * * Copyright (c) 2017, Microchip Technology Inc. * 2017 Cristian Birsan * 2017 Claudiu Beznea - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include "sama5d2.dtsi" #include "sama5d2-pinfunc.h" diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts index a48180555ef5..89f0c9979b89 100644 --- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * at91-sama5d27_som1_ek.dts - Device Tree file for SAMA5D27-SOM1-EK board * @@ -5,44 +6,6 @@ * 2016 Nicolas Ferre * 2017 Cristian Birsan * 2017 Claudiu Beznea - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; #include "at91-sama5d27_som1.dtsi" diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts index e62c3b6cde4c..808e399fd39a 100644 --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts @@ -1,46 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * at91-sama5d2_xplained.dts - Device Tree file for SAMA5D2 Xplained board * * Copyright (C) 2015 Atmel, * 2015 Nicolas Ferre - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; #include "sama5d2.dtsi" diff --git a/arch/arm/boot/dts/at91-sama5d4_xplained.dts b/arch/arm/boot/dts/at91-sama5d4_xplained.dts index 43aef56ac74a..fdfc37d716e0 100644 --- a/arch/arm/boot/dts/at91-sama5d4_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d4_xplained.dts @@ -1,46 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * at91-sama5d4_xplained.dts - Device Tree file for SAMA5D4 Xplained board * * Copyright (C) 2015 Atmel, * 2015 Josh Wu - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; #include "sama5d4.dtsi" diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts b/arch/arm/boot/dts/at91-sama5d4ek.dts index 12d5af938aa3..0cc1cff13e46 100644 --- a/arch/arm/boot/dts/at91-sama5d4ek.dts +++ b/arch/arm/boot/dts/at91-sama5d4ek.dts @@ -1,46 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * at91-sama5d4ek.dts - Device Tree file for SAMA5D4 Evaluation Kit * * Copyright (C) 2014 Atmel, * 2014 Nicolas Ferre - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; #include "sama5d4.dtsi" diff --git a/arch/arm/boot/dts/at91sam9260ek.dts b/arch/arm/boot/dts/at91sam9260ek.dts index 07d1b571e601..81f808a10931 100644 --- a/arch/arm/boot/dts/at91sam9260ek.dts +++ b/arch/arm/boot/dts/at91sam9260ek.dts @@ -1,46 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for Atmel at91sam9260 Evaluation Kit * * Copyright (C) 2016 Atmel, * 2016 Nicolas Ferre - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; #include "at91sam9260.dtsi" diff --git a/arch/arm/boot/dts/sama5d36ek_cmp.dts b/arch/arm/boot/dts/sama5d36ek_cmp.dts index b632143844e5..66695b9a3e77 100644 --- a/arch/arm/boot/dts/sama5d36ek_cmp.dts +++ b/arch/arm/boot/dts/sama5d36ek_cmp.dts @@ -1,45 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * sama5d36ek_cmp.dts - Device Tree file for SAMA5D36-EK CMP board * * Copyright (C) 2016 Atmel, - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; #include "sama5d36.dtsi" diff --git a/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi b/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi index a02f59021364..9d2563602cbe 100644 --- a/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi +++ b/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi @@ -1,45 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * sama5d3xcm_cmp.dtsi - Device Tree Include file for SAMA5D36 CMP CPU Module * * Copyright (C) 2016 Atmel, - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ / { diff --git a/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi b/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi index 97e171db5970..8a6916a69da4 100644 --- a/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi +++ b/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi @@ -1,45 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * sama5d3xmb_cmp.dts - Device Tree file for SAMA5D3x CMP mother board * * Copyright (C) 2016 Atmel, - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include "sama5d3xcm_cmp.dtsi" -- cgit From a4a11b7934a5350fa825fee35b4bbbbe581a313a Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 3 Apr 2019 22:52:19 +0200 Subject: ARM: dts: at91-vinco: use SPDX-License-Identifier External E-Mail The X11 license text [1] is explicitly for the X Consortium and has a couple of extra clauses. The MIT license text [2] is actually what the current DT files claim. [1] https://spdx.org/licenses/X11.html [2] https://spdx.org/licenses/MIT.html Signed-off-by: Alexandre Belloni Acked-by: Gregory CLEMENT Acked-by: Nicolas Ferre Signed-off-by: Ludovic Desroches --- arch/arm/boot/dts/at91-vinco.dts | 39 +-------------------------------------- 1 file changed, 1 insertion(+), 38 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-vinco.dts b/arch/arm/boot/dts/at91-vinco.dts index 430277291e02..15050fdd479d 100644 --- a/arch/arm/boot/dts/at91-vinco.dts +++ b/arch/arm/boot/dts/at91-vinco.dts @@ -1,47 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for VInCo platform * * Copyright (C) 2014 Atmel, * 2014 Nicolas Ferre * 2015 Gregory CLEMENT - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; #include "sama5d4.dtsi" -- cgit From 3b6150a6eb61f03df60ca6b835e7a5f671372a1a Mon Sep 17 00:00:00 2001 From: Christina Quast Date: Mon, 8 Apr 2019 10:01:51 -0700 Subject: ARM: dts: am335x: bone-common: Replaced register offsets with defines The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-bone-common.dtsi | 116 +++++++++++++++--------------- 1 file changed, 58 insertions(+), 58 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index 456eef57ef89..42cfc3b37c32 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -71,118 +71,118 @@ user_leds_s0: user_leds_s0 { pinctrl-single,pins = < - AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ - AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */ - AM33XX_IOPAD(0x85c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */ - AM33XX_IOPAD(0x860, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a6.gpio1_22 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a7.gpio1_23 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a8.gpio1_24 */ >; }; i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_sda.i2c0_sda */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_scl.i2c0_scl */ >; }; i2c2_pins: pinmux_i2c2_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.i2c2_sda */ - AM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.i2c2_scl */ + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_ctsn.i2c2_sda */ + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_rtsn.i2c2_scl */ >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; clkout2_pin: pinmux_clkout2_pin { pinctrl-single,pins = < - AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ - AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */ - AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */ - AM33XX_IOPAD(0x918, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */ - AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */ - AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */ - AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */ - AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */ - AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */ - AM33XX_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */ - AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */ - AM33XX_IOPAD(0x938, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */ - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */ - AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE0) >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ - AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spio0_cs1.gpio0_6 */ - AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ - AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ - AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ - AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ - AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ - AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spio0_cs1.gpio0_6 */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) >; }; emmc_pins: pinmux_emmc_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ - AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ - AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ - AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ >; }; }; -- cgit From 399c6b924a834b3c1f2db48614682ed1b50d512d Mon Sep 17 00:00:00 2001 From: Christina Quast Date: Mon, 8 Apr 2019 10:01:52 -0700 Subject: ARM: dts: am335x: boneblack-common: Replaced register offsets with defines The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-boneblack-common.dtsi | 54 +++++++++++++------------- 1 file changed, 27 insertions(+), 27 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-boneblack-common.dtsi b/arch/arm/boot/dts/am335x-boneblack-common.dtsi index e543c2bee8c2..283e288b6e42 100644 --- a/arch/arm/boot/dts/am335x-boneblack-common.dtsi +++ b/arch/arm/boot/dts/am335x-boneblack-common.dtsi @@ -30,43 +30,43 @@ &am33xx_pinmux { nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x9b0, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr0 */ - AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ - AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ - AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ - AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ - AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ - AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ - AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ - AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ - AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ - AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ - AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ - AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ - AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ - AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ - AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ - AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ - AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_vsync.lcd_vsync */ - AM33XX_IOPAD(0x8e4, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_hsync.lcd_hsync */ - AM33XX_IOPAD(0x8e8, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_pclk.lcd_pclk */ - AM33XX_IOPAD(0x8ec, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x9b0, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr0 */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) >; }; mcasp0_pins: mcasp0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLUP | MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */ - AM33XX_IOPAD(0x99c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ - AM33XX_IOPAD(0x994, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */ - AM33XX_IOPAD(0x990, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */ - AM33XX_IOPAD(0x86c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.GPIO1_27 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */ >; }; }; -- cgit From 682668df1f64efedccabdca0eee3028d9f04b29c Mon Sep 17 00:00:00 2001 From: Christina Quast Date: Mon, 8 Apr 2019 10:01:52 -0700 Subject: ARM: dts: am335x: boneblack-wireless: Replaced register offsets with defines The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-boneblack-wireless.dts | 28 ++++++++++++------------- 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-boneblack-wireless.dts b/arch/arm/boot/dts/am335x-boneblack-wireless.dts index 83f49f616b19..5b275c96fccf 100644 --- a/arch/arm/boot/dts/am335x-boneblack-wireless.dts +++ b/arch/arm/boot/dts/am335x-boneblack-wireless.dts @@ -32,35 +32,35 @@ &am33xx_pinmux { bt_pins: pinmux_bt_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gmii1_txd0.gpio0_28 - BT_EN */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gmii1_txd0.gpio0_28 - BT_EN */ >; }; mmc3_pins: pinmux_mmc3_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE6 ) /* (L15) gmii1_rxd1.mmc2_clk */ - AM33XX_IOPAD(0x914, PIN_INPUT_PULLUP | MUX_MODE6 ) /* (J16) gmii1_txen.mmc2_cmd */ - AM33XX_IOPAD(0x918, PIN_INPUT_PULLUP | MUX_MODE5 ) /* (J17) gmii1_rxdv.mmc2_dat0 */ - AM33XX_IOPAD(0x91c, PIN_INPUT_PULLUP | MUX_MODE5 ) /* (J18) gmii1_txd3.mmc2_dat1 */ - AM33XX_IOPAD(0x920, PIN_INPUT_PULLUP | MUX_MODE5 ) /* (K15) gmii1_txd2.mmc2_dat2 */ - AM33XX_IOPAD(0x908, PIN_INPUT_PULLUP | MUX_MODE5 ) /* (H16) gmii1_col.mmc2_dat3 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE6 ) /* (L15) gmii1_rxd1.mmc2_clk */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLUP, MUX_MODE6 ) /* (J16) gmii1_txen.mmc2_cmd */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (J17) gmii1_rxdv.mmc2_dat0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (J18) gmii1_txd3.mmc2_dat1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (K15) gmii1_txd2.mmc2_dat2 */ + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (H16) gmii1_col.mmc2_dat3 */ >; }; uart3_pins: pinmux_uart3_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE1) /* gmii1_rxd3.uart3_rxd */ - AM33XX_IOPAD(0x938, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gmii1_rxd2.uart3_txd */ - AM33XX_IOPAD(0x948, PIN_INPUT | MUX_MODE3) /* mdio_data.uart3_ctsn */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* mdio_clk.uart3_rtsn */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gmii1_rxd3.uart3_rxd */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* gmii1_rxd2.uart3_txd */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT, MUX_MODE3) /* mdio_data.uart3_ctsn */ + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* mdio_clk.uart3_rtsn */ >; }; wl18xx_pins: pinmux_wl18xx_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gmii1_txclk.gpio3_9 WL_EN */ - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_refclk.gpio0_29 WL_IRQ */ - AM33XX_IOPAD(0x930, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gmii1_rxclk.gpio3_10 LS_BUF_EN */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gmii1_txclk.gpio3_9 WL_EN */ + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_refclk.gpio0_29 WL_IRQ */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gmii1_rxclk.gpio3_10 LS_BUF_EN */ >; }; }; -- cgit From 05165a63d6057669269b9c7856e874577382e238 Mon Sep 17 00:00:00 2001 From: Christina Quast Date: Mon, 8 Apr 2019 10:01:53 -0700 Subject: ARM: dts: am335x: pocketbeagle: Replaced register offsets with defines The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-pocketbeagle.dts | 56 +++++++++++++++---------------- 1 file changed, 28 insertions(+), 28 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-pocketbeagle.dts b/arch/arm/boot/dts/am335x-pocketbeagle.dts index 62fe5cab9fae..ff4f919d22f6 100644 --- a/arch/arm/boot/dts/am335x-pocketbeagle.dts +++ b/arch/arm/boot/dts/am335x-pocketbeagle.dts @@ -62,74 +62,74 @@ &am33xx_pinmux { i2c2_pins: pinmux-i2c2-pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE3) /* (D17) uart1_rtsn.I2C2_SCL */ - AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE3) /* (D18) uart1_ctsn.I2C2_SDA */ + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D17) uart1_rtsn.I2C2_SCL */ + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D18) uart1_ctsn.I2C2_SDA */ >; }; ehrpwm0_pins: pinmux-ehrpwm0-pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x990, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* (A13) mcasp0_aclkx.ehrpwm0A */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* (A13) mcasp0_aclkx.ehrpwm0A */ >; }; ehrpwm1_pins: pinmux-ehrpwm1-pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* (U14) gpmc_a2.ehrpwm1A */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* (U14) gpmc_a2.ehrpwm1A */ >; }; mmc0_pins: pinmux-mmc0-pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */ - AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* (G16) mmc0_dat0.mmc0_dat0 */ - AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* (G15) mmc0_dat1.mmc0_dat1 */ - AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* (F18) mmc0_dat2.mmc0_dat2 */ - AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* (F17) mmc0_dat3.mmc0_dat3 */ - AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* (G18) mmc0_cmd.mmc0_cmd */ - AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* (G17) mmc0_clk.mmc0_clk */ - AM33XX_IOPAD(0x9a0, PIN_INPUT | MUX_MODE4) /* (B12) mcasp0_aclkr.mmc0_sdwp */ + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT, MUX_MODE4) /* (B12) mcasp0_aclkr.mmc0_sdwp */ >; }; spi0_pins: pinmux-spi0-pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* (A17) spi0_sclk.spi0_sclk */ - AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */ - AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */ - AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */ + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) >; }; spi1_pins: pinmux-spi1-pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x964, PIN_INPUT_PULLUP | MUX_MODE4) /* (C18) eCAP0_in_PWM0_out.spi1_sclk */ - AM33XX_IOPAD(0x968, PIN_INPUT_PULLUP | MUX_MODE4) /* (E18) uart0_ctsn.spi1_d0 */ - AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE4) /* (E17) uart0_rtsn.spi1_d1 */ - AM33XX_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE4) /* (A15) xdma_event_intr0.spi1_cs1 */ + AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_INPUT_PULLUP, MUX_MODE4) /* (C18) eCAP0_in_PWM0_out.spi1_sclk */ + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* (E18) uart0_ctsn.spi1_d0 */ + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* (E17) uart0_rtsn.spi1_d1 */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_INPUT_PULLUP, MUX_MODE4) /* (A15) xdma_event_intr0.spi1_cs1 */ >; }; usr_leds_pins: pinmux-usr-leds-pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7) /* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */ - AM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7) /* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */ - AM33XX_IOPAD(0x85c, PIN_OUTPUT | MUX_MODE7) /* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */ - AM33XX_IOPAD(0x860, PIN_OUTPUT | MUX_MODE7) /* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) /* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7) /* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7) /* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */ >; }; uart0_pins: pinmux-uart0-pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* (E15) uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* (E16) uart0_txd.uart0_txd */ + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; uart4_pins: pinmux-uart4-pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6) /* (T17) gpmc_wait0.uart4_rxd */ - AM33XX_IOPAD(0x874, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* (U17) gpmc_wpn.uart4_txd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) /* (T17) gpmc_wait0.uart4_rxd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* (U17) gpmc_wpn.uart4_txd */ >; }; }; -- cgit From d6212ce3fc93ef85bce84edb216a32090cabd80c Mon Sep 17 00:00:00 2001 From: Ziping Chen Date: Wed, 27 Mar 2019 03:33:38 +0100 Subject: ARM: dts: sunxi: Add R_LRADC support for A83T Allwinner A83T SoC has a low res adc like the one in Allwinner A10 SoC. Now the driver has been modified to support it. Add support for it. Signed-off-by: Ziping Chen Signed-off-by: Ondrej Jirman Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index f739b88efb53..60859c19270f 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -1075,6 +1075,13 @@ status = "disabled"; }; + r_lradc: lradc@1f03c00 { + compatible = "allwinner,sun8i-a83t-r-lradc"; + reg = <0x01f03c00 0x100>; + interrupts = ; + status = "disabled"; + }; + r_pio: pinctrl@1f02c00 { compatible = "allwinner,sun8i-a83t-r-pinctrl"; reg = <0x01f02c00 0x400>; -- cgit From 5824c8ebb94d362ff0a278ff420bc22f7e075d32 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Wed, 27 Mar 2019 03:33:39 +0100 Subject: ARM: dts: sun8i: tbs-a711: Add support for volume keys input TBS A711 tablet has volume up/down keys connected to r_lradc. Add support for these keys. Signed-off-by: Ondrej Jirman Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts index 87c04d4b6ba3..66d078053d5f 100644 --- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts +++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts @@ -46,6 +46,7 @@ #include #include +#include / { model = "TBS A711 Tablet"; @@ -219,6 +220,25 @@ status = "okay"; }; +&r_lradc { + vref-supply = <®_aldo2>; + status = "okay"; + + button@210 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <210000>; + }; + + button@410 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <410000>; + }; +}; + &r_rsb { status = "okay"; -- cgit From 013df97be45f023f5902c1102606c4034c668ba5 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 9 Apr 2019 00:57:43 +0800 Subject: ARM: dts: sun8i: a83t: Add I2C2 pinmux setting for PE pins I2C2 is available on the PE pingroup, on the same pins as the camera sensor interface (CSI) controller's camera control interface pins. This provides an option to use I2C2 instead of that control interface to configure camera sensors. Add a pinctrl node for it. The property /omit-if-no-ref/ is added to keep the device tree blob size down if it is unused. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 60859c19270f..b105a85467b3 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -709,6 +709,12 @@ function = "i2c1"; }; + /omit-if-no-ref/ + i2c2_pe_pins: i2c2-pe-pins { + pins = "PE14", "PE15"; + function = "i2c2"; + }; + i2c2_ph_pins: i2c2-ph-pins { pins = "PH4", "PH5"; function = "i2c2"; -- cgit From b5acec09e259d9972b0e82e3a97ca019f0df29bb Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Mon, 25 Mar 2019 15:15:25 +0530 Subject: ARM: dts: dra7: Add properties to enable PCIe x2 lane mode ti,syscon-lane-sel and ti,syscon-lane-conf properties specific to enable PCIe x2 lane mode are added here. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 2bc9add8b7a5..d87e932f45bd 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -193,6 +193,7 @@ ti,hwmods = "pcie1"; phys = <&pcie1_phy>; phy-names = "pcie-phy0"; + ti,syscon-lane-sel = <&scm_conf_pcie 0x18>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie1_intc 1>, <0 0 0 2 &pcie1_intc 2>, @@ -218,6 +219,7 @@ phys = <&pcie1_phy>; phy-names = "pcie-phy0"; ti,syscon-unaligned-access = <&scm_conf1 0x14 1>; + ti,syscon-lane-sel = <&scm_conf_pcie 0x18>; status = "disabled"; }; }; -- cgit From d921e53a51076c4494c6435ab142d36b21687755 Mon Sep 17 00:00:00 2001 From: Kabir Sahane Date: Fri, 29 Mar 2019 12:53:32 -0500 Subject: ARM: dts: am43xx-epos-evm: Keep DCDC5 and DCDC6 always on These regulator outputs are needed even in deep sleep modes to prevent low-voltage detection events. Make these always ON to avoid this. Signed-off-by: Kabir Sahane Signed-off-by: Andrew F. Davis Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am43x-epos-evm.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index 9dfd80e3b76e..7db5cf3facde 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -634,12 +634,16 @@ regulator-name = "v1_0bat"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; }; dcdc6: regulator-dcdc6 { regulator-name = "v1_8bat"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; }; ldo1: regulator-ldo1 { -- cgit From 177425ef586a932b968d4adf6a258da61b0ae727 Mon Sep 17 00:00:00 2001 From: Mike Erdahl Date: Fri, 29 Mar 2019 12:53:33 -0500 Subject: ARM: dts: am43xx-epos-evm: Keep DCDC3 regulator on in suspend to memory When going to suspend to ram mode (or rtc-only mode), the DDR regulator must be told to stay on, else this rail will go down when the PMIC_EN signal is deasserted. Signed-off-by: Mike Erdahl Signed-off-by: Andrew F. Davis Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am43x-epos-evm.dts | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index 7db5cf3facde..606b848d809f 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -620,6 +620,12 @@ regulator-name = "vdcdc3"; regulator-boot-on; regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + regulator-state-disk { + regulator-off-in-suspend; + }; }; dcdc4: regulator-dcdc4 { -- cgit From e74cf9186be870e4a78ddfd59b0c4b57ab549c0e Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Fri, 29 Mar 2019 12:53:34 -0500 Subject: ARM: dts: am43xx-epos-evm: Add matrix keypad as wakeup source Mark matrix-keypad as a wakeup source. Signed-off-by: Andrew F. Davis Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am43x-epos-evm.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index 606b848d809f..9b8b132b04e1 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -80,6 +80,7 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&matrix_keypad_default>; pinctrl-1 = <&matrix_keypad_sleep>; + wakeup-source; row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */ &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */ -- cgit From b453c417609fa035c76e6a9c0c3dcf2cb42c1112 Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Fri, 29 Mar 2019 13:13:13 -0500 Subject: ARM: dts: omap2420-n810: Use new CODEC reset pin name The correct DT property for specifying a GPIO used for reset is "reset-gpios", the driver now accepts this name, use it here. Signed-off-by: Andrew F. Davis Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap2420-n810.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap2420-n810.dts b/arch/arm/boot/dts/omap2420-n810.dts index 96b9913ecc1f..09c1dbc0bb69 100644 --- a/arch/arm/boot/dts/omap2420-n810.dts +++ b/arch/arm/boot/dts/omap2420-n810.dts @@ -48,7 +48,7 @@ pinctrl-names = "default"; pinctrl-0 = <&aic33_pins>; - gpio-reset = <&gpio4 22 GPIO_ACTIVE_LOW>; /* gpio118 */ + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; /* gpio118 */ ai3x-gpio-func = < 10 /* AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK */ -- cgit From ed01ffd9dd1c7e585f73b08877192a2cf754d006 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Tue, 9 Apr 2019 09:00:53 -0700 Subject: ARM: dts: Add common mcpdm dts file for omap4 The mcpdm module found on omap4 and 5 needs pdmclk clock from the pmic that may or may not be wired. Without this clock we cannot read the registers for mcpdm at all. For the external mcpdm clock to work, it needs to be muxed at the module level for ti-sysc driver probe to mux it early enough for probe. Let's set up a common file for it to make things a bit easier to make l4 abe interconnect to probe with ti-sysc driver. Note that this is not needed for omap5 as we can just update mcpdm muxing in omap5-board-common.dtsi in later patches. Cc: devicetree@vger.kernel.org Cc: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-duovero.dtsi | 21 +---------------- arch/arm/boot/dts/omap4-mcpdm.dtsi | 38 +++++++++++++++++++++++++++++++ arch/arm/boot/dts/omap4-panda-common.dtsi | 21 +---------------- arch/arm/boot/dts/omap4-sdp.dts | 21 +---------------- arch/arm/boot/dts/omap4-var-som-om44.dtsi | 21 +---------------- 5 files changed, 42 insertions(+), 80 deletions(-) create mode 100644 arch/arm/boot/dts/omap4-mcpdm.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap4-duovero.dtsi b/arch/arm/boot/dts/omap4-duovero.dtsi index 5e8169153414..a1dacb8a6987 100644 --- a/arch/arm/boot/dts/omap4-duovero.dtsi +++ b/arch/arm/boot/dts/omap4-duovero.dtsi @@ -7,6 +7,7 @@ */ #include "omap443x.dtsi" +#include "omap4-mcpdm.dtsi" / { model = "Gumstix Duovero"; @@ -82,16 +83,6 @@ >; }; - mcpdm_pins: pinmux_mcpdm_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x106, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_ul_data.abe_pdm_ul_data */ - OMAP4_IOPAD(0x108, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_dl_data.abe_pdm_dl_data */ - OMAP4_IOPAD(0x10a, PIN_INPUT_PULLUP | MUX_MODE0) /* abe_pdm_frame.abe_pdm_frame */ - OMAP4_IOPAD(0x10c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_lb_clk.abe_pdm_lb_clk */ - OMAP4_IOPAD(0x10e, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */ - >; - }; - mcbsp1_pins: pinmux_mcbsp1_pins { pinctrl-single,pins = < OMAP4_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */ @@ -210,16 +201,6 @@ status = "okay"; }; -&mcpdm { - pinctrl-names = "default"; - pinctrl-0 = <&mcpdm_pins>; - - clocks = <&twl6040>; - clock-names = "pdmclk"; - - status = "okay"; -}; - &mmc1 { pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; diff --git a/arch/arm/boot/dts/omap4-mcpdm.dtsi b/arch/arm/boot/dts/omap4-mcpdm.dtsi new file mode 100644 index 000000000000..9d40e433c4b5 --- /dev/null +++ b/arch/arm/boot/dts/omap4-mcpdm.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common omap4 mcpdm configuration + * + * Only include this file if your board has pdmclk wired from the + * pmic to ABE as mcpdm uses an external clock for the module. + */ + +&omap4_pmx_core { + mcpdm_pins: pinmux_mcpdm_pins { + pinctrl-single,pins = < + /* 0x4a100106 abe_pdm_ul_data.abe_pdm_ul_data ag25 */ + OMAP4_IOPAD(0x106, PIN_INPUT_PULLDOWN | MUX_MODE0) + + /* 0x4a100108 abe_pdm_dl_data.abe_pdm_dl_data af25 */ + OMAP4_IOPAD(0x108, PIN_INPUT_PULLDOWN | MUX_MODE0) + + /* 0x4a10010a abe_pdm_frame.abe_pdm_frame ae25 */ + OMAP4_IOPAD(0x10a, PIN_INPUT_PULLUP | MUX_MODE0) + + /* 0x4a10010c abe_pdm_lb_clk.abe_pdm_lb_clk af26 */ + OMAP4_IOPAD(0x10c, PIN_INPUT_PULLDOWN | MUX_MODE0) + + /* 0x4a10010e abe_clks.abe_clks ah26 */ + OMAP4_IOPAD(0x10e, PIN_INPUT_PULLDOWN | MUX_MODE0) + >; + }; +}; + +&mcpdm { + pinctrl-names = "default"; + pinctrl-0 = <&mcpdm_pins>; + + clocks = <&twl6040>; + clock-names = "pdmclk"; + + status = "okay"; +}; diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index 926f018823a4..68e1894df713 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -7,6 +7,7 @@ */ #include #include "elpida_ecb240abacn.dtsi" +#include "omap4-mcpdm.dtsi" / { memory@80000000 { @@ -226,16 +227,6 @@ >; }; - mcpdm_pins: pinmux_mcpdm_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x106, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_ul_data.abe_pdm_ul_data */ - OMAP4_IOPAD(0x108, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_dl_data.abe_pdm_dl_data */ - OMAP4_IOPAD(0x10a, PIN_INPUT_PULLUP | MUX_MODE0) /* abe_pdm_frame.abe_pdm_frame */ - OMAP4_IOPAD(0x10c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_lb_clk.abe_pdm_lb_clk */ - OMAP4_IOPAD(0x10e, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */ - >; - }; - mcbsp1_pins: pinmux_mcbsp1_pins { pinctrl-single,pins = < OMAP4_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */ @@ -509,16 +500,6 @@ status = "okay"; }; -&mcpdm { - pinctrl-names = "default"; - pinctrl-0 = <&mcpdm_pins>; - - clocks = <&twl6040>; - clock-names = "pdmclk"; - - status = "okay"; -}; - &twl_usb_comparator { usb-supply = <&vusb>; }; diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index c88817bdcc56..fb51a4bffd35 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -9,6 +9,7 @@ #include "omap443x.dtsi" #include "elpida_ecb240abacn.dtsi" +#include "omap4-mcpdm.dtsi" / { model = "TI OMAP4 SDP board"; @@ -246,16 +247,6 @@ >; }; - mcpdm_pins: pinmux_mcpdm_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x106, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_ul_data.abe_pdm_ul_data */ - OMAP4_IOPAD(0x108, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_dl_data.abe_pdm_dl_data */ - OMAP4_IOPAD(0x10a, PIN_INPUT_PULLUP | MUX_MODE0) /* abe_pdm_frame.abe_pdm_frame */ - OMAP4_IOPAD(0x10c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_lb_clk.abe_pdm_lb_clk */ - OMAP4_IOPAD(0x10e, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */ - >; - }; - dmic_pins: pinmux_dmic_pins { pinctrl-single,pins = < OMAP4_IOPAD(0x110, PIN_OUTPUT | MUX_MODE0) /* abe_dmic_clk1.abe_dmic_clk1 */ @@ -649,16 +640,6 @@ status = "okay"; }; -&mcpdm { - pinctrl-names = "default"; - pinctrl-0 = <&mcpdm_pins>; - - clocks = <&twl6040>; - clock-names = "pdmclk"; - - status = "okay"; -}; - &twl_usb_comparator { usb-supply = <&vusb>; }; diff --git a/arch/arm/boot/dts/omap4-var-som-om44.dtsi b/arch/arm/boot/dts/omap4-var-som-om44.dtsi index 10fce28ceb5b..9562d372077c 100644 --- a/arch/arm/boot/dts/omap4-var-som-om44.dtsi +++ b/arch/arm/boot/dts/omap4-var-som-om44.dtsi @@ -7,6 +7,7 @@ * published by the Free Software Foundation. */ #include "omap4460.dtsi" +#include "omap4-mcpdm.dtsi" / { model = "Variscite VAR-SOM-OM44"; @@ -74,16 +75,6 @@ >; }; - mcpdm_pins: pinmux_mcpdm_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x106, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_ul_data.abe_pdm_ul_data */ - OMAP4_IOPAD(0x108, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_dl_data.abe_pdm_dl_data */ - OMAP4_IOPAD(0x10a, PIN_INPUT_PULLUP | MUX_MODE0) /* abe_pdm_frame.abe_pdm_frame */ - OMAP4_IOPAD(0x10c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_lb_clk.abe_pdm_lb_clk */ - OMAP4_IOPAD(0x10e, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */ - >; - }; - tsc2004_pins: pinmux_tsc2004_pins { pinctrl-single,pins = < OMAP4_IOPAD(0x090, PIN_INPUT | MUX_MODE3) /* gpmc_ncs4.gpio_101 (irq) */ @@ -251,16 +242,6 @@ status = "disabled"; }; -&mcpdm { - pinctrl-names = "default"; - pinctrl-0 = <&mcpdm_pins>; - - clocks = <&twl6040>; - clock-names = "pdmclk"; - - status = "okay"; -}; - &gpmc { status = "disabled"; }; -- cgit From 5b5975312903a90220dc980a366a259faedc6808 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Tue, 9 Apr 2019 09:00:53 -0700 Subject: ARM: dts: Add l4 abe interconnect hierarchy and ti-sysc data for omap4 We can now add l4 abe interconnect hierarchy and ti-sysc data with ti-sysc driver supporting external optional clocks needed by mcpdm. This data is generated based on platform data from a booted system and the interconnect acces protection registers for ranges. To avoid regressions, we initially validate the device tree provided data against the existing platform data on boot. Note that mcpdm we now need to enable at module level only for devices that have the external pdmclk wired from the PMIC as the clock is needed for the module to be accessible. Cc: devicetree@vger.kernel.org Cc: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-l4-abe.dtsi | 501 ++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/omap4-mcpdm.dtsi | 12 +- arch/arm/boot/dts/omap4.dtsi | 192 +------------- 3 files changed, 514 insertions(+), 191 deletions(-) create mode 100644 arch/arm/boot/dts/omap4-l4-abe.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap4-l4-abe.dtsi b/arch/arm/boot/dts/omap4-l4-abe.dtsi new file mode 100644 index 000000000000..67072df39bc7 --- /dev/null +++ b/arch/arm/boot/dts/omap4-l4-abe.dtsi @@ -0,0 +1,501 @@ +&l4_abe { /* 0x40100000 */ + compatible = "ti,omap4-l4-abe", "simple-bus"; + reg = <0x40100000 0x400>, + <0x40100400 0x400>; + reg-names = "la", "ap"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */ + <0x49000000 0x49000000 0x100000>; + segment@0 { /* 0x40100000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = + /* CPU to L4 ABE mapping */ + <0x00000000 0x00000000 0x000400>, /* ap 0 */ + <0x00000400 0x00000400 0x000400>, /* ap 1 */ + <0x00022000 0x00022000 0x001000>, /* ap 2 */ + <0x00023000 0x00023000 0x001000>, /* ap 3 */ + <0x00024000 0x00024000 0x001000>, /* ap 4 */ + <0x00025000 0x00025000 0x001000>, /* ap 5 */ + <0x00026000 0x00026000 0x001000>, /* ap 6 */ + <0x00027000 0x00027000 0x001000>, /* ap 7 */ + <0x00028000 0x00028000 0x001000>, /* ap 8 */ + <0x00029000 0x00029000 0x001000>, /* ap 9 */ + <0x0002a000 0x0002a000 0x001000>, /* ap 10 */ + <0x0002b000 0x0002b000 0x001000>, /* ap 11 */ + <0x0002e000 0x0002e000 0x001000>, /* ap 12 */ + <0x0002f000 0x0002f000 0x001000>, /* ap 13 */ + <0x00030000 0x00030000 0x001000>, /* ap 14 */ + <0x00031000 0x00031000 0x001000>, /* ap 15 */ + <0x00032000 0x00032000 0x001000>, /* ap 16 */ + <0x00033000 0x00033000 0x001000>, /* ap 17 */ + <0x00038000 0x00038000 0x001000>, /* ap 18 */ + <0x00039000 0x00039000 0x001000>, /* ap 19 */ + <0x0003a000 0x0003a000 0x001000>, /* ap 20 */ + <0x0003b000 0x0003b000 0x001000>, /* ap 21 */ + <0x0003c000 0x0003c000 0x001000>, /* ap 22 */ + <0x0003d000 0x0003d000 0x001000>, /* ap 23 */ + <0x0003e000 0x0003e000 0x001000>, /* ap 24 */ + <0x0003f000 0x0003f000 0x001000>, /* ap 25 */ + <0x00080000 0x00080000 0x010000>, /* ap 26 */ + <0x00080000 0x00080000 0x001000>, /* ap 27 */ + <0x000a0000 0x000a0000 0x010000>, /* ap 28 */ + <0x000a0000 0x000a0000 0x001000>, /* ap 29 */ + <0x000c0000 0x000c0000 0x010000>, /* ap 30 */ + <0x000c0000 0x000c0000 0x001000>, /* ap 31 */ + <0x000f1000 0x000f1000 0x001000>, /* ap 32 */ + <0x000f2000 0x000f2000 0x001000>, /* ap 33 */ + + /* L3 to L4 ABE mapping */ + <0x49000000 0x49000000 0x000400>, /* ap 0 */ + <0x49000400 0x49000400 0x000400>, /* ap 1 */ + <0x49022000 0x49022000 0x001000>, /* ap 2 */ + <0x49023000 0x49023000 0x001000>, /* ap 3 */ + <0x49024000 0x49024000 0x001000>, /* ap 4 */ + <0x49025000 0x49025000 0x001000>, /* ap 5 */ + <0x49026000 0x49026000 0x001000>, /* ap 6 */ + <0x49027000 0x49027000 0x001000>, /* ap 7 */ + <0x49028000 0x49028000 0x001000>, /* ap 8 */ + <0x49029000 0x49029000 0x001000>, /* ap 9 */ + <0x4902a000 0x4902a000 0x001000>, /* ap 10 */ + <0x4902b000 0x4902b000 0x001000>, /* ap 11 */ + <0x4902e000 0x4902e000 0x001000>, /* ap 12 */ + <0x4902f000 0x4902f000 0x001000>, /* ap 13 */ + <0x49030000 0x49030000 0x001000>, /* ap 14 */ + <0x49031000 0x49031000 0x001000>, /* ap 15 */ + <0x49032000 0x49032000 0x001000>, /* ap 16 */ + <0x49033000 0x49033000 0x001000>, /* ap 17 */ + <0x49038000 0x49038000 0x001000>, /* ap 18 */ + <0x49039000 0x49039000 0x001000>, /* ap 19 */ + <0x4903a000 0x4903a000 0x001000>, /* ap 20 */ + <0x4903b000 0x4903b000 0x001000>, /* ap 21 */ + <0x4903c000 0x4903c000 0x001000>, /* ap 22 */ + <0x4903d000 0x4903d000 0x001000>, /* ap 23 */ + <0x4903e000 0x4903e000 0x001000>, /* ap 24 */ + <0x4903f000 0x4903f000 0x001000>, /* ap 25 */ + <0x49080000 0x49080000 0x010000>, /* ap 26 */ + <0x49080000 0x49080000 0x001000>, /* ap 27 */ + <0x490a0000 0x490a0000 0x010000>, /* ap 28 */ + <0x490a0000 0x490a0000 0x001000>, /* ap 29 */ + <0x490c0000 0x490c0000 0x010000>, /* ap 30 */ + <0x490c0000 0x490c0000 0x001000>, /* ap 31 */ + <0x490f1000 0x490f1000 0x001000>, /* ap 32 */ + <0x490f2000 0x490f2000 0x001000>; /* ap 33 */ + + target-module@22000 { /* 0x40122000, ap 2 02.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "mcbsp1"; + reg = <0x2208c 0x4>; + reg-names = "sysc"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET)>; + ti,sysc-sidle = , + , + ; + /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP4_MCBSP1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x22000 0x1000>, + <0x49022000 0x49022000 0x1000>; + + mcbsp1: mcbsp@0 { + compatible = "ti,omap4-mcbsp"; + reg = <0x0 0xff>, /* MPU private access */ + <0x49022000 0xff>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = ; + interrupt-names = "common"; + ti,buffer-size = <128>; + dmas = <&sdma 33>, + <&sdma 34>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + }; + + target-module@24000 { /* 0x40124000, ap 4 04.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "mcbsp2"; + reg = <0x2408c 0x4>; + reg-names = "sysc"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET)>; + ti,sysc-sidle = , + , + ; + /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP4_MCBSP2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x24000 0x1000>, + <0x49024000 0x49024000 0x1000>; + + mcbsp2: mcbsp@0 { + compatible = "ti,omap4-mcbsp"; + reg = <0x0 0xff>, /* MPU private access */ + <0x49024000 0xff>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = ; + interrupt-names = "common"; + ti,buffer-size = <128>; + dmas = <&sdma 17>, + <&sdma 18>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + }; + + target-module@26000 { /* 0x40126000, ap 6 06.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "mcbsp3"; + reg = <0x2608c 0x4>; + reg-names = "sysc"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET)>; + ti,sysc-sidle = , + , + ; + /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP4_MCBSP3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x26000 0x1000>, + <0x49026000 0x49026000 0x1000>; + + mcbsp3: mcbsp@0 { + compatible = "ti,omap4-mcbsp"; + reg = <0x0 0xff>, /* MPU private access */ + <0x49026000 0xff>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = ; + interrupt-names = "common"; + ti,buffer-size = <128>; + dmas = <&sdma 19>, + <&sdma 20>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + }; + + target-module@28000 { /* 0x40128000, ap 8 08.0 */ + compatible = "ti,sysc-mcasp", "ti,sysc"; + ti,hwmods = "mcasp"; + reg = <0x28000 0x4>, + <0x28004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x28000 0x1000>, + <0x49028000 0x49028000 0x1000>; + + /* + * Child device unsupported by davinci-mcasp. At least + * RX path is disabled for omap4, and only DIT mode + * works with no I2S. See also old Android kernel + * omap-mcasp driver for more information. + */ + }; + + target-module@2a000 { /* 0x4012a000, ap 10 0a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2a000 0x1000>, + <0x4902a000 0x4902a000 0x1000>; + }; + + target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "dmic"; + reg = <0x2e000 0x4>, + <0x2e010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP4_DMIC_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2e000 0x1000>, + <0x4902e000 0x4902e000 0x1000>; + + dmic: dmic@0 { + compatible = "ti,omap4-dmic"; + reg = <0x0 0x7f>, /* MPU private access */ + <0x4902e000 0x7f>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = ; + dmas = <&sdma 67>; + dma-names = "up_link"; + status = "disabled"; + }; + }; + + target-module@30000 { /* 0x40130000, ap 14 0e.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "wd_timer3"; + reg = <0x30000 0x4>, + <0x30010 0x4>, + <0x30014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP4_WD_TIMER3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x30000 0x1000>, + <0x49030000 0x49030000 0x1000>; + + wdt3: wdt@0 { + compatible = "ti,omap4-wdt", "ti,omap3-wdt"; + reg = <0x0 0x80>; + interrupts = ; + }; + }; + + mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mcpdm"; + reg = <0x32000 0x4>, + <0x32010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP4_MCPDM_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x32000 0x1000>, + <0x49032000 0x49032000 0x1000>; + + /* Must be only enabled for boards with pdmclk wired */ + status = "disabled"; + + mcpdm: mcpdm@0 { + compatible = "ti,omap4-mcpdm"; + reg = <0x0 0x7f>, /* MPU private access */ + <0x49032000 0x7f>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = ; + dmas = <&sdma 65>, + <&sdma 66>; + dma-names = "up_link", "dn_link"; + }; + }; + + target-module@38000 { /* 0x40138000, ap 18 12.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer5"; + reg = <0x38000 0x4>, + <0x38010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x38000 0x1000>, + <0x49038000 0x49038000 0x1000>; + + timer5: timer@0 { + compatible = "ti,omap4430-timer"; + reg = <0x00000000 0x80>, + <0x49038000 0x80>; + clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + ti,timer-dsp; + }; + }; + + target-module@3a000 { /* 0x4013a000, ap 20 14.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer6"; + reg = <0x3a000 0x4>, + <0x3a010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3a000 0x1000>, + <0x4903a000 0x4903a000 0x1000>; + + timer6: timer@0 { + compatible = "ti,omap4430-timer"; + reg = <0x00000000 0x80>, + <0x4903a000 0x80>; + clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + ti,timer-dsp; + }; + }; + + target-module@3c000 { /* 0x4013c000, ap 22 16.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer7"; + reg = <0x3c000 0x4>, + <0x3c010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3c000 0x1000>, + <0x4903c000 0x4903c000 0x1000>; + + timer7: timer@0 { + compatible = "ti,omap4430-timer"; + reg = <0x00000000 0x80>, + <0x4903c000 0x80>; + clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + ti,timer-dsp; + }; + }; + + target-module@3e000 { /* 0x4013e000, ap 24 18.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer8"; + reg = <0x3e000 0x4>, + <0x3e010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3e000 0x1000>, + <0x4903e000 0x4903e000 0x1000>; + + timer8: timer@0 { + compatible = "ti,omap4430-timer"; + reg = <0x00000000 0x80>, + <0x4903e000 0x80>; + clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + ti,timer-pwm; + ti,timer-dsp; + }; + }; + + target-module@80000 { /* 0x40180000, ap 26 1a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x80000 0x10000>, + <0x49080000 0x49080000 0x10000>; + }; + + target-module@a0000 { /* 0x401a0000, ap 28 1c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa0000 0x10000>, + <0x490a0000 0x490a0000 0x10000>; + }; + + target-module@c0000 { /* 0x401c0000, ap 30 1e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc0000 0x10000>, + <0x490c0000 0x490c0000 0x10000>; + }; + + target-module@f1000 { /* 0x401f1000, ap 32 20.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "aess"; + reg = <0xf1000 0x4>, + <0xf1010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + ; + /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf1000 0x1000>, + <0x490f1000 0x490f1000 0x1000>; + + /* + * No child device binding or driver in mainline. + * See Android tree and related upstreaming efforts + * for the old driver. + */ + }; + }; +}; + diff --git a/arch/arm/boot/dts/omap4-mcpdm.dtsi b/arch/arm/boot/dts/omap4-mcpdm.dtsi index 9d40e433c4b5..915a9b31a33b 100644 --- a/arch/arm/boot/dts/omap4-mcpdm.dtsi +++ b/arch/arm/boot/dts/omap4-mcpdm.dtsi @@ -27,12 +27,18 @@ }; }; -&mcpdm { +&mcpdm_module { + /* + * McPDM pads must be muxed at the interconnect target module + * level as the module on the SoC needs external clock from + * the PMIC + */ pinctrl-names = "default"; pinctrl-0 = <&mcpdm_pins>; + status = "okay"; +}; +&mcpdm { clocks = <&twl6040>; clock-names = "pdmclk"; - - status = "okay"; }; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 1a96d4317c97..442a737f35fe 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -148,6 +148,9 @@ l4_per: interconnect@48000000 { }; + l4_abe: interconnect@40100000 { + }; + ocmcram: ocmcram@40304000 { compatible = "mmio-sram"; reg = <0x40304000 0xa000>; /* 40k */ @@ -214,130 +217,6 @@ #iommu-cells = <0>; ti,iommu-bus-err-back; }; - target-module@40130000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "wd_timer3"; - reg = <0x40130000 0x4>, - <0x40130010 0x4>, - <0x40130014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): abe, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP4_WD_TIMER3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x40130000 0x1000>, /* MPU private access */ - <0x49030000 0x49030000 0x0080>; /* L3 Interconnect */ - - wdt3: wdt@0 { - compatible = "ti,omap4-wdt", "ti,omap3-wdt"; - reg = <0x0 0x80>; - interrupts = ; - }; - }; - - mcpdm: mcpdm@40132000 { - compatible = "ti,omap4-mcpdm"; - reg = <0x40132000 0x7f>, /* MPU private access */ - <0x49032000 0x7f>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - ti,hwmods = "mcpdm"; - dmas = <&sdma 65>, - <&sdma 66>; - dma-names = "up_link", "dn_link"; - status = "disabled"; - }; - - dmic: dmic@4012e000 { - compatible = "ti,omap4-dmic"; - reg = <0x4012e000 0x7f>, /* MPU private access */ - <0x4902e000 0x7f>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - ti,hwmods = "dmic"; - dmas = <&sdma 67>; - dma-names = "up_link"; - status = "disabled"; - }; - - mcbsp1: mcbsp@40122000 { - compatible = "ti,omap4-mcbsp"; - reg = <0x40122000 0xff>, /* MPU private access */ - <0x49022000 0xff>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - interrupt-names = "common"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp1"; - dmas = <&sdma 33>, - <&sdma 34>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - mcbsp2: mcbsp@40124000 { - compatible = "ti,omap4-mcbsp"; - reg = <0x40124000 0xff>, /* MPU private access */ - <0x49024000 0xff>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - interrupt-names = "common"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp2"; - dmas = <&sdma 17>, - <&sdma 18>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - mcbsp3: mcbsp@40126000 { - compatible = "ti,omap4-mcbsp"; - reg = <0x40126000 0xff>, /* MPU private access */ - <0x49026000 0xff>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - interrupt-names = "common"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp3"; - dmas = <&sdma 19>, - <&sdma 20>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - target-module@40128000 { - compatible = "ti,sysc-mcasp", "ti,sysc"; - ti,hwmods = "mcasp"; - reg = <0x40128000 0x4>, - <0x40128004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - , - ; - clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x40128000 0x1000>, /* MPU */ - <0x49028000 0x49028000 0x1000>; /* L3 */ - - /* - * Child device unsupported by davinci-mcasp. At least - * RX path is disabled for omap4, and only DIT mode - * works with no I2S. See also old Android kernel - * omap-mcasp driver for more information. - */ - }; - target-module@4012c000 { compatible = "ti,sysc-omap4", "ti,sysc"; ti,hwmods = "slimbus1"; @@ -359,33 +238,6 @@ /* No child device binding or driver in mainline */ }; - target-module@401f1000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "aess"; - reg = <0x401f1000 0x4>, - <0x401f1010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - ; - clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x401f1000 0x1000>, /* MPU */ - <0x490f1000 0x490f1000 0x1000>; /* L3 */ - - /* - * No child device binding or driver in mainline. - * See Android tree and related upstreaming efforts - * for the old driver. - */ - }; - dmm@4e000000 { compatible = "ti,omap4-dmm"; reg = <0x4e000000 0x800>; @@ -417,43 +269,6 @@ hw-caps-temp-alert; }; - timer5: timer@40138000 { - compatible = "ti,omap4430-timer"; - reg = <0x40138000 0x80>, - <0x49038000 0x80>; - interrupts = ; - ti,hwmods = "timer5"; - ti,timer-dsp; - }; - - timer6: timer@4013a000 { - compatible = "ti,omap4430-timer"; - reg = <0x4013a000 0x80>, - <0x4903a000 0x80>; - interrupts = ; - ti,hwmods = "timer6"; - ti,timer-dsp; - }; - - timer7: timer@4013c000 { - compatible = "ti,omap4430-timer"; - reg = <0x4013c000 0x80>, - <0x4903c000 0x80>; - interrupts = ; - ti,hwmods = "timer7"; - ti,timer-dsp; - }; - - timer8: timer@4013e000 { - compatible = "ti,omap4430-timer"; - reg = <0x4013e000 0x80>, - <0x4903e000 0x80>; - interrupts = ; - ti,hwmods = "timer8"; - ti,timer-pwm; - ti,timer-dsp; - }; - aes1: aes@4b501000 { compatible = "ti,omap4-aes"; ti,hwmods = "aes1"; @@ -629,4 +444,5 @@ }; #include "omap4-l4.dtsi" +#include "omap4-l4-abe.dtsi" #include "omap44xx-clocks.dtsi" -- cgit From b2770b2d6f1b4d33e919fc2a9ccf536efedc1e40 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Tue, 9 Apr 2019 09:00:54 -0700 Subject: ARM: dts: Add l4 abe interconnect hierarchy and ti-sysc data for omap5 We can now add l4 abe interconnect hierarchy and ti-sysc data with ti-sysc driver supporting external optional clocks needed by mcpdm. This data is generated based on platform data from a booted system and the interconnect acces protection registers for ranges. To avoid regressions, we initially validate the device tree provided data against the existing platform data on boot. Note that mcpdm we now need to enable at module level only for devices that have the external pdmclk wired from the PMIC as the clock is needed for the module to be accessible. Also note that abe seems to be the same as on omap4 except for domains and clocks and we may be able to combine the l4 abe data later on. But let's play it safe and just initially use what we have already defined in the platform data. Cc: devicetree@vger.kernel.org Cc: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5-board-common.dtsi | 8 +- arch/arm/boot/dts/omap5-l4-abe.dtsi | 447 ++++++++++++++++++++++++++++++ arch/arm/boot/dts/omap5.dtsi | 115 +------- 3 files changed, 458 insertions(+), 112 deletions(-) create mode 100644 arch/arm/boot/dts/omap5-l4-abe.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/omap5-board-common.dtsi index 61a06f6add3c..2dc3e1950c96 100644 --- a/arch/arm/boot/dts/omap5-board-common.dtsi +++ b/arch/arm/boot/dts/omap5-board-common.dtsi @@ -667,14 +667,16 @@ }; }; -&mcpdm { +&mcpdm_module { + /* Module on the SoC needs external clock from the PMIC */ pinctrl-names = "default"; pinctrl-0 = <&mcpdm_pins>; + status = "okay"; +}; +&mcpdm { clocks = <&twl6040>; clock-names = "pdmclk"; - - status = "okay"; }; &mcbsp1 { diff --git a/arch/arm/boot/dts/omap5-l4-abe.dtsi b/arch/arm/boot/dts/omap5-l4-abe.dtsi new file mode 100644 index 000000000000..dc9d0532f4cf --- /dev/null +++ b/arch/arm/boot/dts/omap5-l4-abe.dtsi @@ -0,0 +1,447 @@ +&l4_abe { /* 0x40100000 */ + compatible = "ti,omap5-l4-abe", "simple-bus"; + reg = <0x40100000 0x400>, + <0x40100400 0x400>; + reg-names = "la", "ap"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */ + <0x49000000 0x49000000 0x100000>; + segment@0 { /* 0x40100000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = + /* CPU to L4 ABE mapping */ + <0x00000000 0x00000000 0x000400>, /* ap 0 */ + <0x00000400 0x00000400 0x000400>, /* ap 1 */ + <0x00022000 0x00022000 0x001000>, /* ap 2 */ + <0x00023000 0x00023000 0x001000>, /* ap 3 */ + <0x00024000 0x00024000 0x001000>, /* ap 4 */ + <0x00025000 0x00025000 0x001000>, /* ap 5 */ + <0x00026000 0x00026000 0x001000>, /* ap 6 */ + <0x00027000 0x00027000 0x001000>, /* ap 7 */ + <0x00028000 0x00028000 0x001000>, /* ap 8 */ + <0x00029000 0x00029000 0x001000>, /* ap 9 */ + <0x0002a000 0x0002a000 0x001000>, /* ap 10 */ + <0x0002b000 0x0002b000 0x001000>, /* ap 11 */ + <0x0002e000 0x0002e000 0x001000>, /* ap 12 */ + <0x0002f000 0x0002f000 0x001000>, /* ap 13 */ + <0x00030000 0x00030000 0x001000>, /* ap 14 */ + <0x00031000 0x00031000 0x001000>, /* ap 15 */ + <0x00032000 0x00032000 0x001000>, /* ap 16 */ + <0x00033000 0x00033000 0x001000>, /* ap 17 */ + <0x00038000 0x00038000 0x001000>, /* ap 18 */ + <0x00039000 0x00039000 0x001000>, /* ap 19 */ + <0x0003a000 0x0003a000 0x001000>, /* ap 20 */ + <0x0003b000 0x0003b000 0x001000>, /* ap 21 */ + <0x0003c000 0x0003c000 0x001000>, /* ap 22 */ + <0x0003d000 0x0003d000 0x001000>, /* ap 23 */ + <0x0003e000 0x0003e000 0x001000>, /* ap 24 */ + <0x0003f000 0x0003f000 0x001000>, /* ap 25 */ + <0x00080000 0x00080000 0x010000>, /* ap 26 */ + <0x00080000 0x00080000 0x001000>, /* ap 27 */ + <0x000a0000 0x000a0000 0x010000>, /* ap 28 */ + <0x000a0000 0x000a0000 0x001000>, /* ap 29 */ + <0x000c0000 0x000c0000 0x010000>, /* ap 30 */ + <0x000c0000 0x000c0000 0x001000>, /* ap 31 */ + <0x000f1000 0x000f1000 0x001000>, /* ap 32 */ + <0x000f2000 0x000f2000 0x001000>, /* ap 33 */ + + /* L3 to L4 ABE mapping */ + <0x49000000 0x49000000 0x000400>, /* ap 0 */ + <0x49000400 0x49000400 0x000400>, /* ap 1 */ + <0x49022000 0x49022000 0x001000>, /* ap 2 */ + <0x49023000 0x49023000 0x001000>, /* ap 3 */ + <0x49024000 0x49024000 0x001000>, /* ap 4 */ + <0x49025000 0x49025000 0x001000>, /* ap 5 */ + <0x49026000 0x49026000 0x001000>, /* ap 6 */ + <0x49027000 0x49027000 0x001000>, /* ap 7 */ + <0x49028000 0x49028000 0x001000>, /* ap 8 */ + <0x49029000 0x49029000 0x001000>, /* ap 9 */ + <0x4902a000 0x4902a000 0x001000>, /* ap 10 */ + <0x4902b000 0x4902b000 0x001000>, /* ap 11 */ + <0x4902e000 0x4902e000 0x001000>, /* ap 12 */ + <0x4902f000 0x4902f000 0x001000>, /* ap 13 */ + <0x49030000 0x49030000 0x001000>, /* ap 14 */ + <0x49031000 0x49031000 0x001000>, /* ap 15 */ + <0x49032000 0x49032000 0x001000>, /* ap 16 */ + <0x49033000 0x49033000 0x001000>, /* ap 17 */ + <0x49038000 0x49038000 0x001000>, /* ap 18 */ + <0x49039000 0x49039000 0x001000>, /* ap 19 */ + <0x4903a000 0x4903a000 0x001000>, /* ap 20 */ + <0x4903b000 0x4903b000 0x001000>, /* ap 21 */ + <0x4903c000 0x4903c000 0x001000>, /* ap 22 */ + <0x4903d000 0x4903d000 0x001000>, /* ap 23 */ + <0x4903e000 0x4903e000 0x001000>, /* ap 24 */ + <0x4903f000 0x4903f000 0x001000>, /* ap 25 */ + <0x49080000 0x49080000 0x010000>, /* ap 26 */ + <0x49080000 0x49080000 0x001000>, /* ap 27 */ + <0x490a0000 0x490a0000 0x010000>, /* ap 28 */ + <0x490a0000 0x490a0000 0x001000>, /* ap 29 */ + <0x490c0000 0x490c0000 0x010000>, /* ap 30 */ + <0x490c0000 0x490c0000 0x001000>, /* ap 31 */ + <0x490f1000 0x490f1000 0x001000>, /* ap 32 */ + <0x490f2000 0x490f2000 0x001000>; /* ap 33 */ + + target-module@22000 { /* 0x40122000, ap 2 02.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "mcbsp1"; + reg = <0x2208c 0x4>; + reg-names = "sysc"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET)>; + ti,sysc-sidle = , + , + ; + /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP5_MCBSP1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x22000 0x1000>, + <0x49022000 0x49022000 0x1000>; + + mcbsp1: mcbsp@0 { + compatible = "ti,omap4-mcbsp"; + reg = <0x0 0xff>, /* MPU private access */ + <0x49022000 0xff>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = ; + interrupt-names = "common"; + ti,buffer-size = <128>; + dmas = <&sdma 33>, + <&sdma 34>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + }; + + target-module@24000 { /* 0x40124000, ap 4 04.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "mcbsp2"; + reg = <0x2408c 0x4>; + reg-names = "sysc"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET)>; + ti,sysc-sidle = , + , + ; + /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP5_MCBSP2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x24000 0x1000>, + <0x49024000 0x49024000 0x1000>; + + mcbsp2: mcbsp@0 { + compatible = "ti,omap4-mcbsp"; + reg = <0x0 0xff>, /* MPU private access */ + <0x49024000 0xff>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = ; + interrupt-names = "common"; + ti,buffer-size = <128>; + dmas = <&sdma 17>, + <&sdma 18>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + }; + + target-module@26000 { /* 0x40126000, ap 6 06.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "mcbsp3"; + reg = <0x2608c 0x4>; + reg-names = "sysc"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET)>; + ti,sysc-sidle = , + , + ; + /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP5_MCBSP3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x26000 0x1000>, + <0x49026000 0x49026000 0x1000>; + + mcbsp3: mcbsp@0 { + compatible = "ti,omap4-mcbsp"; + reg = <0x0 0xff>, /* MPU private access */ + <0x49026000 0xff>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = ; + interrupt-names = "common"; + ti,buffer-size = <128>; + dmas = <&sdma 19>, + <&sdma 20>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + }; + + target-module@28000 { /* 0x40128000, ap 8 08.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x28000 0x1000>, + <0x49028000 0x49028000 0x1000>; + }; + + target-module@2a000 { /* 0x4012a000, ap 10 0a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2a000 0x1000>, + <0x4902a000 0x4902a000 0x1000>; + }; + + target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "dmic"; + reg = <0x2e000 0x4>, + <0x2e010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP5_DMIC_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2e000 0x1000>, + <0x4902e000 0x4902e000 0x1000>; + + dmic: dmic@0 { + compatible = "ti,omap4-dmic"; + reg = <0x0 0x7f>, /* MPU private access */ + <0x4902e000 0x7f>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = ; + dmas = <&sdma 67>; + dma-names = "up_link"; + status = "disabled"; + }; + }; + + target-module@30000 { /* 0x40130000, ap 14 0e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x30000 0x1000>, + <0x49030000 0x49030000 0x1000>; + }; + + mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mcpdm"; + reg = <0x32000 0x4>, + <0x32010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP5_MCPDM_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x32000 0x1000>, + <0x49032000 0x49032000 0x1000>; + + /* Must be only enabled for boards with pdmclk wired */ + status = "disabled"; + + mcpdm: mcpdm@0 { + compatible = "ti,omap4-mcpdm"; + reg = <0x0 0x7f>, /* MPU private access */ + <0x49032000 0x7f>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = ; + dmas = <&sdma 65>, + <&sdma 66>; + dma-names = "up_link", "dn_link"; + }; + }; + + target-module@38000 { /* 0x40138000, ap 18 12.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer5"; + reg = <0x38000 0x4>, + <0x38010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x38000 0x1000>, + <0x49038000 0x49038000 0x1000>; + + timer5: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>, + <0x49038000 0x80>; + clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + ti,timer-dsp; + ti,timer-pwm; + }; + }; + + target-module@3a000 { /* 0x4013a000, ap 20 14.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer6"; + reg = <0x3a000 0x4>, + <0x3a010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3a000 0x1000>, + <0x4903a000 0x4903a000 0x1000>; + + timer6: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>, + <0x4903a000 0x80>; + clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + ti,timer-dsp; + ti,timer-pwm; + }; + }; + + target-module@3c000 { /* 0x4013c000, ap 22 16.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer7"; + reg = <0x3c000 0x4>, + <0x3c010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3c000 0x1000>, + <0x4903c000 0x4903c000 0x1000>; + + timer7: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>, + <0x4903c000 0x80>; + clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + ti,timer-dsp; + }; + }; + + target-module@3e000 { /* 0x4013e000, ap 24 18.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer8"; + reg = <0x3e000 0x4>, + <0x3e010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3e000 0x1000>, + <0x4903e000 0x4903e000 0x1000>; + + timer8: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>, + <0x4903e000 0x80>; + clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + ti,timer-dsp; + ti,timer-pwm; + }; + }; + + target-module@80000 { /* 0x40180000, ap 26 1a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x80000 0x10000>, + <0x49080000 0x49080000 0x10000>; + }; + + target-module@a0000 { /* 0x401a0000, ap 28 1c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa0000 0x10000>, + <0x490a0000 0x490a0000 0x10000>; + }; + + target-module@c0000 { /* 0x401c0000, ap 30 1e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc0000 0x10000>, + <0x490c0000 0x490c0000 0x10000>; + }; + + target-module@f1000 { /* 0x401f1000, ap 32 20.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf1000 0x1000>, + <0x490f1000 0x490f1000 0x1000>; + }; + }; +}; + diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 2fefaafdf901..4b40e4748649 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -161,6 +161,9 @@ l4_per: interconnect@48000000 { }; + l4_abe: interconnect@40100000 { + }; + ocmcram: ocmcram@40300000 { compatible = "mmio-sram"; reg = <0x40300000 0x20000>; /* 128k */ @@ -202,115 +205,6 @@ ti,iommu-bus-err-back; }; - mcpdm: mcpdm@40132000 { - compatible = "ti,omap4-mcpdm"; - reg = <0x40132000 0x7f>, /* MPU private access */ - <0x49032000 0x7f>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - ti,hwmods = "mcpdm"; - dmas = <&sdma 65>, - <&sdma 66>; - dma-names = "up_link", "dn_link"; - status = "disabled"; - }; - - dmic: dmic@4012e000 { - compatible = "ti,omap4-dmic"; - reg = <0x4012e000 0x7f>, /* MPU private access */ - <0x4902e000 0x7f>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - ti,hwmods = "dmic"; - dmas = <&sdma 67>; - dma-names = "up_link"; - status = "disabled"; - }; - - mcbsp1: mcbsp@40122000 { - compatible = "ti,omap4-mcbsp"; - reg = <0x40122000 0xff>, /* MPU private access */ - <0x49022000 0xff>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - interrupt-names = "common"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp1"; - dmas = <&sdma 33>, - <&sdma 34>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - mcbsp2: mcbsp@40124000 { - compatible = "ti,omap4-mcbsp"; - reg = <0x40124000 0xff>, /* MPU private access */ - <0x49024000 0xff>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - interrupt-names = "common"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp2"; - dmas = <&sdma 17>, - <&sdma 18>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - mcbsp3: mcbsp@40126000 { - compatible = "ti,omap4-mcbsp"; - reg = <0x40126000 0xff>, /* MPU private access */ - <0x49026000 0xff>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - interrupt-names = "common"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp3"; - dmas = <&sdma 19>, - <&sdma 20>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - timer5: timer@40138000 { - compatible = "ti,omap5430-timer"; - reg = <0x40138000 0x80>, - <0x49038000 0x80>; - interrupts = ; - ti,hwmods = "timer5"; - ti,timer-dsp; - ti,timer-pwm; - }; - - timer6: timer@4013a000 { - compatible = "ti,omap5430-timer"; - reg = <0x4013a000 0x80>, - <0x4903a000 0x80>; - interrupts = ; - ti,hwmods = "timer6"; - ti,timer-dsp; - ti,timer-pwm; - }; - - timer7: timer@4013c000 { - compatible = "ti,omap5430-timer"; - reg = <0x4013c000 0x80>, - <0x4903c000 0x80>; - interrupts = ; - ti,hwmods = "timer7"; - ti,timer-dsp; - }; - - timer8: timer@4013e000 { - compatible = "ti,omap5430-timer"; - reg = <0x4013e000 0x80>, - <0x4903e000 0x80>; - interrupts = ; - ti,hwmods = "timer8"; - ti,timer-dsp; - ti,timer-pwm; - }; - dmm@4e000000 { compatible = "ti,omap5-dmm"; reg = <0x4e000000 0x800>; @@ -517,3 +411,6 @@ &core_thermal { coefficients = <0 2000>; }; + +#include "omap5-l4-abe.dtsi" +#include "omap54xx-clocks.dtsi" -- cgit From 33984dd6c4bb89b606e38ed5810a157fe81b241c Mon Sep 17 00:00:00 2001 From: Brian Masney Date: Tue, 5 Mar 2019 19:53:09 -0500 Subject: ARM: dts: qcom: apq8064: add gpio-ranges This adds the gpio-ranges property so that the GPIO pins are initialized by the GPIO framework and not pinctrl. This fixes a circular dependency between these two frameworks so GPIO hogging can be used on this board. This was not tested on this particular hardware, however this same change was tested on qcom-pm8941 using a LG Nexus 5 (hammerhead) phone. Signed-off-by: Brian Masney Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-apq8064.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index bd6907db615b..8ca89c79bd0e 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -714,6 +714,7 @@ interrupt-controller; #interrupt-cells = <2>; gpio-controller; + gpio-ranges = <&pm8921_gpio 0 0 44>; #gpio-cells = <2>; }; -- cgit From 3bc5163ebbacf0f0d319f73de3d5e09a61e74f92 Mon Sep 17 00:00:00 2001 From: Brian Masney Date: Tue, 5 Mar 2019 19:53:10 -0500 Subject: ARM: dts: qcom: mdm9615: add gpio-ranges This adds the gpio-ranges property so that the GPIO pins are initialized by the GPIO framework and not pinctrl. This fixes a circular dependency between these two frameworks so GPIO hogging can be used on this board. This was not tested on this particular hardware, however this same change was tested on qcom-pm8941 using a LG Nexus 5 (hammerhead) phone. Signed-off-by: Brian Masney Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-mdm9615.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi index 02afc6a42005..356e9535f7a6 100644 --- a/arch/arm/boot/dts/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi @@ -326,6 +326,7 @@ interrupt-controller; #interrupt-cells = <2>; gpio-controller; + gpio-ranges = <&pmicgpio 0 0 6>; #gpio-cells = <2>; }; }; -- cgit From 546f72e7ecb25594a30f884da0d8ae79ad278cef Mon Sep 17 00:00:00 2001 From: Brian Masney Date: Tue, 5 Mar 2019 19:53:11 -0500 Subject: ARM: dts: qcom: msm8660: add gpio-ranges This adds the gpio-ranges property so that the GPIO pins are initialized by the GPIO framework and not pinctrl. This fixes a circular dependency between these two frameworks so GPIO hogging can be used on this board. This was not tested on this particular hardware, however this same change was tested on qcom-pm8941 using a LG Nexus 5 (hammerhead) phone. Signed-off-by: Brian Masney Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-msm8660.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 65a994f0e09b..ec5cbc468bd3 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -295,6 +295,7 @@ interrupt-controller; #interrupt-cells = <2>; gpio-controller; + gpio-ranges = <&pm8058_gpio 0 0 44>; #gpio-cells = <2>; }; -- cgit From 05d86a0ae83b62a11f74760d8edf84580beccb3e Mon Sep 17 00:00:00 2001 From: Brian Masney Date: Tue, 5 Mar 2019 19:53:12 -0500 Subject: ARM: dts: qcom: pma8084: add gpio-ranges This adds the gpio-ranges property so that the GPIO pins are initialized by the GPIO framework and not pinctrl. This fixes a circular dependency between these two frameworks so GPIO hogging can be used on this board. This was not tested on this particular hardware, however this same change was tested on qcom-pm8941 using a LG Nexus 5 (hammerhead) phone. Signed-off-by: Brian Masney Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-pma8084.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-pma8084.dtsi b/arch/arm/boot/dts/qcom-pma8084.dtsi index 8f5ea7add20f..ea1ca166165c 100644 --- a/arch/arm/boot/dts/qcom-pma8084.dtsi +++ b/arch/arm/boot/dts/qcom-pma8084.dtsi @@ -31,6 +31,7 @@ compatible = "qcom,pma8084-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pma8084_gpios 0 0 22>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; -- cgit From f3e35357cd460a8aeb48b8113dc4b761a7d5c828 Mon Sep 17 00:00:00 2001 From: Christian Lamparter Date: Tue, 26 Feb 2019 01:12:01 +0100 Subject: ARM: dts: qcom: ipq4019: enlarge PCIe BAR range David Bauer reported that the VDSL modem (attached via PCIe) on his AVM Fritz!Box 7530 was complaining about not having enough space in the BAR. A closer inspection of the old qcom-ipq40xx.dtsi pulled from the GL-iNet repository listed: | qcom,pcie@80000 { | compatible = "qcom,msm_pcie"; | reg = <0x80000 0x2000>, | <0x99000 0x800>, | <0x40000000 0xf1d>, | <0x40000f20 0xa8>, | <0x40100000 0x1000>, | <0x40200000 0x100000>, | <0x40300000 0xd00000>; | reg-names = "parf", "phy", "dm_core", "elbi", | "conf", "io", "bars"; Matching the reg-names with the listed reg leads to <0xd00000> as the size for the "bars". Cc: stable@vger.kernel.org BugLink: https://www.mail-archive.com/openwrt-devel@lists.openwrt.org/msg45212.html Reported-by: David Bauer Signed-off-by: Christian Lamparter Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 9e75f97770ce..1008dfbcb972 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -400,8 +400,8 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000 - 0x82000000 0 0x40300000 0x40300000 0 0x400000>; + ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000>, + <0x82000000 0 0x40300000 0x40300000 0 0x00d00000>; interrupts = ; interrupt-names = "msi"; -- cgit From 22f88e311399d4f68abc662934253f553edb18f2 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 3 Apr 2018 14:32:11 +0200 Subject: ARM: dts: sun5i: Add the MBUS controller The MBUS (and its associated controller) is the bus in the Allwinner SoCs that DMA devices use in the system to access the memory. Among other things (and depending on the SoC generation), it can also enforce priorities or report bandwidth usages on a per-master basis. One of the most notable thing is that instead of having the same mapping for the RAM than the CPU, it maps it at address 0, which means we'll have to do address translation thanks to the dma-ranges property. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index 8dd49016eb1e..cb820bd7974c 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -127,6 +127,7 @@ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; + dma-ranges; ranges; system-control@1c00000 { @@ -181,6 +182,14 @@ }; }; + mbus: dram-controller@1c01000 { + compatible = "allwinner,sun5i-a13-mbus"; + reg = <0x01c01000 0x1000>; + clocks = <&ccu 99>; + dma-ranges = <0x00000000 0x40000000 0x20000000>; + #interconnect-cells = <1>; + }; + dma: dma-controller@1c02000 { compatible = "allwinner,sun4i-a10-dma"; reg = <0x01c02000 0x1000>; @@ -723,6 +732,8 @@ clock-names = "ahb", "mod", "ram"; resets = <&ccu RST_DE_FE>; + interconnects = <&mbus 19>; + interconnect-names = "dma-mem"; status = "disabled"; ports { @@ -748,6 +759,8 @@ clock-names = "ahb", "mod", "ram"; resets = <&ccu RST_DE_BE>; + interconnects = <&mbus 18>; + interconnect-names = "dma-mem"; status = "disabled"; assigned-clocks = <&ccu CLK_DE_BE>; -- cgit From 06d536094645c703ce29d75de91eddb438d361bf Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 8 Apr 2019 07:19:25 +0200 Subject: ARM: dts: exynos: Use stdout-path property instead of console in bootargs Replacing bootargs with stdout-path property in chosen node allows using early console by adding just 'earlycon' parameter to the kernel command line. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Sylwester Nawrocki --- arch/arm/boot/dts/exynos4412-trats2.dts | 3 ++- arch/arm/boot/dts/exynos5250-smdk5250.dts | 3 ++- arch/arm/boot/dts/exynos5260-xyref5260.dts | 2 +- arch/arm/boot/dts/exynos5410-smdk5410.dts | 2 +- arch/arm/boot/dts/exynos5420-smdk5420.dts | 3 ++- 5 files changed, 8 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts index 327ee980d3a5..aac533933c61 100644 --- a/arch/arm/boot/dts/exynos4412-trats2.dts +++ b/arch/arm/boot/dts/exynos4412-trats2.dts @@ -22,6 +22,7 @@ }; chosen { - bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rootwait earlyprintk panic=5"; + bootargs = "root=/dev/mmcblk0p5 rootwait earlyprintk panic=5"; + stdout-path = "serial2:115200n8"; }; }; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index d5e66189ed2a..6dc96948a9cc 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -24,7 +24,8 @@ }; chosen { - bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc"; + bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc"; + stdout-path = "serial2:115200n8"; }; vdd: fixed-regulator-vdd { diff --git a/arch/arm/boot/dts/exynos5260-xyref5260.dts b/arch/arm/boot/dts/exynos5260-xyref5260.dts index fa19c59b2fb6..36a2b77eeb9d 100644 --- a/arch/arm/boot/dts/exynos5260-xyref5260.dts +++ b/arch/arm/boot/dts/exynos5260-xyref5260.dts @@ -19,7 +19,7 @@ }; chosen { - bootargs = "console=ttySAC2,115200"; + stdout-path = "serial2:115200n8"; }; fin_pll: xxti { diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts index 8fc8c841d34b..dffa5e3ed90c 100644 --- a/arch/arm/boot/dts/exynos5410-smdk5410.dts +++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts @@ -19,7 +19,7 @@ }; chosen { - bootargs = "console=ttySAC2,115200"; + stdout-path = "serial2:115200n8"; }; fin_pll: xxti { diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index 3cf905047893..8240e5186972 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -21,7 +21,8 @@ }; chosen { - bootargs = "console=ttySAC2,115200 init=/linuxrc"; + bootargs = "init=/linuxrc"; + stdout-path = "serial2:115200n8"; }; fixed-rate-clocks { -- cgit From 8cc76b1c75722196fb3d7ffe67cbfeb721a7b0e3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 8 Apr 2019 07:19:26 +0200 Subject: ARM: dts: exynos: Remove console argument from bootargs Remove the "console=ttySAC..." argument from DTSes having a proper stdout-path property. To make the code functionally equivalent, add the serial port baud rate and parity. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Sylwester Nawrocki --- arch/arm/boot/dts/exynos4210-origen.dts | 4 ++-- arch/arm/boot/dts/exynos4210-smdkv310.dts | 4 ++-- arch/arm/boot/dts/exynos4210-trats.dts | 4 ++-- arch/arm/boot/dts/exynos4210-universal_c210.dts | 4 ++-- arch/arm/boot/dts/exynos4412-origen.dts | 3 +-- arch/arm/boot/dts/exynos4412-smdk4412.dts | 4 ++-- 6 files changed, 11 insertions(+), 12 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index dd9ec05eb0f7..36b1edea254a 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -30,8 +30,8 @@ }; chosen { - bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc"; - stdout-path = &serial_2; + bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc"; + stdout-path = "serial2:115200n8"; }; mmc_reg: voltage-regulator { diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts index 7a3e621edede..77fc11e593ad 100644 --- a/arch/arm/boot/dts/exynos4210-smdkv310.dts +++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts @@ -26,8 +26,8 @@ }; chosen { - bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc"; - stdout-path = &serial_1; + bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc"; + stdout-path = "serial1:115200n8"; }; fixed-rate-clocks { diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index 8dbc47d627a5..6882480dbaf7 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -26,8 +26,8 @@ }; chosen { - bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rootwait earlyprintk panic=5"; - stdout-path = &serial_2; + bootargs = "root=/dev/mmcblk0p5 rootwait earlyprintk panic=5"; + stdout-path = "serial2:115200n8"; }; regulators { diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index 5c3d98654f13..07d64a8f82e3 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -24,8 +24,8 @@ }; chosen { - bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rw rootwait earlyprintk panic=5 maxcpus=1"; - stdout-path = &serial_2; + bootargs = "root=/dev/mmcblk0p5 rw rootwait earlyprintk panic=5 maxcpus=1"; + stdout-path = "serial2:115200n8"; }; diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index 346f71932457..698de4345d16 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -25,8 +25,7 @@ }; chosen { - bootargs ="console=ttySAC2,115200"; - stdout-path = &serial_2; + stdout-path = "serial2:115200n8"; }; firmware@203f000 { diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts index 5c5c2887c14f..e70fb6e601f0 100644 --- a/arch/arm/boot/dts/exynos4412-smdk4412.dts +++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts @@ -23,8 +23,8 @@ }; chosen { - bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc"; - stdout-path = &serial_1; + bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc"; + stdout-path = "serial1:115200n8"; }; fixed-rate-clocks { -- cgit From a80a1af6ec8ac59fdddeb013d7c1572bcae4f6eb Mon Sep 17 00:00:00 2001 From: Bruno Thomsen Date: Wed, 3 Apr 2019 08:44:25 +0200 Subject: ARM: dts: tq imx7 common board support This adds TQMa7 and MBa7 board support. TQMa7 can be mounted with either i.MX7 Solo or Dual. All TQMa7 board variants can be mounted in MBa7 carrier board. Signed-off-by: Bruno Thomsen Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-mba7.dtsi | 561 ++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/imx7-tqma7.dtsi | 232 ++++++++++++++++ 2 files changed, 793 insertions(+) create mode 100644 arch/arm/boot/dts/imx7-mba7.dtsi create mode 100644 arch/arm/boot/dts/imx7-tqma7.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi new file mode 100644 index 000000000000..578341b6848b --- /dev/null +++ b/arch/arm/boot/dts/imx7-mba7.dtsi @@ -0,0 +1,561 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Device Tree Include file for TQ Systems MBa7 carrier board. + * + * Copyright (C) 2016 TQ Systems GmbH + * Author: Markus Niebel + * Copyright (C) 2019 Bruno Thomsen + * + * Note: This file does not include nodes for all peripheral devices. + * As device driver coverage increases additional nodes can be added. + */ + +#include +#include + +/ { + beeper { + compatible = "gpio-beeper"; + gpios = <&pca9555 0 GPIO_ACTIVE_HIGH>; + }; + + chosen { + stdout-path = &uart6; + }; + + gpio_buttons: gpio-keys { + compatible = "gpio-keys"; + + button-0 { + /* #SWITCH_A */ + label = "S11"; + linux,code = ; + gpios = <&pca9555 13 GPIO_ACTIVE_LOW>; + }; + + button-1 { + /* #SWITCH_B */ + label = "S12"; + linux,code = ; + gpios = <&pca9555 14 GPIO_ACTIVE_LOW>; + }; + + button-2 { + /* #SWITCH_C */ + label = "S13"; + linux,code = ; + gpios = <&pca9555 15 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led1 { + label = "led1"; + gpios = <&pca9555 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led2 { + label = "led2"; + gpios = <&pca9555 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_sd1_vmmc: regulator-sd1-vmmc { + compatible = "regulator-fixed"; + regulator-name = "VCC3V3_SD1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_fec1_pwdn: regulator-fec1-pwdn { + compatible = "regulator-fixed"; + regulator-name = "PWDN_FEC1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_fec2_pwdn: regulator-fec2-pwdn { + compatible = "regulator-fixed"; + regulator-name = "PWDN_FEC2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + regulator-name = "VBUS_USBOTG1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator-usb-otg2-vbus { + compatible = "regulator-fixed"; + regulator-name = "VBUS_USBOTG2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_mpcie_1v5: regulator-mpcie-1v5 { + compatible = "regulator-fixed"; + regulator-name = "VCC1V5_MPCIE"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&pca9555 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_mpcie_3v3: regulator-mpcie-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC3V3_MPCIE"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9555 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_mba_12v0: regulator-mba-12v0 { + compatible = "regulator-fixed"; + regulator-name = "VCC12V0_MBA7"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&pca9555 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_lvds_transmitter: regulator-lvds-transmitter { + compatible = "regulator-fixed"; + regulator-name = "#SHTDN_LVDS"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9555 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator-vref-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VCC1V8_REF"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <&sw2_reg>; + }; + + reg_audio_3v3: regulator-audio-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC3V3_AUDIO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&adc2 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + num-chipselects = <3>; + cs-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>, <&gpio4 1 GPIO_ACTIVE_LOW>, + <&gpio4 2 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + num-chipselects = <1>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>; + phy-reset-duration = <1>; + phy-reset-delay = <1>; + phy-supply = <®_fec1_pwdn>; + phy-handle = <ðphy1_0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1_0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + /* LED1: Link/Activity, LED2: Error */ + ti,led-function = <0x0db0>; + /* Active low, LED1 and LED2 driven by phy */ + ti,led-ctrl = <0x1001>; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&i2c1 { + lm75: temperature-sensor@49 { + compatible = "national,lm75"; + reg = <0x49>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + tlv320aic32x4: audio-codec@18 { + compatible = "ti,tlv320aic32x4"; + reg = <0x18>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + clock-names = "mclk"; + ldoin-supply = <®_audio_3v3>; + iov-supply = <®_audio_3v3>; + }; + + pca9555: gpio-expander@20 { + compatible = "nxp,pca9555"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pca9555>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio7>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_mba7_1>; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x7c + MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x74 + MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x74 + MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 0x74 + MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x74 + MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x74 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x7c + MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x74 + MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x74 + MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 0x74 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x02 + MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x00 + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x71 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71 + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x71 + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x71 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x79 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x79 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x79 + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x79 + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x79 + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x79 + /* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */ + MX7D_PAD_ENET1_COL__GPIO7_IO15 0x40000070 + /* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */ + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x40000078 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x5a + MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x52 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x5a + MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x52 + >; + }; + + pinctrl_hog_mba7_1: hogmba71grp { + fsl,pins = < + /* Limitation: WDOG2_B / WDOG2_RESET not usable */ + MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x4000007c + MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x40000074 + /* #BOOT_EN */ + MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x40000010 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x40000078 + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x40000078 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX7D_PAD_I2C3_SCL__I2C3_SCL 0x40000078 + MX7D_PAD_I2C3_SDA__I2C3_SDA 0x40000078 + >; + }; + + + pinctrl_pca9555: pca95550grp { + fsl,pins = < + MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x78 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x7e + MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x76 + MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x76 + MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x7e + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x7e + MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x76 + MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS 0x76 + MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS 0x7e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x7e + MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x76 + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x7d + MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x75 + MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x75 + MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x7d + >; + }; + + pinctrl_uart7: uart7grp { + fsl,pins = < + MX7D_PAD_EPDC_DATA12__UART7_DCE_RX 0x7e + MX7D_PAD_EPDC_DATA13__UART7_DCE_TX 0x76 + MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS 0x76 + /* Limitation: RTS is not connected */ + MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS 0x7e + >; + }; + + pinctrl_usdhc1_gpio: usdhc1grp_gpio { + fsl,pins = < + /* WP */ + MX7D_PAD_SD1_WP__GPIO5_IO1 0x7c + /* CD */ + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x7c + /* VSELECT */ + MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5e + MX7D_PAD_SD1_CLK__SD1_CLK 0x57 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5e + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5e + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5e + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5e + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5a + MX7D_PAD_SD1_CLK__SD1_CLK 0x57 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5b + MX7D_PAD_SD1_CLK__SD1_CLK 0x57 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b + >; + }; +}; + +&iomuxc_lpsr { + pinctrl_pwm1: pwm1grp { + fsl,pins = < + /* LCD_CONTRAST */ + MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x50 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x5c + MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x59 + >; + }; + + pinctrl_wdog1: wdog1grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30 + >; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh { + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_sd1_vmmc>; + bus-width = <4>; + no-1-8-v; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog1>; +}; diff --git a/arch/arm/boot/dts/imx7-tqma7.dtsi b/arch/arm/boot/dts/imx7-tqma7.dtsi new file mode 100644 index 000000000000..85fe461e5e67 --- /dev/null +++ b/arch/arm/boot/dts/imx7-tqma7.dtsi @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Device Tree Include file for TQ Systems TQMa7x boards with full mounted PCB. + * + * Copyright (C) 2016 TQ Systems GmbH + * Author: Markus Niebel + * Copyright (C) 2019 Bruno Thomsen + */ + +/ { + memory@80000000 { + device_type = "memory"; + /* 512 MB - default configuration */ + reg = <0x80000000 0x20000000>; + }; +}; + +&cpu0 { + arm-supply = <&sw1a_reg>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <100000>; + status = "okay"; + + pfuze3000: pmic@8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic1>; + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + /* NXP SE97BTP with temperature sensor + eeprom */ + se97b: temperature-sensor-eeprom@1e { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; + reg = <0x1e>; + status = "okay"; + }; + + /* ST M24C64 */ + m24c64: eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + status = "okay"; + }; + + at24c02: eeprom@56 { + compatible = "atmel,24c02"; + reg = <0x56>; + pagesize = <16>; + status = "okay"; + }; + + ds1339: rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +&iomuxc { + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x40000078 + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x40000078 + >; + }; + + pinctrl_pmic1: pmic1grp { + fsl,pins = < + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x4000005C + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x56 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5a + MX7D_PAD_SD3_CLK__SD3_CLK 0x51 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5b + MX7D_PAD_SD3_CLK__SD3_CLK 0x51 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b + >; + }; +}; + +&sdma { + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + non-removable; + vmmc-supply = <&vgen4_reg>; + vqmmc-supply = <&sw2_reg>; + status = "okay"; +}; + +&wdog1 { + status = "okay"; +}; -- cgit From c924f0c07e482c92a74173611d7a2611f91bab22 Mon Sep 17 00:00:00 2001 From: Bruno Thomsen Date: Wed, 3 Apr 2019 08:44:26 +0200 Subject: ARM: dts: tq imx7s board support This adds support for the TQ TQMa7S SoM together with the MBa7 carrier board and it's based on the NXP i.MX7Solo SoC. Signed-off-by: Bruno Thomsen Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx7s-mba7.dts | 18 ++++++++++++++++++ arch/arm/boot/dts/imx7s-tqma7.dtsi | 11 +++++++++++ 3 files changed, 30 insertions(+) create mode 100644 arch/arm/boot/dts/imx7s-mba7.dts create mode 100644 arch/arm/boot/dts/imx7s-tqma7.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 1234bd95d85c..e69e2462e2eb 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -588,6 +588,7 @@ dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-sdb-reva.dtb \ imx7d-sdb-sht11.dtb \ imx7s-colibri-eval-v3.dtb \ + imx7s-mba7.dtb \ imx7s-warp.dtb dtb-$(CONFIG_SOC_IMX7ULP) += \ imx7ulp-evk.dtb diff --git a/arch/arm/boot/dts/imx7s-mba7.dts b/arch/arm/boot/dts/imx7s-mba7.dts new file mode 100644 index 000000000000..a143d566a38b --- /dev/null +++ b/arch/arm/boot/dts/imx7s-mba7.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Device Tree Source for TQ Systems TQMa7S board on MBa7 carrier board. + * + * Copyright (C) 2016 TQ Systems GmbH + * Author: Markus Niebel + * Copyright (C) 2019 Bruno Thomsen + */ + +/dts-v1/; + +#include "imx7s-tqma7.dtsi" +#include "imx7-mba7.dtsi" + +/ { + model = "TQ Systems TQMa7S board on MBa7 carrier board"; + compatible = "tq,imx7s-mba7", "fsl,imx7s"; +}; diff --git a/arch/arm/boot/dts/imx7s-tqma7.dtsi b/arch/arm/boot/dts/imx7s-tqma7.dtsi new file mode 100644 index 000000000000..5f5433eb7dd7 --- /dev/null +++ b/arch/arm/boot/dts/imx7s-tqma7.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Device Tree Include file for TQ Systems TQMa7S board with NXP i.MX7Solo SoC. + * + * Copyright (C) 2016 TQ Systems GmbH + * Author: Markus Niebel + * Copyright (C) 2019 Bruno Thomsen + */ + +#include "imx7s.dtsi" +#include "imx7-tqma7.dtsi" -- cgit From 684a586741e2be211ca9bc800ae631b69fb3f8aa Mon Sep 17 00:00:00 2001 From: Bruno Thomsen Date: Wed, 3 Apr 2019 08:44:27 +0200 Subject: ARM: dts: tq imx7d board support This adds support for the TQ TQMa7D SoM together with the MBa7 carrier board and it's based on the NXP i.MX7Dual SoC. Signed-off-by: Bruno Thomsen Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx7d-mba7.dts | 119 +++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/imx7d-tqma7.dtsi | 11 ++++ 3 files changed, 131 insertions(+) create mode 100644 arch/arm/boot/dts/imx7d-mba7.dts create mode 100644 arch/arm/boot/dts/imx7d-tqma7.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index e69e2462e2eb..c6eec98bc3c2 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -580,6 +580,7 @@ dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-cl-som-imx7.dtb \ imx7d-colibri-emmc-eval-v3.dtb \ imx7d-colibri-eval-v3.dtb \ + imx7d-mba7.dtb \ imx7d-nitrogen7.dtb \ imx7d-pico-hobbit.dtb \ imx7d-pico-pi.dtb \ diff --git a/arch/arm/boot/dts/imx7d-mba7.dts b/arch/arm/boot/dts/imx7d-mba7.dts new file mode 100644 index 000000000000..221274c73dbd --- /dev/null +++ b/arch/arm/boot/dts/imx7d-mba7.dts @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Device Tree Source for TQ Systems TQMa7D board on MBa7 carrier board. + * + * Copyright (C) 2016 TQ Systems GmbH + * Author: Markus Niebel + * Copyright (C) 2019 Bruno Thomsen + */ + +/dts-v1/; + +#include "imx7d-tqma7.dtsi" +#include "imx7-mba7.dtsi" + +/ { + model = "TQ Systems TQMa7D board on MBa7 carrier board"; + compatible = "tq,imx7d-mba7", "fsl,imx7d"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + phy-reset-duration = <1>; + phy-reset-delay = <1>; + phy-supply = <®_fec2_pwdn>; + phy-handle = <ðphy2_0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy2_0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + /* LED1: Link/Activity, LED2: error */ + ti,led-function = <0x0db0>; + /* active low, LED1/2 driven by phy */ + ti,led-ctrl = <0x1001>; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_mba7_1>; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX7D_PAD_SD2_CD_B__ENET2_MDIO 0x02 + MX7D_PAD_SD2_WP__ENET2_MDC 0x00 + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x71 + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x71 + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x71 + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x71 + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x71 + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x71 + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x79 + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x79 + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x79 + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x79 + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x79 + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x79 + /* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */ + MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x40000070 + /* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */ + MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x40000078 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + /* #pcie_wake */ + MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x70 + /* #pcie_rst */ + MX7D_PAD_SD2_CLK__GPIO5_IO12 0x70 + /* #pcie_dis */ + MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x70 + >; + }; +}; + +&iomuxc_lpsr { + pinctrl_usbotg2: usbotg2grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x5c + MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x59 + >; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + /* 1.5V logically from 3.3V */ + /* probe deferral not supported */ + /* pcie-bus-supply = <®_mpcie_1v5>; */ + reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>; + disable-gpio = <&gpio2 29 GPIO_ACTIVE_LOW>; + power-on-gpio = <&gpio2 30 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usbotg2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2>; + vbus-supply = <®_usb_otg2_vbus>; + srp-disable; + hnp-disable; + adp-disable; + dr_mode = "host"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7d-tqma7.dtsi b/arch/arm/boot/dts/imx7d-tqma7.dtsi new file mode 100644 index 000000000000..8ad3048dac0d --- /dev/null +++ b/arch/arm/boot/dts/imx7d-tqma7.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Device Tree Include file for TQ Systems TQMa7D board with NXP i.MX7Dual SoC. + * + * Copyright (C) 2016 TQ Systems GmbH + * Author: Markus Niebel + * Copyright (C) 2019 Bruno Thomsen + */ + +#include "imx7d.dtsi" +#include "imx7-tqma7.dtsi" -- cgit From 8137474b9dd4298f7f0ed541b859f30465cbd8a8 Mon Sep 17 00:00:00 2001 From: Rui Miguel Silva Date: Thu, 28 Mar 2019 14:25:12 +0000 Subject: ARM: dts: imx7s: add mipi phy power domain Add power domain index 0 related with mipi-phy to imx7s. While at it rename pcie power-domain node to remove pgc prefix. Signed-off-by: Rui Miguel Silva Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index e88f53a4c7f4..9a680d3d6424 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -606,7 +606,13 @@ #address-cells = <1>; #size-cells = <0>; - pgc_pcie_phy: pgc-power-domain@1 { + pgc_mipi_phy: power-domain@0 { + #power-domain-cells = <0>; + reg = <0>; + power-supply = <®_1p0d>; + }; + + pgc_pcie_phy: power-domain@1 { #power-domain-cells = <0>; reg = <1>; power-supply = <®_1p0d>; -- cgit From 94a905a79f2cf337376c195acda406a2385792f4 Mon Sep 17 00:00:00 2001 From: Rui Miguel Silva Date: Thu, 28 Mar 2019 14:25:13 +0000 Subject: ARM: dts: imx7s: add multiplexer controls The IOMUXC General Purpose Register has bitfield to control video bus multiplexer to control the CSI input between the MIPI-CSI2 and parallel interface. Add that register and mask. Signed-off-by: Rui Miguel Silva Reviewed-by: Philipp Zabel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s.dtsi | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 9a680d3d6424..792efcd2caa1 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -497,8 +497,15 @@ gpr: iomuxc-gpr@30340000 { compatible = "fsl,imx7d-iomuxc-gpr", - "fsl,imx6q-iomuxc-gpr", "syscon"; + "fsl,imx6q-iomuxc-gpr", "syscon", + "simple-mfd"; reg = <0x30340000 0x10000>; + + mux: mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <0>; + mux-reg-masks = <0x14 0x00000010>; + }; }; ocotp: ocotp-ctrl@30350000 { -- cgit From 6a2736fccfb4491c338286bd025c04c8233c36f5 Mon Sep 17 00:00:00 2001 From: Rui Miguel Silva Date: Thu, 28 Mar 2019 14:25:14 +0000 Subject: ARM: dts: imx7s: Add video mux, csi and mipi_csi Add device tree nodes for csi, video multiplexer and mipi-csi. Signed-off-by: Rui Miguel Silva Reviewed-by: Laurent Pinchart Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s.dtsi | 75 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 792efcd2caa1..3286838105c6 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include "imx7d-pinfunc.h" / { @@ -506,6 +507,34 @@ #mux-control-cells = <0>; mux-reg-masks = <0x14 0x00000010>; }; + + video_mux: csi-mux { + compatible = "video-mux"; + mux-controls = <&mux 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + + csi_mux_from_mipi_vc0: endpoint { + remote-endpoint = <&mipi_vc0_to_csi_mux>; + }; + }; + + port@2 { + reg = <2>; + + csi_mux_to_csi: endpoint { + remote-endpoint = <&csi_from_csi_mux>; + }; + }; + }; }; ocotp: ocotp-ctrl@30350000 { @@ -709,6 +738,23 @@ status = "disabled"; }; + csi: csi@30710000 { + compatible = "fsl,imx7-csi"; + reg = <0x30710000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CSI_MCLK_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "axi", "mclk", "dcic"; + status = "disabled"; + + port { + csi_from_csi_mux: endpoint { + remote-endpoint = <&csi_mux_to_csi>; + }; + }; + }; + lcdif: lcdif@30730000 { compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif"; reg = <0x30730000 0x10000>; @@ -718,6 +764,35 @@ clock-names = "pix", "axi"; status = "disabled"; }; + + mipi_csi: mipi-csi@30750000 { + compatible = "fsl,imx7-mipi-csi2"; + reg = <0x30750000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clks IMX7D_IPG_ROOT_CLK>, + <&clks IMX7D_MIPI_CSI_ROOT_CLK>, + <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; + clock-names = "pclk", "wrap", "phy"; + power-domains = <&pgc_mipi_phy>; + phy-supply = <®_1p0d>; + resets = <&src IMX7_RESET_MIPI_PHY_MRST>; + reset-names = "mrst"; + status = "disabled"; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + + mipi_vc0_to_csi_mux: endpoint { + remote-endpoint = <&csi_mux_from_mipi_vc0>; + }; + }; + }; }; aips3: aips-bus@30800000 { -- cgit From 2cd37a97d1ea5861b33822c364554061244b1322 Mon Sep 17 00:00:00 2001 From: Rui Miguel Silva Date: Thu, 28 Mar 2019 14:25:15 +0000 Subject: ARM: dts: imx7s-warp: add csi and mipi_csi node Add and enable csi and mipi_csi nodes. Signed-off-by: Rui Miguel Silva Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s-warp.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts index b1e956205e9a..2d1a0105e6a6 100644 --- a/arch/arm/boot/dts/imx7s-warp.dts +++ b/arch/arm/boot/dts/imx7s-warp.dts @@ -77,6 +77,10 @@ assigned-clock-rates = <884736000>; }; +&csi { + status = "okay"; +}; + &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; @@ -213,6 +217,12 @@ }; }; +&mipi_csi { + clock-frequency = <166000000>; + fsl,csis-hs-settle = <3>; + status = "okay"; +}; + &sai1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai1>; @@ -279,6 +289,10 @@ status = "okay"; }; +&video_mux { + status = "okay"; +}; + &wdog1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; -- cgit From e345fd42493c1e3517207762f2588b9e293fa47f Mon Sep 17 00:00:00 2001 From: Rui Miguel Silva Date: Thu, 28 Mar 2019 14:25:16 +0000 Subject: ARM: dts: imx7s-warp: add ov2680 sensor node Warp7 comes with a Omnivision OV2680 sensor, add the node here to make complete the camera data path for this system. Add the needed regulator to the analog voltage supply, the port and endpoints in mipi_csi node and the pinctrl for the reset gpio. Signed-off-by: Rui Miguel Silva Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s-warp.dts | 45 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts index 2d1a0105e6a6..d6b4888fa686 100644 --- a/arch/arm/boot/dts/imx7s-warp.dts +++ b/arch/arm/boot/dts/imx7s-warp.dts @@ -55,6 +55,14 @@ regulator-always-on; }; + reg_peri_3p15v: regulator-peri-3p15v { + compatible = "regulator-fixed"; + regulator-name = "peri_3p15v_reg"; + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3150000>; + regulator-always-on; + }; + sound { compatible = "simple-audio-card"; simple-audio-card,name = "imx7-sgtl5000"; @@ -184,6 +192,27 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + + ov2680: camera@36 { + compatible = "ovti,ov2680"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov2680>; + reg = <0x36>; + clocks = <&osc>; + clock-names = "xvclk"; + reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; + DOVDD-supply = <&sw2_reg>; + DVDD-supply = <&sw2_reg>; + AVDD-supply = <®_peri_3p15v>; + + port { + ov2680_to_mipi: endpoint { + remote-endpoint = <&mipi_from_sensor>; + clock-lanes = <0>; + data-lanes = <1>; + }; + }; + }; }; &i2c3 { @@ -221,6 +250,16 @@ clock-frequency = <166000000>; fsl,csis-hs-settle = <3>; status = "okay"; + + port@0 { + reg = <0>; + + mipi_from_sensor: endpoint { + remote-endpoint = <&ov2680_to_mipi>; + data-lanes = <1>; + }; + + }; }; &sai1 { @@ -347,6 +386,12 @@ >; }; + pinctrl_ov2680: ov2660grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x14 + >; + }; + pinctrl_sai1: sai1grp { fsl,pins = < MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f -- cgit From b14c872eebc501b9640b04f4a152df51d6eaf2fc Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Thu, 28 Mar 2019 23:49:16 -0700 Subject: ARM: dts: imx6qdl: Specify IMX6QDL_CLK_IPG as "ipg" clock to SDMA Since 25aaa75df1e6 SDMA driver uses clock rates of "ipg" and "ahb" clock to determine if it needs to configure the IP block as operating at 1:1 or 1:2 clock ratio (ACR bit in SDMAARM_CONFIG). Specifying both clocks as IMX6QDL_CLK_SDMA results in driver incorrectly thinking that ratio is 1:1 which results in broken SDMA funtionality(this at least breaks RAVE SP serdev driver on RDU2). Fix the code to specify IMX6QDL_CLK_IPG as "ipg" clock for SDMA, to avoid detecting incorrect clock ratio. Signed-off-by: Andrey Smirnov Reviewed-by: Lucas Stach Cc: Angus Ainslie (Purism) Cc: Chris Healy Cc: Lucas Stach Cc: Fabio Estevam Cc: Shawn Guo Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Tested-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 38b18a007f48..b3a77bcf00d5 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -928,7 +928,7 @@ compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; reg = <0x020ec000 0x4000>; interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_SDMA>, + clocks = <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_SDMA>; clock-names = "ipg", "ahb"; #dma-cells = <3>; -- cgit From 8979117765c19edc3b01cc0ef853537bf93eea4b Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Thu, 28 Mar 2019 23:49:17 -0700 Subject: ARM: dts: imx6sx: Specify IMX6SX_CLK_IPG as "ipg" clock to SDMA Since 25aaa75df1e6 SDMA driver uses clock rates of "ipg" and "ahb" clock to determine if it needs to configure the IP block as operating at 1:1 or 1:2 clock ratio (ACR bit in SDMAARM_CONFIG). Specifying both clocks as IMX6SX_CLK_SDMA results in driver incorrectly thinking that ratio is 1:1 which results in broken SDMA funtionality. Fix the code to specify IMX6SX_CLK_IPG as "ipg" clock for SDMA, to avoid detecting incorrect clock ratio. Signed-off-by: Andrey Smirnov Cc: Angus Ainslie (Purism) Cc: Chris Healy Cc: Lucas Stach Cc: Fabio Estevam Cc: Shawn Guo Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index df0c59519886..b16a123990a2 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -820,7 +820,7 @@ compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma"; reg = <0x020ec000 0x4000>; interrupts = ; - clocks = <&clks IMX6SX_CLK_SDMA>, + clocks = <&clks IMX6SX_CLK_IPG>, <&clks IMX6SX_CLK_SDMA>; clock-names = "ipg", "ahb"; #dma-cells = <3>; -- cgit From 412b032a1dc72fc9d1c258800355efa6671b6315 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Thu, 28 Mar 2019 23:49:18 -0700 Subject: ARM: dts: imx7d: Specify IMX7D_CLK_IPG as "ipg" clock to SDMA Since 25aaa75df1e6 SDMA driver uses clock rates of "ipg" and "ahb" clock to determine if it needs to configure the IP block as operating at 1:1 or 1:2 clock ratio (ACR bit in SDMAARM_CONFIG). Specifying both clocks as IMX7D_CLK_SDMA results in driver incorrectly thinking that ratio is 1:1 which results in broken SDMA funtionality. Fix the code to specify IMX7D_CLK_IPG as "ipg" clock for SDMA, to avoid detecting incorrect clock ratio. Signed-off-by: Andrey Smirnov Cc: Angus Ainslie (Purism) Cc: Chris Healy Cc: Lucas Stach Cc: Fabio Estevam Cc: Shawn Guo Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 3286838105c6..0b01109ac0a9 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -1155,8 +1155,8 @@ compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma"; reg = <0x30bd0000 0x10000>; interrupts = ; - clocks = <&clks IMX7D_SDMA_CORE_CLK>, - <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; + clocks = <&clks IMX7D_IPG_ROOT_CLK>, + <&clks IMX7D_SDMA_CORE_CLK>; clock-names = "ipg", "ahb"; #dma-cells = <3>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; -- cgit From 7b3132ecefdd1fcdf6b86e62021d0e55ea8034db Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Thu, 28 Mar 2019 23:49:19 -0700 Subject: ARM: dts: imx6ul: Specify IMX6UL_CLK_IPG as "ipg" clock to SDMA Since 25aaa75df1e6 SDMA driver uses clock rates of "ipg" and "ahb" clock to determine if it needs to configure the IP block as operating at 1:1 or 1:2 clock ratio (ACR bit in SDMAARM_CONFIG). Specifying both clocks as IMX6UL_CLK_SDMA results in driver incorrectly thinking that ratio is 1:1 which results in broken SDMA funtionality. Fix the code to specify IMX6UL_CLK_IPG as "ipg" clock for SDMA, to avoid detecting incorrect clock ratio. Signed-off-by: Andrey Smirnov Cc: Angus Ainslie (Purism) Cc: Chris Healy Cc: Lucas Stach Cc: Fabio Estevam Cc: Shawn Guo Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index a77bbcae4571..bbf010c73336 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -708,7 +708,7 @@ "fsl,imx35-sdma"; reg = <0x020ec000 0x4000>; interrupts = ; - clocks = <&clks IMX6UL_CLK_SDMA>, + clocks = <&clks IMX6UL_CLK_IPG>, <&clks IMX6UL_CLK_SDMA>; clock-names = "ipg", "ahb"; #dma-cells = <3>; -- cgit From c5ed5daa65d5f665e666b76c3dbfa503066defde Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Thu, 28 Mar 2019 23:49:20 -0700 Subject: ARM: dts: imx6sll: Specify IMX6SLL_CLK_IPG as "ipg" clock to SDMA Since 25aaa75df1e6 SDMA driver uses clock rates of "ipg" and "ahb" clock to determine if it needs to configure the IP block as operating at 1:1 or 1:2 clock ratio (ACR bit in SDMAARM_CONFIG). Specifying both clocks as IMX6SLL_CLK_SDMA result in driver incorrectly thinking that ratio is 1:1 which results in broken SDMA funtionality. Fix the code to specify IMX6SLL_CLK_IPG as "ipg" clock for SDMA, to avoid detecting incorrect clock ratio. Signed-off-by: Andrey Smirnov Cc: Angus Ainslie (Purism) Cc: Chris Healy Cc: Lucas Stach Cc: Fabio Estevam Cc: Shawn Guo Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sll.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi index 62847c68330b..ed598d72038c 100644 --- a/arch/arm/boot/dts/imx6sll.dtsi +++ b/arch/arm/boot/dts/imx6sll.dtsi @@ -621,7 +621,7 @@ compatible = "fsl,imx6sll-sdma", "fsl,imx35-sdma"; reg = <0x020ec000 0x4000>; interrupts = ; - clocks = <&clks IMX6SLL_CLK_SDMA>, + clocks = <&clks IMX6SLL_CLK_IPG>, <&clks IMX6SLL_CLK_SDMA>; clock-names = "ipg", "ahb"; #dma-cells = <3>; -- cgit From cc839d0f8c284fcb7591780b568f13415bbb737c Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Thu, 28 Mar 2019 23:49:21 -0700 Subject: ARM: dts: imx6sx: Specify IMX6SX_CLK_IPG as "ahb" clock to SDMA Since 25aaa75df1e6 SDMA driver uses clock rates of "ipg" and "ahb" clock to determine if it needs to configure the IP block as operating at 1:1 or 1:2 clock ratio (ACR bit in SDMAARM_CONFIG). Specifying both clocks as IMX6SL_CLK_SDMA results in driver incorrectly thinking that ratio is 1:1 which results in broken SDMA funtionality. Fix the code to specify IMX6SL_CLK_AHB as "ahb" clock for SDMA, to avoid detecting incorrect clock ratio. Signed-off-by: Andrey Smirnov Cc: Angus Ainslie (Purism) Cc: Chris Healy Cc: Lucas Stach Cc: Fabio Estevam Cc: Shawn Guo Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 0ad5d507abec..9ddbeea64b72 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -748,7 +748,7 @@ reg = <0x020ec000 0x4000>; interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_SDMA>, - <&clks IMX6SL_CLK_SDMA>; + <&clks IMX6SL_CLK_AHB>; clock-names = "ipg", "ahb"; #dma-cells = <3>; /* imx6sl reuses imx6q sdma firmware */ -- cgit From 28c168018e0902c67eb9c60d0fc4c8aa166c4efe Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Thu, 28 Mar 2019 23:49:22 -0700 Subject: ARM: dts: imx53: Specify IMX5_CLK_IPG as "ahb" clock to SDMA Since 25aaa75df1e6 SDMA driver uses clock rates of "ipg" and "ahb" clock to determine if it needs to configure the IP block as operating at 1:1 or 1:2 clock ratio (ACR bit in SDMAARM_CONFIG). Specifying both clocks as IMX5_CLK_SDMA results in driver incorrectly thinking that ratio is 1:1 which results in broken SDMA funtionality. Fix the code to specify IMX5_CLK_AHB as "ahb" clock for SDMA, to avoid detecting incorrect clock ratio. Signed-off-by: Andrey Smirnov Cc: Angus Ainslie (Purism) Cc: Chris Healy Cc: Lucas Stach Cc: Fabio Estevam Cc: Shawn Guo Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index b3300300aabe..9b672ed2486d 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -702,7 +702,7 @@ reg = <0x63fb0000 0x4000>; interrupts = <6>; clocks = <&clks IMX5_CLK_SDMA_GATE>, - <&clks IMX5_CLK_SDMA_GATE>; + <&clks IMX5_CLK_AHB>; clock-names = "ipg", "ahb"; #dma-cells = <3>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; -- cgit From 918bbde8085ae147a43dcb491953e0dd8f3e9d6a Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Thu, 28 Mar 2019 23:49:23 -0700 Subject: ARM: dts: imx51: Specify IMX5_CLK_IPG as "ahb" clock to SDMA Since 25aaa75df1e6 SDMA driver uses clock rates of "ipg" and "ahb" clock to determine if it needs to configure the IP block as operating at 1:1 or 1:2 clock ratio (ACR bit in SDMAARM_CONFIG). Specifying both clocks as IMX5_CLK_SDMA results in driver incorrectly thinking that ratio is 1:1 which results in broken SDMA funtionality. Fix the code to specify IMX5_CLK_AHB as "ahb" clock for SDMA, to avoid detecting incorrect clock ratio. Signed-off-by: Andrey Smirnov Cc: Angus Ainslie (Purism) Cc: Chris Healy Cc: Lucas Stach Cc: Fabio Estevam Cc: Shawn Guo Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index a5ee25cedc10..0a4b9a5d9a9c 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -489,7 +489,7 @@ reg = <0x83fb0000 0x4000>; interrupts = <6>; clocks = <&clks IMX5_CLK_SDMA_GATE>, - <&clks IMX5_CLK_SDMA_GATE>; + <&clks IMX5_CLK_AHB>; clock-names = "ipg", "ahb"; #dma-cells = <3>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; -- cgit From b7b4fda2636296471e29b78c2aa9535d7bedb7a0 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Thu, 28 Mar 2019 23:49:24 -0700 Subject: ARM: dts: imx50: Specify IMX5_CLK_IPG as "ahb" clock to SDMA Since 25aaa75df1e6 SDMA driver uses clock rates of "ipg" and "ahb" clock to determine if it needs to configure the IP block as operating at 1:1 or 1:2 clock ratio (ACR bit in SDMAARM_CONFIG). Specifying both clocks as IMX5_CLK_SDMA results in driver incorrectly thinking that ratio is 1:1 which results in broken SDMA funtionality. Fix the code to specify IMX5_CLK_AHB as "ahb" clock for SDMA, to avoid detecting incorrect clock ratio. Signed-off-by: Andrey Smirnov Cc: Angus Ainslie (Purism) Cc: Chris Healy Cc: Lucas Stach Cc: Fabio Estevam Cc: Shawn Guo Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx50.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index 5dd61bff3b76..0bfe7c91d0eb 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -430,7 +430,7 @@ reg = <0x63fb0000 0x4000>; interrupts = <6>; clocks = <&clks IMX5_CLK_SDMA_GATE>, - <&clks IMX5_CLK_SDMA_GATE>; + <&clks IMX5_CLK_AHB>; clock-names = "ipg", "ahb"; #dma-cells = <3>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin"; -- cgit From 1268d8339ca46e3a5c642b38baa1512a19378af4 Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Fri, 29 Mar 2019 13:13:10 -0500 Subject: ARM: dts: mx6qdl-zii-rdu2: Use new CODEC reset pin name The correct DT property for specifying a GPIO used for reset is "reset-gpios", the driver now accepts this name, use it here. Note the GPIO polarity in the driver was ignored before and always assumed to be active low, when all the DTs are fixed we will start respecting the specified polarity. Switch polarity in DT to the currently assumed one, this way when the driver changes the behavior will not change. Signed-off-by: Andrew F. Davis Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi index 9f664897bf4e..7fa989ec403b 100644 --- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi @@ -385,7 +385,7 @@ AVDD-supply = <®_3p3v>; IOVDD-supply = <®_3p3v>; DVDD-supply = <&vgen4_reg>; - gpio-reset = <&gpio1 2 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; }; accel@1c { @@ -578,7 +578,7 @@ AVDD-supply = <®_3p3v>; IOVDD-supply = <®_3p3v>; DVDD-supply = <&vgen4_reg>; - gpio-reset = <&gpio1 0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; }; touchscreen@20 { -- cgit From c83bbdc227138d6fdc3ddfa8f7396d8f2b631ecf Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Fri, 29 Mar 2019 13:13:11 -0500 Subject: ARM: dts: imx6qdl-gw5903: Use new CODEC reset pin name The correct DT property for specifying a GPIO used for reset is "reset-gpios", the driver now accepts this name, use it here. Signed-off-by: Andrew F. Davis Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-gw5903.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl-gw5903.dtsi b/arch/arm/boot/dts/imx6qdl-gw5903.dtsi index 9cb9a7439121..aee9221f0f29 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5903.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5903.dtsi @@ -311,7 +311,7 @@ tlv320aic3105: codec@18 { compatible = "ti,tlv320aic3x"; reg = <0x18>; - gpio-reset = <&gpio5 17 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; clocks = <&clks IMX6QDL_CLK_CKO>; ai3x-micbias-vg = <2>; /* MICBIAS_2_5V */ /* Regulators */ -- cgit From cadb32a9c118a1443a95c7a0bbec086b773a0f32 Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Fri, 29 Mar 2019 13:13:12 -0500 Subject: ARM: dts: imx6qdl-var-dart: Use new CODEC reset pin name The correct DT property for specifying a GPIO used for reset is "reset-gpios", the driver now accepts this name, use it here. Signed-off-by: Andrew F. Davis Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-var-dart.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl-var-dart.dtsi b/arch/arm/boot/dts/imx6qdl-var-dart.dtsi index 8752a4961c47..c41cac502bac 100644 --- a/arch/arm/boot/dts/imx6qdl-var-dart.dtsi +++ b/arch/arm/boot/dts/imx6qdl-var-dart.dtsi @@ -183,7 +183,7 @@ IOVDD-supply = <®_3p3v>; DVDD-supply = <®_3p3v>; ai3x-ocmv = <0>; - gpio-reset = <&gpio5 5 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; }; }; -- cgit From 891d940aef2f98ba043c6e63008a99dbdf68bdc6 Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Sun, 31 Mar 2019 21:16:02 +0200 Subject: ARM: dts: imx50: Add Kobo Aura DTS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Kobo Aura is an e-book reader released in 2013. With the devicetree in its current state, the kernel will boot and run for about ten seconds. To solve this, the embedded controller needs to be told that the system should stay powered on. This will be done in a later patchset. - The IOMUXC mode bits for the SD interfaces were taken from the vendor's U-Boot fork. - The bus width of the eMMC is 4 bits in the vendor kernel, but I achieved better performance with 8 bits. - The SDIO clock frequency for the WiFi chip is 25MHz in the vendor kernel, but the WiFi chip (BCM43362) supports 50MHz, which works reliably on this board and gives slightly better performance. - The I2C pins' IOMUXC settings come from the vendor's U-Boot fork. Signed-off-by: Jonathan Neuschäfer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/imx50-kobo-aura.dts | 258 ++++++++++++++++++++++++++++++++++ 2 files changed, 260 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/imx50-kobo-aura.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index c6eec98bc3c2..7776f97c4497 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -363,7 +363,8 @@ dtb-$(CONFIG_SOC_IMX35) += \ imx35-eukrea-mbimxsd35-baseboard.dtb \ imx35-pdk.dtb dtb-$(CONFIG_SOC_IMX50) += \ - imx50-evk.dtb + imx50-evk.dtb \ + imx50-kobo-aura.dtb dtb-$(CONFIG_SOC_IMX51) += \ imx51-apf51.dtb \ imx51-apf51dev.dtb \ diff --git a/arch/arm/boot/dts/imx50-kobo-aura.dts b/arch/arm/boot/dts/imx50-kobo-aura.dts new file mode 100644 index 000000000000..a0eaf869b913 --- /dev/null +++ b/arch/arm/boot/dts/imx50-kobo-aura.dts @@ -0,0 +1,258 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright 2019 Jonathan Neuschäfer +// +// The Kobo Aura e-book reader, model N514. The mainboard is marked as E606F0B. + +/dts-v1/; +#include "imx50.dtsi" +#include + +/ { + model = "Kobo Aura (N514)"; + compatible = "kobo,aura", "fsl,imx50"; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + memory@70000000 { + device_type = "memory"; + reg = <0x70000000 0x10000000>; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + on { + label = "kobo_aura:orange:on"; + gpios = <&gpio6 24 GPIO_ACTIVE_LOW>; + panic-indicator; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys>; + + power { + label = "Power Button"; + gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + hallsensor { + label = "Hallsensor"; + gpios = <&gpio5 15 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + }; + + frontlight { + label = "Frontlight"; + gpios = <&gpio4 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + sd2_pwrseq: pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd2_reset>; + reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + }; + + sd2_vmmc: gpio-regulator { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd2_vmmc>; + regulator-name = "vmmc"; + states = <3300000 0>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-gpio = <&gpio4 12 GPIO_ACTIVE_LOW>; + startup-delay-us = <100000>; + }; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd1>; + max-frequency = <50000000>; + bus-width = <4>; + cd-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; + disable-wp; + status = "okay"; + + /* External µSD card */ +}; + +&esdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd2>; + bus-width = <4>; + max-frequency = <50000000>; + disable-wp; + mmc-pwrseq = <&sd2_pwrseq>; + vmmc-supply = <&sd2_vmmc>; + status = "okay"; + + /* CyberTan WC121 SDIO WiFi (BCM43362) */ +}; + +&esdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd3>; + bus-width = <8>; + non-removable; + max-frequency = <50000000>; + disable-wp; + status = "okay"; + + /* Internal eMMC */ +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + /* TODO: ektf2132 touch controller at 0x15 */ +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + /* TODO: TPS65185 PMIC for E Ink at 0x68 */ +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + /* TODO: embedded controller at 0x43 */ +}; + +&iomuxc { + pinctrl_gpiokeys: gpiokeys { + fsl,pins = < + MX50_PAD_CSPI_MISO__GPIO4_10 0x0 + MX50_PAD_SD2_D7__GPIO5_15 0x0 + MX50_PAD_KEY_ROW0__GPIO4_1 0x0 + >; + }; + + pinctrl_i2c1: i2c1 { + fsl,pins = < + MX50_PAD_I2C1_SCL__I2C1_SCL 0x400001fd + MX50_PAD_I2C1_SDA__I2C1_SDA 0x400001fd + >; + }; + + pinctrl_i2c2: i2c2 { + fsl,pins = < + MX50_PAD_I2C2_SCL__I2C2_SCL 0x400001fd + MX50_PAD_I2C2_SDA__I2C2_SDA 0x400001fd + >; + }; + + pinctrl_i2c3: i2c3 { + fsl,pins = < + MX50_PAD_I2C3_SCL__I2C3_SCL 0x400001fd + MX50_PAD_I2C3_SDA__I2C3_SDA 0x400001fd + >; + }; + + pinctrl_leds: leds { + fsl,pins = < + MX50_PAD_PWM1__GPIO6_24 0x0 + >; + }; + + pinctrl_sd1: sd1 { + fsl,pins = < + MX50_PAD_SD1_CMD__ESDHC1_CMD 0x1e4 + MX50_PAD_SD1_CLK__ESDHC1_CLK 0xd4 + MX50_PAD_SD1_D0__ESDHC1_DAT0 0x1d4 + MX50_PAD_SD1_D1__ESDHC1_DAT1 0x1d4 + MX50_PAD_SD1_D2__ESDHC1_DAT2 0x1d4 + MX50_PAD_SD1_D3__ESDHC1_DAT3 0x1d4 + + MX50_PAD_SD2_CD__GPIO5_17 0x0 + >; + }; + + pinctrl_sd2: sd2 { + fsl,pins = < + MX50_PAD_SD2_CMD__ESDHC2_CMD 0x1e4 + MX50_PAD_SD2_CLK__ESDHC2_CLK 0xd4 + MX50_PAD_SD2_D0__ESDHC2_DAT0 0x1d4 + MX50_PAD_SD2_D1__ESDHC2_DAT1 0x1d4 + MX50_PAD_SD2_D2__ESDHC2_DAT2 0x1d4 + MX50_PAD_SD2_D3__ESDHC2_DAT3 0x1d4 + >; + }; + + pinctrl_sd2_reset: sd2-reset { + fsl,pins = < + MX50_PAD_ECSPI2_MOSI__GPIO4_17 0x0 + >; + }; + + pinctrl_sd2_vmmc: sd2-vmmc { + fsl,pins = < + MX50_PAD_ECSPI1_SCLK__GPIO4_12 0x0 + >; + }; + + pinctrl_sd3: sd3 { + fsl,pins = < + MX50_PAD_SD3_CMD__ESDHC3_CMD 0x1e4 + MX50_PAD_SD3_CLK__ESDHC3_CLK 0xd4 + MX50_PAD_SD3_D0__ESDHC3_DAT0 0x1d4 + MX50_PAD_SD3_D1__ESDHC3_DAT1 0x1d4 + MX50_PAD_SD3_D2__ESDHC3_DAT2 0x1d4 + MX50_PAD_SD3_D3__ESDHC3_DAT3 0x1d4 + MX50_PAD_SD3_D4__ESDHC3_DAT4 0x1d4 + MX50_PAD_SD3_D5__ESDHC3_DAT5 0x1d4 + MX50_PAD_SD3_D6__ESDHC3_DAT6 0x1d4 + MX50_PAD_SD3_D7__ESDHC3_DAT7 0x1d4 + >; + }; + + pinctrl_uart2: uart2 { + fsl,pins = < + MX50_PAD_UART2_TXD__UART2_TXD_MUX 0x1e4 + MX50_PAD_UART2_RXD__UART2_RXD_MUX 0x1e4 + >; + }; + + pinctrl_usbphy: usbphy { + fsl,pins = < + MX50_PAD_ECSPI2_SS0__GPIO4_19 0x0 + >; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbotg { + phy_type = "utmi_wide"; + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbphy>; + vbus-detect-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>; +}; -- cgit From 4b08ecc7c68525e6e472a3e10ca1ba00e0facb26 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Mon, 1 Apr 2019 02:51:11 +0000 Subject: ARM: dts: imx6sll: add cooling-cells for cpu-freq cooling device Add #cooling-cells for i.MX6SLL cpu-freq cooling device usage. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sll.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi index ed598d72038c..1b4899f0fcde 100644 --- a/arch/arm/boot/dts/imx6sll.dtsi +++ b/arch/arm/boot/dts/imx6sll.dtsi @@ -64,6 +64,7 @@ 198000 1175000 >; clock-latency = <61036>; /* two CLK32 periods */ + #cooling-cells = <2>; clocks = <&clks IMX6SLL_CLK_ARM>, <&clks IMX6SLL_CLK_PLL2_PFD2>, <&clks IMX6SLL_CLK_STEP>, -- cgit From 45d91250405b08a13c41d879eb70d71f22773032 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 2 Apr 2019 14:25:45 -0500 Subject: ARM: dts: imx6q-logicpd: Enable Analog audio capture The original submission had functional audio out and was based on reviewing other boards using the same wm8962 codec. However, the Logic PD board uses an analog microphone which was being disabled for a digital mic. This patch corrects that and explicitly sets the gpio-cfg pins all to 0x0000 which allows the analog microphone to capture audio. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi b/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi index fb01fa6e4224..12b18c801b98 100644 --- a/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi +++ b/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi @@ -247,9 +247,9 @@ gpio-cfg = < 0x0000 /* 0:Default */ 0x0000 /* 1:Default */ - 0x0013 /* 2:FN_DMICCLK */ + 0x0000 /* 2:FN_DMICCLK */ 0x0000 /* 3:Default */ - 0x8014 /* 4:FN_DMICCDAT */ + 0x0000 /* 4:FN_DMICCDAT */ 0x0000 /* 5:Default */ >; }; -- cgit From 6fd6d6f6a2f06cb921a0185072854c3d35d86ff1 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 2 Apr 2019 14:25:46 -0500 Subject: ARM: dts: imx6q-logicpd: Shutdown LCD regulator during suspend The LCD power sequencer is very finicky. The backlight cannot be driven until after the sequencer is done. Until now, the regulators were marked with 'regulator-always-on' to make sure it came up before the backlight. This patch allows the LCD regulators to power down and prevent the backlight from being used again until the sequencer is ready. This reduces standby power consumption by ~100mW. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-logicpd.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6q-logicpd.dts b/arch/arm/boot/dts/imx6q-logicpd.dts index 45eb0b7f75f8..d96ae54be338 100644 --- a/arch/arm/boot/dts/imx6q-logicpd.dts +++ b/arch/arm/boot/dts/imx6q-logicpd.dts @@ -21,6 +21,8 @@ panel-lvds0 { compatible = "okaya,rs800480t-7x0gp"; + power-supply = <®_lcd_reset>; + backlight = <&backlight>; port { panel_in_lvds0: endpoint { @@ -38,7 +40,6 @@ regulator-max-microvolt = <3300000>; gpio = <&gpio4 17 GPIO_ACTIVE_HIGH>; enable-active-high; - regulator-always-on; vin-supply = <®_3v3>; startup-delay-us = <500000>; }; @@ -52,7 +53,6 @@ regulator-max-microvolt = <3300000>; gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; enable-active-high; - regulator-always-on; vin-supply = <®_lcd>; }; }; -- cgit From 7ee137a96a880ba303684eacc9a4f7a22836b184 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 3 Apr 2019 09:53:13 -0300 Subject: ARM: dts: imx: Switch Zii dts to SPDX identifier Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-zii-rdu1.dts | 38 +--------------------------- arch/arm/boot/dts/imx6q-zii-rdu2.dts | 38 +--------------------------- arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi | 38 +--------------------------- arch/arm/boot/dts/imx6qp-zii-rdu2.dts | 38 +--------------------------- arch/arm/boot/dts/vf610-zii-dev-rev-b.dts | 41 +------------------------------ arch/arm/boot/dts/vf610-zii-dev-rev-c.dts | 41 +------------------------------ 6 files changed, 6 insertions(+), 228 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts index a8220f08dcbf..3596060f52e7 100644 --- a/arch/arm/boot/dts/imx51-zii-rdu1.dts +++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Copyright (C) 2017 Zodiac Inflight Innovations - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6q-zii-rdu2.dts b/arch/arm/boot/dts/imx6q-zii-rdu2.dts index 0f0743db2779..a1c5e69d81ba 100644 --- a/arch/arm/boot/dts/imx6q-zii-rdu2.dts +++ b/arch/arm/boot/dts/imx6q-zii-rdu2.dts @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Copyright (C) 2016-2017 Zodiac Inflight Innovations - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi index 7fa989ec403b..93be00a60c88 100644 --- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Copyright (C) 2016-2017 Zodiac Inflight Innovations - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include diff --git a/arch/arm/boot/dts/imx6qp-zii-rdu2.dts b/arch/arm/boot/dts/imx6qp-zii-rdu2.dts index 98bf7a6b2850..57de447c4609 100644 --- a/arch/arm/boot/dts/imx6qp-zii-rdu2.dts +++ b/arch/arm/boot/dts/imx6qp-zii-rdu2.dts @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Copyright (C) 2016-2017 Zodiac Inflight Innovations - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts index bd79e00bf615..38a394449ee5 100644 --- a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts +++ b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts @@ -1,45 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Copyright (C) 2015, 2016 Zodiac Inflight Innovations - * - * Based on an original 'vf610-twr.dts' which is Copyright 2015, - * Freescale Semiconductor, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts index 6f4a5602cefd..fe111f742ec2 100644 --- a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts +++ b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts @@ -1,45 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Copyright (C) 2015, 2016 Zodiac Inflight Innovations - * - * Based on an original 'vf610-twr.dts' which is Copyright 2015, - * Freescale Semiconductor, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; -- cgit From 00e3ff8b980b7604dcaa6ea8b2fb157ff8d16c30 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 3 Apr 2019 09:53:14 -0300 Subject: ARM: dts: imx: Use generic node names for Zii dts The devicetree specification recommends using generic node names. Some Zii dts files already follow such recommendation, but some don't, so use generic node names for consistency among the Zii dts files. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-zii-cfu1.dts | 8 ++++---- arch/arm/boot/dts/vf610-zii-dev-rev-b.dts | 14 +++++++------- arch/arm/boot/dts/vf610-zii-dev-rev-c.dts | 8 ++++---- arch/arm/boot/dts/vf610-zii-dev.dtsi | 4 ++-- arch/arm/boot/dts/vf610-zii-scu4-aib.dts | 10 +++++----- arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts | 8 ++++---- 6 files changed, 26 insertions(+), 26 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/vf610-zii-cfu1.dts b/arch/arm/boot/dts/vf610-zii-cfu1.dts index afc25b33bd3b..9466913693ac 100644 --- a/arch/arm/boot/dts/vf610-zii-cfu1.dts +++ b/arch/arm/boot/dts/vf610-zii-cfu1.dts @@ -94,7 +94,7 @@ */ status = "disabled"; - m25p128@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p128", "jedec,spi-nor"; @@ -212,7 +212,7 @@ pinctrl-0 = <&pinctrl_i2c0>; status = "okay"; - pca9554@22 { + io-expander@22 { compatible = "nxp,pca9554"; reg = <0x22>; gpio-controller; @@ -223,13 +223,13 @@ reg = <0x48>; }; - at24c04@52 { + eeprom@52 { compatible = "atmel,24c04"; reg = <0x52>; label = "nvm"; }; - at24c04@54 { + eeprom@54 { compatible = "atmel,24c04"; reg = <0x54>; label = "nameplate"; diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts index 38a394449ee5..8b0baf6a4098 100644 --- a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts +++ b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts @@ -299,7 +299,7 @@ &gpio1 8 GPIO_ACTIVE_HIGH>; num-chipselects = <2>; - m25p128@0 { + flash@0 { compatible = "m25p128", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; @@ -328,7 +328,7 @@ pinctrl-0 = <&pinctrl_i2c0>; status = "okay"; - gpio5: pca9554@20 { + gpio5: io-expander@20 { compatible = "nxp,pca9554"; reg = <0x20>; gpio-controller; @@ -336,7 +336,7 @@ }; - gpio6: pca9554@22 { + gpio6: io-expander@22 { compatible = "nxp,pca9554"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pca9554_22>; @@ -369,7 +369,7 @@ #size-cells = <0>; reg = <0>; - sfp1: at24c04@50 { + sfp1: eeprom@50 { compatible = "atmel,24c02"; reg = <0x50>; }; @@ -380,7 +380,7 @@ #size-cells = <0>; reg = <1>; - sfp2: at24c04@50 { + sfp2: eeprom@50 { compatible = "atmel,24c02"; reg = <0x50>; }; @@ -391,7 +391,7 @@ #size-cells = <0>; reg = <2>; - sfp3: at24c04@50 { + sfp3: eeprom@50 { compatible = "atmel,24c02"; reg = <0x50>; }; @@ -402,7 +402,7 @@ #size-cells = <0>; reg = <3>; - sfp4: at24c04@50 { + sfp4: eeprom@50 { compatible = "atmel,24c02"; reg = <0x50>; }; diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts index fe111f742ec2..778e02c000d1 100644 --- a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts +++ b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts @@ -238,7 +238,7 @@ status = "okay"; spi-num-chipselects = <2>; - m25p128@0 { + flash@0 { compatible = "m25p128", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; @@ -274,7 +274,7 @@ * P1 - WE2_CMD * P2 - WE2_CLK */ - gpio5: pca9557@18 { + gpio5: io-expander@18 { compatible = "nxp,pca9557"; reg = <0x18>; gpio-controller; @@ -322,7 +322,7 @@ * IO0 - WE1_CLK * IO1 - WE1_CMD */ - gpio7: pca9554@22 { + gpio7: io-expander@22 { compatible = "nxp,pca9554"; reg = <0x22>; gpio-controller; @@ -332,7 +332,7 @@ }; &i2c1 { - at24mac602@50 { + eeprom@50 { compatible = "atmel,24c02"; reg = <0x50>; read-only; diff --git a/arch/arm/boot/dts/vf610-zii-dev.dtsi b/arch/arm/boot/dts/vf610-zii-dev.dtsi index 19eb4a849efb..36bbb8a9f4d8 100644 --- a/arch/arm/boot/dts/vf610-zii-dev.dtsi +++ b/arch/arm/boot/dts/vf610-zii-dev.dtsi @@ -147,12 +147,12 @@ reg = <0x48>; }; - at24c04@50 { + eeprom@50 { compatible = "atmel,24c04"; reg = <0x50>; }; - at24c04@52 { + eeprom@52 { compatible = "atmel,24c04"; reg = <0x52>; }; diff --git a/arch/arm/boot/dts/vf610-zii-scu4-aib.dts b/arch/arm/boot/dts/vf610-zii-scu4-aib.dts index e3952e9ea0db..d7019e89f588 100644 --- a/arch/arm/boot/dts/vf610-zii-scu4-aib.dts +++ b/arch/arm/boot/dts/vf610-zii-scu4-aib.dts @@ -505,14 +505,14 @@ pinctrl-0 = <&pinctrl_i2c0>; status = "okay"; - gpio5: pca9554@20 { + gpio5: io-expander@20 { compatible = "nxp,pca9554"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; }; - gpio6: pca9554@22 { + gpio6: io-expander@22 { compatible = "nxp,pca9554"; reg = <0x22>; gpio-controller; @@ -524,12 +524,12 @@ reg = <0x48>; }; - at24c04@50 { + eeprom@50 { compatible = "atmel,24c04"; reg = <0x50>; }; - at24c04@52 { + eeprom@52 { compatible = "atmel,24c04"; reg = <0x52>; }; @@ -577,7 +577,7 @@ reg = <0x4f>; }; - gpio7: pca9555@23 { + gpio7: io-expander@23 { compatible = "nxp,pca9555"; gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts index 8366bae632d6..453fce80f858 100644 --- a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts +++ b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts @@ -69,7 +69,7 @@ */ status = "disabled"; - m25p128@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p128", "jedec,spi-nor"; @@ -194,7 +194,7 @@ pinctrl-0 = <&pinctrl_i2c0>; status = "okay"; - gpio6: pca9505@22 { + gpio6: io-expander@22 { compatible = "nxp,pca9554"; reg = <0x22>; gpio-controller; @@ -206,13 +206,13 @@ reg = <0x48>; }; - at24c04@50 { + eeprom@50 { compatible = "atmel,24c04"; reg = <0x50>; label = "nameplate"; }; - at24c04@52 { + eeprom@52 { compatible = "atmel,24c04"; reg = <0x52>; }; -- cgit From 35dc29ef0f5de174537ddeb0f202adb8e99e2ea6 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Mon, 8 Apr 2019 07:44:21 +0000 Subject: ARM: dts: imx6dl-sabreauto: update opp table for auto part Update i.MX6DL automotive part's opp table according to i.MX6DL automotive datasheet Rev.9, 11/2018, it adds 996MHz set-point support as below: LDO enabled(min value): 996MHz: VDDARM: 1.275V, VDDSOC: 1.175V; 792MHz: VDDARM: 1.150V, VDDSOC: 1.150V; 396MHz: VDDARM: 1.125V, VDDSOC: 1.150V; Adding 25mV to cover board IR drop, for LDO enabled mode of 996MHz, as the max value of LDO output can NOT exceed 1.3V, so 25mV is NOT added for VDDARM. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-sabreauto.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6dl-sabreauto.dts b/arch/arm/boot/dts/imx6dl-sabreauto.dts index 660d52a245ba..ff3283c83a39 100644 --- a/arch/arm/boot/dts/imx6dl-sabreauto.dts +++ b/arch/arm/boot/dts/imx6dl-sabreauto.dts @@ -11,3 +11,18 @@ model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board"; compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl"; }; + +&cpu0 { + operating-points = < + /* kHz uV */ + 996000 1275000 + 792000 1175000 + 396000 1150000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1200000 + 792000 1175000 + 396000 1175000 + >; +}; -- cgit From 61c0f6b8b42d37407cb55594a7883da6a53f70ac Mon Sep 17 00:00:00 2001 From: Ludovic Barre Date: Fri, 1 Mar 2019 09:47:00 +0100 Subject: ARM: dts: stm32: add sdmmc1 support on stm32h743 This patch adds support of sdmmc1 on stm32h743. Signed-off-by: Ludovic Barre Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32h743.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi index 5cac79ebebb1..c065266ee377 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/stm32h743.dtsi @@ -339,6 +339,20 @@ dma-requests = <32>; }; + sdmmc1: sdmmc@52007000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x10153180>; + reg = <0x52007000 0x1000>; + interrupts = <49>; + interrupt-names = "cmd_irq"; + clocks = <&rcc SDMMC1_CK>; + clock-names = "apb_pclk"; + resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <120000000>; + }; + exti: interrupt-controller@58000000 { compatible = "st,stm32h7-exti"; interrupt-controller; -- cgit From 90f16fea400ba7b145e15ed601adceb501d5054f Mon Sep 17 00:00:00 2001 From: Ludovic Barre Date: Fri, 1 Mar 2019 09:47:00 +0100 Subject: ARM: dts: stm32: add sdmmc1 support on stm32h743i eval board This patch adds sdmmc1 support on stm32h743i eval board. This board has an external driver to control signal direction polarity. Signed-off-by: Ludovic Barre Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32h743-pinctrl.dtsi | 68 ++++++++++++++++++++++++++++++++ arch/arm/boot/dts/stm32h743i-eval.dts | 23 ++++++++++- 2 files changed, 90 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi index 980b2769caf9..e44e7baa3f17 100644 --- a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi @@ -188,6 +188,74 @@ }; }; + sdmmc1_b4_pins_a: sdmmc1-b4-0 { + pins { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + , /* SDMMC1_CK */ + ; /* SDMMC1_CMD */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { + pins1 { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + ; /* SDMMC1_CK */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + pins2{ + pinmux = ; /* SDMMC1_CMD */ + slew-rate = <3>; + drive-open-drain; + bias-disable; + }; + }; + + sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { + pins { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + , /* SDMMC1_CK */ + ; /* SDMMC1_CMD */ + }; + }; + + sdmmc1_dir_pins_a: sdmmc1-dir-0 { + pins1 { + pinmux = , /* SDMMC1_D0DIR */ + , /* SDMMC1_D123DIR */ + ; /* SDMMC1_CDIR */ + slew-rate = <3>; + drive-push-pull; + bias-pull-up; + }; + pins2{ + pinmux = ; /* SDMMC1_CKIN */ + bias-pull-up; + }; + }; + + sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { + pins { + pinmux = , /* SDMMC1_D0DIR */ + , /* SDMMC1_D123DIR */ + , /* SDMMC1_CDIR */ + ; /* SDMMC1_CKIN */ + }; + }; + usart1_pins: usart1@0 { pins1 { pinmux = ; /* USART1_TX */ diff --git a/arch/arm/boot/dts/stm32h743i-eval.dts b/arch/arm/boot/dts/stm32h743i-eval.dts index ebc3f0933f5c..ab78ad532375 100644 --- a/arch/arm/boot/dts/stm32h743i-eval.dts +++ b/arch/arm/boot/dts/stm32h743i-eval.dts @@ -70,13 +70,20 @@ regulator-always-on; }; + v2v9_sd: regulator-v2v9_sd { + compatible = "regulator-fixed"; + regulator-name = "v2v9_sd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + }; + usbotg_hs_phy: usb-phy { #phy-cells = <0>; compatible = "usb-nop-xceiv"; clocks = <&rcc USB1ULPI_CK>; clock-names = "main_clk"; }; - }; &adc_12 { @@ -122,6 +129,20 @@ }; }; +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>; + broken-cd; + st,sig-dir; + st,neg-edge; + st,use-ckin; + bus-width = <4>; + vmmc-supply = <&v2v9_sd>; + status = "okay"; +}; + &usart1 { pinctrl-0 = <&usart1_pins>; pinctrl-names = "default"; -- cgit From 30a8e03a1f71ec0bd0208944fac10f7e0433fe3a Mon Sep 17 00:00:00 2001 From: Ludovic Barre Date: Fri, 1 Mar 2019 09:47:00 +0100 Subject: ARM: dts: stm32: add sdmmc1 support on stm32h743i disco board This patch adds sdmmc1 support on stm32h743i disco board. Signed-off-by: Ludovic Barre Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32h743i-disco.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32h743i-disco.dts b/arch/arm/boot/dts/stm32h743i-disco.dts index dd06c8f3d09a..3acd2e9c434e 100644 --- a/arch/arm/boot/dts/stm32h743i-disco.dts +++ b/arch/arm/boot/dts/stm32h743i-disco.dts @@ -61,6 +61,14 @@ aliases { serial0 = &usart2; }; + + v3v3: regulator-v3v3 { + compatible = "regulator-fixed"; + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; }; &clk_hse { @@ -84,6 +92,18 @@ }; }; +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + broken-cd; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + &usart2 { pinctrl-0 = <&usart2_pins>; pinctrl-names = "default"; -- cgit From 8d17cf7a8e8b1ed3e979b1740401e72150fca5e9 Mon Sep 17 00:00:00 2001 From: Ludovic Barre Date: Fri, 1 Mar 2019 09:47:00 +0100 Subject: ARM: dts: stm32: add sdmmc1 support on stm32mp157c This patch adds support of sdmmc1 on stm32mp157c. Signed-off-by: Ludovic Barre Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index f8bbfff5950b..667f5606268b 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -1050,6 +1050,20 @@ status = "disabled"; }; + sdmmc1: sdmmc@58005000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x10153180>; + reg = <0x58005000 0x1000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&rcc SDMMC1_K>; + clock-names = "apb_pclk"; + resets = <&rcc SDMMC1_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <120000000>; + }; + crc1: crc@58009000 { compatible = "st,stm32f7-crc"; reg = <0x58009000 0x400>; -- cgit From 379edbe434e787a40b757ebe371c779c69fc1038 Mon Sep 17 00:00:00 2001 From: Ludovic Barre Date: Tue, 26 Mar 2019 12:01:52 +0100 Subject: ARM: dts: stm32: add sdmmc1 support on stm32mp157c ed1 board This patch adds sdmmc1 support on stm32mp157c ed1 board. Signed-off-by: Ludovic Barre Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 68 +++++++++++++++++++++++++++++++ arch/arm/boot/dts/stm32mp157c-ed1.dts | 37 +++++++++++++++++ 2 files changed, 105 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi index 9ec4694e93a7..9104896e6066 100644 --- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi @@ -325,6 +325,74 @@ }; }; + sdmmc1_b4_pins_a: sdmmc1-b4-0 { + pins { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + , /* SDMMC1_CK */ + ; /* SDMMC1_CMD */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { + pins1 { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + ; /* SDMMC1_CK */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + pins2{ + pinmux = ; /* SDMMC1_CMD */ + slew-rate = <3>; + drive-open-drain; + bias-disable; + }; + }; + + sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { + pins { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + , /* SDMMC1_CK */ + ; /* SDMMC1_CMD */ + }; + }; + + sdmmc1_dir_pins_a: sdmmc1-dir-0 { + pins1 { + pinmux = , /* SDMMC1_D0DIR */ + , /* SDMMC1_D123DIR */ + ; /* SDMMC1_CDIR */ + slew-rate = <3>; + drive-push-pull; + bias-pull-up; + }; + pins2{ + pinmux = ; /* SDMMC1_CKIN */ + bias-pull-up; + }; + }; + + sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { + pins { + pinmux = , /* SDMMC1_D0DIR */ + , /* SDMMC1_D123DIR */ + , /* SDMMC1_CDIR */ + ; /* SDMMC1_CKIN */ + }; + }; + uart4_pins_a: uart4-0 { pins1 { pinmux = ; /* UART4_TX */ diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index d66edb0c66cd..7f4b828d7931 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -7,6 +7,7 @@ #include "stm32mp157c.dtsi" #include "stm32mp157-pinctrl.dtsi" +#include / { model = "STMicroelectronics STM32MP157C eval daughter"; @@ -41,6 +42,14 @@ regulator-always-on; }; + vdd_sd: regulator-vdd_sd { + compatible = "regulator-fixed"; + regulator-name = "vdd_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + vdd_usb: vdd-usb { compatible = "regulator-fixed"; regulator-name = "vdd_usb"; @@ -48,6 +57,19 @@ regulator-max-microvolt = <3300000>; regulator-always-on; }; + + sd_switch: regulator-sd_switch { + compatible = "regulator-gpio"; + regulator-name = "sd_switch"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-type = "voltage"; + regulator-always-on; + + gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + states = <1800000 0x1 2900000 0x0>; + }; }; &dts { @@ -75,6 +97,21 @@ status = "okay"; }; +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>; + broken-cd; + st,sig-dir; + st,neg-edge; + st,use-ckin; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + vqmmc-supply = <&sd_switch>; + status = "okay"; +}; + &timers6 { status = "okay"; /* spare dmas for other usage */ -- cgit From 8f6e0919b7c21400c60693b31e659eb3f6e5179d Mon Sep 17 00:00:00 2001 From: Ludovic Barre Date: Fri, 1 Mar 2019 09:47:00 +0100 Subject: ARM: dts: stm32: add sdmmc1 support on stm32mp157a dk1 board This patch adds sdmmc1 support on stm32mp157a dk1 board. Signed-off-by: Ludovic Barre Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157a-dk1.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157a-dk1.dts b/arch/arm/boot/dts/stm32mp157a-dk1.dts index 873a80ef2b71..e774a34ec4fd 100644 --- a/arch/arm/boot/dts/stm32mp157a-dk1.dts +++ b/arch/arm/boot/dts/stm32mp157a-dk1.dts @@ -36,6 +36,14 @@ default-state = "off"; }; }; + + v3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; }; ðernet0 { @@ -70,6 +78,18 @@ status = "okay"; }; +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + broken-cd; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_a>; -- cgit From eb2493172f723ec902a4c951caa90422ec1458ff Mon Sep 17 00:00:00 2001 From: Fabien Dessenne Date: Fri, 1 Mar 2019 10:18:00 +0100 Subject: ARM: dts: stm32: add IPCC mailbox support on STM32MP157c Add configuration on DT for IPCC mailbox driver. Signed-off-by: Fabien Dessenne Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index 667f5606268b..40d0b42ca1c6 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -886,6 +886,21 @@ status = "disabled"; }; + ipcc: mailbox@4c001000 { + compatible = "st,stm32mp1-ipcc"; + #mbox-cells = <1>; + reg = <0x4c001000 0x400>; + st,proc-id = <0>; + interrupts-extended = + <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <&exti 61 1>; + interrupt-names = "rx", "tx", "wakeup"; + clocks = <&rcc IPCC>; + wakeup-source; + status = "disabled"; + }; + rcc: rcc@50000000 { compatible = "st,stm32mp1-rcc", "syscon"; reg = <0x50000000 0x1000>; -- cgit From 679d9dac52203bbbbee5ca22bf9bfe8ce2ef2a0b Mon Sep 17 00:00:00 2001 From: Fabien Dessenne Date: Fri, 1 Mar 2019 10:18:00 +0100 Subject: ARM: dts: stm32: enable IPCC mailbox support on STM32MP157c-ed1 Enable STM32 IPCC mailbox driver for STM32MP157c-ed1 board. Signed-off-by: Fabien Dessenne Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-ed1.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index 7f4b828d7931..9fd79432798b 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -84,6 +84,10 @@ status = "okay"; }; +&ipcc { + status = "okay"; +}; + &iwdg2 { timeout-sec = <32>; status = "okay"; -- cgit From 682d099514d8f14538da0d9b99732e4cebc5f2d3 Mon Sep 17 00:00:00 2001 From: Fabien Dessenne Date: Fri, 1 Mar 2019 10:18:00 +0100 Subject: ARM: dts: stm32: enable IPCC mailbox support on STM32MP157a-dk1 Enable STM32 IPCC mailbox driver for STM32MP157a-dk1 board. Signed-off-by: Fabien Dessenne Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157a-dk1.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157a-dk1.dts b/arch/arm/boot/dts/stm32mp157a-dk1.dts index e774a34ec4fd..1b1886d6affa 100644 --- a/arch/arm/boot/dts/stm32mp157a-dk1.dts +++ b/arch/arm/boot/dts/stm32mp157a-dk1.dts @@ -65,6 +65,10 @@ }; }; +&ipcc { + status = "okay"; +}; + &iwdg2 { timeout-sec = <32>; status = "okay"; -- cgit From 0f5795069596333493b372fcd0248c45f4152775 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Wed, 12 Dec 2018 09:48:00 +0100 Subject: ARM: dts: stm32: Add clock on stm32mp157c syscfg STM32 syscfg needs a clock to access registers. Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index 40d0b42ca1c6..8b6a140126bb 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -918,6 +918,7 @@ syscfg: syscon@50020000 { compatible = "st,stm32mp157-syscfg", "syscon"; reg = <0x50020000 0x400>; + clocks = <&rcc SYSCFG>; }; lptimer2: timer@50021000 { -- cgit From 3024c18543eaf7c808a826769979b6c44cfeb07e Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Thu, 28 Feb 2019 11:19:00 +0100 Subject: ARM: dts: stm32: Add romem and temperature calibration on stm32mp157c Add & enable stm32 factory-programmed memory. Describe temperature sensor calibration cells. Non-volatile calibration data is made available by stm32mp157c bootrom in bsec_dataX registers. Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index 8b6a140126bb..6ce75f696679 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -1229,6 +1229,19 @@ status = "disabled"; }; + bsec: nvmem@5c005000 { + compatible = "st,stm32mp15-bsec"; + reg = <0x5c005000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ts_cal1: calib@5c { + reg = <0x5c 0x2>; + }; + ts_cal2: calib@5e { + reg = <0x5e 0x2>; + }; + }; + i2c6: i2c@5c009000 { compatible = "st,stm32f7-i2c"; reg = <0x5c009000 0x400>; -- cgit From 8d07b78c3e2e8f42b72b7a1b2e0032e494b92ffe Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Thu, 28 Feb 2019 11:19:00 +0100 Subject: ARM: dts: stm32: Add romem and temperature calibration on stm32f429 Add & enable stm32 factory-programmed memory. Describe temperature sensor calibration cells. Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32f429.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index 588b6ef94e93..4a4954492ed1 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -80,6 +80,19 @@ }; soc { + romem: nvmem@1fff7800 { + compatible = "st,stm32f4-otp"; + reg = <0x1fff7800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ts_cal1: calib@22c { + reg = <0x22c 0x2>; + }; + ts_cal2: calib@22e { + reg = <0x22e 0x2>; + }; + }; + timer2: timer@40000000 { compatible = "st,stm32-timer"; reg = <0x40000000 0x400>; -- cgit From 411435d39079544d09949070518bdbed13d252b3 Mon Sep 17 00:00:00 2001 From: Olivier Moysan Date: Wed, 10 Apr 2019 14:47:52 +0200 Subject: ARM: dts: stm32: add spdifrx support on stm32mp157c This patch adds support of STM32 SPDIFRX on stm32mp157c. Signed-off-by: Olivier Moysan Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index 6ce75f696679..2afeee65c3ea 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -379,6 +379,19 @@ status = "disabled"; }; + spdifrx: audio-controller@4000d000 { + compatible = "st,stm32h7-spdifrx"; + #sound-dai-cells = <0>; + reg = <0x4000d000 0x400>; + clocks = <&rcc SPDIF_K>; + clock-names = "kclk"; + interrupts = ; + dmas = <&dmamux1 93 0x400 0x01>, + <&dmamux1 94 0x400 0x01>; + dma-names = "rx", "rx-ctrl"; + status = "disabled"; + }; + usart2: serial@4000e000 { compatible = "st,stm32h7-uart"; reg = <0x4000e000 0x400>; -- cgit From 94d3d6f4dc693c612fa7272733824e7c967c517a Mon Sep 17 00:00:00 2001 From: Olivier Moysan Date: Fri, 29 Mar 2019 11:12:00 +0100 Subject: ARM: dts: stm32: add spdfirx pins to stm32mp157c This patch adds spdifrx support on stm32mp157c eval board. Signed-off-by: Olivier Moysan Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi index 9104896e6066..54c133094a8f 100644 --- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi @@ -393,6 +393,19 @@ }; }; + spdifrx_pins_a: spdifrx-0 { + pins { + pinmux = ; /* SPDIF_IN1 */ + bias-disable; + }; + }; + + spdifrx_sleep_pins_a: spdifrx-1 { + pins { + pinmux = ; /* SPDIF_IN1 */ + }; + }; + uart4_pins_a: uart4-0 { pins1 { pinmux = ; /* UART4_TX */ -- cgit From 9c559b1565e6b2dea3e4ad1f588df3b8c566e665 Mon Sep 17 00:00:00 2001 From: Pascal Paillet Date: Tue, 9 Apr 2019 10:59:49 +0200 Subject: ARM: dts: stm32: add stpmic1 support on stm32mp157c ed1 board This patch adds stpmic1 support on stm32mp157c ed1 board. The STPMIC1 is a PMIC from STMicroelectronics. The STPMIC1 integrates 10 regulators, 3 power switches, a watchdog and an input for a power on key. The DMAs are disabled because the PMIC generates a very few traffic and DMA channels may lack for other usage. Signed-off-by: Pascal Paillet Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-ed1.dts | 156 ++++++++++++++++++++++++++++++---- 1 file changed, 140 insertions(+), 16 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index 9fd79432798b..62a8c78e7e2e 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -8,6 +8,7 @@ #include "stm32mp157c.dtsi" #include "stm32mp157-pinctrl.dtsi" #include +#include / { model = "STMicroelectronics STM32MP157C eval daughter"; @@ -42,22 +43,6 @@ regulator-always-on; }; - vdd_sd: regulator-vdd_sd { - compatible = "regulator-fixed"; - regulator-name = "vdd_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_usb: vdd-usb { - compatible = "regulator-fixed"; - regulator-name = "vdd_usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - sd_switch: regulator-sd_switch { compatible = "regulator-gpio"; regulator-name = "sd_switch"; @@ -82,6 +67,145 @@ i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + + regulators { + compatible = "st,stpmic1-regulators"; + ldo1-supply = <&v3v3>; + ldo2-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo5-supply = <&v3v3>; + ldo6-supply = <&v3v3>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + vdda: ldo1 { + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; + }; + + v2v8: ldo2 { + regulator-name = "v2v8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + interrupts = ; + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + interrupts = ; + }; + + vdd_sd: ldo5 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; + regulator-boot-on; + }; + + v1v8: ldo6 { + regulator-name = "v1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + interrupts = ; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + regulator-over-current-protection; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = ; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = ; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = ; + regulator-active-discharge; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = , ; + interrupt-names = "onkey-falling", "onkey-rising"; + power-off-time-sec = <10>; + status = "okay"; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; }; &ipcc { -- cgit From b3e993a6170c764551d31b4108ebe410eb75d41f Mon Sep 17 00:00:00 2001 From: Pascal Paillet Date: Tue, 9 Apr 2019 11:00:39 +0200 Subject: ARM: dts: stm32: add stpmic1 support on stm32mp157a dk1 board This patch adds stpmic1 support on stm32mp157a dk1 board. The STPMIC1 is a PMIC from STMicroelectronics. The STPMIC1 integrates 10 regulators, 3 power switches, a watchdog and an input for a power on key. The DMAs are disabled because the PMIC generates a very few traffic and DMA channels may lack for other usage. Signed-off-by: Pascal Paillet Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157a-dk1.dts | 158 ++++++++++++++++++++++++++++++++-- 1 file changed, 150 insertions(+), 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157a-dk1.dts b/arch/arm/boot/dts/stm32mp157a-dk1.dts index 1b1886d6affa..4bb91abcbcae 100644 --- a/arch/arm/boot/dts/stm32mp157a-dk1.dts +++ b/arch/arm/boot/dts/stm32mp157a-dk1.dts @@ -9,6 +9,7 @@ #include "stm32mp157c.dtsi" #include "stm32mp157-pinctrl.dtsi" #include +#include / { model = "STMicroelectronics STM32MP157A-DK1 Discovery Board"; @@ -36,14 +37,6 @@ default-state = "off"; }; }; - - v3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "v3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; }; ðernet0 { @@ -65,6 +58,155 @@ }; }; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + + regulators { + compatible = "st,stpmic1-regulators"; + ldo1-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo6-supply = <&v3v3>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + v1v8_audio: ldo1 { + regulator-name = "v1v8_audio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + interrupts = ; + }; + + v3v3_hdmi: ldo2 { + regulator-name = "v3v3_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + interrupts = ; + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + interrupts = ; + }; + + vdda: ldo5 { + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; + regulator-boot-on; + }; + + v1v2_hdmi: ldo6 { + regulator-name = "v1v2_hdmi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + interrupts = ; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + regulator-over-current-protection; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = ; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = ; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = ; + regulator-active-discharge; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = , ; + interrupt-names = "onkey-falling", "onkey-rising"; + power-off-time-sec = <10>; + status = "okay"; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; +}; + &ipcc { status = "okay"; }; -- cgit From 09666b76f3588055743d89de9f16d8d3c09380f8 Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Fri, 5 Apr 2019 09:53:00 +0200 Subject: ARM: dts: stm32: Enable STM32F769 clock driver This patch enables clocks for STM32F769 boards. Signed-off-by: Gabriel Fernandez Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32f769-disco.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32f769-disco.dts b/arch/arm/boot/dts/stm32f769-disco.dts index 3c7216844a9b..6f1d0ac8c31c 100644 --- a/arch/arm/boot/dts/stm32f769-disco.dts +++ b/arch/arm/boot/dts/stm32f769-disco.dts @@ -102,6 +102,10 @@ }; }; +&rcc { + compatible = "st,stm32f769-rcc", "st,stm32f746-rcc", "st,stm32-rcc"; +}; + &cec { pinctrl-0 = <&cec_pins_a>; pinctrl-names = "default"; -- cgit From 81987fff52f1a5fba8fe814029e37961aaf77ee9 Mon Sep 17 00:00:00 2001 From: Yannick Fertré Date: Wed, 10 Apr 2019 15:51:38 +0200 Subject: ARM: dts: stm32: add power supply of otm8009a on stm32mp157c-dk2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch adds a new property (power-supply) to panel otm8009a (orisetech) on stm32mp157c-dk2 & regulator v3v3. Signed-off-by: Yannick Fertré Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-dk2.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157c-dk2.dts b/arch/arm/boot/dts/stm32mp157c-dk2.dts index 363aeb91d1d6..20ea601a546d 100644 --- a/arch/arm/boot/dts/stm32mp157c-dk2.dts +++ b/arch/arm/boot/dts/stm32mp157c-dk2.dts @@ -50,6 +50,7 @@ compatible = "orisetech,otm8009a"; reg = <0>; reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>; + power-supply = <&v3v3>; status = "okay"; port { -- cgit From f85c8acc7a1f60bedea18e4f4819a0edce16ed76 Mon Sep 17 00:00:00 2001 From: Yannick Fertré Date: Fri, 29 Mar 2019 11:48:00 +0100 Subject: ARM: dts: stm32: add I2C sleep pins muxing on stm32mp157 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add I2C sleep pins muxing for low power mode. Signed-off-by: Pierre-Yves MORDRET Signed-off-by: Yannick Fertré Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi index 54c133094a8f..2192fd25857a 100644 --- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi @@ -213,6 +213,13 @@ }; }; + i2c1_pins_sleep_a: i2c1-1 { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + }; + }; + i2c2_pins_a: i2c2-0 { pins { pinmux = , /* I2C2_SCL */ @@ -223,6 +230,13 @@ }; }; + i2c2_pins_sleep_a: i2c2-1 { + pins { + pinmux = , /* I2C2_SCL */ + ; /* I2C2_SDA */ + }; + }; + i2c5_pins_a: i2c5-0 { pins { pinmux = , /* I2C5_SCL */ @@ -233,6 +247,14 @@ }; }; + i2c5_pins_sleep_a: i2c5-1 { + pins { + pinmux = , /* I2C5_SCL */ + ; /* I2C5_SDA */ + + }; + }; + m_can1_pins_a: m-can1-0 { pins1 { pinmux = ; /* CAN1_TX */ @@ -452,6 +474,13 @@ }; }; + i2c4_pins_sleep_a: i2c4-1 { + pins { + pinmux = , /* I2C4_SCL */ + ; /* I2C4_SDA */ + }; + }; + spi1_pins_a: spi1-0 { pins1 { pinmux = , /* SPI1_SCK */ -- cgit From 63834ff2d60458a45bbe6e6d67363cfada195090 Mon Sep 17 00:00:00 2001 From: Yannick Fertré Date: Fri, 29 Mar 2019 13:28:00 +0100 Subject: ARM: dts: stm32: add ltdc pins muxing on stm32mp157 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add ltdc pins muxing on stm32mp157. Signed-off-by: Yannick Fertré Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 138 ++++++++++++++++++++++++++++++ 1 file changed, 138 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi index 2192fd25857a..902666d71ca0 100644 --- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi @@ -255,6 +255,144 @@ }; }; + ltdc_pins_a: ltdc-a-0 { + pins { + pinmux = , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R0 */ + , /* LCD_R1 */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G0 */ + , /* LCD_G1 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B0 */ + , /* LCD_B1 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + ltdc_pins_sleep_a: ltdc-a-1 { + pins { + pinmux = , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R0 */ + , /* LCD_R1 */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G0 */ + , /* LCD_G1 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B0 */ + , /* LCD_B1 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + }; + }; + + ltdc_pins_b: ltdc-b-0 { + pins { + pinmux = , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R0 */ + , /* LCD_R1 */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G0 */ + , /* LCD_G1 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B0 */ + , /* LCD_B1 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + ltdc_pins_sleep_b: ltdc-b-1 { + pins { + pinmux = , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R0 */ + , /* LCD_R1 */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G0 */ + , /* LCD_G1 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B0 */ + , /* LCD_B1 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + }; + }; + m_can1_pins_a: m-can1-0 { pins1 { pinmux = ; /* CAN1_TX */ -- cgit From 5eaae049416d8a327965e3ba5c271851d3069aaa Mon Sep 17 00:00:00 2001 From: Yannick Fertré Date: Wed, 10 Apr 2019 16:06:27 +0200 Subject: ARM: dts: stm32: add cec pins muxing on stm32mp157 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a new pin muxing for cec. Signed-off-by: Yannick Fertré Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi index 902666d71ca0..85c417d9983b 100644 --- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi @@ -157,6 +157,27 @@ }; }; + cec_pins_sleep_a: cec-sleep-0 { + pins { + pinmux = ; /* HDMI_CEC */ + }; + }; + + cec_pins_b: cec-1 { + pins { + pinmux = ; + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + cec_pins_sleep_b: cec-sleep-1 { + pins { + pinmux = ; /* HDMI_CEC */ + }; + }; + ethernet0_rgmii_pins_a: rgmii-0 { pins1 { pinmux = , /* ETH_RGMII_CLK125 */ -- cgit From 3fca6a1ab935e69df40dd67e3425627243685b7f Mon Sep 17 00:00:00 2001 From: Yannick Fertré Date: Fri, 29 Mar 2019 13:29:00 +0100 Subject: ARM: dts: stm32: enable cec on stm32mp157a-dk1 board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable CEC (Consumer Electronics Control) device. Signed-off-by: Yannick Fertré Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157a-dk1.dts | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157a-dk1.dts b/arch/arm/boot/dts/stm32mp157a-dk1.dts index 4bb91abcbcae..098dbfb06b61 100644 --- a/arch/arm/boot/dts/stm32mp157a-dk1.dts +++ b/arch/arm/boot/dts/stm32mp157a-dk1.dts @@ -39,6 +39,13 @@ }; }; +&cec { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cec_pins_b>; + pinctrl-1 = <&cec_pins_sleep_b>; + status = "okay"; +}; + ðernet0 { status = "okay"; pinctrl-0 = <ðernet0_rgmii_pins_a>; -- cgit From 2f60eb2f03b9c3d0a31592c55a88ef62b1403b5d Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Wed, 10 Apr 2019 11:30:10 -0700 Subject: ARM: dts: rockchip: Remove unnecessary setting of UART0 SCLK rate on veyron Some veyron devices have a Bluetooth controller connected on UART0. The UART needs to operate at a high speed, however setting the clock rate at initialization has no practical effect. During initialization user space adjusts the UART baudrate multiple times, which ends up changing the SCLK rate. After a successful initiatalization the clk is running at the desired speed (48MHz). Remove the unnecessary clock rate configuration from the DT. Signed-off-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-veyron.dtsi | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index 5181d9435fda..fa38eb967f12 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -395,10 +395,6 @@ &uart0 { status = "okay"; - /* We need to go faster than 24MHz, so adjust clock parents / rates */ - assigned-clocks = <&cru SCLK_UART0>; - assigned-clock-rates = <48000000>; - /* Pins don't include flow control by default; add that in */ pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; -- cgit From 280fa349757bb240c650882feee5a861150ccc2d Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Tue, 9 Apr 2019 16:14:05 -0700 Subject: ARM: dts: rockchip: Add BT_EN to the power sequence for veyron Add GPIO D5 (BT_ENABLE_L) as reset-GPIO to the power sequence for the Bluetooth/WiFi module. On devices with a Broadcom module the signal needs to be asserted to use Bluetooth. Note that BT_ENABLE_L is a misnomer in the schematics, the signal actually is active-high. Signed-off-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-veyron.dtsi | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index fa38eb967f12..efa7b425c9ed 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -62,12 +62,19 @@ pinctrl-0 = <&bt_enable_l>, <&wifi_enable_h>; /* - * On the module itself this is one of these (depending - * on the actual card populated): + * Depending on the actual card populated GPIO4 D4 and D5 + * correspond to one of these signals on the module: + * + * D4: * - SDIO_RESET_L_WL_REG_ON * - PDN (power down when low) + * + * D5: + * - BT_I2S_WS_BT_RFDISABLE_L + * - No connect */ - reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>, + <&gpio4 RK_PD5 GPIO_ACTIVE_LOW>; }; vcc_5v: vcc-5v { -- cgit From 07f08d9cee459b4d91d79becb7628c7ddeea0a59 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 2 Apr 2019 14:08:57 +0200 Subject: ARM: dts: rockchip: bulk convert gpios to their constant counterparts Rockchip SoCs use 2 different numbering schemes. Where the gpio- controllers just count 0-31 for their 32 gpios, the underlying iomux controller splits these into 4 separate entities A-D. Device-schematics always use these iomux-values to identify pins, so to make mapping schematics to devicetree easier Andy Yan introduced named constants for the pins but so far we only used them on new additions. Using a sed-script created by Emil Renner Berthing bulk-convert the remaining raw gpio numbers into their descriptive counterparts and also gets rid of the unhelpful RK_FUNC_x -> x and RK_GPIOx -> x mappings: /rockchip,pins *=/bcheck b # to end of script :append-next-line N :check /^[^;]*$/bappend-next-line s/ Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3036-kylin.dts | 10 +- arch/arm/boot/dts/rk3036.dtsi | 136 +++++----- arch/arm/boot/dts/rk3066a-marsboard.dts | 2 +- arch/arm/boot/dts/rk3066a-mk808.dts | 8 +- arch/arm/boot/dts/rk3066a-rayeager.dts | 26 +- arch/arm/boot/dts/rk3066a.dtsi | 180 +++++++------- arch/arm/boot/dts/rk3188-px3-evb.dts | 4 +- arch/arm/boot/dts/rk3188-radxarock.dts | 14 +- arch/arm/boot/dts/rk3188.dtsi | 210 ++++++++-------- arch/arm/boot/dts/rk322x.dtsi | 170 ++++++------- arch/arm/boot/dts/rk3288-evb-act8846.dts | 4 +- arch/arm/boot/dts/rk3288-evb.dtsi | 26 +- arch/arm/boot/dts/rk3288-fennec.dts | 10 +- arch/arm/boot/dts/rk3288-firefly-beta.dts | 4 +- arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi | 10 +- arch/arm/boot/dts/rk3288-firefly-reload.dts | 36 +-- arch/arm/boot/dts/rk3288-firefly.dts | 4 +- arch/arm/boot/dts/rk3288-firefly.dtsi | 38 +-- arch/arm/boot/dts/rk3288-miqi.dts | 28 +-- arch/arm/boot/dts/rk3288-phycore-rdk.dts | 28 +-- arch/arm/boot/dts/rk3288-phycore-som.dtsi | 30 +-- arch/arm/boot/dts/rk3288-r89.dts | 14 +- arch/arm/boot/dts/rk3288-rock2-som.dtsi | 4 +- arch/arm/boot/dts/rk3288-rock2-square.dts | 18 +- arch/arm/boot/dts/rk3288-tinker.dtsi | 30 +-- arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi | 8 +- arch/arm/boot/dts/rk3288-veyron-brain.dts | 8 +- arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi | 18 +- arch/arm/boot/dts/rk3288-veyron-jaq.dts | 14 +- arch/arm/boot/dts/rk3288-veyron-jerry.dts | 14 +- arch/arm/boot/dts/rk3288-veyron-mickey.dts | 6 +- arch/arm/boot/dts/rk3288-veyron-mighty.dts | 2 +- arch/arm/boot/dts/rk3288-veyron-minnie.dts | 24 +- arch/arm/boot/dts/rk3288-veyron-pinky.dts | 6 +- arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi | 16 +- arch/arm/boot/dts/rk3288-veyron-speedy.dts | 14 +- arch/arm/boot/dts/rk3288-veyron.dtsi | 50 ++-- arch/arm/boot/dts/rk3288-vyasa.dts | 6 +- arch/arm/boot/dts/rk3288.dtsi | 286 +++++++++++----------- arch/arm/boot/dts/rv1108.dtsi | 138 +++++------ 40 files changed, 827 insertions(+), 827 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts index 0173eb11ec28..fb3cf005cc90 100644 --- a/arch/arm/boot/dts/rk3036-kylin.dts +++ b/arch/arm/boot/dts/rk3036-kylin.dts @@ -368,31 +368,31 @@ &pinctrl { leds { led_ctl: led-ctl { - rockchip,pins = <2 30 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; }; }; pmic { pmic_int: pmic-int { - rockchip,pins = <2 2 RK_FUNC_GPIO &pcfg_pull_default>; + rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_default>; }; }; sdio { bt_wake_h: bt-wake-h { - rockchip,pins = <2 8 RK_FUNC_GPIO &pcfg_pull_default>; + rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_default>; }; }; sdmmc { sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <2 28 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; }; }; sleep { global_pwroff: global-pwroff { - rockchip,pins = <2 7 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>; }; }; }; diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index 59c90863b0e7..0290ea4edd32 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -551,71 +551,71 @@ pwm0 { pwm0_pin: pwm0-pin { - rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; }; }; pwm1 { pwm1_pin: pwm1-pin { - rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>; }; }; pwm2 { pwm2_pin: pwm2-pin { - rockchip,pins = <0 1 2 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>; }; }; pwm3 { pwm3_pin: pwm3-pin { - rockchip,pins = <0 27 1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; }; }; sdmmc { sdmmc_clk: sdmmc-clk { - rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; }; sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_default>; + rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>; }; sdmmc_cd: sdmmc-cd { - rockchip,pins = <1 17 RK_FUNC_1 &pcfg_pull_default>; + rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>; }; sdmmc_bus1: sdmmc-bus1 { - rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>; + rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>; }; sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>, - <1 19 RK_FUNC_1 &pcfg_pull_default>, - <1 20 RK_FUNC_1 &pcfg_pull_default>, - <1 21 RK_FUNC_1 &pcfg_pull_default>; + rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>, + <1 RK_PC3 1 &pcfg_pull_default>, + <1 RK_PC4 1 &pcfg_pull_default>, + <1 RK_PC5 1 &pcfg_pull_default>; }; }; sdio { sdio_bus1: sdio-bus1 { - rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>; + rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>; }; sdio_bus4: sdio-bus4 { - rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>, - <0 12 RK_FUNC_1 &pcfg_pull_default>, - <0 13 RK_FUNC_1 &pcfg_pull_default>, - <0 14 RK_FUNC_1 &pcfg_pull_default>; + rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>, + <0 RK_PB4 1 &pcfg_pull_default>, + <0 RK_PB5 1 &pcfg_pull_default>, + <0 RK_PB6 1 &pcfg_pull_default>; }; sdio_cmd: sdio-cmd { - rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_default>; + rockchip,pins = <0 RK_PB0 1 &pcfg_pull_default>; }; sdio_clk: sdio-clk { - rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none>; }; }; @@ -625,135 +625,135 @@ * We also have external pulls, so disable the internal ones. */ emmc_clk: emmc-clk { - rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; }; emmc_cmd: emmc-cmd { - rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_default>; + rockchip,pins = <2 RK_PA1 2 &pcfg_pull_default>; }; emmc_bus8: emmc-bus8 { - rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_default>, - <1 25 RK_FUNC_2 &pcfg_pull_default>, - <1 26 RK_FUNC_2 &pcfg_pull_default>, - <1 27 RK_FUNC_2 &pcfg_pull_default>, - <1 28 RK_FUNC_2 &pcfg_pull_default>, - <1 29 RK_FUNC_2 &pcfg_pull_default>, - <1 30 RK_FUNC_2 &pcfg_pull_default>, - <1 31 RK_FUNC_2 &pcfg_pull_default>; + rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, + <1 RK_PD1 2 &pcfg_pull_default>, + <1 RK_PD2 2 &pcfg_pull_default>, + <1 RK_PD3 2 &pcfg_pull_default>, + <1 RK_PD4 2 &pcfg_pull_default>, + <1 RK_PD5 2 &pcfg_pull_default>, + <1 RK_PD6 2 &pcfg_pull_default>, + <1 RK_PD7 2 &pcfg_pull_default>; }; }; emac { emac_xfer: emac-xfer { - rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_default>, /* crs_dvalid */ - <2 13 RK_FUNC_1 &pcfg_pull_default>, /* tx_en */ - <2 14 RK_FUNC_1 &pcfg_pull_default>, /* mac_clk */ - <2 15 RK_FUNC_1 &pcfg_pull_default>, /* rx_err */ - <2 16 RK_FUNC_1 &pcfg_pull_default>, /* rxd1 */ - <2 17 RK_FUNC_1 &pcfg_pull_default>, /* rxd0 */ - <2 18 RK_FUNC_1 &pcfg_pull_default>, /* txd1 */ - <2 19 RK_FUNC_1 &pcfg_pull_default>; /* txd0 */ + rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */ + <2 RK_PB5 1 &pcfg_pull_default>, /* tx_en */ + <2 RK_PB6 1 &pcfg_pull_default>, /* mac_clk */ + <2 RK_PB7 1 &pcfg_pull_default>, /* rx_err */ + <2 RK_PC0 1 &pcfg_pull_default>, /* rxd1 */ + <2 RK_PC1 1 &pcfg_pull_default>, /* rxd0 */ + <2 RK_PC2 1 &pcfg_pull_default>, /* txd1 */ + <2 RK_PC3 1 &pcfg_pull_default>; /* txd0 */ }; emac_mdio: emac-mdio { - rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_default>, /* mac_md */ - <2 25 RK_FUNC_1 &pcfg_pull_default>; /* mac_mdclk */ + rockchip,pins = <2 RK_PB4 1 &pcfg_pull_default>, /* mac_md */ + <2 RK_PD1 1 &pcfg_pull_default>; /* mac_mdclk */ }; }; i2c0 { i2c0_xfer: i2c0-xfer { - rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>, - <0 1 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, + <0 RK_PA1 1 &pcfg_pull_none>; }; }; i2c1 { i2c1_xfer: i2c1-xfer { - rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, - <0 3 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, + <0 RK_PA3 1 &pcfg_pull_none>; }; }; i2c2 { i2c2_xfer: i2c2-xfer { - rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>, - <2 21 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>, + <2 RK_PC5 1 &pcfg_pull_none>; }; }; i2s { i2s_bus: i2s-bus { - rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_default>, - <1 1 RK_FUNC_1 &pcfg_pull_default>, - <1 2 RK_FUNC_1 &pcfg_pull_default>, - <1 3 RK_FUNC_1 &pcfg_pull_default>, - <1 4 RK_FUNC_1 &pcfg_pull_default>, - <1 5 RK_FUNC_1 &pcfg_pull_default>; + rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>, + <1 RK_PA1 1 &pcfg_pull_default>, + <1 RK_PA2 1 &pcfg_pull_default>, + <1 RK_PA3 1 &pcfg_pull_default>, + <1 RK_PA4 1 &pcfg_pull_default>, + <1 RK_PA5 1 &pcfg_pull_default>; }; }; hdmi { hdmi_ctl: hdmi-ctl { - rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>, - <1 9 RK_FUNC_1 &pcfg_pull_none>, - <1 10 RK_FUNC_1 &pcfg_pull_none>, - <1 11 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>, + <1 RK_PB1 1 &pcfg_pull_none>, + <1 RK_PB2 1 &pcfg_pull_none>, + <1 RK_PB3 1 &pcfg_pull_none>; }; }; uart0 { uart0_xfer: uart0-xfer { - rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>, - <0 17 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>, + <0 RK_PC1 1 &pcfg_pull_none>; }; uart0_cts: uart0-cts { - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_default>; + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_default>; }; uart0_rts: uart0-rts { - rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>; }; }; uart1 { uart1_xfer: uart1-xfer { - rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_default>, - <2 23 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PC6 1 &pcfg_pull_default>, + <2 RK_PC7 1 &pcfg_pull_none>; }; /* no rts / cts for uart1 */ }; uart2 { uart2_xfer: uart2-xfer { - rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_default>, - <1 19 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>, + <1 RK_PC3 2 &pcfg_pull_none>; }; /* no rts / cts for uart2 */ }; spi-pins { spi_txd:spi-txd { - rockchip,pins = <1 29 RK_FUNC_3 &pcfg_pull_default>; + rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>; }; spi_rxd:spi-rxd { - rockchip,pins = <1 28 RK_FUNC_3 &pcfg_pull_default>; + rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>; }; spi_clk:spi-clk { - rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_default>; + rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>; }; spi_cs0:spi-cs0 { - rockchip,pins = <1 30 RK_FUNC_3 &pcfg_pull_default>; + rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>; }; spi_cs1:spi-cs1 { - rockchip,pins = <1 31 RK_FUNC_3 &pcfg_pull_default>; + rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>; }; }; diff --git a/arch/arm/boot/dts/rk3066a-marsboard.dts b/arch/arm/boot/dts/rk3066a-marsboard.dts index ce525b956ae5..7e01f6406a86 100644 --- a/arch/arm/boot/dts/rk3066a-marsboard.dts +++ b/arch/arm/boot/dts/rk3066a-marsboard.dts @@ -168,7 +168,7 @@ &pinctrl { lan8720a { phy_int: phy-int { - rockchip,pins = ; + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; diff --git a/arch/arm/boot/dts/rk3066a-mk808.dts b/arch/arm/boot/dts/rk3066a-mk808.dts index 8bc259d3e450..365eff621113 100644 --- a/arch/arm/boot/dts/rk3066a-mk808.dts +++ b/arch/arm/boot/dts/rk3066a-mk808.dts @@ -136,25 +136,25 @@ &pinctrl { usb-host { host_drv: host-drv { - rockchip,pins = ; + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_default>; }; }; usb-otg { otg_drv: otg-drv { - rockchip,pins = ; + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_default>; }; }; sdmmc { sdmmc_pwr: sdmmc-pwr { - rockchip,pins = ; + rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_default>; }; }; sdio { wifi_pwr: wifi-pwr { - rockchip,pins = ; + rockchip,pins = <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts index 949fa800582d..f9db6bb9fa11 100644 --- a/arch/arm/boot/dts/rk3066a-rayeager.dts +++ b/arch/arm/boot/dts/rk3066a-rayeager.dts @@ -322,71 +322,71 @@ ak8963 { comp_int: comp-int { - rockchip,pins = <4 17 RK_FUNC_GPIO &pcfg_pull_default>; + rockchip,pins = <4 RK_PC1 RK_FUNC_GPIO &pcfg_pull_default>; }; }; emac { rmii_rst: rmii-rst { - rockchip,pins = <1 30 RK_FUNC_GPIO &pcfg_output_high>; + rockchip,pins = <1 RK_PD6 RK_FUNC_GPIO &pcfg_output_high>; }; }; ir { ir_int: ir-int { - rockchip,pins = <6 1 RK_FUNC_GPIO &pcfg_pull_default>; + rockchip,pins = <6 RK_PA1 RK_FUNC_GPIO &pcfg_pull_default>; }; }; keys { pwr_key: pwr-key { - rockchip,pins = <6 2 RK_FUNC_GPIO &pcfg_pull_default>; + rockchip,pins = <6 RK_PA2 RK_FUNC_GPIO &pcfg_pull_default>; }; }; mma8452 { gsensor_int: gsensor-int { - rockchip,pins = <4 16 RK_FUNC_GPIO &pcfg_pull_default>; + rockchip,pins = <4 RK_PC0 RK_FUNC_GPIO &pcfg_pull_default>; }; }; mmc { sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <3 7 RK_FUNC_GPIO &pcfg_pull_default>; + rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_default>; }; }; usb_host { host_drv: host-drv { - rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_default>; + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_default>; }; hub_rst: hub-rst { - rockchip,pins = <1 31 RK_FUNC_GPIO &pcfg_output_high>; + rockchip,pins = <1 RK_PD7 RK_FUNC_GPIO &pcfg_output_high>; }; sata_pwr: sata-pwr { - rockchip,pins = <4 22 RK_FUNC_GPIO &pcfg_pull_default>; + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_default>; }; sata_reset: sata-reset { - rockchip,pins = <0 13 RK_FUNC_GPIO &pcfg_output_high>; + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_output_high>; }; }; usb_otg { otg_drv: otg-drv { - rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_default>; + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_default>; }; }; tps { pmic_int: pmic-int { - rockchip,pins = <6 4 RK_FUNC_GPIO &pcfg_pull_default>; + rockchip,pins = <6 RK_PA4 RK_FUNC_GPIO &pcfg_pull_default>; }; pwr_hold: pwr-hold { - rockchip,pins = <6 8 RK_FUNC_GPIO &pcfg_output_high>; + rockchip,pins = <6 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; }; }; }; diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index d9504fd456a7..3d1b02f45ffd 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -391,33 +391,33 @@ emac { emac_xfer: emac-xfer { - rockchip,pins = , /* mac_clk */ - , /* tx_en */ - , /* txd1 */ - , /* txd0 */ - , /* rx_err */ - , /* crs_dvalid */ - , /* rxd1 */ - ; /* rxd0 */ + rockchip,pins = <1 RK_PC0 2 &pcfg_pull_none>, /* mac_clk */ + <1 RK_PC1 2 &pcfg_pull_none>, /* tx_en */ + <1 RK_PC2 2 &pcfg_pull_none>, /* txd1 */ + <1 RK_PC3 2 &pcfg_pull_none>, /* txd0 */ + <1 RK_PC4 2 &pcfg_pull_none>, /* rx_err */ + <1 RK_PC5 2 &pcfg_pull_none>, /* crs_dvalid */ + <1 RK_PC6 2 &pcfg_pull_none>, /* rxd1 */ + <1 RK_PC7 2 &pcfg_pull_none>; /* rxd0 */ }; emac_mdio: emac-mdio { - rockchip,pins = , /* mac_md */ - ; /* mac_mdclk */ + rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, /* mac_md */ + <1 RK_PD1 2 &pcfg_pull_none>; /* mac_mdclk */ }; }; emmc { emmc_clk: emmc-clk { - rockchip,pins = ; + rockchip,pins = <3 RK_PD7 2 &pcfg_pull_default>; }; emmc_cmd: emmc-cmd { - rockchip,pins = ; + rockchip,pins = <4 RK_PB1 2 &pcfg_pull_default>; }; emmc_rst: emmc-rst { - rockchip,pins = ; + rockchip,pins = <4 RK_PB2 2 &pcfg_pull_default>; }; /* @@ -441,243 +441,243 @@ i2c0 { i2c0_xfer: i2c0-xfer { - rockchip,pins = , - ; + rockchip,pins = <2 RK_PD4 1 &pcfg_pull_none>, + <2 RK_PD5 1 &pcfg_pull_none>; }; }; i2c1 { i2c1_xfer: i2c1-xfer { - rockchip,pins = , - ; + rockchip,pins = <2 RK_PD6 1 &pcfg_pull_none>, + <2 RK_PD7 1 &pcfg_pull_none>; }; }; i2c2 { i2c2_xfer: i2c2-xfer { - rockchip,pins = , - ; + rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none>, + <3 RK_PA1 1 &pcfg_pull_none>; }; }; i2c3 { i2c3_xfer: i2c3-xfer { - rockchip,pins = , - ; + rockchip,pins = <3 RK_PA2 2 &pcfg_pull_none>, + <3 RK_PA3 2 &pcfg_pull_none>; }; }; i2c4 { i2c4_xfer: i2c4-xfer { - rockchip,pins = , - ; + rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>, + <3 RK_PA5 1 &pcfg_pull_none>; }; }; pwm0 { pwm0_out: pwm0-out { - rockchip,pins = ; + rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; }; }; pwm1 { pwm1_out: pwm1-out { - rockchip,pins = ; + rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>; }; }; pwm2 { pwm2_out: pwm2-out { - rockchip,pins = ; + rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; }; }; pwm3 { pwm3_out: pwm3-out { - rockchip,pins = ; + rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>; }; }; spi0 { spi0_clk: spi0-clk { - rockchip,pins = ; + rockchip,pins = <1 RK_PA5 2 &pcfg_pull_default>; }; spi0_cs0: spi0-cs0 { - rockchip,pins = ; + rockchip,pins = <1 RK_PA4 2 &pcfg_pull_default>; }; spi0_tx: spi0-tx { - rockchip,pins = ; + rockchip,pins = <1 RK_PA7 2 &pcfg_pull_default>; }; spi0_rx: spi0-rx { - rockchip,pins = ; + rockchip,pins = <1 RK_PA6 2 &pcfg_pull_default>; }; spi0_cs1: spi0-cs1 { - rockchip,pins = ; + rockchip,pins = <4 RK_PB7 1 &pcfg_pull_default>; }; }; spi1 { spi1_clk: spi1-clk { - rockchip,pins = ; + rockchip,pins = <2 RK_PC3 2 &pcfg_pull_default>; }; spi1_cs0: spi1-cs0 { - rockchip,pins = ; + rockchip,pins = <2 RK_PC4 2 &pcfg_pull_default>; }; spi1_rx: spi1-rx { - rockchip,pins = ; + rockchip,pins = <2 RK_PC6 2 &pcfg_pull_default>; }; spi1_tx: spi1-tx { - rockchip,pins = ; + rockchip,pins = <2 RK_PC5 2 &pcfg_pull_default>; }; spi1_cs1: spi1-cs1 { - rockchip,pins = ; + rockchip,pins = <2 RK_PC7 2 &pcfg_pull_default>; }; }; uart0 { uart0_xfer: uart0-xfer { - rockchip,pins = , - ; + rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>, + <1 RK_PA1 1 &pcfg_pull_default>; }; uart0_cts: uart0-cts { - rockchip,pins = ; + rockchip,pins = <1 RK_PA2 1 &pcfg_pull_default>; }; uart0_rts: uart0-rts { - rockchip,pins = ; + rockchip,pins = <1 RK_PA3 1 &pcfg_pull_default>; }; }; uart1 { uart1_xfer: uart1-xfer { - rockchip,pins = , - ; + rockchip,pins = <1 RK_PA4 1 &pcfg_pull_default>, + <1 RK_PA5 1 &pcfg_pull_default>; }; uart1_cts: uart1-cts { - rockchip,pins = ; + rockchip,pins = <1 RK_PA6 1 &pcfg_pull_default>; }; uart1_rts: uart1-rts { - rockchip,pins = ; + rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; }; }; uart2 { uart2_xfer: uart2-xfer { - rockchip,pins = , - ; + rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>, + <1 RK_PB1 1 &pcfg_pull_default>; }; /* no rts / cts for uart2 */ }; uart3 { uart3_xfer: uart3-xfer { - rockchip,pins = , - ; + rockchip,pins = <3 RK_PD3 1 &pcfg_pull_default>, + <3 RK_PD4 1 &pcfg_pull_default>; }; uart3_cts: uart3-cts { - rockchip,pins = ; + rockchip,pins = <3 RK_PD5 1 &pcfg_pull_default>; }; uart3_rts: uart3-rts { - rockchip,pins = ; + rockchip,pins = <3 RK_PD6 1 &pcfg_pull_default>; }; }; sd0 { sd0_clk: sd0-clk { - rockchip,pins = ; + rockchip,pins = <3 RK_PB0 1 &pcfg_pull_default>; }; sd0_cmd: sd0-cmd { - rockchip,pins = ; + rockchip,pins = <3 RK_PB1 1 &pcfg_pull_default>; }; sd0_cd: sd0-cd { - rockchip,pins = ; + rockchip,pins = <3 RK_PB6 1 &pcfg_pull_default>; }; sd0_wp: sd0-wp { - rockchip,pins = ; + rockchip,pins = <3 RK_PB7 1 &pcfg_pull_default>; }; sd0_bus1: sd0-bus-width1 { - rockchip,pins = ; + rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>; }; sd0_bus4: sd0-bus-width4 { - rockchip,pins = , - , - , - ; + rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>, + <3 RK_PB3 1 &pcfg_pull_default>, + <3 RK_PB4 1 &pcfg_pull_default>, + <3 RK_PB5 1 &pcfg_pull_default>; }; }; sd1 { sd1_clk: sd1-clk { - rockchip,pins = ; + rockchip,pins = <3 RK_PC5 1 &pcfg_pull_default>; }; sd1_cmd: sd1-cmd { - rockchip,pins = ; + rockchip,pins = <3 RK_PC0 1 &pcfg_pull_default>; }; sd1_cd: sd1-cd { - rockchip,pins = ; + rockchip,pins = <3 RK_PC6 1 &pcfg_pull_default>; }; sd1_wp: sd1-wp { - rockchip,pins = ; + rockchip,pins = <3 RK_PC7 1 &pcfg_pull_default>; }; sd1_bus1: sd1-bus-width1 { - rockchip,pins = ; + rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>; }; sd1_bus4: sd1-bus-width4 { - rockchip,pins = , - , - , - ; + rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>, + <3 RK_PC2 1 &pcfg_pull_default>, + <3 RK_PC3 1 &pcfg_pull_default>, + <3 RK_PC4 1 &pcfg_pull_default>; }; }; i2s0 { i2s0_bus: i2s0-bus { - rockchip,pins = , - , - , - , - , - , - , - , - ; + rockchip,pins = <0 RK_PA7 1 &pcfg_pull_default>, + <0 RK_PB0 1 &pcfg_pull_default>, + <0 RK_PB1 1 &pcfg_pull_default>, + <0 RK_PB2 1 &pcfg_pull_default>, + <0 RK_PB3 1 &pcfg_pull_default>, + <0 RK_PB4 1 &pcfg_pull_default>, + <0 RK_PB5 1 &pcfg_pull_default>, + <0 RK_PB6 1 &pcfg_pull_default>, + <0 RK_PB7 1 &pcfg_pull_default>; }; }; i2s1 { i2s1_bus: i2s1-bus { - rockchip,pins = , - , - , - , - , - ; + rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>, + <0 RK_PC1 1 &pcfg_pull_default>, + <0 RK_PC2 1 &pcfg_pull_default>, + <0 RK_PC3 1 &pcfg_pull_default>, + <0 RK_PC4 1 &pcfg_pull_default>, + <0 RK_PC5 1 &pcfg_pull_default>; }; }; i2s2 { i2s2_bus: i2s2-bus { - rockchip,pins = , - , - , - , - , - ; + rockchip,pins = <0 RK_PD0 1 &pcfg_pull_default>, + <0 RK_PD1 1 &pcfg_pull_default>, + <0 RK_PD2 1 &pcfg_pull_default>, + <0 RK_PD3 1 &pcfg_pull_default>, + <0 RK_PD4 1 &pcfg_pull_default>, + <0 RK_PD5 1 &pcfg_pull_default>; }; }; }; diff --git a/arch/arm/boot/dts/rk3188-px3-evb.dts b/arch/arm/boot/dts/rk3188-px3-evb.dts index c0eaa9c5490b..c32e1d441cf7 100644 --- a/arch/arm/boot/dts/rk3188-px3-evb.dts +++ b/arch/arm/boot/dts/rk3188-px3-evb.dts @@ -247,10 +247,10 @@ usb { host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; }; otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <2 31 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <2 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index 94bc81c24049..c9a7f5409960 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -307,40 +307,40 @@ act8846 { act8846_dvs0_ctl: act8846-dvs0-ctl { - rockchip,pins = ; + rockchip,pins = <3 RK_PD3 RK_FUNC_GPIO &pcfg_output_low>; }; }; hym8563 { rtc_int: rtc-int { - rockchip,pins = ; + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; }; }; lan8720a { phy_int: phy-int { - rockchip,pins = ; + rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; }; }; ir-receiver { ir_recv_pin: ir-recv-pin { - rockchip,pins = ; + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; sd0 { sdmmc_pwr: sdmmc-pwr { - rockchip,pins = ; + rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; }; }; usb { host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; }; otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <2 31 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <2 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 3ed49898f4b2..10ede65d90f3 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -315,15 +315,15 @@ emmc { emmc_clk: emmc-clk { - rockchip,pins = ; + rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>; }; emmc_cmd: emmc-cmd { - rockchip,pins = ; + rockchip,pins = <0 RK_PD2 2 &pcfg_pull_up>; }; emmc_rst: emmc-rst { - rockchip,pins = ; + rockchip,pins = <0 RK_PD3 2 &pcfg_pull_none>; }; /* @@ -336,291 +336,291 @@ emac { emac_xfer: emac-xfer { - rockchip,pins = , /* tx_en */ - , /* txd1 */ - , /* txd0 */ - , /* rxd0 */ - , /* rxd1 */ - , /* mac_clk */ - , /* rx_err */ - ; /* crs_dvalid */ + rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>, /* tx_en */ + <3 RK_PC1 2 &pcfg_pull_none>, /* txd1 */ + <3 RK_PC2 2 &pcfg_pull_none>, /* txd0 */ + <3 RK_PC3 2 &pcfg_pull_none>, /* rxd0 */ + <3 RK_PC4 2 &pcfg_pull_none>, /* rxd1 */ + <3 RK_PC5 2 &pcfg_pull_none>, /* mac_clk */ + <3 RK_PC6 2 &pcfg_pull_none>, /* rx_err */ + <3 RK_PC7 2 &pcfg_pull_none>; /* crs_dvalid */ }; emac_mdio: emac-mdio { - rockchip,pins = , - ; + rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>, + <3 RK_PD1 2 &pcfg_pull_none>; }; }; i2c0 { i2c0_xfer: i2c0-xfer { - rockchip,pins = , - ; + rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, + <1 RK_PD1 1 &pcfg_pull_none>; }; }; i2c1 { i2c1_xfer: i2c1-xfer { - rockchip,pins = , - ; + rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>, + <1 RK_PD3 1 &pcfg_pull_none>; }; }; i2c2 { i2c2_xfer: i2c2-xfer { - rockchip,pins = , - ; + rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>, + <1 RK_PD5 1 &pcfg_pull_none>; }; }; i2c3 { i2c3_xfer: i2c3-xfer { - rockchip,pins = , - ; + rockchip,pins = <3 RK_PB6 2 &pcfg_pull_none>, + <3 RK_PB7 2 &pcfg_pull_none>; }; }; i2c4 { i2c4_xfer: i2c4-xfer { - rockchip,pins = , - ; + rockchip,pins = <1 RK_PD6 1 &pcfg_pull_none>, + <1 RK_PD7 1 &pcfg_pull_none>; }; }; lcdc1 { lcdc1_dclk: lcdc1-dclk { - rockchip,pins = <2 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>; }; lcdc1_den: lcdc1-den { - rockchip,pins = <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none>; }; lcdc1_hsync: lcdc1-hsync { - rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>; }; lcdc1_vsync: lcdc1-vsync { - rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>; }; lcdc1_rgb24: ldcd1-rgb24 { - rockchip,pins = <2 RK_PA0 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PA1 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PA3 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PC6 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>, + <2 RK_PA1 1 &pcfg_pull_none>, + <2 RK_PA2 1 &pcfg_pull_none>, + <2 RK_PA3 1 &pcfg_pull_none>, + <2 RK_PA4 1 &pcfg_pull_none>, + <2 RK_PA5 1 &pcfg_pull_none>, + <2 RK_PA6 1 &pcfg_pull_none>, + <2 RK_PA7 1 &pcfg_pull_none>, + <2 RK_PB0 1 &pcfg_pull_none>, + <2 RK_PB1 1 &pcfg_pull_none>, + <2 RK_PB2 1 &pcfg_pull_none>, + <2 RK_PB3 1 &pcfg_pull_none>, + <2 RK_PB4 1 &pcfg_pull_none>, + <2 RK_PB5 1 &pcfg_pull_none>, + <2 RK_PB6 1 &pcfg_pull_none>, + <2 RK_PB7 1 &pcfg_pull_none>, + <2 RK_PC0 1 &pcfg_pull_none>, + <2 RK_PC1 1 &pcfg_pull_none>, + <2 RK_PC2 1 &pcfg_pull_none>, + <2 RK_PC3 1 &pcfg_pull_none>, + <2 RK_PC4 1 &pcfg_pull_none>, + <2 RK_PC5 1 &pcfg_pull_none>, + <2 RK_PC6 1 &pcfg_pull_none>, + <2 RK_PC7 1 &pcfg_pull_none>; }; }; pwm0 { pwm0_out: pwm0-out { - rockchip,pins = ; + rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; }; }; pwm1 { pwm1_out: pwm1-out { - rockchip,pins = ; + rockchip,pins = <3 RK_PD4 1 &pcfg_pull_none>; }; }; pwm2 { pwm2_out: pwm2-out { - rockchip,pins = ; + rockchip,pins = <3 RK_PD5 1 &pcfg_pull_none>; }; }; pwm3 { pwm3_out: pwm3-out { - rockchip,pins = ; + rockchip,pins = <3 RK_PD6 1 &pcfg_pull_none>; }; }; spi0 { spi0_clk: spi0-clk { - rockchip,pins = ; + rockchip,pins = <1 RK_PA6 2 &pcfg_pull_up>; }; spi0_cs0: spi0-cs0 { - rockchip,pins = ; + rockchip,pins = <1 RK_PA7 2 &pcfg_pull_up>; }; spi0_tx: spi0-tx { - rockchip,pins = ; + rockchip,pins = <1 RK_PA5 2 &pcfg_pull_up>; }; spi0_rx: spi0-rx { - rockchip,pins = ; + rockchip,pins = <1 RK_PA4 2 &pcfg_pull_up>; }; spi0_cs1: spi0-cs1 { - rockchip,pins = ; + rockchip,pins = <1 RK_PB7 1 &pcfg_pull_up>; }; }; spi1 { spi1_clk: spi1-clk { - rockchip,pins = ; + rockchip,pins = <0 RK_PD6 1 &pcfg_pull_up>; }; spi1_cs0: spi1-cs0 { - rockchip,pins = ; + rockchip,pins = <0 RK_PD7 1 &pcfg_pull_up>; }; spi1_rx: spi1-rx { - rockchip,pins = ; + rockchip,pins = <0 RK_PD4 1 &pcfg_pull_up>; }; spi1_tx: spi1-tx { - rockchip,pins = ; + rockchip,pins = <0 RK_PD5 1 &pcfg_pull_up>; }; spi1_cs1: spi1-cs1 { - rockchip,pins = ; + rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>; }; }; uart0 { uart0_xfer: uart0-xfer { - rockchip,pins = , - ; + rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up>, + <1 RK_PA1 1 &pcfg_pull_none>; }; uart0_cts: uart0-cts { - rockchip,pins = ; + rockchip,pins = <1 RK_PA2 1 &pcfg_pull_none>; }; uart0_rts: uart0-rts { - rockchip,pins = ; + rockchip,pins = <1 RK_PA3 1 &pcfg_pull_none>; }; }; uart1 { uart1_xfer: uart1-xfer { - rockchip,pins = , - ; + rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up>, + <1 RK_PA5 1 &pcfg_pull_none>; }; uart1_cts: uart1-cts { - rockchip,pins = ; + rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>; }; uart1_rts: uart1-rts { - rockchip,pins = ; + rockchip,pins = <1 RK_PA7 1 &pcfg_pull_none>; }; }; uart2 { uart2_xfer: uart2-xfer { - rockchip,pins = , - ; + rockchip,pins = <1 RK_PB0 1 &pcfg_pull_up>, + <1 RK_PB1 1 &pcfg_pull_none>; }; /* no rts / cts for uart2 */ }; uart3 { uart3_xfer: uart3-xfer { - rockchip,pins = , - ; + rockchip,pins = <1 RK_PB2 1 &pcfg_pull_up>, + <1 RK_PB3 1 &pcfg_pull_none>; }; uart3_cts: uart3-cts { - rockchip,pins = ; + rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none>; }; uart3_rts: uart3-rts { - rockchip,pins = ; + rockchip,pins = <1 RK_PB5 1 &pcfg_pull_none>; }; }; sd0 { sd0_clk: sd0-clk { - rockchip,pins = ; + rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none>; }; sd0_cmd: sd0-cmd { - rockchip,pins = ; + rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>; }; sd0_cd: sd0-cd { - rockchip,pins = ; + rockchip,pins = <3 RK_PB0 1 &pcfg_pull_none>; }; sd0_wp: sd0-wp { - rockchip,pins = ; + rockchip,pins = <3 RK_PB1 1 &pcfg_pull_none>; }; sd0_pwr: sd0-pwr { - rockchip,pins = ; + rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>; }; sd0_bus1: sd0-bus-width1 { - rockchip,pins = ; + rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>; }; sd0_bus4: sd0-bus-width4 { - rockchip,pins = , - , - , - ; + rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>, + <3 RK_PA5 1 &pcfg_pull_none>, + <3 RK_PA6 1 &pcfg_pull_none>, + <3 RK_PA7 1 &pcfg_pull_none>; }; }; sd1 { sd1_clk: sd1-clk { - rockchip,pins = ; + rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>; }; sd1_cmd: sd1-cmd { - rockchip,pins = ; + rockchip,pins = <3 RK_PC0 1 &pcfg_pull_none>; }; sd1_cd: sd1-cd { - rockchip,pins = ; + rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>; }; sd1_wp: sd1-wp { - rockchip,pins = ; + rockchip,pins = <3 RK_PC7 1 &pcfg_pull_none>; }; sd1_bus1: sd1-bus-width1 { - rockchip,pins = ; + rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>; }; sd1_bus4: sd1-bus-width4 { - rockchip,pins = , - , - , - ; + rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>, + <3 RK_PC2 1 &pcfg_pull_none>, + <3 RK_PC3 1 &pcfg_pull_none>, + <3 RK_PC4 1 &pcfg_pull_none>; }; }; i2s0 { i2s0_bus: i2s0-bus { - rockchip,pins = , - , - , - , - , - ; + rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>, + <1 RK_PC1 1 &pcfg_pull_none>, + <1 RK_PC2 1 &pcfg_pull_none>, + <1 RK_PC3 1 &pcfg_pull_none>, + <1 RK_PC4 1 &pcfg_pull_none>, + <1 RK_PC5 1 &pcfg_pull_none>; }; }; spdif { spdif_tx: spdif-tx { - rockchip,pins = ; + rockchip,pins = <1 RK_PB6 1 &pcfg_pull_none>; }; }; }; diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index 29f19076dceb..da102fff96a2 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -865,228 +865,228 @@ emmc { emmc_clk: emmc-clk { - rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; }; emmc_cmd: emmc-cmd { - rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <1 RK_PC6 2 &pcfg_pull_none>; }; emmc_bus8: emmc-bus8 { - rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, - <1 25 RK_FUNC_2 &pcfg_pull_none>, - <1 26 RK_FUNC_2 &pcfg_pull_none>, - <1 27 RK_FUNC_2 &pcfg_pull_none>, - <1 28 RK_FUNC_2 &pcfg_pull_none>, - <1 29 RK_FUNC_2 &pcfg_pull_none>, - <1 30 RK_FUNC_2 &pcfg_pull_none>, - <1 31 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, + <1 RK_PD1 2 &pcfg_pull_none>, + <1 RK_PD2 2 &pcfg_pull_none>, + <1 RK_PD3 2 &pcfg_pull_none>, + <1 RK_PD4 2 &pcfg_pull_none>, + <1 RK_PD5 2 &pcfg_pull_none>, + <1 RK_PD6 2 &pcfg_pull_none>, + <1 RK_PD7 2 &pcfg_pull_none>; }; }; gmac { rgmii_pins: rgmii-pins { - rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>, - <2 12 RK_FUNC_1 &pcfg_pull_none>, - <2 25 RK_FUNC_1 &pcfg_pull_none>, - <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 22 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 23 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 9 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 17 RK_FUNC_1 &pcfg_pull_none>, - <2 16 RK_FUNC_1 &pcfg_pull_none>, - <2 21 RK_FUNC_2 &pcfg_pull_none>, - <2 20 RK_FUNC_2 &pcfg_pull_none>, - <2 11 RK_FUNC_1 &pcfg_pull_none>, - <2 8 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>, + <2 RK_PB4 1 &pcfg_pull_none>, + <2 RK_PD1 1 &pcfg_pull_none>, + <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>, + <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>, + <2 RK_PC6 1 &pcfg_pull_none_drv_12ma>, + <2 RK_PC7 1 &pcfg_pull_none_drv_12ma>, + <2 RK_PB1 1 &pcfg_pull_none_drv_12ma>, + <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>, + <2 RK_PC1 1 &pcfg_pull_none>, + <2 RK_PC0 1 &pcfg_pull_none>, + <2 RK_PC5 2 &pcfg_pull_none>, + <2 RK_PC4 2 &pcfg_pull_none>, + <2 RK_PB3 1 &pcfg_pull_none>, + <2 RK_PB0 1 &pcfg_pull_none>; }; rmii_pins: rmii-pins { - rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>, - <2 12 RK_FUNC_1 &pcfg_pull_none>, - <2 25 RK_FUNC_1 &pcfg_pull_none>, - <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 17 RK_FUNC_1 &pcfg_pull_none>, - <2 16 RK_FUNC_1 &pcfg_pull_none>, - <2 8 RK_FUNC_1 &pcfg_pull_none>, - <2 15 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>, + <2 RK_PB4 1 &pcfg_pull_none>, + <2 RK_PD1 1 &pcfg_pull_none>, + <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>, + <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>, + <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>, + <2 RK_PC1 1 &pcfg_pull_none>, + <2 RK_PC0 1 &pcfg_pull_none>, + <2 RK_PB0 1 &pcfg_pull_none>, + <2 RK_PB7 1 &pcfg_pull_none>; }; phy_pins: phy-pins { - rockchip,pins = <2 14 RK_FUNC_2 &pcfg_pull_none>, - <2 8 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PB6 2 &pcfg_pull_none>, + <2 RK_PB0 2 &pcfg_pull_none>; }; }; i2c0 { i2c0_xfer: i2c0-xfer { - rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>, - <0 1 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, + <0 RK_PA1 1 &pcfg_pull_none>; }; }; i2c1 { i2c1_xfer: i2c1-xfer { - rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, - <0 3 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, + <0 RK_PA3 1 &pcfg_pull_none>; }; }; i2c2 { i2c2_xfer: i2c2-xfer { - rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>, - <2 21 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>, + <2 RK_PC5 1 &pcfg_pull_none>; }; }; i2c3 { i2c3_xfer: i2c3-xfer { - rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>, - <0 7 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, + <0 RK_PA7 1 &pcfg_pull_none>; }; }; spi-0 { spi0_clk: spi0-clk { - rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>; }; spi0_cs0: spi0-cs0 { - rockchip,pins = <0 14 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>; }; spi0_tx: spi0-tx { - rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>; }; spi0_rx: spi0-rx { - rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>; }; spi0_cs1: spi0-cs1 { - rockchip,pins = <1 12 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <1 RK_PB4 1 &pcfg_pull_up>; }; }; spi-1 { spi1_clk: spi1-clk { - rockchip,pins = <0 23 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>; }; spi1_cs0: spi1-cs0 { - rockchip,pins = <2 2 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <2 RK_PA2 2 &pcfg_pull_up>; }; spi1_rx: spi1-rx { - rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up>; }; spi1_tx: spi1-tx { - rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <2 RK_PA1 2 &pcfg_pull_up>; }; spi1_cs1: spi1-cs1 { - rockchip,pins = <2 3 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <2 RK_PA3 2 &pcfg_pull_up>; }; }; i2s1 { i2s1_bus: i2s1-bus { - rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_none>, - <0 9 RK_FUNC_1 &pcfg_pull_none>, - <0 11 RK_FUNC_1 &pcfg_pull_none>, - <0 12 RK_FUNC_1 &pcfg_pull_none>, - <0 13 RK_FUNC_1 &pcfg_pull_none>, - <0 14 RK_FUNC_1 &pcfg_pull_none>, - <1 2 RK_FUNC_2 &pcfg_pull_none>, - <1 4 RK_FUNC_2 &pcfg_pull_none>, - <1 5 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, + <0 RK_PB1 1 &pcfg_pull_none>, + <0 RK_PB3 1 &pcfg_pull_none>, + <0 RK_PB4 1 &pcfg_pull_none>, + <0 RK_PB5 1 &pcfg_pull_none>, + <0 RK_PB6 1 &pcfg_pull_none>, + <1 RK_PA2 2 &pcfg_pull_none>, + <1 RK_PA4 2 &pcfg_pull_none>, + <1 RK_PA5 2 &pcfg_pull_none>; }; }; pwm0 { pwm0_pin: pwm0-pin { - rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>; }; }; pwm1 { pwm1_pin: pwm1-pin { - rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; }; }; pwm2 { pwm2_pin: pwm2-pin { - rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <1 RK_PB4 2 &pcfg_pull_none>; }; }; pwm3 { pwm3_pin: pwm3-pin { - rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; }; }; spdif { spdif_tx: spdif-tx { - rockchip,pins = <3 31 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <3 RK_PD7 2 &pcfg_pull_none>; }; }; tsadc { otp_gpio: otp-gpio { - rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; }; otp_out: otp-out { - rockchip,pins = <0 24 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>; }; }; uart0 { uart0_xfer: uart0-xfer { - rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>, - <2 27 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>, + <2 RK_PD3 1 &pcfg_pull_none>; }; uart0_cts: uart0-cts { - rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PD5 1 &pcfg_pull_none>; }; uart0_rts: uart0-rts { - rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>; }; }; uart1 { uart1_xfer: uart1-xfer { - rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>, - <1 10 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>, + <1 RK_PB2 1 &pcfg_pull_none>; }; uart1_cts: uart1-cts { - rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>; }; uart1_rts: uart1-rts { - rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; }; }; uart2 { uart2_xfer: uart2-xfer { - rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>, - <1 19 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>, + <1 RK_PC3 2 &pcfg_pull_none>; }; uart21_xfer: uart21-xfer { - rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>, - <1 9 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <1 RK_PB2 2 &pcfg_pull_up>, + <1 RK_PB1 2 &pcfg_pull_none>; }; uart2_cts: uart2-cts { - rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; }; uart2_rts: uart2-rts { - rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; }; }; }; diff --git a/arch/arm/boot/dts/rk3288-evb-act8846.dts b/arch/arm/boot/dts/rk3288-evb-act8846.dts index 6592c809e2a5..80080767c365 100644 --- a/arch/arm/boot/dts/rk3288-evb-act8846.dts +++ b/arch/arm/boot/dts/rk3288-evb-act8846.dts @@ -175,13 +175,13 @@ &pinctrl { lcd { lcd_en: lcd-en { - rockchip,pins = <7 3 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; wifi { wifi_pwr: wifi-pwr { - rockchip,pins = <7 9 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <7 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi index 97e4d552ff0f..820440715302 100644 --- a/arch/arm/boot/dts/rk3288-evb.dtsi +++ b/arch/arm/boot/dts/rk3288-evb.dtsi @@ -314,25 +314,25 @@ backlight { bl_en: bl-en { - rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; buttons { pwrbtn: pwrbtn { - rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; }; }; lcd { lcd_cs: lcd-cs { - rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; }; }; pmic { pmic_int: pmic-int { - rockchip,pins = ; + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; }; }; @@ -342,34 +342,34 @@ * high-speed mode on EVB board so bump up to 8ma. */ sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, - <6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, - <6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, - <6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; + rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_8ma>, + <6 RK_PC1 1 &pcfg_pull_up_drv_8ma>, + <6 RK_PC2 1 &pcfg_pull_up_drv_8ma>, + <6 RK_PC3 1 &pcfg_pull_up_drv_8ma>; }; sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; + rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>; }; sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; + rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_8ma>; }; sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; usb { host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; }; }; eth_phy { eth_phy_pwr: eth-phy-pwr { - rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; diff --git a/arch/arm/boot/dts/rk3288-fennec.dts b/arch/arm/boot/dts/rk3288-fennec.dts index 29af26e6d442..4847cf902a15 100644 --- a/arch/arm/boot/dts/rk3288-fennec.dts +++ b/arch/arm/boot/dts/rk3288-fennec.dts @@ -278,27 +278,27 @@ gmac { phy_int: phy-int { - rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; }; phy_pmeb: phy-pmeb { - rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; }; phy_rst: phy-rst { - rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; }; }; pmic { pmic_int: pmic-int { - rockchip,pins = ; + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; }; }; usbphy { host_drv: host-drv { - rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; diff --git a/arch/arm/boot/dts/rk3288-firefly-beta.dts b/arch/arm/boot/dts/rk3288-firefly-beta.dts index 0f3c29d7fbab..135e8832141f 100644 --- a/arch/arm/boot/dts/rk3288-firefly-beta.dts +++ b/arch/arm/boot/dts/rk3288-firefly-beta.dts @@ -18,13 +18,13 @@ &pinctrl { act8846 { pmic_vsel: pmic-vsel { - rockchip,pins = <7 1 RK_FUNC_GPIO &pcfg_output_low>; + rockchip,pins = <7 RK_PA1 RK_FUNC_GPIO &pcfg_output_low>; }; }; ir { ir_int: ir-int { - rockchip,pins = <7 5 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <7 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; }; }; }; diff --git a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi index f57f286a93c3..61435d8ee37b 100644 --- a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi @@ -224,25 +224,25 @@ act8846 { pwr_hold: pwr-hold { - rockchip,pins = <0 1 RK_FUNC_GPIO &pcfg_output_high>; + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_output_high>; }; pmic_vsel: pmic-vsel { - rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_output_low>; + rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_output_low>; }; }; gmac { phy_int: phy-int { - rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; }; phy_pmeb: phy-pmeb { - rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; }; phy_rst: phy-rst { - rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; }; }; }; diff --git a/arch/arm/boot/dts/rk3288-firefly-reload.dts b/arch/arm/boot/dts/rk3288-firefly-reload.dts index 3a646c5f4fcf..1574383fd2dc 100644 --- a/arch/arm/boot/dts/rk3288-firefly-reload.dts +++ b/arch/arm/boot/dts/rk3288-firefly-reload.dts @@ -306,39 +306,39 @@ &pinctrl { ir { ir_int: ir-int { - rockchip,pins = <7 0 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <7 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; }; }; dvp { dvp_pwr: dvp-pwr { - rockchip,pins = <0 11 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; }; cif_pwr: cif-pwr { - rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; }; }; hym8563 { rtc_int: rtc-int { - rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; }; }; keys { pwr_key: pwr-key { - rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; }; }; leds { power_led: power-led { - rockchip,pins = <8 2 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <8 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; }; work_led: work-led { - rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; }; }; @@ -348,44 +348,44 @@ * high-speed mode on firefly board so bump up to 12ma. */ sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, - <6 17 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, - <6 18 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, - <6 19 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; + rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_12ma>, + <6 RK_PC1 1 &pcfg_pull_up_drv_12ma>, + <6 RK_PC2 1 &pcfg_pull_up_drv_12ma>, + <6 RK_PC3 1 &pcfg_pull_up_drv_12ma>; }; sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_12ma>; + rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_12ma>; }; sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; + rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_12ma>; }; sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; sdio { wifi_enable: wifi-enable { - rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; }; }; usb_host { host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; }; usbhub_rst: usbhub-rst { - rockchip,pins = <8 3 RK_FUNC_GPIO &pcfg_output_high>; + rockchip,pins = <8 RK_PA3 RK_FUNC_GPIO &pcfg_output_high>; }; }; usb_otg { otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; diff --git a/arch/arm/boot/dts/rk3288-firefly.dts b/arch/arm/boot/dts/rk3288-firefly.dts index 556ab42dd81c..313459dab2e4 100644 --- a/arch/arm/boot/dts/rk3288-firefly.dts +++ b/arch/arm/boot/dts/rk3288-firefly.dts @@ -18,13 +18,13 @@ &pinctrl { act8846 { pmic_vsel: pmic-vsel { - rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_output_low>; + rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_output_low>; }; }; ir { ir_int: ir-int { - rockchip,pins = <7 0 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <7 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; }; }; }; diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi index a6ff7eac4aa8..5e0a19004e46 100644 --- a/arch/arm/boot/dts/rk3288-firefly.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly.dtsi @@ -392,49 +392,49 @@ act8846 { pwr_hold: pwr-hold { - rockchip,pins = <0 1 RK_FUNC_GPIO &pcfg_output_high>; + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_output_high>; }; }; dvp { dvp_pwr: dvp-pwr { - rockchip,pins = <0 11 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; gmac { phy_int: phy-int { - rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; }; phy_pmeb: phy-pmeb { - rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; }; phy_rst: phy-rst { - rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; }; }; hym8563 { rtc_int: rtc-int { - rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; }; }; keys { pwr_key: pwr-key { - rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; }; }; leds { power_led: power-led { - rockchip,pins = <8 2 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <8 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; }; work_led: work-led { - rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; }; }; @@ -444,38 +444,38 @@ * high-speed mode on firefly board so bump up to 12ma. */ sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, - <6 17 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, - <6 18 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, - <6 19 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; + rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_12ma>, + <6 RK_PC1 1 &pcfg_pull_up_drv_12ma>, + <6 RK_PC2 1 &pcfg_pull_up_drv_12ma>, + <6 RK_PC3 1 &pcfg_pull_up_drv_12ma>; }; sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_12ma>; + rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_12ma>; }; sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; + rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_12ma>; }; sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; usb_host { host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; }; usbhub_rst: usbhub-rst { - rockchip,pins = <8 3 RK_FUNC_GPIO &pcfg_output_high>; + rockchip,pins = <8 RK_PA3 RK_FUNC_GPIO &pcfg_output_high>; }; }; usb_otg { otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts index fb7365b604bb..c41d012c8850 100644 --- a/arch/arm/boot/dts/rk3288-miqi.dts +++ b/arch/arm/boot/dts/rk3288-miqi.dts @@ -296,29 +296,29 @@ act8846 { pmic_int: pmic-int { - rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; }; pmic_sleep: pmic-sleep { - rockchip,pins = <0 0 RK_FUNC_GPIO &pcfg_output_low>; + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_output_low>; }; pmic_vsel: pmic-vsel { - rockchip,pins = <7 1 RK_FUNC_GPIO &pcfg_output_low>; + rockchip,pins = <7 RK_PA1 RK_FUNC_GPIO &pcfg_output_low>; }; }; gmac { phy_int: phy-int { - rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; }; phy_pmeb: phy-pmeb { - rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; }; phy_rst: phy-rst { - rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; }; }; @@ -328,28 +328,28 @@ * high-speed mode on firefly board so bump up to 12ma. */ sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, - <6 17 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, - <6 18 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, - <6 19 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; + rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_12ma>, + <6 RK_PC1 1 &pcfg_pull_up_drv_12ma>, + <6 RK_PC2 1 &pcfg_pull_up_drv_12ma>, + <6 RK_PC3 1 &pcfg_pull_up_drv_12ma>; }; sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_12ma>; + rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_12ma>; }; sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; + rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_12ma>; }; sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; usb_host { host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; diff --git a/arch/arm/boot/dts/rk3288-phycore-rdk.dts b/arch/arm/boot/dts/rk3288-phycore-rdk.dts index 7077c3403483..1e33859de484 100644 --- a/arch/arm/boot/dts/rk3288-phycore-rdk.dts +++ b/arch/arm/boot/dts/rk3288-phycore-rdk.dts @@ -160,15 +160,15 @@ buttons { user_button_pins: user-button-pins { /* button 1 */ - rockchip,pins = <8 3 RK_FUNC_GPIO &pcfg_pull_up>, + rockchip,pins = <8 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>, /* button 2 */ - <8 0 RK_FUNC_GPIO &pcfg_pull_up>; + <8 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; }; }; rv4162 { i2c_rtc_int: i2c-rtc-int { - rockchip,pins = <5 10 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <5 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; }; }; @@ -178,44 +178,44 @@ * high-speed mode on pcm-947 board so bump up to 12 mA. */ sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, - <6 17 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, - <6 18 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, - <6 19 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; + rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_12ma>, + <6 RK_PC1 1 &pcfg_pull_up_drv_12ma>, + <6 RK_PC2 1 &pcfg_pull_up_drv_12ma>, + <6 RK_PC3 1 &pcfg_pull_up_drv_12ma>; }; sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_12ma>; + rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_12ma>; }; sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; + rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_12ma>; }; sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; touchscreen { ts_irq_pin: ts-irq-pin { - rockchip,pins = <5 15 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <5 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; }; }; usb_host { host0_vbus_drv: host0-vbus-drv { - rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; }; host1_vbus_drv: host1-vbus-drv { - rockchip,pins = <2 0 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; usb_otg { otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; diff --git a/arch/arm/boot/dts/rk3288-phycore-som.dtsi b/arch/arm/boot/dts/rk3288-phycore-som.dtsi index c218dd54c9b5..77a47b9b756d 100644 --- a/arch/arm/boot/dts/rk3288-phycore-som.dtsi +++ b/arch/arm/boot/dts/rk3288-phycore-som.dtsi @@ -342,49 +342,49 @@ * We also have external pulls, so disable the internal ones. */ emmc_clk: emmc-clk { - rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_12ma>; + rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none_12ma>; }; emmc_cmd: emmc-cmd { - rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_12ma>; + rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none_12ma>; }; emmc_bus8: emmc-bus8 { - rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_12ma>, - <3 1 RK_FUNC_2 &pcfg_pull_none_12ma>, - <3 2 RK_FUNC_2 &pcfg_pull_none_12ma>, - <3 3 RK_FUNC_2 &pcfg_pull_none_12ma>, - <3 4 RK_FUNC_2 &pcfg_pull_none_12ma>, - <3 5 RK_FUNC_2 &pcfg_pull_none_12ma>, - <3 6 RK_FUNC_2 &pcfg_pull_none_12ma>, - <3 7 RK_FUNC_2 &pcfg_pull_none_12ma>; + rockchip,pins = <3 RK_PA0 2 &pcfg_pull_none_12ma>, + <3 RK_PA1 2 &pcfg_pull_none_12ma>, + <3 RK_PA2 2 &pcfg_pull_none_12ma>, + <3 RK_PA3 2 &pcfg_pull_none_12ma>, + <3 RK_PA4 2 &pcfg_pull_none_12ma>, + <3 RK_PA5 2 &pcfg_pull_none_12ma>, + <3 RK_PA6 2 &pcfg_pull_none_12ma>, + <3 RK_PA7 2 &pcfg_pull_none_12ma>; }; }; gmac { phy_int: phy-int { - rockchip,pins = <4 2 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; }; phy_rst: phy-rst { - rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; }; }; leds { user_led: user-led { - rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_output_high>; + rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_output_high>; }; }; pmic { pmic_int: pmic-int { - rockchip,pins = ; + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; }; /* Pin for switching state between sleep and non-sleep state */ pmic_sleep: pmic-sleep { - rockchip,pins = ; + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; }; }; }; diff --git a/arch/arm/boot/dts/rk3288-r89.dts b/arch/arm/boot/dts/rk3288-r89.dts index 28972fb4e221..a6ffc381abaa 100644 --- a/arch/arm/boot/dts/rk3288-r89.dts +++ b/arch/arm/boot/dts/rk3288-r89.dts @@ -265,39 +265,39 @@ act8846 { pmic_vsel: pmic-vsel { - rockchip,pins = <7 1 RK_FUNC_GPIO &pcfg_output_low>; + rockchip,pins = <7 RK_PA1 RK_FUNC_GPIO &pcfg_output_low>; }; pwr_hold: pwr-hold { - rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_output_high>; + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_output_high>; }; }; buttons { pwrbtn: pwrbtn { - rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; }; }; ir { ir_int: ir-int { - rockchip,pins = <7 0 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <7 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; }; }; pmic { pmic_int: pmic-int { - rockchip,pins = ; + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; }; }; usb { host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; }; otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; diff --git a/arch/arm/boot/dts/rk3288-rock2-som.dtsi b/arch/arm/boot/dts/rk3288-rock2-som.dtsi index 32e1ab336662..9f9e2bfd1295 100644 --- a/arch/arm/boot/dts/rk3288-rock2-som.dtsi +++ b/arch/arm/boot/dts/rk3288-rock2-som.dtsi @@ -231,13 +231,13 @@ emmc { emmc_reset: emmc-reset { - rockchip,pins = <3 9 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; }; }; gmac { phy_rst: phy-rst { - rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; }; }; }; diff --git a/arch/arm/boot/dts/rk3288-rock2-square.dts b/arch/arm/boot/dts/rk3288-rock2-square.dts index 5b7e1c9e92e1..cdcdc921ee09 100644 --- a/arch/arm/boot/dts/rk3288-rock2-square.dts +++ b/arch/arm/boot/dts/rk3288-rock2-square.dts @@ -204,53 +204,53 @@ &pinctrl { ir { ir_int: ir-int { - rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; }; }; keys { pwr_key: pwr-key { - rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; }; }; pmic { pmic_int: pmic-int { - rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; }; }; headphone { hp_det: hp-det { - rockchip,pins = <7 7 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <7 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; }; phone_ctl: phone-ctl { - rockchip,pins = <8 0 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <8 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; }; }; usb { host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; }; }; sata { sata_pwr_en: sata-pwr-en { - rockchip,pins = <0 13 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; sdmmc { sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; sdio { wifi_enable: wifi-enable { - rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; diff --git a/arch/arm/boot/dts/rk3288-tinker.dtsi b/arch/arm/boot/dts/rk3288-tinker.dtsi index b053589f8ff8..1e6bbd63808f 100644 --- a/arch/arm/boot/dts/rk3288-tinker.dtsi +++ b/arch/arm/boot/dts/rk3288-tinker.dtsi @@ -363,68 +363,68 @@ backlight { bl_en: bl-en { - rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; buttons { pwrbtn: pwrbtn { - rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; }; }; eth_phy { eth_phy_pwr: eth-phy-pwr { - rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; }; }; pmic { pmic_int: pmic-int { - rockchip,pins = ; }; dvs_1: dvs-1 { - rockchip,pins = ; }; dvs_2: dvs-2 { - rockchip,pins = ; }; }; sdmmc { sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, - <6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, - <6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, - <6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; + rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_8ma>, + <6 RK_PC1 1 &pcfg_pull_up_drv_8ma>, + <6 RK_PC2 1 &pcfg_pull_up_drv_8ma>, + <6 RK_PC3 1 &pcfg_pull_up_drv_8ma>; }; sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 20 RK_FUNC_1 \ + rockchip,pins = <6 RK_PC4 1 \ &pcfg_pull_none_drv_8ma>; }; sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; + rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_8ma>; }; sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; usb { host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; }; pwr_3g: pwr-3g { - rockchip,pins = <7 8 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <7 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; diff --git a/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi b/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi index eaf921694e68..445270aa136e 100644 --- a/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi @@ -73,7 +73,7 @@ &pinctrl { codec { hp_det: hp-det { - rockchip,pins = <6 5 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <6 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; }; /* @@ -82,17 +82,17 @@ * we've got a ts3a227e chip but the driver requires it. */ int_codec: int-codec { - rockchip,pins = <6 7 RK_FUNC_GPIO &pcfg_pull_down>; + rockchip,pins = <6 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; }; mic_det: mic-det { - rockchip,pins = <6 11 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <6 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; }; }; headset { ts3a227e_int_l: ts3a227e-int-l { - rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; }; }; }; diff --git a/arch/arm/boot/dts/rk3288-veyron-brain.dts b/arch/arm/boot/dts/rk3288-veyron-brain.dts index 5c94a33d695d..406146cbff29 100644 --- a/arch/arm/boot/dts/rk3288-veyron-brain.dts +++ b/arch/arm/boot/dts/rk3288-veyron-brain.dts @@ -42,23 +42,23 @@ &pinctrl { hdmi { vcc50_hdmi_en: vcc50-hdmi-en { - rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; pmic { dvs_1: dvs-1 { - rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_down>; + rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>; }; dvs_2: dvs-2 { - rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; + rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; }; }; usb-host { usb2_pwr_en: usb2-pwr-en { - rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi index b54746df3661..72c4754032e9 100644 --- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi @@ -244,51 +244,51 @@ backlight { bl_en: bl-en { - rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; buttons { ap_lid_int_l: ap-lid-int-l { - rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; }; }; charger { ac_present_ap: ac-present-ap { - rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; }; }; cros-ec { ec_int: ec-int { - rockchip,pins = <7 7 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <7 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; }; }; suspend { suspend_l_wake: suspend-l-wake { - rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_output_low>; + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_output_low>; }; suspend_l_sleep: suspend-l-sleep { - rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_output_high>; + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_output_high>; }; }; trackpad { trackpad_int: trackpad-int { - rockchip,pins = <7 3 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; }; }; usb-host { host1_pwr_en: host1-pwr-en { - rockchip,pins = <0 11 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; }; usbotg_pwren_h: usbotg-pwren-h { - rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; diff --git a/arch/arm/boot/dts/rk3288-veyron-jaq.dts b/arch/arm/boot/dts/rk3288-veyron-jaq.dts index 9d6814c7f285..e248f55ee8d2 100644 --- a/arch/arm/boot/dts/rk3288-veyron-jaq.dts +++ b/arch/arm/boot/dts/rk3288-veyron-jaq.dts @@ -138,39 +138,39 @@ &pinctrl { backlight { bl_pwr_en: bl_pwr_en { - rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; }; }; buck-5v { drv_5v: drv-5v { - rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; hdmi { vcc50_hdmi_en: vcc50-hdmi-en { - rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; lcd { lcd_enable_h: lcd-en { - rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; }; avdd_1v8_disp_en: avdd-1v8-disp-en { - rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; pmic { dvs_1: dvs-1 { - rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; + rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; }; dvs_2: dvs-2 { - rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; + rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; }; }; }; diff --git a/arch/arm/boot/dts/rk3288-veyron-jerry.dts b/arch/arm/boot/dts/rk3288-veyron-jerry.dts index 3e8f700a0d64..b1613af83d5d 100644 --- a/arch/arm/boot/dts/rk3288-veyron-jerry.dts +++ b/arch/arm/boot/dts/rk3288-veyron-jerry.dts @@ -106,39 +106,39 @@ &pinctrl { backlight { bl_pwr_en: bl_pwr_en { - rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; }; }; buck-5v { drv_5v: drv-5v { - rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; hdmi { vcc50_hdmi_en: vcc50-hdmi-en { - rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; lcd { lcd_enable_h: lcd-en { - rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; }; avdd_1v8_disp_en: avdd-1v8-disp-en { - rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; pmic { dvs_1: dvs-1 { - rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; + rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; }; dvs_2: dvs-2 { - rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; + rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; }; }; }; diff --git a/arch/arm/boot/dts/rk3288-veyron-mickey.dts b/arch/arm/boot/dts/rk3288-veyron-mickey.dts index d889ab3c8235..e852594417b5 100644 --- a/arch/arm/boot/dts/rk3288-veyron-mickey.dts +++ b/arch/arm/boot/dts/rk3288-veyron-mickey.dts @@ -186,17 +186,17 @@ &pinctrl { hdmi { power_hdmi_on: power-hdmi-on { - rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; pmic { dvs_1: dvs-1 { - rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; + rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; }; dvs_2: dvs-2 { - rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; + rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; }; }; }; diff --git a/arch/arm/boot/dts/rk3288-veyron-mighty.dts b/arch/arm/boot/dts/rk3288-veyron-mighty.dts index f640857cbdae..27fbc07476d2 100644 --- a/arch/arm/boot/dts/rk3288-veyron-mighty.dts +++ b/arch/arm/boot/dts/rk3288-veyron-mighty.dts @@ -28,7 +28,7 @@ &pinctrl { sdmmc { sdmmc_wp_gpio: sdmmc-wp-gpio { - rockchip,pins = <7 10 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <7 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; }; }; }; diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rk3288-veyron-minnie.dts index f95d0c5fcf71..468a1818545d 100644 --- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts +++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts @@ -191,65 +191,65 @@ &pinctrl { backlight { bl_pwr_en: bl_pwr_en { - rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; }; }; buck-5v { drv_5v: drv-5v { - rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; buttons { volum_down_l: volum-down-l { - rockchip,pins = <5 11 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <5 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; }; volum_up_l: volum-up-l { - rockchip,pins = <5 10 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <5 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; }; }; hdmi { vcc50_hdmi_en: vcc50-hdmi-en { - rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; lcd { lcd_enable_h: lcd-en { - rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; }; avdd_1v8_disp_en: avdd-1v8-disp-en { - rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; pmic { dvs_1: dvs-1 { - rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; + rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; }; dvs_2: dvs-2 { - rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; + rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; }; }; prochot { gpio_prochot: gpio-prochot { - rockchip,pins = <2 8 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; touchscreen { touch_int: touch-int { - rockchip,pins = <2 14 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; }; touch_rst: touch-rst { - rockchip,pins = <2 15 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; diff --git a/arch/arm/boot/dts/rk3288-veyron-pinky.dts b/arch/arm/boot/dts/rk3288-veyron-pinky.dts index 2950aadf49f0..9645be7b3d8c 100644 --- a/arch/arm/boot/dts/rk3288-veyron-pinky.dts +++ b/arch/arm/boot/dts/rk3288-veyron-pinky.dts @@ -55,19 +55,19 @@ &pinctrl { buttons { pwr_key_h: pwr-key-h { - rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; emmc { emmc_reset: emmc-reset { - rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; }; }; sdmmc { sdmmc_wp_gpio: sdmmc-wp-gpio { - rockchip,pins = <7 10 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <7 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; }; }; }; diff --git a/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi b/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi index a4570444cc79..fe950f9863e8 100644 --- a/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi @@ -16,18 +16,18 @@ * We also have external pulls, so disable the internal ones. */ sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, - <6 17 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, - <6 18 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, - <6 19 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; + rockchip,pins = <6 RK_PC0 1 &pcfg_pull_none_drv_8ma>, + <6 RK_PC1 1 &pcfg_pull_none_drv_8ma>, + <6 RK_PC2 1 &pcfg_pull_none_drv_8ma>, + <6 RK_PC3 1 &pcfg_pull_none_drv_8ma>; }; sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; + rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>; }; sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; + rockchip,pins = <6 RK_PC5 1 &pcfg_pull_none_drv_8ma>; }; /* @@ -37,12 +37,12 @@ * think there's a card inserted */ sdmmc_cd_disabled: sdmmc-cd-disabled { - rockchip,pins = <6 22 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <6 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; }; /* This is where we actually hook up CD */ sdmmc_cd_gpio: sdmmc-cd-gpio { - rockchip,pins = <7 5 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <7 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; diff --git a/arch/arm/boot/dts/rk3288-veyron-speedy.dts b/arch/arm/boot/dts/rk3288-veyron-speedy.dts index e16421d80d22..2ac8748a3a0c 100644 --- a/arch/arm/boot/dts/rk3288-veyron-speedy.dts +++ b/arch/arm/boot/dts/rk3288-veyron-speedy.dts @@ -104,39 +104,39 @@ &pinctrl { backlight { bl_pwr_en: bl_pwr_en { - rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; }; }; buck-5v { drv_5v: drv-5v { - rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; hdmi { vcc50_hdmi_en: vcc50-hdmi-en { - rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; lcd { lcd_enable_h: lcd-en { - rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; }; avdd_1v8_disp_en: avdd-1v8-disp-en { - rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; pmic { dvs_1: dvs-1 { - rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; + rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; }; dvs_2: dvs-2 { - rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; + rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; }; }; }; diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index efa7b425c9ed..e4f0c00011f2 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -480,13 +480,13 @@ buttons { pwr_key_l: pwr-key-l { - rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; }; }; emmc { emmc_reset: emmc-reset { - rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; }; /* @@ -494,51 +494,51 @@ * We also have external pulls, so disable the internal ones. */ emmc_clk: emmc-clk { - rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; + rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none_drv_8ma>; }; emmc_cmd: emmc-cmd { - rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; + rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none_drv_8ma>; }; emmc_bus8: emmc-bus8 { - rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, - <3 1 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, - <3 2 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, - <3 3 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, - <3 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, - <3 5 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, - <3 6 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, - <3 7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; + rockchip,pins = <3 RK_PA0 2 &pcfg_pull_none_drv_8ma>, + <3 RK_PA1 2 &pcfg_pull_none_drv_8ma>, + <3 RK_PA2 2 &pcfg_pull_none_drv_8ma>, + <3 RK_PA3 2 &pcfg_pull_none_drv_8ma>, + <3 RK_PA4 2 &pcfg_pull_none_drv_8ma>, + <3 RK_PA5 2 &pcfg_pull_none_drv_8ma>, + <3 RK_PA6 2 &pcfg_pull_none_drv_8ma>, + <3 RK_PA7 2 &pcfg_pull_none_drv_8ma>; }; }; pmic { pmic_int_l: pmic-int-l { - rockchip,pins = ; + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; }; }; reboot { ap_warm_reset_h: ap-warm-reset-h { - rockchip,pins = ; + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; recovery-switch { rec_mode_l: rec-mode-l { - rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; }; }; sdio0 { wifi_enable_h: wifienable-h { - rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; }; /* NOTE: mislabelled on schematic; should be bt_enable_h */ bt_enable_l: bt-enable-l { - rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; }; /* @@ -546,30 +546,30 @@ * We also have external pulls, so disable the internal ones. */ sdio0_bus4: sdio0-bus4 { - rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, - <4 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, - <4 22 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, - <4 23 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; + rockchip,pins = <4 RK_PC4 1 &pcfg_pull_none_drv_8ma>, + <4 RK_PC5 1 &pcfg_pull_none_drv_8ma>, + <4 RK_PC6 1 &pcfg_pull_none_drv_8ma>, + <4 RK_PC7 1 &pcfg_pull_none_drv_8ma>; }; sdio0_cmd: sdio0-cmd { - rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; + rockchip,pins = <4 RK_PD0 1 &pcfg_pull_none_drv_8ma>; }; sdio0_clk: sdio0-clk { - rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; + rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none_drv_8ma>; }; }; tpm { tpm_int_h: tpm-int-h { - rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; }; }; write-protect { fw_wp_ap: fw-wp-ap { - rockchip,pins = <7 6 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <7 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; diff --git a/arch/arm/boot/dts/rk3288-vyasa.dts b/arch/arm/boot/dts/rk3288-vyasa.dts index 40b232eb5011..ba06e9f97ddc 100644 --- a/arch/arm/boot/dts/rk3288-vyasa.dts +++ b/arch/arm/boot/dts/rk3288-vyasa.dts @@ -448,13 +448,13 @@ pmic { pmic_int: pmic-int { - rockchip,pins = ; + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; }; }; usb_host { phy_pwr_en: phy-pwr-en { - rockchip,pins = ; + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_output_high>; }; usb2_pwr_en: usb2-pwr-en { @@ -464,7 +464,7 @@ usb_otg { otg_vbus_drv: otg-vbus-drv { - rockchip,pins = ; + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; }; }; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 743a7d85daf7..23e9c5253019 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -1532,16 +1532,16 @@ hdmi { hdmi_cec_c0: hdmi-cec-c0 { - rockchip,pins = <7 RK_PC0 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>; }; hdmi_cec_c7: hdmi-cec-c7 { - rockchip,pins = <7 RK_PC7 RK_FUNC_4 &pcfg_pull_none>; + rockchip,pins = <7 RK_PC7 4 &pcfg_pull_none>; }; hdmi_ddc: hdmi-ddc { - rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>, - <7 20 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>, + <7 RK_PC4 2 &pcfg_pull_none>; }; }; @@ -1564,421 +1564,421 @@ sleep { global_pwroff: global-pwroff { - rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>; }; ddrio_pwroff: ddrio-pwroff { - rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>; }; ddr0_retention: ddr0-retention { - rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>; }; ddr1_retention: ddr1-retention { - rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>; }; }; edp { edp_hpd: edp-hpd { - rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>; + rockchip,pins = <7 RK_PB3 2 &pcfg_pull_down>; }; }; i2c0 { i2c0_xfer: i2c0-xfer { - rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>, - <0 16 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>, + <0 RK_PC0 1 &pcfg_pull_none>; }; }; i2c1 { i2c1_xfer: i2c1-xfer { - rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>, - <8 5 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <8 RK_PA4 1 &pcfg_pull_none>, + <8 RK_PA5 1 &pcfg_pull_none>; }; }; i2c2 { i2c2_xfer: i2c2-xfer { - rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>, - <6 10 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <6 RK_PB1 1 &pcfg_pull_none>, + <6 RK_PB2 1 &pcfg_pull_none>; }; }; i2c3 { i2c3_xfer: i2c3-xfer { - rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>, - <2 17 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>, + <2 RK_PC1 1 &pcfg_pull_none>; }; }; i2c4 { i2c4_xfer: i2c4-xfer { - rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>, - <7 18 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <7 RK_PC1 1 &pcfg_pull_none>, + <7 RK_PC2 1 &pcfg_pull_none>; }; }; i2c5 { i2c5_xfer: i2c5-xfer { - rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>, - <7 20 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <7 RK_PC3 1 &pcfg_pull_none>, + <7 RK_PC4 1 &pcfg_pull_none>; }; }; i2s0 { i2s0_bus: i2s0-bus { - rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>, - <6 1 RK_FUNC_1 &pcfg_pull_none>, - <6 2 RK_FUNC_1 &pcfg_pull_none>, - <6 3 RK_FUNC_1 &pcfg_pull_none>, - <6 4 RK_FUNC_1 &pcfg_pull_none>, - <6 8 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <6 RK_PA0 1 &pcfg_pull_none>, + <6 RK_PA1 1 &pcfg_pull_none>, + <6 RK_PA2 1 &pcfg_pull_none>, + <6 RK_PA3 1 &pcfg_pull_none>, + <6 RK_PA4 1 &pcfg_pull_none>, + <6 RK_PB0 1 &pcfg_pull_none>; }; }; lcdc { lcdc_ctl: lcdc-ctl { - rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>, - <1 25 RK_FUNC_1 &pcfg_pull_none>, - <1 26 RK_FUNC_1 &pcfg_pull_none>, - <1 27 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, + <1 RK_PD1 1 &pcfg_pull_none>, + <1 RK_PD2 1 &pcfg_pull_none>, + <1 RK_PD3 1 &pcfg_pull_none>; }; }; sdmmc { sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none>; }; sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>; }; sdmmc_cd: sdmmc-cd { - rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>; }; sdmmc_bus1: sdmmc-bus1 { - rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>; }; sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>, - <6 17 RK_FUNC_1 &pcfg_pull_up>, - <6 18 RK_FUNC_1 &pcfg_pull_up>, - <6 19 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>, + <6 RK_PC1 1 &pcfg_pull_up>, + <6 RK_PC2 1 &pcfg_pull_up>, + <6 RK_PC3 1 &pcfg_pull_up>; }; }; sdio0 { sdio0_bus1: sdio0-bus1 { - rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>; }; sdio0_bus4: sdio0-bus4 { - rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>, - <4 21 RK_FUNC_1 &pcfg_pull_up>, - <4 22 RK_FUNC_1 &pcfg_pull_up>, - <4 23 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>, + <4 RK_PC5 1 &pcfg_pull_up>, + <4 RK_PC6 1 &pcfg_pull_up>, + <4 RK_PC7 1 &pcfg_pull_up>; }; sdio0_cmd: sdio0-cmd { - rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <4 RK_PD0 1 &pcfg_pull_up>; }; sdio0_clk: sdio0-clk { - rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none>; }; sdio0_cd: sdio0-cd { - rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <4 RK_PD2 1 &pcfg_pull_up>; }; sdio0_wp: sdio0-wp { - rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <4 RK_PD3 1 &pcfg_pull_up>; }; sdio0_pwr: sdio0-pwr { - rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <4 RK_PD4 1 &pcfg_pull_up>; }; sdio0_bkpwr: sdio0-bkpwr { - rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <4 RK_PD5 1 &pcfg_pull_up>; }; sdio0_int: sdio0-int { - rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <4 RK_PD6 1 &pcfg_pull_up>; }; }; sdio1 { sdio1_bus1: sdio1-bus1 { - rockchip,pins = <3 24 4 &pcfg_pull_up>; + rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>; }; sdio1_bus4: sdio1-bus4 { - rockchip,pins = <3 24 4 &pcfg_pull_up>, - <3 25 4 &pcfg_pull_up>, - <3 26 4 &pcfg_pull_up>, - <3 27 4 &pcfg_pull_up>; + rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>, + <3 RK_PD1 4 &pcfg_pull_up>, + <3 RK_PD2 4 &pcfg_pull_up>, + <3 RK_PD3 4 &pcfg_pull_up>; }; sdio1_cd: sdio1-cd { - rockchip,pins = <3 28 4 &pcfg_pull_up>; + rockchip,pins = <3 RK_PD4 4 &pcfg_pull_up>; }; sdio1_wp: sdio1-wp { - rockchip,pins = <3 29 4 &pcfg_pull_up>; + rockchip,pins = <3 RK_PD5 4 &pcfg_pull_up>; }; sdio1_bkpwr: sdio1-bkpwr { - rockchip,pins = <3 30 4 &pcfg_pull_up>; + rockchip,pins = <3 RK_PD6 4 &pcfg_pull_up>; }; sdio1_int: sdio1-int { - rockchip,pins = <3 31 4 &pcfg_pull_up>; + rockchip,pins = <3 RK_PD7 4 &pcfg_pull_up>; }; sdio1_cmd: sdio1-cmd { - rockchip,pins = <4 6 4 &pcfg_pull_up>; + rockchip,pins = <4 RK_PA6 4 &pcfg_pull_up>; }; sdio1_clk: sdio1-clk { - rockchip,pins = <4 7 4 &pcfg_pull_none>; + rockchip,pins = <4 RK_PA7 4 &pcfg_pull_none>; }; sdio1_pwr: sdio1-pwr { - rockchip,pins = <4 9 4 &pcfg_pull_up>; + rockchip,pins = <4 RK_PB1 4 &pcfg_pull_up>; }; }; emmc { emmc_clk: emmc-clk { - rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none>; }; emmc_cmd: emmc-cmd { - rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <3 RK_PC0 2 &pcfg_pull_up>; }; emmc_pwr: emmc-pwr { - rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <3 RK_PB1 2 &pcfg_pull_up>; }; emmc_bus1: emmc-bus1 { - rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>; }; emmc_bus4: emmc-bus4 { - rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, - <3 1 RK_FUNC_2 &pcfg_pull_up>, - <3 2 RK_FUNC_2 &pcfg_pull_up>, - <3 3 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>, + <3 RK_PA1 2 &pcfg_pull_up>, + <3 RK_PA2 2 &pcfg_pull_up>, + <3 RK_PA3 2 &pcfg_pull_up>; }; emmc_bus8: emmc-bus8 { - rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, - <3 1 RK_FUNC_2 &pcfg_pull_up>, - <3 2 RK_FUNC_2 &pcfg_pull_up>, - <3 3 RK_FUNC_2 &pcfg_pull_up>, - <3 4 RK_FUNC_2 &pcfg_pull_up>, - <3 5 RK_FUNC_2 &pcfg_pull_up>, - <3 6 RK_FUNC_2 &pcfg_pull_up>, - <3 7 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>, + <3 RK_PA1 2 &pcfg_pull_up>, + <3 RK_PA2 2 &pcfg_pull_up>, + <3 RK_PA3 2 &pcfg_pull_up>, + <3 RK_PA4 2 &pcfg_pull_up>, + <3 RK_PA5 2 &pcfg_pull_up>, + <3 RK_PA6 2 &pcfg_pull_up>, + <3 RK_PA7 2 &pcfg_pull_up>; }; }; spi0 { spi0_clk: spi0-clk { - rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <5 RK_PB4 1 &pcfg_pull_up>; }; spi0_cs0: spi0-cs0 { - rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <5 RK_PB5 1 &pcfg_pull_up>; }; spi0_tx: spi0-tx { - rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <5 RK_PB6 1 &pcfg_pull_up>; }; spi0_rx: spi0-rx { - rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <5 RK_PB7 1 &pcfg_pull_up>; }; spi0_cs1: spi0-cs1 { - rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <5 RK_PC0 1 &pcfg_pull_up>; }; }; spi1 { spi1_clk: spi1-clk { - rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <7 RK_PB4 2 &pcfg_pull_up>; }; spi1_cs0: spi1-cs0 { - rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <7 RK_PB5 2 &pcfg_pull_up>; }; spi1_rx: spi1-rx { - rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <7 RK_PB6 2 &pcfg_pull_up>; }; spi1_tx: spi1-tx { - rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <7 RK_PB7 2 &pcfg_pull_up>; }; }; spi2 { spi2_cs1: spi2-cs1 { - rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <8 RK_PA3 1 &pcfg_pull_up>; }; spi2_clk: spi2-clk { - rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <8 RK_PA6 1 &pcfg_pull_up>; }; spi2_cs0: spi2-cs0 { - rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <8 RK_PA7 1 &pcfg_pull_up>; }; spi2_rx: spi2-rx { - rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <8 RK_PB0 1 &pcfg_pull_up>; }; spi2_tx: spi2-tx { - rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <8 RK_PB1 1 &pcfg_pull_up>; }; }; uart0 { uart0_xfer: uart0-xfer { - rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>, - <4 17 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <4 RK_PC0 1 &pcfg_pull_up>, + <4 RK_PC1 1 &pcfg_pull_none>; }; uart0_cts: uart0-cts { - rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <4 RK_PC2 1 &pcfg_pull_up>; }; uart0_rts: uart0-rts { - rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <4 RK_PC3 1 &pcfg_pull_none>; }; }; uart1 { uart1_xfer: uart1-xfer { - rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>, - <5 9 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <5 RK_PB0 1 &pcfg_pull_up>, + <5 RK_PB1 1 &pcfg_pull_none>; }; uart1_cts: uart1-cts { - rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <5 RK_PB2 1 &pcfg_pull_up>; }; uart1_rts: uart1-rts { - rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <5 RK_PB3 1 &pcfg_pull_none>; }; }; uart2 { uart2_xfer: uart2-xfer { - rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>, - <7 23 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <7 RK_PC6 1 &pcfg_pull_up>, + <7 RK_PC7 1 &pcfg_pull_none>; }; /* no rts / cts for uart2 */ }; uart3 { uart3_xfer: uart3-xfer { - rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>, - <7 8 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <7 RK_PA7 1 &pcfg_pull_up>, + <7 RK_PB0 1 &pcfg_pull_none>; }; uart3_cts: uart3-cts { - rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <7 RK_PB1 1 &pcfg_pull_up>; }; uart3_rts: uart3-rts { - rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <7 RK_PB2 1 &pcfg_pull_none>; }; }; uart4 { uart4_xfer: uart4-xfer { - rockchip,pins = <5 15 3 &pcfg_pull_up>, - <5 14 3 &pcfg_pull_none>; + rockchip,pins = <5 RK_PB7 3 &pcfg_pull_up>, + <5 RK_PB6 3 &pcfg_pull_none>; }; uart4_cts: uart4-cts { - rockchip,pins = <5 12 3 &pcfg_pull_up>; + rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>; }; uart4_rts: uart4-rts { - rockchip,pins = <5 13 3 &pcfg_pull_none>; + rockchip,pins = <5 RK_PB5 3 &pcfg_pull_none>; }; }; tsadc { otp_gpio: otp-gpio { - rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; }; otp_out: otp-out { - rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>; }; }; pwm0 { pwm0_pin: pwm0-pin { - rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <7 RK_PA0 1 &pcfg_pull_none>; }; }; pwm1 { pwm1_pin: pwm1-pin { - rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <7 RK_PA1 1 &pcfg_pull_none>; }; }; pwm2 { pwm2_pin: pwm2-pin { - rockchip,pins = <7 22 3 &pcfg_pull_none>; + rockchip,pins = <7 RK_PC6 3 &pcfg_pull_none>; }; }; pwm3 { pwm3_pin: pwm3-pin { - rockchip,pins = <7 23 3 &pcfg_pull_none>; + rockchip,pins = <7 RK_PC7 3 &pcfg_pull_none>; }; }; gmac { rgmii_pins: rgmii-pins { - rockchip,pins = <3 30 3 &pcfg_pull_none>, - <3 31 3 &pcfg_pull_none>, - <3 26 3 &pcfg_pull_none>, - <3 27 3 &pcfg_pull_none>, - <3 28 3 &pcfg_pull_none_12ma>, - <3 29 3 &pcfg_pull_none_12ma>, - <3 24 3 &pcfg_pull_none_12ma>, - <3 25 3 &pcfg_pull_none_12ma>, - <4 0 3 &pcfg_pull_none>, - <4 5 3 &pcfg_pull_none>, - <4 6 3 &pcfg_pull_none>, - <4 9 3 &pcfg_pull_none_12ma>, - <4 4 3 &pcfg_pull_none_12ma>, - <4 1 3 &pcfg_pull_none>, - <4 3 3 &pcfg_pull_none>; + rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>, + <3 RK_PD7 3 &pcfg_pull_none>, + <3 RK_PD2 3 &pcfg_pull_none>, + <3 RK_PD3 3 &pcfg_pull_none>, + <3 RK_PD4 3 &pcfg_pull_none_12ma>, + <3 RK_PD5 3 &pcfg_pull_none_12ma>, + <3 RK_PD0 3 &pcfg_pull_none_12ma>, + <3 RK_PD1 3 &pcfg_pull_none_12ma>, + <4 RK_PA0 3 &pcfg_pull_none>, + <4 RK_PA5 3 &pcfg_pull_none>, + <4 RK_PA6 3 &pcfg_pull_none>, + <4 RK_PB1 3 &pcfg_pull_none_12ma>, + <4 RK_PA4 3 &pcfg_pull_none_12ma>, + <4 RK_PA1 3 &pcfg_pull_none>, + <4 RK_PA3 3 &pcfg_pull_none>; }; rmii_pins: rmii-pins { - rockchip,pins = <3 30 3 &pcfg_pull_none>, - <3 31 3 &pcfg_pull_none>, - <3 28 3 &pcfg_pull_none>, - <3 29 3 &pcfg_pull_none>, - <4 0 3 &pcfg_pull_none>, - <4 5 3 &pcfg_pull_none>, - <4 4 3 &pcfg_pull_none>, - <4 1 3 &pcfg_pull_none>, - <4 2 3 &pcfg_pull_none>, - <4 3 3 &pcfg_pull_none>; + rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>, + <3 RK_PD7 3 &pcfg_pull_none>, + <3 RK_PD4 3 &pcfg_pull_none>, + <3 RK_PD5 3 &pcfg_pull_none>, + <4 RK_PA0 3 &pcfg_pull_none>, + <4 RK_PA5 3 &pcfg_pull_none>, + <4 RK_PA4 3 &pcfg_pull_none>, + <4 RK_PA1 3 &pcfg_pull_none>, + <4 RK_PA2 3 &pcfg_pull_none>, + <4 RK_PA3 3 &pcfg_pull_none>; }; }; spdif { spdif_tx: spdif-tx { - rockchip,pins = ; + rockchip,pins = <6 RK_PB3 1 &pcfg_pull_none>; }; }; }; diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index f47ac86d2852..5876690ee09e 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -682,58 +682,58 @@ emmc { emmc_bus8: emmc-bus8 { - rockchip,pins = <2 RK_PA0 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA1 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA6 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA7 RK_FUNC_2 &pcfg_pull_up_drv_8ma>; + rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up_drv_8ma>, + <2 RK_PA1 2 &pcfg_pull_up_drv_8ma>, + <2 RK_PA2 2 &pcfg_pull_up_drv_8ma>, + <2 RK_PA3 2 &pcfg_pull_up_drv_8ma>, + <2 RK_PA4 2 &pcfg_pull_up_drv_8ma>, + <2 RK_PA5 2 &pcfg_pull_up_drv_8ma>, + <2 RK_PA6 2 &pcfg_pull_up_drv_8ma>, + <2 RK_PA7 2 &pcfg_pull_up_drv_8ma>; }; emmc_clk: emmc-clk { - rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; + rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none_drv_8ma>; }; emmc_cmd: emmc-cmd { - rockchip,pins = <2 RK_PB4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>; + rockchip,pins = <2 RK_PB4 2 &pcfg_pull_up_drv_8ma>; }; }; gmac { rmii_pins: rmii-pins { - rockchip,pins = <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PC4 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PB2 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, - <1 RK_PB3 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, - <1 RK_PB4 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, - <1 RK_PB5 RK_FUNC_3 &pcfg_pull_none>, - <1 RK_PB6 RK_FUNC_3 &pcfg_pull_none>, - <1 RK_PB7 RK_FUNC_3 &pcfg_pull_none>, - <1 RK_PC2 RK_FUNC_3 &pcfg_pull_none>; + rockchip,pins = <1 RK_PC5 2 &pcfg_pull_none>, + <1 RK_PC3 2 &pcfg_pull_none>, + <1 RK_PC4 2 &pcfg_pull_none>, + <1 RK_PB2 3 &pcfg_pull_none_drv_12ma>, + <1 RK_PB3 3 &pcfg_pull_none_drv_12ma>, + <1 RK_PB4 3 &pcfg_pull_none_drv_12ma>, + <1 RK_PB5 3 &pcfg_pull_none>, + <1 RK_PB6 3 &pcfg_pull_none>, + <1 RK_PB7 3 &pcfg_pull_none>, + <1 RK_PC2 3 &pcfg_pull_none>; }; }; i2c0 { i2c0_xfer: i2c0-xfer { - rockchip,pins = <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none_smt>, - <0 RK_PB2 RK_FUNC_1 &pcfg_pull_none_smt>; + rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none_smt>, + <0 RK_PB2 1 &pcfg_pull_none_smt>; }; }; i2c1 { i2c1_xfer: i2c1-xfer { - rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>, - <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <2 RK_PD3 1 &pcfg_pull_up>, + <2 RK_PD4 1 &pcfg_pull_up>; }; }; i2c2m1 { i2c2m1_xfer: i2c2m1-xfer { - rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>, - <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC2 2 &pcfg_pull_none>, + <0 RK_PC6 3 &pcfg_pull_none>; }; i2c2m1_gpio: i2c2m1-gpio { @@ -744,8 +744,8 @@ i2c2m05v { i2c2m05v_xfer: i2c2m05v-xfer { - rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <1 RK_PD5 2 &pcfg_pull_none>, + <1 RK_PD4 2 &pcfg_pull_none>; }; i2c2m05v_gpio: i2c2m05v-gpio { @@ -756,123 +756,123 @@ i2c3 { i2c3_xfer: i2c3-xfer { - rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, - <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <0 RK_PB6 1 &pcfg_pull_none>, + <0 RK_PC4 2 &pcfg_pull_none>; }; }; pwm0 { pwm0_pin: pwm0-pin { - rockchip,pins = <0 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC5 1 &pcfg_pull_none>; }; }; pwm1 { pwm1_pin: pwm1-pin { - rockchip,pins = <0 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; }; }; pwm2 { pwm2_pin: pwm2-pin { - rockchip,pins = <0 RK_PC6 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC6 1 &pcfg_pull_none>; }; }; pwm3 { pwm3_pin: pwm3-pin { - rockchip,pins = <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC0 1 &pcfg_pull_none>; }; }; pwm4 { pwm4_pin: pwm4-pin { - rockchip,pins = <1 RK_PC1 RK_FUNC_3 &pcfg_pull_none>; + rockchip,pins = <1 RK_PC1 3 &pcfg_pull_none>; }; }; pwm5 { pwm5_pin: pwm5-pin { - rockchip,pins = <1 RK_PA7 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <1 RK_PA7 2 &pcfg_pull_none>; }; }; pwm6 { pwm6_pin: pwm6-pin { - rockchip,pins = <1 RK_PB0 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>; }; }; pwm7 { pwm7_pin: pwm7-pin { - rockchip,pins = <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <1 RK_PB1 2 &pcfg_pull_none>; }; }; sdmmc { sdmmc_clk: sdmmc-clk { - rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>; + rockchip,pins = <3 RK_PC4 1 &pcfg_pull_none_drv_4ma>; }; sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; + rockchip,pins = <3 RK_PC5 1 &pcfg_pull_up_drv_4ma>; }; sdmmc_cd: sdmmc-cd { - rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; + rockchip,pins = <0 RK_PA1 1 &pcfg_pull_up_drv_4ma>; }; sdmmc_bus1: sdmmc-bus1 { - rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; + rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>; }; sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, - <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, - <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, - <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; + rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>, + <3 RK_PC2 1 &pcfg_pull_up_drv_4ma>, + <3 RK_PC1 1 &pcfg_pull_up_drv_4ma>, + <3 RK_PC0 1 &pcfg_pull_up_drv_4ma>; }; }; spim0 { spim0_clk: spim0-clk { - rockchip,pins = <1 RK_PD0 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <1 RK_PD0 2 &pcfg_pull_up>; }; spim0_cs0: spim0-cs0 { - rockchip,pins = <1 RK_PD1 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <1 RK_PD1 2 &pcfg_pull_up>; }; spim0_tx: spim0-tx { - rockchip,pins = <1 RK_PD3 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>; }; spim0_rx: spim0-rx { - rockchip,pins = <1 RK_PD2 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>; }; }; spim1 { spim1_clk: spim1-clk { - rockchip,pins = <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>; }; spim1_cs0: spim1-cs0 { - rockchip,pins = <0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <0 RK_PA4 1 &pcfg_pull_up>; }; spim1_rx: spim1-rx { - rockchip,pins = <0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <0 RK_PB0 1 &pcfg_pull_up>; }; spim1_tx: spim1-tx { - rockchip,pins = <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <0 RK_PA7 1 &pcfg_pull_up>; }; }; tsadc { otp_out: otp-out { - rockchip,pins = <0 RK_PB7 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>; }; otp_gpio: otp-gpio { @@ -882,16 +882,16 @@ uart0 { uart0_xfer: uart0-xfer { - rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>, - <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>, + <3 RK_PA5 1 &pcfg_pull_none>; }; uart0_cts: uart0-cts { - rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>; }; uart0_rts: uart0-rts { - rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>; }; uart0_rts_gpio: uart0-rts-gpio { @@ -901,40 +901,40 @@ uart1 { uart1_xfer: uart1-xfer { - rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>, - <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PD3 1 &pcfg_pull_up>, + <1 RK_PD2 1 &pcfg_pull_none>; }; uart1_cts: uart1-cts { - rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>; }; uart1_rts: uart1-rts { - rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>; }; }; uart2m0 { uart2m0_xfer: uart2m0-xfer { - rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>, - <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PD2 1 &pcfg_pull_up>, + <2 RK_PD1 1 &pcfg_pull_none>; }; }; uart2m1 { uart2m1_xfer: uart2m1-xfer { - rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>, - <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up>, + <3 RK_PC2 2 &pcfg_pull_none>; }; }; uart2_5v { uart2_5v_cts: uart2_5v-cts { - rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>; }; uart2_5v_rts: uart2_5v-rts { - rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PD5 1 &pcfg_pull_none>; }; }; }; -- cgit From ac60c5e33df4ec2b69c7e3ebbc0ccf1557e7bd5e Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Thu, 11 Apr 2019 17:01:58 -0700 Subject: ARM: dts: rockchip: Add dynamic-power-coefficient for rk3288 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The value was determined with the following method: - take CPUs 1-3 offline - for each OPP - set cpufreq min and max freq to OPP freq - start dhrystone benchmark - measure CPU power consumption during 10s - calculate Cx for OPPx - Cx = (Px - P1) / (Vx²fx - V1²f1) [1] using the following units: mW / Ghz / V [2] - C = avg(C2, ..., Cn) [1] see commit 4daa001a1773 ("arm64: dts: juno: Add cpu dynamic-power-coefficient information") [2] https://patchwork.kernel.org/patch/10493615/#22158551 FTR, these are the values for the different OPPs: freq (kHz) mV Px (mW) Cx 126000 900 39 216000 900 66 370 312000 900 95 372 408000 900 122 363 600000 900 177 359 696000 950 230 363 816000 1000 297 361 1008000 1050 404 362 1200000 1100 528 362 1416000 1200 770 377 1512000 1300 984 385 1608000 1350 1156 394 Signed-off-by: Matthias Kaehlcke Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 23e9c5253019..884957da8700 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -64,6 +64,7 @@ #cooling-cells = <2>; /* min followed by max */ clock-latency = <40000>; clocks = <&cru ARMCLK>; + dynamic-power-coefficient = <370>; }; cpu1: cpu@501 { device_type = "cpu"; @@ -74,6 +75,7 @@ #cooling-cells = <2>; /* min followed by max */ clock-latency = <40000>; clocks = <&cru ARMCLK>; + dynamic-power-coefficient = <370>; }; cpu2: cpu@502 { device_type = "cpu"; @@ -84,6 +86,7 @@ #cooling-cells = <2>; /* min followed by max */ clock-latency = <40000>; clocks = <&cru ARMCLK>; + dynamic-power-coefficient = <370>; }; cpu3: cpu@503 { device_type = "cpu"; @@ -94,6 +97,7 @@ #cooling-cells = <2>; /* min followed by max */ clock-latency = <40000>; clocks = <&cru ARMCLK>; + dynamic-power-coefficient = <370>; }; }; -- cgit From 8a5deb4e316a5469f137e62eb1bbf6147ddbfd3d Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Thu, 11 Apr 2019 16:21:55 -0700 Subject: ARM: dts: rockchip: Add DDR retention/poweroff to rk3288-veyron hogs Even though upstream Linux doesn't yet go into deep enough suspend to get DDR into self refresh, there is no harm in setting these pins up. They'll only actually do something if we go into a deeper suspend but leaving them configed always is fine. Signed-off-by: Douglas Anderson Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi | 4 ++++ arch/arm/boot/dts/rk3288-veyron.dtsi | 4 ++++ 2 files changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi index 72c4754032e9..b9cc90f0f25c 100644 --- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi @@ -229,6 +229,8 @@ &pinctrl { pinctrl-0 = < /* Common for sleep and wake, but no owners */ + &ddr0_retention + &ddrio_pwroff &global_pwroff /* Wake only */ @@ -236,6 +238,8 @@ >; pinctrl-1 = < /* Common for sleep and wake, but no owners */ + &ddr0_retention + &ddrio_pwroff &global_pwroff /* Sleep only */ diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index e4f0c00011f2..35755870bf66 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -453,10 +453,14 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = < /* Common for sleep and wake, but no owners */ + &ddr0_retention + &ddrio_pwroff &global_pwroff >; pinctrl-1 = < /* Common for sleep and wake, but no owners */ + &ddr0_retention + &ddrio_pwroff &global_pwroff >; -- cgit From f408170d1829779188aa774ec711bf267349b13b Mon Sep 17 00:00:00 2001 From: Cao Van Dong Date: Thu, 11 Apr 2019 16:54:03 +0900 Subject: ARM: dts: r8a77470: Add HSCIF support Add hscif{0|1|2} nodes to dtsi for HSCIF support on the RZ/G1C (r8a77470) SoC. Signed-off-by: Cao Van Dong Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a77470.dtsi | 48 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index 493cf2b3f795..60bd79fc35f7 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -588,6 +588,54 @@ status = "disabled"; }; + hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a77470", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 717>, + <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 717>; + status = "disabled"; + }; + + hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a77470", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c8000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 716>, + <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + }; + + hscif2: serial@e62d0000 { + compatible = "renesas,hscif-r8a77470", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62d0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 713>, + <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, + <&dmac1 0x3b>, <&dmac1 0x3c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 713>; + status = "disabled"; + }; + sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a77470", "renesas,rcar-gen2-sdhi"; -- cgit From 3d59e55ef864f5b42bac865912df4aad56d7a67e Mon Sep 17 00:00:00 2001 From: Cao Van Dong Date: Thu, 11 Apr 2019 16:54:05 +0900 Subject: ARM: dts: r8a77470: Add PWM support Add pwm{0|1|2|3|4|5|6} nodes to dtsi for PWM support on the RZ/G1C (r8a77470) SoC. Signed-off-by: Cao Van Dong Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a77470.dtsi | 70 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index 60bd79fc35f7..c9f6e6b11e24 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -636,6 +636,76 @@ status = "disabled"; }; + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a77470", "renesas,rcar-gen2-sdhi"; -- cgit From 1631b58c7ef690869dcd4b853bf6d06ba54e74d0 Mon Sep 17 00:00:00 2001 From: Cao Van Dong Date: Tue, 9 Apr 2019 17:51:46 +0900 Subject: ARM: dts: r8a77470: Add VIN support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add vin{0|1} nodes to dtsi for VIN support on the RZ/G1C (r8a77470) SoC. Signed-off-by: Cao Van Dong Reviewed-by: Niklas Söderlund Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a77470.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index c9f6e6b11e24..2e02ff4bd4f7 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -706,6 +706,28 @@ status = "disabled"; }; + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a77470", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 811>; + status = "disabled"; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a77470", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 810>; + status = "disabled"; + }; + sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a77470", "renesas,rcar-gen2-sdhi"; -- cgit From 1a675db44002ed9674d6e534b1400a9d756ef34b Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 10 Apr 2019 15:48:45 +0100 Subject: ARM: dts: r8a77470: Add USB PHY DT support Define the r8a77470 generic part of the USB PHY device node. Signed-off-by: Biju Das Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a77470.dtsi | 56 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index 2e02ff4bd4f7..eb7c53ed077a 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -325,6 +325,42 @@ status = "disabled"; }; + usbphy0: usb-phy@e6590100 { + compatible = "renesas,usb-phy-r8a77470", + "renesas,rcar-gen2-usb-phy"; + reg = <0 0xe6590100 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cpg CPG_MOD 704>; + clock-names = "usbhs"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; + + usb0: usb-channel@0 { + reg = <0>; + #phy-cells = <1>; + }; + }; + + usbphy1: usb-phy@e6598100 { + compatible = "renesas,usb-phy-r8a77470", + "renesas,rcar-gen2-usb-phy"; + reg = <0 0xe6598100 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cpg CPG_MOD 706>; + clock-names = "usbhs"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 706>; + status = "disabled"; + + usb1: usb-channel@0 { + reg = <0>; + #phy-cells = <1>; + }; + }; + usb_dmac00: dma-controller@e65a0000 { compatible = "renesas,r8a77470-usb-dmac", "renesas,usb-dmac"; @@ -728,6 +764,26 @@ status = "disabled"; }; + usb2_phy0: usb-phy@ee080200 { + compatible = "renesas,usb2-phy-r8a77470"; + reg = <0 0xee080200 0 0x700>; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 703>; + #phy-cells = <0>; + status = "disabled"; + }; + + usb2_phy1: usb-phy@ee0c0200 { + compatible = "renesas,usb2-phy-r8a77470"; + reg = <0 0xee0c0200 0 0x700>; + clocks = <&cpg CPG_MOD 705>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 705>; + #phy-cells = <0>; + status = "disabled"; + }; + sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a77470", "renesas,rcar-gen2-sdhi"; -- cgit From e18cfb6e0418e099e42c9fb697dfba24096c90ca Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 10 Apr 2019 15:48:46 +0100 Subject: ARM: dts: iwg23s-sbc: Enable USB Phy[01] Enable USB phy[01] on iWave iwg23s sbc based on RZ/G1C SoC. Signed-off-by: Biju Das Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 32 +++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts index 9f9eb15a1e65..7ae7ee1ed199 100644 --- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts +++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts @@ -214,6 +214,16 @@ function = "sdhi2"; power-source = <1800>; }; + + usb0_pins: usb0 { + groups = "usb0"; + function = "usb0"; + }; + + usb1_pins: usb1 { + groups = "usb1"; + function = "usb1"; + }; }; &qspi0 { @@ -274,3 +284,25 @@ sd-uhs-sdr50; status = "okay"; }; + +&usb2_phy0 { + status = "okay"; +}; + +&usb2_phy1 { + status = "okay"; +}; + +&usbphy0 { + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&usbphy1 { + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; -- cgit From ce5940798cf1eb1ba70e94702cbb334ca370f96b Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 10 Apr 2019 15:48:47 +0100 Subject: ARM: dts: r8a77470: Add USB2.0 Host (EHCI/OHCI) device Define the r8a77470 generic part of the USB2.0 Host Controller device nodes (ehci[01]/ohci[01]). Signed-off-by: Biju Das Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a77470.dtsi | 50 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index eb7c53ed077a..0ad1ec092305 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -764,6 +764,31 @@ status = "disabled"; }; + ohci0: usb@ee080000 { + compatible = "generic-ohci"; + reg = <0 0xee080000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + phys = <&usb0 0>, <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + }; + + ehci0: usb@ee080100 { + compatible = "generic-ehci"; + reg = <0 0xee080100 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + phys = <&usb0 0>, <&usb2_phy0>; + phy-names = "usb"; + companion = <&ohci0>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + }; + usb2_phy0: usb-phy@ee080200 { compatible = "renesas,usb2-phy-r8a77470"; reg = <0 0xee080200 0 0x700>; @@ -774,6 +799,31 @@ status = "disabled"; }; + ohci1: usb@ee0c0000 { + compatible = "generic-ohci"; + reg = <0 0xee0c0000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 705>; + phys = <&usb0 1>, <&usb2_phy1>, <&usb1 0>; + phy-names = "usb"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 705>; + status = "disabled"; + }; + + ehci1: usb@ee0c0100 { + compatible = "generic-ehci"; + reg = <0 0xee0c0100 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 705>; + phys = <&usb0 1>, <&usb2_phy1>, <&usb1 0>; + phy-names = "usb"; + companion = <&ohci1>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 705>; + status = "disabled"; + }; + usb2_phy1: usb-phy@ee0c0200 { compatible = "renesas,usb2-phy-r8a77470"; reg = <0 0xee0c0200 0 0x700>; -- cgit From 034484c4a3c77113304c8b5e1b35a9fad048274e Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 10 Apr 2019 15:48:48 +0100 Subject: ARM: dts: iwg23s-sbc: Enable USB USB2.0 Host Enable USB2.0 host on the iwg23s sbc. Signed-off-by: Biju Das Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts index 7ae7ee1ed199..366832cc92bc 100644 --- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts +++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts @@ -106,6 +106,10 @@ }; }; +&ehci1 { + status = "okay"; +}; + &extal_clk { clock-frequency = <20000000>; }; @@ -166,6 +170,10 @@ }; }; +&ohci1 { + status = "okay"; +}; + &pfc { avb_pins: avb { groups = "avb_mdio", "avb_gmii_tx_rx"; -- cgit From 307ca5cf4778b6bf0d2a025b0e4f653742214de8 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 10 Apr 2019 15:48:49 +0100 Subject: ARM: dts: r8a77470: Add HSUSB device nodes Define the r8a77470 generic part of the HSUSB0/1 device nodes. Currently the renesas_usbhs driver doesn't handle multiple phys and we don't have a proper hardware to validate such driver changes. So for hsusb1 it is assumed that usbphy0 will be enabled by either channel0 host or device. In future, if any boards support hsusb1, we will need to add multiple phy support in the renesas_usbhs driver and override the board dts to enable the same. Signed-off-by: Biju Das Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a77470.dtsi | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index 0ad1ec092305..56cb10b42ed9 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -325,6 +325,23 @@ status = "disabled"; }; + hsusb0: hsusb@e6590000 { + compatible = "renesas,usbhs-r8a77470", + "renesas,rcar-gen2-usbhs"; + reg = <0 0xe6590000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 704>; + dmas = <&usb_dmac00 0>, <&usb_dmac00 1>, + <&usb_dmac10 0>, <&usb_dmac10 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + renesas,buswait = <4>; + phys = <&usb0 1>; + phy-names = "usb"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; + }; + usbphy0: usb-phy@e6590100 { compatible = "renesas,usb-phy-r8a77470", "renesas,rcar-gen2-usb-phy"; @@ -343,6 +360,24 @@ }; }; + hsusb1: hsusb@e6598000 { + compatible = "renesas,usbhs-r8a77470", + "renesas,rcar-gen2-usbhs"; + reg = <0 0xe6598000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 706>; + dmas = <&usb_dmac01 0>, <&usb_dmac01 1>, + <&usb_dmac11 0>, <&usb_dmac11 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + renesas,buswait = <4>; + /* We need to turn on usbphy0 to make usbphy1 to work */ + phys = <&usb1 1>; + phy-names = "usb"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 706>; + status = "disabled"; + }; + usbphy1: usb-phy@e6598100 { compatible = "renesas,usb-phy-r8a77470", "renesas,rcar-gen2-usb-phy"; -- cgit From 0725a5478e3b7080666512e6889c94bc361e7b88 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 10 Apr 2019 15:48:50 +0100 Subject: ARM: dts: iwg23s-sbc: Enable HS-USB Enable HS-USB device for the iWave SBC based on RZ/G1C. Signed-off-by: Biju Das Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts index 366832cc92bc..2840eb0d6fd4 100644 --- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts +++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts @@ -123,6 +123,10 @@ }; }; +&hsusb0 { + status = "okay"; +}; + &i2c3 { pinctrl-0 = <&i2c3_pins>; pinctrl-names = "default"; -- cgit From 7229d544c83ac7bc020db47d0a15b918f157f756 Mon Sep 17 00:00:00 2001 From: Christina Quast Date: Tue, 9 Apr 2019 18:03:32 +0200 Subject: ARM: dts: am335x: baltos-ir2110: Replaced register offsets with defines The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-baltos-ir2110.dts | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-baltos-ir2110.dts b/arch/arm/boot/dts/am335x-baltos-ir2110.dts index 50dcf1290ac6..2f650a736b44 100644 --- a/arch/arm/boot/dts/am335x-baltos-ir2110.dts +++ b/arch/arm/boot/dts/am335x-baltos-ir2110.dts @@ -23,14 +23,14 @@ &am33xx_pinmux { uart1_pins: pinmux_uart1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0) /* uart1_rxd */ - AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE0) /* uart1_txd */ - AM33XX_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart1_ctsn */ - AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn */ - AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */ - AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */ - AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */ - AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */ + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */ + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */ + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */ + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */ >; }; }; -- cgit From a48d48e6535b3f1247b30bd55d79ed776ebf08e6 Mon Sep 17 00:00:00 2001 From: Christina Quast Date: Tue, 9 Apr 2019 18:03:33 +0200 Subject: ARM: dts: am335x: baltos-ir3220: Replaced register offsets with defines The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-baltos-ir3220.dts | 38 +++++++++++++++--------------- 1 file changed, 19 insertions(+), 19 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-baltos-ir3220.dts b/arch/arm/boot/dts/am335x-baltos-ir3220.dts index f3f1abd26470..1ba66d5e21e8 100644 --- a/arch/arm/boot/dts/am335x-baltos-ir3220.dts +++ b/arch/arm/boot/dts/am335x-baltos-ir3220.dts @@ -23,35 +23,35 @@ &am33xx_pinmux { tca6416_pins: pinmux_tca6416_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT_PULLUP, MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */ >; }; uart1_pins: pinmux_uart1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0) /* uart1_rxd */ - AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE0) /* uart1_txd */ - AM33XX_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart1_ctsn */ - AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn */ - AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */ - AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */ - AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */ - AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */ + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */ + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */ + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */ + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */ >; }; uart2_pins: pinmux_uart2_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1) /* spi0_sclk.uart2_rxd_mux3 */ - AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1) /* spi0_d0.uart2_txd_mux3 */ - AM33XX_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE2) /* i2c0_sda.uart2_ctsn_mux0 */ - AM33XX_IOPAD(0x98c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* i2c0_scl.uart2_rtsn_mux0 */ - AM33XX_IOPAD(0x830, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.gpio1[12] DTR */ - AM33XX_IOPAD(0x834, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.gpio1[13] DSR */ - AM33XX_IOPAD(0x838, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.gpio1[14] DCD */ - AM33XX_IOPAD(0x83c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.gpio1[15] RI */ - - AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */ + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* spi0_sclk.uart2_rxd_mux3 */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* spi0_d0.uart2_txd_mux3 */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE2) /* i2c0_sda.uart2_ctsn_mux0 */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* i2c0_scl.uart2_rtsn_mux0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad12.gpio1[12] DTR */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad13.gpio1[13] DSR */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad14.gpio1[14] DCD */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad15.gpio1[15] RI */ + + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */ >; }; }; -- cgit From f6385bd149ecd5c40b01874e5599b697d7d9daa4 Mon Sep 17 00:00:00 2001 From: Christina Quast Date: Tue, 9 Apr 2019 18:03:34 +0200 Subject: ARM: dts: am335x: baltos-ir5221: Replaced register offsets with defines The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-baltos-ir5221.dts | 42 +++++++++++++++--------------- 1 file changed, 21 insertions(+), 21 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-baltos-ir5221.dts b/arch/arm/boot/dts/am335x-baltos-ir5221.dts index 42f473f0ed77..eed65fc0e8e6 100644 --- a/arch/arm/boot/dts/am335x-baltos-ir5221.dts +++ b/arch/arm/boot/dts/am335x-baltos-ir5221.dts @@ -23,43 +23,43 @@ &am33xx_pinmux { tca6416_pins: pinmux_tca6416_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT_PULLUP, MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */ >; }; dcan1_pins: pinmux_dcan1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.dcan1_tx_mux0 */ - AM33XX_IOPAD(0x96c, PIN_INPUT | MUX_MODE2) /* uart0_rtsn.dcan1_rx_mux0 */ + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart0_ctsn.dcan1_tx_mux0 */ + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2) /* uart0_rtsn.dcan1_rx_mux0 */ >; }; uart1_pins: pinmux_uart1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0) /* uart1_rxd */ - AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE0) /* uart1_txd */ - AM33XX_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart1_ctsn */ - AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn */ - AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */ - AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */ - AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */ - AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */ + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */ + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */ + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */ + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */ >; }; uart2_pins: pinmux_uart2_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1) /* spi0_sclk.uart2_rxd_mux3 */ - AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1) /* spi0_d0.uart2_txd_mux3 */ - AM33XX_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE2) /* i2c0_sda.uart2_ctsn_mux0 */ - AM33XX_IOPAD(0x98c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* i2c0_scl.uart2_rtsn_mux0 */ - AM33XX_IOPAD(0x830, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.gpio1[12] DTR */ - AM33XX_IOPAD(0x834, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.gpio1[13] DSR */ - AM33XX_IOPAD(0x838, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.gpio1[14] DCD */ - AM33XX_IOPAD(0x83c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.gpio1[15] RI */ - - AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */ + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* spi0_sclk.uart2_rxd_mux3 */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* spi0_d0.uart2_txd_mux3 */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE2) /* i2c0_sda.uart2_ctsn_mux0 */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* i2c0_scl.uart2_rtsn_mux0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad12.gpio1[12] DTR */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad13.gpio1[13] DSR */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad14.gpio1[14] DCD */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad15.gpio1[15] RI */ + + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */ >; }; -- cgit From 8ce8c4b31a826f3c519adfb8079059b2b5300d90 Mon Sep 17 00:00:00 2001 From: Christina Quast Date: Tue, 9 Apr 2019 18:03:35 +0200 Subject: ARM: dts: am335x: baltos-leds: Replaced register offsets with defines The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-baltos-leds.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-baltos-leds.dtsi b/arch/arm/boot/dts/am335x-baltos-leds.dtsi index 3ab1767d5c13..fe75050c016f 100644 --- a/arch/arm/boot/dts/am335x-baltos-leds.dtsi +++ b/arch/arm/boot/dts/am335x-baltos-leds.dtsi @@ -42,9 +42,9 @@ &am33xx_pinmux { user_leds: pinmux_user_leds { pinctrl-single,pins = < - AM33XX_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mii1_col.gpio3_0 PWR LED */ - AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mii1_txd3.gpio0_16 WLAN LED */ - AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mii1_txd2.gpio0_17 APP LED */ + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mii1_col.gpio3_0 PWR LED */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mii1_txd3.gpio0_16 WLAN LED */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mii1_txd2.gpio0_17 APP LED */ >; }; }; -- cgit From 11ce1e08971e1fcb8409a8766be79cb259811a0d Mon Sep 17 00:00:00 2001 From: Christina Quast Date: Tue, 9 Apr 2019 18:03:36 +0200 Subject: ARM: dts: am335x: baltos: Replaced register offsets with defines The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-baltos.dtsi | 140 +++++++++++++++++------------------ 1 file changed, 70 insertions(+), 70 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-baltos.dtsi b/arch/arm/boot/dts/am335x-baltos.dtsi index 8c6fc4161ad7..b572ad1f1377 100644 --- a/arch/arm/boot/dts/am335x-baltos.dtsi +++ b/arch/arm/boot/dts/am335x-baltos.dtsi @@ -53,130 +53,130 @@ &am33xx_pinmux { mmc2_pins: pinmux_mmc2_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad8.mmc1_dat0_mux0 */ - AM33XX_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad9.mmc1_dat1_mux0 */ - AM33XX_IOPAD(0x828, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad10.mmc1_dat2_mux0 */ - AM33XX_IOPAD(0x82c, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad11.mmc1_dat3_mux0 */ - AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk_mux0 */ - AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd_mux0 */ - AM33XX_IOPAD(0x9e4, PIN_INPUT_PULLUP | MUX_MODE7) /* emu0.gpio3[7] */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad8.mmc1_dat0_mux0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad9.mmc1_dat1_mux0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad10.mmc1_dat2_mux0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad11.mmc1_dat3_mux0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk_mux0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd_mux0 */ + AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_INPUT_PULLUP, MUX_MODE7) /* emu0.gpio3[7] */ >; }; wl12xx_gpio: pinmux_wl12xx_gpio { pinctrl-single,pins = < - AM33XX_IOPAD(0x9e8, PIN_OUTPUT_PULLUP | MUX_MODE7) /* emu1.gpio3[8] */ + AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_OUTPUT_PULLUP, MUX_MODE7) /* emu1.gpio3[8] */ >; }; tps65910_pins: pinmux_tps65910_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ben1.gpio1[28] */ + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_ben1.gpio1[28] */ >; }; i2c1_pins: pinmux_i2c1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x958, PIN_INPUT | MUX_MODE2) /* spi0_d1.i2c1_sda_mux3 */ - AM33XX_IOPAD(0x95c, PIN_INPUT | MUX_MODE2) /* spi0_cs0.i2c1_scl_mux3 */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE2) /* spi0_d1.i2c1_sda_mux3 */ + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT, MUX_MODE2) /* spi0_cs0.i2c1_scl_mux3 */ >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ - AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ - AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_tx_en.rmii1_txen */ - AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ - AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk */ + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_tx_en.rmii1_txen */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk */ /* Slave 2 */ - AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ - AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ - AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ - AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ - AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ - AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ - AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ - AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ - AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ - AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ - AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ - AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ - AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* Slave 2 reset value*/ - AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) /* mdio_data.mdio_data */ + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) /* mdio_clk.mdio_clk */ >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; nandflash_pins_s0: nandflash_pins_s0 { pinctrl-single,pins = < - AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ - AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ - AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ - AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ - AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ - AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ - AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ - AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ - AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ - AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */ - AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ - AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ - AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ - AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ - AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_30 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ + AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) /* gpmc_wen.gpmc_wen */ + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ >; }; }; -- cgit From 0b119fafc882e23f47968ec5ec2e13ae745b5d6e Mon Sep 17 00:00:00 2001 From: Christina Quast Date: Tue, 9 Apr 2019 18:03:37 +0200 Subject: ARM: dts: am335x: base0033: Replaced register offsets with defines The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-base0033.dts | 48 +++++++++++++++++------------------ 1 file changed, 24 insertions(+), 24 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-base0033.dts b/arch/arm/boot/dts/am335x-base0033.dts index 29782be07605..cbd5bd8c57de 100644 --- a/arch/arm/boot/dts/am335x-base0033.dts +++ b/arch/arm/boot/dts/am335x-base0033.dts @@ -46,39 +46,39 @@ &am33xx_pinmux { nxp_hdmi_pins: pinmux_nxp_hdmi_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE3) /* xdma_event_intr0.clkout1 */ - AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0 */ - AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1 */ - AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2 */ - AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3 */ - AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4 */ - AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5 */ - AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6 */ - AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7 */ - AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8 */ - AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9 */ - AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10 */ - AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11 */ - AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12 */ - AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13 */ - AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14 */ - AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15 */ - AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* lcd_vsync */ - AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* lcd_hsync */ - AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* lcd_pclk */ - AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE3) /* xdma_event_intr0.clkout1 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) >; }; nxp_hdmi_off_pins: pinmux_nxp_hdmi_off_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE3) /* xdma_event_intr0.clkout1 */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE3) /* xdma_event_intr0.clkout1 */ >; }; leds_base_pins: pinmux_leds_base_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ - AM33XX_IOPAD(0x888, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.gpio2_0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_csn3.gpio2_0 */ >; }; }; -- cgit From ada077fa906e26bfc8665901ccd351e7dfd188b4 Mon Sep 17 00:00:00 2001 From: Christina Quast Date: Tue, 9 Apr 2019 18:03:38 +0200 Subject: ARM: dts: am335x: bonegreen-wireless: Replaced register offsets with defines The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-bonegreen-wireless.dts | 28 ++++++++++++------------- 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-bonegreen-wireless.dts b/arch/arm/boot/dts/am335x-bonegreen-wireless.dts index 57731f0daf10..7db86a9c836a 100644 --- a/arch/arm/boot/dts/am335x-bonegreen-wireless.dts +++ b/arch/arm/boot/dts/am335x-bonegreen-wireless.dts @@ -32,35 +32,35 @@ &am33xx_pinmux { bt_pins: pinmux_bt_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x878, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_ad12.gpio1_28 BT_EN */ + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_ad12.gpio1_28 BT_EN */ >; }; mmc3_pins: pinmux_mmc3_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad12.mmc2_dat0 */ - AM33XX_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad13.mmc2_dat1 */ - AM33XX_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad14.mmc2_dat2 */ - AM33XX_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad15.mmc2_dat3 */ - AM33XX_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ - AM33XX_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad12.mmc2_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad13.mmc2_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad14.mmc2_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad15.mmc2_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc2_clk */ >; }; uart3_pins: pinmux_uart3_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE1) /* gmii1_rxd3.uart3_rxd */ - AM33XX_IOPAD(0x938, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gmii1_rxd2.uart3_txd */ - AM33XX_IOPAD(0x948, PIN_INPUT | MUX_MODE3) /* mdio_data.uart3_ctsn */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* mdio_clk.uart3_rtsn */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gmii1_rxd3.uart3_rxd */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* gmii1_rxd2.uart3_txd */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT, MUX_MODE3) /* mdio_data.uart3_ctsn */ + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* mdio_clk.uart3_rtsn */ >; }; wl18xx_pins: pinmux_wl18xx_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x828, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad10.gpio0_26 WL_EN */ - AM33XX_IOPAD(0x82C, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad11.gpio0_27 WL_IRQ */ - AM33XX_IOPAD(0x87C, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_csn0.gpio1_29 LS_BUF_EN */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad10.gpio0_26 WL_EN */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad11.gpio0_27 WL_IRQ */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_csn0.gpio1_29 LS_BUF_EN */ >; }; }; -- cgit From 9faf08c2e677a391f23c09e22e00fdbce22ae5f9 Mon Sep 17 00:00:00 2001 From: Christina Quast Date: Tue, 9 Apr 2019 18:03:39 +0200 Subject: ARM: dts: am335x: boneblue: Replaced register offsets with defines The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-boneblue.dts | 104 +++++++++++++++++----------------- 1 file changed, 52 insertions(+), 52 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-boneblue.dts b/arch/arm/boot/dts/am335x-boneblue.dts index ccb147e70d17..8d241c856c8d 100644 --- a/arch/arm/boot/dts/am335x-boneblue.dts +++ b/arch/arm/boot/dts/am335x-boneblue.dts @@ -130,135 +130,135 @@ &am33xx_pinmux { user_leds_s0: user_leds_s0 { pinctrl-single,pins = < - AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7) /* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */ - AM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7) /* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */ - AM33XX_IOPAD(0x85c, PIN_OUTPUT | MUX_MODE7) /* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */ - AM33XX_IOPAD(0x860, PIN_OUTPUT | MUX_MODE7) /* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */ - AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] - WIFI_LED */ - AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE7) /* (R7) gpmc_advn_ale.gpio2[2] - P8.7, LED_RED, GP1_PIN_5 */ - AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE7) /* (T7) gpmc_oen_ren.gpio2[3] - P8.8, LED_GREEN, GP1_PIN_6 */ - AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE7) /* (U12) gpmc_ad11.gpio0[27] - P8.17, BATT_LED_1 */ - AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE7) /* (T5) lcd_data15.gpio0[11] - P8.32, BATT_LED_2 */ - AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE7) /* (V6) gpmc_csn0.gpio1[29] - P8.26, BATT_LED_3 */ - AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE7) /* (T11) gpmc_ad10.gpio0[26] - P8.14, BATT_LED_4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) /* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7) /* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7) /* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] - WIFI_LED */ + AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE7) /* (R7) gpmc_advn_ale.gpio2[2] - P8.7, LED_RED, GP1_PIN_5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE7) /* (T7) gpmc_oen_ren.gpio2[3] - P8.8, LED_GREEN, GP1_PIN_6 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE7) /* (U12) gpmc_ad11.gpio0[27] - P8.17, BATT_LED_1 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE7) /* (T5) lcd_data15.gpio0[11] - P8.32, BATT_LED_2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE7) /* (V6) gpmc_csn0.gpio1[29] - P8.26, BATT_LED_3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7) /* (T11) gpmc_ad10.gpio0[26] - P8.14, BATT_LED_4 */ >; }; i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* (C17) I2C0_SDA.I2C0_SDA */ - AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* (C16) I2C0_SCL.I2C0_SCL */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) /* (C17) I2C0_SDA.I2C0_SDA */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) /* (C16) I2C0_SCL.I2C0_SCL */ >; }; i2c2_pins: pinmux_i2c2_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE3) /* (D18) uart1_ctsn.I2C2_SDA */ - AM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE3) /* (D17) uart1_rtsn.I2C2_SCL */ + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D18) uart1_ctsn.I2C2_SDA */ + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D17) uart1_rtsn.I2C2_SCL */ >; }; /* UT0 */ uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* (E15) uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* (E16) uart0_txd.uart0_txd */ + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; /* UT1 */ uart1_pins: pinmux_uart1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* (D16) uart1_rxd.uart1_rxd */ - AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* (D15) uart1_txd.uart1_txd */ + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; /* GPS */ uart2_pins: pinmux_uart2_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE1) /* (A17) spi0_sclk.uart2_rxd */ - AM33XX_IOPAD(0x954, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* (B17) spi0_d0.uart2_txd */ + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE1) /* (A17) spi0_sclk.uart2_rxd */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* (B17) spi0_d0.uart2_txd */ >; }; /* DSM2 */ uart4_pins: pinmux_uart4_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6) /* (T17) gpmc_wait0.uart4_rxd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) /* (T17) gpmc_wait0.uart4_rxd */ >; }; /* UT5 */ uart5_pins: pinmux_uart5_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x8C4, PIN_INPUT_PULLUP | MUX_MODE4) /* (U2) lcd_data9.uart5_rxd */ - AM33XX_IOPAD(0x8C0, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* (U1) lcd_data8.uart5_txd */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_INPUT_PULLUP, MUX_MODE4) /* (U2) lcd_data9.uart5_rxd */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* (U1) lcd_data8.uart5_txd */ >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */ + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */ >; }; mmc2_pins: pinmux_mmc2_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* (U9) gpmc_csn1.mmc1_clk */ - AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* (V9) gpmc_csn2.mmc1_cmd */ - AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* (U7) gpmc_ad0.mmc1_dat0 */ - AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* (V7) gpmc_ad1.mmc1_dat1 */ - AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* (R8) gpmc_ad2.mmc1_dat2 */ - AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* (T8) gpmc_ad3.mmc1_dat3 */ - AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* (U8) gpmc_ad4.mmc1_dat4 */ - AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* (V8) gpmc_ad5.mmc1_dat5 */ - AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* (R9) gpmc_ad6.mmc1_dat6 */ - AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* (T9) gpmc_ad7.mmc1_dat7 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* (U9) gpmc_csn1.mmc1_clk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* (V9) gpmc_csn2.mmc1_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* (U7) gpmc_ad0.mmc1_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* (V7) gpmc_ad1.mmc1_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* (R8) gpmc_ad2.mmc1_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* (T8) gpmc_ad3.mmc1_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* (U8) gpmc_ad4.mmc1_dat4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* (V8) gpmc_ad5.mmc1_dat5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* (R9) gpmc_ad6.mmc1_dat6 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* (T9) gpmc_ad7.mmc1_dat7 */ >; }; mmc3_pins: pinmux_mmc3_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE6) /* (L15) gmii1_rxd1.mmc2_clk */ - AM33XX_IOPAD(0x914, PIN_INPUT_PULLUP | MUX_MODE6) /* (J16) gmii1_txen.mmc2_cmd */ - AM33XX_IOPAD(0x918, PIN_INPUT_PULLUP | MUX_MODE5) /* (J17) gmii1_rxdv.mmc2_dat0 */ - AM33XX_IOPAD(0x91c, PIN_INPUT_PULLUP | MUX_MODE5) /* (J18) gmii1_txd3.mmc2_dat1 */ - AM33XX_IOPAD(0x920, PIN_INPUT_PULLUP | MUX_MODE5) /* (K15) gmii1_txd2.mmc2_dat2 */ - AM33XX_IOPAD(0x908, PIN_INPUT_PULLUP | MUX_MODE5) /* (H16) gmii1_col.mmc2_dat3 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE6) /* (L15) gmii1_rxd1.mmc2_clk */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLUP, MUX_MODE6) /* (J16) gmii1_txen.mmc2_cmd */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE5) /* (J17) gmii1_rxdv.mmc2_dat0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLUP, MUX_MODE5) /* (J18) gmii1_txd3.mmc2_dat1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLUP, MUX_MODE5) /* (K15) gmii1_txd2.mmc2_dat2 */ + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE5) /* (H16) gmii1_col.mmc2_dat3 */ >; }; bt_pins: pinmux_bt_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLUP | MUX_MODE7) /* (K17) gmii1_txd0.gpio0[28] - BT_EN */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* (K17) gmii1_txd0.gpio0[28] - BT_EN */ >; }; uart3_pins: pinmux_uart3_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */ - AM33XX_IOPAD(0x938, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */ - AM33XX_IOPAD(0x948, PIN_INPUT | MUX_MODE3) /* (M17) mdio_data.uart3_ctsn */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* (M18) mdio_clk.uart3_rtsn */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT, MUX_MODE3) /* (M17) mdio_data.uart3_ctsn */ + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* (M18) mdio_clk.uart3_rtsn */ >; }; wl18xx_pins: pinmux_wl18xx_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] - WL_EN */ - AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (K16) gmii1_txd1.gpio0[21] - WL_IRQ */ - AM33XX_IOPAD(0x930, PIN_OUTPUT_PULLUP | MUX_MODE7) /* (L18) gmii1_rxclk.gpio3[10] - LS_BUF_EN */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] - WL_EN */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* (K16) gmii1_txd1.gpio0[21] - WL_IRQ */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7) /* (L18) gmii1_rxclk.gpio3[10] - LS_BUF_EN */ >; }; /* DCAN */ dcan1_pins: pinmux_dcan1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x96c, PIN_INPUT | MUX_MODE2) /* (E17) uart0_rtsn.dcan1_rx */ - AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE2) /* (E18) uart0_ctsn.dcan1_tx */ - AM33XX_IOPAD(0x940, PIN_OUTPUT | MUX_MODE7) /* (M16) gmii1_rxd0.gpio2[21] */ + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2) /* (E17) uart0_rtsn.dcan1_rx */ + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* (E18) uart0_ctsn.dcan1_tx */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_OUTPUT, MUX_MODE7) /* (M16) gmii1_rxd0.gpio2[21] */ >; }; }; -- cgit From e52a7204cdd3e49a6e609a6dc56593a091ad56eb Mon Sep 17 00:00:00 2001 From: Christina Quast Date: Tue, 9 Apr 2019 18:03:40 +0200 Subject: ARM: dts: am335x: bonegreen-common: Replaced register offsets with defines The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-bonegreen-common.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-bonegreen-common.dtsi b/arch/arm/boot/dts/am335x-bonegreen-common.dtsi index 853e6d3a028d..71317e372ec7 100644 --- a/arch/arm/boot/dts/am335x-bonegreen-common.dtsi +++ b/arch/arm/boot/dts/am335x-bonegreen-common.dtsi @@ -27,8 +27,8 @@ &am33xx_pinmux { uart2_pins: uart2_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1) /* spi0_sclk.uart2_rxd */ - AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1) /* spi0_d0.uart2_txd */ + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* spi0_sclk.uart2_rxd */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* spi0_d0.uart2_txd */ >; }; }; -- cgit From 4e5835effc3d5dcfd695413c59a59ec3335ac5ad Mon Sep 17 00:00:00 2001 From: Christina Quast Date: Tue, 9 Apr 2019 18:03:41 +0200 Subject: ARM: dts: am335x: chiliboard: Replaced register offsets with defines The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-chiliboard.dts | 66 ++++++++++++++++----------------- 1 file changed, 33 insertions(+), 33 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-chiliboard.dts b/arch/arm/boot/dts/am335x-chiliboard.dts index bffa5dce54ec..31da68355e57 100644 --- a/arch/arm/boot/dts/am335x-chiliboard.dts +++ b/arch/arm/boot/dts/am335x-chiliboard.dts @@ -41,79 +41,79 @@ &am33xx_pinmux { uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ - AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */ - AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ - AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ - AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ - AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ - AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii_ref_clk */ + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ - AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* mdio_data.mdio_data */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) /* mdio_clk.mdio_clk */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; usb1_drvvbus: usb1_drvvbus { pinctrl-single,pins = < - AM33XX_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb1_drvvbus.usb1_drvvbus */ + AM33XX_PADCONF(AM335X_PIN_USB1_DRVVBUS, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; sd_pins: pinmux_sd_card { pinctrl-single,pins = < - AM33XX_IOPAD(0x8f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ - AM33XX_IOPAD(0x8f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ - AM33XX_IOPAD(0x8f8, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ - AM33XX_IOPAD(0x8fc, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ - AM33XX_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ - AM33XX_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ - AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */ >; }; led_gpio_pins: led_gpio_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x9e4, PIN_OUTPUT | MUX_MODE7) /* emu0.gpio3_7 */ - AM33XX_IOPAD(0x9e8, PIN_OUTPUT | MUX_MODE7) /* emu1.gpio3_8 */ + AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_OUTPUT, MUX_MODE7) /* emu0.gpio3_7 */ + AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_OUTPUT, MUX_MODE7) /* emu1.gpio3_8 */ >; }; }; -- cgit From 125a6f3c58e3986fbcc49a68db8184b8accdb14e Mon Sep 17 00:00:00 2001 From: Christina Quast Date: Tue, 9 Apr 2019 18:03:42 +0200 Subject: ARM: dts: am335x: chilisom: Replaced register offsets with defines The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-chilisom.dtsi | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-chilisom.dtsi b/arch/arm/boot/dts/am335x-chilisom.dtsi index 1b43ebd08b38..8b88bf6dafc4 100644 --- a/arch/arm/boot/dts/am335x-chilisom.dtsi +++ b/arch/arm/boot/dts/am335x-chilisom.dtsi @@ -30,28 +30,28 @@ i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; nandflash_pins: nandflash_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ - AM33XX_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ - AM33XX_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ - AM33XX_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ - AM33XX_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ - AM33XX_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ - AM33XX_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ - AM33XX_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ - - AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ - AM33XX_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ - AM33XX_IOPAD(0x890, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ - AM33XX_IOPAD(0x894, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ - AM33XX_IOPAD(0x898, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_wen.gpmc_wen */ - AM33XX_IOPAD(0x89c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLDOWN, MUX_MODE0) + + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; }; -- cgit From 6c4f9ebf86dbc7f73ecb21d005d6a28d844bb7e8 Mon Sep 17 00:00:00 2001 From: Christina Quast Date: Tue, 9 Apr 2019 18:03:43 +0200 Subject: ARM: dts: am335x: cm-t335: Replaced register offsets with defines The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-cm-t335.dts | 190 ++++++++++++++--------------------- 1 file changed, 77 insertions(+), 113 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-cm-t335.dts b/arch/arm/boot/dts/am335x-cm-t335.dts index 2c724bb60417..3b0bb88dfc12 100644 --- a/arch/arm/boot/dts/am335x-cm-t335.dts +++ b/arch/arm/boot/dts/am335x-cm-t335.dts @@ -94,108 +94,85 @@ i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < - /* i2c0_sda.i2c0_sda */ - AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) - /* i2c0_scl.i2c0_scl */ - AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; i2c1_pins: pinmux_i2c1_pins { pinctrl-single,pins = < /* uart0_ctsn.i2c1_sda */ - AM33XX_IOPAD(0x968, PIN_INPUT_PULLUP | MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE2) /* uart0_rtsn.i2c1_scl */ - AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) >; }; gpio_led_pins: pinmux_gpio_led_pins { pinctrl-single,pins = < /* gpmc_csn3.gpio2_0 */ - AM33XX_IOPAD(0x888, PIN_OUTPUT | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_OUTPUT, MUX_MODE7) >; }; nandflash_pins: pinmux_nandflash_pins { pinctrl-single,pins = < - /* gpmc_ad0.gpmc_ad0 */ - AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) - /* gpmc_ad1.gpmc_ad1 */ - AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) - /* gpmc_ad2.gpmc_ad2 */ - AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) - /* gpmc_ad3.gpmc_ad3 */ - AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) - /* gpmc_ad4.gpmc_ad4 */ - AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) - /* gpmc_ad5.gpmc_ad5 */ - AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) - /* gpmc_ad6.gpmc_ad6 */ - AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) - /* gpmc_ad7.gpmc_ad7 */ - AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) - /* gpmc_wait0.gpmc_wait0 */ - AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_wpn.gpio0_30 */ - AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) - /* gpmc_csn0.gpmc_csn0 */ - AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) - /* gpmc_advn_ale.gpmc_advn_ale */ - AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) - /* gpmc_oen_ren.gpmc_oen_ren */ - AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) - /* gpmc_wen.gpmc_wen */ - AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) - /* gpmc_ben0_cle.gpmc_ben0_cle */ - AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < - /* uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) - /* uart0_txd.uart0_txd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; uart1_pins: pinmux_uart1_pins { pinctrl-single,pins = < - /* uart1_ctsn.uart1_ctsn */ - AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0) - /* uart1_rtsn.uart1_rtsn */ - AM33XX_IOPAD(0x97C, PIN_OUTPUT_PULLDOWN | MUX_MODE0) - /* uart1_rxd.uart1_rxd */ - AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) - /* uart1_txd.uart1_txd */ - AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; dcan0_pins: pinmux_dcan0_pins { pinctrl-single,pins = < /* uart1_ctsn.dcan0_tx */ - AM33XX_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart1_rtsn.dcan0_rx */ - AM33XX_IOPAD(0x97C, PIN_INPUT | MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT, MUX_MODE2) >; }; dcan1_pins: pinmux_dcan1_pins { pinctrl-single,pins = < /* uart1_rxd.dcan1_tx */ - AM33XX_IOPAD(0x980, PIN_OUTPUT | MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_OUTPUT, MUX_MODE2) /* uart1_txd.dcan1_rx */ - AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE2) >; }; ecap0_pins: pinmux_ecap0_pins { pinctrl-single,pins = < - /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ - AM33XX_IOPAD(0x964, 0x0) + AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, 0x0, MUX_MODE0) >; }; @@ -203,96 +180,83 @@ pinctrl-single,pins = < /* Slave 1 */ /* mii1_tx_en.rgmii1_tctl */ - AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ - AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ - AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ - AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ - AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ - AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ - AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ - AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ - AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ - AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ - AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < - /* mdio_data.mdio_data */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) - /* mdio_clk.mdio_clk */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < - /* mmc0_dat3.mmc0_dat3 */ - AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) - /* mmc0_dat2.mmc0_dat2 */ - AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) - /* mmc0_dat1.mmc0_dat1 */ - AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) - /* mmc0_dat0.mmc0_dat0 */ - AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) - /* mmc0_clk.mmc0_clk */ - AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) - /* mmc0_cmd.mmc0_cmd */ - AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) >; }; spi0_pins: pinmux_spi0_pins { pinctrl-single,pins = < - /* spi0_sclk.spi0_sclk */ - AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE0) - /* spi0_d0.spi0_d0 */ - AM33XX_IOPAD(0x954, PIN_OUTPUT_PULLUP | MUX_MODE0) - /* spi0_d1.spi0_d1 */ - AM33XX_IOPAD(0x958, PIN_INPUT | MUX_MODE0) - /* spi0_cs0.spi0_cs0 */ - AM33XX_IOPAD(0x95C, PIN_OUTPUT | MUX_MODE0) - /* spi0_cs1.spi0_cs1 */ - AM33XX_IOPAD(0x960, PIN_OUTPUT | MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_OUTPUT, MUX_MODE0) >; }; @@ -300,7 +264,7 @@ bluetooth_pins: pinmux_bluetooth_pins { pinctrl-single,pins = < /* XDMA_EVENT_INTR0.gpio0_19 - bluetooth enable */ - AM33XX_IOPAD(0x9b0, PIN_OUTPUT_PULLUP | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLUP, MUX_MODE7) >; }; @@ -308,13 +272,13 @@ mcasp1_pins: pinmux_mcasp1_pins { pinctrl-single,pins = < /* MII1_CRS.mcasp1_aclkx */ - AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* MII1_RX_ER.mcasp1_fsx */ - AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* MII1_COL.mcasp1_axr2 */ - AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE4) + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE4) /* RMII1_REF_CLK.mcasp1_axr3 */ - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) >; }; @@ -322,9 +286,9 @@ wifi_pins: pinmux_wifi_pins { pinctrl-single,pins = < /* EMU1.gpio3_8 - WiFi IRQ */ - AM33XX_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_INPUT_PULLUP, MUX_MODE7) /* XDMA_EVENT_INTR1.gpio0_20 - WiFi enable */ - AM33XX_IOPAD(0x9b4, PIN_OUTPUT | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT, MUX_MODE7) >; }; }; -- cgit From ef2791fd13c3f3517ab56cb747db8854c6954ec6 Mon Sep 17 00:00:00 2001 From: Christina Quast Date: Tue, 9 Apr 2019 18:03:44 +0200 Subject: ARM: dts: am335x: evm: Replaced register offsets with defines The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-evm.dts | 234 +++++++++++++++++++-------------------- 1 file changed, 117 insertions(+), 117 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index dce5be5df97b..e9f4b28ae99c 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -172,222 +172,222 @@ matrix_keypad_s0: matrix_keypad_s0 { pinctrl-single,pins = < - AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ - AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */ - AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */ - AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */ - AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a6.gpio1_22 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a9.gpio1_25 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a10.gpio1_26 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.gpio1_27 */ >; }; volume_keys_s0: volume_keys_s0 { pinctrl-single,pins = < - AM33XX_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */ - AM33XX_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */ + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* spi0_sclk.gpio0_2 */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* spi0_d0.gpio0_3 */ >; }; i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_sda.i2c0_sda */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_scl.i2c0_scl */ >; }; i2c1_pins: pinmux_i2c1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */ - AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d1.i2c1_sda */ + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_cs0.i2c1_scl */ >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; uart1_pins: pinmux_uart1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */ - AM33XX_IOPAD(0x97C, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */ - AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ - AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; clkout2_pin: pinmux_clkout2_pin { pinctrl-single,pins = < - AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ >; }; nandflash_pins_s0: nandflash_pins_s0 { pinctrl-single,pins = < - AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ - AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ - AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ - AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ - AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ - AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ - AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ - AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ - AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ - AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */ - AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ - AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ - AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ - AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ - AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_30 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) >; }; ecap0_pins: backlight_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */ + AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, 0x0, MUX_MODE0) >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ - AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ - AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ - AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ - AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ - AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ - AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ - AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ - AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ - AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ - AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ - AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ - AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ - AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ - AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ - AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ - AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ - AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ - AM33XX_IOPAD(0x9a0, PIN_INPUT | MUX_MODE4) /* mcasp0_aclkr.mmc0_sdwp */ + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT, MUX_MODE4) /* mcasp0_aclkr.mmc0_sdwp */ >; }; mmc3_pins: pinmux_mmc3_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */ - AM33XX_IOPAD(0x848, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */ - AM33XX_IOPAD(0x84c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */ - AM33XX_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */ - AM33XX_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */ - AM33XX_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */ >; }; wlan_pins: pinmux_wlan_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 */ - AM33XX_IOPAD(0x99c, PIN_INPUT | MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */ - AM33XX_IOPAD(0x9ac, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a0.gpio1_16 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_INPUT, MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 */ >; }; lcd_pins_s0: lcd_pins_s0 { pinctrl-single,pins = < - AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */ - AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */ - AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */ - AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */ - AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */ - AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */ - AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */ - AM33XX_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */ - AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ - AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ - AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ - AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ - AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ - AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ - AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ - AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ - AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ - AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ - AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ - AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ - AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ - AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ - AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ - AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ - AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */ - AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */ - AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */ - AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad8.lcd_data23 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad9.lcd_data22 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad10.lcd_data21 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad11.lcd_data20 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad12.lcd_data19 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad13.lcd_data18 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad14.lcd_data17 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad15.lcd_data16 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) >; }; mcasp1_pins: mcasp1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ - AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ - AM33XX_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* mii1_col.mcasp1_axr2 */ + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ >; }; mcasp1_pins_sleep: mcasp1_pins_sleep { pinctrl-single,pins = < - AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; dcan1_pins_default: dcan1_pins_default { pinctrl-single,pins = < - AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */ - AM33XX_IOPAD(0x96c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart0_rtsn.d_can1_rx */ + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart0_ctsn.d_can1_tx */ + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE2) /* uart0_rtsn.d_can1_rx */ >; }; }; -- cgit From 1f757e0616cf55afee24a75b055f0472405d79a8 Mon Sep 17 00:00:00 2001 From: Christina Quast Date: Tue, 9 Apr 2019 18:03:45 +0200 Subject: ARM: dts: am335x: evmsk: Replaced register offsets with defines The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-evmsk.dts | 292 ++++++++++++++++++------------------- 1 file changed, 146 insertions(+), 146 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index b128998097ce..b8e4b654557f 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -209,241 +209,241 @@ lcd_pins_default: lcd_pins_default { pinctrl-single,pins = < - AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */ - AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */ - AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */ - AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */ - AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */ - AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */ - AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */ - AM33XX_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */ - AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ - AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ - AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ - AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ - AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ - AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ - AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ - AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ - AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ - AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ - AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ - AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ - AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ - AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ - AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ - AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ - AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */ - AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */ - AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */ - AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad8.lcd_data23 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad9.lcd_data22 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad10.lcd_data21 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad11.lcd_data20 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad12.lcd_data19 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad13.lcd_data18 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad14.lcd_data17 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad15.lcd_data16 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) >; }; lcd_pins_sleep: lcd_pins_sleep { pinctrl-single,pins = < - AM33XX_IOPAD(0x820, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad8.lcd_data23 */ - AM33XX_IOPAD(0x824, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad9.lcd_data22 */ - AM33XX_IOPAD(0x828, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad10.lcd_data21 */ - AM33XX_IOPAD(0x82c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad11.lcd_data20 */ - AM33XX_IOPAD(0x830, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.lcd_data19 */ - AM33XX_IOPAD(0x834, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.lcd_data18 */ - AM33XX_IOPAD(0x838, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.lcd_data17 */ - AM33XX_IOPAD(0x83c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.lcd_data16 */ - AM33XX_IOPAD(0x8a0, PULL_DISABLE | MUX_MODE7) /* lcd_data0.lcd_data0 */ - AM33XX_IOPAD(0x8a4, PULL_DISABLE | MUX_MODE7) /* lcd_data1.lcd_data1 */ - AM33XX_IOPAD(0x8a8, PULL_DISABLE | MUX_MODE7) /* lcd_data2.lcd_data2 */ - AM33XX_IOPAD(0x8ac, PULL_DISABLE | MUX_MODE7) /* lcd_data3.lcd_data3 */ - AM33XX_IOPAD(0x8b0, PULL_DISABLE | MUX_MODE7) /* lcd_data4.lcd_data4 */ - AM33XX_IOPAD(0x8b4, PULL_DISABLE | MUX_MODE7) /* lcd_data5.lcd_data5 */ - AM33XX_IOPAD(0x8b8, PULL_DISABLE | MUX_MODE7) /* lcd_data6.lcd_data6 */ - AM33XX_IOPAD(0x8bc, PULL_DISABLE | MUX_MODE7) /* lcd_data7.lcd_data7 */ - AM33XX_IOPAD(0x8c0, PULL_DISABLE | MUX_MODE7) /* lcd_data8.lcd_data8 */ - AM33XX_IOPAD(0x8c4, PULL_DISABLE | MUX_MODE7) /* lcd_data9.lcd_data9 */ - AM33XX_IOPAD(0x8c8, PULL_DISABLE | MUX_MODE7) /* lcd_data10.lcd_data10 */ - AM33XX_IOPAD(0x8cc, PULL_DISABLE | MUX_MODE7) /* lcd_data11.lcd_data11 */ - AM33XX_IOPAD(0x8d0, PULL_DISABLE | MUX_MODE7) /* lcd_data12.lcd_data12 */ - AM33XX_IOPAD(0x8d4, PULL_DISABLE | MUX_MODE7) /* lcd_data13.lcd_data13 */ - AM33XX_IOPAD(0x8d8, PULL_DISABLE | MUX_MODE7) /* lcd_data14.lcd_data14 */ - AM33XX_IOPAD(0x8dc, PULL_DISABLE | MUX_MODE7) /* lcd_data15.lcd_data15 */ - AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.lcd_vsync */ - AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.lcd_hsync */ - AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.lcd_pclk */ - AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.lcd_ac_bias_en */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad8.lcd_data23 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad9.lcd_data22 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad10.lcd_data21 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad11.lcd_data20 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad12.lcd_data19 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad13.lcd_data18 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad14.lcd_data17 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad15.lcd_data16 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; user_leds_s0: user_leds_s0 { pinctrl-single,pins = < - AM33XX_IOPAD(0x810, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */ - AM33XX_IOPAD(0x814, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */ - AM33XX_IOPAD(0x818, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */ - AM33XX_IOPAD(0x81c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad4.gpio1_4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad5.gpio1_5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad6.gpio1_6 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad7.gpio1_7 */ >; }; gpio_keys_s0: gpio_keys_s0 { pinctrl-single,pins = < - AM33XX_IOPAD(0x894, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_oen_ren.gpio2_3 */ - AM33XX_IOPAD(0x890, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */ - AM33XX_IOPAD(0x870, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_wait0.gpio0_30 */ - AM33XX_IOPAD(0x89c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_oen_ren.gpio2_3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_wait0.gpio0_30 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */ >; }; i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; clkout2_pin: pinmux_clkout2_pin { pinctrl-single,pins = < - AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ >; }; ecap2_pins: backlight_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x99c, MUX_MODE4) /* mcasp0_ahclkr.ecap2_in_pwm2_out */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, 0x0, MUX_MODE4) /* mcasp0_ahclkr.ecap2_in_pwm2_out */ >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ - AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ - AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ - AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ - AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ - AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ - AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ - AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ - AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ - AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ - AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ /* Slave 2 */ - AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ - AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ - AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ - AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ - AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ - AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ - AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ - AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ - AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ - AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ - AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ - AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ - AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* Slave 2 reset value*/ - AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ - AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ - AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ - AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ - AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ - AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ - AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ - AM33XX_IOPAD(0x9a0, PIN_INPUT | MUX_MODE4) /* mcasp0_aclkr.mmc0_sdwp */ + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT, MUX_MODE4) /* mcasp0_aclkr.mmc0_sdwp */ >; }; mcasp1_pins: mcasp1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ - AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ - AM33XX_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* mii1_col.mcasp1_axr2 */ + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ >; }; mcasp1_pins_sleep: mcasp1_pins_sleep { pinctrl-single,pins = < - AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; mmc2_pins: pinmux_mmc2_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */ - AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ >; }; wl12xx_gpio: pinmux_wl12xx_gpio { pinctrl-single,pins = < - AM33XX_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_csn0.gpio1_29 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_csn0.gpio1_29 */ >; }; }; -- cgit From 33ef1394a97db67118f1e1c2edd3acb6f6782adb Mon Sep 17 00:00:00 2001 From: Christina Quast Date: Tue, 9 Apr 2019 18:03:46 +0200 Subject: ARM: dts: am335x: icev2: Replaced register offsets with defines The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-icev2.dts | 116 ++++++++++++++++++------------------- 1 file changed, 58 insertions(+), 58 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/am335x-icev2.dts index 9ac775c71072..4365684fa66f 100644 --- a/arch/arm/boot/dts/am335x-icev2.dts +++ b/arch/arm/boot/dts/am335x-icev2.dts @@ -157,111 +157,111 @@ &am33xx_pinmux { user_leds: user_leds { pinctrl-single,pins = < - AM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */ - AM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */ - AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */ - AM33XX_IOPAD(0x9b4, PIN_OUTPUT | MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */ - AM33XX_IOPAD(0x880, PIN_OUTPUT | MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */ - AM33XX_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT, MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT, MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT, MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT, MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT, MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */ >; }; mmc0_pins_default: mmc0_pins_default { pinctrl-single,pins = < - AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* (F17) mmc0_dat3.mmc0_dat3 */ - AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* (F18) mmc0_dat2.mmc0_dat2 */ - AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* (G15) mmc0_dat1.mmc0_dat1 */ - AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* (G16) mmc0_dat0.mmc0_dat0 */ - AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* (G17) mmc0_clk.mmc0_clk */ - AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* (G18) mmc0_cmd.mmc0_cmd */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) >; }; i2c0_pins_default: i2c0_pins_default { pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* (C17) I2C0_SDA.I2C0_SDA */ - AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* (C16) I2C0_SCL.I2C0_SCL */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0) >; }; spi0_pins_default: spi0_pins_default { pinctrl-single,pins = < - AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* (A17) spi0_sclk.spi0_sclk */ - AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */ - AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */ - AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */ - AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE0) /* (C15) spi0_cs1.spi0_cs1 */ - AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7) /* (B12) mcasp0_aclkr.gpio3[18] */ + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* (B12) mcasp0_aclkr.gpio3[18] */ >; }; uart3_pins_default: uart3_pins_default { pinctrl-single,pins = < - AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */ - AM33XX_IOPAD(0x938, PIN_OUTPUT_PULLUP | MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLUP, MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */ >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1, RMII mode */ - AM33XX_IOPAD(0x90c, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_crs.rmii1_crs_dv */ - AM33XX_IOPAD(0x944, (PIN_INPUT_PULLUP | MUX_MODE0)) /* rmii1_refclk.rmii1_refclk */ - AM33XX_IOPAD(0x940, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_rxd0.rmii1_rxd0 */ - AM33XX_IOPAD(0x93c, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_rxd1.rmii1_rxd1 */ - AM33XX_IOPAD(0x910, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_rxerr.rmii1_rxerr */ - AM33XX_IOPAD(0x928, (PIN_OUTPUT_PULLDOWN | MUX_MODE1)) /* mii1_txd0.rmii1_txd0 */ - AM33XX_IOPAD(0x924, (PIN_OUTPUT_PULLDOWN | MUX_MODE1)) /* mii1_txd1.rmii1_txd1 */ - AM33XX_IOPAD(0x914, (PIN_OUTPUT_PULLDOWN | MUX_MODE1)) /* mii1_txen.rmii1_txen */ + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txen.rmii1_txen */ /* Slave 2, RMII mode */ - AM33XX_IOPAD(0x870, (PIN_INPUT_PULLUP | MUX_MODE3)) /* gpmc_wait0.rmii2_crs_dv */ - AM33XX_IOPAD(0x908, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_col.rmii2_refclk */ - AM33XX_IOPAD(0x86c, (PIN_INPUT_PULLUP | MUX_MODE3)) /* gpmc_a11.rmii2_rxd0 */ - AM33XX_IOPAD(0x868, (PIN_INPUT_PULLUP | MUX_MODE3)) /* gpmc_a10.rmii2_rxd1 */ - AM33XX_IOPAD(0x874, (PIN_INPUT_PULLUP | MUX_MODE3)) /* gpmc_wpn.rmii2_rxerr */ - AM33XX_IOPAD(0x854, (PIN_OUTPUT_PULLDOWN | MUX_MODE3)) /* gpmc_a5.rmii2_txd0 */ - AM33XX_IOPAD(0x850, (PIN_OUTPUT_PULLDOWN | MUX_MODE3)) /* gpmc_a4.rmii2_txd1 */ - AM33XX_IOPAD(0x840, (PIN_OUTPUT_PULLDOWN | MUX_MODE3)) /* gpmc_a0.rmii2_txen */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_wait0.rmii2_crs_dv */ + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_col.rmii2_refclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a11.rmii2_rxd0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a10.rmii2_rxd1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_wpn.rmii2_rxerr */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* gpmc_a5.rmii2_txd0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* gpmc_a4.rmii2_txd1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* gpmc_a0.rmii2_txen */ >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ - AM33XX_IOPAD(0x90c, (PIN_INPUT_PULLDOWN | MUX_MODE7)) - AM33XX_IOPAD(0x944, (PIN_INPUT_PULLDOWN | MUX_MODE7)) - AM33XX_IOPAD(0x940, (PIN_INPUT_PULLDOWN | MUX_MODE7)) - AM33XX_IOPAD(0x93c, (PIN_INPUT_PULLDOWN | MUX_MODE7)) - AM33XX_IOPAD(0x910, (PIN_INPUT_PULLDOWN | MUX_MODE7)) - AM33XX_IOPAD(0x928, (PIN_INPUT_PULLDOWN | MUX_MODE7)) - AM33XX_IOPAD(0x924, (PIN_INPUT_PULLDOWN | MUX_MODE7)) - AM33XX_IOPAD(0x914, (PIN_INPUT_PULLDOWN | MUX_MODE7)) + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* Slave 2 reset value */ - AM33XX_IOPAD(0x870, (PIN_INPUT_PULLDOWN | MUX_MODE7)) - AM33XX_IOPAD(0x908, (PIN_INPUT_PULLDOWN | MUX_MODE7)) - AM33XX_IOPAD(0x86c, (PIN_INPUT_PULLDOWN | MUX_MODE7)) - AM33XX_IOPAD(0x868, (PIN_INPUT_PULLDOWN | MUX_MODE7)) - AM33XX_IOPAD(0x874, (PIN_INPUT_PULLDOWN | MUX_MODE7)) - AM33XX_IOPAD(0x854, (PIN_INPUT_PULLDOWN | MUX_MODE7)) - AM33XX_IOPAD(0x850, (PIN_INPUT_PULLDOWN | MUX_MODE7)) - AM33XX_IOPAD(0x840, (PIN_INPUT_PULLDOWN | MUX_MODE7)) + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ - AM33XX_IOPAD(0x948, (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)) /* mdio_data.mdio_data */ - AM33XX_IOPAD(0x94c, (PIN_OUTPUT_PULLUP | MUX_MODE0)) /* mdio_clk.mdio_clk */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ - AM33XX_IOPAD(0x948, (PIN_INPUT_PULLDOWN | MUX_MODE7)) - AM33XX_IOPAD(0x94c, (PIN_INPUT_PULLDOWN | MUX_MODE7)) + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; }; -- cgit From bcbb63b80284af0061ac44fe944d31a8482d2b8a Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Mon, 8 Apr 2019 12:42:49 +0300 Subject: ARM: dts: dra7: Separate AM57 dtsi files AM5 and DRA7 SoC families have different set of modules in them so the SoC sepecific dtsi files need to be separated. e.g. Some of the major differences between AM576 and DRA76 DRA76x AM576x USB3 x USB4 x ATL x VCP x MLB x ISS x PRU-ICSS1 x PRU-ICSS2 x This patch only deals with disabling USB3, USB4 and ATL for AM57 variants. Signed-off-by: Roger Quadros Reviewed-by: Lokesh Vutla Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am5718.dtsi | 32 ++++++++++++++++++++++++ arch/arm/boot/dts/am571x-idk.dts | 2 +- arch/arm/boot/dts/am5728.dtsi | 33 +++++++++++++++++++++++++ arch/arm/boot/dts/am572x-idk.dts | 5 ++-- arch/arm/boot/dts/am5748.dtsi | 33 +++++++++++++++++++++++++ arch/arm/boot/dts/am574x-idk.dts | 4 +-- arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi | 2 +- arch/arm/boot/dts/am57xx-cl-som-am57x.dts | 2 +- arch/arm/boot/dts/dra7-l4.dtsi | 6 ++--- 9 files changed, 108 insertions(+), 11 deletions(-) create mode 100644 arch/arm/boot/dts/am5718.dtsi create mode 100644 arch/arm/boot/dts/am5728.dtsi create mode 100644 arch/arm/boot/dts/am5748.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am5718.dtsi b/arch/arm/boot/dts/am5718.dtsi new file mode 100644 index 000000000000..d51007c3e8c4 --- /dev/null +++ b/arch/arm/boot/dts/am5718.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include "dra72x.dtsi" + +/ { + compatible = "ti,am5718", "ti,dra7"; +}; + +/* + * These modules are not present on AM5718 + * + * ATL + * VCP1, VCP2 + * MLB + * ISS + * USB3, USB4 + */ + +&usb3_tm { + status = "disabled"; +}; + +&usb4_tm { + status = "disabled"; +}; + +&atl_tm { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/am571x-idk.dts b/arch/arm/boot/dts/am571x-idk.dts index 6432309b39e3..66116ad3f9f4 100644 --- a/arch/arm/boot/dts/am571x-idk.dts +++ b/arch/arm/boot/dts/am571x-idk.dts @@ -7,7 +7,7 @@ */ /dts-v1/; -#include "dra72x.dtsi" +#include "am5718.dtsi" #include #include #include "dra7-mmc-iodelay.dtsi" diff --git a/arch/arm/boot/dts/am5728.dtsi b/arch/arm/boot/dts/am5728.dtsi new file mode 100644 index 000000000000..82e5427ef6a9 --- /dev/null +++ b/arch/arm/boot/dts/am5728.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include "dra74x.dtsi" + +/ { + compatible = "ti,am5728", "ti,dra7"; +}; + +/* + * These modules are not present on AM5728 + * + * EVE1, EVE2 + * ATL + * VCP1, VCP2 + * MLB + * ISS + * USB3, USB4 + */ + +&usb3_tm { + status = "disabled"; +}; + +&usb4_tm { + status = "disabled"; +}; + +&atl_tm { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/am572x-idk.dts b/arch/arm/boot/dts/am572x-idk.dts index b2fb6e097be7..4f835222c266 100644 --- a/arch/arm/boot/dts/am572x-idk.dts +++ b/arch/arm/boot/dts/am572x-idk.dts @@ -8,15 +8,14 @@ /dts-v1/; -#include "dra74x.dtsi" +#include "am5728.dtsi" #include "dra7-mmc-iodelay.dtsi" #include "dra74x-mmc-iodelay.dtsi" #include "am572x-idk-common.dtsi" / { model = "TI AM5728 IDK"; - compatible = "ti,am5728-idk", "ti,am5728", "ti,dra742", "ti,dra74", - "ti,dra7"; + compatible = "ti,am5728-idk", "ti,am5728", "ti,dra7"; }; &mmc1 { diff --git a/arch/arm/boot/dts/am5748.dtsi b/arch/arm/boot/dts/am5748.dtsi new file mode 100644 index 000000000000..5e129759d04a --- /dev/null +++ b/arch/arm/boot/dts/am5748.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include "dra76x.dtsi" + +/ { + compatible = "ti,am5748", "ti,dra762", "ti,dra7"; +}; + +/* + * These modules are not present on AM5748 + * + * EVE1, EVE2 + * ATL + * VCP1, VCP2 + * MLB + * ISS + * USB3, USB4 + */ + +&usb3_tm { + status = "disabled"; +}; + +&usb4_tm { + status = "disabled"; +}; + +&atl_tm { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/am574x-idk.dts b/arch/arm/boot/dts/am574x-idk.dts index 378dfa780ac1..dc5141c35610 100644 --- a/arch/arm/boot/dts/am574x-idk.dts +++ b/arch/arm/boot/dts/am574x-idk.dts @@ -6,14 +6,14 @@ /dts-v1/; -#include "dra76x.dtsi" +#include "am5748.dtsi" #include "dra7-mmc-iodelay.dtsi" #include "dra76x-mmc-iodelay.dtsi" #include "am572x-idk-common.dtsi" / { model = "TI AM5748 IDK"; - compatible = "ti,am5728-idk", "ti,dra762", "ti,dra7"; + compatible = "ti,am5748-idk", "ti,am5748", "ti,dra762", "ti,dra7"; }; &qspi { diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi index 1e6620f139dd..2341a56ebab9 100644 --- a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi +++ b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi @@ -7,7 +7,7 @@ */ /dts-v1/; -#include "dra74x.dtsi" +#include "am5728.dtsi" #include "am57xx-commercial-grade.dtsi" #include "dra74x-mmc-iodelay.dtsi" #include diff --git a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts index 4748ce8747ad..0460de0da2bf 100644 --- a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts +++ b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts @@ -13,7 +13,7 @@ #include #include -#include "dra74x.dtsi" +#include "am5728.dtsi" / { model = "CompuLab CL-SOM-AM57x"; diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi index 414f1cd68733..fe9f0bc29fec 100644 --- a/arch/arm/boot/dts/dra7-l4.dtsi +++ b/arch/arm/boot/dts/dra7-l4.dtsi @@ -2499,7 +2499,7 @@ ranges = <0x0 0x3a000 0x1000>; }; - target-module@3c000 { /* 0x4843c000, ap 23 08.0 */ + atl_tm: target-module@3c000 { /* 0x4843c000, ap 23 08.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x3c000 0x4>; reg-names = "rev"; @@ -4099,7 +4099,7 @@ }; }; - target-module@100000 { /* 0x48900000, ap 85 04.0 */ + usb3_tm: target-module@100000 { /* 0x48900000, ap 85 04.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; ti,hwmods = "usb_otg_ss3"; reg = <0x100000 0x4>, @@ -4148,7 +4148,7 @@ }; }; - target-module@140000 { /* 0x48940000, ap 75 3c.0 */ + usb4_tm: target-module@140000 { /* 0x48940000, ap 75 3c.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; ti,hwmods = "usb_otg_ss4"; reg = <0x140000 0x4>, -- cgit From ed27ae71bf610004d04cb956d0a7687342006a1f Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Thu, 11 Apr 2019 16:21:56 -0700 Subject: ARM: dts: rockchip: vcc33_ccd off in suspend for rk3288-veyron-chromebook As per my comments when the device tree for rk3288-veyron-chromebook first landed: > Technically I think vcc33_ccd can be off since we have > 'needs-reset-on-resume' down in the EHCI port (this regulator is for > the USB webcam that's connected to the EHCI port). > > ...but leaving it on for now seems fine until we get suspend/resume > more solid. It's probably about time to do it right. [1] https://lore.kernel.org/linux-arm-kernel/CAD=FV=U37Yx8Mqk75_x05zxonvdc3qRMhqp8TyTDPWGHqSuRqg@mail.gmail.com/ Signed-off-by: Douglas Anderson Reviewed-by: Elaine Zhang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi index b9cc90f0f25c..fbef34578100 100644 --- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi @@ -176,8 +176,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; + regulator-off-in-suspend; }; }; }; -- cgit From 356150e86d75653d1f679c6ef583144b26d0a686 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Thu, 11 Apr 2019 16:21:57 -0700 Subject: ARM: dts: rockchip: vdd_gpu off in suspend for rk3288-veyron At some point long long ago the downstream GPU driver would crash if we turned the GPU off during suspend. For some context you can see: https://chromium-review.googlesource.com/#/c/215780/5..6/arch/arm/boot/dts/rk3288-pinky-rev2.dts At some point in time not too long after that got fixed. It's unclear why the GPU is left enabled during suspend on the mainline kernel. Everything seems fine if I turn this off, so let's do it. Signed-off-by: Douglas Anderson Reviewed-by: Elaine Zhang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-veyron.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index 35755870bf66..758fe225c702 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -219,8 +219,7 @@ regulator-max-microvolt = <1250000>; regulator-ramp-delay = <6001>; regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; + regulator-off-in-suspend; }; }; -- cgit From 635e1e78a6857abc6b09c337fb962f86fbefd3a8 Mon Sep 17 00:00:00 2001 From: Pablo Greco Date: Fri, 12 Apr 2019 07:33:00 -0300 Subject: ARM: dts: sun8i: v40: bananapi-m2-berry: Sort device node dereferences. The device node dereferences are out of order, sort them. Signed-off-by: Pablo Greco Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 36 +++++++++++------------ 1 file changed, 18 insertions(+), 18 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts index bf97f6244c23..f05cabd34b8e 100644 --- a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts +++ b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts @@ -105,6 +105,24 @@ #include "axp22x.dtsi" +&mmc0 { + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 7 13 GPIO_ACTIVE_LOW>; /* PH13 */ + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pg_pins>; + vmmc-supply = <®_dldo2>; + vqmmc-supply = <®_dldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + ®_aldo3 { regulator-always-on; regulator-min-microvolt = <2700000>; @@ -152,24 +170,6 @@ regulator-name = "vcc-wifi"; }; -&mmc0 { - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 7 13 GPIO_ACTIVE_LOW>; /* PH13 */ - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pg_pins>; - vmmc-supply = <®_dldo2>; - vqmmc-supply = <®_dldo1>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; -- cgit From 8558c6e21ceb359b7293386fc497ed8d8bc85c13 Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Fri, 12 Apr 2019 06:58:32 +0200 Subject: ARM: dts: sun8i: h3: bluetooth for Banana Pi M2 Zero board The Banana Pi M2 Zero board has an AP6212 BT+Wifi combo chip with Broadcom internals attached to UART1 and some gpios. This addition is in line with similar boards. Signed-off-by: Andreas Kemnade Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts index 0e5f0eec3810..78a37a47185a 100644 --- a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts +++ b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts @@ -66,6 +66,8 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ + clocks = <&rtc 1>; + clock-names = "ext_clock"; }; }; @@ -119,7 +121,20 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts; status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rtc 1>; + clock-names = "lpo"; + vbat-supply = <®_vcc3v3>; + vddio-supply = <®_vcc3v3>; + device-wakeup-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ + host-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ + shutdown-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + }; + }; &usb_otg { -- cgit From 387fbf73ebe71d7c392e9c258a404c8f9fb3ec68 Mon Sep 17 00:00:00 2001 From: Christina Quast Date: Fri, 12 Apr 2019 18:26:11 +0200 Subject: ARM: dts: am335x: igep0033: Replaced register offsets with defines The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-igep0033.dtsi | 40 +++++++++++++++++----------------- 1 file changed, 20 insertions(+), 20 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi index cbd22f25de95..312deb6cf6a2 100644 --- a/arch/arm/boot/dts/am335x-igep0033.dtsi +++ b/arch/arm/boot/dts/am335x-igep0033.dtsi @@ -57,41 +57,41 @@ &am33xx_pinmux { i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; nandflash_pins: pinmux_nandflash_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ - AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ - AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ - AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ - AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ - AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ - AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ - AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ - AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ - AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */ - AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ - AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ - AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ - AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ - AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_30 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; leds_pins: pinmux_leds_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x85c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a7.gpio1_23 */ >; }; }; -- cgit From c422b10e88f00edd840aa830b395519d08fbbabd Mon Sep 17 00:00:00 2001 From: Christina Quast Date: Fri, 12 Apr 2019 18:26:12 +0200 Subject: ARM: dts: am335x: lxm: Replaced register offsets with defines The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-lxm.dts | 120 +++++++++++++++++++-------------------- 1 file changed, 60 insertions(+), 60 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-lxm.dts b/arch/arm/boot/dts/am335x-lxm.dts index d0e8e720a4d6..aa4cd2b8d4b6 100644 --- a/arch/arm/boot/dts/am335x-lxm.dts +++ b/arch/arm/boot/dts/am335x-lxm.dts @@ -46,109 +46,109 @@ &am33xx_pinmux { mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3 */ - AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2 */ - AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1 */ - AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0 */ - AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk */ - AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) >; }; i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0) >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ - AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_int */ - AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_crs_dv */ - AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_rxer */ - AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* rmii1_txen */ - AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* rmii1_td1 */ - AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* rmii1_td0 */ - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_rd1 */ - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_rd0 */ - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_int */ + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_crs_dv */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_rxer */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* rmii1_txen */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* rmii1_td1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* rmii1_td0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_rd1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_rd0 */ + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) /* Slave 2 */ - AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_txen */ - AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_td1 */ - AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_td0 */ - AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rd1 */ - AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rd0 */ - AM33XX_IOPAD(0x870, PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_crs_dv */ - AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rxer */ - AM33XX_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_int */ - AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii2_refclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_txen */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_crs_dv */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rxer */ + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_int */ + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii2_refclk */ >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ - AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_int */ - AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_crs_dv */ - AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_rxer */ - AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_txen */ - AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_td1 */ - AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_td0 */ - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_rd1 */ - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_rd0 */ - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_refclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_int */ + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_crs_dv */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_rxer */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_txen */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_td1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_td0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_rd1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_rd0 */ + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_refclk */ /* Slave 2 reset value*/ - AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_txen */ - AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_td1 */ - AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_td0 */ - AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_rd1 */ - AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_rd0 */ - AM33XX_IOPAD(0x870, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_crs_dv */ - AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_rxer */ - AM33XX_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_int */ - AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_refclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_txen */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_td1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_td0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_rd1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_rd0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_crs_dv */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_rxer */ + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_int */ + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_refclk */ >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; emmc_pins: pinmux_emmc_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ - AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ - AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ - AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; }; -- cgit From 876144dd533296b0c94b68a8d775d117f55ffefa Mon Sep 17 00:00:00 2001 From: Christina Quast Date: Fri, 12 Apr 2019 18:26:13 +0200 Subject: ARM: dts: am335x: moxa-uc-2100-common: Replaced register offsets with defines The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi | 42 +++++++++++------------ 1 file changed, 21 insertions(+), 21 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi index cb5913a69837..671d4a5da9c4 100644 --- a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi +++ b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi @@ -33,54 +33,54 @@ i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; push_button_pins: pinmux_push_button { pinctrl-single,pins = < - AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.gpio2_23 */ + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2_23 */ >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; mmc1_pins_default: pinmux_mmc1_pins { pinctrl-single,pins = < /* eMMC */ - AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad12.mmc1_dat0 */ - AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad13.mmc1_dat1 */ - AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad14.mmc1_dat2 */ - AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad15.mmc1_dat3 */ - AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad8.mmc1_dat4 */ - AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad9.mmc1_dat5 */ - AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad10.mmc1_dat6 */ - AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad11.mmc1_dat7 */ - AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad12.mmc1_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad13.mmc1_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad14.mmc1_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad15.mmc1_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad8.mmc1_dat4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad9.mmc1_dat5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad10.mmc1_dat6 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad11.mmc1_dat7 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ >; }; spi0_pins: pinmux_spi0 { pinctrl-single,pins = < - AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_sclk.spi0_sclk */ - AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ - AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0.spi0_d0 */ - AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */ + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) >; }; }; -- cgit From 4a424b0b168ed8ecb301ac6f9b86f1240149afe3 Mon Sep 17 00:00:00 2001 From: Christina Quast Date: Fri, 12 Apr 2019 18:26:14 +0200 Subject: ARM: dts: am335x: moxa-uc-2101: Replaced register offsets with defines The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-moxa-uc-2101.dts | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-moxa-uc-2101.dts b/arch/arm/boot/dts/am335x-moxa-uc-2101.dts index 48aee6de4cdb..5923b6e7e1cb 100644 --- a/arch/arm/boot/dts/am335x-moxa-uc-2101.dts +++ b/arch/arm/boot/dts/am335x-moxa-uc-2101.dts @@ -31,23 +31,23 @@ cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ - AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ - AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ - AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ - AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ - AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ - AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mii1_refclk.rmii1_refclk */ + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txen.rmii1_txen */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) >; }; spi1_pins: pinmux_spi1 { pinctrl-single,pins = < - AM33XX_IOPAD(0x964, PIN_INPUT_PULLUP | MUX_MODE4) /* ecap0_in_pwm0_out.spi1_sclk */ - AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE4) /* uart1_ctsn.spi1_cs0 */ - AM33XX_IOPAD(0x968, PIN_INPUT_PULLUP | MUX_MODE4) /* uart0_ctsn.spi1_d0 */ - AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE4) /* uart0_rtsn.spi1_d1 */ + AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_INPUT_PULLUP, MUX_MODE4) /* ecap0_in_pwm0_out.spi1_sclk */ + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* uart1_ctsn.spi1_cs0 */ + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* uart0_ctsn.spi1_d0 */ + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* uart0_rtsn.spi1_d1 */ >; }; }; -- cgit From c68a4ffd3d75d5e54e8b355218d622d0f4d70f9d Mon Sep 17 00:00:00 2001 From: Christina Quast Date: Fri, 12 Apr 2019 18:26:15 +0200 Subject: ARM: dts: am335x: moxa-uc-8100-me-t: Replaced register offsets with defines The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts | 116 ++++++++++++------------- 1 file changed, 58 insertions(+), 58 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts b/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts index e562ce40f290..5a2fb4bd4e02 100644 --- a/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts +++ b/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts @@ -104,79 +104,79 @@ minipcie_pins: pinmux_minipcie { pinctrl-single,pins = < - AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.gpio2_24 */ - AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.gpio2_25 */ - AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.gpio2_22 Power off PIN*/ + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_pclk.gpio2_24 */ + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_ac_bias_en.gpio2_25 */ + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_vsync.gpio2_22 Power off PIN*/ >; }; push_button_pins: pinmux_push_button { pinctrl-single,pins = < - AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahcklx.gpio3_21 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mcasp0_ahcklx.gpio3_21 */ >; }; i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; i2c1_pins: pinmux_i2c1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x968, PIN_INPUT_PULLUP | MUX_MODE3) /* uart0_ctsn.i2c1_sda */ - AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE3) /* uart0_rtsn.i2c1_scl */ + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart0_ctsn.i2c1_sda */ + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart0_rtsn.i2c1_scl */ >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; uart1_pins: pinmux_uart1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */ - AM33XX_IOPAD(0x97C, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */ - AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ - AM33XX_IOPAD(0x984, PIN_OUTPUT | MUX_MODE0) /* uart1_txd.uart1_txd */ + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0) >; }; uart2_pins: pinmux_uart2_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x8d8, PIN_INPUT | MUX_MODE6) /* lcd_data14.uart5_ctsn */ - AM33XX_IOPAD(0x8dc, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* lcd_data15.uart5_rtsn */ - AM33XX_IOPAD(0x8c4, PIN_INPUT_PULLUP | MUX_MODE4) /* lcd_data9.uart5_rxd */ - AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE4) /* lcd_data8.uart5_txd */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_INPUT, MUX_MODE6) /* lcd_data14.uart5_ctsn */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* lcd_data15.uart5_rtsn */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_INPUT_PULLUP, MUX_MODE4) /* lcd_data9.uart5_rxd */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE4) /* lcd_data8.uart5_txd */ >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ - AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ - AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ - AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ - AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ - AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ - AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mii1_refclk.rmii1_refclk */ + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) /* Slave 2 */ - AM33XX_IOPAD(0x870, PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_crs_dv */ - AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rxer */ - AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_txen */ - AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_td1 */ - AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_td0 */ - AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rd1 */ - AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rd0 */ - AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii2_refclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_crs_dv */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rxer */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_txen */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii2_refclk */ >; }; @@ -184,46 +184,46 @@ davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; mmc0_pins_default: pinmux_mmc0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3 */ - AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2 */ - AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1 */ - AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0 */ - AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk */ - AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd */ - AM33XX_IOPAD(0x990, PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkx.gpio3_14 */ - AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkx.gpio3_18 */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkx.gpio3_14 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkx.gpio3_18 */ >; }; mmc2_pins_default: pinmux_mmc2_pins { pinctrl-single,pins = < /* eMMC */ - AM33XX_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad12.mmc2_dat0 */ - AM33XX_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad13.mmc2_dat1 */ - AM33XX_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad14.mmc2_dat2 */ - AM33XX_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad15.mmc2_dat3 */ - AM33XX_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad8.mmc2_dat4 */ - AM33XX_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad9.mmc2_dat5 */ - AM33XX_IOPAD(0x828, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad10.mmc2_dat6 */ - AM33XX_IOPAD(0x82c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad11.mmc2_dat7 */ - AM33XX_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ - AM33XX_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad12.mmc2_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad13.mmc2_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad14.mmc2_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad15.mmc2_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad8.mmc2_dat4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad9.mmc2_dat5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad10.mmc2_dat6 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad11.mmc2_dat7 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc2_clk */ >; }; spi0_pins: pinmux_spi0 { pinctrl-single,pins = < - AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_sclk.spi0_sclk */ - AM33XX_IOPAD(0x95C, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ - AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0.spi0_d0 */ - AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */ + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) >; }; -- cgit From affcce6f7c5c608baf89403443eaa27919aea28b Mon Sep 17 00:00:00 2001 From: Christina Quast Date: Fri, 12 Apr 2019 18:26:16 +0200 Subject: ARM: dts: am335x: nano: Replaced register offsets with defines The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-nano.dts | 140 +++++++++++++++++++------------------- 1 file changed, 70 insertions(+), 70 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-nano.dts b/arch/arm/boot/dts/am335x-nano.dts index 9c9143ed4003..0052657331ee 100644 --- a/arch/arm/boot/dts/am335x-nano.dts +++ b/arch/arm/boot/dts/am335x-nano.dts @@ -41,121 +41,121 @@ misc_pins: misc_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE7) /* spi0_cs0.gpio0_5 */ + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE7) /* spi0_cs0.gpio0_5 */ >; }; gpmc_pins: gpmc_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ - AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ - AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ - AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ - AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ - AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ - AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ - AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ - AM33XX_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad8.gpmc_ad8 */ - AM33XX_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad9.gpmc_ad9 */ - AM33XX_IOPAD(0x828, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad10.gpmc_ad10 */ - AM33XX_IOPAD(0x82c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad11.gpmc_ad11 */ - AM33XX_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad12.gpmc_ad12 */ - AM33XX_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad13.gpmc_ad13 */ - AM33XX_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad14.gpmc_ad14 */ - AM33XX_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad15.gpmc_ad15 */ - - AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ - AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ - AM33XX_IOPAD(0x880, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn1.gpmc_csn1 */ - AM33XX_IOPAD(0x884, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn2.gpmc_csn2 */ - AM33XX_IOPAD(0x888, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn3.gpmc_csn3 */ - - AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ - AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ - AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ - AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0_cle.gpmc_ben0_cle */ - - AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE1) /* lcd_data1.gpmc_a1 */ - AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE1) /* lcd_data2.gpmc_a2 */ - AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE1) /* lcd_data3.gpmc_a3 */ - AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE1) /* lcd_data4.gpmc_a4 */ - AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE1) /* lcd_data5.gpmc_a5 */ - AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE1) /* lcd_data6.gpmc_a6 */ - AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE1) /* lcd_data7.gpmc_a7 */ - - AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE1) /* lcd_vsync.gpmc_a8 */ - AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE1) /* lcd_hsync.gpmc_a9 */ - AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE1) /* lcd_pclk.gpmc_a10 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE0) + + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_OUTPUT, MUX_MODE0) + + AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) + + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE1) /* lcd_data1.gpmc_a1 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE1) /* lcd_data2.gpmc_a2 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE1) /* lcd_data3.gpmc_a3 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE1) /* lcd_data4.gpmc_a4 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE1) /* lcd_data5.gpmc_a5 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE1) /* lcd_data6.gpmc_a6 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE1) /* lcd_data7.gpmc_a7 */ + + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE1) /* lcd_vsync.gpmc_a8 */ + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE1) /* lcd_hsync.gpmc_a9 */ + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE1) /* lcd_pclk.gpmc_a10 */ >; }; i2c0_pins: i2c0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM33XX_IOPAD(0x98c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLDOWN, MUX_MODE0) >; }; uart0_pins: uart0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT | MUX_MODE0) /* uart0_txd.uart0_txd */ + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT, MUX_MODE0) >; }; uart1_pins: uart1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x978, PIN_OUTPUT | MUX_MODE7) /* uart1_ctsn.uart1_ctsn */ - AM33XX_IOPAD(0x97c, PIN_OUTPUT | MUX_MODE7) /* uart1_rtsn.uart1_rtsn */ - AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ - AM33XX_IOPAD(0x984, PIN_OUTPUT | MUX_MODE0) /* uart1_txd.uart1_txd */ + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0) >; }; uart2_pins: uart2_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x8c0, PIN_INPUT_PULLUP | MUX_MODE7) /* lcd_data8.gpio2[14] */ - AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE7) /* lcd_data9.gpio2[15] */ - AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1) /* spi0_sclk.uart2_rxd */ - AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1) /* spi0_d0.uart2_txd */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_INPUT_PULLUP, MUX_MODE7) /* lcd_data8.gpio2[14] */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE7) /* lcd_data9.gpio2[15] */ + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* spi0_sclk.uart2_rxd */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* spi0_d0.uart2_txd */ >; }; uart3_pins: uart3_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x8c8, PIN_INPUT_PULLUP | MUX_MODE6) /* lcd_data10.uart3_ctsn */ - AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE6) /* lcd_data11.uart3_rtsn */ - AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE1) /* spi0_cs1.uart3_rxd */ - AM33XX_IOPAD(0x964, PIN_OUTPUT | MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_INPUT_PULLUP, MUX_MODE6) /* lcd_data10.uart3_ctsn */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE6) /* lcd_data11.uart3_rtsn */ + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE1) /* spi0_cs1.uart3_rxd */ + AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT, MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */ >; }; uart4_pins: uart4_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x8d0, PIN_INPUT_PULLUP | MUX_MODE6) /* lcd_data12.uart4_ctsn */ - AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE6) /* lcd_data13.uart4_rtsn */ - AM33XX_IOPAD(0x968, PIN_INPUT | MUX_MODE1) /* uart0_ctsn.uart4_rxd */ - AM33XX_IOPAD(0x96c, PIN_OUTPUT | MUX_MODE1) /* uart0_rtsn.uart4_txd */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_INPUT_PULLUP, MUX_MODE6) /* lcd_data12.uart4_ctsn */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE6) /* lcd_data13.uart4_rtsn */ + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT, MUX_MODE1) /* uart0_ctsn.uart4_rxd */ + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE1) /* uart0_rtsn.uart4_txd */ >; }; uart5_pins: uart5_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x8d8, PIN_INPUT | MUX_MODE4) /* lcd_data14.uart5_rxd */ - AM33XX_IOPAD(0x944, PIN_OUTPUT | MUX_MODE3) /* rmiii1_refclk.uart5_txd */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_INPUT, MUX_MODE4) /* lcd_data14.uart5_rxd */ + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT, MUX_MODE3) /* rmiii1_refclk.uart5_txd */ >; }; mmc1_pins: mmc1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ - AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ - AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ - AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ - AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ - AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ - AM33XX_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE7) /* emu1.gpio3[8] */ - AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3[18] */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_clk.mmc0_clk */ + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ + AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_INPUT_PULLUP, MUX_MODE7) /* emu1.gpio3[8] */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkr.gpio3[18] */ >; }; }; -- cgit From 443fca762bc33986262bfc7cee5800053f05606b Mon Sep 17 00:00:00 2001 From: Christina Quast Date: Fri, 12 Apr 2019 18:26:17 +0200 Subject: ARM: dts: am335x: osd3358-sm-red: Replaced register offsets with defines The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-osd3358-sm-red.dts | 168 ++++++++++++++-------------- 1 file changed, 84 insertions(+), 84 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-osd3358-sm-red.dts b/arch/arm/boot/dts/am335x-osd3358-sm-red.dts index 95d54cf3849e..f47cc9fea253 100644 --- a/arch/arm/boot/dts/am335x-osd3358-sm-red.dts +++ b/arch/arm/boot/dts/am335x-osd3358-sm-red.dts @@ -40,61 +40,61 @@ &am33xx_pinmux { nxp_hdmi_bonelt_pins: nxp-hdmi-bonelt-pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x9b0, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr0 */ - AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ - AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ - AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ - AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ - AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ - AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ - AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ - AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ - AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ - AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ - AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ - AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ - AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ - AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ - AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ - AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ - AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_vsync.lcd_vsync */ - AM33XX_IOPAD(0x8e4, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_hsync.lcd_hsync */ - AM33XX_IOPAD(0x8e8, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_pclk.lcd_pclk */ - AM33XX_IOPAD(0x8ec, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; nxp_hdmi_bonelt_off_pins: nxp-hdmi-bonelt-off-pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x9b0, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr0 */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) >; }; mcasp0_pins: mcasp0-pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLUP | MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */ - AM33XX_IOPAD(0x99c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ - AM33XX_IOPAD(0x994, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */ - AM33XX_IOPAD(0x990, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */ - AM33XX_IOPAD(0x86c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.GPIO1_27 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */ >; }; flash_enable: flash-enable { pinctrl-single,pins = < - AM33XX_IOPAD(0x944, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* rmii1_ref_clk.gpio0_29 */ + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* rmii1_ref_clk.gpio0_29 */ >; }; imu_interrupt: imu-interrupt { pinctrl-single,pins = < - AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) /* mii1_rx_er.gpio3_2 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_rx_er.gpio3_2 */ >; }; ethernet_interrupt: ethernet-interrupt{ pinctrl-single,pins = < - AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) /* mii1_col.gpio3_0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_col.gpio3_0 */ >; }; }; @@ -269,109 +269,109 @@ user_leds_s0: user-leds-s0 { pinctrl-single,pins = < - AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ - AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */ - AM33XX_IOPAD(0x85c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */ - AM33XX_IOPAD(0x860, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a6.gpio1_22 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a7.gpio1_23 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a8.gpio1_24 */ >; }; i2c2_pins: pinmux-i2c2-pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.i2c2_sda */ - AM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.i2c2_scl */ + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_ctsn.i2c2_sda */ + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_rtsn.i2c2_scl */ >; }; uart0_pins: pinmux-uart0-pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; clkout2_pin: pinmux-clkout2-pin { pinctrl-single,pins = < - AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ >; }; cpsw_default: cpsw-default { pinctrl-single,pins = < /* Slave 1 */ - AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ - AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ - AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_txd3 */ - AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_txd2 */ - AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */ - AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */ - AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_txclk */ - AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rxclk */ - AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rxd3 */ - AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rxd2 */ - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */ - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) >; }; cpsw_sleep: cpsw-sleep { pinctrl-single,pins = < /* Slave 1 reset value */ - AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; davinci_mdio_default: davinci-mdio-default { pinctrl-single,pins = < /* MDIO */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; davinci_mdio_sleep: davinci-mdio-sleep { pinctrl-single,pins = < /* MDIO reset value */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; mmc1_pins: pinmux-mmc1-pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */ - AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* (G16) mmc0_dat0.mmc0_dat0 */ - AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* (G15) mmc0_dat1.mmc0_dat1 */ - AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* (F18) mmc0_dat2.mmc0_dat2 */ - AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* (F17) mmc0_dat3.mmc0_dat3 */ - AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* (G18) mmc0_cmd.mmc0_cmd */ - AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* (G17) mmc0_clk.mmc0_clk */ + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) >; }; emmc_pins: pinmux-emmc-pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ - AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ - AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ - AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ >; }; }; -- cgit From 558fee9ab5042e46f952f7b2db4f65bb5a7a8d1e Mon Sep 17 00:00:00 2001 From: Christina Quast Date: Fri, 12 Apr 2019 18:26:18 +0200 Subject: ARM: dts: am335x: osd335x-common: Replaced register offsets with defines The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-osd335x-common.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-osd335x-common.dtsi b/arch/arm/boot/dts/am335x-osd335x-common.dtsi index f8ff473f94f0..a8b6842489f7 100644 --- a/arch/arm/boot/dts/am335x-osd335x-common.dtsi +++ b/arch/arm/boot/dts/am335x-osd335x-common.dtsi @@ -36,8 +36,8 @@ &am33xx_pinmux { i2c0_pins: pinmux-i2c0-pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* (C17) I2C0_SDA.I2C0_SDA */ - AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* (C16) I2C0_SCL.I2C0_SCL */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; }; -- cgit From 781288d2bdeff0bd79d129d2bd442e1b20f5080e Mon Sep 17 00:00:00 2001 From: Christina Quast Date: Fri, 12 Apr 2019 18:26:19 +0200 Subject: ARM: dts: am335x: pcm-953: Replaced register offsets with defines The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-pcm-953.dtsi | 74 +++++++++++++++++------------------ 1 file changed, 37 insertions(+), 37 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-pcm-953.dtsi b/arch/arm/boot/dts/am335x-pcm-953.dtsi index 1ec8e0d80191..baceaa7bb33b 100644 --- a/arch/arm/boot/dts/am335x-pcm-953.dtsi +++ b/arch/arm/boot/dts/am335x-pcm-953.dtsi @@ -79,15 +79,15 @@ &am33xx_pinmux { user_buttons_pins: pinmux_user_buttons { pinctrl-single,pins = < - AM33XX_IOPAD(0x9e4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* emu0.gpio3_7 */ - AM33XX_IOPAD(0x9e8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* emu1.gpio3_8 */ + AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* emu0.gpio3_7 */ + AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* emu1.gpio3_8 */ >; }; user_leds_pins: pinmux_user_leds { pinctrl-single,pins = < - AM33XX_IOPAD(0x880, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn1.gpio1_30 */ - AM33XX_IOPAD(0x884, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn2.gpio1_31 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_csn1.gpio1_30 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_csn2.gpio1_31 */ >; }; }; @@ -96,8 +96,8 @@ &am33xx_pinmux { dcan1_pins: pinmux_dcan1 { pinctrl-single,pins = < - AM33XX_IOPAD(0x980, PIN_OUTPUT_PULLUP | MUX_MODE2) /* uart1_rxd.dcan1_tx_mux2 */ - AM33XX_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.dcan1_rx_mux2 */ + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart1_rxd.dcan1_tx_mux2 */ + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT_PULLUP, MUX_MODE2) /* uart1_txd.dcan1_rx_mux2 */ >; }; }; @@ -112,18 +112,18 @@ &am33xx_pinmux { ethernet1_pins: pinmux_ethernet1 { pinctrl-single,pins = < - AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ - AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ - AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ - AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ - AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ - AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ - AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ - AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ - AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ - AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ - AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ - AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ >; }; }; @@ -171,8 +171,8 @@ cb_gpio_pins: pinmux_cb_gpio { pinctrl-single,pins = < - AM33XX_IOPAD(0x968, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart0_ctsn.gpio1_8 */ - AM33XX_IOPAD(0x96c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart0_rtsn.gpio1_9 */ + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* uart0_ctsn.gpio1_8 */ + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* uart0_rtsn.gpio1_9 */ >; }; }; @@ -181,13 +181,13 @@ &am33xx_pinmux { mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ - AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ - AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ - AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ - AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ - AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ - AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE7) /* spi0_cs1.mmc0_sdcd */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7) /* spi0_cs1.mmc0_sdcd */ >; }; }; @@ -205,31 +205,31 @@ &am33xx_pinmux { uart0_pins: pinmux_uart0 { pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; uart1_pins: pinmux_uart1 { pinctrl-single,pins = < - AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ - AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ - AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */ - AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */ + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; uart2_pins: pinmux_uart2 { pinctrl-single,pins = < - AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_tx_clk.uart2_rxd */ - AM33XX_IOPAD(0x930, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_rx_clk.uart2_txd */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_tx_clk.uart2_rxd */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_rx_clk.uart2_txd */ >; }; uart3_pins: pinmux_uart3 { pinctrl-single,pins = < - AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd3.uart3_rxd */ - AM33XX_IOPAD(0x938, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd2.uart3_txd */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxd3.uart3_rxd */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_rxd2.uart3_txd */ >; }; }; -- cgit From 898c4a59bc62ab6a1beee8ae0d606b8ec5f65e30 Mon Sep 17 00:00:00 2001 From: Christina Quast Date: Fri, 12 Apr 2019 18:26:20 +0200 Subject: ARM: dts: am335x: pdu001: Replaced register offsets with defines The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-pdu001.dts | 170 ++++++++++++++++++------------------ 1 file changed, 85 insertions(+), 85 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-pdu001.dts b/arch/arm/boot/dts/am335x-pdu001.dts index ae43d61f4e8b..3141255f72c2 100644 --- a/arch/arm/boot/dts/am335x-pdu001.dts +++ b/arch/arm/boot/dts/am335x-pdu001.dts @@ -92,162 +92,162 @@ i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; i2c1_pins: pinmux_i2c1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */ - AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d1.i2c1_sda */ + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_cs0.i2c1_scl */ >; }; i2c2_pins: pinmux_i2c2_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_clk.i2c2_sda */ - AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d0.i2c2_scl */ + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_clk.i2c2_sda */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d0.i2c2_scl */ >; }; spi1_pins: pinmux_spi1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_sclk */ - AM33XX_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ - AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */ - AM33XX_IOPAD(0x99C, PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT, MUX_MODE3) /* mcasp0_aclkx.spi1_sclk */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT, MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE3) /* mcasp0_axr0.spi1_d1 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT, MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */ >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x96C, PIN_OUTPUT | MUX_MODE7) /* uart0_rtsn.gpio1_9 */ - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; uart1_pins: pinmux_uart1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ - AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; uart3_pins: pinmux_uart3_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE1) /* spi0_cs1.uart3_rxd */ - AM33XX_IOPAD(0x964, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */ + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE1) /* spi0_cs1.uart3_rxd */ + AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */ >; }; clkout2_pin: pinmux_clkout2_pin { pinctrl-single,pins = < - AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Port 1 (emac0) */ - AM33XX_IOPAD(0x908, PIN_INPUT | MUX_MODE0) /* mii1_col.mii1_col */ - AM33XX_IOPAD(0x90C, PIN_INPUT | MUX_MODE0) /* mii1_crs.mii1_crs */ - AM33XX_IOPAD(0x910, PIN_INPUT | MUX_MODE0) /* mii1_rxer.mii1_rxer */ - AM33XX_IOPAD(0x914, PIN_OUTPUT | MUX_MODE0) /* mii1_txen.mii1_txen */ - AM33XX_IOPAD(0x918, PIN_INPUT | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */ - AM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE0) /* mii1_txd3.mii1_txd3 */ - AM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE0) /* mii1_txd2.mii1_txd2 */ - AM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE0) /* mii1_txd1.mii1_txd1 */ - AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE0) /* mii1_txd0.mii1_txd0 */ - AM33XX_IOPAD(0x92c, PIN_INPUT | MUX_MODE0) /* mii1_txclk.mii1_txclk */ - AM33XX_IOPAD(0x930, PIN_INPUT | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */ - AM33XX_IOPAD(0x934, PIN_INPUT | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */ - AM33XX_IOPAD(0x938, PIN_INPUT | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */ - AM33XX_IOPAD(0x93c, PIN_INPUT | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */ - AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT, MUX_MODE0) /* Port 2 (emac1) */ - AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE1) /* mii2_txen.gpmc_a0 */ - AM33XX_IOPAD(0x844, PIN_INPUT | MUX_MODE1) /* mii2_rxdv.gpmc_a1 */ - AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE1) /* mii2_txd3.gpmc_a2 */ - AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE1) /* mii2_txd2.gpmc_a3 */ - AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE1) /* mii2_txd1.gpmc_a4 */ - AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE1) /* mii2_txd0.gpmc_a5 */ - AM33XX_IOPAD(0x858, PIN_INPUT | MUX_MODE1) /* mii2_txclk.gpmc_a6 */ - AM33XX_IOPAD(0x85c, PIN_INPUT | MUX_MODE1) /* mii2_rxclk.gpmc_a7 */ - AM33XX_IOPAD(0x860, PIN_INPUT | MUX_MODE1) /* mii2_rxd3.gpmc_a8 */ - AM33XX_IOPAD(0x864, PIN_INPUT | MUX_MODE1) /* mii2_rxd2.gpmc_a9 */ - AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE1) /* mii2_rxd1.gpmc_a10 */ - AM33XX_IOPAD(0x86C, PIN_INPUT | MUX_MODE1) /* mii2_rxd0.gpmc_a11 */ - AM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE1) /* mii2_crs.gpmc_wait0 */ - AM33XX_IOPAD(0x874, PIN_INPUT | MUX_MODE1) /* mii2_rxer.gpmc_wpn */ - AM33XX_IOPAD(0x878, PIN_INPUT | MUX_MODE1) /* mii2_col.gpmc_ben1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* mii2_txen.gpmc_a0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT, MUX_MODE1) /* mii2_rxdv.gpmc_a1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1) /* mii2_txd3.gpmc_a2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1) /* mii2_txd2.gpmc_a3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1) /* mii2_txd1.gpmc_a4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1) /* mii2_txd0.gpmc_a5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT, MUX_MODE1) /* mii2_txclk.gpmc_a6 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT, MUX_MODE1) /* mii2_rxclk.gpmc_a7 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT, MUX_MODE1) /* mii2_rxd3.gpmc_a8 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE1) /* mii2_rxd2.gpmc_a9 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE1) /* mii2_rxd1.gpmc_a10 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT, MUX_MODE1) /* mii2_rxd0.gpmc_a11 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT, MUX_MODE1) /* mii2_crs.gpmc_wait0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT, MUX_MODE1) /* mii2_rxer.gpmc_wpn */ + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT, MUX_MODE1) /* mii2_col.gpmc_ben1 */ >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < - AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; mmc1_pins: pinmux_mmc1_pins { /* eMMC */ pinctrl-single,pins = < - AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3 */ - AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2 */ - AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1 */ - AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0 */ - AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk */ - AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) >; }; mmc2_pins: pinmux_mmc2_pins { /* SD cardcage */ pinctrl-single,pins = < - AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ /* card change signal for frontpanel SD cardcage */ - AM33XX_IOPAD(0x890, PIN_INPUT | MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT, MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */ >; }; lcd_pins_s0: lcd_pins_s0 { pinctrl-single,pins = < - AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ - AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ - AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ - AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ - AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ - AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ - AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ - AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ - AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ - AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ - AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ - AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ - AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ - AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ - AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ - AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ - AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */ - AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */ - AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */ - AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) >; }; dcan0_pins: pinmux_dcan0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */ - AM33XX_IOPAD(0x97c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart1_rtsn.d_can0_rx */ + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart1_ctsn.d_can0_tx */ + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE2) /* uart1_rtsn.d_can0_rx */ >; }; }; -- cgit From 891ffb8fcd464bd88d385fe7dfbf66f65bc26253 Mon Sep 17 00:00:00 2001 From: Christina Quast Date: Fri, 12 Apr 2019 18:26:21 +0200 Subject: ARM: dts: am335x: pepper: Replaced register offsets with defines The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-pepper.dts | 200 ++++++++++++++++++------------------ 1 file changed, 100 insertions(+), 100 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-pepper.dts b/arch/arm/boot/dts/am335x-pepper.dts index 6be79b8349ac..5c3e49f93ac4 100644 --- a/arch/arm/boot/dts/am335x-pepper.dts +++ b/arch/arm/boot/dts/am335x-pepper.dts @@ -93,14 +93,14 @@ &am33xx_pinmux { i2c0_pins: pinmux_i2c0 { pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; i2c1_pins: pinmux_i2c1 { pinctrl-single,pins = < - AM33XX_IOPAD(0x90C, PIN_INPUT_PULLUP | MUX_MODE3) /* mii1_crs,i2c1_sda */ - AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE3) /* mii1_rxerr,i2c1_scl */ + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLUP, MUX_MODE3) /* mii1_crs,i2c1_sda */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE3) /* mii1_rxerr,i2c1_scl */ >; }; }; @@ -130,7 +130,7 @@ &am33xx_pinmux { accel_pins: pinmux_accel { pinctrl-single,pins = < - AM33XX_IOPAD(0x898, PIN_INPUT | MUX_MODE7) /* gpmc_wen.gpio2_4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_INPUT, MUX_MODE7) /* gpmc_wen.gpio2_4 */ >; }; }; @@ -177,12 +177,12 @@ &am33xx_pinmux { audio_pins: pinmux_audio { pinctrl-single,pins = < - AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */ - AM33XX_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */ - AM33XX_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */ - AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0.mcasp0_axr0 */ - AM33XX_IOPAD(0x9a8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr1.mcasp0_axr1 */ - AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE7) /* gpmc_a0.gpio1_16 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE7) /* gpmc_a0.gpio1_16 */ >; }; }; @@ -228,36 +228,36 @@ &am33xx_pinmux { lcd_pins: pinmux_lcd { pinctrl-single,pins = < - AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ - AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ - AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ - AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ - AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ - AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ - AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ - AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ - AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ - AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ - AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ - AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ - AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ - AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ - AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ - AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ - AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data16 */ - AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data17 */ - AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data18 */ - AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data19 */ - AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data20 */ - AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data21 */ - AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data22 */ - AM33XX_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data23 */ - AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */ - AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */ - AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */ - AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad8.lcd_data16 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad9.lcd_data17 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad10.lcd_data18 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad11.lcd_data19 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad12.lcd_data20 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad13.lcd_data21 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad14.lcd_data22 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad15.lcd_data23 */ + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) /* Display Enable */ - AM33XX_IOPAD(0x86c, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a11.gpio1_27 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a11.gpio1_27 */ >; }; }; @@ -299,29 +299,29 @@ &am33xx_pinmux { ethernet_pins: pinmux_ethernet { pinctrl-single,pins = < - AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ - AM33XX_IOPAD(0x918, PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ - AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ - AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ - AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ - AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ - AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ - AM33XX_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ - AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd3.rgmii1_rxd3 */ - AM33XX_IOPAD(0x938, PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd2.rgmii1_rxd2 */ - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */ - AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE2) /* ethernet interrupt */ - AM33XX_IOPAD(0x944, PIN_INPUT_PULLUP | MUX_MODE7) /* rmii2_refclk.gpio0_29 */ + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLUP, MUX_MODE7) /* rmii2_refclk.gpio0_29 */ /* ethernet PHY nReset */ - AM33XX_IOPAD(0x908, PIN_OUTPUT_PULLUP | MUX_MODE7) /* mii1_col.gpio3_0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLUP, MUX_MODE7) /* mii1_col.gpio3_0 */ >; }; mdio_pins: pinmux_mdio { pinctrl-single,pins = < - AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; }; @@ -364,45 +364,45 @@ &am33xx_pinmux { sd_pins: pinmux_sd_card { pinctrl-single,pins = < - AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ - AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ - AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ - AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ - AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ - AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ - AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */ >; }; emmc_pins: pinmux_emmc { pinctrl-single,pins = < - AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ - AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ - AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ - AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ /* EMMC nReset */ - AM33XX_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */ >; }; wireless_pins: pinmux_wireless { pinctrl-single,pins = < - AM33XX_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */ - AM33XX_IOPAD(0x848, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */ - AM33XX_IOPAD(0x84c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */ - AM33XX_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ben1.mmc2_dat3 */ - AM33XX_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ - AM33XX_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc1_clk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a1.mmc2_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a2.mmc2_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a3.mmc2_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ben1.mmc2_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc1_clk */ /* WLAN nReset */ - AM33XX_IOPAD(0x860, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a8.gpio1_24 */ /* WLAN nPower down */ - AM33XX_IOPAD(0x870, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wait0.gpio0_30 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_wait0.gpio0_30 */ /* 32kHz Clock */ - AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ >; }; }; @@ -498,10 +498,10 @@ &am33xx_pinmux { spi0_pins: pinmux_spi0 { pinctrl-single,pins = < - AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_sclk.spi0_sclk */ - AM33XX_IOPAD(0x95C, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ - AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0.spi0_d0 */ - AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */ + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) >; }; }; @@ -539,16 +539,16 @@ &am33xx_pinmux { uart0_pins: pinmux_uart0 { pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; uart1_pins: pinmux_uart1 { pinctrl-single,pins = < - AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */ - AM33XX_IOPAD(0x97C, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */ - AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ - AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; }; @@ -591,9 +591,9 @@ usb_pins: pinmux_usb { pinctrl-single,pins = < /* USB0 Over-Current (active low) */ - AM33XX_IOPAD(0x864, PIN_INPUT | MUX_MODE7) /* gpmc_a9.gpio1_25 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE7) /* gpmc_a9.gpio1_25 */ /* USB1 Over-Current (active low) */ - AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE7) /* gpmc_a10.gpio1_26 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7) /* gpmc_a10.gpio1_26 */ >; }; }; @@ -649,16 +649,16 @@ &am33xx_pinmux { user_leds_pins: pinmux_user_leds { pinctrl-single,pins = < - AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE7) /* gpmc_a4.gpio1_20 */ - AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7) /* gpmc_a5.gpio1_21 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE7) /* gpmc_a4.gpio1_20 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* gpmc_a5.gpio1_21 */ >; }; user_buttons_pins: pinmux_user_buttons { pinctrl-single,pins = < - AM33XX_IOPAD(0x858, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */ - AM33XX_IOPAD(0x85C, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a7.gpio1_21 */ - AM33XX_IOPAD(0x964, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio0_7 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_a6.gpio1_22 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_a7.gpio1_21 */ + AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_a8.gpio0_7 */ >; }; }; -- cgit From a3328bf02d77262e396e9382a10af4f7a6c0e5f1 Mon Sep 17 00:00:00 2001 From: Christina Quast Date: Fri, 12 Apr 2019 18:26:22 +0200 Subject: ARM: dts: am335x: phycore-som: Replaced register offsets with defines The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-phycore-som.dtsi | 60 +++++++++++++++---------------- 1 file changed, 30 insertions(+), 30 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-phycore-som.dtsi b/arch/arm/boot/dts/am335x-phycore-som.dtsi index 015adb626b03..23c3039c567e 100644 --- a/arch/arm/boot/dts/am335x-phycore-som.dtsi +++ b/arch/arm/boot/dts/am335x-phycore-som.dtsi @@ -57,22 +57,22 @@ &am33xx_pinmux { ethernet0_pins: pinmux_ethernet0 { pinctrl-single,pins = < - AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ - AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ - AM33XX_IOPAD(0x914, PIN_OUTPUT | MUX_MODE1) /* mii1_txen.rmii1_txen */ - AM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ - AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */ + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) >; }; mdio_pins: pinmux_mdio { pinctrl-single,pins = < /* MDIO */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; }; @@ -104,8 +104,8 @@ &am33xx_pinmux { i2c0_pins: pinmux_i2c0 { pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0) >; }; }; @@ -144,20 +144,20 @@ &am33xx_pinmux { nandflash_pins: pinmux_nandflash { pinctrl-single,pins = < - AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ - AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ - AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ - AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ - AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ - AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ - AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ - AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ - AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ - AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ - AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ - AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ - AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ - AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) >; }; }; @@ -296,10 +296,10 @@ &am33xx_pinmux { spi0_pins: pinmux_spi0 { pinctrl-single,pins = < - AM33XX_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_clk.spi0_clk */ - AM33XX_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_d0.spi0_d0 */ - AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */ - AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) >; }; }; -- cgit From c5ebf24a41d30936cfff3d5b5d762b8e7023fa58 Mon Sep 17 00:00:00 2001 From: Christina Quast Date: Fri, 12 Apr 2019 18:26:23 +0200 Subject: ARM: dts: am335x: sancloud-bbe: Replaced register offsets with defines The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-sancloud-bbe.dts | 62 +++++++++++++++---------------- 1 file changed, 31 insertions(+), 31 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe.dts b/arch/arm/boot/dts/am335x-sancloud-bbe.dts index 35527fdf56cc..7ed27b5c4756 100644 --- a/arch/arm/boot/dts/am335x-sancloud-bbe.dts +++ b/arch/arm/boot/dts/am335x-sancloud-bbe.dts @@ -23,70 +23,70 @@ cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ - AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ - AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ - AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ - AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ - AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ - AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ - AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ - AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ - AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ - AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ - AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; usb_hub_ctrl: usb_hub_ctrl { pinctrl-single,pins = < - AM33XX_IOPAD(0x944, PIN_OUTPUT_PULLUP | MUX_MODE7) /* rmii1_refclk.gpio0_29 */ + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7) /* rmii1_refclk.gpio0_29 */ >; }; mpu6050_pins: pinmux_mpu6050_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x968, PIN_INPUT | MUX_MODE7) /* uart0_ctsn.gpio1_8 */ + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT, MUX_MODE7) /* uart0_ctsn.gpio1_8 */ >; }; lps3331ap_pins: pinmux_lps3331ap_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE7) /* gpmc_a10.gpio1_26 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7) /* gpmc_a10.gpio1_26 */ >; }; }; -- cgit From 631493a16af3acbd7f964f7b2ec8bf76d96a9400 Mon Sep 17 00:00:00 2001 From: Christina Quast Date: Fri, 12 Apr 2019 18:26:24 +0200 Subject: ARM: dts: am335x: sbc-t335: Replaced register offsets with defines The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-sbc-t335.dts | 152 +++++++++++++--------------------- 1 file changed, 56 insertions(+), 96 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-sbc-t335.dts b/arch/arm/boot/dts/am335x-sbc-t335.dts index 917d7ccc9109..07c46a59f1d2 100644 --- a/arch/arm/boot/dts/am335x-sbc-t335.dts +++ b/arch/arm/boot/dts/am335x-sbc-t335.dts @@ -70,122 +70,82 @@ lcd_pins_default: lcd_pins_default { pinctrl-single,pins = < /* gpmc_ad8.lcd_data23 */ - AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad9.lcd_data22 */ - AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad10.lcd_data21 */ - AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad11.lcd_data20 */ - AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad12.lcd_data19 */ - AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad13.lcd_data18 */ - AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad14.lcd_data17 */ - AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad15.lcd_data16 */ - AM33XX_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1) - /* lcd_data0.lcd_data0 */ - AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) - /* lcd_data1.lcd_data1 */ - AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) - /* lcd_data2.lcd_data2 */ - AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) - /* lcd_data3.lcd_data3 */ - AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) - /* lcd_data4.lcd_data4 */ - AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) - /* lcd_data5.lcd_data5 */ - AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) - /* lcd_data6.lcd_data6 */ - AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) - /* lcd_data7.lcd_data7 */ - AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) - /* lcd_data8.lcd_data8 */ - AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) - /* lcd_data9.lcd_data9 */ - AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) - /* lcd_data10.lcd_data10 */ - AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) - /* lcd_data11.lcd_data11 */ - AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) - /* lcd_data12.lcd_data12 */ - AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) - /* lcd_data13.lcd_data13 */ - AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) - /* lcd_data14.lcd_data14 */ - AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) - /* lcd_data15.lcd_data15 */ - AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) - /* lcd_vsync.lcd_vsync */ - AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) - /* lcd_hsync.lcd_hsync */ - AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) - /* lcd_pclk.lcd_pclk */ - AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) - /* lcd_ac_bias_en.lcd_ac_bias_en */ - AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) >; }; lcd_pins_sleep: lcd_pins_sleep { pinctrl-single,pins = < /* gpmc_ad8.lcd_data23 */ - AM33XX_IOPAD(0x820, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad9.lcd_data22 */ - AM33XX_IOPAD(0x824, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad10.lcd_data21 */ - AM33XX_IOPAD(0x828, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad11.lcd_data20 */ - AM33XX_IOPAD(0x82c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad12.lcd_data19 */ - AM33XX_IOPAD(0x830, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad13.lcd_data18 */ - AM33XX_IOPAD(0x834, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad14.lcd_data17 */ - AM33XX_IOPAD(0x838, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad15.lcd_data16 */ - AM33XX_IOPAD(0x83c, PIN_INPUT_PULLDOWN | MUX_MODE7) - /* lcd_data0.lcd_data0 */ - AM33XX_IOPAD(0x8a0, PULL_DISABLE | MUX_MODE7) - /* lcd_data1.lcd_data1 */ - AM33XX_IOPAD(0x8a4, PULL_DISABLE | MUX_MODE7) - /* lcd_data2.lcd_data2 */ - AM33XX_IOPAD(0x8a8, PULL_DISABLE | MUX_MODE7) - /* lcd_data3.lcd_data3 */ - AM33XX_IOPAD(0x8ac, PULL_DISABLE | MUX_MODE7) - /* lcd_data4.lcd_data4 */ - AM33XX_IOPAD(0x8b0, PULL_DISABLE | MUX_MODE7) - /* lcd_data5.lcd_data5 */ - AM33XX_IOPAD(0x8b4, PULL_DISABLE | MUX_MODE7) - /* lcd_data6.lcd_data6 */ - AM33XX_IOPAD(0x8b8, PULL_DISABLE | MUX_MODE7) - /* lcd_data7.lcd_data7 */ - AM33XX_IOPAD(0x8bc, PULL_DISABLE | MUX_MODE7) - /* lcd_data8.lcd_data8 */ - AM33XX_IOPAD(0x8c0, PULL_DISABLE | MUX_MODE7) - /* lcd_data9.lcd_data9 */ - AM33XX_IOPAD(0x8c4, PULL_DISABLE | MUX_MODE7) - /* lcd_data10.lcd_data10 */ - AM33XX_IOPAD(0x8c8, PULL_DISABLE | MUX_MODE7) - /* lcd_data11.lcd_data11 */ - AM33XX_IOPAD(0x8cc, PULL_DISABLE | MUX_MODE7) - /* lcd_data12.lcd_data12 */ - AM33XX_IOPAD(0x8d0, PULL_DISABLE | MUX_MODE7) - /* lcd_data13.lcd_data13 */ - AM33XX_IOPAD(0x8d4, PULL_DISABLE | MUX_MODE7) - /* lcd_data14.lcd_data14 */ - AM33XX_IOPAD(0x8d8, PULL_DISABLE | MUX_MODE7) - /* lcd_data15.lcd_data15 */ - AM33XX_IOPAD(0x8dc, PULL_DISABLE | MUX_MODE7) - /* lcd_vsync.lcd_vsync */ - AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | MUX_MODE7) - /* lcd_hsync.lcd_hsync */ - AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7) - /* lcd_pclk.lcd_pclk */ - AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7) - /* lcd_ac_bias_en.lcd_ac_bias_en */ - AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; }; -- cgit From aa7ed183730ab7667293128ad4d11bf1273f5850 Mon Sep 17 00:00:00 2001 From: Christina Quast Date: Fri, 12 Apr 2019 18:26:25 +0200 Subject: ARM: dts: am335x: shc: Replaced register offsets with defines The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-shc.dts | 226 +++++++++++++++++++-------------------- 1 file changed, 112 insertions(+), 114 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-shc.dts b/arch/arm/boot/dts/am335x-shc.dts index bfbe27a80006..5b0368504015 100644 --- a/arch/arm/boot/dts/am335x-shc.dts +++ b/arch/arm/boot/dts/am335x-shc.dts @@ -382,193 +382,191 @@ clkout2_pin: pinmux_clkout2_pin { pinctrl-single,pins = < /* xdma_event_intr1.clkout2 */ - AM33XX_IOPAD(0x9b4, PIN_INPUT | MUX_MODE6) + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT, MUX_MODE6) >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ - AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE0) >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ - AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < - /* mdio_data.mdio_data */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) - /* mdio_clk.mdio_clk */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; ehrpwm1_pins: pinmux_ehrpwm1 { pinctrl-single,pins = < - AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE6) /* gpmc_a3.gpio1_19 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE6) /* gpmc_a3.gpio1_19 */ >; }; emmc_pins: pinmux_emmc_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x880, PIN_INPUT | MUX_MODE2) - AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) - AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) - AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) - AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) - AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) - AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) - AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) - AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) - AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) >; }; i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) - AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0) >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE5) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE5) >; }; mmc3_pins: pinmux_mmc3_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x830, PIN_INPUT | MUX_MODE3) - AM33XX_IOPAD(0x834, PIN_INPUT | MUX_MODE3) - AM33XX_IOPAD(0x838, PIN_INPUT | MUX_MODE3) - AM33XX_IOPAD(0x83c, PIN_INPUT | MUX_MODE3) - AM33XX_IOPAD(0x888, PIN_INPUT | MUX_MODE3) - AM33XX_IOPAD(0x88c, PIN_INPUT | MUX_MODE3) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT, MUX_MODE3) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT, MUX_MODE3) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT, MUX_MODE3) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT, MUX_MODE3) + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT, MUX_MODE3) + AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT, MUX_MODE3) >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x968, PIN_INPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x96c, PIN_OUTPUT | MUX_MODE0) - AM33XX_IOPAD(0x970, PIN_INPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x974, PIN_OUTPUT | MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT, MUX_MODE0) >; }; uart1_pins: pinmux_uart1 { pinctrl-single,pins = < - AM33XX_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x97C, PIN_OUTPUT | MUX_MODE0) - AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0) - AM33XX_IOPAD(0x984, PIN_OUTPUT | MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0) >; }; uart2_pins: pinmux_uart2_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1) - AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) >; }; uart4_pins: pinmux_uart4_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6) - AM33XX_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE6) + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLUP, MUX_MODE6) >; }; user_leds_s0: user_leds_s0 { pinctrl-single,pins = < - AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x844, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x85c, PIN_OUTPUT_PULLUP | MUX_MODE7) - AM33XX_IOPAD(0x860, PIN_INPUT | MUX_MODE7) - AM33XX_IOPAD(0x864, PIN_INPUT | MUX_MODE7) - AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE7) - AM33XX_IOPAD(0x86c, PIN_INPUT | MUX_MODE7) - AM33XX_IOPAD(0x878, PIN_OUTPUT_PULLUP | MUX_MODE7) - AM33XX_IOPAD(0x87c, PIN_INPUT | MUX_MODE7) - AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x894, PIN_INPUT | MUX_MODE7) - AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x958, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x964, PIN_OUTPUT_PULLUP | MUX_MODE7) - AM33XX_IOPAD(0x9a0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x9a4, PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x9a8, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLUP | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLUP, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_OUTPUT_PULLUP, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_INPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT_PULLUP, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSR, PIN_OUTPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE7) >; }; }; -- cgit From b1e0c487f31d1fb9536c53301a079e73f2758537 Mon Sep 17 00:00:00 2001 From: Christina Quast Date: Fri, 12 Apr 2019 18:26:26 +0200 Subject: ARM: dts: am335x: sl50: Replaced register offsets with defines The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-sl50.dts | 208 +++++++++++++++++++------------------- 1 file changed, 104 insertions(+), 104 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-sl50.dts b/arch/arm/boot/dts/am335x-sl50.dts index 38d57b89f7d3..1ac0c8aa98c5 100644 --- a/arch/arm/boot/dts/am335x-sl50.dts +++ b/arch/arm/boot/dts/am335x-sl50.dts @@ -218,227 +218,227 @@ audio_pins: pinmux_audio_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */ - AM33XX_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */ - AM33XX_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */ - AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0.mcasp0_axr0 */ - AM33XX_IOPAD(0x99c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) >; }; audio_pa_pins: pinmux_audio_pa_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* SoundPA_en - mcasp0_aclkr.gpio3_18 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLDOWN, MUX_MODE7) /* SoundPA_en - mcasp0_aclkr.gpio3_18 */ >; }; audio_mclk_pins: pinmux_audio_mclk_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.gpio1_27 */ >; }; backlight0_pins: pinmux_backlight0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE7) /* gpmc_wen.gpio2_4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE7) /* gpmc_wen.gpio2_4 */ >; }; backlight1_pins: pinmux_backlight1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE7) /* gpmc_ad10.gpio0_26 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad10.gpio0_26 */ >; }; lcd_pins: pinmux_lcd_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ - AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ - AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ - AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ - AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ - AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ - AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ - AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ - AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ - AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ - AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ - AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ - AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ - AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ - AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ - AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ - AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_vsync.lcd_vsync */ - AM33XX_IOPAD(0x8e4, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_hsync.lcd_hsync */ - AM33XX_IOPAD(0x8e8, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_pclk.lcd_pclk */ - AM33XX_IOPAD(0x8ec, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; led_pins: pinmux_led_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7) /* gpmc_a5.gpio1_21 */ - AM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7) /* gpmc_a6.gpio1_22 */ - AM33XX_IOPAD(0x85c, PIN_OUTPUT | MUX_MODE7) /* gpmc_a7.gpio1_23 */ - AM33XX_IOPAD(0x860, PIN_OUTPUT | MUX_MODE7) /* gpmc_a8.gpio1_24 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* gpmc_a5.gpio1_21 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) /* gpmc_a6.gpio1_22 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7) /* gpmc_a7.gpio1_23 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7) /* gpmc_a8.gpio1_24 */ >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; uart1_pins: pinmux_uart1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ - AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; uart4_pins: pinmux_uart4_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6) /* gpmc_wait0.uart4_rxd */ - AM33XX_IOPAD(0x874, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* gpmc_wpn.uart4_txd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) /* gpmc_wait0.uart4_rxd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* gpmc_wpn.uart4_txd */ >; }; i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; i2c2_pins: pinmux_i2c2_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.i2c2_sda */ - AM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.i2c2_scl */ + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_ctsn.i2c2_sda */ + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_rtsn.i2c2_scl */ >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ - AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */ - AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */ - AM33XX_IOPAD(0x918, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */ - AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */ - AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */ - AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */ - AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */ - AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */ - AM33XX_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */ - AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */ - AM33XX_IOPAD(0x938, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */ - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */ - AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE0) >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ - AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) /* Ethernet */ - AM33XX_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE7) /* Ethernet_nRST - gpmc_ad14.gpio1_14 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE7) /* Ethernet_nRST - gpmc_ad14.gpio1_14 */ >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x96c, PIN_INPUT | MUX_MODE7) /* uart0_rtsn.gpio1_9 */ + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE7) /* uart0_rtsn.gpio1_9 */ >; }; emmc_pwrseq_pins: pinmux_emmc_pwrseq_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a4.gpio1_20 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a4.gpio1_20 */ >; }; emmc_pins: pinmux_emmc_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ - AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ - AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ - AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ >; }; ehrpwm1_pins: pinmux_ehrpwm1a_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE6) /* gpmc_a2.ehrpwm1a */ - AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE6) /* gpmc_a3.ehrpwm1b */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE6) /* gpmc_a2.ehrpwm1a */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE6) /* gpmc_a3.ehrpwm1b */ >; }; rtc0_irq_pins: pinmux_rtc0_irq_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ad9.gpio0_23 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_ad9.gpio0_23 */ >; }; spi0_pins: pinmux_spi0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* SPI0_MOSI - spi0_d0.spi0_d0 */ - AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* SPI0_MISO - spi0_d1.spi0_d1 */ - AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* SPI0_CLK - spi0_clk.spi0_clk */ - AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* SPI0_CS0 (NBATTSS) - spi0_cs0.spi0_cs0 */ - AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE0) /* SPI0_CS1 (FPGA_FLASH_NCS) - spi0_cs1.spi0_cs1 */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_MOSI */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_MISO */ + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_CS0 (NBATTSS) */ + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_CS1 (FPGA_FLASH_NCS) */ >; }; lwb_pins: pinmux_lwb_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE7) /* nKbdInt - gpmc_ad12.gpio1_12 */ - AM33XX_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE7) /* nKbdReset - gpmc_ad13.gpio1_13 */ - AM33XX_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7) /* USB1_enPower - gpmc_a1.gpio1_17 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE7) /* nKbdInt - gpmc_ad12.gpio1_12 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE7) /* nKbdReset - gpmc_ad13.gpio1_13 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE7) /* USB1_enPower - gpmc_a1.gpio1_17 */ /* PDI Bus - Battery system */ - AM33XX_IOPAD(0x840, PIN_INPUT_PULLUP | MUX_MODE7) /* nBattReset gpmc_a0.gpio1_16 */ - AM33XX_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE7) /* BattPDIData gpmc_ad15.gpio1_15 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLUP, MUX_MODE7) /* nBattReset gpmc_a0.gpio1_16 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE7) /* BattPDIData gpmc_ad15.gpio1_15 */ /* FPGA */ - AM33XX_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE7) /* FPGA_DONE - gpmc_ad8.gpio0_22 */ - AM33XX_IOPAD(0x840, PIN_INPUT_PULLUP | MUX_MODE7) /* FPGA_NRST - gpmc_a0.gpio1_16 */ - AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) /* FPGA_RUN - gpmc_a1.gpio1_17 */ - AM33XX_IOPAD(0x864, PIN_INPUT_PULLUP | MUX_MODE7) /* ENFPGA - gpmc_a9.gpio1_25 */ - AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) /* FPGA_PROGRAM - gpmc_a10.gpio1_26 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE7) /* FPGA_DONE - gpmc_ad8.gpio0_22 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLUP, MUX_MODE7) /* FPGA_NRST - gpmc_a0.gpio1_16 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* FPGA_RUN - gpmc_a1.gpio1_17 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLUP, MUX_MODE7) /* ENFPGA - gpmc_a9.gpio1_25 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* FPGA_PROGRAM - gpmc_a10.gpio1_26 */ >; }; }; -- cgit From e5b258e53e58a3afd228bbef4d376c7a470cfa58 Mon Sep 17 00:00:00 2001 From: Christina Quast Date: Fri, 12 Apr 2019 18:26:27 +0200 Subject: ARM: dts: am335x: wega: Replaced register offsets with defines The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-wega.dtsi | 68 +++++++++++++++++++------------------- 1 file changed, 34 insertions(+), 34 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-wega.dtsi b/arch/arm/boot/dts/am335x-wega.dtsi index 8ce541739b24..b7d28a20341f 100644 --- a/arch/arm/boot/dts/am335x-wega.dtsi +++ b/arch/arm/boot/dts/am335x-wega.dtsi @@ -32,11 +32,11 @@ &am33xx_pinmux { mcasp0_pins: pinmux_mcasp0 { pinctrl-single,pins = < - AM33XX_IOPAD(0x9AC, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahclkx.mcasp0_ahclkx */ - AM33XX_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */ - AM33XX_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */ - AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0.mcasp0_axr0 */ - AM33XX_IOPAD(0x9A8, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr1.mcasp0_axr1 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; }; @@ -84,8 +84,8 @@ &am33xx_pinmux { dcan1_pins: pinmux_dcan1 { pinctrl-single,pins = < - AM33XX_IOPAD(0x968, PIN_OUTPUT_PULLUP | MUX_MODE2) /* uart0_ctsn.d_can1_tx */ - AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE2) /* uart0_rtsn.d_can1_rx */ + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart0_ctsn.d_can1_tx */ + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) /* uart0_rtsn.d_can1_rx */ >; }; }; @@ -100,20 +100,20 @@ &am33xx_pinmux { ethernet1_pins: pinmux_ethernet1 { pinctrl-single,pins = < - AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE1) /* gpmc_a0.mii2_txen */ - AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a1.mii2_rxdv */ - AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE1) /* gpmc_a2.mii2_txd3 */ - AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE1) /* gpmc_a3.mii2_txd2 */ - AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE1) /* gpmc_a4.mii2_txd1 */ - AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE1) /* gpmc_a5.mii2_txd0 */ - AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a6.mii2_txclk */ - AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a7.mii2_rxclk */ - AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a8.mii2_rxd3 */ - AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a9.mii2_rxd2 */ - AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a10.mii2_rxd1 */ - AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a11.mii2_rxd0 */ - AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_wpn.mii2_rxerr */ - AM33XX_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_ben1.mii2_col */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* gpmc_a0.mii2_txen */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a1.mii2_rxdv */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1) /* gpmc_a2.mii2_txd3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1) /* gpmc_a3.mii2_txd2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1) /* gpmc_a4.mii2_txd1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1) /* gpmc_a5.mii2_txd0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a6.mii2_txclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a7.mii2_rxclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a8.mii2_rxd3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a9.mii2_rxd2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a10.mii2_rxd1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a11.mii2_rxd0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_wpn.mii2_rxerr */ + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_ben1.mii2_col */ >; }; }; @@ -141,13 +141,13 @@ &am33xx_pinmux { mmc1_pins: pinmux_mmc1 { pinctrl-single,pins = < - AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ - AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ - AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ - AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ - AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ - AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ - AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE7) /* spi0_cs1.mmc0_sdcd */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7) /* spi0_cs1.mmc0_sdcd */ >; }; }; @@ -171,17 +171,17 @@ &am33xx_pinmux { uart0_pins: pinmux_uart0 { pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; uart1_pins: pinmux_uart1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ - AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ - AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */ - AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */ + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; }; -- cgit From f6eb973db22ab5636cfcdabe171d4b753525de4e Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 13 Apr 2019 18:34:21 +0200 Subject: ARM: dts: meson: add support for the RTC The 32-bit Meson SoCs have an RTC block in the AO (always on) area. The RTC requires an external 32.768 kHz oscillator to work properly. Whether or not this crystal exists depends on the board, so it has to be added for each board.dts (instead of adding it somewhere in a generic .dtsi). Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson.dtsi | 9 +++++++++ arch/arm/boot/dts/meson8.dtsi | 5 +++++ arch/arm/boot/dts/meson8b.dtsi | 5 +++++ 3 files changed, 19 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index 6f54a8897574..8841783aceec 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -252,6 +252,15 @@ #size-cells = <0>; status = "disabled"; }; + + rtc: rtc@740 { + compatible = "amlogic,meson6-rtc"; + reg = <0x740 0x14>; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + }; }; usb0: usb@c9040000 { diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index d2ec4af82cc5..7ef442462ea4 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -541,6 +541,11 @@ compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; }; +&rtc { + compatible = "amlogic,meson8-rtc"; + resets = <&reset RESET_RTC>; +}; + &saradc { compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc"; clocks = <&clkc CLKID_XTAL>, diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index df42e48f1cc1..800cd65fc50a 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -510,6 +510,11 @@ compatible = "amlogic,meson8b-pwm"; }; +&rtc { + compatible = "amlogic,meson8b-rtc"; + resets = <&reset RESET_RTC>; +}; + &saradc { compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc"; clocks = <&clkc CLKID_XTAL>, -- cgit From 6ffdc4738c5a8856afc46da92453fe7c086f1eaa Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 13 Apr 2019 18:34:22 +0200 Subject: ARM: dts: meson8b: ec100: enable the RTC The RTC is always enabled on this board since the battery is already connected in the factory. According to the schematics the VCC_RTC regulator (which is either powered by the internal 3.3V or a battery) is connected to the 0.9V RTC_VDD input of the SoCs. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b-ec100.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts index 3ca9638fad09..9bf4249cb60d 100644 --- a/arch/arm/boot/dts/meson8b-ec100.dts +++ b/arch/arm/boot/dts/meson8b-ec100.dts @@ -88,6 +88,14 @@ }; }; + rtc32k_xtal: rtc32k-xtal-clk { + /* X2 in the schematics */ + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "RTC32K"; + #clock-cells = <0>; + }; + usb_vbus: regulator-usb-vbus { /* * Silergy SY6288CCAC-GP 2A Power Distribution Switch. @@ -347,6 +355,12 @@ clock-names = "clkin0"; }; +&rtc { + status = "okay"; + clocks = <&rtc32k_xtal>; + vdd-supply = <&vcc_rtc>; +}; + /* exposed through the pin headers labeled "URDUG1" on the top of the PCB */ &uart_AO { status = "okay"; -- cgit From 09ee951617d9af8a86d228b2ed34035076ab6001 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 13 Apr 2019 18:34:23 +0200 Subject: ARM: dts: meson8b: odroid-c1: prepare support for the RTC The Odroid-C1 has the 32.768 kHz oscillator (X3 in the schematics) which is required for the RTC. A battery can be connected separately (to the BT1 header) - then the "rtc" node can be enabled manually. By default the RTC is disabled because the boards typically come without the RTC battery. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b-odroidc1.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts index 0157646e3a89..f3ad9397f670 100644 --- a/arch/arm/boot/dts/meson8b-odroidc1.dts +++ b/arch/arm/boot/dts/meson8b-odroidc1.dts @@ -124,6 +124,14 @@ io-channels = <&saradc 8>; }; + rtc32k_xtal: rtc32k-xtal-clk { + /* X3 in the schematics */ + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "RTC32K"; + #clock-cells = <0>; + }; + vcc_1v8: regulator-vcc-1v8 { /* * RICHTEK RT9179 configured for a fixed output voltage of @@ -345,6 +353,12 @@ clock-names = "clkin0"; }; +&rtc { + /* needs to be enabled manually when a battery is connected */ + clocks = <&rtc32k_xtal>; + vdd-supply = <&vdd_rtc>; +}; + &uart_AO { status = "okay"; pinctrl-0 = <&uart_ao_a_pins>; -- cgit From 3d109bdca9811b5b8362bb8632d621ad36b3bbe7 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 16 Apr 2019 10:28:00 +0200 Subject: ARM: dts: sunxi: Remove useless phy-names from EHCI and OHCI Neither the OHCI or EHCI bindings are using the phy-names property, so we can just drop it. Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 4 ---- arch/arm/boot/dts/sun5i.dtsi | 2 -- arch/arm/boot/dts/sun6i-a31.dtsi | 4 ---- arch/arm/boot/dts/sun7i-a20.dtsi | 4 ---- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 -- arch/arm/boot/dts/sun8i-a83t.dtsi | 3 --- arch/arm/boot/dts/sun8i-r40.dtsi | 4 ---- arch/arm/boot/dts/sun9i-a80.dtsi | 5 ----- 8 files changed, 28 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index ef6ec526f394..e88daa4ef1af 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -520,7 +520,6 @@ interrupts = <39>; clocks = <&ccu CLK_AHB_EHCI0>; phys = <&usbphy 1>; - phy-names = "usb"; status = "disabled"; }; @@ -530,7 +529,6 @@ interrupts = <64>; clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>; phys = <&usbphy 1>; - phy-names = "usb"; status = "disabled"; }; @@ -610,7 +608,6 @@ interrupts = <40>; clocks = <&ccu CLK_AHB_EHCI1>; phys = <&usbphy 2>; - phy-names = "usb"; status = "disabled"; }; @@ -620,7 +617,6 @@ interrupts = <65>; clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>; phys = <&usbphy 2>; - phy-names = "usb"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index cb820bd7974c..0d71b01967a3 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -391,7 +391,6 @@ interrupts = <39>; clocks = <&ccu CLK_AHB_EHCI>; phys = <&usbphy 1>; - phy-names = "usb"; status = "disabled"; }; @@ -401,7 +400,6 @@ interrupts = <40>; clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>; phys = <&usbphy 1>; - phy-names = "usb"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index fa983f9ff5f5..c04efad81bbc 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -543,7 +543,6 @@ clocks = <&ccu CLK_AHB1_EHCI0>; resets = <&ccu RST_AHB1_EHCI0>; phys = <&usbphy 1>; - phy-names = "usb"; status = "disabled"; }; @@ -554,7 +553,6 @@ clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>; resets = <&ccu RST_AHB1_OHCI0>; phys = <&usbphy 1>; - phy-names = "usb"; status = "disabled"; }; @@ -565,7 +563,6 @@ clocks = <&ccu CLK_AHB1_EHCI1>; resets = <&ccu RST_AHB1_EHCI1>; phys = <&usbphy 2>; - phy-names = "usb"; status = "disabled"; }; @@ -576,7 +573,6 @@ clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>; resets = <&ccu RST_AHB1_OHCI1>; phys = <&usbphy 2>; - phy-names = "usb"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 794c915f504b..9ad8e445b240 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -612,7 +612,6 @@ interrupts = ; clocks = <&ccu CLK_AHB_EHCI0>; phys = <&usbphy 1>; - phy-names = "usb"; status = "disabled"; }; @@ -622,7 +621,6 @@ interrupts = ; clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>; phys = <&usbphy 1>; - phy-names = "usb"; status = "disabled"; }; @@ -705,7 +703,6 @@ interrupts = ; clocks = <&ccu CLK_AHB_EHCI1>; phys = <&usbphy 2>; - phy-names = "usb"; status = "disabled"; }; @@ -715,7 +712,6 @@ interrupts = ; clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>; phys = <&usbphy 2>; - phy-names = "usb"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index f76aad0c5d4d..af2fa694a467 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -307,7 +307,6 @@ clocks = <&ccu CLK_BUS_EHCI>; resets = <&ccu RST_BUS_EHCI>; phys = <&usbphy 1>; - phy-names = "usb"; status = "disabled"; }; @@ -318,7 +317,6 @@ clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>; resets = <&ccu RST_BUS_OHCI>; phys = <&usbphy 1>; - phy-names = "usb"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index b105a85467b3..392b0cabbf0d 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -632,7 +632,6 @@ clocks = <&ccu CLK_BUS_EHCI0>; resets = <&ccu RST_BUS_EHCI0>; phys = <&usbphy 1>; - phy-names = "usb"; status = "disabled"; }; @@ -644,7 +643,6 @@ clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>; resets = <&ccu RST_BUS_OHCI0>; phys = <&usbphy 1>; - phy-names = "usb"; status = "disabled"; }; @@ -656,7 +654,6 @@ clocks = <&ccu CLK_BUS_EHCI1>; resets = <&ccu RST_BUS_EHCI1>; phys = <&usbphy 2>; - phy-names = "usb"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index 56c6885b02d1..bb856e53b806 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -273,7 +273,6 @@ clocks = <&ccu CLK_BUS_EHCI1>; resets = <&ccu RST_BUS_EHCI1>; phys = <&usbphy 1>; - phy-names = "usb"; status = "disabled"; }; @@ -285,7 +284,6 @@ <&ccu CLK_USB_OHCI1>; resets = <&ccu RST_BUS_OHCI1>; phys = <&usbphy 1>; - phy-names = "usb"; status = "disabled"; }; @@ -296,7 +294,6 @@ clocks = <&ccu CLK_BUS_EHCI2>; resets = <&ccu RST_BUS_EHCI2>; phys = <&usbphy 2>; - phy-names = "usb"; status = "disabled"; }; @@ -308,7 +305,6 @@ <&ccu CLK_USB_OHCI2>; resets = <&ccu RST_BUS_OHCI2>; phys = <&usbphy 2>; - phy-names = "usb"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index c1aa26db44ae..0c1eec9000e3 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -342,7 +342,6 @@ clocks = <&usb_clocks CLK_BUS_HCI0>; resets = <&usb_clocks RST_USB0_HCI>; phys = <&usbphy1>; - phy-names = "usb"; status = "disabled"; }; @@ -354,7 +353,6 @@ <&usb_clocks CLK_USB_OHCI0>; resets = <&usb_clocks RST_USB0_HCI>; phys = <&usbphy1>; - phy-names = "usb"; status = "disabled"; }; @@ -376,7 +374,6 @@ clocks = <&usb_clocks CLK_BUS_HCI1>; resets = <&usb_clocks RST_USB1_HCI>; phys = <&usbphy2>; - phy-names = "usb"; status = "disabled"; }; @@ -406,7 +403,6 @@ clocks = <&usb_clocks CLK_BUS_HCI2>; resets = <&usb_clocks RST_USB2_HCI>; phys = <&usbphy3>; - phy-names = "usb"; status = "disabled"; }; @@ -418,7 +414,6 @@ <&usb_clocks CLK_USB_OHCI2>; resets = <&usb_clocks RST_USB2_HCI>; phys = <&usbphy3>; - phy-names = "usb"; status = "disabled"; }; -- cgit From 0a3df8bb6dad730d8d368f0dc4c3d7888bd5b789 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 16 Apr 2019 10:28:01 +0200 Subject: ARM: dts: sunxi: h3/h5: Remove useless phy-names from EHCI and OHCI Neither the OHCI or EHCI bindings are using the phy-names property, so we can just drop it. Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 6 ------ 1 file changed, 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 3b18fd71efc1..84977d4eb97a 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -304,7 +304,6 @@ clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>; resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>; phys = <&usbphy 1>; - phy-names = "usb"; status = "disabled"; }; @@ -316,7 +315,6 @@ <&ccu CLK_USB_OHCI1>; resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>; phys = <&usbphy 1>; - phy-names = "usb"; status = "disabled"; }; @@ -327,7 +325,6 @@ clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>; resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>; phys = <&usbphy 2>; - phy-names = "usb"; status = "disabled"; }; @@ -339,7 +336,6 @@ <&ccu CLK_USB_OHCI2>; resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>; phys = <&usbphy 2>; - phy-names = "usb"; status = "disabled"; }; @@ -350,7 +346,6 @@ clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>; resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>; phys = <&usbphy 3>; - phy-names = "usb"; status = "disabled"; }; @@ -362,7 +357,6 @@ <&ccu CLK_USB_OHCI3>; resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>; phys = <&usbphy 3>; - phy-names = "usb"; status = "disabled"; }; -- cgit From 8cb35d345c08ba2dac3a9df705ae28305f7eaf97 Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Wed, 10 Apr 2019 09:10:07 +0200 Subject: ARM: tegra: Convert to SPDX license tags for Tegra124 Apalis Replace boiler plate licenses texts with the SPDX license identifiers in Colibri/Apalis DTS files. Signed-off-by: Igor Opaniuk [treding@nvidia.com: drop unneeded parentheses, keep license at X11] Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-emc.dtsi | 39 ++--------------------------- arch/arm/boot/dts/tegra124-apalis-eval.dts | 40 ++---------------------------- arch/arm/boot/dts/tegra124-apalis.dtsi | 40 ++---------------------------- 3 files changed, 6 insertions(+), 113 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi index ca2c3a557895..d18eaf4a4a3a 100644 --- a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi @@ -1,42 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* - * Copyright 2016 Toradex AG + * Copyright 2016-2019 Toradex AG * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ / { diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/tegra124-apalis-eval.dts index eaee10ef6512..ceb3f6388c7d 100644 --- a/arch/arm/boot/dts/tegra124-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-eval.dts @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* - * Copyright 2016-2018 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright 2016-2019 Toradex AG */ /dts-v1/; diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index 13c93cd507d8..fdc8a4c5aab6 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* - * Copyright 2016-2018 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright 2016-2019 Toradex AG */ #include "tegra124.dtsi" -- cgit From 4a28f63449d0398482e4fb4c8527055250e8e387 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 17 Apr 2019 10:59:24 +0200 Subject: ARM: tegra: Remove gratuitous parentheses in SPDX license identifier Parentheses in the SPDX license identifier are only used to group sub- expressions. If there's no need for such grouping, the parentheses can be omitted. Reviewed-by: Igor Opaniuk Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts | 2 +- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts index 7961eb4bd803..826b776fbe6f 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// SPDX-License-Identifier: GPL-2.0 OR MIT /* * Copyright 2016-2018 Toradex AG */ diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index 367eb8c86098..891f7b76daa4 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// SPDX-License-Identifier: GPL-2.0 OR MIT /* * Copyright 2016-2018 Toradex AG */ -- cgit From 0c2f4ebbd7632e533ca0dfc39781c4b2cb632ec3 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 21 Jan 2019 17:08:46 +0100 Subject: ARM: tegra: apalis: Move PLL power supplies to XUSB pad controller The XUSB pad controller is responsible for supplying power to the PLLs used to drive the various USB, PCI and SATA pads. Move the PLL power supplies from the PCIe and XUSB controllers to the XUSB pad controller to make sure they are available when needed. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 7 +++++++ arch/arm/boot/dts/tegra124-apalis.dtsi | 5 +++++ 2 files changed, 12 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index 891f7b76daa4..0462ed2dd8b8 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -17,6 +17,7 @@ pcie@1003000 { status = "okay"; + avddio-pex-supply = <®_1v05_vdd>; avdd-pex-pll-supply = <®_1v05_vdd>; avdd-pll-erefe-supply = <®_1v05_avdd>; @@ -1796,6 +1797,7 @@ <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0"; + avddio-pex-supply = <®_1v05_vdd>; avdd-pll-erefe-supply = <®_1v05_avdd>; avdd-pll-utmip-supply = <®_1v8_vddio>; @@ -1807,6 +1809,11 @@ }; padctl@7009f000 { + avdd-pll-utmip-supply = <®_1v8_vddio>; + avdd-pll-erefe-supply = <®_1v05_avdd>; + avdd-pex-pll-supply = <®_1v05_vdd>; + hvdd-pex-pll-e-supply = <®_module_3v3>; + pads { usb2 { status = "okay"; diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index fdc8a4c5aab6..d1e8593ef0d9 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -1801,6 +1801,11 @@ }; padctl@7009f000 { + avdd-pll-utmip-supply = <®_1v8_vddio>; + avdd-pll-erefe-supply = <®_1v05_avdd>; + avdd-pex-pll-supply = <®_1v05_vdd>; + hvdd-pex-pll-e-supply = <®_module_3v3>; + pads { usb2 { status = "okay"; -- cgit From cbfe6d036f2a78dcbe33d04ab954d97b43a9e166 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 21 Jan 2019 17:09:55 +0100 Subject: ARM: tegra: jetson-tk1: Move PLL power supplies to XUSB pad controller The XUSB pad controller is responsible for supplying power to the PLLs used to drive the various USB, PCI and SATA pads. Move the PLL power supplies from the PCIe and XUSB controllers to the XUSB pad controller to make sure they are available when needed. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index 33bbb1c5285d..d5fd642f8b77 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1721,6 +1721,11 @@ padctl@7009f000 { status = "okay"; + avdd-pll-utmip-supply = <&vddio_1v8>; + avdd-pll-erefe-supply = <&avdd_1v05_run>; + avdd-pex-pll-supply = <&vdd_1v05_run>; + hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; + pads { usb2 { status = "okay"; -- cgit From 965ae23289d4d9cee1dba743b281daa7eb880146 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 21 Jan 2019 17:10:30 +0100 Subject: ARM: tegra: nyan: Move PLL power supplies to XUSB pad controller The XUSB pad controller is responsible for supplying power to the PLLs used to drive the various USB, PCI and SATA pads. Move the PLL power supplies from the XUSB controller to the XUSB pad controller to make sure they are available when needed. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-nyan.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index a1acd872bcf2..3b10f475037f 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -414,6 +414,11 @@ padctl@7009f000 { status = "okay"; + avdd-pll-utmip-supply = <&vddio_1v8>; + avdd-pll-erefe-supply = <&avdd_1v05_run>; + avdd-pex-pll-supply = <&vdd_1v05_run>; + hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; + pads { usb2 { status = "okay"; -- cgit From de36d5451299b03e4647c73837d0068b3cc5b9ac Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 21 Jan 2019 17:11:10 +0100 Subject: ARM: tegra: venice2: Move PLL power supplies to XUSB pad controller The XUSB pad controller is responsible for supplying power to the PLLs used to drive the various USB, PCI and SATA pads. Move the PLL power supplies from the PCIe and XUSB controllers to the XUSB pad controller to make sure they are available when needed. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-venice2.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 4882b61fb680..5d5e6e18bc7b 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -921,6 +921,11 @@ }; padctl@7009f000 { + avdd-pll-utmip-supply = <&vddio_1v8>; + avdd-pll-erefe-supply = <&avdd_1v05_run>; + avdd-pex-pll-supply = <&vdd_1v05_run>; + hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; + pads { usb2 { status = "okay"; -- cgit From 147f3d5cc676defa4d50871abd2cfaea6488c9cf Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 16 Apr 2019 10:57:41 +0200 Subject: ARM: dts: sun4i: protab2: Remove stale pinctrl-names entry Some nodes still have pinctrl-names entry, yet they don't have any pinctrl group anymore. Drop them. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts b/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts index bcb2fc0c56b1..24a3d23e1952 100644 --- a/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts +++ b/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts @@ -197,7 +197,6 @@ }; &usbphy { - pinctrl-names = "default"; usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; -- cgit From 15a48503ccd8db4da9bf1e80ed01401b64e18d30 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 16 Apr 2019 10:57:42 +0200 Subject: ARM: dts: sun4i: lime: Fix the USB PHY ID detect GPIO properties While the USB PHY Device Tree mandates that the name of the ID detect pin should be usb0_id_det-gpios, a significant number of device tree use usb0_id_det-gpio instead. This was functional because the GPIO framework falls back to the gpio suffix that is legacy, but we should fix this. Commit 2c515b0d05a9 ("ARM: sunxi: Fix the USB PHY ID detect GPIO properties") was supposed to fix this, but one fell through the cracks. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts index 7c1f379c3aed..a8e537fd4bd6 100644 --- a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts +++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts @@ -217,7 +217,7 @@ }; &usbphy { - usb0_id_det-gpio = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; -- cgit From 4b03e16d3013a3991dec2ef44b9b7185338717a6 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 16 Apr 2019 10:57:43 +0200 Subject: ARM: dts: sun6i: i7: Remove useless property The I7 DTS uses an spdif-out property with an "okay" value. However, that property isn't documented anywhere, and isn't used anywhere either. Remove it. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31-i7.dts | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun6i-a31-i7.dts b/arch/arm/boot/dts/sun6i-a31-i7.dts index 0832ac5ae3ec..091eb2ac53b3 100644 --- a/arch/arm/boot/dts/sun6i-a31-i7.dts +++ b/arch/arm/boot/dts/sun6i-a31-i7.dts @@ -157,7 +157,6 @@ &spdif { pinctrl-names = "default"; pinctrl-0 = <&spdif_tx_pin>; - spdif-out = "okay"; status = "okay"; }; -- cgit From 66dc4e4bfc0b3ce8b6cb14d31c3676b5dde623cf Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 16 Apr 2019 10:57:44 +0200 Subject: ARM: dts: sun5i: Reorder pinctrl nodes We try to keep the PIO nodes ordered alphabetically, but this doesn't always work out. Let's fix it. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index 0d71b01967a3..2fb438c4fe9d 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -504,18 +504,18 @@ bias-pull-up; }; - mmc2_8bit_pins: mmc2-8bit-pins { + mmc2_4bit_pc_pins: mmc2-4bit-pc-pins { pins = "PC6", "PC7", "PC8", "PC9", - "PC10", "PC11", "PC12", "PC13", - "PC14", "PC15"; + "PC10", "PC11"; function = "mmc2"; drive-strength = <30>; bias-pull-up; }; - mmc2_4bit_pc_pins: mmc2-4bit-pc-pins { + mmc2_8bit_pins: mmc2-8bit-pins { pins = "PC6", "PC7", "PC8", "PC9", - "PC10", "PC11"; + "PC10", "PC11", "PC12", "PC13", + "PC14", "PC15"; function = "mmc2"; drive-strength = <30>; bias-pull-up; @@ -539,6 +539,11 @@ function = "nand0"; }; + pwm0_pin: pwm0-pin { + pins = "PB2"; + function = "pwm"; + }; + spi2_pe_pins: spi2-pe-pins { pins = "PE1", "PE2", "PE3"; function = "spi2"; @@ -578,11 +583,6 @@ pins = "PG11", "PG12"; function = "uart3"; }; - - pwm0_pin: pwm0-pin { - pins = "PB2"; - function = "pwm"; - }; }; timer@1c20c00 { -- cgit From 7aaee3d11689aee0f23f7bf4f6d7b4015bcdb467 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 16 Apr 2019 10:57:45 +0200 Subject: ARM: dts: sun8i: mapleboard: Remove cd-inverted The cd-inverted property can also be expressed using the GPIO flags. Use the active low GPIO flag to have the same semantic without the confusion. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts b/arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts index 6d626ec1f747..ff0a7a952e0c 100644 --- a/arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts +++ b/arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts @@ -91,8 +91,7 @@ &mmc0 { vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ - cd-inverted; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ status = "okay"; }; -- cgit From 94b42a96dad89da7602828bab481feef70b76ccb Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 18 Apr 2019 00:12:04 +0900 Subject: ARM: dts: kzm9d: Add rw parameter to bootargs Add rw as bootargs parameter to make the KZM9D board bootargs match other boards from Renesas. No need to be special. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/emev2-kzm9d.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts index 1bb8e5c9d029..abfff54d6de5 100644 --- a/arch/arm/boot/dts/emev2-kzm9d.dts +++ b/arch/arm/boot/dts/emev2-kzm9d.dts @@ -25,7 +25,7 @@ }; chosen { - bootargs = "ignore_loglevel root=/dev/nfs ip=dhcp"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; stdout-path = "serial1:115200n8"; }; -- cgit From 44861e54861ef99f4bec4b084eeeee5010df7915 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 18 Apr 2019 00:12:14 +0900 Subject: ARM: dts: bockw: Reorder bootargs Reorder bootargs parameters to make the BockW board bootargs match other boards from Renesas. No need to be special. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7778-bockw.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/r8a7778-bockw.dts index cecb22924ec4..0b49956069fc 100644 --- a/arch/arm/boot/dts/r8a7778-bockw.dts +++ b/arch/arm/boot/dts/r8a7778-bockw.dts @@ -25,7 +25,7 @@ }; chosen { - bootargs = "ignore_loglevel ip=dhcp root=/dev/nfs rw"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; stdout-path = "serial0:115200n8"; }; -- cgit From ee8b7420feaecffa56bf2784fa4b6a6038b390f2 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 18 Apr 2019 00:12:23 +0900 Subject: ARM: dts: marzen: Add rw to bootargs and use ip=dhcp Add rw as bootargs parameter and change from ip=on to ip=dhcp to make the Marzen board bootargs match other boards from Renesas. No need to be special. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7779-marzen.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts index abc14e7a4c93..d4bee1ec9044 100644 --- a/arch/arm/boot/dts/r8a7779-marzen.dts +++ b/arch/arm/boot/dts/r8a7779-marzen.dts @@ -21,7 +21,7 @@ }; chosen { - bootargs = "ignore_loglevel root=/dev/nfs ip=on"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; stdout-path = "serial0:115200n8"; }; -- cgit From 0750e8344eb7c48f82a54920172a5d0f78eb223b Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 18 Apr 2019 00:12:32 +0900 Subject: ARM: dts: ape6evm: Reorder bootargs Reorder bootargs parameters to make the APE6EVM board bootargs match other boards from Renesas. No need to be special. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a73a4-ape6evm.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts index b1e0d556be0a..f70f4a3e5c43 100644 --- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts +++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts @@ -19,7 +19,7 @@ }; chosen { - bootargs = "ignore_loglevel root=/dev/nfs ip=dhcp rw"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; stdout-path = "serial0:115200n8"; }; -- cgit From 61313fb2cca3214ecd93533c7a327ac12b432768 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 12 Apr 2019 15:02:20 +0200 Subject: ARM: dts: ux500: Add Mali-400 This adds the Mali-400 block, also known as SGA500 or the Smart Graphics Adapter, to the DBx500 DTS file. All resources and bindings are already in place so this just works. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index e6ed7c0354a2..43d11346308e 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -1196,6 +1196,30 @@ status = "disabled"; }; + gpu@a0300000 { + /* + * This block is referred to as "Smart Graphics Adapter SGA500" + * in documentation but is in practice a pretty straight-forward + * MALI-400 GPU block. + */ + compatible = "stericsson,db8500-mali", "arm,mali-400"; + reg = <0xa0300000 0x10000>; + interrupts = , + , + , + , + ; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "combined"; + clocks = <&prcmu_clk PRCMU_ACLK>, <&prcmu_clk PRCMU_SGACLK>; + clock-names = "bus", "core"; + mali-supply = <&db8500_sga_reg>; + power-domains = <&pm_domains DOMAIN_VAPE>; + }; + mcde@a0350000 { compatible = "stericsson,mcde"; reg = <0xa0350000 0x1000>, /* MCDE */ -- cgit From f4bdfcc29a8bf96fc385a8221348781dd5594128 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 8 Oct 2018 13:27:55 +0200 Subject: ARM: dts: Ux500: Add MCDE and Samsung display This adds and updates the device tree nodes for the MCDE display controller and connects the Samsung display to the TVK1281618 user interface board (UIB) so we get nicely working graphics on this reference design. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 50 +++++++++++++++++++++++------- arch/arm/boot/dts/ste-href-stuib.dtsi | 13 ++++++++ arch/arm/boot/dts/ste-href-tvk1281618.dtsi | 13 ++++++++ 3 files changed, 65 insertions(+), 11 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 43d11346308e..81fabf031eff 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -1221,20 +1221,48 @@ }; mcde@a0350000 { - compatible = "stericsson,mcde"; - reg = <0xa0350000 0x1000>, /* MCDE */ - <0xa0351000 0x1000>, /* DSI link 1 */ - <0xa0352000 0x1000>, /* DSI link 2 */ - <0xa0353000 0x1000>; /* DSI link 3 */ + compatible = "ste,mcde"; + reg = <0xa0350000 0x1000>; interrupts = ; + epod-supply = <&db8500_b2r2_mcde_reg>; + vana-supply = <&ab8500_ldo_ana_reg>; clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */ <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */ - <&prcmu_clk PRCMU_PLLDSI>, /* HDMI clock */ - <&prcmu_clk PRCMU_DSI0CLK>, /* DSI 0 */ - <&prcmu_clk PRCMU_DSI1CLK>, /* DSI 1 */ - <&prcmu_clk PRCMU_DSI0ESCCLK>, /* TVout clock 0 */ - <&prcmu_clk PRCMU_DSI1ESCCLK>, /* TVout clock 1 */ - <&prcmu_clk PRCMU_DSI2ESCCLK>; /* TVout clock 2 */ + <&prcmu_clk PRCMU_PLLDSI>; /* HDMI clock */ + clock-names = "mcde", "lcd", "hdmi"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + dsi0: dsi@a0351000 { + compatible = "ste,mcde-dsi"; + reg = <0xa0351000 0x1000>; + vana-supply = <&ab8500_ldo_ana_reg>; + clocks = <&prcmu_clk PRCMU_DSI0CLK>, <&prcmu_clk PRCMU_DSI0ESCCLK>; + clock-names = "hs", "lp"; + #address-cells = <1>; + #size-cells = <0>; + }; + dsi1: dsi@a0352000 { + compatible = "ste,mcde-dsi"; + reg = <0xa0352000 0x1000>; + vana-supply = <&ab8500_ldo_ana_reg>; + clocks = <&prcmu_clk PRCMU_DSI1CLK>, <&prcmu_clk PRCMU_DSI1ESCCLK>; + clock-names = "hs", "lp"; + #address-cells = <1>; + #size-cells = <0>; + }; + dsi2: dsi@a0353000 { + compatible = "ste,mcde-dsi"; + reg = <0xa0353000 0x1000>; + vana-supply = <&ab8500_ldo_ana_reg>; + /* This DSI port only has the Low Power / Energy Save clock */ + clocks = <&prcmu_clk PRCMU_DSI2ESCCLK>; + clock-names = "lp"; + #address-cells = <1>; + #size-cells = <0>; + }; }; cryp@a03cb000 { diff --git a/arch/arm/boot/dts/ste-href-stuib.dtsi b/arch/arm/boot/dts/ste-href-stuib.dtsi index 35e944d8b5c4..eeaea21f5eca 100644 --- a/arch/arm/boot/dts/ste-href-stuib.dtsi +++ b/arch/arm/boot/dts/ste-href-stuib.dtsi @@ -190,5 +190,18 @@ }; }; }; + + mcde@a0350000 { + status = "okay"; + + dsi@a0351000 { + panel { + compatible = "samsung,s6d16d0"; + reg = <0>; + vdd1-supply = <&ab8500_ldo_aux1_reg>; + reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi index 0e7d77d719d7..76868444caa4 100644 --- a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi +++ b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi @@ -274,5 +274,18 @@ }; }; }; + + mcde@a0350000 { + status = "okay"; + + dsi@a0351000 { + panel { + compatible = "samsung,s6d16d0"; + reg = <0>; + vdd1-supply = <&ab8500_ldo_aux1_reg>; + reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + }; + }; + }; }; }; -- cgit From 1078946b4b2e44ffe924b0261afddbb38ff7d2c2 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Fri, 12 Apr 2019 01:30:42 +0300 Subject: ARM: tegra: Add ACTMON support on Tegra30 Add support for ACTMON on Tegra30. This is used to monitor activity from different components. Based on the collected statistics, the rate at which the external memory needs to be clocked can be derived. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index d2b553f76719..e074258d4518 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -370,6 +370,17 @@ reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */ }; + actmon@6000c800 { + compatible = "nvidia,tegra30-actmon"; + reg = <0x6000c800 0x400>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_ACTMON>, + <&tegra_car TEGRA30_CLK_EMC>; + clock-names = "actmon", "emc"; + resets = <&tegra_car TEGRA30_CLK_ACTMON>; + reset-names = "actmon"; + }; + gpio: gpio@6000d000 { compatible = "nvidia,tegra30-gpio"; reg = <0x6000d000 0x1000>; -- cgit From 6cb6cfd61ec55690497115b9c08d30ff3c40e74a Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Tue, 16 Apr 2019 14:40:23 +0800 Subject: ARM: dtsi: axp81x: add USB power supply node The AXP813/818 has a VBUS power input. Add a device node for it, now that we support it. Signed-off-by: Quentin Schulz [wens@csie.org: Add commit message] Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/axp81x.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/axp81x.dtsi b/arch/arm/boot/dts/axp81x.dtsi index bd83962d3627..1dfeeceabf4c 100644 --- a/arch/arm/boot/dts/axp81x.dtsi +++ b/arch/arm/boot/dts/axp81x.dtsi @@ -171,4 +171,8 @@ status = "disabled"; }; }; + + usb_power_supply: usb-power-supply { + compatible = "x-powers,axp813-usb-power-supply"; + }; }; -- cgit From 6e0c67e34ffced703abb573d6266104b08bc95d4 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 16 Apr 2019 14:40:24 +0800 Subject: ARM: dts: sun8i: a83t: Enable USB OTG controller on some boards The Bananapi M3 and Cubietruck Plus both have USB OTG ports wired to the SoC and PMIC in the same way, with the N_VBUSEN pin on the PMIC controlling VBUS output, the PMIC's VBUS input for sensing VBUS, and PH11 on the SoC for sensing the ID pin. Enable OTG on both boards. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 12 ++++++++++++ arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts | 12 ++++++++++++ 2 files changed, 24 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts index 838be7b3715f..9d34eabba121 100644 --- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts +++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts @@ -389,7 +389,19 @@ }; }; +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + &usbphy { + usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_drivevbus>; usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts index fcbec3d7ccd7..ea299d3d84d0 100644 --- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts +++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts @@ -420,7 +420,19 @@ }; }; +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + &usbphy { + usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_drivevbus>; usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; -- cgit From 37917ce5b4ee51e3164738cb653266f1a7d53120 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Fri, 19 Apr 2019 23:54:43 +0300 Subject: ARM: dts: lpc32xx: change hexadecimal values to lower case This is a non-functional change, all inconsistent hexadecimal values found in the file are now fixed. Taking a chance to interfere into some non-functional change I add my copyright notice for work done during the last few years. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc32xx.dtsi | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index 20b38f4ade37..5eb223dffbe7 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -1,6 +1,7 @@ /* * NXP LPC32xx SoC * + * Copyright (C) 2015-2019 Vladimir Zapolskiy * Copyright 2012 Roland Stigge * * The code contained herein is licensed under the GNU General Public @@ -232,7 +233,7 @@ i2s1: i2s@2009c000 { compatible = "nxp,lpc3220-i2s"; - reg = <0x2009C000 0x1000>; + reg = <0x2009c000 0x1000>; }; /* UART5 first since it is the default console, ttyS0 */ @@ -275,7 +276,7 @@ i2c1: i2c@400a0000 { compatible = "nxp,pnx-i2c"; - reg = <0x400A0000 0x100>; + reg = <0x400a0000 0x100>; interrupt-parent = <&sic1>; interrupts = <19 IRQ_TYPE_LEVEL_LOW>; #address-cells = <1>; @@ -286,7 +287,7 @@ i2c2: i2c@400a8000 { compatible = "nxp,pnx-i2c"; - reg = <0x400A8000 0x100>; + reg = <0x400a8000 0x100>; interrupt-parent = <&sic1>; interrupts = <18 IRQ_TYPE_LEVEL_LOW>; #address-cells = <1>; @@ -297,7 +298,7 @@ mpwm: mpwm@400e8000 { compatible = "nxp,lpc3220-motor-pwm"; - reg = <0x400E8000 0x78>; + reg = <0x400e8000 0x78>; status = "disabled"; #pwm-cells = <2>; }; @@ -396,7 +397,7 @@ timer4: timer@4002c000 { compatible = "nxp,lpc3220-timer"; - reg = <0x4002C000 0x1000>; + reg = <0x4002c000 0x1000>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; clocks = <&clk LPC32XX_CLK_TIMER4>; clock-names = "timerclk"; @@ -414,7 +415,7 @@ watchdog: watchdog@4003c000 { compatible = "nxp,pnx4008-wdt"; - reg = <0x4003C000 0x1000>; + reg = <0x4003c000 0x1000>; clocks = <&clk LPC32XX_CLK_WDOG>; }; @@ -453,7 +454,7 @@ timer1: timer@4004c000 { compatible = "nxp,lpc3220-timer"; - reg = <0x4004C000 0x1000>; + reg = <0x4004c000 0x1000>; interrupts = <17 IRQ_TYPE_LEVEL_LOW>; clocks = <&clk LPC32XX_CLK_TIMER1>; clock-names = "timerclk"; @@ -479,7 +480,7 @@ pwm1: pwm@4005c000 { compatible = "nxp,lpc3220-pwm"; - reg = <0x4005C000 0x4>; + reg = <0x4005c000 0x4>; clocks = <&clk LPC32XX_CLK_PWM1>; assigned-clocks = <&clk LPC32XX_CLK_PWM1>; assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>; @@ -488,7 +489,7 @@ pwm2: pwm@4005c004 { compatible = "nxp,lpc3220-pwm"; - reg = <0x4005C004 0x4>; + reg = <0x4005c004 0x4>; clocks = <&clk LPC32XX_CLK_PWM2>; assigned-clocks = <&clk LPC32XX_CLK_PWM2>; assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>; -- cgit From 903fa2ab79d832ef3dcf7424f0227799cbeda3da Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Fri, 19 Apr 2019 23:54:44 +0300 Subject: ARM: dts: lpc32xx: disable I2S controllers by default The I2S controllers found on NXP LPC32xx SoCs are not yet in use by any boards supported in upstream, disable the controllers by default. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc32xx.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index 5eb223dffbe7..aa1d9dd248fd 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -219,6 +219,7 @@ i2s0: i2s@20094000 { compatible = "nxp,lpc3220-i2s"; reg = <0x20094000 0x1000>; + status = "disabled"; }; sd: sd@20098000 { @@ -234,6 +235,7 @@ i2s1: i2s@2009c000 { compatible = "nxp,lpc3220-i2s"; reg = <0x2009c000 0x1000>; + status = "disabled"; }; /* UART5 first since it is the default console, ttyS0 */ -- cgit From 4c546175dbe1b9bde68f547666a2c1f75d65b817 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Fri, 19 Apr 2019 23:54:45 +0300 Subject: ARM: dts: lpc32xx: disable MAC controller by default NXP LPC3220 and LPC3230 SoCs do NOT contain a MAC controller, so, since for now there is just one dtsi file for all variants of NXP LPC32xx SoCs, it is reasonable to disable the controller by default and enable it in device tree files of particular boards. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc3250-ea3250.dts | 1 + arch/arm/boot/dts/lpc3250-phy3250.dts | 1 + arch/arm/boot/dts/lpc32xx.dtsi | 1 + 3 files changed, 3 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/lpc3250-ea3250.dts b/arch/arm/boot/dts/lpc3250-ea3250.dts index f46a11827ef6..4adf4c96f798 100644 --- a/arch/arm/boot/dts/lpc3250-ea3250.dts +++ b/arch/arm/boot/dts/lpc3250-ea3250.dts @@ -201,6 +201,7 @@ &mac { phy-mode = "rmii"; use-iram; + status = "okay"; }; /* Here, choose exactly one from: ohci, usbd */ diff --git a/arch/arm/boot/dts/lpc3250-phy3250.dts b/arch/arm/boot/dts/lpc3250-phy3250.dts index ebd19258e22b..b99726d278f6 100644 --- a/arch/arm/boot/dts/lpc3250-phy3250.dts +++ b/arch/arm/boot/dts/lpc3250-phy3250.dts @@ -134,6 +134,7 @@ &mac { phy-mode = "rmii"; use-iram; + status = "okay"; }; /* Here, choose exactly one from: ohci, usbd */ diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index aa1d9dd248fd..a0fedab579b4 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -153,6 +153,7 @@ reg = <0x31060000 0x1000>; interrupts = <29 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_MAC>; + status = "disabled"; }; emc: memory-controller@31080000 { -- cgit From cea862386791e281c4e9ab07dd118321f6655435 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Fri, 19 Apr 2019 23:54:46 +0300 Subject: ARM: dts: lpc32xx: add address and size cell values to SPI controller nodes All 4 SPI controllers on NXP LPC32xx SoC support SPI slaves discerning them by one cell address value, set it as default to avoid duplication in board device tree files. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc3250-phy3250.dts | 2 -- arch/arm/boot/dts/lpc32xx.dtsi | 8 ++++++++ 2 files changed, 8 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/lpc3250-phy3250.dts b/arch/arm/boot/dts/lpc3250-phy3250.dts index b99726d278f6..1b15f798794b 100644 --- a/arch/arm/boot/dts/lpc3250-phy3250.dts +++ b/arch/arm/boot/dts/lpc3250-phy3250.dts @@ -202,8 +202,6 @@ }; &ssp0 { - #address-cells = <1>; - #size-cells = <0>; num-cs = <1>; cs-gpios = <&gpio 3 5 0>; status = "okay"; diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index a0fedab579b4..bc32450de423 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -187,6 +187,8 @@ interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_SSP0>; clock-names = "apb_pclk"; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -194,6 +196,8 @@ compatible = "nxp,lpc3220-spi"; reg = <0x20088000 0x1000>; clocks = <&clk LPC32XX_CLK_SPI1>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -207,6 +211,8 @@ interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_SSP1>; clock-names = "apb_pclk"; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -214,6 +220,8 @@ compatible = "nxp,lpc3220-spi"; reg = <0x20090000 0x1000>; clocks = <&clk LPC32XX_CLK_SPI2>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; -- cgit From d5a71e4646a741f22863b12d0037e15b5844af90 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Fri, 19 Apr 2019 23:54:47 +0300 Subject: ARM: dts: lpc32xx: use SPDX license identifier Replace GPLv2+ header with the SPDX identifier. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc32xx.dtsi | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index bc32450de423..7b7ec7b1217b 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -1,15 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * NXP LPC32xx SoC * * Copyright (C) 2015-2019 Vladimir Zapolskiy * Copyright 2012 Roland Stigge - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html */ #include -- cgit From 6143613a84ada5de602a717f0a41b0ae6c88755f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 12 Apr 2019 12:49:52 +0200 Subject: ARM: dts: imx53: Rename M53 SoM touchscreen node Rename the touchscreen node to match contemporary design. Signed-off-by: Marek Vasut Cc: Shawn Guo Cc: Fabio Estevam Cc: NXP Linux Team To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53-m53.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx53-m53.dtsi b/arch/arm/boot/dts/imx53-m53.dtsi index db2e5bce9b6a..d1770e1d5e50 100644 --- a/arch/arm/boot/dts/imx53-m53.dtsi +++ b/arch/arm/boot/dts/imx53-m53.dtsi @@ -52,7 +52,7 @@ clock-frequency = <400000>; status = "okay"; - stmpe610@41 { + touchscreen@41 { compatible = "st,stmpe610"; reg = <0x41>; id = <0>; -- cgit From 716be61d186939eebacdbccfc14e9ea3bd70f8c6 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 12 Apr 2019 12:49:53 +0200 Subject: ARM: dts: imx53: Add Menlosystems M53 board Add device tree for the Menlosystems board based on i.MX53 M53 SoM. Signed-off-by: Marek Vasut Cc: Shawn Guo Cc: Fabio Estevam Cc: NXP Linux Team To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx53-m53menlo.dts | 311 +++++++++++++++++++++++++++++++++++ 2 files changed, 312 insertions(+) create mode 100644 arch/arm/boot/dts/imx53-m53menlo.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7776f97c4497..87dc9b7fef9b 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -381,6 +381,7 @@ dtb-$(CONFIG_SOC_IMX53) += \ imx53-kp-ddc.dtb \ imx53-kp-hsc.dtb \ imx53-m53evk.dtb \ + imx53-m53menlo.dtb \ imx53-mba53.dtb \ imx53-ppd.dtb \ imx53-qsb.dtb \ diff --git a/arch/arm/boot/dts/imx53-m53menlo.dts b/arch/arm/boot/dts/imx53-m53menlo.dts new file mode 100644 index 000000000000..f0a3fde0739c --- /dev/null +++ b/arch/arm/boot/dts/imx53-m53menlo.dts @@ -0,0 +1,311 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Marek Vasut + */ + +/dts-v1/; +#include "imx53-m53.dtsi" + +/ { + model = "MENLO M53 EMBEDDED DEVICE"; + compatible = "menlo,m53menlo", "fsl,imx53"; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + + user1 { + label = "TestLed601"; + gpios = <&gpio6 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + }; + + user2 { + label = "TestLed602"; + gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + eth { + label = "EthLedYe"; + gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + }; + + panel { + compatible = "edt,etm070080dh6"; + enable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + reg_usbh1_vbus: regulator-usbh1-vbus { + compatible = "regulator-fixed"; + regulator-name = "vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX5_CLK_CKO1_SEL>, + <&clks IMX5_CLK_CKO1_PODF>, + <&clks IMX5_CLK_CKO1>; + assigned-clock-parents = <&clks IMX5_CLK_AHB>; + assigned-clock-rates = <133333334>, <33333334>, <33333334>; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rmii"; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_edt_ft5x06>; + interrupt-parent = <&gpio6>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; + wake-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + + dac@60 { + compatible = "microchip,mcp4725"; + reg = <0x60>; + }; +}; + +&i2c2 { + touchscreen@41 { + status = "disabled"; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx53-m53evk { + hoggrp { + fsl,pins = < + MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4 + MX53_PAD_EIM_EB3__GPIO2_31 0x1d5 + MX53_PAD_PATA_DA_0__GPIO7_6 0x1d5 + MX53_PAD_GPIO_19__CCM_CLKO 0x1d5 + MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK 0x1d5 + MX53_PAD_CSI0_DAT4__GPIO5_22 0x1d5 + MX53_PAD_CSI0_DAT5__GPIO5_23 0x1d5 + MX53_PAD_CSI0_DAT6__GPIO5_24 0x1d5 + MX53_PAD_CSI0_DAT7__GPIO5_25 0x1d5 + MX53_PAD_CSI0_DAT8__GPIO5_26 0x1d5 + MX53_PAD_CSI0_DAT9__GPIO5_27 0x1d5 + MX53_PAD_CSI0_DAT10__GPIO5_28 0x1d5 + MX53_PAD_CSI0_DAT11__GPIO5_29 0x1d5 + MX53_PAD_CSI0_DAT14__GPIO6_0 0x1d5 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX53_PAD_CSI0_DAT15__GPIO6_1 0x1d5 + MX53_PAD_CSI0_DAT16__GPIO6_2 0x1d5 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX53_PAD_GPIO_7__CAN1_TXCAN 0x1c4 + MX53_PAD_GPIO_8__CAN1_RXCAN 0x1c4 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX53_PAD_KEY_COL4__CAN2_TXCAN 0x1c4 + MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x1c4 + >; + }; + + pinctrl_display_gpio: display-gpiogrp { + fsl,pins = < + MX53_PAD_CSI0_DAT12__GPIO5_30 0x1d5 /* Reset */ + MX53_PAD_CSI0_DAT13__GPIO5_31 0x1d5 /* Interrupt */ + >; + }; + + pinctrl_edt_ft5x06: edt-ft5x06grp { + fsl,pins = < + MX53_PAD_PATA_DATA9__GPIO2_9 0x1d5 /* Reset */ + MX53_PAD_CSI0_DAT19__GPIO6_5 0x1d5 /* Interrupt */ + MX53_PAD_PATA_DATA10__GPIO2_10 0x1d5 /* Wake */ + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 + MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 + MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX53_PAD_FEC_MDC__FEC_MDC 0x4 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4 + MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX53_PAD_GPIO_6__I2C3_SDA 0x400001e4 + MX53_PAD_GPIO_5__I2C3_SCL 0x400001e4 + >; + }; + + pinctrl_lvds0: lvds0grp { + /* LVDS pins only have pin mux configuration */ + fsl,pins = < + MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 + MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 + MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 + MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 + MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 + MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 + MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 + >; + }; + + pinctrl_usb: usbgrp { + fsl,pins = < + MX53_PAD_GPIO_2__GPIO1_2 0x1d5 + MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x1d5 + >; + }; + }; +}; + +&ldb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0>; + status = "okay"; + + lvds0: lvds-channel@0 { + reg = <0>; + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + port@2 { + reg = <2>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb>; + vbus-supply = <®_usbh1_vbus>; + phy_type = "utmi"; + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbotg { + dr_mode = "peripheral"; + status = "okay"; +}; -- cgit From 71f2b9957d983659586308c9f64acc4dc3d22aa2 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Wed, 6 Mar 2019 09:19:22 +1300 Subject: ARM: dts: armada-38x: add interrupts for watchdog The first interrupt is for the regular watchdog timeout. Normally the RSTOUT line will trigger a reset before this interrupt fires but on systems with a non-standard reset it may still trigger. The second interrupt is for a timer1 which is used as a pre-timeout for the watchdog. Signed-off-by: Chris Packham Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-38x.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 96c18703e471..3f4bb44d85f0 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -415,6 +415,8 @@ reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>; clocks = <&coreclk 2>, <&refclk>; clock-names = "nbclk", "fixed"; + interrupts-extended = <&gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; }; cpurst: cpurst@20800 { -- cgit From 5ea0c200bd30a96732fb50a5d7428d0d75b39d28 Mon Sep 17 00:00:00 2001 From: Bruno Thomsen Date: Tue, 16 Apr 2019 11:08:05 +0200 Subject: ARM: dts: bugfix tqma7 soft reset issue Running reboot command on the TQMa7 board would just hang infinite at the end of the system shutdown process. Handling of i.MX7 errata e10574: Watchdog: A watchdog timeout or software trigger will not reset the SOC. Moved pinctrl from common mba7 to common tqma7 dtsi as it improves readability of errata handling. Most integrators of this SoM will likely use the development board as inspiration for handling this SoC issue. Signed-off-by: Bruno Thomsen Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-mba7.dtsi | 11 ----------- arch/arm/boot/dts/imx7-tqma7.dtsi | 17 +++++++++++++++++ 2 files changed, 17 insertions(+), 11 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi index 578341b6848b..50abf18ad30b 100644 --- a/arch/arm/boot/dts/imx7-mba7.dtsi +++ b/arch/arm/boot/dts/imx7-mba7.dtsi @@ -472,12 +472,6 @@ MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x59 >; }; - - pinctrl_wdog1: wdog1grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30 - >; - }; }; &pwm1 { @@ -554,8 +548,3 @@ no-1-8-v; status = "okay"; }; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog1>; -}; diff --git a/arch/arm/boot/dts/imx7-tqma7.dtsi b/arch/arm/boot/dts/imx7-tqma7.dtsi index 85fe461e5e67..9aaed85138cb 100644 --- a/arch/arm/boot/dts/imx7-tqma7.dtsi +++ b/arch/arm/boot/dts/imx7-tqma7.dtsi @@ -209,6 +209,14 @@ }; }; +&iomuxc_lpsr { + pinctrl_wdog1: wdog1grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30 + >; + }; +}; + &sdma { status = "okay"; }; @@ -228,5 +236,14 @@ }; &wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog1>; + /* + * Errata e10574: + * WDOG reset needs to run with WDOG_RESET_B signal enabled. + * X1-51 (WDOG1#) signal needs carrier board handling to reset + * TQMa7 on X1-22 (RESET_IN#). + */ + fsl,ext-reset-output; status = "okay"; }; -- cgit From 69ab5392f5177aad19e006c5ba8e78bf059fee68 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Sun, 14 Apr 2019 11:34:03 -0700 Subject: ARM: dts: Add support for ZII i.MX7 RPU2 board Add support for ZII's i.MX7 based Remote Peripheral Unit 2 (RPU2) board. Signed-off-by: Andrey Smirnov Reviewed-by: Fabio Estevam Cc: Shawn Guo Cc: Chris Healy Cc: Andrew Lunn Cc: Fabio Estevam Cc: Rob Herring Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx7d-zii-rpu2.dts | 941 +++++++++++++++++++++++++++++++++++ 2 files changed, 942 insertions(+) create mode 100644 arch/arm/boot/dts/imx7d-zii-rpu2.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 87dc9b7fef9b..55f3c20d103d 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -590,6 +590,7 @@ dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-sdb.dtb \ imx7d-sdb-reva.dtb \ imx7d-sdb-sht11.dtb \ + imx7d-zii-rpu2.dtb \ imx7s-colibri-eval-v3.dtb \ imx7s-mba7.dtb \ imx7s-warp.dtb diff --git a/arch/arm/boot/dts/imx7d-zii-rpu2.dts b/arch/arm/boot/dts/imx7d-zii-rpu2.dts new file mode 100644 index 000000000000..3e467a94e8a6 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-zii-rpu2.dts @@ -0,0 +1,941 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device tree file for ZII's RPU2 board + * + * RPU - Remote Peripheral Unit + * + * Copyright (C) 2019 Zodiac Inflight Innovations + */ + +/dts-v1/; +#include +#include "imx7d.dtsi" + +/ { + model = "ZII RPU2 Board"; + compatible = "zii,imx7d-rpu2", "fsl,imx7d"; + + chosen { + stdout-path = &uart1; + }; + + cs2000_ref: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + cs2000_in_dummy: dummy-oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pinctrl_leds_debug>; + pinctrl-names = "default"; + + debug { + label = "zii:green:debug1"; + gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>, + <&adc2 1>; + }; + + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1_stby>; + regulator-name = "can1-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2_stby>; + regulator-name = "can2-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator-vref-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "GEN_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5p0v_main: regulator-5p0v-main { + compatible = "regulator-fixed"; + regulator-name = "5V_MAIN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + sound1 { + compatible = "simple-audio-card"; + simple-audio-card,name = "Audio Output 1"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound1_codec>; + simple-audio-card,frame-master = <&sound1_codec>; + simple-audio-card,widgets = + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HPLEFT", + "Headphone Jack", "HPRIGHT", + "LEFTIN", "HPL", + "RIGHTIN", "HPR"; + simple-audio-card,aux-devs = <&hpa1>; + + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + + sound1_codec: simple-audio-card,codec { + sound-dai = <&codec1>; + clocks = <&cs2000>; + }; + }; + + sound2 { + compatible = "simple-audio-card"; + simple-audio-card,name = "Audio Output 2"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound2_codec>; + simple-audio-card,frame-master = <&sound2_codec>; + simple-audio-card,widgets = + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HPLEFT", + "Headphone Jack", "HPRIGHT", + "LEFTIN", "HPL", + "RIGHTIN", "HPR"; + simple-audio-card,aux-devs = <&hpa2>; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + + sound2_codec: simple-audio-card,codec { + sound-dai = <&codec2>; + clocks = <&cs2000>; + }; + }; + + sound3 { + compatible = "simple-audio-card"; + simple-audio-card,name = "Audio Output 3"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound3_codec>; + simple-audio-card,frame-master = <&sound3_codec>; + simple-audio-card,widgets = + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HPLEFT", + "Headphone Jack", "HPRIGHT", + "LEFTIN", "HPL", + "RIGHTIN", "HPR"; + simple-audio-card,aux-devs = <&hpa3>; + + simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + + sound3_codec: simple-audio-card,codec { + sound-dai = <&codec3>; + clocks = <&cs2000>; + }; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&adc2 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&cpu0 { + arm-supply = <&sw1a_reg>; +}; + +&clks { + assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <884736000>; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii"; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + + mdio1: mdio { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + switch: switch@0 { + compatible = "marvell,mv88e6085"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_switch>; + reg = <0>; + eeprom-length = <512>; + interrupt-parent = <&gpio1>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "eth_cu_1000_1"; + }; + + port@1 { + reg = <1>; + label = "eth_cu_1000_2"; + }; + + port@2 { + reg = <2>; + label = "pic"; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&fec1>; + phy-mode = "rgmii-id"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@6 { + reg = <6>; + label = "gigabit_proc"; + ethernet = <&fec2>; + phy-mode = "rgmii-id"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, + <&clks IMX7D_ENET2_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii"; + fsl,magic-packet; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_stby>; + status = "okay"; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>; + + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", + "usb_1_en_b", + "usb_2_en_b", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", ""; +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio2>; + + gpio-line-names = "12v_out_en_1", + "12v_out_en_2", + "12v_out_en_3", + "28v_out_en_5", + "28v_out_en_1", + "28v_out_en_2", + "28v_out_en_3", + "28v_out_en_4", + "", "", + "usb_3_en_b", + "usb_4_en_b", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", ""; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pmic@8 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + cs2000: clkgen@4e { + compatible = "cirrus,cs2000-cp"; + reg = <0x4e>; + #clock-cells = <0>; + clock-names = "clk_in", "ref_clk"; + clocks = <&cs2000_in_dummy>, <&cs2000_ref>; + assigned-clocks = <&cs2000>; + assigned-clock-rates = <24000000>; + }; + + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + }; + + eeprom@52 { + compatible = "atmel,24c04"; + reg = <0x52>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + codec2: codec@18 { + compatible = "ti,tlv320dac3100"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_codec2>; + reg = <0x18>; + #sound-dai-cells = <0>; + HPVDD-supply = <®_3p3v>; + SPRVDD-supply = <®_3p3v>; + SPLVDD-supply = <®_3p3v>; + AVDD-supply = <®_3p3v>; + IOVDD-supply = <®_3p3v>; + DVDD-supply = <&vgen4_reg>; + gpio-reset = <&gpio1 6 GPIO_ACTIVE_LOW>; + }; + + hpa2: amp@60 { + compatible = "ti,tpa6130a2"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpa2>; + reg = <0x60>; + power-gpio = <&gpio3 27 GPIO_ACTIVE_HIGH>; + Vdd-supply = <®_5p0v_main>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + codec3: codec@18 { + compatible = "ti,tlv320dac3100"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_codec3>; + reg = <0x18>; + #sound-dai-cells = <0>; + HPVDD-supply = <®_3p3v>; + SPRVDD-supply = <®_3p3v>; + SPLVDD-supply = <®_3p3v>; + AVDD-supply = <®_3p3v>; + IOVDD-supply = <®_3p3v>; + DVDD-supply = <&vgen4_reg>; + gpio-reset = <&gpio1 7 GPIO_ACTIVE_LOW>; + }; + + hpa3: amp@60 { + compatible = "ti,tpa6130a2"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpa3>; + reg = <0x60>; + power-gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>; + Vdd-supply = <®_5p0v_main>; + }; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + codec1: codec@18 { + compatible = "ti,tlv320dac3100"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_codec1>; + reg = <0x18>; + #sound-dai-cells = <0>; + HPVDD-supply = <®_3p3v>; + SPRVDD-supply = <®_3p3v>; + SPLVDD-supply = <®_3p3v>; + AVDD-supply = <®_3p3v>; + IOVDD-supply = <®_3p3v>; + DVDD-supply = <&vgen4_reg>; + gpio-reset = <&gpio1 5 GPIO_ACTIVE_LOW>; + }; + + hpa1: amp@60 { + compatible = "ti,tpa6130a2"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpa1>; + reg = <0x60>; + power-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>; + Vdd-supply = <®_5p0v_main>; + }; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, + <&clks IMX7D_SAI1_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <36864000>; + status = "okay"; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clks IMX7D_SAI2_ROOT_SRC>, + <&clks IMX7D_SAI2_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <36864000>; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>, + <&clks IMX7D_SAI3_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <36864000>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; + + rave-sp { + compatible = "zii,rave-sp-rdu2"; + current-speed = <1000000>; + #address-cells = <1>; + #size-cells = <1>; + + watchdog { + compatible = "zii,rave-sp-watchdog"; + }; + + eeprom@a3 { + compatible = "zii,rave-sp-eeprom"; + reg = <0xa3 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + zii,eeprom-name = "main-eeprom"; + }; + }; +}; + +&usbotg1 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <4>; + no-1-8-v; + no-sdio; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + no-1-8-v; + non-removable; + no-sdio; + no-sd; + keep-power-in-suspend; + status = "okay"; +}; + +&wdog1 { + status = "disabled"; +}; + +&snvs_rtc { + status = "disabled"; +}; + +&snvs_pwrkey { + status = "disabled"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x2 + MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x2 + MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x2 + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x59 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3 + MX7D_PAD_SD2_WP__ENET1_MDC 0x3 + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 + MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT 0x1 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x59 + MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x59 + >; + }; + + pinctrl_flexcan1_stby: flexcan1stbygrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO08__GPIO1_IO8 0x59 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59 + MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59 + >; + }; + + pinctrl_flexcan2_stby: flexcan2stbygrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 + >; + }; + + pinctrl_gpio1: gpio1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x00 + MX7D_PAD_GPIO1_IO11__GPIO1_IO11 0x00 + >; + }; + + pinctrl_gpio2: gpio2grp { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x00 + MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x00 + MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x00 + MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x03 + MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x03 + MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x03 + MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x03 + MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x03 + MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x00 + MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x00 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x4000007f + MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x4000007f + MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x4000007f + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f + MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x4000007f + MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x4000007f + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f + MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f + >; + }; + + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x4000007f + MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x4000007f + >; + }; + + pinctrl_leds_debug: debuggrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x59 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f + MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f + MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x30 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f + MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f + MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x30 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x1f + MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x1f + MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x30 + >; + }; + + pinctrl_tpa1: tpa6130-1grp { + fsl,pins = < + MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x40000038 + >; + }; + + pinctrl_tpa2: tpa6130-2grp { + fsl,pins = < + MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x40000038 + >; + }; + + pinctrl_tpa3: tpa6130-3grp { + fsl,pins = < + MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x40000038 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79 + MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX7D_PAD_SD2_DATA0__UART4_DCE_RX 0x79 + MX7D_PAD_SD2_DATA1__UART4_DCE_TX 0x79 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x59 + >; + }; +}; + +&iomuxc_lpsr { + pinctrl_codec1: dac1grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x40000038 + >; + }; + + pinctrl_codec2: dac2grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x40000038 + >; + }; + + pinctrl_codec3: dac3grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x40000038 + >; + }; + + pinctrl_switch: switchgrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x08 + >; + }; +}; -- cgit From 1437626ec447400d66738b7af5006df456142f44 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Sun, 14 Apr 2019 11:35:57 -0700 Subject: ARM: dts: vf610-zii-dev: Mark i2c0 SCL as GPIO_OPEN_DRAIN Mark i2c0 SCL as GPIO_OPEN_DRAIN to fix the following warning: gpio-36 (scl): enforced open drain please flag it properly in DT/ACPI DSDT/board file Signed-off-by: Andrey Smirnov Cc: Shawn Guo Cc: Chris Healy Cc: Andrew Lunn Cc: Fabio Estevam Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-zii-dev.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/vf610-zii-dev.dtsi b/arch/arm/boot/dts/vf610-zii-dev.dtsi index 36bbb8a9f4d8..0507e6dcbb21 100644 --- a/arch/arm/boot/dts/vf610-zii-dev.dtsi +++ b/arch/arm/boot/dts/vf610-zii-dev.dtsi @@ -138,7 +138,7 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0>; pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; status = "okay"; -- cgit From 2ea5c9b28fab2f34a0ac5d9b3d17216dd35d3162 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Sun, 14 Apr 2019 11:35:58 -0700 Subject: ARM: dts: vf610-zii-dev-rev-b: Specify CS as GPIO_ACTIVE_LOW in spi0 Specify CS as GPIO_ACTIVE_LOW in spi0 to fix the following warning: m25p128@0 enforce active low on chipselect handle Signed-off-by: Andrey Smirnov Cc: Shawn Guo Cc: Chris Healy Cc: Andrew Lunn Cc: Fabio Estevam Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-zii-dev-rev-b.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts index 8b0baf6a4098..48086c5e8549 100644 --- a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts +++ b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts @@ -295,7 +295,7 @@ gpio-sck = <&gpio1 12 GPIO_ACTIVE_HIGH>; gpio-mosi = <&gpio1 11 GPIO_ACTIVE_HIGH>; gpio-miso = <&gpio1 10 GPIO_ACTIVE_HIGH>; - cs-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH + cs-gpios = <&gpio1 9 GPIO_ACTIVE_LOW &gpio1 8 GPIO_ACTIVE_HIGH>; num-chipselects = <2>; -- cgit From 4171797ff78fa1f351b890e18411b7959b506149 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Sun, 14 Apr 2019 11:34:01 -0700 Subject: ARM: dts: imx7s: Specify #io-channel-cells in ADC nodes Specify #io-channel-cells in ADC nodes. Needed to be able to reference them by phandle. Signed-off-by: Andrey Smirnov Cc: Shawn Guo Cc: Chris Healy Cc: Andrew Lunn Cc: Fabio Estevam Cc: Rob Herring Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 0b01109ac0a9..106711d2c01b 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -670,6 +670,7 @@ interrupts = ; clocks = <&clks IMX7D_ADC_ROOT_CLK>; clock-names = "adc"; + #io-channel-cells = <1>; status = "disabled"; }; @@ -679,6 +680,7 @@ interrupts = ; clocks = <&clks IMX7D_ADC_ROOT_CLK>; clock-names = "adc"; + #io-channel-cells = <1>; status = "disabled"; }; -- cgit From be00300147ae3c0b2fa4dbc5f00d4332a8d00fac Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 15 Apr 2019 20:05:07 +0200 Subject: ARM: dts: exynos: Move pmu and timer nodes out of soc The ARM PMU and ARM architected timer nodes are part of ARM CPU design therefore they should not be inside the soc node. This also fixes DTC W=1 warnings like: arch/arm/boot/dts/exynos3250.dtsi:106.21-135.5: Warning (simple_bus_reg): /soc/fixed-rate-clocks: missing or empty reg/ranges property arch/arm/boot/dts/exynos3250.dtsi:676.7-680.5: Warning (simple_bus_reg): /soc/pmu: missing or empty reg/ranges property Signed-off-by: Krzysztof Kozlowski Tested-by: Marek Szyprowski --- arch/arm/boot/dts/exynos3250.dtsi | 12 ++++++------ arch/arm/boot/dts/exynos4.dtsi | 12 ++++++------ arch/arm/boot/dts/exynos5250.dtsi | 40 +++++++++++++++++++-------------------- arch/arm/boot/dts/exynos54xx.dtsi | 38 ++++++++++++++++++------------------- 4 files changed, 51 insertions(+), 51 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 5892a9f7622f..af54b306204b 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -97,6 +97,12 @@ }; }; + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + ; + }; + soc: soc { compatible = "simple-bus"; #address-cells = <1>; @@ -673,12 +679,6 @@ status = "disabled"; }; - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - ; - }; - ppmu_dmc0: ppmu_dmc0@106a0000 { compatible = "samsung,exynos-ppmu"; reg = <0x106a0000 0x2000>; diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 6085e92ac2d7..1c21627e3c3c 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -51,6 +51,12 @@ serial3 = &serial_3; }; + pmu: pmu { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&combiner>; + interrupts = <2 2>, <3 2>; + }; + soc: soc { compatible = "simple-bus"; #address-cells = <1>; @@ -169,12 +175,6 @@ reg = <0x10440000 0x1000>; }; - pmu: pmu { - compatible = "arm,cortex-a9-pmu"; - interrupt-parent = <&combiner>; - interrupts = <2 2>, <3 2>; - }; - sys_reg: syscon@10010000 { compatible = "samsung,exynos4-sysreg", "syscon"; reg = <0x10010000 0x400>; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 80986b97dfe5..d5e0392b409e 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -157,6 +157,12 @@ }; }; + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupt-parent = <&combiner>; + interrupts = <1 2>, <22 4>; + }; + soc: soc { sysram@2020000 { compatible = "mmio-sram"; @@ -227,20 +233,6 @@ power-domains = <&pd_mau>; }; - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - /* - * Unfortunately we need this since some versions - * of U-Boot on Exynos don't set the CNTFRQ register, - * so we need the value from DT. - */ - clock-frequency = <24000000>; - }; - mct@101c0000 { compatible = "samsung,exynos4210-mct"; reg = <0x101C0000 0x800>; @@ -265,12 +257,6 @@ }; }; - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupt-parent = <&combiner>; - interrupts = <1 2>, <22 4>; - }; - pinctrl_0: pinctrl@11400000 { compatible = "samsung,exynos5250-pinctrl"; reg = <0x11400000 0x1000>; @@ -1097,6 +1083,20 @@ }; }; }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + /* + * Unfortunately we need this since some versions + * of U-Boot on Exynos don't set the CNTFRQ register, + * so we need the value from DT. + */ + clock-frequency = <24000000>; + }; }; &dp { diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi index de26e5ee0d2d..ae866bcc30c4 100644 --- a/arch/arm/boot/dts/exynos54xx.dtsi +++ b/arch/arm/boot/dts/exynos54xx.dtsi @@ -25,27 +25,27 @@ usbdrdphy1 = &usbdrd_phy1; }; - soc: soc { - arm_a7_pmu: arm-a7-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - status = "disabled"; - }; + arm_a7_pmu: arm-a7-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + status = "disabled"; + }; - arm_a15_pmu: arm-a15-pmu { - compatible = "arm,cortex-a15-pmu"; - interrupt-parent = <&combiner>; - interrupts = <1 2>, - <7 0>, - <16 6>, - <19 2>; - status = "disabled"; - }; + arm_a15_pmu: arm-a15-pmu { + compatible = "arm,cortex-a15-pmu"; + interrupt-parent = <&combiner>; + interrupts = <1 2>, + <7 0>, + <16 6>, + <19 2>; + status = "disabled"; + }; + soc: soc { sysram@2020000 { compatible = "mmio-sram"; reg = <0x02020000 0x54000>; -- cgit From 39691e775a52c7f69cf164500bd541f7c88a468f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 15 Apr 2019 20:05:08 +0200 Subject: ARM: dts: exynos: Remove unneeded address/size cells from fixed-clock on Exynos3250 xusbxti fixed-clock should not have address/size cells because it does not have any children. This also fixes DTC W=1 warning: arch/arm/boot/dts/exynos3250.dtsi:112.21-139.5: Warning (simple_bus_reg): /soc/fixed-rate-clocks: missing or empty reg/ranges property Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos3250.dtsi | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index af54b306204b..6e74e6815b01 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -115,8 +115,6 @@ xusbxti: clock@0 { compatible = "fixed-clock"; - #address-cells = <1>; - #size-cells = <0>; reg = <0>; clock-frequency = <0>; #clock-cells = <0>; -- cgit From 1e440c223503c24959fcccb96c2b0e775a6b3bb9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 15 Apr 2019 20:05:09 +0200 Subject: ARM: dts: exynos: Move fixed-clocks out of soc on Exynos3250 The three fixed-clocks (xusbxti, xxti and xtcxo) are inputs to the Exynos3250 therefore they should not be inside the soc node. This also fixes DTC W=1 warning: arch/arm/boot/dts/exynos3250.dtsi:112.21-139.5: Warning (simple_bus_reg): /soc/fixed-rate-clocks: missing or empty reg/ranges property Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos3250.dtsi | 58 +++++++++++++++++++-------------------- 1 file changed, 29 insertions(+), 29 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 6e74e6815b01..8ce3a7786b19 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -97,6 +97,35 @@ }; }; + fixed-rate-clocks { + #address-cells = <1>; + #size-cells = <0>; + + xusbxti: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + clock-frequency = <0>; + #clock-cells = <0>; + clock-output-names = "xusbxti"; + }; + + xxti: clock@1 { + compatible = "fixed-clock"; + reg = <1>; + clock-frequency = <0>; + #clock-cells = <0>; + clock-output-names = "xxti"; + }; + + xtcxo: clock@2 { + compatible = "fixed-clock"; + reg = <2>; + clock-frequency = <0>; + #clock-cells = <0>; + clock-output-names = "xtcxo"; + }; + }; + pmu { compatible = "arm,cortex-a7-pmu"; interrupts = , @@ -109,35 +138,6 @@ #size-cells = <1>; ranges; - fixed-rate-clocks { - #address-cells = <1>; - #size-cells = <0>; - - xusbxti: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - clock-frequency = <0>; - #clock-cells = <0>; - clock-output-names = "xusbxti"; - }; - - xxti: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - clock-frequency = <0>; - #clock-cells = <0>; - clock-output-names = "xxti"; - }; - - xtcxo: clock@2 { - compatible = "fixed-clock"; - reg = <2>; - clock-frequency = <0>; - #clock-cells = <0>; - clock-output-names = "xtcxo"; - }; - }; - sysram@2020000 { compatible = "mmio-sram"; reg = <0x02020000 0x40000>; -- cgit From 0fd5ff9e4cf4469911856d4e48b513e87cd4f279 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 15 Apr 2019 20:05:10 +0200 Subject: ARM: dts: exynos: Properly override node to use MDMA0 on Universal C210 The Universal C210 (Exynos4210) uses the secure interface of MDMA0, instead of regular one - non-secure MDMA1. DTS was overriding MDMA1 node address which caused DTC W=1 warning: arch/arm/boot/dts/exynos4.dtsi:707.25-716.6: Warning (simple_bus_reg): /soc/amba/mdma@12850000: simple-bus unit address format error, expected "12840000" Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4.dtsi | 2 +- arch/arm/boot/dts/exynos4210-universal_c210.dts | 17 ++++++++++++++++- 2 files changed, 17 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 1c21627e3c3c..36ccf227434d 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -675,7 +675,7 @@ status = "disabled"; }; - amba { + amba: amba { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index 07d64a8f82e3..bf092e97e14f 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -177,6 +177,20 @@ }; }; +&amba { + mdma0: mdma@12840000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x12840000 0x1000>; + interrupts = ; + clocks = <&clock CLK_MDMA>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <1>; + power-domains = <&pd_lcd0>; + }; +}; + &camera { status = "okay"; @@ -491,7 +505,8 @@ }; &mdma1 { - reg = <0x12840000 0x1000>; + /* Use the secure mdma0 */ + status = "disabled"; }; &mixer { -- cgit From b4bcbdee137833aab04942671b48a9a3beb0801b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 15 Apr 2019 21:02:22 +0200 Subject: ARM: dts: s5pv210: Fix camera clock provider on Goni board The camera driver (according also to bindings) registers a clock provider if clock-output-names property is present and later the sensors use registered clocks. The DTS for S5Pv210 Goni board was incorrectly adding a child node with clock output cells but without clock-output-names property. Although the DTS was compiling (with "/soc/camera/clock-controller: missing or empty reg/ranges property" warning), the clock provider was not registered. Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210-goni.dts | 2 +- arch/arm/boot/dts/s5pv210.dtsi | 6 ++---- 2 files changed, 3 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/s5pv210-goni.dts b/arch/arm/boot/dts/s5pv210-goni.dts index eb6d1926c0d6..fbbd93707404 100644 --- a/arch/arm/boot/dts/s5pv210-goni.dts +++ b/arch/arm/boot/dts/s5pv210-goni.dts @@ -376,7 +376,7 @@ vdd_core-supply = <&ldo14_reg>; clock-frequency = <16000000>; - clocks = <&clock_cam 0>; + clocks = <&camera 0>; clock-names = "mclk"; nreset-gpios = <&gpb 2 0>; nstby-gpios = <&gpb 0 0>; diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index a44d5eb56bed..2ad642f51fd9 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -585,12 +585,10 @@ clock-names = "sclk_cam0", "sclk_cam1"; #address-cells = <1>; #size-cells = <1>; + #clock-cells = <1>; + clock-output-names = "cam_a_clkout", "cam_b_clkout"; ranges; - clock_cam: clock-controller { - #clock-cells = <1>; - }; - csis0: csis@fa600000 { compatible = "samsung,s5pv210-csis"; reg = <0xfa600000 0x4000>; -- cgit From 6969d1d9c61524d3ce492cfdca92d5dfa51e2e54 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Wed, 19 Dec 2018 15:55:28 -0800 Subject: ARM: dts: qcom-apq8064: Set 'cxo_board' as ref clock of the DSI PHY Add 'xo_board' as ref clock for the DSI PHY, it was previously hardcoded in the PLL 'driver' for the 28nm 8960 PHY. Signed-off-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-apq8064.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 8ca89c79bd0e..65975df6a8c3 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -1303,8 +1303,9 @@ <0x04700300 0x200>, <0x04700500 0x5c>; reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator"; - clock-names = "iface_clk"; - clocks = <&mmcc DSI_M_AHB_CLK>; + clock-names = "iface_clk", "ref"; + clocks = <&mmcc DSI_M_AHB_CLK>, + <&cxo_board>; }; -- cgit From c8e3993dd5b90d4e1c5a0edf853fa91add12b302 Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Tue, 23 Apr 2019 15:12:34 +0100 Subject: dt-bindings: hwmon (pwm-fan) Remove dead "cooling-*-state" properties The old "cooling-{min,max}-state" properties for thermal bindings were ratified to "cooling-{min,max}-level" by commit eb168b70dea5 ("of: thermal: Fix inconsitency between cooling-*-state and cooling-*-level"), which were later removed entirely by commit e04907dbc259 ("dt-bindings: thermal: Remove "cooling-{min|max}-level" properties"). The pwm-fan binding, however, was apparently in-flight in parallel with that ratification, and so managed to introduce an example of the old properties which escaped the scope of the later cleanup and has thus continued to be dutifully copied for new boards despite being useless. Clean up these remaining undocumented anachronisms to minimise any further confusion. Acked-by: Guenter Roeck Reviewed-by: Krzysztof Kozlowski Acked-by: Thierry Reding Acked-by: Heiko Stuebner Acked-by: Shawn Guo Reviewed-by: Rob Herring Signed-off-by: Robin Murphy Signed-off-by: Olof Johansson --- arch/arm/boot/dts/exynos4412-odroidu3.dts | 2 -- arch/arm/boot/dts/exynos5410-odroidxu.dts | 2 -- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 2 -- arch/arm/boot/dts/imx6qdl-emcon.dtsi | 2 -- 4 files changed, 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/exynos4412-odroidu3.dts index 88891ff5f238..96d99887bceb 100644 --- a/arch/arm/boot/dts/exynos4412-odroidu3.dts +++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts @@ -34,8 +34,6 @@ fan0: pwm-fan { compatible = "pwm-fan"; pwms = <&pwm 0 10000 0>; - cooling-min-state = <0>; - cooling-max-state = <3>; #cooling-cells = <2>; cooling-levels = <0 102 170 230>; }; diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index 434a7591ff63..8f9e08f940ab 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -38,8 +38,6 @@ fan0: pwm-fan { compatible = "pwm-fan"; pwms = <&pwm 0 20972 0>; - cooling-min-state = <0>; - cooling-max-state = <3>; #cooling-cells = <2>; cooling-levels = <0 130 170 230>; }; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index 5f195ad7e467..93a48f2dda49 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -44,8 +44,6 @@ fan0: pwm-fan { compatible = "pwm-fan"; pwms = <&pwm 0 20972 0>; - cooling-min-state = <0>; - cooling-max-state = <3>; #cooling-cells = <2>; cooling-levels = <0 130 170 230>; }; diff --git a/arch/arm/boot/dts/imx6qdl-emcon.dtsi b/arch/arm/boot/dts/imx6qdl-emcon.dtsi index 397e205551c4..70d26616d771 100644 --- a/arch/arm/boot/dts/imx6qdl-emcon.dtsi +++ b/arch/arm/boot/dts/imx6qdl-emcon.dtsi @@ -77,8 +77,6 @@ pwm_fan: pwm-fan { compatible = "pwm-fan"; - cooling-min-state = <0>; - cooling-max-state = <4>; #cooling-cells = <2>; pwms = <&pwm4 0 50000>; cooling-levels = <0 64 127 191 255>; -- cgit From 44b9c8e7729081105f9fb13ca6b8ed4803170954 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 27 Apr 2019 11:54:51 +0200 Subject: ARM: dts: gemini: Indent DIR-685 partition table It is discouraged to have OF partitions as subnodes directly under the device, create a "partitions" subnode and put the partitions inside it. Signed-off-by: Linus Walleij Signed-off-by: Olof Johansson --- arch/arm/boot/dts/gemini-dlink-dir-685.dts | 82 ++++++++++++++++-------------- 1 file changed, 44 insertions(+), 38 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/gemini-dlink-dir-685.dts b/arch/arm/boot/dts/gemini-dlink-dir-685.dts index 592111c8d6fd..cfbfbc91a1e1 100644 --- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts +++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts @@ -267,44 +267,50 @@ /* 32MB of flash */ reg = <0x30000000 0x02000000>; - /* - * This "RedBoot" is the Storlink derivative. - */ - partition@0 { - label = "RedBoot"; - reg = <0x00000000 0x00040000>; - read-only; - }; - /* - * This firmware image contains the kernel catenated - * with the squashfs root filesystem. For some reason - * this is called "upgrade" on the vendor system. - */ - partition@40000 { - label = "upgrade"; - reg = <0x00040000 0x01f40000>; - read-only; - }; - /* RGDB, Residental Gateway Database? */ - partition@1f80000 { - label = "rgdb"; - reg = <0x01f80000 0x00040000>; - read-only; - }; - /* - * This partition contains MAC addresses for WAN, - * WLAN and LAN, and the country code (for wireless - * I guess). - */ - partition@1fc0000 { - label = "nvram"; - reg = <0x01fc0000 0x00020000>; - read-only; - }; - partition@1fe0000 { - label = "LangPack"; - reg = <0x01fe0000 0x00020000>; - read-only; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* + * This "RedBoot" is the Storlink derivative. + */ + partition@0 { + label = "RedBoot"; + reg = <0x00000000 0x00040000>; + read-only; + }; + /* + * This firmware image contains the kernel catenated + * with the squashfs root filesystem. For some reason + * this is called "upgrade" on the vendor system. + */ + partition@40000 { + label = "upgrade"; + reg = <0x00040000 0x01f40000>; + read-only; + }; + /* RGDB, Residental Gateway Database? */ + partition@1f80000 { + label = "rgdb"; + reg = <0x01f80000 0x00040000>; + read-only; + }; + /* + * This partition contains MAC addresses for WAN, + * WLAN and LAN, and the country code (for wireless + * I guess). + */ + partition@1fc0000 { + label = "nvram"; + reg = <0x01fc0000 0x00020000>; + read-only; + }; + partition@1fe0000 { + label = "LangPack"; + reg = <0x01fe0000 0x00020000>; + read-only; + }; }; }; -- cgit