From e73307b9ebc4ecb02df60be441a541c37dbdce7a Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 29 Sep 2022 15:29:56 +0200 Subject: ARM: cns3xxx: remove entire platform MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit cns3xxx was marked as unused a while ago, and gets removed entirely now. Acked-by: Krzysztof Hałasa Signed-off-by: Arnd Bergmann --- arch/arm/Kconfig | 2 - arch/arm/Kconfig.debug | 10 - arch/arm/Makefile | 1 - arch/arm/configs/cns3420vb_defconfig | 63 ---- arch/arm/mach-cns3xxx/Kconfig | 21 -- arch/arm/mach-cns3xxx/Makefile | 6 - arch/arm/mach-cns3xxx/cns3420vb.c | 252 --------------- arch/arm/mach-cns3xxx/cns3xxx.h | 593 ----------------------------------- arch/arm/mach-cns3xxx/core.c | 410 ------------------------ arch/arm/mach-cns3xxx/core.h | 32 -- arch/arm/mach-cns3xxx/devices.c | 108 ------- arch/arm/mach-cns3xxx/devices.h | 17 - arch/arm/mach-cns3xxx/pcie.c | 290 ----------------- arch/arm/mach-cns3xxx/pm.c | 120 ------- arch/arm/mach-cns3xxx/pm.h | 20 -- 15 files changed, 1945 deletions(-) delete mode 100644 arch/arm/configs/cns3420vb_defconfig delete mode 100644 arch/arm/mach-cns3xxx/Kconfig delete mode 100644 arch/arm/mach-cns3xxx/Makefile delete mode 100644 arch/arm/mach-cns3xxx/cns3420vb.c delete mode 100644 arch/arm/mach-cns3xxx/cns3xxx.h delete mode 100644 arch/arm/mach-cns3xxx/core.c delete mode 100644 arch/arm/mach-cns3xxx/core.h delete mode 100644 arch/arm/mach-cns3xxx/devices.c delete mode 100644 arch/arm/mach-cns3xxx/devices.h delete mode 100644 arch/arm/mach-cns3xxx/pcie.c delete mode 100644 arch/arm/mach-cns3xxx/pm.c delete mode 100644 arch/arm/mach-cns3xxx/pm.h (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 43c7773b89ae..76ffb49e23fc 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -438,8 +438,6 @@ source "arch/arm/mach-berlin/Kconfig" source "arch/arm/mach-clps711x/Kconfig" -source "arch/arm/mach-cns3xxx/Kconfig" - source "arch/arm/mach-davinci/Kconfig" source "arch/arm/mach-digicolor/Kconfig" diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index c345775f035b..3b11e1d04625 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -307,14 +307,6 @@ choice Say Y here if you want the debug print routines to direct their output to the second serial port on these devices. - config DEBUG_CNS3XXX - bool "Kernel Kernel low-level debugging on Cavium Networks CNS3xxx" - depends on ARCH_CNS3XXX - select DEBUG_UART_8250 - help - Say Y here if you want the debug print routines to direct - their output to the CNS3xxx UART0. - config DEBUG_DAVINCI_DA8XX_UART1 bool "Kernel low-level debugging on DaVinci DA8XX using UART1" depends on ARCH_DAVINCI_DA8XX @@ -1685,7 +1677,6 @@ config DEBUG_UART_PHYS DEBUG_S3C2410_UART1) default 0x50008000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART2 || \ DEBUG_S3C2410_UART2) - default 0x78000000 if DEBUG_CNS3XXX default 0x7c0003f8 if DEBUG_FOOTBRIDGE_COM1 default 0x7f005000 if DEBUG_S3C64XX_UART && DEBUG_S3C_UART0 default 0x7f005400 if DEBUG_S3C64XX_UART && DEBUG_S3C_UART1 @@ -1818,7 +1809,6 @@ config DEBUG_UART_VIRT DEBUG_OMAP4UART2 || DEBUG_OMAP5UART2 default 0xfa06e000 if DEBUG_OMAP2UART3 || DEBUG_OMAP4UART4 default 0xfa71e000 if DEBUG_QCOM_UARTDM - default 0xfb002000 if DEBUG_CNS3XXX default 0xfb009000 if DEBUG_REALVIEW_STD_PORT default 0xfb00c000 if DEBUG_AT91_SAMA5D4_USART3 default 0xfb020000 if DEBUG_OMAP3UART3 diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 4067f5169144..d770827588c0 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -178,7 +178,6 @@ machine-$(CONFIG_ARCH_AXXIA) += axxia machine-$(CONFIG_ARCH_BCM) += bcm machine-$(CONFIG_ARCH_BERLIN) += berlin machine-$(CONFIG_ARCH_CLPS711X) += clps711x -machine-$(CONFIG_ARCH_CNS3XXX) += cns3xxx machine-$(CONFIG_ARCH_DAVINCI) += davinci machine-$(CONFIG_ARCH_DIGICOLOR) += digicolor machine-$(CONFIG_ARCH_DOVE) += dove diff --git a/arch/arm/configs/cns3420vb_defconfig b/arch/arm/configs/cns3420vb_defconfig deleted file mode 100644 index b3aab97c0728..000000000000 --- a/arch/arm/configs/cns3420vb_defconfig +++ /dev/null @@ -1,63 +0,0 @@ -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_CGROUPS=y -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_RELAY=y -CONFIG_BLK_DEV_INITRD=y -# CONFIG_PERF_EVENTS is not set -CONFIG_PROFILING=y -CONFIG_ARCH_MULTI_V6=y -CONFIG_ARCH_CNS3XXX=y -CONFIG_MACH_CNS3420VB=y -CONFIG_UNUSED_BOARD_FILES=y -CONFIG_CMDLINE="console=ttyS0,38400 mem=128M root=/dev/mmcblk0p1 ro rootwait" -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_IOSCHED_BFQ=m -#CONFIG_ARCH_MULTI_V7 is not set -CONFIG_DEBUG_CNS3XXX=y -CONFIG_AEABI=y -# CONFIG_SWAP is not set -CONFIG_SLAB=y -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_PHYSMAP=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=20000 -CONFIG_BLK_DEV_SD=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ATA=y -# CONFIG_SATA_PMP is not set -# CONFIG_ATA_SFF is not set -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -CONFIG_LEGACY_PTY_COUNT=16 -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -# CONFIG_HW_RANDOM is not set -# CONFIG_HWMON is not set -# CONFIG_VGA_CONSOLE is not set -# CONFIG_USB_SUPPORT is not set -CONFIG_MMC=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_AUTOFS4_FS=y -CONFIG_FSCACHE=y -CONFIG_TMPFS=y -# CONFIG_ENABLE_MUST_CHECK is not set -# CONFIG_ARM_UNWIND is not set -CONFIG_CRC_CCITT=y -CONFIG_DEBUG_FS=y diff --git a/arch/arm/mach-cns3xxx/Kconfig b/arch/arm/mach-cns3xxx/Kconfig deleted file mode 100644 index 1f85deff2486..000000000000 --- a/arch/arm/mach-cns3xxx/Kconfig +++ /dev/null @@ -1,21 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -menuconfig ARCH_CNS3XXX - bool "Cavium Networks CNS3XXX family" - depends on ARCH_MULTI_V6 - depends on ATAGS && UNUSED_BOARD_FILES - select ARM_GIC - help - Support for Cavium Networks CNS3XXX platform. - -if ARCH_CNS3XXX - -config MACH_CNS3420VB - bool "Support for CNS3420 Validation Board" - depends on ATAGS - help - Include support for the Cavium Networks CNS3420 MPCore Platform - Baseboard. - This is a platform with an on-board ARM11 MPCore and has support - for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, etc. - -endif diff --git a/arch/arm/mach-cns3xxx/Makefile b/arch/arm/mach-cns3xxx/Makefile deleted file mode 100644 index 52ca6ed62304..000000000000 --- a/arch/arm/mach-cns3xxx/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_ARCH_CNS3XXX) += cns3xxx.o -cns3xxx-y += core.o pm.o -cns3xxx-$(CONFIG_ATAGS) += devices.o -cns3xxx-$(CONFIG_PCI) += pcie.o -cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c deleted file mode 100644 index 9099560aa462..000000000000 --- a/arch/arm/mach-cns3xxx/cns3420vb.c +++ /dev/null @@ -1,252 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Cavium Networks CNS3420 Validation Board - * - * Copyright 2000 Deep Blue Solutions Ltd - * Copyright 2008 ARM Limited - * Copyright 2008 Cavium Networks - * Scott Shu - * Copyright 2010 MontaVista Software, LLC. - * Anton Vorontsov - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "cns3xxx.h" -#include "pm.h" -#include "core.h" -#include "devices.h" - -/* - * NOR Flash - */ -static struct mtd_partition cns3420_nor_partitions[] = { - { - .name = "uboot", - .size = 0x00040000, - .offset = 0, - .mask_flags = MTD_WRITEABLE, - }, { - .name = "kernel", - .size = 0x004C0000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "filesystem", - .size = 0x7000000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "filesystem2", - .size = 0x0AE0000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "ubootenv", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - }, -}; - -static struct physmap_flash_data cns3420_nor_pdata = { - .width = 2, - .parts = cns3420_nor_partitions, - .nr_parts = ARRAY_SIZE(cns3420_nor_partitions), -}; - -static struct resource cns3420_nor_res = { - .start = CNS3XXX_FLASH_BASE, - .end = CNS3XXX_FLASH_BASE + SZ_128M - 1, - .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, -}; - -static struct platform_device cns3420_nor_pdev = { - .name = "physmap-flash", - .id = 0, - .resource = &cns3420_nor_res, - .num_resources = 1, - .dev = { - .platform_data = &cns3420_nor_pdata, - }, -}; - -/* - * UART - */ -static void __init cns3420_early_serial_setup(void) -{ -#ifdef CONFIG_SERIAL_8250_CONSOLE - static struct uart_port cns3420_serial_port = { - .membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT, - .mapbase = CNS3XXX_UART0_BASE, - .irq = IRQ_CNS3XXX_UART0, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE, - .regshift = 2, - .uartclk = 24000000, - .line = 0, - .type = PORT_16550A, - .fifosize = 16, - }; - - early_serial_setup(&cns3420_serial_port); -#endif -} - -/* - * USB - */ -static struct resource cns3xxx_usb_ehci_resources[] = { - [0] = { - .start = CNS3XXX_USB_BASE, - .end = CNS3XXX_USB_BASE + SZ_16M - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_CNS3XXX_USB_EHCI, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32); - -static int csn3xxx_usb_power_on(struct platform_device *pdev) -{ - /* - * EHCI and OHCI share the same clock and power, - * resetting twice would cause the 1st controller been reset. - * Therefore only do power up at the first up device, and - * power down at the last down device. - * - * Set USB AHB INCR length to 16 - */ - if (atomic_inc_return(&usb_pwr_ref) == 1) { - cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB); - cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); - cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST); - __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)), - MISC_CHIP_CONFIG_REG); - } - - return 0; -} - -static void csn3xxx_usb_power_off(struct platform_device *pdev) -{ - /* - * EHCI and OHCI share the same clock and power, - * resetting twice would cause the 1st controller been reset. - * Therefore only do power up at the first up device, and - * power down at the last down device. - */ - if (atomic_dec_return(&usb_pwr_ref) == 0) - cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); -} - -static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = { - .power_on = csn3xxx_usb_power_on, - .power_off = csn3xxx_usb_power_off, -}; - -static struct platform_device cns3xxx_usb_ehci_device = { - .name = "ehci-platform", - .num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources), - .resource = cns3xxx_usb_ehci_resources, - .dev = { - .dma_mask = &cns3xxx_usb_ehci_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &cns3xxx_usb_ehci_pdata, - }, -}; - -static struct resource cns3xxx_usb_ohci_resources[] = { - [0] = { - .start = CNS3XXX_USB_OHCI_BASE, - .end = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_CNS3XXX_USB_OHCI, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32); - -static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = { - .num_ports = 1, - .power_on = csn3xxx_usb_power_on, - .power_off = csn3xxx_usb_power_off, -}; - -static struct platform_device cns3xxx_usb_ohci_device = { - .name = "ohci-platform", - .num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources), - .resource = cns3xxx_usb_ohci_resources, - .dev = { - .dma_mask = &cns3xxx_usb_ohci_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &cns3xxx_usb_ohci_pdata, - }, -}; - -/* - * Initialization - */ -static struct platform_device *cns3420_pdevs[] __initdata = { - &cns3420_nor_pdev, - &cns3xxx_usb_ehci_device, - &cns3xxx_usb_ohci_device, -}; - -static void __init cns3420_init(void) -{ - cns3xxx_l2x0_init(); - - platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs)); - - cns3xxx_ahci_init(); - cns3xxx_sdhci_init(); - - pm_power_off = cns3xxx_power_off; -} - -static struct map_desc cns3420_io_desc[] __initdata = { - { - .virtual = CNS3XXX_UART0_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_UART0_BASE), - .length = SZ_4K, - .type = MT_DEVICE, - }, -}; - -static void __init cns3420_map_io(void) -{ - cns3xxx_map_io(); - iotable_init(cns3420_io_desc, ARRAY_SIZE(cns3420_io_desc)); - - cns3420_early_serial_setup(); -} - -MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board") - .atag_offset = 0x100, - .map_io = cns3420_map_io, - .init_irq = cns3xxx_init_irq, - .init_time = cns3xxx_timer_init, - .init_machine = cns3420_init, - .init_late = cns3xxx_pcie_init_late, - .restart = cns3xxx_restart, -MACHINE_END diff --git a/arch/arm/mach-cns3xxx/cns3xxx.h b/arch/arm/mach-cns3xxx/cns3xxx.h deleted file mode 100644 index cbb105a74f90..000000000000 --- a/arch/arm/mach-cns3xxx/cns3xxx.h +++ /dev/null @@ -1,593 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2008 Cavium Networks - */ - -#ifndef __MACH_BOARD_CNS3XXXH -#define __MACH_BOARD_CNS3XXXH - -/* - * Memory map - */ -#define CNS3XXX_FLASH_BASE 0x10000000 /* Flash/SRAM Memory Bank 0 */ -#define CNS3XXX_FLASH_SIZE SZ_256M - -#define CNS3XXX_DDR2SDRAM_BASE 0x20000000 /* DDR2 SDRAM Memory */ - -#define CNS3XXX_SPI_FLASH_BASE 0x60000000 /* SPI Serial Flash Memory */ - -#define CNS3XXX_SWITCH_BASE 0x70000000 /* Switch and HNAT Control */ - -#define CNS3XXX_PPE_BASE 0x70001000 /* HANT */ - -#define CNS3XXX_EMBEDDED_SRAM_BASE 0x70002000 /* HANT Embedded SRAM */ - -#define CNS3XXX_SSP_BASE 0x71000000 /* Synchronous Serial Port - SPI/PCM/I2C */ - -#define CNS3XXX_DMC_BASE 0x72000000 /* DMC Control (DDR2 SDRAM) */ - -#define CNS3XXX_SMC_BASE 0x73000000 /* SMC Control */ - -#define SMC_MEMC_STATUS_OFFSET 0x000 -#define SMC_MEMIF_CFG_OFFSET 0x004 -#define SMC_MEMC_CFG_SET_OFFSET 0x008 -#define SMC_MEMC_CFG_CLR_OFFSET 0x00C -#define SMC_DIRECT_CMD_OFFSET 0x010 -#define SMC_SET_CYCLES_OFFSET 0x014 -#define SMC_SET_OPMODE_OFFSET 0x018 -#define SMC_REFRESH_PERIOD_0_OFFSET 0x020 -#define SMC_REFRESH_PERIOD_1_OFFSET 0x024 -#define SMC_SRAM_CYCLES0_0_OFFSET 0x100 -#define SMC_NAND_CYCLES0_0_OFFSET 0x100 -#define SMC_OPMODE0_0_OFFSET 0x104 -#define SMC_SRAM_CYCLES0_1_OFFSET 0x120 -#define SMC_NAND_CYCLES0_1_OFFSET 0x120 -#define SMC_OPMODE0_1_OFFSET 0x124 -#define SMC_USER_STATUS_OFFSET 0x200 -#define SMC_USER_CONFIG_OFFSET 0x204 -#define SMC_ECC_STATUS_OFFSET 0x300 -#define SMC_ECC_MEMCFG_OFFSET 0x304 -#define SMC_ECC_MEMCOMMAND1_OFFSET 0x308 -#define SMC_ECC_MEMCOMMAND2_OFFSET 0x30C -#define SMC_ECC_ADDR0_OFFSET 0x310 -#define SMC_ECC_ADDR1_OFFSET 0x314 -#define SMC_ECC_VALUE0_OFFSET 0x318 -#define SMC_ECC_VALUE1_OFFSET 0x31C -#define SMC_ECC_VALUE2_OFFSET 0x320 -#define SMC_ECC_VALUE3_OFFSET 0x324 -#define SMC_PERIPH_ID_0_OFFSET 0xFE0 -#define SMC_PERIPH_ID_1_OFFSET 0xFE4 -#define SMC_PERIPH_ID_2_OFFSET 0xFE8 -#define SMC_PERIPH_ID_3_OFFSET 0xFEC -#define SMC_PCELL_ID_0_OFFSET 0xFF0 -#define SMC_PCELL_ID_1_OFFSET 0xFF4 -#define SMC_PCELL_ID_2_OFFSET 0xFF8 -#define SMC_PCELL_ID_3_OFFSET 0xFFC - -#define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */ - -#define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */ - -#define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */ - -#define RTC_SEC_OFFSET 0x00 -#define RTC_MIN_OFFSET 0x04 -#define RTC_HOUR_OFFSET 0x08 -#define RTC_DAY_OFFSET 0x0C -#define RTC_SEC_ALM_OFFSET 0x10 -#define RTC_MIN_ALM_OFFSET 0x14 -#define RTC_HOUR_ALM_OFFSET 0x18 -#define RTC_REC_OFFSET 0x1C -#define RTC_CTRL_OFFSET 0x20 -#define RTC_INTR_STS_OFFSET 0x34 - -#define CNS3XXX_MISC_BASE 0x76000000 /* Misc Control */ -#define CNS3XXX_MISC_BASE_VIRT 0xFB000000 /* Misc Control */ - -#define CNS3XXX_PM_BASE 0x77000000 /* Power Management Control */ -#define CNS3XXX_PM_BASE_VIRT 0xFB001000 - -#define PM_CLK_GATE_OFFSET 0x00 -#define PM_SOFT_RST_OFFSET 0x04 -#define PM_HS_CFG_OFFSET 0x08 -#define PM_CACTIVE_STA_OFFSET 0x0C -#define PM_PWR_STA_OFFSET 0x10 -#define PM_SYS_CLK_CTRL_OFFSET 0x14 -#define PM_PLL_LCD_I2S_CTRL_OFFSET 0x18 -#define PM_PLL_HM_PD_OFFSET 0x1C - -#define CNS3XXX_UART0_BASE 0x78000000 /* UART 0 */ -#define CNS3XXX_UART0_BASE_VIRT 0xFB002000 - -#define CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */ - -#define CNS3XXX_UART2_BASE 0x78800000 /* UART 2 */ - -#define CNS3XXX_DMAC_BASE 0x79000000 /* Generic DMA Control */ - -#define CNS3XXX_CORESIGHT_BASE 0x7A000000 /* CoreSight */ - -#define CNS3XXX_CRYPTO_BASE 0x7B000000 /* Crypto */ - -#define CNS3XXX_I2S_BASE 0x7C000000 /* I2S */ - -#define CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */ -#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFB003000 - -#define TIMER1_COUNTER_OFFSET 0x00 -#define TIMER1_AUTO_RELOAD_OFFSET 0x04 -#define TIMER1_MATCH_V1_OFFSET 0x08 -#define TIMER1_MATCH_V2_OFFSET 0x0C - -#define TIMER2_COUNTER_OFFSET 0x10 -#define TIMER2_AUTO_RELOAD_OFFSET 0x14 -#define TIMER2_MATCH_V1_OFFSET 0x18 -#define TIMER2_MATCH_V2_OFFSET 0x1C - -#define TIMER1_2_CONTROL_OFFSET 0x30 -#define TIMER1_2_INTERRUPT_STATUS_OFFSET 0x34 -#define TIMER1_2_INTERRUPT_MASK_OFFSET 0x38 - -#define TIMER_FREERUN_OFFSET 0x40 -#define TIMER_FREERUN_CONTROL_OFFSET 0x44 - -#define CNS3XXX_HCIE_BASE 0x7D000000 /* HCIE Control */ - -#define CNS3XXX_RAID_BASE 0x7E000000 /* RAID Control */ - -#define CNS3XXX_AXI_IXC_BASE 0x7F000000 /* AXI IXC */ - -#define CNS3XXX_CLCD_BASE 0x80000000 /* LCD Control */ - -#define CNS3XXX_USBOTG_BASE 0x81000000 /* USB OTG Control */ - -#define CNS3XXX_USB_BASE 0x82000000 /* USB Host Control */ - -#define CNS3XXX_SATA2_BASE 0x83000000 /* SATA */ -#define CNS3XXX_SATA2_SIZE SZ_16M - -#define CNS3XXX_CAMERA_BASE 0x84000000 /* Camera Interface */ - -#define CNS3XXX_SDIO_BASE 0x85000000 /* SDIO */ - -#define CNS3XXX_I2S_TDM_BASE 0x86000000 /* I2S TDM */ - -#define CNS3XXX_2DG_BASE 0x87000000 /* 2D Graphic Control */ - -#define CNS3XXX_USB_OHCI_BASE 0x88000000 /* USB OHCI */ - -#define CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */ - -#define CNS3XXX_PCIE0_MEM_BASE 0xA0000000 /* PCIe Port 0 IO/Memory Space */ - -#define CNS3XXX_PCIE0_HOST_BASE 0xAB000000 /* PCIe Port 0 RC Base */ -#define CNS3XXX_PCIE0_HOST_BASE_VIRT 0xE1000000 - -#define CNS3XXX_PCIE0_IO_BASE 0xAC000000 /* PCIe Port 0 */ - -#define CNS3XXX_PCIE0_CFG0_BASE 0xAD000000 /* PCIe Port 0 CFG Type 0 */ -#define CNS3XXX_PCIE0_CFG0_BASE_VIRT 0xE3000000 - -#define CNS3XXX_PCIE0_CFG1_BASE 0xAE000000 /* PCIe Port 0 CFG Type 1 */ -#define CNS3XXX_PCIE0_CFG1_BASE_VIRT 0xE4000000 - -#define CNS3XXX_PCIE0_MSG_BASE 0xAF000000 /* PCIe Port 0 Message Space */ - -#define CNS3XXX_PCIE1_MEM_BASE 0xB0000000 /* PCIe Port 1 IO/Memory Space */ - -#define CNS3XXX_PCIE1_HOST_BASE 0xBB000000 /* PCIe Port 1 RC Base */ -#define CNS3XXX_PCIE1_HOST_BASE_VIRT 0xE9000000 - -#define CNS3XXX_PCIE1_IO_BASE 0xBC000000 /* PCIe Port 1 */ - -#define CNS3XXX_PCIE1_CFG0_BASE 0xBD000000 /* PCIe Port 1 CFG Type 0 */ -#define CNS3XXX_PCIE1_CFG0_BASE_VIRT 0xEB000000 - -#define CNS3XXX_PCIE1_CFG1_BASE 0xBE000000 /* PCIe Port 1 CFG Type 1 */ -#define CNS3XXX_PCIE1_CFG1_BASE_VIRT 0xEC000000 - -#define CNS3XXX_PCIE1_MSG_BASE 0xBF000000 /* PCIe Port 1 Message Space */ - -/* - * Testchip peripheral and fpga gic regions - */ -#define CNS3XXX_TC11MP_SCU_BASE 0x90000000 /* IRQ, Test chip */ -#define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFB004000 - -#define CNS3XXX_TC11MP_GIC_CPU_BASE 0x90000100 /* Test chip interrupt controller CPU interface */ -#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x100) - -#define CNS3XXX_TC11MP_TWD_BASE 0x90000600 -#define CNS3XXX_TC11MP_TWD_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x600) - -#define CNS3XXX_TC11MP_GIC_DIST_BASE 0x90001000 /* Test chip interrupt controller distributor */ -#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x1000) - -#define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */ - -/* - * Misc block - */ -#define MISC_MEM_MAP(offs) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs)) - -#define MISC_MEMORY_REMAP_REG MISC_MEM_MAP(0x00) -#define MISC_CHIP_CONFIG_REG MISC_MEM_MAP(0x04) -#define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP(0x08) -#define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP(0x0C) -#define MISC_IO_PIN_FUNC_SELECTION_REG MISC_MEM_MAP(0x10) -#define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP(0x14) -#define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP(0x18) -#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A MISC_MEM_MAP(0x1C) -#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B MISC_MEM_MAP(0x20) -#define MISC_GPIOA_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x24) -#define MISC_GPIOA_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x28) -#define MISC_GPIOB_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x2C) -#define MISC_GPIOB_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x30) -#define MISC_IO_PULL_CTRL_REG MISC_MEM_MAP(0x34) -#define MISC_E_FUSE_31_0_REG MISC_MEM_MAP(0x40) -#define MISC_E_FUSE_63_32_REG MISC_MEM_MAP(0x44) -#define MISC_E_FUSE_95_64_REG MISC_MEM_MAP(0x48) -#define MISC_E_FUSE_127_96_REG MISC_MEM_MAP(0x4C) -#define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP(0x50) -#define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP(0x54) - -#define MISC_SATA_POWER_MODE MISC_MEM_MAP(0x310) - -#define MISC_USB_CFG_REG MISC_MEM_MAP(0x800) -#define MISC_USB_STS_REG MISC_MEM_MAP(0x804) -#define MISC_USBPHY00_CFG_REG MISC_MEM_MAP(0x808) -#define MISC_USBPHY01_CFG_REG MISC_MEM_MAP(0x80c) -#define MISC_USBPHY10_CFG_REG MISC_MEM_MAP(0x810) -#define MISC_USBPHY11_CFG_REG MISC_MEM_MAP(0x814) - -#define MISC_PCIEPHY_CMCTL(x) MISC_MEM_MAP(0x900 + (x) * 0x004) -#define MISC_PCIEPHY_CTL(x) MISC_MEM_MAP(0x940 + (x) * 0x100) -#define MISC_PCIE_AXIS_AWMISC(x) MISC_MEM_MAP(0x944 + (x) * 0x100) -#define MISC_PCIE_AXIS_ARMISC(x) MISC_MEM_MAP(0x948 + (x) * 0x100) -#define MISC_PCIE_AXIS_RMISC(x) MISC_MEM_MAP(0x94C + (x) * 0x100) -#define MISC_PCIE_AXIS_BMISC(x) MISC_MEM_MAP(0x950 + (x) * 0x100) -#define MISC_PCIE_AXIM_RMISC(x) MISC_MEM_MAP(0x954 + (x) * 0x100) -#define MISC_PCIE_AXIM_BMISC(x) MISC_MEM_MAP(0x958 + (x) * 0x100) -#define MISC_PCIE_CTRL(x) MISC_MEM_MAP(0x95C + (x) * 0x100) -#define MISC_PCIE_PM_DEBUG(x) MISC_MEM_MAP(0x960 + (x) * 0x100) -#define MISC_PCIE_RFC_DEBUG(x) MISC_MEM_MAP(0x964 + (x) * 0x100) -#define MISC_PCIE_CXPL_DEBUGL(x) MISC_MEM_MAP(0x968 + (x) * 0x100) -#define MISC_PCIE_CXPL_DEBUGH(x) MISC_MEM_MAP(0x96C + (x) * 0x100) -#define MISC_PCIE_DIAG_DEBUGH(x) MISC_MEM_MAP(0x970 + (x) * 0x100) -#define MISC_PCIE_W1CLR(x) MISC_MEM_MAP(0x974 + (x) * 0x100) -#define MISC_PCIE_INT_MASK(x) MISC_MEM_MAP(0x978 + (x) * 0x100) -#define MISC_PCIE_INT_STATUS(x) MISC_MEM_MAP(0x97C + (x) * 0x100) - -/* - * Power management and clock control - */ -#define PMU_MEM_MAP(offs) (void __iomem *)(CNS3XXX_PM_BASE_VIRT + (offs)) - -#define PM_CLK_GATE_REG PMU_MEM_MAP(0x000) -#define PM_SOFT_RST_REG PMU_MEM_MAP(0x004) -#define PM_HS_CFG_REG PMU_MEM_MAP(0x008) -#define PM_CACTIVE_STA_REG PMU_MEM_MAP(0x00C) -#define PM_PWR_STA_REG PMU_MEM_MAP(0x010) -#define PM_CLK_CTRL_REG PMU_MEM_MAP(0x014) -#define PM_PLL_LCD_I2S_CTRL_REG PMU_MEM_MAP(0x018) -#define PM_PLL_HM_PD_CTRL_REG PMU_MEM_MAP(0x01C) -#define PM_REGULAT_CTRL_REG PMU_MEM_MAP(0x020) -#define PM_WDT_CTRL_REG PMU_MEM_MAP(0x024) -#define PM_WU_CTRL0_REG PMU_MEM_MAP(0x028) -#define PM_WU_CTRL1_REG PMU_MEM_MAP(0x02C) -#define PM_CSR_REG PMU_MEM_MAP(0x030) - -/* PM_CLK_GATE_REG */ -#define PM_CLK_GATE_REG_OFFSET_SDIO (25) -#define PM_CLK_GATE_REG_OFFSET_GPU (24) -#define PM_CLK_GATE_REG_OFFSET_CIM (23) -#define PM_CLK_GATE_REG_OFFSET_LCDC (22) -#define PM_CLK_GATE_REG_OFFSET_I2S (21) -#define PM_CLK_GATE_REG_OFFSET_RAID (20) -#define PM_CLK_GATE_REG_OFFSET_SATA (19) -#define PM_CLK_GATE_REG_OFFSET_PCIE(x) (17 + (x)) -#define PM_CLK_GATE_REG_OFFSET_USB_HOST (16) -#define PM_CLK_GATE_REG_OFFSET_USB_OTG (15) -#define PM_CLK_GATE_REG_OFFSET_TIMER (14) -#define PM_CLK_GATE_REG_OFFSET_CRYPTO (13) -#define PM_CLK_GATE_REG_OFFSET_HCIE (12) -#define PM_CLK_GATE_REG_OFFSET_SWITCH (11) -#define PM_CLK_GATE_REG_OFFSET_GPIO (10) -#define PM_CLK_GATE_REG_OFFSET_UART3 (9) -#define PM_CLK_GATE_REG_OFFSET_UART2 (8) -#define PM_CLK_GATE_REG_OFFSET_UART1 (7) -#define PM_CLK_GATE_REG_OFFSET_RTC (5) -#define PM_CLK_GATE_REG_OFFSET_GDMA (4) -#define PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C (3) -#define PM_CLK_GATE_REG_OFFSET_SMC_NFI (1) -#define PM_CLK_GATE_REG_MASK (0x03FFFFBA) - -/* PM_SOFT_RST_REG */ -#define PM_SOFT_RST_REG_OFFST_WARM_RST_FLAG (31) -#define PM_SOFT_RST_REG_OFFST_CPU1 (29) -#define PM_SOFT_RST_REG_OFFST_CPU0 (28) -#define PM_SOFT_RST_REG_OFFST_SDIO (25) -#define PM_SOFT_RST_REG_OFFST_GPU (24) -#define PM_SOFT_RST_REG_OFFST_CIM (23) -#define PM_SOFT_RST_REG_OFFST_LCDC (22) -#define PM_SOFT_RST_REG_OFFST_I2S (21) -#define PM_SOFT_RST_REG_OFFST_RAID (20) -#define PM_SOFT_RST_REG_OFFST_SATA (19) -#define PM_SOFT_RST_REG_OFFST_PCIE(x) (17 + (x)) -#define PM_SOFT_RST_REG_OFFST_USB_HOST (16) -#define PM_SOFT_RST_REG_OFFST_USB_OTG (15) -#define PM_SOFT_RST_REG_OFFST_TIMER (14) -#define PM_SOFT_RST_REG_OFFST_CRYPTO (13) -#define PM_SOFT_RST_REG_OFFST_HCIE (12) -#define PM_SOFT_RST_REG_OFFST_SWITCH (11) -#define PM_SOFT_RST_REG_OFFST_GPIO (10) -#define PM_SOFT_RST_REG_OFFST_UART3 (9) -#define PM_SOFT_RST_REG_OFFST_UART2 (8) -#define PM_SOFT_RST_REG_OFFST_UART1 (7) -#define PM_SOFT_RST_REG_OFFST_RTC (5) -#define PM_SOFT_RST_REG_OFFST_GDMA (4) -#define PM_SOFT_RST_REG_OFFST_SPI_PCM_I2C (3) -#define PM_SOFT_RST_REG_OFFST_DMC (2) -#define PM_SOFT_RST_REG_OFFST_SMC_NFI (1) -#define PM_SOFT_RST_REG_OFFST_GLOBAL (0) -#define PM_SOFT_RST_REG_MASK (0xF3FFFFBF) - -/* PMHS_CFG_REG */ -#define PM_HS_CFG_REG_OFFSET_SDIO (25) -#define PM_HS_CFG_REG_OFFSET_GPU (24) -#define PM_HS_CFG_REG_OFFSET_CIM (23) -#define PM_HS_CFG_REG_OFFSET_LCDC (22) -#define PM_HS_CFG_REG_OFFSET_I2S (21) -#define PM_HS_CFG_REG_OFFSET_RAID (20) -#define PM_HS_CFG_REG_OFFSET_SATA (19) -#define PM_HS_CFG_REG_OFFSET_PCIE1 (18) -#define PM_HS_CFG_REG_OFFSET_PCIE0 (17) -#define PM_HS_CFG_REG_OFFSET_USB_HOST (16) -#define PM_HS_CFG_REG_OFFSET_USB_OTG (15) -#define PM_HS_CFG_REG_OFFSET_TIMER (14) -#define PM_HS_CFG_REG_OFFSET_CRYPTO (13) -#define PM_HS_CFG_REG_OFFSET_HCIE (12) -#define PM_HS_CFG_REG_OFFSET_SWITCH (11) -#define PM_HS_CFG_REG_OFFSET_GPIO (10) -#define PM_HS_CFG_REG_OFFSET_UART3 (9) -#define PM_HS_CFG_REG_OFFSET_UART2 (8) -#define PM_HS_CFG_REG_OFFSET_UART1 (7) -#define PM_HS_CFG_REG_OFFSET_RTC (5) -#define PM_HS_CFG_REG_OFFSET_GDMA (4) -#define PM_HS_CFG_REG_OFFSET_SPI_PCM_I2S (3) -#define PM_HS_CFG_REG_OFFSET_DMC (2) -#define PM_HS_CFG_REG_OFFSET_SMC_NFI (1) -#define PM_HS_CFG_REG_MASK (0x03FFFFBE) -#define PM_HS_CFG_REG_MASK_SUPPORT (0x01100806) - -/* PM_CACTIVE_STA_REG */ -#define PM_CACTIVE_STA_REG_OFFSET_SDIO (25) -#define PM_CACTIVE_STA_REG_OFFSET_GPU (24) -#define PM_CACTIVE_STA_REG_OFFSET_CIM (23) -#define PM_CACTIVE_STA_REG_OFFSET_LCDC (22) -#define PM_CACTIVE_STA_REG_OFFSET_I2S (21) -#define PM_CACTIVE_STA_REG_OFFSET_RAID (20) -#define PM_CACTIVE_STA_REG_OFFSET_SATA (19) -#define PM_CACTIVE_STA_REG_OFFSET_PCIE1 (18) -#define PM_CACTIVE_STA_REG_OFFSET_PCIE0 (17) -#define PM_CACTIVE_STA_REG_OFFSET_USB_HOST (16) -#define PM_CACTIVE_STA_REG_OFFSET_USB_OTG (15) -#define PM_CACTIVE_STA_REG_OFFSET_TIMER (14) -#define PM_CACTIVE_STA_REG_OFFSET_CRYPTO (13) -#define PM_CACTIVE_STA_REG_OFFSET_HCIE (12) -#define PM_CACTIVE_STA_REG_OFFSET_SWITCH (11) -#define PM_CACTIVE_STA_REG_OFFSET_GPIO (10) -#define PM_CACTIVE_STA_REG_OFFSET_UART3 (9) -#define PM_CACTIVE_STA_REG_OFFSET_UART2 (8) -#define PM_CACTIVE_STA_REG_OFFSET_UART1 (7) -#define PM_CACTIVE_STA_REG_OFFSET_RTC (5) -#define PM_CACTIVE_STA_REG_OFFSET_GDMA (4) -#define PM_CACTIVE_STA_REG_OFFSET_SPI_PCM_I2S (3) -#define PM_CACTIVE_STA_REG_OFFSET_DMC (2) -#define PM_CACTIVE_STA_REG_OFFSET_SMC_NFI (1) -#define PM_CACTIVE_STA_REG_MASK (0x03FFFFBE) - -/* PM_PWR_STA_REG */ -#define PM_PWR_STA_REG_REG_OFFSET_SDIO (25) -#define PM_PWR_STA_REG_REG_OFFSET_GPU (24) -#define PM_PWR_STA_REG_REG_OFFSET_CIM (23) -#define PM_PWR_STA_REG_REG_OFFSET_LCDC (22) -#define PM_PWR_STA_REG_REG_OFFSET_I2S (21) -#define PM_PWR_STA_REG_REG_OFFSET_RAID (20) -#define PM_PWR_STA_REG_REG_OFFSET_SATA (19) -#define PM_PWR_STA_REG_REG_OFFSET_PCIE1 (18) -#define PM_PWR_STA_REG_REG_OFFSET_PCIE0 (17) -#define PM_PWR_STA_REG_REG_OFFSET_USB_HOST (16) -#define PM_PWR_STA_REG_REG_OFFSET_USB_OTG (15) -#define PM_PWR_STA_REG_REG_OFFSET_TIMER (14) -#define PM_PWR_STA_REG_REG_OFFSET_CRYPTO (13) -#define PM_PWR_STA_REG_REG_OFFSET_HCIE (12) -#define PM_PWR_STA_REG_REG_OFFSET_SWITCH (11) -#define PM_PWR_STA_REG_REG_OFFSET_GPIO (10) -#define PM_PWR_STA_REG_REG_OFFSET_UART3 (9) -#define PM_PWR_STA_REG_REG_OFFSET_UART2 (8) -#define PM_PWR_STA_REG_REG_OFFSET_UART1 (7) -#define PM_PWR_STA_REG_REG_OFFSET_RTC (5) -#define PM_PWR_STA_REG_REG_OFFSET_GDMA (4) -#define PM_PWR_STA_REG_REG_OFFSET_SPI_PCM_I2S (3) -#define PM_PWR_STA_REG_REG_OFFSET_DMC (2) -#define PM_PWR_STA_REG_REG_OFFSET_SMC_NFI (1) -#define PM_PWR_STA_REG_REG_MASK (0x03FFFFBE) - -/* PM_CLK_CTRL_REG */ -#define PM_CLK_CTRL_REG_OFFSET_I2S_MCLK (31) -#define PM_CLK_CTRL_REG_OFFSET_DDR2_CHG_EN (30) -#define PM_CLK_CTRL_REG_OFFSET_PCIE_REF1_EN (29) -#define PM_CLK_CTRL_REG_OFFSET_PCIE_REF0_EN (28) -#define PM_CLK_CTRL_REG_OFFSET_TIMER_SIM_MODE (27) -#define PM_CLK_CTRL_REG_OFFSET_I2SCLK_DIV (24) -#define PM_CLK_CTRL_REG_OFFSET_I2SCLK_SEL (22) -#define PM_CLK_CTRL_REG_OFFSET_CLKOUT_DIV (20) -#define PM_CLK_CTRL_REG_OFFSET_CLKOUT_SEL (16) -#define PM_CLK_CTRL_REG_OFFSET_MDC_DIV (14) -#define PM_CLK_CTRL_REG_OFFSET_CRYPTO_CLK_SEL (12) -#define PM_CLK_CTRL_REG_OFFSET_CPU_PWR_MODE (9) -#define PM_CLK_CTRL_REG_OFFSET_PLL_DDR2_SEL (7) -#define PM_CLK_CTRL_REG_OFFSET_DIV_IMMEDIATE (6) -#define PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV (4) -#define PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL (0) - -#define PM_CPU_CLK_DIV(DIV) { \ - PM_CLK_CTRL_REG &= ~((0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \ - PM_CLK_CTRL_REG |= (((DIV)&0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \ -} - -#define PM_PLL_CPU_SEL(CPU) { \ - PM_CLK_CTRL_REG &= ~((0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \ - PM_CLK_CTRL_REG |= (((CPU)&0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \ -} - -/* PM_PLL_LCD_I2S_CTRL_REG */ -#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_MCLK_SMC_DIV (22) -#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_R_SEL (17) -#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_P (11) -#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_M (3) -#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_S (0) - -/* PM_PLL_HM_PD_CTRL_REG */ -#define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1 (11) -#define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0 (10) -#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2SCD (6) -#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2S (5) -#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_LCD (4) -#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB (3) -#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_RGMII (2) -#define PM_PLL_HM_PD_CTRL_REG_MASK (0x00000C7C) - -/* PM_WDT_CTRL_REG */ -#define PM_WDT_CTRL_REG_OFFSET_RESET_CPU_ONLY (0) - -/* PM_CSR_REG - Clock Scaling Register*/ -#define PM_CSR_REG_OFFSET_CSR_EN (30) -#define PM_CSR_REG_OFFSET_CSR_NUM (0) - -#define CNS3XXX_PWR_CLK_EN(BLOCK) (0x1< -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "cns3xxx.h" -#include "core.h" -#include "pm.h" - -static struct map_desc cns3xxx_io_desc[] __initdata = { - { - .virtual = CNS3XXX_TC11MP_SCU_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_TC11MP_SCU_BASE), - .length = SZ_8K, - .type = MT_DEVICE, - }, { - .virtual = CNS3XXX_TIMER1_2_3_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_TIMER1_2_3_BASE), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = CNS3XXX_MISC_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_MISC_BASE), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = CNS3XXX_PM_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_PM_BASE), - .length = SZ_4K, - .type = MT_DEVICE, -#ifdef CONFIG_PCI - }, { - .virtual = CNS3XXX_PCIE0_HOST_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_PCIE0_HOST_BASE), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = CNS3XXX_PCIE0_CFG0_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG0_BASE), - .length = SZ_64K, /* really 4 KiB at offset 32 KiB */ - .type = MT_DEVICE, - }, { - .virtual = CNS3XXX_PCIE0_CFG1_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG1_BASE), - .length = SZ_16M, - .type = MT_DEVICE, - }, { - .virtual = CNS3XXX_PCIE1_HOST_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_PCIE1_HOST_BASE), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = CNS3XXX_PCIE1_CFG0_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG0_BASE), - .length = SZ_64K, /* really 4 KiB at offset 32 KiB */ - .type = MT_DEVICE, - }, { - .virtual = CNS3XXX_PCIE1_CFG1_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG1_BASE), - .length = SZ_16M, - .type = MT_DEVICE, -#endif - }, -}; - -void __init cns3xxx_map_io(void) -{ - iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc)); -} - -/* used by entry-macro.S */ -void __init cns3xxx_init_irq(void) -{ - gic_init(IOMEM(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT), - IOMEM(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT)); -} - -void cns3xxx_power_off(void) -{ - u32 __iomem *pm_base = IOMEM(CNS3XXX_PM_BASE_VIRT); - u32 clkctrl; - - printk(KERN_INFO "powering system down...\n"); - - clkctrl = readl(pm_base + PM_SYS_CLK_CTRL_OFFSET); - clkctrl &= 0xfffff1ff; - clkctrl |= (0x5 << 9); /* Hibernate */ - writel(clkctrl, pm_base + PM_SYS_CLK_CTRL_OFFSET); - -} - -/* - * Timer - */ -static void __iomem *cns3xxx_tmr1; - -static int cns3xxx_shutdown(struct clock_event_device *clk) -{ - writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); - return 0; -} - -static int cns3xxx_set_oneshot(struct clock_event_device *clk) -{ - unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); - - /* period set, and timer enabled in 'next_event' hook */ - ctrl |= (1 << 2) | (1 << 9); - writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); - return 0; -} - -static int cns3xxx_set_periodic(struct clock_event_device *clk) -{ - unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); - int pclk = cns3xxx_cpu_clock() / 8; - int reload; - - reload = pclk * 20 / (3 * HZ) * 0x25000; - writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); - ctrl |= (1 << 0) | (1 << 2) | (1 << 9); - writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); - return 0; -} - -static int cns3xxx_timer_set_next_event(unsigned long evt, - struct clock_event_device *unused) -{ - unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); - - writel(evt, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); - writel(ctrl | (1 << 0), cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); - - return 0; -} - -static struct clock_event_device cns3xxx_tmr1_clockevent = { - .name = "cns3xxx timer1", - .features = CLOCK_EVT_FEAT_PERIODIC | - CLOCK_EVT_FEAT_ONESHOT, - .set_state_shutdown = cns3xxx_shutdown, - .set_state_periodic = cns3xxx_set_periodic, - .set_state_oneshot = cns3xxx_set_oneshot, - .tick_resume = cns3xxx_shutdown, - .set_next_event = cns3xxx_timer_set_next_event, - .rating = 350, - .cpumask = cpu_all_mask, -}; - -static void __init cns3xxx_clockevents_init(unsigned int timer_irq) -{ - cns3xxx_tmr1_clockevent.irq = timer_irq; - clockevents_config_and_register(&cns3xxx_tmr1_clockevent, - (cns3xxx_cpu_clock() >> 3) * 1000000, - 0xf, 0xffffffff); -} - -/* - * IRQ handler for the timer - */ -static irqreturn_t cns3xxx_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt = &cns3xxx_tmr1_clockevent; - u32 __iomem *stat = cns3xxx_tmr1 + TIMER1_2_INTERRUPT_STATUS_OFFSET; - u32 val; - - /* Clear the interrupt */ - val = readl(stat); - writel(val & ~(1 << 2), stat); - - evt->event_handler(evt); - - return IRQ_HANDLED; -} - -/* - * Set up the clock source and clock events devices - */ -static void __init __cns3xxx_timer_init(unsigned int timer_irq) -{ - u32 val; - u32 irq_mask; - - /* - * Initialise to a known state (all timers off) - */ - - /* disable timer1 and timer2 */ - writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); - /* stop free running timer3 */ - writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET); - - /* timer1 */ - writel(0x5C800, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET); - writel(0x5C800, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); - - writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V1_OFFSET); - writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V2_OFFSET); - - /* mask irq, non-mask timer1 overflow */ - irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); - irq_mask &= ~(1 << 2); - irq_mask |= 0x03; - writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); - - /* down counter */ - val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); - val |= (1 << 9); - writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); - - /* timer2 */ - writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V1_OFFSET); - writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V2_OFFSET); - - /* mask irq */ - irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); - irq_mask |= ((1 << 3) | (1 << 4) | (1 << 5)); - writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); - - /* down counter */ - val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); - val |= (1 << 10); - writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); - - /* Make irqs happen for the system timer */ - if (request_irq(timer_irq, cns3xxx_timer_interrupt, - IRQF_TIMER | IRQF_IRQPOLL, "timer", NULL)) - pr_err("Failed to request irq %d (timer)\n", timer_irq); - - cns3xxx_clockevents_init(timer_irq); -} - -void __init cns3xxx_timer_init(void) -{ - cns3xxx_tmr1 = IOMEM(CNS3XXX_TIMER1_2_3_BASE_VIRT); - - __cns3xxx_timer_init(IRQ_CNS3XXX_TIMER0); -} - -#ifdef CONFIG_CACHE_L2X0 - -void __init cns3xxx_l2x0_init(void) -{ - void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K); - u32 val; - - if (WARN_ON(!base)) - return; - - /* - * Tag RAM Control register - * - * bit[10:8] - 1 cycle of write accesses latency - * bit[6:4] - 1 cycle of read accesses latency - * bit[3:0] - 1 cycle of setup latency - * - * 1 cycle of latency for setup, read and write accesses - */ - val = readl(base + L310_TAG_LATENCY_CTRL); - val &= 0xfffff888; - writel(val, base + L310_TAG_LATENCY_CTRL); - - /* - * Data RAM Control register - * - * bit[10:8] - 1 cycles of write accesses latency - * bit[6:4] - 1 cycles of read accesses latency - * bit[3:0] - 1 cycle of setup latency - * - * 1 cycle of latency for setup, read and write accesses - */ - val = readl(base + L310_DATA_LATENCY_CTRL); - val &= 0xfffff888; - writel(val, base + L310_DATA_LATENCY_CTRL); - - /* 32 KiB, 8-way, parity disable */ - l2x0_init(base, 0x00500000, 0xfe0f0fff); -} - -#endif /* CONFIG_CACHE_L2X0 */ - -static int csn3xxx_usb_power_on(struct platform_device *pdev) -{ - /* - * EHCI and OHCI share the same clock and power, - * resetting twice would cause the 1st controller been reset. - * Therefore only do power up at the first up device, and - * power down at the last down device. - * - * Set USB AHB INCR length to 16 - */ - if (atomic_inc_return(&usb_pwr_ref) == 1) { - cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB); - cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); - cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST); - __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)), - MISC_CHIP_CONFIG_REG); - } - - return 0; -} - -static void csn3xxx_usb_power_off(struct platform_device *pdev) -{ - /* - * EHCI and OHCI share the same clock and power, - * resetting twice would cause the 1st controller been reset. - * Therefore only do power up at the first up device, and - * power down at the last down device. - */ - if (atomic_dec_return(&usb_pwr_ref) == 0) - cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); -} - -static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = { - .power_on = csn3xxx_usb_power_on, - .power_off = csn3xxx_usb_power_off, -}; - -static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = { - .num_ports = 1, - .power_on = csn3xxx_usb_power_on, - .power_off = csn3xxx_usb_power_off, -}; - -static const struct of_dev_auxdata cns3xxx_auxdata[] __initconst = { - { "intel,usb-ehci", CNS3XXX_USB_BASE, "ehci-platform", &cns3xxx_usb_ehci_pdata }, - { "intel,usb-ohci", CNS3XXX_USB_OHCI_BASE, "ohci-platform", &cns3xxx_usb_ohci_pdata }, - { "cavium,cns3420-ahci", CNS3XXX_SATA2_BASE, "ahci", NULL }, - { "cavium,cns3420-sdhci", CNS3XXX_SDIO_BASE, "ahci", NULL }, - {}, -}; - -static void __init cns3xxx_init(void) -{ - struct device_node *dn; - - cns3xxx_l2x0_init(); - - dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-ahci"); - if (of_device_is_available(dn)) { - u32 tmp; - - tmp = __raw_readl(MISC_SATA_POWER_MODE); - tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */ - tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */ - __raw_writel(tmp, MISC_SATA_POWER_MODE); - - /* Enable SATA PHY */ - cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0); - cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1); - - /* Enable SATA Clock */ - cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA); - - /* De-Asscer SATA Reset */ - cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA)); - } - of_node_put(dn); - - dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-sdhci"); - if (of_device_is_available(dn)) { - u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014); - u32 gpioa_pins = __raw_readl(gpioa); - - /* MMC/SD pins share with GPIOA */ - gpioa_pins |= 0x1fff0004; - __raw_writel(gpioa_pins, gpioa); - - cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO)); - cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO)); - } - of_node_put(dn); - - pm_power_off = cns3xxx_power_off; - - of_platform_default_populate(NULL, cns3xxx_auxdata, NULL); -} - -static const char *const cns3xxx_dt_compat[] __initconst = { - "cavium,cns3410", - "cavium,cns3420", - NULL, -}; - -DT_MACHINE_START(CNS3XXX_DT, "Cavium Networks CNS3xxx") - .dt_compat = cns3xxx_dt_compat, - .map_io = cns3xxx_map_io, - .init_irq = cns3xxx_init_irq, - .init_time = cns3xxx_timer_init, - .init_machine = cns3xxx_init, - .init_late = cns3xxx_pcie_init_late, - .restart = cns3xxx_restart, -MACHINE_END diff --git a/arch/arm/mach-cns3xxx/core.h b/arch/arm/mach-cns3xxx/core.h deleted file mode 100644 index a96eabaea301..000000000000 --- a/arch/arm/mach-cns3xxx/core.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2000 Deep Blue Solutions Ltd - * Copyright 2004 ARM Limited - * Copyright 2008 Cavium Networks - */ - -#ifndef __CNS3XXX_CORE_H -#define __CNS3XXX_CORE_H - -#include - -extern void cns3xxx_timer_init(void); - -#ifdef CONFIG_CACHE_L2X0 -void __init cns3xxx_l2x0_init(void); -#else -static inline void cns3xxx_l2x0_init(void) {} -#endif /* CONFIG_CACHE_L2X0 */ - -#ifdef CONFIG_PCI -extern void __init cns3xxx_pcie_init_late(void); -#else -static inline void __init cns3xxx_pcie_init_late(void) {} -#endif - -void __init cns3xxx_map_io(void); -void __init cns3xxx_init_irq(void); -void cns3xxx_power_off(void); -void cns3xxx_restart(enum reboot_mode, const char *); - -#endif /* __CNS3XXX_CORE_H */ diff --git a/arch/arm/mach-cns3xxx/devices.c b/arch/arm/mach-cns3xxx/devices.c deleted file mode 100644 index 0f1ba8a0377d..000000000000 --- a/arch/arm/mach-cns3xxx/devices.c +++ /dev/null @@ -1,108 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * CNS3xxx common devices - * - * Copyright 2008 Cavium Networks - * Scott Shu - * Copyright 2010 MontaVista Software, LLC. - * Anton Vorontsov - */ - -#include -#include -#include -#include -#include -#include "cns3xxx.h" -#include "pm.h" -#include "core.h" -#include "devices.h" - -/* - * AHCI - */ -static struct resource cns3xxx_ahci_resource[] = { - [0] = { - .start = CNS3XXX_SATA2_BASE, - .end = CNS3XXX_SATA2_BASE + CNS3XXX_SATA2_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_CNS3XXX_SATA, - .end = IRQ_CNS3XXX_SATA, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 cns3xxx_ahci_dmamask = DMA_BIT_MASK(32); - -static struct platform_device cns3xxx_ahci_pdev = { - .name = "ahci", - .id = 0, - .resource = cns3xxx_ahci_resource, - .num_resources = ARRAY_SIZE(cns3xxx_ahci_resource), - .dev = { - .dma_mask = &cns3xxx_ahci_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -void __init cns3xxx_ahci_init(void) -{ - u32 tmp; - - tmp = __raw_readl(MISC_SATA_POWER_MODE); - tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */ - tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */ - __raw_writel(tmp, MISC_SATA_POWER_MODE); - - /* Enable SATA PHY */ - cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0); - cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1); - - /* Enable SATA Clock */ - cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA); - - /* De-Asscer SATA Reset */ - cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA)); - - platform_device_register(&cns3xxx_ahci_pdev); -} - -/* - * SDHCI - */ -static struct resource cns3xxx_sdhci_resources[] = { - [0] = { - .start = CNS3XXX_SDIO_BASE, - .end = CNS3XXX_SDIO_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_CNS3XXX_SDIO, - .end = IRQ_CNS3XXX_SDIO, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device cns3xxx_sdhci_pdev = { - .name = "sdhci-cns3xxx", - .id = 0, - .num_resources = ARRAY_SIZE(cns3xxx_sdhci_resources), - .resource = cns3xxx_sdhci_resources, -}; - -void __init cns3xxx_sdhci_init(void) -{ - u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014); - u32 gpioa_pins = __raw_readl(gpioa); - - /* MMC/SD pins share with GPIOA */ - gpioa_pins |= 0x1fff0004; - __raw_writel(gpioa_pins, gpioa); - - cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO)); - cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO)); - - platform_device_register(&cns3xxx_sdhci_pdev); -} diff --git a/arch/arm/mach-cns3xxx/devices.h b/arch/arm/mach-cns3xxx/devices.h deleted file mode 100644 index ab16530d0116..000000000000 --- a/arch/arm/mach-cns3xxx/devices.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * CNS3xxx common devices - * - * Copyright 2008 Cavium Networks - * Scott Shu - * Copyright 2010 MontaVista Software, LLC. - * Anton Vorontsov - */ - -#ifndef __CNS3XXX_DEVICES_H_ -#define __CNS3XXX_DEVICES_H_ - -void __init cns3xxx_ahci_init(void); -void __init cns3xxx_sdhci_init(void); - -#endif /* __CNS3XXX_DEVICES_H_ */ diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c deleted file mode 100644 index e92fbd679dfb..000000000000 --- a/arch/arm/mach-cns3xxx/pcie.c +++ /dev/null @@ -1,290 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * PCI-E support for CNS3xxx - * - * Copyright 2008 Cavium Networks - * Richard Liu - * Copyright 2010 MontaVista Software, LLC. - * Anton Vorontsov - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "cns3xxx.h" -#include "core.h" - -struct cns3xxx_pcie { - void __iomem *host_regs; /* PCI config registers for host bridge */ - void __iomem *cfg0_regs; /* PCI Type 0 config registers */ - void __iomem *cfg1_regs; /* PCI Type 1 config registers */ - unsigned int irqs[2]; - struct resource res_io; - struct resource res_mem; - int port; - bool linked; -}; - -static struct cns3xxx_pcie *sysdata_to_cnspci(void *sysdata) -{ - struct pci_sys_data *root = sysdata; - - return root->private_data; -} - -static struct cns3xxx_pcie *pdev_to_cnspci(const struct pci_dev *dev) -{ - return sysdata_to_cnspci(dev->sysdata); -} - -static struct cns3xxx_pcie *pbus_to_cnspci(struct pci_bus *bus) -{ - return sysdata_to_cnspci(bus->sysdata); -} - -static void __iomem *cns3xxx_pci_map_bus(struct pci_bus *bus, - unsigned int devfn, int where) -{ - struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus); - int busno = bus->number; - int slot = PCI_SLOT(devfn); - void __iomem *base; - - /* If there is no link, just show the CNS PCI bridge. */ - if (!cnspci->linked && busno > 0) - return NULL; - - /* - * The CNS PCI bridge doesn't fit into the PCI hierarchy, though - * we still want to access it. - * We place the host bridge on bus 0, and the directly connected - * device on bus 1, slot 0. - */ - if (busno == 0) { /* internal PCIe bus, host bridge device */ - if (devfn == 0) /* device# and function# are ignored by hw */ - base = cnspci->host_regs; - else - return NULL; /* no such device */ - - } else if (busno == 1) { /* directly connected PCIe device */ - if (slot == 0) /* device# is ignored by hw */ - base = cnspci->cfg0_regs; - else - return NULL; /* no such device */ - } else /* remote PCI bus */ - base = cnspci->cfg1_regs + ((busno & 0xf) << 20); - - return base + where + (devfn << 12); -} - -static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 *val) -{ - int ret; - u32 mask = (0x1ull << (size * 8)) - 1; - int shift = (where % 4) * 8; - - ret = pci_generic_config_read(bus, devfn, where, size, val); - - if (ret == PCIBIOS_SUCCESSFUL && !bus->number && !devfn && - (where & 0xffc) == PCI_CLASS_REVISION) - /* - * RC's class is 0xb, but Linux PCI driver needs 0x604 - * for a PCIe bridge. So we must fixup the class code - * to 0x604 here. - */ - *val = ((((*val << shift) & 0xff) | (0x604 << 16)) >> shift) & mask; - - return ret; -} - -static int cns3xxx_pci_setup(int nr, struct pci_sys_data *sys) -{ - struct cns3xxx_pcie *cnspci = sysdata_to_cnspci(sys); - struct resource *res_io = &cnspci->res_io; - struct resource *res_mem = &cnspci->res_mem; - - BUG_ON(request_resource(&iomem_resource, res_io) || - request_resource(&iomem_resource, res_mem)); - - pci_add_resource_offset(&sys->resources, res_io, sys->io_offset); - pci_add_resource_offset(&sys->resources, res_mem, sys->mem_offset); - - return 1; -} - -static struct pci_ops cns3xxx_pcie_ops = { - .map_bus = cns3xxx_pci_map_bus, - .read = cns3xxx_pci_read_config, - .write = pci_generic_config_write, -}; - -static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev); - int irq = cnspci->irqs[!!dev->bus->number]; - - pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n", - pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn), - PCI_FUNC(dev->devfn), slot, pin, irq); - - return irq; -} - -static struct cns3xxx_pcie cns3xxx_pcie[] = { - [0] = { - .host_regs = (void __iomem *)CNS3XXX_PCIE0_HOST_BASE_VIRT, - .cfg0_regs = (void __iomem *)CNS3XXX_PCIE0_CFG0_BASE_VIRT, - .cfg1_regs = (void __iomem *)CNS3XXX_PCIE0_CFG1_BASE_VIRT, - .res_io = { - .name = "PCIe0 I/O space", - .start = CNS3XXX_PCIE0_IO_BASE, - .end = CNS3XXX_PCIE0_CFG0_BASE - 1, /* 16 MiB */ - .flags = IORESOURCE_IO, - }, - .res_mem = { - .name = "PCIe0 non-prefetchable", - .start = CNS3XXX_PCIE0_MEM_BASE, - .end = CNS3XXX_PCIE0_HOST_BASE - 1, /* 176 MiB */ - .flags = IORESOURCE_MEM, - }, - .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, }, - .port = 0, - }, - [1] = { - .host_regs = (void __iomem *)CNS3XXX_PCIE1_HOST_BASE_VIRT, - .cfg0_regs = (void __iomem *)CNS3XXX_PCIE1_CFG0_BASE_VIRT, - .cfg1_regs = (void __iomem *)CNS3XXX_PCIE1_CFG1_BASE_VIRT, - .res_io = { - .name = "PCIe1 I/O space", - .start = CNS3XXX_PCIE1_IO_BASE, - .end = CNS3XXX_PCIE1_CFG0_BASE - 1, /* 16 MiB */ - .flags = IORESOURCE_IO, - }, - .res_mem = { - .name = "PCIe1 non-prefetchable", - .start = CNS3XXX_PCIE1_MEM_BASE, - .end = CNS3XXX_PCIE1_HOST_BASE - 1, /* 176 MiB */ - .flags = IORESOURCE_MEM, - }, - .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, }, - .port = 1, - }, -}; - -static void __init cns3xxx_pcie_check_link(struct cns3xxx_pcie *cnspci) -{ - int port = cnspci->port; - u32 reg; - unsigned long time; - - reg = __raw_readl(MISC_PCIE_CTRL(port)); - /* - * Enable Application Request to 1, it will exit L1 automatically, - * but when chip back, it will use another clock, still can use 0x1. - */ - reg |= 0x3; - __raw_writel(reg, MISC_PCIE_CTRL(port)); - - pr_info("PCIe: Port[%d] Enable PCIe LTSSM\n", port); - pr_info("PCIe: Port[%d] Check data link layer...", port); - - time = jiffies; - while (1) { - reg = __raw_readl(MISC_PCIE_PM_DEBUG(port)); - if (reg & 0x1) { - pr_info("Link up.\n"); - cnspci->linked = 1; - break; - } else if (time_after(jiffies, time + 50)) { - pr_info("Device not found.\n"); - break; - } - } -} - -static void cns3xxx_write_config(struct cns3xxx_pcie *cnspci, - int where, int size, u32 val) -{ - void __iomem *base = cnspci->host_regs + (where & 0xffc); - u32 v; - u32 mask = (0x1ull << (size * 8)) - 1; - int shift = (where % 4) * 8; - - v = readl_relaxed(base); - - v &= ~(mask << shift); - v |= (val & mask) << shift; - - writel_relaxed(v, base); - readl_relaxed(base); -} - -static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci) -{ - u16 mem_base = cnspci->res_mem.start >> 16; - u16 mem_limit = cnspci->res_mem.end >> 16; - u16 io_base = cnspci->res_io.start >> 16; - u16 io_limit = cnspci->res_io.end >> 16; - - cns3xxx_write_config(cnspci, PCI_PRIMARY_BUS, 1, 0); - cns3xxx_write_config(cnspci, PCI_SECONDARY_BUS, 1, 1); - cns3xxx_write_config(cnspci, PCI_SUBORDINATE_BUS, 1, 1); - cns3xxx_write_config(cnspci, PCI_MEMORY_BASE, 2, mem_base); - cns3xxx_write_config(cnspci, PCI_MEMORY_LIMIT, 2, mem_limit); - cns3xxx_write_config(cnspci, PCI_IO_BASE_UPPER16, 2, io_base); - cns3xxx_write_config(cnspci, PCI_IO_LIMIT_UPPER16, 2, io_limit); - - if (!cnspci->linked) - return; - - /* Set Device Max_Read_Request_Size to 128 byte */ - pcie_bus_config = PCIE_BUS_PEER2PEER; - - /* Disable PCIe0 Interrupt Mask INTA to INTD */ - __raw_writel(~0x3FFF, MISC_PCIE_INT_MASK(cnspci->port)); -} - -static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr, - struct pt_regs *regs) -{ - if (fsr & (1 << 10)) - regs->ARM_pc += 4; - return 0; -} - -void __init cns3xxx_pcie_init_late(void) -{ - int i; - void *private_data; - struct hw_pci hw_pci = { - .nr_controllers = 1, - .ops = &cns3xxx_pcie_ops, - .setup = cns3xxx_pci_setup, - .map_irq = cns3xxx_pcie_map_irq, - .private_data = &private_data, - }; - - pcibios_min_io = 0; - pcibios_min_mem = 0; - - hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS, 0, - "imprecise external abort"); - - for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) { - cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i)); - cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i)); - cns3xxx_pcie_check_link(&cns3xxx_pcie[i]); - cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]); - private_data = &cns3xxx_pcie[i]; - pci_common_init(&hw_pci); - } - - pci_assign_unassigned_resources(); -} diff --git a/arch/arm/mach-cns3xxx/pm.c b/arch/arm/mach-cns3xxx/pm.c deleted file mode 100644 index 72e8a7ec7a38..000000000000 --- a/arch/arm/mach-cns3xxx/pm.c +++ /dev/null @@ -1,120 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2008 Cavium Networks - */ - -#include -#include -#include -#include -#include -#include "cns3xxx.h" -#include "pm.h" -#include "core.h" - -void cns3xxx_pwr_clk_en(unsigned int block) -{ - u32 reg = __raw_readl(PM_CLK_GATE_REG); - - reg |= (block & PM_CLK_GATE_REG_MASK); - __raw_writel(reg, PM_CLK_GATE_REG); -} -EXPORT_SYMBOL(cns3xxx_pwr_clk_en); - -void cns3xxx_pwr_clk_dis(unsigned int block) -{ - u32 reg = __raw_readl(PM_CLK_GATE_REG); - - reg &= ~(block & PM_CLK_GATE_REG_MASK); - __raw_writel(reg, PM_CLK_GATE_REG); -} -EXPORT_SYMBOL(cns3xxx_pwr_clk_dis); - -void cns3xxx_pwr_power_up(unsigned int block) -{ - u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG); - - reg &= ~(block & CNS3XXX_PWR_PLL_ALL); - __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG); - - /* Wait for 300us for the PLL output clock locked. */ - udelay(300); -}; -EXPORT_SYMBOL(cns3xxx_pwr_power_up); - -void cns3xxx_pwr_power_down(unsigned int block) -{ - u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG); - - /* write '1' to power down */ - reg |= (block & CNS3XXX_PWR_PLL_ALL); - __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG); -}; -EXPORT_SYMBOL(cns3xxx_pwr_power_down); - -static void cns3xxx_pwr_soft_rst_force(unsigned int block) -{ - u32 reg = __raw_readl(PM_SOFT_RST_REG); - - /* - * bit 0, 28, 29 => program low to reset, - * the other else program low and then high - */ - if (block & 0x30000001) { - reg &= ~(block & PM_SOFT_RST_REG_MASK); - } else { - reg &= ~(block & PM_SOFT_RST_REG_MASK); - __raw_writel(reg, PM_SOFT_RST_REG); - reg |= (block & PM_SOFT_RST_REG_MASK); - } - - __raw_writel(reg, PM_SOFT_RST_REG); -} - -void cns3xxx_pwr_soft_rst(unsigned int block) -{ - static unsigned int soft_reset; - - if (soft_reset & block) { - /* SPI/I2C/GPIO use the same block, reset once. */ - return; - } else { - soft_reset |= block; - } - cns3xxx_pwr_soft_rst_force(block); -} -EXPORT_SYMBOL(cns3xxx_pwr_soft_rst); - -void cns3xxx_restart(enum reboot_mode mode, const char *cmd) -{ - /* - * To reset, we hit the on-board reset register - * in the system FPGA. - */ - cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(GLOBAL)); -} - -/* - * cns3xxx_cpu_clock - return CPU/L2 clock - * aclk: cpu clock/2 - * hclk: cpu clock/4 - * pclk: cpu clock/8 - */ -int cns3xxx_cpu_clock(void) -{ - u32 reg = __raw_readl(PM_CLK_CTRL_REG); - int cpu; - int cpu_sel; - int div_sel; - - cpu_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf; - div_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3; - - cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel; - - return cpu; -} -EXPORT_SYMBOL(cns3xxx_cpu_clock); - -atomic_t usb_pwr_ref = ATOMIC_INIT(0); -EXPORT_SYMBOL(usb_pwr_ref); diff --git a/arch/arm/mach-cns3xxx/pm.h b/arch/arm/mach-cns3xxx/pm.h deleted file mode 100644 index 61b73e59f0ff..000000000000 --- a/arch/arm/mach-cns3xxx/pm.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2000 Deep Blue Solutions Ltd - * Copyright 2004 ARM Limited - * Copyright 2008 Cavium Networks - */ - -#ifndef __CNS3XXX_PM_H -#define __CNS3XXX_PM_H - -#include - -void cns3xxx_pwr_clk_en(unsigned int block); -void cns3xxx_pwr_clk_dis(unsigned int block); -void cns3xxx_pwr_power_up(unsigned int block); -void cns3xxx_pwr_power_down(unsigned int block); - -extern atomic_t usb_pwr_ref; - -#endif /* __CNS3XXX_PM_H */ -- cgit From ca2259c352519721a659239e187c1d3a375a8f96 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 29 Sep 2022 15:37:53 +0200 Subject: ARM: ep93xx: remove old board files These five board files were marked as unused a while ago, and nobody wanted to keep them around for longer, so remove them now. We still have the edb93xx, visision_ep9307 and ts72xx files, which can hopefully be converted to device tree in the future. Cc: Lennert Buytenhek Cc: Hubert Feurstein Acked-by: Alexander Sverdlin Signed-off-by: Arnd Bergmann --- arch/arm/boot/compressed/misc-ep93xx.h | 13 +-- arch/arm/mach-ep93xx/Kconfig | 63 ------------- arch/arm/mach-ep93xx/Makefile | 5 - arch/arm/mach-ep93xx/adssphere.c | 41 --------- arch/arm/mach-ep93xx/gesbc9312.c | 41 --------- arch/arm/mach-ep93xx/micro9.c | 125 ------------------------- arch/arm/mach-ep93xx/simone.c | 128 -------------------------- arch/arm/mach-ep93xx/snappercl15.c | 162 --------------------------------- 8 files changed, 1 insertion(+), 577 deletions(-) delete mode 100644 arch/arm/mach-ep93xx/adssphere.c delete mode 100644 arch/arm/mach-ep93xx/gesbc9312.c delete mode 100644 arch/arm/mach-ep93xx/micro9.c delete mode 100644 arch/arm/mach-ep93xx/simone.c delete mode 100644 arch/arm/mach-ep93xx/snappercl15.c (limited to 'arch/arm') diff --git a/arch/arm/boot/compressed/misc-ep93xx.h b/arch/arm/boot/compressed/misc-ep93xx.h index 3dc942589cba..65b4121d1490 100644 --- a/arch/arm/boot/compressed/misc-ep93xx.h +++ b/arch/arm/boot/compressed/misc-ep93xx.h @@ -57,8 +57,7 @@ static inline void ep93xx_decomp_setup(void) if (machine_is_ts72xx()) ts72xx_watchdog_disable(); - if (machine_is_adssphere() || - machine_is_edb9301() || + if (machine_is_edb9301() || machine_is_edb9302() || machine_is_edb9302a() || machine_is_edb9302a() || @@ -69,16 +68,6 @@ static inline void ep93xx_decomp_setup(void) machine_is_edb9315() || machine_is_edb9315a() || machine_is_edb9315a() || - machine_is_gesbc9312() || - machine_is_micro9() || - machine_is_micro9l() || - machine_is_micro9m() || - machine_is_micro9s() || - machine_is_micro9m() || - machine_is_micro9l() || - machine_is_micro9s() || - machine_is_sim_one() || - machine_is_snapper_cl15() || machine_is_ts72xx() || machine_is_bk3() || machine_is_vision_ep9307()) diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig index 2c40996a444b..703f3d232a60 100644 --- a/arch/arm/mach-ep93xx/Kconfig +++ b/arch/arm/mach-ep93xx/Kconfig @@ -25,13 +25,6 @@ config EP93XX_SOC_COMMON comment "EP93xx Platforms" -config MACH_ADSSPHERE - bool "Support ADS Sphere" - depends on UNUSED_BOARD_FILES - help - Say 'Y' here if you want your kernel to support the ADS - Sphere board. - config MACH_BK3 bool "Support Liebherr BK3.1" select MACH_TS72XX @@ -98,62 +91,6 @@ config MACH_EDB9315A Say 'Y' here if you want your kernel to support the Cirrus Logic EDB9315A Evaluation Board. -config MACH_GESBC9312 - bool "Support Glomation GESBC-9312-sx" - depends on UNUSED_BOARD_FILES - help - Say 'Y' here if you want your kernel to support the Glomation - GESBC-9312-sx board. - -config MACH_MICRO9 - bool - -config MACH_MICRO9H - bool "Support Contec Micro9-High" - select MACH_MICRO9 - depends on UNUSED_BOARD_FILES - help - Say 'Y' here if you want your kernel to support the - Contec Micro9-High board. - -config MACH_MICRO9M - bool "Support Contec Micro9-Mid" - select MACH_MICRO9 - depends on UNUSED_BOARD_FILES - help - Say 'Y' here if you want your kernel to support the - Contec Micro9-Mid board. - -config MACH_MICRO9L - bool "Support Contec Micro9-Lite" - select MACH_MICRO9 - depends on UNUSED_BOARD_FILES - help - Say 'Y' here if you want your kernel to support the - Contec Micro9-Lite board. - -config MACH_MICRO9S - bool "Support Contec Micro9-Slim" - select MACH_MICRO9 - depends on UNUSED_BOARD_FILES - help - Say 'Y' here if you want your kernel to support the - Contec Micro9-Slim board. - -config MACH_SIM_ONE - bool "Support Simplemachines Sim.One board" - depends on UNUSED_BOARD_FILES - help - Say 'Y' here if you want your kernel to support the - Simplemachines Sim.One board. - -config MACH_SNAPPER_CL15 - bool "Support Bluewater Systems Snapper CL15 Module" - depends on UNUSED_BOARD_FILES - help - Say 'Y' here if you want your kernel to support the Bluewater - Systems Snapper CL15 Module. - config MACH_TS72XX bool "Support Technologic Systems TS-72xx SBC" help diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile index cfad517fac46..62e37403df14 100644 --- a/arch/arm/mach-ep93xx/Makefile +++ b/arch/arm/mach-ep93xx/Makefile @@ -6,11 +6,6 @@ obj-y := core.o clock.o timer-ep93xx.o obj-$(CONFIG_EP93XX_DMA) += dma.o -obj-$(CONFIG_MACH_ADSSPHERE) += adssphere.o obj-$(CONFIG_MACH_EDB93XX) += edb93xx.o -obj-$(CONFIG_MACH_GESBC9312) += gesbc9312.o -obj-$(CONFIG_MACH_MICRO9) += micro9.o -obj-$(CONFIG_MACH_SIM_ONE) += simone.o -obj-$(CONFIG_MACH_SNAPPER_CL15) += snappercl15.o obj-$(CONFIG_MACH_TS72XX) += ts72xx.o obj-$(CONFIG_MACH_VISION_EP9307)+= vision_ep9307.o diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c deleted file mode 100644 index 0c48d3c5b8e7..000000000000 --- a/arch/arm/mach-ep93xx/adssphere.c +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-ep93xx/adssphere.c - * ADS Sphere support. - * - * Copyright (C) 2006 Lennert Buytenhek - */ - -#include -#include -#include -#include - -#include "hardware.h" - -#include -#include - -#include "soc.h" - -static struct ep93xx_eth_data __initdata adssphere_eth_data = { - .phy_id = 1, -}; - -static void __init adssphere_init_machine(void) -{ - ep93xx_init_devices(); - ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M); - ep93xx_register_eth(&adssphere_eth_data, 1); -} - -MACHINE_START(ADSSPHERE, "ADS Sphere board") - /* Maintainer: Lennert Buytenhek */ - .atag_offset = 0x100, - .nr_irqs = NR_EP93XX_IRQS, - .map_io = ep93xx_map_io, - .init_irq = ep93xx_init_irq, - .init_time = ep93xx_timer_init, - .init_machine = adssphere_init_machine, - .restart = ep93xx_restart, -MACHINE_END diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c deleted file mode 100644 index 0b7043e3e178..000000000000 --- a/arch/arm/mach-ep93xx/gesbc9312.c +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-ep93xx/gesbc9312.c - * Glomation GESBC-9312-sx support. - * - * Copyright (C) 2006 Lennert Buytenhek - */ - -#include -#include -#include -#include - -#include "hardware.h" - -#include -#include - -#include "soc.h" - -static struct ep93xx_eth_data __initdata gesbc9312_eth_data = { - .phy_id = 1, -}; - -static void __init gesbc9312_init_machine(void) -{ - ep93xx_init_devices(); - ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_8M); - ep93xx_register_eth(&gesbc9312_eth_data, 0); -} - -MACHINE_START(GESBC9312, "Glomation GESBC-9312-sx") - /* Maintainer: Lennert Buytenhek */ - .atag_offset = 0x100, - .nr_irqs = NR_EP93XX_IRQS, - .map_io = ep93xx_map_io, - .init_irq = ep93xx_init_irq, - .init_time = ep93xx_timer_init, - .init_machine = gesbc9312_init_machine, - .restart = ep93xx_restart, -MACHINE_END diff --git a/arch/arm/mach-ep93xx/micro9.c b/arch/arm/mach-ep93xx/micro9.c deleted file mode 100644 index c121c459aa17..000000000000 --- a/arch/arm/mach-ep93xx/micro9.c +++ /dev/null @@ -1,125 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-ep93xx/micro9.c - * - * Copyright (C) 2006 Contec Steuerungstechnik & Automation GmbH - * Manfred Gruber - * Copyright (C) 2009 Contec Steuerungstechnik & Automation GmbH - * Hubert Feurstein - */ - -#include -#include -#include -#include - -#include "hardware.h" - -#include -#include - -#include "soc.h" - -/************************************************************************* - * Micro9 NOR Flash - * - * Micro9-High has up to 64MB of 32-bit flash on CS1 - * Micro9-Mid has up to 64MB of either 32-bit or 16-bit flash on CS1 - * Micro9-Lite uses a separate MTD map driver for flash support - * Micro9-Slim has up to 64MB of either 32-bit or 16-bit flash on CS1 - *************************************************************************/ -static unsigned int __init micro9_detect_bootwidth(void) -{ - u32 v; - - /* Detect the bus width of the external flash memory */ - v = __raw_readl(EP93XX_SYSCON_SYSCFG); - if (v & EP93XX_SYSCON_SYSCFG_LCSN7) - return 4; /* 32-bit */ - else - return 2; /* 16-bit */ -} - -static void __init micro9_register_flash(void) -{ - unsigned int width; - - if (machine_is_micro9()) - width = 4; - else if (machine_is_micro9m() || machine_is_micro9s()) - width = micro9_detect_bootwidth(); - else - width = 0; - - if (width) - ep93xx_register_flash(width, EP93XX_CS1_PHYS_BASE, SZ_64M); -} - - -/************************************************************************* - * Micro9 Ethernet - *************************************************************************/ -static struct ep93xx_eth_data __initdata micro9_eth_data = { - .phy_id = 0x1f, -}; - - -static void __init micro9_init_machine(void) -{ - ep93xx_init_devices(); - ep93xx_register_eth(µ9_eth_data, 1); - micro9_register_flash(); -} - - -#ifdef CONFIG_MACH_MICRO9H -MACHINE_START(MICRO9, "Contec Micro9-High") - /* Maintainer: Hubert Feurstein */ - .atag_offset = 0x100, - .nr_irqs = NR_EP93XX_IRQS, - .map_io = ep93xx_map_io, - .init_irq = ep93xx_init_irq, - .init_time = ep93xx_timer_init, - .init_machine = micro9_init_machine, - .restart = ep93xx_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_MICRO9M -MACHINE_START(MICRO9M, "Contec Micro9-Mid") - /* Maintainer: Hubert Feurstein */ - .atag_offset = 0x100, - .nr_irqs = NR_EP93XX_IRQS, - .map_io = ep93xx_map_io, - .init_irq = ep93xx_init_irq, - .init_time = ep93xx_timer_init, - .init_machine = micro9_init_machine, - .restart = ep93xx_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_MICRO9L -MACHINE_START(MICRO9L, "Contec Micro9-Lite") - /* Maintainer: Hubert Feurstein */ - .atag_offset = 0x100, - .nr_irqs = NR_EP93XX_IRQS, - .map_io = ep93xx_map_io, - .init_irq = ep93xx_init_irq, - .init_time = ep93xx_timer_init, - .init_machine = micro9_init_machine, - .restart = ep93xx_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_MICRO9S -MACHINE_START(MICRO9S, "Contec Micro9-Slim") - /* Maintainer: Hubert Feurstein */ - .atag_offset = 0x100, - .nr_irqs = NR_EP93XX_IRQS, - .map_io = ep93xx_map_io, - .init_irq = ep93xx_init_irq, - .init_time = ep93xx_timer_init, - .init_machine = micro9_init_machine, - .restart = ep93xx_restart, -MACHINE_END -#endif diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c deleted file mode 100644 index 569e72413561..000000000000 --- a/arch/arm/mach-ep93xx/simone.c +++ /dev/null @@ -1,128 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-ep93xx/simone.c - * Simplemachines Sim.One support. - * - * Copyright (C) 2010 Ryan Mallon - * - * Based on the 2.6.24.7 support: - * Copyright (C) 2009 Simplemachines - * MMC support by Peter Ivanov , 2007 - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "hardware.h" -#include "gpio-ep93xx.h" - -#include -#include - -#include "soc.h" - -static struct ep93xx_eth_data __initdata simone_eth_data = { - .phy_id = 1, -}; - -static struct ep93xxfb_mach_info __initdata simone_fb_info = { - .flags = EP93XXFB_USE_SDCSN0 | EP93XXFB_PCLK_FALLING, -}; - -static struct mmc_spi_platform_data simone_mmc_spi_data = { - .detect_delay = 500, - .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, -}; - -static struct gpiod_lookup_table simone_mmc_spi_gpio_table = { - .dev_id = "mmc_spi.0", /* "mmc_spi" @ CS0 */ - .table = { - /* Card detect */ - GPIO_LOOKUP_IDX("A", 0, NULL, 0, GPIO_ACTIVE_LOW), - { }, - }, -}; - -static struct spi_board_info simone_spi_devices[] __initdata = { - { - .modalias = "mmc_spi", - .platform_data = &simone_mmc_spi_data, - /* - * We use 10 MHz even though the maximum is 3.7 MHz. The driver - * will limit it automatically to max. frequency. - */ - .max_speed_hz = 10 * 1000 * 1000, - .bus_num = 0, - .chip_select = 0, - .mode = SPI_MODE_3, - }, -}; - -/* - * Up to v1.3, the Sim.One used SFRMOUT as SD card chip select, but this goes - * low between multi-message command blocks. From v1.4, it uses a GPIO instead. - * v1.3 parts will still work, since the signal on SFRMOUT is automatic. - */ -static struct gpiod_lookup_table simone_spi_cs_gpio_table = { - .dev_id = "spi0", - .table = { - GPIO_LOOKUP("A", 1, "cs", GPIO_ACTIVE_LOW), - { }, - }, -}; - -static struct ep93xx_spi_info simone_spi_info __initdata = { - .use_dma = 1, -}; - -static struct i2c_board_info __initdata simone_i2c_board_info[] = { - { - I2C_BOARD_INFO("ds1337", 0x68), - }, -}; - -static struct platform_device simone_audio_device = { - .name = "simone-audio", - .id = -1, -}; - -static void __init simone_register_audio(void) -{ - ep93xx_register_ac97(); - platform_device_register(&simone_audio_device); -} - -static void __init simone_init_machine(void) -{ - ep93xx_init_devices(); - ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_8M); - ep93xx_register_eth(&simone_eth_data, 1); - ep93xx_register_fb(&simone_fb_info); - ep93xx_register_i2c(simone_i2c_board_info, - ARRAY_SIZE(simone_i2c_board_info)); - gpiod_add_lookup_table(&simone_mmc_spi_gpio_table); - gpiod_add_lookup_table(&simone_spi_cs_gpio_table); - ep93xx_register_spi(&simone_spi_info, simone_spi_devices, - ARRAY_SIZE(simone_spi_devices)); - simone_register_audio(); -} - -MACHINE_START(SIM_ONE, "Simplemachines Sim.One Board") - /* Maintainer: Ryan Mallon */ - .atag_offset = 0x100, - .nr_irqs = NR_EP93XX_IRQS, - .map_io = ep93xx_map_io, - .init_irq = ep93xx_init_irq, - .init_time = ep93xx_timer_init, - .init_machine = simone_init_machine, - .restart = ep93xx_restart, -MACHINE_END diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c deleted file mode 100644 index 1dfb725671b1..000000000000 --- a/arch/arm/mach-ep93xx/snappercl15.c +++ /dev/null @@ -1,162 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-ep93xx/snappercl15.c - * Bluewater Systems Snapper CL15 system module - * - * Copyright (C) 2009 Bluewater Systems Ltd - * Author: Ryan Mallon - * - * NAND code adapted from driver by: - * Andre Renaud - * James R. McKaskill - */ - -#include -#include -#include -#include -#include -#include - -#include - -#include "hardware.h" -#include -#include "gpio-ep93xx.h" - -#include -#include - -#include "soc.h" - -#define SNAPPERCL15_NAND_BASE (EP93XX_CS7_PHYS_BASE + SZ_16M) - -#define SNAPPERCL15_NAND_WPN (1 << 8) /* Write protect (active low) */ -#define SNAPPERCL15_NAND_ALE (1 << 9) /* Address latch */ -#define SNAPPERCL15_NAND_CLE (1 << 10) /* Command latch */ -#define SNAPPERCL15_NAND_CEN (1 << 11) /* Chip enable (active low) */ -#define SNAPPERCL15_NAND_RDY (1 << 14) /* Device ready */ - -#define NAND_CTRL_ADDR(chip) (chip->legacy.IO_ADDR_W + 0x40) - -static void snappercl15_nand_cmd_ctrl(struct nand_chip *chip, int cmd, - unsigned int ctrl) -{ - static u16 nand_state = SNAPPERCL15_NAND_WPN; - u16 set; - - if (ctrl & NAND_CTRL_CHANGE) { - set = SNAPPERCL15_NAND_CEN | SNAPPERCL15_NAND_WPN; - - if (ctrl & NAND_NCE) - set &= ~SNAPPERCL15_NAND_CEN; - if (ctrl & NAND_CLE) - set |= SNAPPERCL15_NAND_CLE; - if (ctrl & NAND_ALE) - set |= SNAPPERCL15_NAND_ALE; - - nand_state &= ~(SNAPPERCL15_NAND_CEN | - SNAPPERCL15_NAND_CLE | - SNAPPERCL15_NAND_ALE); - nand_state |= set; - __raw_writew(nand_state, NAND_CTRL_ADDR(chip)); - } - - if (cmd != NAND_CMD_NONE) - __raw_writew((cmd & 0xff) | nand_state, - chip->legacy.IO_ADDR_W); -} - -static int snappercl15_nand_dev_ready(struct nand_chip *chip) -{ - return !!(__raw_readw(NAND_CTRL_ADDR(chip)) & SNAPPERCL15_NAND_RDY); -} - -static struct mtd_partition snappercl15_nand_parts[] = { - { - .name = "Kernel", - .offset = 0, - .size = SZ_2M, - }, - { - .name = "Filesystem", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - }, -}; - -static struct platform_nand_data snappercl15_nand_data = { - .chip = { - .nr_chips = 1, - .partitions = snappercl15_nand_parts, - .nr_partitions = ARRAY_SIZE(snappercl15_nand_parts), - .chip_delay = 25, - }, - .ctrl = { - .dev_ready = snappercl15_nand_dev_ready, - .cmd_ctrl = snappercl15_nand_cmd_ctrl, - }, -}; - -static struct resource snappercl15_nand_resource[] = { - { - .start = SNAPPERCL15_NAND_BASE, - .end = SNAPPERCL15_NAND_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device snappercl15_nand_device = { - .name = "gen_nand", - .id = -1, - .dev.platform_data = &snappercl15_nand_data, - .resource = snappercl15_nand_resource, - .num_resources = ARRAY_SIZE(snappercl15_nand_resource), -}; - -static struct ep93xx_eth_data __initdata snappercl15_eth_data = { - .phy_id = 1, -}; - -static struct i2c_board_info __initdata snappercl15_i2c_data[] = { - { - /* Audio codec */ - I2C_BOARD_INFO("tlv320aic23", 0x1a), - }, -}; - -static struct ep93xxfb_mach_info __initdata snappercl15_fb_info = { -}; - -static struct platform_device snappercl15_audio_device = { - .name = "snappercl15-audio", - .id = -1, -}; - -static void __init snappercl15_register_audio(void) -{ - ep93xx_register_i2s(); - platform_device_register(&snappercl15_audio_device); -} - -static void __init snappercl15_init_machine(void) -{ - ep93xx_init_devices(); - ep93xx_register_eth(&snappercl15_eth_data, 1); - ep93xx_register_i2c(snappercl15_i2c_data, - ARRAY_SIZE(snappercl15_i2c_data)); - ep93xx_register_fb(&snappercl15_fb_info); - snappercl15_register_audio(); - platform_device_register(&snappercl15_nand_device); -} - -MACHINE_START(SNAPPER_CL15, "Bluewater Systems Snapper CL15") - /* Maintainer: Ryan Mallon */ - .atag_offset = 0x100, - .nr_irqs = NR_EP93XX_IRQS, - .map_io = ep93xx_map_io, - .init_irq = ep93xx_init_irq, - .init_time = ep93xx_timer_init, - .init_machine = snappercl15_init_machine, - .restart = ep93xx_restart, -MACHINE_END -- cgit From e2fe85aa6a6387c4babe4c191e50b7af8ee37faf Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 16 Sep 2022 11:58:07 +0200 Subject: ARM: mv78xx0: un-deprecate Terastation WXL This board is still being worked on by the Debian-on-Buffalo project, so let's leave it in the tree for now. Link: https://github.com/1000001101000/Debian_on_Buffalo Cc: Andrew Lunn Cc: Sebastian Hesselbarth Cc: Gregory Clement Signed-off-by: Arnd Bergmann --- arch/arm/configs/mv78xx0_defconfig | 1 - arch/arm/mach-mv78xx0/Kconfig | 4 +++- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/mv78xx0_defconfig b/arch/arm/configs/mv78xx0_defconfig index 877c5150a987..f02f29d3fecb 100644 --- a/arch/arm/configs/mv78xx0_defconfig +++ b/arch/arm/configs/mv78xx0_defconfig @@ -17,7 +17,6 @@ CONFIG_MACH_TERASTATION_WXL=y CONFIG_AEABI=y CONFIG_HIGHMEM=y CONFIG_FPE_NWFPE=y -CONFIG_UNUSED_BOARD_FILES=y CONFIG_VFP=y CONFIG_KPROBES=y CONFIG_MODULES=y diff --git a/arch/arm/mach-mv78xx0/Kconfig b/arch/arm/mach-mv78xx0/Kconfig index da92f94494cc..0464b732ead4 100644 --- a/arch/arm/mach-mv78xx0/Kconfig +++ b/arch/arm/mach-mv78xx0/Kconfig @@ -3,7 +3,7 @@ menuconfig ARCH_MV78XX0 bool "Marvell MV78xx0" depends on ARCH_MULTI_V5 depends on CPU_LITTLE_ENDIAN - depends on ATAGS && UNUSED_BOARD_FILES + depends on ATAGS select CPU_FEROCEON select GPIOLIB select MVEBU_MBUS @@ -17,12 +17,14 @@ if ARCH_MV78XX0 config MACH_DB78X00_BP bool "Marvell DB-78x00-BP Development Board" + depends on UNUSED_BOARD_FILES help Say 'Y' here if you want your kernel to support the Marvell DB-78x00-BP Development Board. config MACH_RD78X00_MASA bool "Marvell RD-78x00-mASA Reference Design" + depends on UNUSED_BOARD_FILES help Say 'Y' here if you want your kernel to support the Marvell RD-78x00-mASA Reference Design. -- cgit From c09846fc1ff4ced5c55840fb7f171ebc6e5478e4 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 29 Sep 2022 15:36:58 +0200 Subject: ARM: orion: remove unused board files As planned earlier, all board support that was marked unused can be removed now after nobody explicitly asked for these to be kept. In particular, all of the reference designs get removed now, as these are not commonly used productively any more. Also, the machines that were not supported by Debian or the Debian_on_Buffalo group because of limitations with RAM size are gone. Cc: Lennert Buytenhek Cc: Nicolas Pitre Cc: Imre Kaloz Signed-off-by: Arnd Bergmann --- arch/arm/configs/mv78xx0_defconfig | 2 - arch/arm/mach-dove/Kconfig | 8 - arch/arm/mach-dove/Makefile | 1 - arch/arm/mach-dove/dove-db-setup.c | 101 ------- arch/arm/mach-mv78xx0/Kconfig | 14 - arch/arm/mach-mv78xx0/Makefile | 2 - arch/arm/mach-mv78xx0/db78x00-bp-setup.c | 101 ------- arch/arm/mach-mv78xx0/rd78x00-masa-setup.c | 86 ------ arch/arm/mach-orion5x/Kconfig | 59 ----- arch/arm/mach-orion5x/Makefile | 8 - arch/arm/mach-orion5x/db88f5281-setup.c | 376 --------------------------- arch/arm/mach-orion5x/ls_hgl-setup.c | 275 -------------------- arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c | 172 ------------ arch/arm/mach-orion5x/rd88f5181l-ge-setup.c | 183 ------------- arch/arm/mach-orion5x/rd88f5182-setup.c | 288 -------------------- arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c | 120 --------- arch/arm/mach-orion5x/wnr854t-setup.c | 175 ------------- arch/arm/mach-orion5x/wrt350n-v2-setup.c | 263 ------------------- 18 files changed, 2234 deletions(-) delete mode 100644 arch/arm/mach-dove/dove-db-setup.c delete mode 100644 arch/arm/mach-mv78xx0/db78x00-bp-setup.c delete mode 100644 arch/arm/mach-mv78xx0/rd78x00-masa-setup.c delete mode 100644 arch/arm/mach-orion5x/db88f5281-setup.c delete mode 100644 arch/arm/mach-orion5x/ls_hgl-setup.c delete mode 100644 arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c delete mode 100644 arch/arm/mach-orion5x/rd88f5181l-ge-setup.c delete mode 100644 arch/arm/mach-orion5x/rd88f5182-setup.c delete mode 100644 arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c delete mode 100644 arch/arm/mach-orion5x/wnr854t-setup.c delete mode 100644 arch/arm/mach-orion5x/wrt350n-v2-setup.c (limited to 'arch/arm') diff --git a/arch/arm/configs/mv78xx0_defconfig b/arch/arm/configs/mv78xx0_defconfig index f02f29d3fecb..3a1088079514 100644 --- a/arch/arm/configs/mv78xx0_defconfig +++ b/arch/arm/configs/mv78xx0_defconfig @@ -11,8 +11,6 @@ CONFIG_ARCH_MULTI_V5=y # CONFIG_ARCH_MULTI_V6 is not set # CONFIG_ARCH_MULTI_V7 is not set CONFIG_ARCH_MV78XX0=y -CONFIG_MACH_DB78X00_BP=y -CONFIG_MACH_RD78X00_MASA=y CONFIG_MACH_TERASTATION_WXL=y CONFIG_AEABI=y CONFIG_HIGHMEM=y diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig index 2252f465cafd..996888ffcfe7 100644 --- a/arch/arm/mach-dove/Kconfig +++ b/arch/arm/mach-dove/Kconfig @@ -18,14 +18,6 @@ if ARCH_DOVE config DOVE_LEGACY bool -config MACH_DOVE_DB - bool "Marvell DB-MV88AP510 Development Board" - select DOVE_LEGACY - select I2C_BOARDINFO if I2C - help - Say 'Y' here if you want your kernel to support the - Marvell DB-MV88AP510 Development Board. - config MACH_CM_A510 bool "CompuLab CM-A510 Board" select DOVE_LEGACY diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile index da373a5768ba..0d31390be069 100644 --- a/arch/arm/mach-dove/Makefile +++ b/arch/arm/mach-dove/Makefile @@ -4,5 +4,4 @@ ccflags-y := -I$(srctree)/arch/arm/plat-orion/include obj-y += common.o obj-$(CONFIG_DOVE_LEGACY) += irq.o mpp.o obj-$(CONFIG_PCI) += pcie.o -obj-$(CONFIG_MACH_DOVE_DB) += dove-db-setup.o obj-$(CONFIG_MACH_CM_A510) += cm-a510.o diff --git a/arch/arm/mach-dove/dove-db-setup.c b/arch/arm/mach-dove/dove-db-setup.c deleted file mode 100644 index d5bf54040577..000000000000 --- a/arch/arm/mach-dove/dove-db-setup.c +++ /dev/null @@ -1,101 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/mach-dove/dove-db-setup.c - * - * Marvell DB-MV88AP510-BP Development Board Setup - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "dove.h" -#include "common.h" - -static struct mv643xx_eth_platform_data dove_db_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT, -}; - -static struct mv_sata_platform_data dove_db_sata_data = { - .n_ports = 1, -}; - -/***************************************************************************** - * SPI Devices: - * SPI0: 4M Flash ST-M25P32-VMF6P - ****************************************************************************/ -static const struct flash_platform_data dove_db_spi_flash_data = { - .type = "m25p64", -}; - -static struct spi_board_info __initdata dove_db_spi_flash_info[] = { - { - .modalias = "m25p80", - .platform_data = &dove_db_spi_flash_data, - .irq = -1, - .max_speed_hz = 20000000, - .bus_num = 0, - .chip_select = 0, - }, -}; - -/***************************************************************************** - * PCI - ****************************************************************************/ -static int __init dove_db_pci_init(void) -{ - if (machine_is_dove_db()) - dove_pcie_init(1, 1); - - return 0; -} - -subsys_initcall(dove_db_pci_init); - -/***************************************************************************** - * Board Init - ****************************************************************************/ -static void __init dove_db_init(void) -{ - /* - * Basic Dove setup. Needs to be called early. - */ - dove_init(); - - dove_ge00_init(&dove_db_ge00_data); - dove_ehci0_init(); - dove_ehci1_init(); - dove_sata_init(&dove_db_sata_data); - dove_sdio0_init(); - dove_sdio1_init(); - dove_spi0_init(); - dove_spi1_init(); - dove_uart0_init(); - dove_uart1_init(); - dove_i2c_init(); - spi_register_board_info(dove_db_spi_flash_info, - ARRAY_SIZE(dove_db_spi_flash_info)); -} - -MACHINE_START(DOVE_DB, "Marvell DB-MV88AP510-BP Development Board") - .atag_offset = 0x100, - .nr_irqs = DOVE_NR_IRQS, - .init_machine = dove_db_init, - .map_io = dove_map_io, - .init_early = dove_init_early, - .init_irq = dove_init_irq, - .init_time = dove_timer_init, - .restart = dove_restart, -MACHINE_END diff --git a/arch/arm/mach-mv78xx0/Kconfig b/arch/arm/mach-mv78xx0/Kconfig index 0464b732ead4..9de3bbc09c3a 100644 --- a/arch/arm/mach-mv78xx0/Kconfig +++ b/arch/arm/mach-mv78xx0/Kconfig @@ -15,20 +15,6 @@ menuconfig ARCH_MV78XX0 if ARCH_MV78XX0 -config MACH_DB78X00_BP - bool "Marvell DB-78x00-BP Development Board" - depends on UNUSED_BOARD_FILES - help - Say 'Y' here if you want your kernel to support the - Marvell DB-78x00-BP Development Board. - -config MACH_RD78X00_MASA - bool "Marvell RD-78x00-mASA Reference Design" - depends on UNUSED_BOARD_FILES - help - Say 'Y' here if you want your kernel to support the - Marvell RD-78x00-mASA Reference Design. - config MACH_TERASTATION_WXL bool "Buffalo WLX (Terastation Duo) NAS" help diff --git a/arch/arm/mach-mv78xx0/Makefile b/arch/arm/mach-mv78xx0/Makefile index 50aff70065f2..ddee6ae501bb 100644 --- a/arch/arm/mach-mv78xx0/Makefile +++ b/arch/arm/mach-mv78xx0/Makefile @@ -2,6 +2,4 @@ ccflags-y := -I$(srctree)/arch/arm/plat-orion/include obj-y += common.o mpp.o irq.o pcie.o -obj-$(CONFIG_MACH_DB78X00_BP) += db78x00-bp-setup.o -obj-$(CONFIG_MACH_RD78X00_MASA) += rd78x00-masa-setup.o obj-$(CONFIG_MACH_TERASTATION_WXL) += buffalo-wxl-setup.o diff --git a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c deleted file mode 100644 index da633a33a0c1..000000000000 --- a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c +++ /dev/null @@ -1,101 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/mach-mv78xx0/db78x00-bp-setup.c - * - * Marvell DB-78x00-BP Development Board Setup - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "mv78xx0.h" -#include "common.h" - -static struct mv643xx_eth_platform_data db78x00_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(8), -}; - -static struct mv643xx_eth_platform_data db78x00_ge01_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(9), -}; - -static struct mv643xx_eth_platform_data db78x00_ge10_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(10), -}; - -static struct mv643xx_eth_platform_data db78x00_ge11_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(11), -}; - -static struct mv_sata_platform_data db78x00_sata_data = { - .n_ports = 2, -}; - -static struct i2c_board_info __initdata db78x00_i2c_rtc = { - I2C_BOARD_INFO("ds1338", 0x68), -}; - - -static void __init db78x00_init(void) -{ - /* - * Basic MV78xx0 setup. Needs to be called early. - */ - mv78xx0_init(); - - /* - * Partition on-chip peripherals between the two CPU cores. - */ - if (mv78xx0_core_index() == 0) { - mv78xx0_ehci0_init(); - mv78xx0_ehci1_init(); - mv78xx0_ehci2_init(); - mv78xx0_ge00_init(&db78x00_ge00_data); - mv78xx0_ge01_init(&db78x00_ge01_data); - mv78xx0_ge10_init(&db78x00_ge10_data); - mv78xx0_ge11_init(&db78x00_ge11_data); - mv78xx0_sata_init(&db78x00_sata_data); - mv78xx0_uart0_init(); - mv78xx0_uart2_init(); - mv78xx0_i2c_init(); - i2c_register_board_info(0, &db78x00_i2c_rtc, 1); - } else { - mv78xx0_uart1_init(); - mv78xx0_uart3_init(); - } -} - -static int __init db78x00_pci_init(void) -{ - if (machine_is_db78x00_bp()) { - /* - * Assign the x16 PCIe slot on the board to CPU core - * #0, and let CPU core #1 have the four x1 slots. - */ - if (mv78xx0_core_index() == 0) - mv78xx0_pcie_init(0, 1); - else - mv78xx0_pcie_init(1, 0); - } - - return 0; -} -subsys_initcall(db78x00_pci_init); - -MACHINE_START(DB78X00_BP, "Marvell DB-78x00-BP Development Board") - /* Maintainer: Lennert Buytenhek */ - .atag_offset = 0x100, - .nr_irqs = MV78XX0_NR_IRQS, - .init_machine = db78x00_init, - .map_io = mv78xx0_map_io, - .init_early = mv78xx0_init_early, - .init_irq = mv78xx0_init_irq, - .init_time = mv78xx0_timer_init, - .restart = mv78xx0_restart, -MACHINE_END diff --git a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c deleted file mode 100644 index 80ca8b1a81de..000000000000 --- a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c +++ /dev/null @@ -1,86 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/mach-mv78x00/rd78x00-masa-setup.c - * - * Marvell RD-78x00-mASA Development Board Setup - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "mv78xx0.h" -#include "common.h" - -static struct mv643xx_eth_platform_data rd78x00_masa_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(8), -}; - -static struct mv643xx_eth_platform_data rd78x00_masa_ge01_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(9), -}; - -static struct mv643xx_eth_platform_data rd78x00_masa_ge10_data = { -}; - -static struct mv643xx_eth_platform_data rd78x00_masa_ge11_data = { -}; - -static struct mv_sata_platform_data rd78x00_masa_sata_data = { - .n_ports = 2, -}; - -static void __init rd78x00_masa_init(void) -{ - /* - * Basic MV78x00 setup. Needs to be called early. - */ - mv78xx0_init(); - - /* - * Partition on-chip peripherals between the two CPU cores. - */ - if (mv78xx0_core_index() == 0) { - mv78xx0_ehci0_init(); - mv78xx0_ehci1_init(); - mv78xx0_ge00_init(&rd78x00_masa_ge00_data); - mv78xx0_ge10_init(&rd78x00_masa_ge10_data); - mv78xx0_sata_init(&rd78x00_masa_sata_data); - mv78xx0_uart0_init(); - mv78xx0_uart2_init(); - } else { - mv78xx0_ehci2_init(); - mv78xx0_ge01_init(&rd78x00_masa_ge01_data); - mv78xx0_ge11_init(&rd78x00_masa_ge11_data); - mv78xx0_uart1_init(); - mv78xx0_uart3_init(); - } -} - -static int __init rd78x00_pci_init(void) -{ - /* - * Assign all PCIe devices to CPU core #0. - */ - if (machine_is_rd78x00_masa() && mv78xx0_core_index() == 0) - mv78xx0_pcie_init(1, 1); - - return 0; -} -subsys_initcall(rd78x00_pci_init); - -MACHINE_START(RD78X00_MASA, "Marvell RD-78x00-MASA Development Board") - /* Maintainer: Lennert Buytenhek */ - .atag_offset = 0x100, - .nr_irqs = MV78XX0_NR_IRQS, - .init_machine = rd78x00_masa_init, - .map_io = mv78xx0_map_io, - .init_early = mv78xx0_init_early, - .init_irq = mv78xx0_init_irq, - .init_time = mv78xx0_timer_init, - .restart = mv78xx0_restart, -MACHINE_END diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig index 0044b2823710..ee449ca032d2 100644 --- a/arch/arm/mach-orion5x/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig @@ -28,22 +28,6 @@ config ARCH_ORION5X_DT Say 'Y' here if you want your kernel to support the Marvell Orion5x using flattened device tree. -config MACH_DB88F5281 - bool "Marvell Orion-2 Development Board" - select I2C_BOARDINFO if I2C - depends on ATAGS && UNUSED_BOARD_FILES - help - Say 'Y' here if you want your kernel to support the - Marvell Orion-2 (88F5281) Development Board - -config MACH_RD88F5182 - bool "Marvell Orion-NAS Reference Design" - select I2C_BOARDINFO if I2C - depends on ATAGS && UNUSED_BOARD_FILES - help - Say 'Y' here if you want your kernel to support the - Marvell Orion-NAS (88F5182) RD2 - config MACH_RD88F5182_DT bool "Marvell Orion-NAS Reference Design (Flattened Device Tree)" select ARCH_ORION5X_DT @@ -98,14 +82,6 @@ config MACH_LINKSTATION_MINI Say 'Y' here if you want your kernel to support the Buffalo Linkstation Mini (LS-WSGL) platform. -config MACH_LINKSTATION_LS_HGL - bool "Buffalo Linkstation LS-HGL" - depends on ATAGS && UNUSED_BOARD_FILES - select I2C_BOARDINFO if I2C - help - Say 'Y' here if you want your kernel to support the - Buffalo Linkstation LS-HGL platform. - config MACH_TS409 bool "QNAP TS-409" depends on ATAGS @@ -113,13 +89,6 @@ config MACH_TS409 Say 'Y' here if you want your kernel to support the QNAP TS-409 platform. -config MACH_WRT350N_V2 - bool "Linksys WRT350N v2" - depends on ATAGS && UNUSED_BOARD_FILES - help - Say 'Y' here if you want your kernel to support the - Linksys WRT350N v2 platform. - config MACH_TS78XX bool "Technologic Systems TS-78xx" depends on ATAGS @@ -156,32 +125,4 @@ config MACH_MSS2_DT Say 'Y' here if you want your kernel to support the Maxtor Shared Storage II platform. -config MACH_WNR854T - bool "Netgear WNR854T" - depends on ATAGS && UNUSED_BOARD_FILES - help - Say 'Y' here if you want your kernel to support the - Netgear WNR854T platform. - -config MACH_RD88F5181L_GE - bool "Marvell Orion-VoIP GE Reference Design" - depends on ATAGS && UNUSED_BOARD_FILES - help - Say 'Y' here if you want your kernel to support the - Marvell Orion-VoIP GE (88F5181L) RD. - -config MACH_RD88F5181L_FXO - bool "Marvell Orion-VoIP FXO Reference Design" - depends on ATAGS && UNUSED_BOARD_FILES - help - Say 'Y' here if you want your kernel to support the - Marvell Orion-VoIP FXO (88F5181L) RD. - -config MACH_RD88F6183AP_GE - bool "Marvell Orion-1-90 AP GE Reference Design" - depends on ATAGS && UNUSED_BOARD_FILES - help - Say 'Y' here if you want your kernel to support the - Marvell Orion-1-90 (88F6183) AP GE RD. - endif diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile index 572c3520f7fe..6f54d7fef27a 100644 --- a/arch/arm/mach-orion5x/Makefile +++ b/arch/arm/mach-orion5x/Makefile @@ -2,23 +2,15 @@ ccflags-y := -I$(srctree)/arch/arm/plat-orion/include obj-y += common.o pci.o irq.o mpp.o -obj-$(CONFIG_MACH_DB88F5281) += db88f5281-setup.o -obj-$(CONFIG_MACH_RD88F5182) += rd88f5182-setup.o obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o obj-$(CONFIG_MACH_TERASTATION_PRO2) += terastation_pro2-setup.o obj-$(CONFIG_MACH_LINKSTATION_PRO) += kurobox_pro-setup.o -obj-$(CONFIG_MACH_LINKSTATION_LS_HGL) += ls_hgl-setup.o obj-$(CONFIG_MACH_DNS323) += dns323-setup.o obj-$(CONFIG_MACH_TS209) += ts209-setup.o tsx09-common.o obj-$(CONFIG_MACH_TS409) += ts409-setup.o tsx09-common.o -obj-$(CONFIG_MACH_WRT350N_V2) += wrt350n-v2-setup.o obj-$(CONFIG_MACH_TS78XX) += ts78xx-setup.o obj-$(CONFIG_MACH_MV2120) += mv2120-setup.o obj-$(CONFIG_MACH_NET2BIG) += net2big-setup.o -obj-$(CONFIG_MACH_WNR854T) += wnr854t-setup.o -obj-$(CONFIG_MACH_RD88F5181L_GE) += rd88f5181l-ge-setup.o -obj-$(CONFIG_MACH_RD88F5181L_FXO) += rd88f5181l-fxo-setup.o -obj-$(CONFIG_MACH_RD88F6183AP_GE) += rd88f6183ap-ge-setup.o obj-$(CONFIG_ARCH_ORION5X_DT) += board-dt.o obj-$(CONFIG_MACH_D2NET_DT) += board-d2net.o diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c deleted file mode 100644 index fe1a4cef1ba2..000000000000 --- a/arch/arm/mach-orion5x/db88f5281-setup.c +++ /dev/null @@ -1,376 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/mach-orion5x/db88f5281-setup.c - * - * Marvell Orion-2 Development Board Setup - * - * Maintainer: Tzachi Perelstein - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "common.h" -#include "mpp.h" -#include "orion5x.h" - -/***************************************************************************** - * DB-88F5281 on board devices - ****************************************************************************/ - -/* - * 512K NOR flash Device bus boot chip select - */ - -#define DB88F5281_NOR_BOOT_BASE 0xf4000000 -#define DB88F5281_NOR_BOOT_SIZE SZ_512K - -/* - * 7-Segment on Device bus chip select 0 - */ - -#define DB88F5281_7SEG_BASE 0xfa000000 -#define DB88F5281_7SEG_SIZE SZ_1K - -/* - * 32M NOR flash on Device bus chip select 1 - */ - -#define DB88F5281_NOR_BASE 0xfc000000 -#define DB88F5281_NOR_SIZE SZ_32M - -/* - * 32M NAND flash on Device bus chip select 2 - */ - -#define DB88F5281_NAND_BASE 0xfa800000 -#define DB88F5281_NAND_SIZE SZ_1K - -/* - * PCI - */ - -#define DB88F5281_PCI_SLOT0_OFFS 7 -#define DB88F5281_PCI_SLOT0_IRQ_PIN 12 -#define DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN 13 - -/***************************************************************************** - * 512M NOR Flash on Device bus Boot CS - ****************************************************************************/ - -static struct physmap_flash_data db88f5281_boot_flash_data = { - .width = 1, /* 8 bit bus width */ -}; - -static struct resource db88f5281_boot_flash_resource = { - .flags = IORESOURCE_MEM, - .start = DB88F5281_NOR_BOOT_BASE, - .end = DB88F5281_NOR_BOOT_BASE + DB88F5281_NOR_BOOT_SIZE - 1, -}; - -static struct platform_device db88f5281_boot_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &db88f5281_boot_flash_data, - }, - .num_resources = 1, - .resource = &db88f5281_boot_flash_resource, -}; - -/***************************************************************************** - * 32M NOR Flash on Device bus CS1 - ****************************************************************************/ - -static struct physmap_flash_data db88f5281_nor_flash_data = { - .width = 4, /* 32 bit bus width */ -}; - -static struct resource db88f5281_nor_flash_resource = { - .flags = IORESOURCE_MEM, - .start = DB88F5281_NOR_BASE, - .end = DB88F5281_NOR_BASE + DB88F5281_NOR_SIZE - 1, -}; - -static struct platform_device db88f5281_nor_flash = { - .name = "physmap-flash", - .id = 1, - .dev = { - .platform_data = &db88f5281_nor_flash_data, - }, - .num_resources = 1, - .resource = &db88f5281_nor_flash_resource, -}; - -/***************************************************************************** - * 32M NAND Flash on Device bus CS2 - ****************************************************************************/ - -static struct mtd_partition db88f5281_nand_parts[] = { - { - .name = "kernel", - .offset = 0, - .size = SZ_2M, - }, { - .name = "root", - .offset = SZ_2M, - .size = (SZ_16M - SZ_2M), - }, { - .name = "user", - .offset = SZ_16M, - .size = SZ_8M, - }, { - .name = "recovery", - .offset = (SZ_16M + SZ_8M), - .size = SZ_8M, - }, -}; - -static struct resource db88f5281_nand_resource = { - .flags = IORESOURCE_MEM, - .start = DB88F5281_NAND_BASE, - .end = DB88F5281_NAND_BASE + DB88F5281_NAND_SIZE - 1, -}; - -static struct orion_nand_data db88f5281_nand_data = { - .parts = db88f5281_nand_parts, - .nr_parts = ARRAY_SIZE(db88f5281_nand_parts), - .cle = 0, - .ale = 1, - .width = 8, -}; - -static struct platform_device db88f5281_nand_flash = { - .name = "orion_nand", - .id = -1, - .dev = { - .platform_data = &db88f5281_nand_data, - }, - .resource = &db88f5281_nand_resource, - .num_resources = 1, -}; - -/***************************************************************************** - * 7-Segment on Device bus CS0 - * Dummy counter every 2 sec - ****************************************************************************/ - -static void __iomem *db88f5281_7seg; -static struct timer_list db88f5281_timer; - -static void db88f5281_7seg_event(struct timer_list *unused) -{ - static int count = 0; - writel(0, db88f5281_7seg + (count << 4)); - count = (count + 1) & 7; - mod_timer(&db88f5281_timer, jiffies + 2 * HZ); -} - -static int __init db88f5281_7seg_init(void) -{ - if (machine_is_db88f5281()) { - db88f5281_7seg = ioremap(DB88F5281_7SEG_BASE, - DB88F5281_7SEG_SIZE); - if (!db88f5281_7seg) { - printk(KERN_ERR "Failed to ioremap db88f5281_7seg\n"); - return -EIO; - } - timer_setup(&db88f5281_timer, db88f5281_7seg_event, 0); - mod_timer(&db88f5281_timer, jiffies + 2 * HZ); - } - - return 0; -} - -__initcall(db88f5281_7seg_init); - -/***************************************************************************** - * PCI - ****************************************************************************/ - -static void __init db88f5281_pci_preinit(void) -{ - int pin; - - /* - * Configure PCI GPIO IRQ pins - */ - pin = DB88F5281_PCI_SLOT0_IRQ_PIN; - if (gpio_request(pin, "PCI Int1") == 0) { - if (gpio_direction_input(pin) == 0) { - irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); - } else { - printk(KERN_ERR "db88f5281_pci_preinit failed to " - "set_irq_type pin %d\n", pin); - gpio_free(pin); - } - } else { - printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin); - } - - pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN; - if (gpio_request(pin, "PCI Int2") == 0) { - if (gpio_direction_input(pin) == 0) { - irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); - } else { - printk(KERN_ERR "db88f5281_pci_preinit failed " - "to set_irq_type pin %d\n", pin); - gpio_free(pin); - } - } else { - printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin); - } -} - -static int __init db88f5281_pci_map_irq(const struct pci_dev *dev, u8 slot, - u8 pin) -{ - int irq; - - /* - * Check for devices with hard-wired IRQs. - */ - irq = orion5x_pci_map_irq(dev, slot, pin); - if (irq != -1) - return irq; - - /* - * PCI IRQs are connected via GPIOs. - */ - switch (slot - DB88F5281_PCI_SLOT0_OFFS) { - case 0: - return gpio_to_irq(DB88F5281_PCI_SLOT0_IRQ_PIN); - case 1: - case 2: - return gpio_to_irq(DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN); - default: - return -1; - } -} - -static struct hw_pci db88f5281_pci __initdata = { - .nr_controllers = 2, - .preinit = db88f5281_pci_preinit, - .setup = orion5x_pci_sys_setup, - .scan = orion5x_pci_sys_scan_bus, - .map_irq = db88f5281_pci_map_irq, -}; - -static int __init db88f5281_pci_init(void) -{ - if (machine_is_db88f5281()) - pci_common_init(&db88f5281_pci); - - return 0; -} - -subsys_initcall(db88f5281_pci_init); - -/***************************************************************************** - * Ethernet - ****************************************************************************/ -static struct mv643xx_eth_platform_data db88f5281_eth_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(8), -}; - -/***************************************************************************** - * RTC DS1339 on I2C bus - ****************************************************************************/ -static struct i2c_board_info __initdata db88f5281_i2c_rtc = { - I2C_BOARD_INFO("ds1339", 0x68), -}; - -/***************************************************************************** - * General Setup - ****************************************************************************/ -static unsigned int db88f5281_mpp_modes[] __initdata = { - MPP0_GPIO, /* USB Over Current */ - MPP1_GPIO, /* USB Vbat input */ - MPP2_PCI_ARB, /* PCI_REQn[2] */ - MPP3_PCI_ARB, /* PCI_GNTn[2] */ - MPP4_PCI_ARB, /* PCI_REQn[3] */ - MPP5_PCI_ARB, /* PCI_GNTn[3] */ - MPP6_GPIO, /* JP0, CON17.2 */ - MPP7_GPIO, /* JP1, CON17.1 */ - MPP8_GPIO, /* JP2, CON11.2 */ - MPP9_GPIO, /* JP3, CON11.3 */ - MPP10_GPIO, /* RTC int */ - MPP11_GPIO, /* Baud Rate Generator */ - MPP12_GPIO, /* PCI int 1 */ - MPP13_GPIO, /* PCI int 2 */ - MPP14_NAND, /* NAND_REn[2] */ - MPP15_NAND, /* NAND_WEn[2] */ - MPP16_UART, /* UART1_RX */ - MPP17_UART, /* UART1_TX */ - MPP18_UART, /* UART1_CTSn */ - MPP19_UART, /* UART1_RTSn */ - 0, -}; - -static void __init db88f5281_init(void) -{ - /* - * Basic Orion setup. Need to be called early. - */ - orion5x_init(); - - orion5x_mpp_conf(db88f5281_mpp_modes); - writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */ - - /* - * Configure peripherals. - */ - orion5x_ehci0_init(); - orion5x_eth_init(&db88f5281_eth_data); - orion5x_i2c_init(); - orion5x_uart0_init(); - orion5x_uart1_init(); - - mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, - ORION_MBUS_DEVBUS_BOOT_ATTR, - DB88F5281_NOR_BOOT_BASE, - DB88F5281_NOR_BOOT_SIZE); - platform_device_register(&db88f5281_boot_flash); - - mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(0), - ORION_MBUS_DEVBUS_ATTR(0), - DB88F5281_7SEG_BASE, - DB88F5281_7SEG_SIZE); - - mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(1), - ORION_MBUS_DEVBUS_ATTR(1), - DB88F5281_NOR_BASE, - DB88F5281_NOR_SIZE); - platform_device_register(&db88f5281_nor_flash); - - mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(2), - ORION_MBUS_DEVBUS_ATTR(2), - DB88F5281_NAND_BASE, - DB88F5281_NAND_SIZE); - platform_device_register(&db88f5281_nand_flash); - - i2c_register_board_info(0, &db88f5281_i2c_rtc, 1); -} - -MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board") - /* Maintainer: Tzachi Perelstein */ - .atag_offset = 0x100, - .nr_irqs = ORION5X_NR_IRQS, - .init_machine = db88f5281_init, - .map_io = orion5x_map_io, - .init_early = orion5x_init_early, - .init_irq = orion5x_init_irq, - .init_time = orion5x_timer_init, - .restart = orion5x_restart, -MACHINE_END diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c deleted file mode 100644 index af07f617465f..000000000000 --- a/arch/arm/mach-orion5x/ls_hgl-setup.c +++ /dev/null @@ -1,275 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/mach-orion5x/ls_hgl-setup.c - * - * Maintainer: Zhu Qingsen - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "common.h" -#include "mpp.h" -#include "orion5x.h" - -/***************************************************************************** - * Linkstation LS-HGL Info - ****************************************************************************/ - -/* - * 256K NOR flash Device bus boot chip select - */ - -#define LS_HGL_NOR_BOOT_BASE 0xf4000000 -#define LS_HGL_NOR_BOOT_SIZE SZ_256K - -/***************************************************************************** - * 256KB NOR Flash on BOOT Device - ****************************************************************************/ - -static struct physmap_flash_data ls_hgl_nor_flash_data = { - .width = 1, -}; - -static struct resource ls_hgl_nor_flash_resource = { - .flags = IORESOURCE_MEM, - .start = LS_HGL_NOR_BOOT_BASE, - .end = LS_HGL_NOR_BOOT_BASE + LS_HGL_NOR_BOOT_SIZE - 1, -}; - -static struct platform_device ls_hgl_nor_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &ls_hgl_nor_flash_data, - }, - .num_resources = 1, - .resource = &ls_hgl_nor_flash_resource, -}; - -/***************************************************************************** - * Ethernet - ****************************************************************************/ - -static struct mv643xx_eth_platform_data ls_hgl_eth_data = { - .phy_addr = 8, -}; - -/***************************************************************************** - * RTC 5C372a on I2C bus - ****************************************************************************/ - -static struct i2c_board_info __initdata ls_hgl_i2c_rtc = { - I2C_BOARD_INFO("rs5c372a", 0x32), -}; - -/***************************************************************************** - * LEDs attached to GPIO - ****************************************************************************/ - -#define LS_HGL_GPIO_LED_ALARM 2 -#define LS_HGL_GPIO_LED_INFO 3 -#define LS_HGL_GPIO_LED_FUNC 17 -#define LS_HGL_GPIO_LED_PWR 0 - - -static struct gpio_led ls_hgl_led_pins[] = { - { - .name = "alarm:red", - .gpio = LS_HGL_GPIO_LED_ALARM, - .active_low = 1, - }, { - .name = "info:amber", - .gpio = LS_HGL_GPIO_LED_INFO, - .active_low = 1, - }, { - .name = "func:blue:top", - .gpio = LS_HGL_GPIO_LED_FUNC, - .active_low = 1, - }, { - .name = "power:blue:bottom", - .gpio = LS_HGL_GPIO_LED_PWR, - }, -}; - -static struct gpio_led_platform_data ls_hgl_led_data = { - .leds = ls_hgl_led_pins, - .num_leds = ARRAY_SIZE(ls_hgl_led_pins), -}; - -static struct platform_device ls_hgl_leds = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &ls_hgl_led_data, - }, -}; - -/**************************************************************************** - * GPIO Attached Keys - ****************************************************************************/ -#define LS_HGL_GPIO_KEY_FUNC 15 -#define LS_HGL_GPIO_KEY_POWER 8 -#define LS_HGL_GPIO_KEY_AUTOPOWER 10 - -#define LS_HGL_SW_POWER 0x00 -#define LS_HGL_SW_AUTOPOWER 0x01 - -static struct gpio_keys_button ls_hgl_buttons[] = { - { - .code = KEY_OPTION, - .gpio = LS_HGL_GPIO_KEY_FUNC, - .desc = "Function Button", - .active_low = 1, - }, { - .type = EV_SW, - .code = LS_HGL_SW_POWER, - .gpio = LS_HGL_GPIO_KEY_POWER, - .desc = "Power-on Switch", - .active_low = 1, - }, { - .type = EV_SW, - .code = LS_HGL_SW_AUTOPOWER, - .gpio = LS_HGL_GPIO_KEY_AUTOPOWER, - .desc = "Power-auto Switch", - .active_low = 1, - }, -}; - -static struct gpio_keys_platform_data ls_hgl_button_data = { - .buttons = ls_hgl_buttons, - .nbuttons = ARRAY_SIZE(ls_hgl_buttons), -}; - -static struct platform_device ls_hgl_button_device = { - .name = "gpio-keys", - .id = -1, - .num_resources = 0, - .dev = { - .platform_data = &ls_hgl_button_data, - }, -}; - - -/***************************************************************************** - * SATA - ****************************************************************************/ -static struct mv_sata_platform_data ls_hgl_sata_data = { - .n_ports = 2, -}; - - -/***************************************************************************** - * Linkstation LS-HGL specific power off method: reboot - ****************************************************************************/ -/* - * On the Linkstation LS-HGL, the shutdown process is following: - * - Userland monitors key events until the power switch goes to off position - * - The board reboots - * - U-boot starts and goes into an idle mode waiting for the user - * to move the switch to ON position - */ - -static void ls_hgl_power_off(void) -{ - orion5x_restart(REBOOT_HARD, NULL); -} - - -/***************************************************************************** - * General Setup - ****************************************************************************/ - -#define LS_HGL_GPIO_USB_POWER 9 -#define LS_HGL_GPIO_AUTO_POWER 10 -#define LS_HGL_GPIO_POWER 8 - -#define LS_HGL_GPIO_HDD_POWER 1 - -static unsigned int ls_hgl_mpp_modes[] __initdata = { - MPP0_GPIO, /* LED_PWR */ - MPP1_GPIO, /* HDD_PWR */ - MPP2_GPIO, /* LED_ALARM */ - MPP3_GPIO, /* LED_INFO */ - MPP4_UNUSED, - MPP5_UNUSED, - MPP6_GPIO, /* FAN_LCK */ - MPP7_GPIO, /* INIT */ - MPP8_GPIO, /* POWER */ - MPP9_GPIO, /* USB_PWR */ - MPP10_GPIO, /* AUTO_POWER */ - MPP11_UNUSED, /* LED_ETH (dummy) */ - MPP12_UNUSED, - MPP13_UNUSED, - MPP14_UNUSED, - MPP15_GPIO, /* FUNC */ - MPP16_UNUSED, - MPP17_GPIO, /* LED_FUNC */ - MPP18_UNUSED, - MPP19_UNUSED, - 0, -}; - -static void __init ls_hgl_init(void) -{ - /* - * Setup basic Orion functions. Need to be called early. - */ - orion5x_init(); - - orion5x_mpp_conf(ls_hgl_mpp_modes); - - /* - * Configure peripherals. - */ - orion5x_ehci0_init(); - orion5x_ehci1_init(); - orion5x_eth_init(&ls_hgl_eth_data); - orion5x_i2c_init(); - orion5x_sata_init(&ls_hgl_sata_data); - orion5x_uart0_init(); - orion5x_xor_init(); - - mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, - ORION_MBUS_DEVBUS_BOOT_ATTR, - LS_HGL_NOR_BOOT_BASE, - LS_HGL_NOR_BOOT_SIZE); - platform_device_register(&ls_hgl_nor_flash); - - platform_device_register(&ls_hgl_button_device); - - platform_device_register(&ls_hgl_leds); - - i2c_register_board_info(0, &ls_hgl_i2c_rtc, 1); - - /* enable USB power */ - gpio_set_value(LS_HGL_GPIO_USB_POWER, 1); - - /* register power-off method */ - pm_power_off = ls_hgl_power_off; - - pr_info("%s: finished\n", __func__); -} - -MACHINE_START(LINKSTATION_LS_HGL, "Buffalo Linkstation LS-HGL") - /* Maintainer: Zhu Qingsen */ - .atag_offset = 0x100, - .nr_irqs = ORION5X_NR_IRQS, - .init_machine = ls_hgl_init, - .map_io = orion5x_map_io, - .init_early = orion5x_init_early, - .init_irq = orion5x_init_irq, - .init_time = orion5x_timer_init, - .fixup = tag_fixup_mem32, - .restart = orion5x_restart, -MACHINE_END diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c deleted file mode 100644 index 432fc8357d9e..000000000000 --- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c +++ /dev/null @@ -1,172 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c - * - * Marvell Orion-VoIP FXO Reference Design Setup - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "common.h" -#include "mpp.h" -#include "orion5x.h" - -/***************************************************************************** - * RD-88F5181L FXO Info - ****************************************************************************/ -/* - * 8M NOR flash Device bus boot chip select - */ -#define RD88F5181L_FXO_NOR_BOOT_BASE 0xff800000 -#define RD88F5181L_FXO_NOR_BOOT_SIZE SZ_8M - - -/***************************************************************************** - * 8M NOR Flash on Device bus Boot chip select - ****************************************************************************/ -static struct physmap_flash_data rd88f5181l_fxo_nor_boot_flash_data = { - .width = 1, -}; - -static struct resource rd88f5181l_fxo_nor_boot_flash_resource = { - .flags = IORESOURCE_MEM, - .start = RD88F5181L_FXO_NOR_BOOT_BASE, - .end = RD88F5181L_FXO_NOR_BOOT_BASE + - RD88F5181L_FXO_NOR_BOOT_SIZE - 1, -}; - -static struct platform_device rd88f5181l_fxo_nor_boot_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &rd88f5181l_fxo_nor_boot_flash_data, - }, - .num_resources = 1, - .resource = &rd88f5181l_fxo_nor_boot_flash_resource, -}; - - -/***************************************************************************** - * General Setup - ****************************************************************************/ -static unsigned int rd88f5181l_fxo_mpp_modes[] __initdata = { - MPP0_GPIO, /* LED1 CardBus LED (front panel) */ - MPP1_GPIO, /* PCI_intA */ - MPP2_GPIO, /* Hard Reset / Factory Init*/ - MPP3_GPIO, /* FXS or DAA select */ - MPP4_GPIO, /* LED6 - phone LED (front panel) */ - MPP5_GPIO, /* LED5 - phone LED (front panel) */ - MPP6_PCI_CLK, /* CPU PCI refclk */ - MPP7_PCI_CLK, /* PCI/PCIe refclk */ - MPP8_GPIO, /* CardBus reset */ - MPP9_GPIO, /* GE_RXERR */ - MPP10_GPIO, /* LED2 MiniPCI LED (front panel) */ - MPP11_GPIO, /* Lifeline control */ - MPP12_GIGE, /* GE_TXD[4] */ - MPP13_GIGE, /* GE_TXD[5] */ - MPP14_GIGE, /* GE_TXD[6] */ - MPP15_GIGE, /* GE_TXD[7] */ - MPP16_GIGE, /* GE_RXD[4] */ - MPP17_GIGE, /* GE_RXD[5] */ - MPP18_GIGE, /* GE_RXD[6] */ - MPP19_GIGE, /* GE_RXD[7] */ - 0, -}; - -static struct mv643xx_eth_platform_data rd88f5181l_fxo_eth_data = { - .phy_addr = MV643XX_ETH_PHY_NONE, - .speed = SPEED_1000, - .duplex = DUPLEX_FULL, -}; - -static struct dsa_chip_data rd88f5181l_fxo_switch_chip_data = { - .port_names[0] = "lan2", - .port_names[1] = "lan1", - .port_names[2] = "wan", - .port_names[3] = "cpu", - .port_names[5] = "lan4", - .port_names[7] = "lan3", -}; - -static void __init rd88f5181l_fxo_init(void) -{ - /* - * Setup basic Orion functions. Need to be called early. - */ - orion5x_init(); - - orion5x_mpp_conf(rd88f5181l_fxo_mpp_modes); - - /* - * Configure peripherals. - */ - orion5x_ehci0_init(); - orion5x_eth_init(&rd88f5181l_fxo_eth_data); - orion5x_eth_switch_init(&rd88f5181l_fxo_switch_chip_data); - orion5x_uart0_init(); - - mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, - ORION_MBUS_DEVBUS_BOOT_ATTR, - RD88F5181L_FXO_NOR_BOOT_BASE, - RD88F5181L_FXO_NOR_BOOT_SIZE); - platform_device_register(&rd88f5181l_fxo_nor_boot_flash); -} - -static int __init -rd88f5181l_fxo_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - int irq; - - /* - * Check for devices with hard-wired IRQs. - */ - irq = orion5x_pci_map_irq(dev, slot, pin); - if (irq != -1) - return irq; - - /* - * Mini-PCI / Cardbus slot. - */ - return gpio_to_irq(1); -} - -static struct hw_pci rd88f5181l_fxo_pci __initdata = { - .nr_controllers = 2, - .setup = orion5x_pci_sys_setup, - .scan = orion5x_pci_sys_scan_bus, - .map_irq = rd88f5181l_fxo_pci_map_irq, -}; - -static int __init rd88f5181l_fxo_pci_init(void) -{ - if (machine_is_rd88f5181l_fxo()) { - orion5x_pci_set_cardbus_mode(); - pci_common_init(&rd88f5181l_fxo_pci); - } - - return 0; -} -subsys_initcall(rd88f5181l_fxo_pci_init); - -MACHINE_START(RD88F5181L_FXO, "Marvell Orion-VoIP FXO Reference Design") - /* Maintainer: Nicolas Pitre */ - .atag_offset = 0x100, - .nr_irqs = ORION5X_NR_IRQS, - .init_machine = rd88f5181l_fxo_init, - .map_io = orion5x_map_io, - .init_early = orion5x_init_early, - .init_irq = orion5x_init_irq, - .init_time = orion5x_timer_init, - .fixup = tag_fixup_mem32, - .restart = orion5x_restart, -MACHINE_END diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c deleted file mode 100644 index d4b1a9c3cd36..000000000000 --- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c +++ /dev/null @@ -1,183 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/mach-orion5x/rd88f5181l-ge-setup.c - * - * Marvell Orion-VoIP GE Reference Design Setup - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "common.h" -#include "mpp.h" -#include "orion5x.h" - -/***************************************************************************** - * RD-88F5181L GE Info - ****************************************************************************/ -/* - * 16M NOR flash Device bus boot chip select - */ -#define RD88F5181L_GE_NOR_BOOT_BASE 0xff000000 -#define RD88F5181L_GE_NOR_BOOT_SIZE SZ_16M - - -/***************************************************************************** - * 16M NOR Flash on Device bus Boot chip select - ****************************************************************************/ -static struct physmap_flash_data rd88f5181l_ge_nor_boot_flash_data = { - .width = 1, -}; - -static struct resource rd88f5181l_ge_nor_boot_flash_resource = { - .flags = IORESOURCE_MEM, - .start = RD88F5181L_GE_NOR_BOOT_BASE, - .end = RD88F5181L_GE_NOR_BOOT_BASE + - RD88F5181L_GE_NOR_BOOT_SIZE - 1, -}; - -static struct platform_device rd88f5181l_ge_nor_boot_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &rd88f5181l_ge_nor_boot_flash_data, - }, - .num_resources = 1, - .resource = &rd88f5181l_ge_nor_boot_flash_resource, -}; - - -/***************************************************************************** - * General Setup - ****************************************************************************/ -static unsigned int rd88f5181l_ge_mpp_modes[] __initdata = { - MPP0_GPIO, /* LED1 */ - MPP1_GPIO, /* LED5 */ - MPP2_GPIO, /* LED4 */ - MPP3_GPIO, /* LED3 */ - MPP4_GPIO, /* PCI_intA */ - MPP5_GPIO, /* RTC interrupt */ - MPP6_PCI_CLK, /* CPU PCI refclk */ - MPP7_PCI_CLK, /* PCI/PCIe refclk */ - MPP8_GPIO, /* 88e6131 interrupt */ - MPP9_GPIO, /* GE_RXERR */ - MPP10_GPIO, /* PCI_intB */ - MPP11_GPIO, /* LED2 */ - MPP12_GIGE, /* GE_TXD[4] */ - MPP13_GIGE, /* GE_TXD[5] */ - MPP14_GIGE, /* GE_TXD[6] */ - MPP15_GIGE, /* GE_TXD[7] */ - MPP16_GIGE, /* GE_RXD[4] */ - MPP17_GIGE, /* GE_RXD[5] */ - MPP18_GIGE, /* GE_RXD[6] */ - MPP19_GIGE, /* GE_RXD[7] */ - 0, -}; - -static struct mv643xx_eth_platform_data rd88f5181l_ge_eth_data = { - .phy_addr = MV643XX_ETH_PHY_NONE, - .speed = SPEED_1000, - .duplex = DUPLEX_FULL, -}; - -static struct dsa_chip_data rd88f5181l_ge_switch_chip_data = { - .port_names[0] = "lan2", - .port_names[1] = "lan1", - .port_names[2] = "wan", - .port_names[3] = "cpu", - .port_names[5] = "lan4", - .port_names[7] = "lan3", -}; - -static struct i2c_board_info __initdata rd88f5181l_ge_i2c_rtc = { - I2C_BOARD_INFO("ds1338", 0x68), -}; - -static void __init rd88f5181l_ge_init(void) -{ - /* - * Setup basic Orion functions. Need to be called early. - */ - orion5x_init(); - - orion5x_mpp_conf(rd88f5181l_ge_mpp_modes); - - /* - * Configure peripherals. - */ - orion5x_ehci0_init(); - orion5x_eth_init(&rd88f5181l_ge_eth_data); - orion5x_eth_switch_init(&rd88f5181l_ge_switch_chip_data); - orion5x_i2c_init(); - orion5x_uart0_init(); - - mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, - ORION_MBUS_DEVBUS_BOOT_ATTR, - RD88F5181L_GE_NOR_BOOT_BASE, - RD88F5181L_GE_NOR_BOOT_SIZE); - platform_device_register(&rd88f5181l_ge_nor_boot_flash); - - i2c_register_board_info(0, &rd88f5181l_ge_i2c_rtc, 1); -} - -static int __init -rd88f5181l_ge_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - int irq; - - /* - * Check for devices with hard-wired IRQs. - */ - irq = orion5x_pci_map_irq(dev, slot, pin); - if (irq != -1) - return irq; - - /* - * Cardbus slot. - */ - if (pin == 1) - return gpio_to_irq(4); - else - return gpio_to_irq(10); -} - -static struct hw_pci rd88f5181l_ge_pci __initdata = { - .nr_controllers = 2, - .setup = orion5x_pci_sys_setup, - .scan = orion5x_pci_sys_scan_bus, - .map_irq = rd88f5181l_ge_pci_map_irq, -}; - -static int __init rd88f5181l_ge_pci_init(void) -{ - if (machine_is_rd88f5181l_ge()) { - orion5x_pci_set_cardbus_mode(); - pci_common_init(&rd88f5181l_ge_pci); - } - - return 0; -} -subsys_initcall(rd88f5181l_ge_pci_init); - -MACHINE_START(RD88F5181L_GE, "Marvell Orion-VoIP GE Reference Design") - /* Maintainer: Lennert Buytenhek */ - .atag_offset = 0x100, - .nr_irqs = ORION5X_NR_IRQS, - .init_machine = rd88f5181l_ge_init, - .map_io = orion5x_map_io, - .init_early = orion5x_init_early, - .init_irq = orion5x_init_irq, - .init_time = orion5x_timer_init, - .fixup = tag_fixup_mem32, - .restart = orion5x_restart, -MACHINE_END diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c deleted file mode 100644 index 6ffcfc6445e2..000000000000 --- a/arch/arm/mach-orion5x/rd88f5182-setup.c +++ /dev/null @@ -1,288 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/mach-orion5x/rd88f5182-setup.c - * - * Marvell Orion-NAS Reference Design Setup - * - * Maintainer: Ronen Shitrit - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "common.h" -#include "mpp.h" -#include "orion5x.h" - -/***************************************************************************** - * RD-88F5182 Info - ****************************************************************************/ - -/* - * 512K NOR flash Device bus boot chip select - */ - -#define RD88F5182_NOR_BOOT_BASE 0xf4000000 -#define RD88F5182_NOR_BOOT_SIZE SZ_512K - -/* - * 16M NOR flash on Device bus chip select 1 - */ - -#define RD88F5182_NOR_BASE 0xfc000000 -#define RD88F5182_NOR_SIZE SZ_16M - -/* - * PCI - */ - -#define RD88F5182_PCI_SLOT0_OFFS 7 -#define RD88F5182_PCI_SLOT0_IRQ_A_PIN 7 -#define RD88F5182_PCI_SLOT0_IRQ_B_PIN 6 - -/***************************************************************************** - * 16M NOR Flash on Device bus CS1 - ****************************************************************************/ - -static struct physmap_flash_data rd88f5182_nor_flash_data = { - .width = 1, -}; - -static struct resource rd88f5182_nor_flash_resource = { - .flags = IORESOURCE_MEM, - .start = RD88F5182_NOR_BASE, - .end = RD88F5182_NOR_BASE + RD88F5182_NOR_SIZE - 1, -}; - -static struct platform_device rd88f5182_nor_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &rd88f5182_nor_flash_data, - }, - .num_resources = 1, - .resource = &rd88f5182_nor_flash_resource, -}; - -/***************************************************************************** - * Use GPIO LED as CPU active indication - ****************************************************************************/ - -#define RD88F5182_GPIO_LED 0 - -static struct gpio_led rd88f5182_gpio_led_pins[] = { - { - .name = "rd88f5182:cpu", - .default_trigger = "cpu0", - .gpio = RD88F5182_GPIO_LED, - }, -}; - -static struct gpio_led_platform_data rd88f5182_gpio_led_data = { - .leds = rd88f5182_gpio_led_pins, - .num_leds = ARRAY_SIZE(rd88f5182_gpio_led_pins), -}; - -static struct platform_device rd88f5182_gpio_leds = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &rd88f5182_gpio_led_data, - }, -}; - -/***************************************************************************** - * PCI - ****************************************************************************/ - -static void __init rd88f5182_pci_preinit(void) -{ - int pin; - - /* - * Configure PCI GPIO IRQ pins - */ - pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN; - if (gpio_request(pin, "PCI IntA") == 0) { - if (gpio_direction_input(pin) == 0) { - irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); - } else { - printk(KERN_ERR "rd88f5182_pci_preinit failed to " - "set_irq_type pin %d\n", pin); - gpio_free(pin); - } - } else { - printk(KERN_ERR "rd88f5182_pci_preinit failed to request gpio %d\n", pin); - } - - pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN; - if (gpio_request(pin, "PCI IntB") == 0) { - if (gpio_direction_input(pin) == 0) { - irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); - } else { - printk(KERN_ERR "rd88f5182_pci_preinit failed to " - "set_irq_type pin %d\n", pin); - gpio_free(pin); - } - } else { - printk(KERN_ERR "rd88f5182_pci_preinit failed to gpio_request %d\n", pin); - } -} - -static int __init rd88f5182_pci_map_irq(const struct pci_dev *dev, u8 slot, - u8 pin) -{ - int irq; - - /* - * Check for devices with hard-wired IRQs. - */ - irq = orion5x_pci_map_irq(dev, slot, pin); - if (irq != -1) - return irq; - - /* - * PCI IRQs are connected via GPIOs - */ - switch (slot - RD88F5182_PCI_SLOT0_OFFS) { - case 0: - if (pin == 1) - return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_A_PIN); - else - return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_B_PIN); - default: - return -1; - } -} - -static struct hw_pci rd88f5182_pci __initdata = { - .nr_controllers = 2, - .preinit = rd88f5182_pci_preinit, - .setup = orion5x_pci_sys_setup, - .scan = orion5x_pci_sys_scan_bus, - .map_irq = rd88f5182_pci_map_irq, -}; - -static int __init rd88f5182_pci_init(void) -{ - if (machine_is_rd88f5182()) - pci_common_init(&rd88f5182_pci); - - return 0; -} - -subsys_initcall(rd88f5182_pci_init); - -/***************************************************************************** - * Ethernet - ****************************************************************************/ - -static struct mv643xx_eth_platform_data rd88f5182_eth_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(8), -}; - -/***************************************************************************** - * RTC DS1338 on I2C bus - ****************************************************************************/ -static struct i2c_board_info __initdata rd88f5182_i2c_rtc = { - I2C_BOARD_INFO("ds1338", 0x68), -}; - -/***************************************************************************** - * Sata - ****************************************************************************/ -static struct mv_sata_platform_data rd88f5182_sata_data = { - .n_ports = 2, -}; - -/***************************************************************************** - * General Setup - ****************************************************************************/ -static unsigned int rd88f5182_mpp_modes[] __initdata = { - MPP0_GPIO, /* Debug Led */ - MPP1_GPIO, /* Reset Switch */ - MPP2_UNUSED, - MPP3_GPIO, /* RTC Int */ - MPP4_GPIO, - MPP5_GPIO, - MPP6_GPIO, /* PCI_intA */ - MPP7_GPIO, /* PCI_intB */ - MPP8_UNUSED, - MPP9_UNUSED, - MPP10_UNUSED, - MPP11_UNUSED, - MPP12_SATA_LED, /* SATA 0 presence */ - MPP13_SATA_LED, /* SATA 1 presence */ - MPP14_SATA_LED, /* SATA 0 active */ - MPP15_SATA_LED, /* SATA 1 active */ - MPP16_UNUSED, - MPP17_UNUSED, - MPP18_UNUSED, - MPP19_UNUSED, - 0, -}; - -static void __init rd88f5182_init(void) -{ - /* - * Setup basic Orion functions. Need to be called early. - */ - orion5x_init(); - - orion5x_mpp_conf(rd88f5182_mpp_modes); - - /* - * MPP[20] PCI Clock to MV88F5182 - * MPP[21] PCI Clock to mini PCI CON11 - * MPP[22] USB 0 over current indication - * MPP[23] USB 1 over current indication - * MPP[24] USB 1 over current enable - * MPP[25] USB 0 over current enable - */ - - /* - * Configure peripherals. - */ - orion5x_ehci0_init(); - orion5x_ehci1_init(); - orion5x_eth_init(&rd88f5182_eth_data); - orion5x_i2c_init(); - orion5x_sata_init(&rd88f5182_sata_data); - orion5x_uart0_init(); - orion5x_xor_init(); - - mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, - ORION_MBUS_DEVBUS_BOOT_ATTR, - RD88F5182_NOR_BOOT_BASE, - RD88F5182_NOR_BOOT_SIZE); - mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(1), - ORION_MBUS_DEVBUS_ATTR(1), - RD88F5182_NOR_BASE, - RD88F5182_NOR_SIZE); - platform_device_register(&rd88f5182_nor_flash); - platform_device_register(&rd88f5182_gpio_leds); - - i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1); -} - -MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design") - /* Maintainer: Ronen Shitrit */ - .atag_offset = 0x100, - .nr_irqs = ORION5X_NR_IRQS, - .init_machine = rd88f5182_init, - .map_io = orion5x_map_io, - .init_early = orion5x_init_early, - .init_irq = orion5x_init_irq, - .init_time = orion5x_timer_init, - .restart = orion5x_restart, -MACHINE_END diff --git a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c deleted file mode 100644 index 93f74fd6b4da..000000000000 --- a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c +++ /dev/null @@ -1,120 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/mach-orion5x/rd88f6183-ap-ge-setup.c - * - * Marvell Orion-1-90 AP GE Reference Design Setup - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "common.h" -#include "orion5x.h" - -static struct mv643xx_eth_platform_data rd88f6183ap_ge_eth_data = { - .phy_addr = -1, - .speed = SPEED_1000, - .duplex = DUPLEX_FULL, -}; - -static struct dsa_chip_data rd88f6183ap_ge_switch_chip_data = { - .port_names[0] = "lan1", - .port_names[1] = "lan2", - .port_names[2] = "lan3", - .port_names[3] = "lan4", - .port_names[4] = "wan", - .port_names[5] = "cpu", -}; - -static struct mtd_partition rd88f6183ap_ge_partitions[] = { - { - .name = "kernel", - .offset = 0x00000000, - .size = 0x00200000, - }, { - .name = "rootfs", - .offset = 0x00200000, - .size = 0x00500000, - }, { - .name = "nvram", - .offset = 0x00700000, - .size = 0x00080000, - }, -}; - -static struct flash_platform_data rd88f6183ap_ge_spi_slave_data = { - .type = "m25p64", - .nr_parts = ARRAY_SIZE(rd88f6183ap_ge_partitions), - .parts = rd88f6183ap_ge_partitions, -}; - -static struct spi_board_info __initdata rd88f6183ap_ge_spi_slave_info[] = { - { - .modalias = "m25p80", - .platform_data = &rd88f6183ap_ge_spi_slave_data, - .max_speed_hz = 20000000, - .bus_num = 0, - .chip_select = 0, - }, -}; - -static void __init rd88f6183ap_ge_init(void) -{ - /* - * Setup basic Orion functions. Need to be called early. - */ - orion5x_init(); - - /* - * Configure peripherals. - */ - orion5x_ehci0_init(); - orion5x_eth_init(&rd88f6183ap_ge_eth_data); - orion5x_eth_switch_init(&rd88f6183ap_ge_switch_chip_data); - spi_register_board_info(rd88f6183ap_ge_spi_slave_info, - ARRAY_SIZE(rd88f6183ap_ge_spi_slave_info)); - orion5x_spi_init(); - orion5x_uart0_init(); -} - -static struct hw_pci rd88f6183ap_ge_pci __initdata = { - .nr_controllers = 2, - .setup = orion5x_pci_sys_setup, - .scan = orion5x_pci_sys_scan_bus, - .map_irq = orion5x_pci_map_irq, -}; - -static int __init rd88f6183ap_ge_pci_init(void) -{ - if (machine_is_rd88f6183ap_ge()) { - orion5x_pci_disable(); - pci_common_init(&rd88f6183ap_ge_pci); - } - - return 0; -} -subsys_initcall(rd88f6183ap_ge_pci_init); - -MACHINE_START(RD88F6183AP_GE, "Marvell Orion-1-90 AP GE Reference Design") - /* Maintainer: Lennert Buytenhek */ - .atag_offset = 0x100, - .nr_irqs = ORION5X_NR_IRQS, - .init_machine = rd88f6183ap_ge_init, - .map_io = orion5x_map_io, - .init_early = orion5x_init_early, - .init_irq = orion5x_init_irq, - .init_time = orion5x_timer_init, - .fixup = tag_fixup_mem32, - .restart = orion5x_restart, -MACHINE_END diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c deleted file mode 100644 index e5f327054dd3..000000000000 --- a/arch/arm/mach-orion5x/wnr854t-setup.c +++ /dev/null @@ -1,175 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -// arch/arm/mach-orion5x/wnr854t-setup.c -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "orion5x.h" -#include "common.h" -#include "mpp.h" - -static unsigned int wnr854t_mpp_modes[] __initdata = { - MPP0_GPIO, /* Power LED green (0=on) */ - MPP1_GPIO, /* Reset Button (0=off) */ - MPP2_GPIO, /* Power LED blink (0=off) */ - MPP3_GPIO, /* WAN Status LED amber (0=off) */ - MPP4_GPIO, /* PCI int */ - MPP5_GPIO, /* ??? */ - MPP6_GPIO, /* ??? */ - MPP7_GPIO, /* ??? */ - MPP8_UNUSED, /* ??? */ - MPP9_GIGE, /* GE_RXERR */ - MPP10_UNUSED, /* ??? */ - MPP11_UNUSED, /* ??? */ - MPP12_GIGE, /* GE_TXD[4] */ - MPP13_GIGE, /* GE_TXD[5] */ - MPP14_GIGE, /* GE_TXD[6] */ - MPP15_GIGE, /* GE_TXD[7] */ - MPP16_GIGE, /* GE_RXD[4] */ - MPP17_GIGE, /* GE_RXD[5] */ - MPP18_GIGE, /* GE_RXD[6] */ - MPP19_GIGE, /* GE_RXD[7] */ - 0, -}; - -/* - * 8M NOR flash Device bus boot chip select - */ -#define WNR854T_NOR_BOOT_BASE 0xf4000000 -#define WNR854T_NOR_BOOT_SIZE SZ_8M - -static struct mtd_partition wnr854t_nor_flash_partitions[] = { - { - .name = "kernel", - .offset = 0x00000000, - .size = 0x00100000, - }, { - .name = "rootfs", - .offset = 0x00100000, - .size = 0x00660000, - }, { - .name = "uboot", - .offset = 0x00760000, - .size = 0x00040000, - }, -}; - -static struct physmap_flash_data wnr854t_nor_flash_data = { - .width = 2, - .parts = wnr854t_nor_flash_partitions, - .nr_parts = ARRAY_SIZE(wnr854t_nor_flash_partitions), -}; - -static struct resource wnr854t_nor_flash_resource = { - .flags = IORESOURCE_MEM, - .start = WNR854T_NOR_BOOT_BASE, - .end = WNR854T_NOR_BOOT_BASE + WNR854T_NOR_BOOT_SIZE - 1, -}; - -static struct platform_device wnr854t_nor_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &wnr854t_nor_flash_data, - }, - .num_resources = 1, - .resource = &wnr854t_nor_flash_resource, -}; - -static struct mv643xx_eth_platform_data wnr854t_eth_data = { - .phy_addr = MV643XX_ETH_PHY_NONE, - .speed = SPEED_1000, - .duplex = DUPLEX_FULL, -}; - -static struct dsa_chip_data wnr854t_switch_chip_data = { - .port_names[0] = "lan3", - .port_names[1] = "lan4", - .port_names[2] = "wan", - .port_names[3] = "cpu", - .port_names[5] = "lan1", - .port_names[7] = "lan2", -}; - -static void __init wnr854t_init(void) -{ - /* - * Setup basic Orion functions. Need to be called early. - */ - orion5x_init(); - - orion5x_mpp_conf(wnr854t_mpp_modes); - - /* - * Configure peripherals. - */ - orion5x_eth_init(&wnr854t_eth_data); - orion5x_eth_switch_init(&wnr854t_switch_chip_data); - orion5x_uart0_init(); - - mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, - ORION_MBUS_DEVBUS_BOOT_ATTR, - WNR854T_NOR_BOOT_BASE, - WNR854T_NOR_BOOT_SIZE); - platform_device_register(&wnr854t_nor_flash); -} - -static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot, - u8 pin) -{ - int irq; - - /* - * Check for devices with hard-wired IRQs. - */ - irq = orion5x_pci_map_irq(dev, slot, pin); - if (irq != -1) - return irq; - - /* - * Mini-PCI slot. - */ - if (slot == 7) - return gpio_to_irq(4); - - return -1; -} - -static struct hw_pci wnr854t_pci __initdata = { - .nr_controllers = 2, - .setup = orion5x_pci_sys_setup, - .scan = orion5x_pci_sys_scan_bus, - .map_irq = wnr854t_pci_map_irq, -}; - -static int __init wnr854t_pci_init(void) -{ - if (machine_is_wnr854t()) - pci_common_init(&wnr854t_pci); - - return 0; -} -subsys_initcall(wnr854t_pci_init); - -MACHINE_START(WNR854T, "Netgear WNR854T") - /* Maintainer: Imre Kaloz */ - .atag_offset = 0x100, - .nr_irqs = ORION5X_NR_IRQS, - .init_machine = wnr854t_init, - .map_io = orion5x_map_io, - .init_early = orion5x_init_early, - .init_irq = orion5x_init_irq, - .init_time = orion5x_timer_init, - .fixup = tag_fixup_mem32, - .restart = orion5x_restart, -MACHINE_END diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c deleted file mode 100644 index e6a2da6662df..000000000000 --- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c +++ /dev/null @@ -1,263 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -// arch/arm/mach-orion5x/wrt350n-v2-setup.c -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "orion5x.h" -#include "common.h" -#include "mpp.h" - -/* - * LEDs attached to GPIO - */ -static struct gpio_led wrt350n_v2_led_pins[] = { - { - .name = "wrt350nv2:green:power", - .gpio = 0, - .active_low = 1, - }, { - .name = "wrt350nv2:green:security", - .gpio = 1, - .active_low = 1, - }, { - .name = "wrt350nv2:orange:power", - .gpio = 5, - .active_low = 1, - }, { - .name = "wrt350nv2:green:usb", - .gpio = 6, - .active_low = 1, - }, { - .name = "wrt350nv2:green:wireless", - .gpio = 7, - .active_low = 1, - }, -}; - -static struct gpio_led_platform_data wrt350n_v2_led_data = { - .leds = wrt350n_v2_led_pins, - .num_leds = ARRAY_SIZE(wrt350n_v2_led_pins), -}; - -static struct platform_device wrt350n_v2_leds = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &wrt350n_v2_led_data, - }, -}; - -/* - * Buttons attached to GPIO - */ -static struct gpio_keys_button wrt350n_v2_buttons[] = { - { - .code = KEY_RESTART, - .gpio = 3, - .desc = "Reset Button", - .active_low = 1, - }, { - .code = KEY_WPS_BUTTON, - .gpio = 2, - .desc = "WPS Button", - .active_low = 1, - }, -}; - -static struct gpio_keys_platform_data wrt350n_v2_button_data = { - .buttons = wrt350n_v2_buttons, - .nbuttons = ARRAY_SIZE(wrt350n_v2_buttons), -}; - -static struct platform_device wrt350n_v2_button_device = { - .name = "gpio-keys", - .id = -1, - .num_resources = 0, - .dev = { - .platform_data = &wrt350n_v2_button_data, - }, -}; - -/* - * General setup - */ -static unsigned int wrt350n_v2_mpp_modes[] __initdata = { - MPP0_GPIO, /* Power LED green (0=on) */ - MPP1_GPIO, /* Security LED (0=on) */ - MPP2_GPIO, /* Internal Button (0=on) */ - MPP3_GPIO, /* Reset Button (0=on) */ - MPP4_GPIO, /* PCI int */ - MPP5_GPIO, /* Power LED orange (0=on) */ - MPP6_GPIO, /* USB LED (0=on) */ - MPP7_GPIO, /* Wireless LED (0=on) */ - MPP8_UNUSED, /* ??? */ - MPP9_GIGE, /* GE_RXERR */ - MPP10_UNUSED, /* ??? */ - MPP11_UNUSED, /* ??? */ - MPP12_GIGE, /* GE_TXD[4] */ - MPP13_GIGE, /* GE_TXD[5] */ - MPP14_GIGE, /* GE_TXD[6] */ - MPP15_GIGE, /* GE_TXD[7] */ - MPP16_GIGE, /* GE_RXD[4] */ - MPP17_GIGE, /* GE_RXD[5] */ - MPP18_GIGE, /* GE_RXD[6] */ - MPP19_GIGE, /* GE_RXD[7] */ - 0, -}; - -/* - * 8M NOR flash Device bus boot chip select - */ -#define WRT350N_V2_NOR_BOOT_BASE 0xf4000000 -#define WRT350N_V2_NOR_BOOT_SIZE SZ_8M - -static struct mtd_partition wrt350n_v2_nor_flash_partitions[] = { - { - .name = "kernel", - .offset = 0x00000000, - .size = 0x00760000, - }, { - .name = "rootfs", - .offset = 0x001a0000, - .size = 0x005c0000, - }, { - .name = "lang", - .offset = 0x00760000, - .size = 0x00040000, - }, { - .name = "nvram", - .offset = 0x007a0000, - .size = 0x00020000, - }, { - .name = "u-boot", - .offset = 0x007c0000, - .size = 0x00040000, - }, -}; - -static struct physmap_flash_data wrt350n_v2_nor_flash_data = { - .width = 1, - .parts = wrt350n_v2_nor_flash_partitions, - .nr_parts = ARRAY_SIZE(wrt350n_v2_nor_flash_partitions), -}; - -static struct resource wrt350n_v2_nor_flash_resource = { - .flags = IORESOURCE_MEM, - .start = WRT350N_V2_NOR_BOOT_BASE, - .end = WRT350N_V2_NOR_BOOT_BASE + WRT350N_V2_NOR_BOOT_SIZE - 1, -}; - -static struct platform_device wrt350n_v2_nor_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &wrt350n_v2_nor_flash_data, - }, - .num_resources = 1, - .resource = &wrt350n_v2_nor_flash_resource, -}; - -static struct mv643xx_eth_platform_data wrt350n_v2_eth_data = { - .phy_addr = MV643XX_ETH_PHY_NONE, - .speed = SPEED_1000, - .duplex = DUPLEX_FULL, -}; - -static struct dsa_chip_data wrt350n_v2_switch_chip_data = { - .port_names[0] = "lan2", - .port_names[1] = "lan1", - .port_names[2] = "wan", - .port_names[3] = "cpu", - .port_names[5] = "lan3", - .port_names[7] = "lan4", -}; - -static void __init wrt350n_v2_init(void) -{ - /* - * Setup basic Orion functions. Need to be called early. - */ - orion5x_init(); - - orion5x_mpp_conf(wrt350n_v2_mpp_modes); - - /* - * Configure peripherals. - */ - orion5x_ehci0_init(); - orion5x_eth_init(&wrt350n_v2_eth_data); - orion5x_eth_switch_init(&wrt350n_v2_switch_chip_data); - orion5x_uart0_init(); - - mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, - ORION_MBUS_DEVBUS_BOOT_ATTR, - WRT350N_V2_NOR_BOOT_BASE, - WRT350N_V2_NOR_BOOT_SIZE); - platform_device_register(&wrt350n_v2_nor_flash); - platform_device_register(&wrt350n_v2_leds); - platform_device_register(&wrt350n_v2_button_device); -} - -static int __init wrt350n_v2_pci_map_irq(const struct pci_dev *dev, u8 slot, - u8 pin) -{ - int irq; - - /* - * Check for devices with hard-wired IRQs. - */ - irq = orion5x_pci_map_irq(dev, slot, pin); - if (irq != -1) - return irq; - - /* - * Mini-PCI slot. - */ - if (slot == 7) - return gpio_to_irq(4); - - return -1; -} - -static struct hw_pci wrt350n_v2_pci __initdata = { - .nr_controllers = 2, - .setup = orion5x_pci_sys_setup, - .scan = orion5x_pci_sys_scan_bus, - .map_irq = wrt350n_v2_pci_map_irq, -}; - -static int __init wrt350n_v2_pci_init(void) -{ - if (machine_is_wrt350n_v2()) - pci_common_init(&wrt350n_v2_pci); - - return 0; -} -subsys_initcall(wrt350n_v2_pci_init); - -MACHINE_START(WRT350N_V2, "Linksys WRT350N v2") - /* Maintainer: Lennert Buytenhek */ - .atag_offset = 0x100, - .nr_irqs = ORION5X_NR_IRQS, - .init_machine = wrt350n_v2_init, - .map_io = orion5x_map_io, - .init_early = orion5x_init_early, - .init_irq = orion5x_init_irq, - .init_time = orion5x_timer_init, - .fixup = tag_fixup_mem32, - .restart = orion5x_restart, -MACHINE_END -- cgit From fd68572b57f2be17e18905d28e5b7165741ad48a Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 22 Sep 2022 15:28:21 +0200 Subject: ARM: orion5x: remove dsa_chip_data references This is no longer used anywhere, which means we can kill off one link to gpio numbers. Cc: Andrew Lunn Signed-off-by: Arnd Bergmann --- arch/arm/mach-orion5x/common.c | 10 ---------- arch/arm/mach-orion5x/common.h | 2 -- arch/arm/plat-orion/common.c | 31 ------------------------------- arch/arm/plat-orion/include/plat/common.h | 3 --- 4 files changed, 46 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 2e711b7252c6..df056d60b675 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include @@ -100,15 +99,6 @@ void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) } -/***************************************************************************** - * Ethernet switch - ****************************************************************************/ -void __init orion5x_eth_switch_init(struct dsa_chip_data *d) -{ - orion_ge00_switch_init(d); -} - - /***************************************************************************** * I2C ****************************************************************************/ diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h index eb96009e21c4..f2e0577bf50f 100644 --- a/arch/arm/mach-orion5x/common.h +++ b/arch/arm/mach-orion5x/common.h @@ -4,7 +4,6 @@ #include -struct dsa_chip_data; struct mv643xx_eth_platform_data; struct mv_sata_platform_data; @@ -42,7 +41,6 @@ void orion5x_setup_wins(void); void orion5x_ehci0_init(void); void orion5x_ehci1_init(void); void orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data); -void orion5x_eth_switch_init(struct dsa_chip_data *d); void orion5x_i2c_init(void); void orion5x_sata_init(struct mv_sata_platform_data *sata_data); void orion5x_spi_init(void); diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c index 8647cb80a93b..cabe98386245 100644 --- a/arch/arm/plat-orion/common.c +++ b/arch/arm/plat-orion/common.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include @@ -468,36 +467,6 @@ void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data, eth_data, &orion_ge11); } -#ifdef CONFIG_ARCH_ORION5X -/***************************************************************************** - * Ethernet switch - ****************************************************************************/ -static __initdata struct mdio_board_info orion_ge00_switch_board_info = { - .bus_id = "orion-mii", - .modalias = "mv88e6085", -}; - -void __init orion_ge00_switch_init(struct dsa_chip_data *d) -{ - unsigned int i; - - if (!IS_BUILTIN(CONFIG_PHYLIB)) - return; - - for (i = 0; i < ARRAY_SIZE(d->port_names); i++) { - if (!strcmp(d->port_names[i], "cpu")) { - d->netdev[i] = &orion_ge00.dev; - break; - } - } - - orion_ge00_switch_board_info.mdio_addr = d->sw_addr; - orion_ge00_switch_board_info.platform_data = d; - - mdiobus_register_board_info(&orion_ge00_switch_board_info, 1); -} -#endif - /***************************************************************************** * I2C ****************************************************************************/ diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h index 3647d3b33c20..d2aad95d20cb 100644 --- a/arch/arm/plat-orion/include/plat/common.h +++ b/arch/arm/plat-orion/include/plat/common.h @@ -12,7 +12,6 @@ #include #include -struct dsa_chip_data; struct mv_sata_platform_data; void __init orion_uart0_init(void __iomem *membase, @@ -57,8 +56,6 @@ void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data, unsigned long mapbase, unsigned long irq); -void __init orion_ge00_switch_init(struct dsa_chip_data *d); - void __init orion_i2c_init(unsigned long mapbase, unsigned long irq, unsigned long freq_m); -- cgit From b91a69d162aae0f097432c8166956eccf71783d3 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 29 Sep 2022 15:31:18 +0200 Subject: ARM: iop32x: remove the platform This was marked as unused in 5.19 and can now be removed Cc: Lennert Buytenhek Cc: Martin Michlmayr Acked-by: Dan Williams Acked-by: Wolfram Sang # for I2C Signed-off-by: Arnd Bergmann --- arch/arm/Kconfig | 4 +- arch/arm/Kconfig.debug | 6 +- arch/arm/Makefile | 1 - arch/arm/configs/iop32x_defconfig | 126 ------------ arch/arm/kernel/entry-common.S | 15 -- arch/arm/mach-iop32x/Kconfig | 54 ----- arch/arm/mach-iop32x/Makefile | 20 -- arch/arm/mach-iop32x/adma.c | 163 --------------- arch/arm/mach-iop32x/cp6.c | 48 ----- arch/arm/mach-iop32x/em7210.c | 232 --------------------- arch/arm/mach-iop32x/glantank.c | 214 -------------------- arch/arm/mach-iop32x/glantank.h | 12 -- arch/arm/mach-iop32x/gpio-iop32x.h | 11 - arch/arm/mach-iop32x/hardware.h | 38 ---- arch/arm/mach-iop32x/i2c.c | 92 --------- arch/arm/mach-iop32x/iop3xx.h | 326 ------------------------------ arch/arm/mach-iop32x/iq31244.c | 333 ------------------------------ arch/arm/mach-iop32x/iq31244.h | 16 -- arch/arm/mach-iop32x/iq80321.c | 192 ------------------ arch/arm/mach-iop32x/iq80321.h | 16 -- arch/arm/mach-iop32x/irq.c | 95 --------- arch/arm/mach-iop32x/irqs.h | 48 ----- arch/arm/mach-iop32x/n2100.c | 367 --------------------------------- arch/arm/mach-iop32x/n2100.h | 18 -- arch/arm/mach-iop32x/pci.c | 404 ------------------------------------- arch/arm/mach-iop32x/pmu.c | 29 --- arch/arm/mach-iop32x/restart.c | 17 -- arch/arm/mach-iop32x/setup.c | 31 --- arch/arm/mach-iop32x/time.c | 179 ---------------- 29 files changed, 3 insertions(+), 3104 deletions(-) delete mode 100644 arch/arm/configs/iop32x_defconfig delete mode 100644 arch/arm/mach-iop32x/Kconfig delete mode 100644 arch/arm/mach-iop32x/Makefile delete mode 100644 arch/arm/mach-iop32x/adma.c delete mode 100644 arch/arm/mach-iop32x/cp6.c delete mode 100644 arch/arm/mach-iop32x/em7210.c delete mode 100644 arch/arm/mach-iop32x/glantank.c delete mode 100644 arch/arm/mach-iop32x/glantank.h delete mode 100644 arch/arm/mach-iop32x/gpio-iop32x.h delete mode 100644 arch/arm/mach-iop32x/hardware.h delete mode 100644 arch/arm/mach-iop32x/i2c.c delete mode 100644 arch/arm/mach-iop32x/iop3xx.h delete mode 100644 arch/arm/mach-iop32x/iq31244.c delete mode 100644 arch/arm/mach-iop32x/iq31244.h delete mode 100644 arch/arm/mach-iop32x/iq80321.c delete mode 100644 arch/arm/mach-iop32x/iq80321.h delete mode 100644 arch/arm/mach-iop32x/irq.c delete mode 100644 arch/arm/mach-iop32x/irqs.h delete mode 100644 arch/arm/mach-iop32x/n2100.c delete mode 100644 arch/arm/mach-iop32x/n2100.h delete mode 100644 arch/arm/mach-iop32x/pci.c delete mode 100644 arch/arm/mach-iop32x/pmu.c delete mode 100644 arch/arm/mach-iop32x/restart.c delete mode 100644 arch/arm/mach-iop32x/setup.c delete mode 100644 arch/arm/mach-iop32x/time.c (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 76ffb49e23fc..2efd0d91a0a0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -283,7 +283,7 @@ config PHYS_OFFSET default 0x00000000 if ARCH_FOOTBRIDGE default 0x10000000 if ARCH_OMAP1 || ARCH_RPC default 0x30000000 if ARCH_S3C24XX - default 0xa0000000 if ARCH_IOP32X || ARCH_PXA + default 0xa0000000 if ARCH_PXA default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 default 0 help @@ -460,8 +460,6 @@ source "arch/arm/mach-hpe/Kconfig" source "arch/arm/mach-imx/Kconfig" -source "arch/arm/mach-iop32x/Kconfig" - source "arch/arm/mach-ixp4xx/Kconfig" source "arch/arm/mach-keystone/Kconfig" diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 3b11e1d04625..320c93fabb21 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -1610,7 +1610,7 @@ config DEBUG_UART_PL01X # Compatibility options for 8250 config DEBUG_UART_8250 - def_bool ARCH_IOP32X || ARCH_IXP4XX || ARCH_RPC + def_bool ARCH_IXP4XX || ARCH_RPC config DEBUG_UART_PHYS hex "Physical base address of debug UART" @@ -1720,7 +1720,6 @@ config DEBUG_UART_PHYS default 0xfcb00000 if DEBUG_HI3620_UART default 0xfd883000 if DEBUG_ALPINE_UART0 default 0xfe531000 if DEBUG_STIH41X_SBC_ASC1 - default 0xfe800000 if ARCH_IOP32X default 0xfed32000 if DEBUG_STIH41X_ASC2 default 0xff690000 if DEBUG_RK32_UART2 default 0xffc02000 if DEBUG_SOCFPGA_UART0 @@ -1825,7 +1824,6 @@ config DEBUG_UART_VIRT default 0xfe018000 if DEBUG_MMP_UART3 default 0xfe100000 if DEBUG_IMX23_UART || DEBUG_IMX28_UART default 0xfe300000 if DEBUG_BCM_KONA_UART - default 0xfe800000 if ARCH_IOP32X default 0xfeb00000 if DEBUG_HI3620_UART || DEBUG_HIX5HD2_UART default 0xfeb24000 if DEBUG_RK3X_UART0 default 0xfeb26000 if DEBUG_RK3X_UART1 @@ -1867,7 +1865,7 @@ config DEBUG_UART_VIRT config DEBUG_UART_8250_SHIFT int "Register offset shift for the 8250 debug UART" depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250 - default 0 if DEBUG_FOOTBRIDGE_COM1 || ARCH_IOP32X || DEBUG_BCM_5301X || \ + default 0 if DEBUG_FOOTBRIDGE_COM1 || DEBUG_BCM_5301X || \ DEBUG_BCM_HR2 || DEBUG_OMAP7XXUART1 || DEBUG_OMAP7XXUART2 || \ DEBUG_OMAP7XXUART3 default 3 if DEBUG_MSTARV7_PMUART diff --git a/arch/arm/Makefile b/arch/arm/Makefile index d770827588c0..8fc34ec5dd84 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -188,7 +188,6 @@ machine-$(CONFIG_ARCH_GEMINI) += gemini machine-$(CONFIG_ARCH_HIGHBANK) += highbank machine-$(CONFIG_ARCH_HISI) += hisi machine-$(CONFIG_ARCH_HPE) += hpe -machine-$(CONFIG_ARCH_IOP32X) += iop32x machine-$(CONFIG_ARCH_IXP4XX) += ixp4xx machine-$(CONFIG_ARCH_KEYSTONE) += keystone machine-$(CONFIG_ARCH_LPC18XX) += lpc18xx diff --git a/arch/arm/configs/iop32x_defconfig b/arch/arm/configs/iop32x_defconfig deleted file mode 100644 index 19e30e790d35..000000000000 --- a/arch/arm/configs/iop32x_defconfig +++ /dev/null @@ -1,126 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_KALLSYMS_ALL=y -# CONFIG_ARCH_MULTI_V7 is not set -CONFIG_ARCH_IOP32X=y -CONFIG_MACH_GLANTANK=y -CONFIG_ARCH_IQ80321=y -CONFIG_ARCH_IQ31244=y -CONFIG_MACH_N2100=y -CONFIG_UNUSED_BOARD_FILES=y -CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/nfs ip=bootp cachepolicy=writealloc" -CONFIG_FPE_NWFPE=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_SLAB=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IPV6=y -# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET6_XFRM_MODE_TUNNEL is not set -# CONFIG_INET6_XFRM_MODE_BEET is not set -# CONFIG_IPV6_SIT is not set -CONFIG_MTD=y -CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y -CONFIG_MTD_REDBOOT_PARTS_READONLY=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_PHYSMAP=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_NBD=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_SG=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ATA=y -CONFIG_SATA_SIL=y -CONFIG_SATA_VITESSE=y -CONFIG_MD=y -CONFIG_BLK_DEV_MD=y -CONFIG_MD_RAID0=y -CONFIG_MD_RAID1=y -CONFIG_MD_RAID10=y -CONFIG_MD_RAID456=y -CONFIG_BLK_DEV_DM=y -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_NET_PCI=y -CONFIG_E100=y -CONFIG_E1000=y -CONFIG_R8169=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_HW_RANDOM=y -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_IOP3XX=y -# CONFIG_VGA_CONSOLE is not set -# CONFIG_USB_HID is not set -CONFIG_USB=y -CONFIG_USB_MON=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_ROOT_HUB_TT=y -CONFIG_USB_EHCI_TT_NEWSCHED=y -CONFIG_USB_UHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_RS5C372=y -CONFIG_DMADEVICES=y -CONFIG_INTEL_IOP_ADMA=y -CONFIG_NET_DMA=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -CONFIG_TMPFS=y -CONFIG_ECRYPT_FS=y -CONFIG_JFFS2_FS=y -CONFIG_CRAMFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_NFSD=y -CONFIG_KEYS=y -CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_LRW=y -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_XCBC=y -CONFIG_CRYPTO_MD4=y -CONFIG_CRYPTO_MICHAEL_MIC=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_TGR192=y -CONFIG_CRYPTO_WP512=y -CONFIG_CRYPTO_AES=y -CONFIG_CRYPTO_ANUBIS=y -CONFIG_CRYPTO_ARC4=y -CONFIG_CRYPTO_BLOWFISH=y -CONFIG_CRYPTO_CAST5=y -CONFIG_CRYPTO_CAST6=y -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_KHAZAD=y -CONFIG_CRYPTO_SERPENT=y -CONFIG_CRYPTO_TEA=y -CONFIG_CRYPTO_TWOFISH=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_LIBCRC32C=y -CONFIG_DEBUG_KERNEL=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_LL=y -CONFIG_DEBUG_LL_UART_8250=y diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index 405a607b754f..03d4c5578c5c 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -16,15 +16,6 @@ .equ NR_syscalls, __NR_syscalls - .macro arch_ret_to_user, tmp -#ifdef CONFIG_ARCH_IOP32X - mrc p15, 0, \tmp, c15, c1, 0 - tst \tmp, #(1 << 6) - bicne \tmp, \tmp, #(1 << 6) - mcrne p15, 0, \tmp, c15, c1, 0 @ Disable cp6 access -#endif - .endm - #include "entry-header.S" saved_psr .req r8 @@ -55,10 +46,6 @@ __ret_fast_syscall: movs r1, r1, lsl #16 bne fast_work_pending - - /* perform architecture specific actions before user return */ - arch_ret_to_user r1 - restore_user_regs fast = 1, offset = S_OFF UNWIND(.fnend ) ENDPROC(ret_fast_syscall) @@ -129,8 +116,6 @@ ENTRY(ret_to_user_from_irq) no_work_pending: asm_trace_hardirqs_on save = 0 - /* perform architecture specific actions before user return */ - arch_ret_to_user r1 ct_user_enter save = 0 restore_user_regs fast = 0, offset = 0 diff --git a/arch/arm/mach-iop32x/Kconfig b/arch/arm/mach-iop32x/Kconfig deleted file mode 100644 index 761fbb04faa1..000000000000 --- a/arch/arm/mach-iop32x/Kconfig +++ /dev/null @@ -1,54 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -menuconfig ARCH_IOP32X - bool "IOP32x-based platforms" - depends on ARCH_MULTI_V5 - depends on CPU_LITTLE_ENDIAN - depends on ATAGS && UNUSED_BOARD_FILES - select CPU_XSCALE - select GPIO_IOP - select GPIOLIB - select FORCE_PCI - help - Support for Intel's 80219 and IOP32X (XScale) family of - processors. - -if ARCH_IOP32X - -config MACH_EP80219 - bool - -config MACH_GLANTANK - bool "Enable support for the IO-Data GLAN Tank" - help - Say Y here if you want to run your kernel on the GLAN Tank - NAS appliance or machines from IO-Data's HDL-Gxxx, HDL-GWxxx - and HDL-GZxxx series. - -config ARCH_IQ80321 - bool "Enable support for IQ80321" - help - Say Y here if you want to run your kernel on the Intel IQ80321 - evaluation kit for the IOP321 processor. - -config ARCH_IQ31244 - bool "Enable support for EP80219/IQ31244" - select MACH_EP80219 - help - Say Y here if you want to run your kernel on the Intel EP80219 - evaluation kit for the Intel 80219 processor (a IOP321 variant) - or the IQ31244 evaluation kit for the IOP321 processor. - -config MACH_N2100 - bool "Enable support for the Thecus n2100" - help - Say Y here if you want to run your kernel on the Thecus n2100 - NAS appliance. - -config MACH_EM7210 - bool "Enable support for the Lanner EM7210" - help - Say Y here if you want to run your kernel on the Lanner EM7210 - board. Say also Y here if you have a SS4000e Baxter Creek NAS - appliance." - -endif diff --git a/arch/arm/mach-iop32x/Makefile b/arch/arm/mach-iop32x/Makefile deleted file mode 100644 index c8018ef5c6a9..000000000000 --- a/arch/arm/mach-iop32x/Makefile +++ /dev/null @@ -1,20 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Makefile for the linux kernel. -# - -obj-$(CONFIG_ARCH_IOP32X) += irq.o -obj-$(CONFIG_ARCH_IOP32X) += i2c.o -obj-$(CONFIG_ARCH_IOP32X) += pci.o -obj-$(CONFIG_ARCH_IOP32X) += setup.o -obj-$(CONFIG_ARCH_IOP32X) += time.o -obj-$(CONFIG_ARCH_IOP32X) += cp6.o -obj-$(CONFIG_ARCH_IOP32X) += adma.o -obj-$(CONFIG_ARCH_IOP32X) += pmu.o -obj-$(CONFIG_ARCH_IOP32X) += restart.o - -obj-$(CONFIG_MACH_GLANTANK) += glantank.o -obj-$(CONFIG_ARCH_IQ80321) += iq80321.o -obj-$(CONFIG_ARCH_IQ31244) += iq31244.o -obj-$(CONFIG_MACH_N2100) += n2100.o -obj-$(CONFIG_MACH_EM7210) += em7210.o diff --git a/arch/arm/mach-iop32x/adma.c b/arch/arm/mach-iop32x/adma.c deleted file mode 100644 index 764bcbff98df..000000000000 --- a/arch/arm/mach-iop32x/adma.c +++ /dev/null @@ -1,163 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * platform device definitions for the iop3xx dma/xor engines - * Copyright © 2006, Intel Corporation. - */ -#include -#include -#include - -#include "iop3xx.h" -#include "irqs.h" - -#define IRQ_DMA0_EOT IRQ_IOP32X_DMA0_EOT -#define IRQ_DMA0_EOC IRQ_IOP32X_DMA0_EOC -#define IRQ_DMA0_ERR IRQ_IOP32X_DMA0_ERR - -#define IRQ_DMA1_EOT IRQ_IOP32X_DMA1_EOT -#define IRQ_DMA1_EOC IRQ_IOP32X_DMA1_EOC -#define IRQ_DMA1_ERR IRQ_IOP32X_DMA1_ERR - -#define IRQ_AA_EOT IRQ_IOP32X_AA_EOT -#define IRQ_AA_EOC IRQ_IOP32X_AA_EOC -#define IRQ_AA_ERR IRQ_IOP32X_AA_ERR - -/* AAU and DMA Channels */ -static struct resource iop3xx_dma_0_resources[] = { - [0] = { - .start = IOP3XX_DMA_PHYS_BASE(0), - .end = IOP3XX_DMA_UPPER_PA(0), - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_DMA0_EOT, - .end = IRQ_DMA0_EOT, - .flags = IORESOURCE_IRQ - }, - [2] = { - .start = IRQ_DMA0_EOC, - .end = IRQ_DMA0_EOC, - .flags = IORESOURCE_IRQ - }, - [3] = { - .start = IRQ_DMA0_ERR, - .end = IRQ_DMA0_ERR, - .flags = IORESOURCE_IRQ - } -}; - -static struct resource iop3xx_dma_1_resources[] = { - [0] = { - .start = IOP3XX_DMA_PHYS_BASE(1), - .end = IOP3XX_DMA_UPPER_PA(1), - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_DMA1_EOT, - .end = IRQ_DMA1_EOT, - .flags = IORESOURCE_IRQ - }, - [2] = { - .start = IRQ_DMA1_EOC, - .end = IRQ_DMA1_EOC, - .flags = IORESOURCE_IRQ - }, - [3] = { - .start = IRQ_DMA1_ERR, - .end = IRQ_DMA1_ERR, - .flags = IORESOURCE_IRQ - } -}; - - -static struct resource iop3xx_aau_resources[] = { - [0] = { - .start = IOP3XX_AAU_PHYS_BASE, - .end = IOP3XX_AAU_UPPER_PA, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_AA_EOT, - .end = IRQ_AA_EOT, - .flags = IORESOURCE_IRQ - }, - [2] = { - .start = IRQ_AA_EOC, - .end = IRQ_AA_EOC, - .flags = IORESOURCE_IRQ - }, - [3] = { - .start = IRQ_AA_ERR, - .end = IRQ_AA_ERR, - .flags = IORESOURCE_IRQ - } -}; - -static u64 iop3xx_adma_dmamask = DMA_BIT_MASK(32); - -static struct iop_adma_platform_data iop3xx_dma_0_data = { - .hw_id = DMA0_ID, - .pool_size = PAGE_SIZE, -}; - -static struct iop_adma_platform_data iop3xx_dma_1_data = { - .hw_id = DMA1_ID, - .pool_size = PAGE_SIZE, -}; - -static struct iop_adma_platform_data iop3xx_aau_data = { - .hw_id = AAU_ID, - .pool_size = 3 * PAGE_SIZE, -}; - -struct platform_device iop3xx_dma_0_channel = { - .name = "iop-adma", - .id = 0, - .num_resources = 4, - .resource = iop3xx_dma_0_resources, - .dev = { - .dma_mask = &iop3xx_adma_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = (void *) &iop3xx_dma_0_data, - }, -}; - -struct platform_device iop3xx_dma_1_channel = { - .name = "iop-adma", - .id = 1, - .num_resources = 4, - .resource = iop3xx_dma_1_resources, - .dev = { - .dma_mask = &iop3xx_adma_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = (void *) &iop3xx_dma_1_data, - }, -}; - -struct platform_device iop3xx_aau_channel = { - .name = "iop-adma", - .id = 2, - .num_resources = 4, - .resource = iop3xx_aau_resources, - .dev = { - .dma_mask = &iop3xx_adma_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = (void *) &iop3xx_aau_data, - }, -}; - -static int __init iop3xx_adma_cap_init(void) -{ - dma_cap_set(DMA_MEMCPY, iop3xx_dma_0_data.cap_mask); - dma_cap_set(DMA_INTERRUPT, iop3xx_dma_0_data.cap_mask); - - dma_cap_set(DMA_MEMCPY, iop3xx_dma_1_data.cap_mask); - dma_cap_set(DMA_INTERRUPT, iop3xx_dma_1_data.cap_mask); - - dma_cap_set(DMA_XOR, iop3xx_aau_data.cap_mask); - dma_cap_set(DMA_INTERRUPT, iop3xx_aau_data.cap_mask); - - return 0; -} - -arch_initcall(iop3xx_adma_cap_init); diff --git a/arch/arm/mach-iop32x/cp6.c b/arch/arm/mach-iop32x/cp6.c deleted file mode 100644 index 7135a0ac9949..000000000000 --- a/arch/arm/mach-iop32x/cp6.c +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * IOP Coprocessor-6 access handler - * Copyright (c) 2006, Intel Corporation. - */ -#include -#include -#include - -#include "iop3xx.h" - -void iop_enable_cp6(void) -{ - u32 temp; - - /* enable cp6 access */ - asm volatile ( - "mrc p15, 0, %0, c15, c1, 0\n\t" - "orr %0, %0, #(1 << 6)\n\t" - "mcr p15, 0, %0, c15, c1, 0\n\t" - "mrc p15, 0, %0, c15, c1, 0\n\t" - "mov %0, %0\n\t" - "sub pc, pc, #4 @ cp_wait\n\t" - : "=r"(temp)); -} - -static int cp6_trap(struct pt_regs *regs, unsigned int instr) -{ - iop_enable_cp6(); - - return 0; -} - -/* permit kernel space cp6 access - * deny user space cp6 access - */ -static struct undef_hook cp6_hook = { - .instr_mask = 0x0f000ff0, - .instr_val = 0x0e000610, - .cpsr_mask = MODE_MASK, - .cpsr_val = SVC_MODE, - .fn = cp6_trap, -}; - -void __init iop_init_cp6_handler(void) -{ - register_undef_hook(&cp6_hook); -} diff --git a/arch/arm/mach-iop32x/em7210.c b/arch/arm/mach-iop32x/em7210.c deleted file mode 100644 index ac130aba5a6e..000000000000 --- a/arch/arm/mach-iop32x/em7210.c +++ /dev/null @@ -1,232 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/mach-iop32x/em7210.c - * - * Board support code for the Lanner EM7210 platforms. - * - * Based on arch/arm/mach-iop32x/iq31244.c file. - * - * Copyright (C) 2007 Arnaud Patard - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "hardware.h" -#include "gpio-iop32x.h" -#include "irqs.h" - -static void __init em7210_timer_init(void) -{ - /* http://www.kwaak.net/fotos/fotos-nas/slide_24.html */ - /* 33.333 MHz crystal. */ - iop_init_time(200000000); -} - -/* - * EM7210 RTC - */ -static struct i2c_board_info __initdata em7210_i2c_devices[] = { - { - I2C_BOARD_INFO("rs5c372a", 0x32), - }, -}; - -/* - * EM7210 I/O - */ -static struct map_desc em7210_io_desc[] __initdata = { - { /* on-board devices */ - .virtual = IQ31244_UART, - .pfn = __phys_to_pfn(IQ31244_UART), - .length = 0x00100000, - .type = MT_DEVICE, - }, -}; - -void __init em7210_map_io(void) -{ - iop3xx_map_io(); - iotable_init(em7210_io_desc, ARRAY_SIZE(em7210_io_desc)); -} - - -/* - * EM7210 PCI - */ -#define INTA IRQ_IOP32X_XINT0 -#define INTB IRQ_IOP32X_XINT1 -#define INTC IRQ_IOP32X_XINT2 -#define INTD IRQ_IOP32X_XINT3 - -static int __init -em7210_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - static int pci_irq_table[][4] = { - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - {INTB, INTB, INTB, INTB}, /* console / uart */ - {INTA, INTA, INTA, INTA}, /* 1st 82541 */ - {INTD, INTD, INTD, INTD}, /* 2nd 82541 */ - {INTC, INTC, INTC, INTC}, /* GD31244 */ - {INTD, INTA, INTA, INTA}, /* mini-PCI */ - {INTD, INTC, INTA, INTA}, /* NEC USB */ - }; - - if (pin < 1 || pin > 4) - return -1; - - return pci_irq_table[slot % 6][pin - 1]; -} - -static struct hw_pci em7210_pci __initdata = { - .nr_controllers = 1, - .ops = &iop3xx_ops, - .setup = iop3xx_pci_setup, - .preinit = iop3xx_pci_preinit, - .map_irq = em7210_pci_map_irq, -}; - -static int __init em7210_pci_init(void) -{ - if (machine_is_em7210()) - pci_common_init(&em7210_pci); - - return 0; -} - -subsys_initcall(em7210_pci_init); - - -/* - * EM7210 Flash - */ -static struct physmap_flash_data em7210_flash_data = { - .width = 2, -}; - -static struct resource em7210_flash_resource = { - .start = 0xf0000000, - .end = 0xf1ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device em7210_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &em7210_flash_data, - }, - .num_resources = 1, - .resource = &em7210_flash_resource, -}; - - -/* - * EM7210 UART - * The physical address of the serial port is 0xfe800000, - * so it can be used for physical and virtual address. - */ -static struct plat_serial8250_port em7210_serial_port[] = { - { - .mapbase = IQ31244_UART, - .membase = (char *)IQ31244_UART, - .irq = IRQ_IOP32X_XINT1, - .flags = UPF_SKIP_TEST, - .iotype = UPIO_MEM, - .regshift = 0, - .uartclk = 1843200, - }, - { }, -}; - -static struct resource em7210_uart_resource = { - .start = IQ31244_UART, - .end = IQ31244_UART + 7, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device em7210_serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = em7210_serial_port, - }, - .num_resources = 1, - .resource = &em7210_uart_resource, -}; - -#define EM7210_HARDWARE_POWER 0 - -void em7210_power_off(void) -{ - int ret; - - ret = gpio_direction_output(EM7210_HARDWARE_POWER, 1); - if (ret) - pr_crit("could not drive power off GPIO high\n"); -} - -static int __init em7210_request_gpios(void) -{ - int ret; - - if (!machine_is_em7210()) - return 0; - - ret = gpio_request(EM7210_HARDWARE_POWER, "power"); - if (ret) { - pr_err("could not request power off GPIO\n"); - return 0; - } - - pm_power_off = em7210_power_off; - - return 0; -} -device_initcall(em7210_request_gpios); - -static void __init em7210_init_machine(void) -{ - register_iop32x_gpio(); - platform_device_register(&em7210_serial_device); - gpiod_add_lookup_table(&iop3xx_i2c0_gpio_lookup); - gpiod_add_lookup_table(&iop3xx_i2c1_gpio_lookup); - platform_device_register(&iop3xx_i2c0_device); - platform_device_register(&iop3xx_i2c1_device); - platform_device_register(&em7210_flash_device); - platform_device_register(&iop3xx_dma_0_channel); - platform_device_register(&iop3xx_dma_1_channel); - - i2c_register_board_info(0, em7210_i2c_devices, - ARRAY_SIZE(em7210_i2c_devices)); -} - -MACHINE_START(EM7210, "Lanner EM7210") - .atag_offset = 0x100, - .nr_irqs = IOP32X_NR_IRQS, - .map_io = em7210_map_io, - .init_irq = iop32x_init_irq, - .init_time = em7210_timer_init, - .init_machine = em7210_init_machine, - .restart = iop3xx_restart, -MACHINE_END diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c deleted file mode 100644 index cd6e7da2ea10..000000000000 --- a/arch/arm/mach-iop32x/glantank.c +++ /dev/null @@ -1,214 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-iop32x/glantank.c - * - * Board support code for the GLAN Tank. - * - * Copyright (C) 2006, 2007 Martin Michlmayr - * Copyright (C) 2006 Lennert Buytenhek - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "hardware.h" -#include "gpio-iop32x.h" -#include "irqs.h" - -/* - * GLAN Tank timer tick configuration. - */ -static void __init glantank_timer_init(void) -{ - /* 33.333 MHz crystal. */ - iop_init_time(200000000); -} - - -/* - * GLAN Tank I/O. - */ -static struct map_desc glantank_io_desc[] __initdata = { - { /* on-board devices */ - .virtual = GLANTANK_UART, - .pfn = __phys_to_pfn(GLANTANK_UART), - .length = 0x00100000, - .type = MT_DEVICE - }, -}; - -void __init glantank_map_io(void) -{ - iop3xx_map_io(); - iotable_init(glantank_io_desc, ARRAY_SIZE(glantank_io_desc)); -} - - -/* - * GLAN Tank PCI. - */ -#define INTA IRQ_IOP32X_XINT0 -#define INTB IRQ_IOP32X_XINT1 -#define INTC IRQ_IOP32X_XINT2 -#define INTD IRQ_IOP32X_XINT3 - -static int __init -glantank_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - static int pci_irq_table[][4] = { - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - {INTD, INTD, INTD, INTD}, /* UART (8250) */ - {INTA, INTA, INTA, INTA}, /* Ethernet (E1000) */ - {INTB, INTB, INTB, INTB}, /* IDE (AEC6280R) */ - {INTC, INTC, INTC, INTC}, /* USB (NEC) */ - }; - - BUG_ON(pin < 1 || pin > 4); - - return pci_irq_table[slot % 4][pin - 1]; -} - -static struct hw_pci glantank_pci __initdata = { - .nr_controllers = 1, - .ops = &iop3xx_ops, - .setup = iop3xx_pci_setup, - .preinit = iop3xx_pci_preinit, - .map_irq = glantank_pci_map_irq, -}; - -static int __init glantank_pci_init(void) -{ - if (machine_is_glantank()) - pci_common_init(&glantank_pci); - - return 0; -} - -subsys_initcall(glantank_pci_init); - - -/* - * GLAN Tank machine initialization. - */ -static struct physmap_flash_data glantank_flash_data = { - .width = 2, -}; - -static struct resource glantank_flash_resource = { - .start = 0xf0000000, - .end = 0xf007ffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device glantank_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &glantank_flash_data, - }, - .num_resources = 1, - .resource = &glantank_flash_resource, -}; - -static struct plat_serial8250_port glantank_serial_port[] = { - { - .mapbase = GLANTANK_UART, - .membase = (char *)GLANTANK_UART, - .irq = IRQ_IOP32X_XINT3, - .flags = UPF_SKIP_TEST, - .iotype = UPIO_MEM, - .regshift = 0, - .uartclk = 1843200, - }, - { }, -}; - -static struct resource glantank_uart_resource = { - .start = GLANTANK_UART, - .end = GLANTANK_UART + 7, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device glantank_serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = glantank_serial_port, - }, - .num_resources = 1, - .resource = &glantank_uart_resource, -}; - -static struct f75375s_platform_data glantank_f75375s = { - .pwm = { 255, 255 }, - .pwm_enable = { 0, 0 }, -}; - -static struct i2c_board_info __initdata glantank_i2c_devices[] = { - { - I2C_BOARD_INFO("rs5c372a", 0x32), - }, - { - I2C_BOARD_INFO("f75375", 0x2e), - .platform_data = &glantank_f75375s, - }, -}; - -static void glantank_power_off(void) -{ - __raw_writeb(0x01, IOMEM(0xfe8d0004)); - - while (1) - ; -} - -static void __init glantank_init_machine(void) -{ - register_iop32x_gpio(); - gpiod_add_lookup_table(&iop3xx_i2c0_gpio_lookup); - gpiod_add_lookup_table(&iop3xx_i2c1_gpio_lookup); - platform_device_register(&iop3xx_i2c0_device); - platform_device_register(&iop3xx_i2c1_device); - platform_device_register(&glantank_flash_device); - platform_device_register(&glantank_serial_device); - platform_device_register(&iop3xx_dma_0_channel); - platform_device_register(&iop3xx_dma_1_channel); - - i2c_register_board_info(0, glantank_i2c_devices, - ARRAY_SIZE(glantank_i2c_devices)); - - pm_power_off = glantank_power_off; -} - -MACHINE_START(GLANTANK, "GLAN Tank") - /* Maintainer: Lennert Buytenhek */ - .atag_offset = 0x100, - .nr_irqs = IOP32X_NR_IRQS, - .map_io = glantank_map_io, - .init_irq = iop32x_init_irq, - .init_time = glantank_timer_init, - .init_machine = glantank_init_machine, - .restart = iop3xx_restart, -MACHINE_END diff --git a/arch/arm/mach-iop32x/glantank.h b/arch/arm/mach-iop32x/glantank.h deleted file mode 100644 index f38e86b82c3d..000000000000 --- a/arch/arm/mach-iop32x/glantank.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * IO-Data GLAN Tank board registers - */ - -#ifndef __GLANTANK_H -#define __GLANTANK_H - -#define GLANTANK_UART 0xfe800000 /* UART */ - - -#endif diff --git a/arch/arm/mach-iop32x/gpio-iop32x.h b/arch/arm/mach-iop32x/gpio-iop32x.h deleted file mode 100644 index 20af87e4c5e8..000000000000 --- a/arch/arm/mach-iop32x/gpio-iop32x.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -static struct resource iop32x_gpio_res[] = { - DEFINE_RES_MEM((IOP3XX_PERIPHERAL_PHYS_BASE + 0x07c4), 0x10), -}; - -static inline void register_iop32x_gpio(void) -{ - platform_device_register_simple("gpio-iop", 0, - iop32x_gpio_res, - ARRAY_SIZE(iop32x_gpio_res)); -} diff --git a/arch/arm/mach-iop32x/hardware.h b/arch/arm/mach-iop32x/hardware.h deleted file mode 100644 index 43ab4fb8f9b0..000000000000 --- a/arch/arm/mach-iop32x/hardware.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __HARDWARE_H -#define __HARDWARE_H - -#include - -/* - * Note about PCI IO space mappings - * - * To make IO space accesses efficient, we store virtual addresses in - * the IO resources. - * - * The PCI IO space is located at virtual 0xfe000000 from physical - * 0x90000000. The PCI BARs must be programmed with physical addresses, - * but when we read them, we convert them to virtual addresses. See - * arch/arm/plat-iop/pci.c. - */ - -#ifndef __ASSEMBLY__ -void iop32x_init_irq(void); -#endif - - -/* - * Generic chipset bits - */ -#include "iop3xx.h" - -/* - * Board specific bits - */ -#include "glantank.h" -#include "iq80321.h" -#include "iq31244.h" -#include "n2100.h" - - -#endif diff --git a/arch/arm/mach-iop32x/i2c.c b/arch/arm/mach-iop32x/i2c.c deleted file mode 100644 index e422286af469..000000000000 --- a/arch/arm/mach-iop32x/i2c.c +++ /dev/null @@ -1,92 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/plat-iop/i2c.c - * - * Author: Nicolas Pitre - * Copyright (C) 2001 MontaVista Software, Inc. - * Copyright (C) 2004 Intel Corporation. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "hardware.h" -#include "iop3xx.h" -#include "irqs.h" - -/* - * Each of the I2C busses have corresponding GPIO lines, and the driver - * need to access these directly to drive the bus low at times. - */ - -struct gpiod_lookup_table iop3xx_i2c0_gpio_lookup = { - .dev_id = "IOP3xx-I2C.0", - .table = { - GPIO_LOOKUP("gpio-iop", 7, "scl", GPIO_ACTIVE_HIGH), - GPIO_LOOKUP("gpio-iop", 6, "sda", GPIO_ACTIVE_HIGH), - { } - }, -}; - -struct gpiod_lookup_table iop3xx_i2c1_gpio_lookup = { - .dev_id = "IOP3xx-I2C.1", - .table = { - GPIO_LOOKUP("gpio-iop", 5, "scl", GPIO_ACTIVE_HIGH), - GPIO_LOOKUP("gpio-iop", 4, "sda", GPIO_ACTIVE_HIGH), - { } - }, -}; - -static struct resource iop3xx_i2c0_resources[] = { - [0] = { - .start = 0xfffff680, - .end = 0xfffff697, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IOP32X_I2C_0, - .end = IRQ_IOP32X_I2C_0, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device iop3xx_i2c0_device = { - .name = "IOP3xx-I2C", - .id = 0, - .num_resources = 2, - .resource = iop3xx_i2c0_resources, -}; - - -static struct resource iop3xx_i2c1_resources[] = { - [0] = { - .start = 0xfffff6a0, - .end = 0xfffff6b7, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IOP32X_I2C_1, - .end = IRQ_IOP32X_I2C_1, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device iop3xx_i2c1_device = { - .name = "IOP3xx-I2C", - .id = 1, - .num_resources = 2, - .resource = iop3xx_i2c1_resources, -}; diff --git a/arch/arm/mach-iop32x/iop3xx.h b/arch/arm/mach-iop32x/iop3xx.h deleted file mode 100644 index a6ec7ebadb35..000000000000 --- a/arch/arm/mach-iop32x/iop3xx.h +++ /dev/null @@ -1,326 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Intel IOP32X and IOP33X register definitions - * - * Author: Rory Bolt - * Copyright (C) 2002 Rory Bolt - * Copyright (C) 2004 Intel Corp. - */ - -#ifndef __IOP3XX_H -#define __IOP3XX_H - -/* - * Peripherals that are shared between the iop32x and iop33x but - * located at different addresses. - */ -#define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07e0 + (reg)) - -#include "iop3xx.h" - -/* ATU Parameters - * set up a 1:1 bus to physical ram relationship - * w/ physical ram on top of pci in the memory map - */ -#define IOP32X_MAX_RAM_SIZE 0x40000000UL -#define IOP3XX_MAX_RAM_SIZE IOP32X_MAX_RAM_SIZE -#define IOP3XX_PCI_LOWER_MEM_BA 0x80000000 - -/* - * IOP3XX GPIO handling - */ -#define IOP3XX_GPIO_LINE(x) (x) - -#ifndef __ASSEMBLY__ -extern int init_atu; -extern int iop3xx_get_init_atu(void); -#endif - - -/* - * IOP3XX processor registers - */ -#define IOP3XX_PERIPHERAL_PHYS_BASE 0xffffe000 -#define IOP3XX_PERIPHERAL_VIRT_BASE 0xfedfe000 -#define IOP3XX_PERIPHERAL_SIZE 0x00002000 -#define IOP3XX_PERIPHERAL_UPPER_PA (IOP3XX_PERIPHERAL_PHYS_BASE +\ - IOP3XX_PERIPHERAL_SIZE - 1) -#define IOP3XX_PERIPHERAL_UPPER_VA (IOP3XX_PERIPHERAL_VIRT_BASE +\ - IOP3XX_PERIPHERAL_SIZE - 1) -#define IOP3XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) (addr) -\ - (IOP3XX_PERIPHERAL_PHYS_BASE\ - - IOP3XX_PERIPHERAL_VIRT_BASE)) -#define IOP3XX_REG_ADDR(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + (reg)) - -/* Address Translation Unit */ -#define IOP3XX_ATUVID (volatile u16 *)IOP3XX_REG_ADDR(0x0100) -#define IOP3XX_ATUDID (volatile u16 *)IOP3XX_REG_ADDR(0x0102) -#define IOP3XX_ATUCMD (volatile u16 *)IOP3XX_REG_ADDR(0x0104) -#define IOP3XX_ATUSR (volatile u16 *)IOP3XX_REG_ADDR(0x0106) -#define IOP3XX_ATURID (volatile u8 *)IOP3XX_REG_ADDR(0x0108) -#define IOP3XX_ATUCCR (volatile u32 *)IOP3XX_REG_ADDR(0x0109) -#define IOP3XX_ATUCLSR (volatile u8 *)IOP3XX_REG_ADDR(0x010c) -#define IOP3XX_ATULT (volatile u8 *)IOP3XX_REG_ADDR(0x010d) -#define IOP3XX_ATUHTR (volatile u8 *)IOP3XX_REG_ADDR(0x010e) -#define IOP3XX_ATUBIST (volatile u8 *)IOP3XX_REG_ADDR(0x010f) -#define IOP3XX_IABAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0110) -#define IOP3XX_IAUBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0114) -#define IOP3XX_IABAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0118) -#define IOP3XX_IAUBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x011c) -#define IOP3XX_IABAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0120) -#define IOP3XX_IAUBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0124) -#define IOP3XX_ASVIR (volatile u16 *)IOP3XX_REG_ADDR(0x012c) -#define IOP3XX_ASIR (volatile u16 *)IOP3XX_REG_ADDR(0x012e) -#define IOP3XX_ERBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0130) -#define IOP3XX_ATUILR (volatile u8 *)IOP3XX_REG_ADDR(0x013c) -#define IOP3XX_ATUIPR (volatile u8 *)IOP3XX_REG_ADDR(0x013d) -#define IOP3XX_ATUMGNT (volatile u8 *)IOP3XX_REG_ADDR(0x013e) -#define IOP3XX_ATUMLAT (volatile u8 *)IOP3XX_REG_ADDR(0x013f) -#define IOP3XX_IALR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0140) -#define IOP3XX_IATVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0144) -#define IOP3XX_ERLR (volatile u32 *)IOP3XX_REG_ADDR(0x0148) -#define IOP3XX_ERTVR (volatile u32 *)IOP3XX_REG_ADDR(0x014c) -#define IOP3XX_IALR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0150) -#define IOP3XX_IALR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0154) -#define IOP3XX_IATVR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0158) -#define IOP3XX_OIOWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x015c) -#define IOP3XX_OMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0160) -#define IOP3XX_OUMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0164) -#define IOP3XX_OMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0168) -#define IOP3XX_OUMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x016c) -#define IOP3XX_OUDWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x0178) -#define IOP3XX_ATUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0180) -#define IOP3XX_PCSR (volatile u32 *)IOP3XX_REG_ADDR(0x0184) -#define IOP3XX_ATUISR (volatile u32 *)IOP3XX_REG_ADDR(0x0188) -#define IOP3XX_ATUIMR (volatile u32 *)IOP3XX_REG_ADDR(0x018c) -#define IOP3XX_IABAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0190) -#define IOP3XX_IAUBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0194) -#define IOP3XX_IALR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0198) -#define IOP3XX_IATVR3 (volatile u32 *)IOP3XX_REG_ADDR(0x019c) -#define IOP3XX_OCCAR (volatile u32 *)IOP3XX_REG_ADDR(0x01a4) -#define IOP3XX_OCCDR (volatile u32 *)IOP3XX_REG_ADDR(0x01ac) -#define IOP3XX_PDSCR (volatile u32 *)IOP3XX_REG_ADDR(0x01bc) -#define IOP3XX_PMCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01c0) -#define IOP3XX_PMNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01c1) -#define IOP3XX_APMCR (volatile u16 *)IOP3XX_REG_ADDR(0x01c2) -#define IOP3XX_APMCSR (volatile u16 *)IOP3XX_REG_ADDR(0x01c4) -#define IOP3XX_PCIXCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01e0) -#define IOP3XX_PCIXNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01e1) -#define IOP3XX_PCIXCMD (volatile u16 *)IOP3XX_REG_ADDR(0x01e2) -#define IOP3XX_PCIXSR (volatile u32 *)IOP3XX_REG_ADDR(0x01e4) -#define IOP3XX_PCIIRSR (volatile u32 *)IOP3XX_REG_ADDR(0x01ec) -#define IOP3XX_PCSR_OUT_Q_BUSY (1 << 15) -#define IOP3XX_PCSR_IN_Q_BUSY (1 << 14) -#define IOP3XX_ATUCR_OUT_EN (1 << 1) - -#define IOP3XX_INIT_ATU_DEFAULT 0 -#define IOP3XX_INIT_ATU_DISABLE -1 -#define IOP3XX_INIT_ATU_ENABLE 1 - -/* Messaging Unit */ -#define IOP3XX_IMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0310) -#define IOP3XX_IMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0314) -#define IOP3XX_OMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0318) -#define IOP3XX_OMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x031c) -#define IOP3XX_IDR (volatile u32 *)IOP3XX_REG_ADDR(0x0320) -#define IOP3XX_IISR (volatile u32 *)IOP3XX_REG_ADDR(0x0324) -#define IOP3XX_IIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0328) -#define IOP3XX_ODR (volatile u32 *)IOP3XX_REG_ADDR(0x032c) -#define IOP3XX_OISR (volatile u32 *)IOP3XX_REG_ADDR(0x0330) -#define IOP3XX_OIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0334) -#define IOP3XX_MUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0350) -#define IOP3XX_QBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0354) -#define IOP3XX_IFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0360) -#define IOP3XX_IFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0364) -#define IOP3XX_IPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0368) -#define IOP3XX_IPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x036c) -#define IOP3XX_OFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0370) -#define IOP3XX_OFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0374) -#define IOP3XX_OPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0378) -#define IOP3XX_OPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x037c) -#define IOP3XX_IAR (volatile u32 *)IOP3XX_REG_ADDR(0x0380) - -/* DMA Controller */ -#define IOP3XX_DMA_PHYS_BASE(chan) (IOP3XX_PERIPHERAL_PHYS_BASE + \ - (0x400 + (chan << 6))) -#define IOP3XX_DMA_UPPER_PA(chan) (IOP3XX_DMA_PHYS_BASE(chan) + 0x27) - -/* Peripheral bus interface */ -#define IOP3XX_PBCR (volatile u32 *)IOP3XX_REG_ADDR(0x0680) -#define IOP3XX_PBISR (volatile u32 *)IOP3XX_REG_ADDR(0x0684) -#define IOP3XX_PBBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0688) -#define IOP3XX_PBLR0 (volatile u32 *)IOP3XX_REG_ADDR(0x068c) -#define IOP3XX_PBBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0690) -#define IOP3XX_PBLR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0694) -#define IOP3XX_PBBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0698) -#define IOP3XX_PBLR2 (volatile u32 *)IOP3XX_REG_ADDR(0x069c) -#define IOP3XX_PBBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a0) -#define IOP3XX_PBLR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a4) -#define IOP3XX_PBBAR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06a8) -#define IOP3XX_PBLR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06ac) -#define IOP3XX_PBBAR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b0) -#define IOP3XX_PBLR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b4) -#define IOP3XX_PMBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x06c0) -#define IOP3XX_PMBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x06e0) -#define IOP3XX_PMBR2 (volatile u32 *)IOP3XX_REG_ADDR(0x06e4) - -/* Peripheral performance monitoring unit */ -#define IOP3XX_GTMR (volatile u32 *)IOP3XX_REG_ADDR(0x0700) -#define IOP3XX_ESR (volatile u32 *)IOP3XX_REG_ADDR(0x0704) -#define IOP3XX_EMISR (volatile u32 *)IOP3XX_REG_ADDR(0x0708) -#define IOP3XX_GTSR (volatile u32 *)IOP3XX_REG_ADDR(0x0710) -/* PERCR0 DOESN'T EXIST - index from 1! */ -#define IOP3XX_PERCR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0710) - -/* Timers */ -#define IOP3XX_TU_TMR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0000) -#define IOP3XX_TU_TMR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0004) -#define IOP3XX_TU_TCR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0008) -#define IOP3XX_TU_TCR1 (volatile u32 *)IOP3XX_TIMER_REG(0x000c) -#define IOP3XX_TU_TRR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0010) -#define IOP3XX_TU_TRR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0014) -#define IOP3XX_TU_TISR (volatile u32 *)IOP3XX_TIMER_REG(0x0018) -#define IOP3XX_TU_WDTCR (volatile u32 *)IOP3XX_TIMER_REG(0x001c) -#define IOP_TMR_EN 0x02 -#define IOP_TMR_RELOAD 0x04 -#define IOP_TMR_PRIVILEGED 0x08 -#define IOP_TMR_RATIO_1_1 0x00 - -/* Watchdog timer definitions */ -#define IOP_WDTCR_EN_ARM 0x1e1e1e1e -#define IOP_WDTCR_EN 0xe1e1e1e1 -/* iop3xx does not support stopping the watchdog, so we just re-arm */ -#define IOP_WDTCR_DIS_ARM (IOP_WDTCR_EN_ARM) -#define IOP_WDTCR_DIS (IOP_WDTCR_EN) - -/* Application accelerator unit */ -#define IOP3XX_AAU_PHYS_BASE (IOP3XX_PERIPHERAL_PHYS_BASE + 0x800) -#define IOP3XX_AAU_UPPER_PA (IOP3XX_AAU_PHYS_BASE + 0xa7) - -/* I2C bus interface unit */ -#define IOP3XX_ICR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1680) -#define IOP3XX_ISR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1684) -#define IOP3XX_ISAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1688) -#define IOP3XX_IDBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x168c) -#define IOP3XX_IBMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1694) -#define IOP3XX_ICR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a0) -#define IOP3XX_ISR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a4) -#define IOP3XX_ISAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a8) -#define IOP3XX_IDBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16ac) -#define IOP3XX_IBMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16b4) - - -/* - * IOP3XX I/O and Mem space regions for PCI autoconfiguration - */ -#define IOP3XX_PCI_LOWER_MEM_PA 0x80000000 -#define IOP3XX_PCI_MEM_WINDOW_SIZE 0x08000000 - -#define IOP3XX_PCI_LOWER_IO_PA 0x90000000 -#define IOP3XX_PCI_LOWER_IO_BA 0x00000000 - -#ifndef __ASSEMBLY__ - -#include -#include - -void iop3xx_map_io(void); -void iop_enable_cp6(void); -void iop_init_cp6_handler(void); -void iop_init_time(unsigned long tickrate); -void iop3xx_restart(enum reboot_mode, const char *); - -static inline u32 read_tmr0(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c0, c1, 0" : "=r" (val)); - return val; -} - -static inline void write_tmr0(u32 val) -{ - asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (val)); -} - -static inline void write_tmr1(u32 val) -{ - asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (val)); -} - -static inline u32 read_tcr0(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c2, c1, 0" : "=r" (val)); - return val; -} - -static inline void write_tcr0(u32 val) -{ - asm volatile("mcr p6, 0, %0, c2, c1, 0" : : "r" (val)); -} - -static inline u32 read_tcr1(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c3, c1, 0" : "=r" (val)); - return val; -} - -static inline void write_tcr1(u32 val) -{ - asm volatile("mcr p6, 0, %0, c3, c1, 0" : : "r" (val)); -} - -static inline void write_trr0(u32 val) -{ - asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (val)); -} - -static inline void write_trr1(u32 val) -{ - asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (val)); -} - -static inline void write_tisr(u32 val) -{ - asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (val)); -} - -static inline u32 read_wdtcr(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c7, c1, 0":"=r" (val)); - return val; -} -static inline void write_wdtcr(u32 val) -{ - asm volatile("mcr p6, 0, %0, c7, c1, 0"::"r" (val)); -} - -extern unsigned long get_iop_tick_rate(void); - -/* only iop13xx has these registers, we define these to present a - * common register interface for the iop_wdt driver. - */ -#define IOP_RCSR_WDT (0) -static inline u32 read_rcsr(void) -{ - return 0; -} -static inline void write_wdtsr(u32 val) -{ - do { } while (0); -} - -extern struct platform_device iop3xx_dma_0_channel; -extern struct platform_device iop3xx_dma_1_channel; -extern struct platform_device iop3xx_aau_channel; -extern struct platform_device iop3xx_i2c0_device; -extern struct platform_device iop3xx_i2c1_device; -extern struct gpiod_lookup_table iop3xx_i2c0_gpio_lookup; -extern struct gpiod_lookup_table iop3xx_i2c1_gpio_lookup; - -#endif - - -#endif diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c deleted file mode 100644 index 8b4c29d17265..000000000000 --- a/arch/arm/mach-iop32x/iq31244.c +++ /dev/null @@ -1,333 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-iop32x/iq31244.c - * - * Board support code for the Intel EP80219 and IQ31244 platforms. - * - * Author: Rory Bolt - * Copyright (C) 2002 Rory Bolt - * Copyright 2003 (c) MontaVista, Software, Inc. - * Copyright (C) 2004 Intel Corp. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "hardware.h" -#include "irqs.h" -#include "gpio-iop32x.h" - -/* - * Until March of 2007 iq31244 platforms and ep80219 platforms shared the - * same machine id, and the processor type was used to select board type. - * However this assumption breaks for an iq80219 board which is an iop219 - * processor on an iq31244 board. The force_ep80219 flag has been added - * for old boot loaders using the iq31244 machine id for an ep80219 platform. - */ -static int force_ep80219; - -static int is_80219(void) -{ - return !!((read_cpuid_id() & 0xffffffe0) == 0x69052e20); -} - -static int is_ep80219(void) -{ - if (machine_is_ep80219() || force_ep80219) - return 1; - else - return 0; -} - - -/* - * EP80219/IQ31244 timer tick configuration. - */ -static void __init iq31244_timer_init(void) -{ - if (is_ep80219()) { - /* 33.333 MHz crystal. */ - iop_init_time(200000000); - } else { - /* 33.000 MHz crystal. */ - iop_init_time(198000000); - } -} - - -/* - * IQ31244 I/O. - */ -static struct map_desc iq31244_io_desc[] __initdata = { - { /* on-board devices */ - .virtual = IQ31244_UART, - .pfn = __phys_to_pfn(IQ31244_UART), - .length = 0x00100000, - .type = MT_DEVICE, - }, -}; - -void __init iq31244_map_io(void) -{ - iop3xx_map_io(); - iotable_init(iq31244_io_desc, ARRAY_SIZE(iq31244_io_desc)); -} - - -/* - * EP80219/IQ31244 PCI. - */ -static int __init -ep80219_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - int irq; - - if (slot == 0) { - /* CFlash */ - irq = IRQ_IOP32X_XINT1; - } else if (slot == 1) { - /* 82551 Pro 100 */ - irq = IRQ_IOP32X_XINT0; - } else if (slot == 2) { - /* PCI-X Slot */ - irq = IRQ_IOP32X_XINT3; - } else if (slot == 3) { - /* SATA */ - irq = IRQ_IOP32X_XINT2; - } else { - printk(KERN_ERR "ep80219_pci_map_irq() called for unknown " - "device PCI:%d:%d:%d\n", dev->bus->number, - PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); - irq = -1; - } - - return irq; -} - -static struct hw_pci ep80219_pci __initdata = { - .nr_controllers = 1, - .ops = &iop3xx_ops, - .setup = iop3xx_pci_setup, - .preinit = iop3xx_pci_preinit, - .map_irq = ep80219_pci_map_irq, -}; - -static int __init -iq31244_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - int irq; - - if (slot == 0) { - /* CFlash */ - irq = IRQ_IOP32X_XINT1; - } else if (slot == 1) { - /* SATA */ - irq = IRQ_IOP32X_XINT2; - } else if (slot == 2) { - /* PCI-X Slot */ - irq = IRQ_IOP32X_XINT3; - } else if (slot == 3) { - /* 82546 GigE */ - irq = IRQ_IOP32X_XINT0; - } else { - printk(KERN_ERR "iq31244_pci_map_irq called for unknown " - "device PCI:%d:%d:%d\n", dev->bus->number, - PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); - irq = -1; - } - - return irq; -} - -static struct hw_pci iq31244_pci __initdata = { - .nr_controllers = 1, - .ops = &iop3xx_ops, - .setup = iop3xx_pci_setup, - .preinit = iop3xx_pci_preinit, - .map_irq = iq31244_pci_map_irq, -}; - -static int __init iq31244_pci_init(void) -{ - if (is_ep80219()) - pci_common_init(&ep80219_pci); - else if (machine_is_iq31244()) { - if (is_80219()) { - printk("note: iq31244 board type has been selected\n"); - printk("note: to select ep80219 operation:\n"); - printk("\t1/ specify \"force_ep80219\" on the kernel" - " command line\n"); - printk("\t2/ update boot loader to pass" - " the ep80219 id: %d\n", MACH_TYPE_EP80219); - } - pci_common_init(&iq31244_pci); - } - - return 0; -} - -subsys_initcall(iq31244_pci_init); - - -/* - * IQ31244 machine initialisation. - */ -static struct physmap_flash_data iq31244_flash_data = { - .width = 2, -}; - -static struct resource iq31244_flash_resource = { - .start = 0xf0000000, - .end = 0xf07fffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device iq31244_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &iq31244_flash_data, - }, - .num_resources = 1, - .resource = &iq31244_flash_resource, -}; - -static struct plat_serial8250_port iq31244_serial_port[] = { - { - .mapbase = IQ31244_UART, - .membase = (char *)IQ31244_UART, - .irq = IRQ_IOP32X_XINT1, - .flags = UPF_SKIP_TEST, - .iotype = UPIO_MEM, - .regshift = 0, - .uartclk = 1843200, - }, - { }, -}; - -static struct resource iq31244_uart_resource = { - .start = IQ31244_UART, - .end = IQ31244_UART + 7, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device iq31244_serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = iq31244_serial_port, - }, - .num_resources = 1, - .resource = &iq31244_uart_resource, -}; - -/* - * This function will send a SHUTDOWN_COMPLETE message to the PIC - * controller over I2C. We are not using the i2c subsystem since - * we are going to power off and it may be removed - */ -void ep80219_power_off(void) -{ - /* - * Send the Address byte w/ the start condition - */ - *IOP3XX_IDBR1 = 0x60; - *IOP3XX_ICR1 = 0xE9; - mdelay(1); - - /* - * Send the START_MSG byte w/ no start or stop condition - */ - *IOP3XX_IDBR1 = 0x0F; - *IOP3XX_ICR1 = 0xE8; - mdelay(1); - - /* - * Send the SHUTDOWN_COMPLETE Message ID byte w/ no start or - * stop condition - */ - *IOP3XX_IDBR1 = 0x03; - *IOP3XX_ICR1 = 0xE8; - mdelay(1); - - /* - * Send an ignored byte w/ stop condition - */ - *IOP3XX_IDBR1 = 0x00; - *IOP3XX_ICR1 = 0xEA; - - while (1) - ; -} - -static void __init iq31244_init_machine(void) -{ - register_iop32x_gpio(); - gpiod_add_lookup_table(&iop3xx_i2c0_gpio_lookup); - gpiod_add_lookup_table(&iop3xx_i2c1_gpio_lookup); - platform_device_register(&iop3xx_i2c0_device); - platform_device_register(&iop3xx_i2c1_device); - platform_device_register(&iq31244_flash_device); - platform_device_register(&iq31244_serial_device); - platform_device_register(&iop3xx_dma_0_channel); - platform_device_register(&iop3xx_dma_1_channel); - - if (is_ep80219()) - pm_power_off = ep80219_power_off; - - if (!is_80219()) - platform_device_register(&iop3xx_aau_channel); -} - -static int __init force_ep80219_setup(char *str) -{ - force_ep80219 = 1; - return 1; -} - -__setup("force_ep80219", force_ep80219_setup); - -MACHINE_START(IQ31244, "Intel IQ31244") - /* Maintainer: Intel Corp. */ - .atag_offset = 0x100, - .map_io = iq31244_map_io, - .init_irq = iop32x_init_irq, - .init_time = iq31244_timer_init, - .init_machine = iq31244_init_machine, - .restart = iop3xx_restart, -MACHINE_END - -/* There should have been an ep80219 machine identifier from the beginning. - * Boot roms older than March 2007 do not know the ep80219 machine id. Pass - * "force_ep80219" on the kernel command line, otherwise iq31244 operation - * will be selected. - */ -MACHINE_START(EP80219, "Intel EP80219") - /* Maintainer: Intel Corp. */ - .atag_offset = 0x100, - .nr_irqs = IOP32X_NR_IRQS, - .map_io = iq31244_map_io, - .init_irq = iop32x_init_irq, - .init_time = iq31244_timer_init, - .init_machine = iq31244_init_machine, - .restart = iop3xx_restart, -MACHINE_END diff --git a/arch/arm/mach-iop32x/iq31244.h b/arch/arm/mach-iop32x/iq31244.h deleted file mode 100644 index a7ac691e48d3..000000000000 --- a/arch/arm/mach-iop32x/iq31244.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Intel IQ31244 evaluation board registers - */ - -#ifndef __IQ31244_H -#define __IQ31244_H - -#define IQ31244_UART 0xfe800000 /* UART #1 */ -#define IQ31244_7SEG_1 0xfe840000 /* 7-Segment MSB */ -#define IQ31244_7SEG_0 0xfe850000 /* 7-Segment LSB (WO) */ -#define IQ31244_ROTARY_SW 0xfe8d0000 /* Rotary Switch */ -#define IQ31244_BATT_STAT 0xfe8f0000 /* Battery Status */ - - -#endif diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c deleted file mode 100644 index d9780c4660cb..000000000000 --- a/arch/arm/mach-iop32x/iq80321.c +++ /dev/null @@ -1,192 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-iop32x/iq80321.c - * - * Board support code for the Intel IQ80321 platform. - * - * Author: Rory Bolt - * Copyright (C) 2002 Rory Bolt - * Copyright (C) 2004 Intel Corp. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "hardware.h" -#include "irqs.h" -#include "gpio-iop32x.h" - -/* - * IQ80321 timer tick configuration. - */ -static void __init iq80321_timer_init(void) -{ - /* 33.333 MHz crystal. */ - iop_init_time(200000000); -} - - -/* - * IQ80321 I/O. - */ -static struct map_desc iq80321_io_desc[] __initdata = { - { /* on-board devices */ - .virtual = IQ80321_UART, - .pfn = __phys_to_pfn(IQ80321_UART), - .length = 0x00100000, - .type = MT_DEVICE, - }, -}; - -void __init iq80321_map_io(void) -{ - iop3xx_map_io(); - iotable_init(iq80321_io_desc, ARRAY_SIZE(iq80321_io_desc)); -} - - -/* - * IQ80321 PCI. - */ -static int __init -iq80321_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - int irq; - - if ((slot == 2 || slot == 6) && pin == 1) { - /* PCI-X Slot INTA */ - irq = IRQ_IOP32X_XINT2; - } else if ((slot == 2 || slot == 6) && pin == 2) { - /* PCI-X Slot INTA */ - irq = IRQ_IOP32X_XINT3; - } else if ((slot == 2 || slot == 6) && pin == 3) { - /* PCI-X Slot INTA */ - irq = IRQ_IOP32X_XINT0; - } else if ((slot == 2 || slot == 6) && pin == 4) { - /* PCI-X Slot INTA */ - irq = IRQ_IOP32X_XINT1; - } else if (slot == 4 || slot == 8) { - /* Gig-E */ - irq = IRQ_IOP32X_XINT0; - } else { - printk(KERN_ERR "iq80321_pci_map_irq() called for unknown " - "device PCI:%d:%d:%d\n", dev->bus->number, - PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); - irq = -1; - } - - return irq; -} - -static struct hw_pci iq80321_pci __initdata = { - .nr_controllers = 1, - .ops = &iop3xx_ops, - .setup = iop3xx_pci_setup, - .preinit = iop3xx_pci_preinit_cond, - .map_irq = iq80321_pci_map_irq, -}; - -static int __init iq80321_pci_init(void) -{ - if ((iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) && - machine_is_iq80321()) - pci_common_init(&iq80321_pci); - - return 0; -} - -subsys_initcall(iq80321_pci_init); - - -/* - * IQ80321 machine initialisation. - */ -static struct physmap_flash_data iq80321_flash_data = { - .width = 1, -}; - -static struct resource iq80321_flash_resource = { - .start = 0xf0000000, - .end = 0xf07fffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device iq80321_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &iq80321_flash_data, - }, - .num_resources = 1, - .resource = &iq80321_flash_resource, -}; - -static struct plat_serial8250_port iq80321_serial_port[] = { - { - .mapbase = IQ80321_UART, - .membase = (char *)IQ80321_UART, - .irq = IRQ_IOP32X_XINT1, - .flags = UPF_SKIP_TEST, - .iotype = UPIO_MEM, - .regshift = 0, - .uartclk = 1843200, - }, - { }, -}; - -static struct resource iq80321_uart_resource = { - .start = IQ80321_UART, - .end = IQ80321_UART + 7, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device iq80321_serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = iq80321_serial_port, - }, - .num_resources = 1, - .resource = &iq80321_uart_resource, -}; - -static void __init iq80321_init_machine(void) -{ - register_iop32x_gpio(); - gpiod_add_lookup_table(&iop3xx_i2c0_gpio_lookup); - gpiod_add_lookup_table(&iop3xx_i2c1_gpio_lookup); - platform_device_register(&iop3xx_i2c0_device); - platform_device_register(&iop3xx_i2c1_device); - platform_device_register(&iq80321_flash_device); - platform_device_register(&iq80321_serial_device); - platform_device_register(&iop3xx_dma_0_channel); - platform_device_register(&iop3xx_dma_1_channel); - platform_device_register(&iop3xx_aau_channel); -} - -MACHINE_START(IQ80321, "Intel IQ80321") - /* Maintainer: Intel Corp. */ - .atag_offset = 0x100, - .nr_irqs = IOP32X_NR_IRQS, - .map_io = iq80321_map_io, - .init_irq = iop32x_init_irq, - .init_time = iq80321_timer_init, - .init_machine = iq80321_init_machine, - .restart = iop3xx_restart, -MACHINE_END diff --git a/arch/arm/mach-iop32x/iq80321.h b/arch/arm/mach-iop32x/iq80321.h deleted file mode 100644 index 3a5d10626ea6..000000000000 --- a/arch/arm/mach-iop32x/iq80321.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Intel IQ80321 evaluation board registers - */ - -#ifndef __IQ80321_H -#define __IQ80321_H - -#define IQ80321_UART 0xfe800000 /* UART #1 */ -#define IQ80321_7SEG_1 0xfe840000 /* 7-Segment MSB */ -#define IQ80321_7SEG_0 0xfe850000 /* 7-Segment LSB (WO) */ -#define IQ80321_ROTARY_SW 0xfe8d0000 /* Rotary Switch */ -#define IQ80321_BATT_STAT 0xfe8f0000 /* Battery Status */ - - -#endif diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c deleted file mode 100644 index 6dca7e97d81f..000000000000 --- a/arch/arm/mach-iop32x/irq.c +++ /dev/null @@ -1,95 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/mach-iop32x/irq.c - * - * Generic IOP32X IRQ handling functionality - * - * Author: Rory Bolt - * Copyright (C) 2002 Rory Bolt - */ - -#include -#include -#include -#include -#include -#include - -#include "hardware.h" - -static u32 iop32x_mask; - -static void intctl_write(u32 val) -{ - asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val)); -} - -static void intstr_write(u32 val) -{ - asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val)); -} - -static u32 iintsrc_read(void) -{ - int irq; - - asm volatile("mrc p6, 0, %0, c8, c0, 0" : "=r" (irq)); - - return irq; -} - -static void -iop32x_irq_mask(struct irq_data *d) -{ - iop32x_mask &= ~(1 << (d->irq - 1)); - intctl_write(iop32x_mask); -} - -static void -iop32x_irq_unmask(struct irq_data *d) -{ - iop32x_mask |= 1 << (d->irq - 1); - intctl_write(iop32x_mask); -} - -struct irq_chip ext_chip = { - .name = "IOP32x", - .irq_ack = iop32x_irq_mask, - .irq_mask = iop32x_irq_mask, - .irq_unmask = iop32x_irq_unmask, -}; - -static void iop_handle_irq(struct pt_regs *regs) -{ - u32 mask; - - iop_enable_cp6(); - - do { - mask = iintsrc_read(); - if (mask) - generic_handle_irq(fls(mask)); - } while (mask); -} - -void __init iop32x_init_irq(void) -{ - int i; - - iop_init_cp6_handler(); - set_handle_irq(iop_handle_irq); - - intctl_write(0); - intstr_write(0); - if (machine_is_glantank() || - machine_is_iq80321() || - machine_is_iq31244() || - machine_is_n2100() || - machine_is_em7210()) - *IOP3XX_PCIIRSR = 0x0f; - - for (i = 1; i < NR_IRQS; i++) { - irq_set_chip_and_handler(i, &ext_chip, handle_level_irq); - irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE); - } -} diff --git a/arch/arm/mach-iop32x/irqs.h b/arch/arm/mach-iop32x/irqs.h deleted file mode 100644 index e9fc88e09189..000000000000 --- a/arch/arm/mach-iop32x/irqs.h +++ /dev/null @@ -1,48 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Author: Rory Bolt - * Copyright: (C) 2002 Rory Bolt - */ - -#ifndef __IOP32X_IRQS_H -#define __IOP32X_IRQS_H - -/* Interrupts in Linux start at 1, hardware starts at 0 */ - -#define IOP_IRQ(x) ((x) + 1) - -/* - * IOP80321 chipset interrupts - */ -#define IRQ_IOP32X_DMA0_EOT IOP_IRQ(0) -#define IRQ_IOP32X_DMA0_EOC IOP_IRQ(1) -#define IRQ_IOP32X_DMA1_EOT IOP_IRQ(2) -#define IRQ_IOP32X_DMA1_EOC IOP_IRQ(3) -#define IRQ_IOP32X_AA_EOT IOP_IRQ(6) -#define IRQ_IOP32X_AA_EOC IOP_IRQ(7) -#define IRQ_IOP32X_CORE_PMON IOP_IRQ(8) -#define IRQ_IOP32X_TIMER0 IOP_IRQ(9) -#define IRQ_IOP32X_TIMER1 IOP_IRQ(10) -#define IRQ_IOP32X_I2C_0 IOP_IRQ(11) -#define IRQ_IOP32X_I2C_1 IOP_IRQ(12) -#define IRQ_IOP32X_MESSAGING IOP_IRQ(13) -#define IRQ_IOP32X_ATU_BIST IOP_IRQ(14) -#define IRQ_IOP32X_PERFMON IOP_IRQ(15) -#define IRQ_IOP32X_CORE_PMU IOP_IRQ(16) -#define IRQ_IOP32X_BIU_ERR IOP_IRQ(17) -#define IRQ_IOP32X_ATU_ERR IOP_IRQ(18) -#define IRQ_IOP32X_MCU_ERR IOP_IRQ(19) -#define IRQ_IOP32X_DMA0_ERR IOP_IRQ(20) -#define IRQ_IOP32X_DMA1_ERR IOP_IRQ(21) -#define IRQ_IOP32X_AA_ERR IOP_IRQ(23) -#define IRQ_IOP32X_MSG_ERR IOP_IRQ(24) -#define IRQ_IOP32X_SSP IOP_IRQ(25) -#define IRQ_IOP32X_XINT0 IOP_IRQ(27) -#define IRQ_IOP32X_XINT1 IOP_IRQ(28) -#define IRQ_IOP32X_XINT2 IOP_IRQ(29) -#define IRQ_IOP32X_XINT3 IOP_IRQ(30) -#define IRQ_IOP32X_HPI IOP_IRQ(31) - -#define IOP32X_NR_IRQS (IRQ_IOP32X_HPI + 1) - -#endif diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c deleted file mode 100644 index bb1e2e11bf35..000000000000 --- a/arch/arm/mach-iop32x/n2100.c +++ /dev/null @@ -1,367 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-iop32x/n2100.c - * - * Board support code for the Thecus N2100 platform. - * - * Author: Rory Bolt - * Copyright (C) 2002 Rory Bolt - * Copyright 2003 (c) MontaVista, Software, Inc. - * Copyright (C) 2004 Intel Corp. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "hardware.h" -#include "irqs.h" -#include "gpio-iop32x.h" - -/* - * N2100 timer tick configuration. - */ -static void __init n2100_timer_init(void) -{ - /* 33.000 MHz crystal. */ - iop_init_time(198000000); -} - - -/* - * N2100 I/O. - */ -static struct map_desc n2100_io_desc[] __initdata = { - { /* on-board devices */ - .virtual = N2100_UART, - .pfn = __phys_to_pfn(N2100_UART), - .length = 0x00100000, - .type = MT_DEVICE - }, -}; - -void __init n2100_map_io(void) -{ - iop3xx_map_io(); - iotable_init(n2100_io_desc, ARRAY_SIZE(n2100_io_desc)); -} - - -/* - * N2100 PCI. - */ -static int n2100_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - int irq; - - if (PCI_SLOT(dev->devfn) == 1) { - /* RTL8110SB #1 */ - irq = IRQ_IOP32X_XINT0; - } else if (PCI_SLOT(dev->devfn) == 2) { - /* RTL8110SB #2 */ - irq = IRQ_IOP32X_XINT3; - } else if (PCI_SLOT(dev->devfn) == 3) { - /* Sil3512 */ - irq = IRQ_IOP32X_XINT2; - } else if (PCI_SLOT(dev->devfn) == 4 && pin == 1) { - /* VT6212 INTA */ - irq = IRQ_IOP32X_XINT1; - } else if (PCI_SLOT(dev->devfn) == 4 && pin == 2) { - /* VT6212 INTB */ - irq = IRQ_IOP32X_XINT0; - } else if (PCI_SLOT(dev->devfn) == 4 && pin == 3) { - /* VT6212 INTC */ - irq = IRQ_IOP32X_XINT2; - } else if (PCI_SLOT(dev->devfn) == 5) { - /* Mini-PCI slot */ - irq = IRQ_IOP32X_XINT3; - } else { - printk(KERN_ERR "n2100_pci_map_irq() called for unknown " - "device PCI:%d:%d:%d\n", dev->bus->number, - PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); - irq = -1; - } - - return irq; -} - -static struct hw_pci n2100_pci __initdata = { - .nr_controllers = 1, - .ops = &iop3xx_ops, - .setup = iop3xx_pci_setup, - .preinit = iop3xx_pci_preinit, - .map_irq = n2100_pci_map_irq, -}; - -/* - * Both r8169 chips on the n2100 exhibit PCI parity problems. Turn - * off parity reporting for both ports so we don't get error interrupts - * for them. - */ -static void n2100_fixup_r8169(struct pci_dev *dev) -{ - if (dev->bus->number == 0 && - (dev->devfn == PCI_DEVFN(1, 0) || - dev->devfn == PCI_DEVFN(2, 0))) - pci_disable_parity(dev); -} -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, PCI_ANY_ID, n2100_fixup_r8169); - -static int __init n2100_pci_init(void) -{ - if (machine_is_n2100()) - pci_common_init(&n2100_pci); - - return 0; -} - -subsys_initcall(n2100_pci_init); - - -/* - * N2100 machine initialisation. - */ -static struct physmap_flash_data n2100_flash_data = { - .width = 2, -}; - -static struct resource n2100_flash_resource = { - .start = 0xf0000000, - .end = 0xf0ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device n2100_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &n2100_flash_data, - }, - .num_resources = 1, - .resource = &n2100_flash_resource, -}; - - -static struct plat_serial8250_port n2100_serial_port[] = { - { - .mapbase = N2100_UART, - .membase = (char *)N2100_UART, - .irq = 0, - .flags = UPF_SKIP_TEST | UPF_AUTO_IRQ | UPF_SHARE_IRQ, - .iotype = UPIO_MEM, - .regshift = 0, - .uartclk = 1843200, - }, - { }, -}; - -static struct resource n2100_uart_resource = { - .start = N2100_UART, - .end = N2100_UART + 7, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device n2100_serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = n2100_serial_port, - }, - .num_resources = 1, - .resource = &n2100_uart_resource, -}; - -static struct f75375s_platform_data n2100_f75375s = { - .pwm = { 255, 255 }, - .pwm_enable = { 0, 0 }, -}; - -static struct pca9532_platform_data n2100_leds = { - .leds = { - { .name = "n2100:red:satafail0", - .state = PCA9532_OFF, - .type = PCA9532_TYPE_LED, - }, - { .name = "n2100:red:satafail1", - .state = PCA9532_OFF, - .type = PCA9532_TYPE_LED, - }, - { .name = "n2100:blue:usb", - .state = PCA9532_OFF, - .type = PCA9532_TYPE_LED, - }, - { .type = PCA9532_TYPE_NONE }, - - { .type = PCA9532_TYPE_NONE }, - { .type = PCA9532_TYPE_NONE }, - { .type = PCA9532_TYPE_NONE }, - { .name = "n2100:red:usb", - .state = PCA9532_OFF, - .type = PCA9532_TYPE_LED, - }, - - { .type = PCA9532_TYPE_NONE }, /* power OFF gpio */ - { .type = PCA9532_TYPE_NONE }, /* reset gpio */ - { .type = PCA9532_TYPE_NONE }, - { .type = PCA9532_TYPE_NONE }, - - { .type = PCA9532_TYPE_NONE }, - { .name = "n2100:orange:system", - .state = PCA9532_OFF, - .type = PCA9532_TYPE_LED, - }, - { .name = "n2100:red:system", - .state = PCA9532_OFF, - .type = PCA9532_TYPE_LED, - }, - { .name = "N2100 beeper" , - .state = PCA9532_OFF, - .type = PCA9532_TYPE_N2100_BEEP, - }, - }, - .psc = { 0, 0 }, - .pwm = { 0, 0 }, -}; - -static struct i2c_board_info __initdata n2100_i2c_devices[] = { - { - I2C_BOARD_INFO("rs5c372b", 0x32), - }, - { - I2C_BOARD_INFO("f75375", 0x2e), - .platform_data = &n2100_f75375s, - }, - { - I2C_BOARD_INFO("pca9532", 0x60), - .platform_data = &n2100_leds, - }, -}; - -/* - * Pull PCA9532 GPIO #8 low to power off the machine. - */ -static void n2100_power_off(void) -{ - local_irq_disable(); - - /* Start condition, I2C address of PCA9532, write transaction. */ - *IOP3XX_IDBR0 = 0xc0; - *IOP3XX_ICR0 = 0xe9; - mdelay(1); - - /* Write address 0x08. */ - *IOP3XX_IDBR0 = 0x08; - *IOP3XX_ICR0 = 0xe8; - mdelay(1); - - /* Write data 0x01, stop condition. */ - *IOP3XX_IDBR0 = 0x01; - *IOP3XX_ICR0 = 0xea; - - while (1) - ; -} - -static void n2100_restart(enum reboot_mode mode, const char *cmd) -{ - int ret; - - ret = gpio_direction_output(N2100_HARDWARE_RESET, 0); - if (ret) { - pr_crit("could not drive reset GPIO low\n"); - return; - } - /* Wait for reset to happen */ - while (1) - ; -} - - -static struct timer_list power_button_poll_timer; - -static void power_button_poll(struct timer_list *unused) -{ - if (gpio_get_value(N2100_POWER_BUTTON) == 0) { - ctrl_alt_del(); - return; - } - - power_button_poll_timer.expires = jiffies + (HZ / 10); - add_timer(&power_button_poll_timer); -} - -static int __init n2100_request_gpios(void) -{ - int ret; - - if (!machine_is_n2100()) - return 0; - - ret = gpio_request(N2100_HARDWARE_RESET, "reset"); - if (ret) - pr_err("could not request reset GPIO\n"); - - ret = gpio_request(N2100_POWER_BUTTON, "power"); - if (ret) - pr_err("could not request power GPIO\n"); - else { - ret = gpio_direction_input(N2100_POWER_BUTTON); - if (ret) - pr_err("could not set power GPIO as input\n"); - } - /* Set up power button poll timer */ - timer_setup(&power_button_poll_timer, power_button_poll, 0); - power_button_poll_timer.expires = jiffies + (HZ / 10); - add_timer(&power_button_poll_timer); - return 0; -} -device_initcall(n2100_request_gpios); - -static void __init n2100_init_machine(void) -{ - register_iop32x_gpio(); - gpiod_add_lookup_table(&iop3xx_i2c0_gpio_lookup); - platform_device_register(&iop3xx_i2c0_device); - platform_device_register(&n2100_flash_device); - platform_device_register(&n2100_serial_device); - platform_device_register(&iop3xx_dma_0_channel); - platform_device_register(&iop3xx_dma_1_channel); - - i2c_register_board_info(0, n2100_i2c_devices, - ARRAY_SIZE(n2100_i2c_devices)); - - pm_power_off = n2100_power_off; -} - -MACHINE_START(N2100, "Thecus N2100") - /* Maintainer: Lennert Buytenhek */ - .atag_offset = 0x100, - .nr_irqs = IOP32X_NR_IRQS, - .map_io = n2100_map_io, - .init_irq = iop32x_init_irq, - .init_time = n2100_timer_init, - .init_machine = n2100_init_machine, - .restart = n2100_restart, -MACHINE_END diff --git a/arch/arm/mach-iop32x/n2100.h b/arch/arm/mach-iop32x/n2100.h deleted file mode 100644 index 0b97b940d3e7..000000000000 --- a/arch/arm/mach-iop32x/n2100.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Thecus N2100 board registers - */ - -#ifndef __N2100_H -#define __N2100_H - -#define N2100_UART 0xfe800000 /* UART */ - -#define N2100_COPY_BUTTON IOP3XX_GPIO_LINE(0) -#define N2100_PCA9532_RESET IOP3XX_GPIO_LINE(2) -#define N2100_RESET_BUTTON IOP3XX_GPIO_LINE(3) -#define N2100_HARDWARE_RESET IOP3XX_GPIO_LINE(4) -#define N2100_POWER_BUTTON IOP3XX_GPIO_LINE(5) - - -#endif diff --git a/arch/arm/mach-iop32x/pci.c b/arch/arm/mach-iop32x/pci.c deleted file mode 100644 index 7a215d2ee7e2..000000000000 --- a/arch/arm/mach-iop32x/pci.c +++ /dev/null @@ -1,404 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/plat-iop/pci.c - * - * PCI support for the Intel IOP32X and IOP33X processors - * - * Author: Rory Bolt - * Copyright (C) 2002 Rory Bolt - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "hardware.h" -#include "iop3xx.h" - -// #define DEBUG - -#ifdef DEBUG -#define DBG(x...) printk(x) -#else -#define DBG(x...) do { } while (0) -#endif - -/* - * This routine builds either a type0 or type1 configuration command. If the - * bus is on the 803xx then a type0 made, else a type1 is created. - */ -static u32 iop3xx_cfg_address(struct pci_bus *bus, int devfn, int where) -{ - struct pci_sys_data *sys = bus->sysdata; - u32 addr; - - if (sys->busnr == bus->number) - addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11); - else - addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1; - - addr |= PCI_FUNC(devfn) << 8 | (where & ~3); - - return addr; -} - -/* - * This routine checks the status of the last configuration cycle. If an error - * was detected it returns a 1, else it returns a 0. The errors being checked - * are parity, master abort, target abort (master and target). These types of - * errors occur during a config cycle where there is no device, like during - * the discovery stage. - */ -static int iop3xx_pci_status(void) -{ - unsigned int status; - int ret = 0; - - /* - * Check the status registers. - */ - status = *IOP3XX_ATUSR; - if (status & 0xf900) { - DBG("\t\t\tPCI: P0 - status = 0x%08x\n", status); - *IOP3XX_ATUSR = status & 0xf900; - ret = 1; - } - - status = *IOP3XX_ATUISR; - if (status & 0x679f) { - DBG("\t\t\tPCI: P1 - status = 0x%08x\n", status); - *IOP3XX_ATUISR = status & 0x679f; - ret = 1; - } - - return ret; -} - -/* - * Simply write the address register and read the configuration - * data. Note that the 4 nops ensure that we are able to handle - * a delayed abort (in theory.) - */ -static u32 iop3xx_read(unsigned long addr) -{ - u32 val; - - __asm__ __volatile__( - "str %1, [%2]\n\t" - "ldr %0, [%3]\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - : "=r" (val) - : "r" (addr), "r" (IOP3XX_OCCAR), "r" (IOP3XX_OCCDR)); - - return val; -} - -/* - * The read routines must check the error status of the last configuration - * cycle. If there was an error, the routine returns all hex f's. - */ -static int -iop3xx_read_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 *value) -{ - unsigned long addr = iop3xx_cfg_address(bus, devfn, where); - u32 val = iop3xx_read(addr) >> ((where & 3) * 8); - - if (iop3xx_pci_status()) - val = 0xffffffff; - - *value = val; - - return PCIBIOS_SUCCESSFUL; -} - -static int -iop3xx_write_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 value) -{ - unsigned long addr = iop3xx_cfg_address(bus, devfn, where); - u32 val; - - if (size != 4) { - val = iop3xx_read(addr); - if (iop3xx_pci_status()) - return PCIBIOS_SUCCESSFUL; - - where = (where & 3) * 8; - - if (size == 1) - val &= ~(0xff << where); - else - val &= ~(0xffff << where); - - *IOP3XX_OCCDR = val | value << where; - } else { - asm volatile( - "str %1, [%2]\n\t" - "str %0, [%3]\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - : - : "r" (value), "r" (addr), - "r" (IOP3XX_OCCAR), "r" (IOP3XX_OCCDR)); - } - - return PCIBIOS_SUCCESSFUL; -} - -struct pci_ops iop3xx_ops = { - .read = iop3xx_read_config, - .write = iop3xx_write_config, -}; - -/* - * When a PCI device does not exist during config cycles, the 80200 gets a - * bus error instead of returning 0xffffffff. This handler simply returns. - */ -static int -iop3xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs) -{ - DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n", - addr, fsr, regs->ARM_pc, regs->ARM_lr); - - /* - * If it was an imprecise abort, then we need to correct the - * return address to be _after_ the instruction. - */ - if (fsr & (1 << 10)) - regs->ARM_pc += 4; - - return 0; -} - -int iop3xx_pci_setup(int nr, struct pci_sys_data *sys) -{ - struct resource *res; - struct resource realio; - - if (nr != 0) - return 0; - - res = kzalloc(sizeof(struct resource), GFP_KERNEL); - if (!res) - panic("PCI: unable to alloc resources"); - - res->start = IOP3XX_PCI_LOWER_MEM_PA; - res->end = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE - 1; - res->name = "IOP3XX PCI Memory Space"; - res->flags = IORESOURCE_MEM; - request_resource(&iomem_resource, res); - - /* - * Use whatever translation is already setup. - */ - sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - *IOP3XX_OMWTVR0; - - pci_add_resource_offset(&sys->resources, res, sys->mem_offset); - - realio.start = 0; - realio.end = realio.start + SZ_64K - 1; - pci_remap_iospace(&realio, IOP3XX_PCI_LOWER_IO_PA); - - return 1; -} - -void __init iop3xx_atu_setup(void) -{ - /* BAR 0 ( Disabled ) */ - *IOP3XX_IAUBAR0 = 0x0; - *IOP3XX_IABAR0 = 0x0; - *IOP3XX_IATVR0 = 0x0; - *IOP3XX_IALR0 = 0x0; - - /* BAR 1 ( Disabled ) */ - *IOP3XX_IAUBAR1 = 0x0; - *IOP3XX_IABAR1 = 0x0; - *IOP3XX_IALR1 = 0x0; - - /* BAR 2 (1:1 mapping with Physical RAM) */ - /* Set limit and enable */ - *IOP3XX_IALR2 = ~((u32)IOP3XX_MAX_RAM_SIZE - 1) & ~0x1; - *IOP3XX_IAUBAR2 = 0x0; - - /* Align the inbound bar with the base of memory */ - *IOP3XX_IABAR2 = PHYS_OFFSET | - PCI_BASE_ADDRESS_MEM_TYPE_64 | - PCI_BASE_ADDRESS_MEM_PREFETCH; - - *IOP3XX_IATVR2 = PHYS_OFFSET; - - /* Outbound window 0 */ - *IOP3XX_OMWTVR0 = IOP3XX_PCI_LOWER_MEM_BA; - *IOP3XX_OUMWTVR0 = 0; - - /* Outbound window 1 */ - *IOP3XX_OMWTVR1 = IOP3XX_PCI_LOWER_MEM_BA + - IOP3XX_PCI_MEM_WINDOW_SIZE / 2; - *IOP3XX_OUMWTVR1 = 0; - - /* BAR 3 ( Disabled ) */ - *IOP3XX_IAUBAR3 = 0x0; - *IOP3XX_IABAR3 = 0x0; - *IOP3XX_IATVR3 = 0x0; - *IOP3XX_IALR3 = 0x0; - - /* Setup the I/O Bar - */ - *IOP3XX_OIOWTVR = IOP3XX_PCI_LOWER_IO_BA; - - /* Enable inbound and outbound cycles - */ - *IOP3XX_ATUCMD |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | - PCI_COMMAND_PARITY | PCI_COMMAND_SERR; - *IOP3XX_ATUCR |= IOP3XX_ATUCR_OUT_EN; -} - -void __init iop3xx_atu_disable(void) -{ - *IOP3XX_ATUCMD = 0; - *IOP3XX_ATUCR = 0; - - /* wait for cycles to quiesce */ - while (*IOP3XX_PCSR & (IOP3XX_PCSR_OUT_Q_BUSY | - IOP3XX_PCSR_IN_Q_BUSY)) - cpu_relax(); - - /* BAR 0 ( Disabled ) */ - *IOP3XX_IAUBAR0 = 0x0; - *IOP3XX_IABAR0 = 0x0; - *IOP3XX_IATVR0 = 0x0; - *IOP3XX_IALR0 = 0x0; - - /* BAR 1 ( Disabled ) */ - *IOP3XX_IAUBAR1 = 0x0; - *IOP3XX_IABAR1 = 0x0; - *IOP3XX_IALR1 = 0x0; - - /* BAR 2 ( Disabled ) */ - *IOP3XX_IAUBAR2 = 0x0; - *IOP3XX_IABAR2 = 0x0; - *IOP3XX_IATVR2 = 0x0; - *IOP3XX_IALR2 = 0x0; - - /* BAR 3 ( Disabled ) */ - *IOP3XX_IAUBAR3 = 0x0; - *IOP3XX_IABAR3 = 0x0; - *IOP3XX_IATVR3 = 0x0; - *IOP3XX_IALR3 = 0x0; - - /* Clear the outbound windows */ - *IOP3XX_OIOWTVR = 0; - - /* Outbound window 0 */ - *IOP3XX_OMWTVR0 = 0; - *IOP3XX_OUMWTVR0 = 0; - - /* Outbound window 1 */ - *IOP3XX_OMWTVR1 = 0; - *IOP3XX_OUMWTVR1 = 0; -} - -/* Flag to determine whether the ATU is initialized and the PCI bus scanned */ -int init_atu; - -int iop3xx_get_init_atu(void) { - /* check if default has been overridden */ - if (init_atu != IOP3XX_INIT_ATU_DEFAULT) - return init_atu; - else - return IOP3XX_INIT_ATU_DISABLE; -} - -static void __init iop3xx_atu_debug(void) -{ - DBG("PCI: Intel IOP3xx PCI init.\n"); - DBG("PCI: Outbound memory window 0: PCI 0x%08x%08x\n", - *IOP3XX_OUMWTVR0, *IOP3XX_OMWTVR0); - DBG("PCI: Outbound memory window 1: PCI 0x%08x%08x\n", - *IOP3XX_OUMWTVR1, *IOP3XX_OMWTVR1); - DBG("PCI: Outbound IO window: PCI 0x%08x\n", - *IOP3XX_OIOWTVR); - - DBG("PCI: Inbound memory window 0: PCI 0x%08x%08x 0x%08x -> 0x%08x\n", - *IOP3XX_IAUBAR0, *IOP3XX_IABAR0, *IOP3XX_IALR0, *IOP3XX_IATVR0); - DBG("PCI: Inbound memory window 1: PCI 0x%08x%08x 0x%08x\n", - *IOP3XX_IAUBAR1, *IOP3XX_IABAR1, *IOP3XX_IALR1); - DBG("PCI: Inbound memory window 2: PCI 0x%08x%08x 0x%08x -> 0x%08x\n", - *IOP3XX_IAUBAR2, *IOP3XX_IABAR2, *IOP3XX_IALR2, *IOP3XX_IATVR2); - DBG("PCI: Inbound memory window 3: PCI 0x%08x%08x 0x%08x -> 0x%08x\n", - *IOP3XX_IAUBAR3, *IOP3XX_IABAR3, *IOP3XX_IALR3, *IOP3XX_IATVR3); - - DBG("PCI: Expansion ROM window: PCI 0x%08x%08x 0x%08x -> 0x%08x\n", - 0, *IOP3XX_ERBAR, *IOP3XX_ERLR, *IOP3XX_ERTVR); - - DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD); - DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR); - - hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, 0, "imprecise external abort"); -} - -/* for platforms that might be host-bus-adapters */ -void __init iop3xx_pci_preinit_cond(void) -{ - if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) { - iop3xx_atu_disable(); - iop3xx_atu_setup(); - iop3xx_atu_debug(); - } -} - -void __init iop3xx_pci_preinit(void) -{ - pcibios_min_mem = 0; - - iop3xx_atu_disable(); - iop3xx_atu_setup(); - iop3xx_atu_debug(); -} - -/* allow init_atu to be user overridden */ -static int __init iop3xx_init_atu_setup(char *str) -{ - init_atu = IOP3XX_INIT_ATU_DEFAULT; - if (str) { - while (*str != '\0') { - switch (*str) { - case 'y': - case 'Y': - init_atu = IOP3XX_INIT_ATU_ENABLE; - break; - case 'n': - case 'N': - init_atu = IOP3XX_INIT_ATU_DISABLE; - break; - case ',': - case '=': - break; - default: - printk(KERN_DEBUG "\"%s\" malformed at " - "character: \'%c\'", - __func__, - *str); - *(str + 1) = '\0'; - } - str++; - } - } - - return 1; -} - -__setup("iop3xx_init_atu", iop3xx_init_atu_setup); - diff --git a/arch/arm/mach-iop32x/pmu.c b/arch/arm/mach-iop32x/pmu.c deleted file mode 100644 index bdbc7a3cb8a3..000000000000 --- a/arch/arm/mach-iop32x/pmu.c +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * PMU IRQ registration for the iop3xx xscale PMU families. - * Copyright (C) 2010 Will Deacon, ARM Ltd. - */ - -#include -#include "irqs.h" - -static struct resource pmu_resource = { - .start = IRQ_IOP32X_CORE_PMU, - .end = IRQ_IOP32X_CORE_PMU, - .flags = IORESOURCE_IRQ, -}; - -static struct platform_device pmu_device = { - .name = "xscale-pmu", - .id = -1, - .resource = &pmu_resource, - .num_resources = 1, -}; - -static int __init iop3xx_pmu_init(void) -{ - platform_device_register(&pmu_device); - return 0; -} - -arch_initcall(iop3xx_pmu_init); diff --git a/arch/arm/mach-iop32x/restart.c b/arch/arm/mach-iop32x/restart.c deleted file mode 100644 index 3dfa54d3a7a8..000000000000 --- a/arch/arm/mach-iop32x/restart.c +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * restart.c - * - * Copyright (C) 2001 MontaVista Software, Inc. - */ -#include -#include "hardware.h" -#include "iop3xx.h" - -void iop3xx_restart(enum reboot_mode mode, const char *cmd) -{ - *IOP3XX_PCSR = 0x30; - - /* Jump into ROM at address 0 */ - soft_restart(0); -} diff --git a/arch/arm/mach-iop32x/setup.c b/arch/arm/mach-iop32x/setup.c deleted file mode 100644 index a0a81c28a632..000000000000 --- a/arch/arm/mach-iop32x/setup.c +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/plat-iop/setup.c - * - * Author: Nicolas Pitre - * Copyright (C) 2001 MontaVista Software, Inc. - * Copyright (C) 2004 Intel Corporation. - */ - -#include -#include -#include -#include "iop3xx.h" - -/* - * Standard IO mapping for all IOP3xx based systems. Note that - * the IOP3xx OCCDR must be mapped uncached and unbuffered. - */ -static struct map_desc iop3xx_std_desc[] __initdata = { - { /* mem mapped registers */ - .virtual = IOP3XX_PERIPHERAL_VIRT_BASE, - .pfn = __phys_to_pfn(IOP3XX_PERIPHERAL_PHYS_BASE), - .length = IOP3XX_PERIPHERAL_SIZE, - .type = MT_UNCACHED, - }, -}; - -void __init iop3xx_map_io(void) -{ - iotable_init(iop3xx_std_desc, ARRAY_SIZE(iop3xx_std_desc)); -} diff --git a/arch/arm/mach-iop32x/time.c b/arch/arm/mach-iop32x/time.c deleted file mode 100644 index ae533b66fefd..000000000000 --- a/arch/arm/mach-iop32x/time.c +++ /dev/null @@ -1,179 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/plat-iop/time.c - * - * Timer code for IOP32x and IOP33x based systems - * - * Author: Deepak Saxena - * - * Copyright 2002-2003 MontaVista Software Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "hardware.h" -#include "irqs.h" - -/* - * Minimum clocksource/clockevent timer range in seconds - */ -#define IOP_MIN_RANGE 4 - -/* - * IOP clocksource (free-running timer 1). - */ -static u64 notrace iop_clocksource_read(struct clocksource *unused) -{ - return 0xffffffffu - read_tcr1(); -} - -static struct clocksource iop_clocksource = { - .name = "iop_timer1", - .rating = 300, - .read = iop_clocksource_read, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -/* - * IOP sched_clock() implementation via its clocksource. - */ -static u64 notrace iop_read_sched_clock(void) -{ - return 0xffffffffu - read_tcr1(); -} - -/* - * IOP clockevents (interrupting timer 0). - */ -static int iop_set_next_event(unsigned long delta, - struct clock_event_device *unused) -{ - u32 tmr = IOP_TMR_PRIVILEGED | IOP_TMR_RATIO_1_1; - - BUG_ON(delta == 0); - write_tmr0(tmr & ~(IOP_TMR_EN | IOP_TMR_RELOAD)); - write_tcr0(delta); - write_tmr0((tmr & ~IOP_TMR_RELOAD) | IOP_TMR_EN); - - return 0; -} - -static unsigned long ticks_per_jiffy; - -static int iop_set_periodic(struct clock_event_device *evt) -{ - u32 tmr = read_tmr0(); - - write_tmr0(tmr & ~IOP_TMR_EN); - write_tcr0(ticks_per_jiffy - 1); - write_trr0(ticks_per_jiffy - 1); - tmr |= (IOP_TMR_RELOAD | IOP_TMR_EN); - - write_tmr0(tmr); - return 0; -} - -static int iop_set_oneshot(struct clock_event_device *evt) -{ - u32 tmr = read_tmr0(); - - /* ->set_next_event sets period and enables timer */ - tmr &= ~(IOP_TMR_RELOAD | IOP_TMR_EN); - write_tmr0(tmr); - return 0; -} - -static int iop_shutdown(struct clock_event_device *evt) -{ - u32 tmr = read_tmr0(); - - tmr &= ~IOP_TMR_EN; - write_tmr0(tmr); - return 0; -} - -static int iop_resume(struct clock_event_device *evt) -{ - u32 tmr = read_tmr0(); - - tmr |= IOP_TMR_EN; - write_tmr0(tmr); - return 0; -} - -static struct clock_event_device iop_clockevent = { - .name = "iop_timer0", - .features = CLOCK_EVT_FEAT_PERIODIC | - CLOCK_EVT_FEAT_ONESHOT, - .rating = 300, - .set_next_event = iop_set_next_event, - .set_state_shutdown = iop_shutdown, - .set_state_periodic = iop_set_periodic, - .tick_resume = iop_resume, - .set_state_oneshot = iop_set_oneshot, -}; - -static irqreturn_t -iop_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt = dev_id; - - write_tisr(1); - evt->event_handler(evt); - return IRQ_HANDLED; -} - -static unsigned long iop_tick_rate; -unsigned long get_iop_tick_rate(void) -{ - return iop_tick_rate; -} -EXPORT_SYMBOL(get_iop_tick_rate); - -void __init iop_init_time(unsigned long tick_rate) -{ - u32 timer_ctl; - int irq = IRQ_IOP32X_TIMER0; - - sched_clock_register(iop_read_sched_clock, 32, tick_rate); - - ticks_per_jiffy = DIV_ROUND_CLOSEST(tick_rate, HZ); - iop_tick_rate = tick_rate; - - timer_ctl = IOP_TMR_EN | IOP_TMR_PRIVILEGED | - IOP_TMR_RELOAD | IOP_TMR_RATIO_1_1; - - /* - * Set up interrupting clockevent timer 0. - */ - write_tmr0(timer_ctl & ~IOP_TMR_EN); - write_tisr(1); - if (request_irq(irq, iop_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL, - "IOP Timer Tick", &iop_clockevent)) - pr_err("Failed to request irq() %d (IOP Timer Tick)\n", irq); - iop_clockevent.cpumask = cpumask_of(0); - clockevents_config_and_register(&iop_clockevent, tick_rate, - 0xf, 0xfffffffe); - - /* - * Set up free-running clocksource timer 1. - */ - write_trr1(0xffffffff); - write_tcr1(0xffffffff); - write_tmr1(timer_ctl); - clocksource_register_hz(&iop_clocksource, tick_rate); -} -- cgit From 50f6f34e605b58079bd99d23c5da85347b673ef4 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 29 Sep 2022 15:39:13 +0200 Subject: ARM: footbridge: remove CATS Nobody seems to have a CATS machine any more, so remove it now, leaving only NetWinder and EBSA285. Cc: Russell King Acked-by: Linus Walleij Signed-off-by: Arnd Bergmann --- arch/arm/kernel/head.S | 2 +- arch/arm/mach-footbridge/Kconfig | 12 ----- arch/arm/mach-footbridge/Makefile | 2 - arch/arm/mach-footbridge/cats-hw.c | 98 ------------------------------------- arch/arm/mach-footbridge/cats-pci.c | 64 ------------------------ arch/arm/mach-footbridge/common.c | 3 -- 6 files changed, 1 insertion(+), 180 deletions(-) delete mode 100644 arch/arm/mach-footbridge/cats-hw.c delete mode 100644 arch/arm/mach-footbridge/cats-pci.c (limited to 'arch/arm') diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 29e2900178a1..656991055bc1 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -344,7 +344,7 @@ __create_page_tables: ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags #endif -#if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS) +#if defined(CONFIG_ARCH_NETWINDER) /* * If we're using the NetWinder or CATS, we also need to map * in the 16550-type serial port for the debug messages diff --git a/arch/arm/mach-footbridge/Kconfig b/arch/arm/mach-footbridge/Kconfig index b5e7cbfed119..78189997caa1 100644 --- a/arch/arm/mach-footbridge/Kconfig +++ b/arch/arm/mach-footbridge/Kconfig @@ -16,18 +16,6 @@ menuconfig ARCH_FOOTBRIDGE if ARCH_FOOTBRIDGE -config ARCH_CATS - bool "CATS" - depends on UNUSED_BOARD_FILES - select CLKEVT_I8253 - select CLKSRC_I8253 - select ISA - select FORCE_PCI - help - Say Y here if you intend to run this kernel on the CATS. - - Saying N will reduce the size of the Footbridge kernel. - config ARCH_EBSA285_HOST bool "EBSA285 (host mode)" select ARCH_EBSA285 diff --git a/arch/arm/mach-footbridge/Makefile b/arch/arm/mach-footbridge/Makefile index 55d570739f19..1553cc01b45c 100644 --- a/arch/arm/mach-footbridge/Makefile +++ b/arch/arm/mach-footbridge/Makefile @@ -8,11 +8,9 @@ obj-y := common.o isa-irq.o isa.o isa-rtc.o dma-isa.o pci-y += dc21285.o -pci-$(CONFIG_ARCH_CATS) += cats-pci.o pci-$(CONFIG_ARCH_EBSA285) += ebsa285-pci.o pci-$(CONFIG_ARCH_NETWINDER) += netwinder-pci.o -obj-$(CONFIG_ARCH_CATS) += cats-hw.o isa-timer.o obj-$(CONFIG_ARCH_EBSA285) += ebsa285.o dc21285-timer.o obj-$(CONFIG_ARCH_NETWINDER) += netwinder-hw.o isa-timer.o diff --git a/arch/arm/mach-footbridge/cats-hw.c b/arch/arm/mach-footbridge/cats-hw.c deleted file mode 100644 index e575dc0698cd..000000000000 --- a/arch/arm/mach-footbridge/cats-hw.c +++ /dev/null @@ -1,98 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/arch/arm/mach-footbridge/cats-hw.c - * - * CATS machine fixup - * - * Copyright (C) 1998, 1999 Russell King, Phil Blundell - */ -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - -#include "common.h" - -#define CFG_PORT 0x370 -#define INDEX_PORT (CFG_PORT) -#define DATA_PORT (CFG_PORT + 1) - -static int __init cats_hw_init(void) -{ - if (machine_is_cats()) { - /* Set Aladdin to CONFIGURE mode */ - outb(0x51, CFG_PORT); - outb(0x23, CFG_PORT); - - /* Select logical device 3 */ - outb(0x07, INDEX_PORT); - outb(0x03, DATA_PORT); - - /* Set parallel port to DMA channel 3, ECP+EPP1.9, - enable EPP timeout */ - outb(0x74, INDEX_PORT); - outb(0x03, DATA_PORT); - - outb(0xf0, INDEX_PORT); - outb(0x0f, DATA_PORT); - - outb(0xf1, INDEX_PORT); - outb(0x07, DATA_PORT); - - /* Select logical device 4 */ - outb(0x07, INDEX_PORT); - outb(0x04, DATA_PORT); - - /* UART1 high speed mode */ - outb(0xf0, INDEX_PORT); - outb(0x02, DATA_PORT); - - /* Select logical device 5 */ - outb(0x07, INDEX_PORT); - outb(0x05, DATA_PORT); - - /* UART2 high speed mode */ - outb(0xf0, INDEX_PORT); - outb(0x02, DATA_PORT); - - /* Set Aladdin to RUN mode */ - outb(0xbb, CFG_PORT); - } - - return 0; -} - -__initcall(cats_hw_init); - -/* - * CATS uses soft-reboot by default, since - * hard reboots fail on early boards. - */ -static void __init -fixup_cats(struct tag *tags, char **cmdline) -{ -#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE) - screen_info.orig_video_lines = 25; - screen_info.orig_video_points = 16; - screen_info.orig_y = 24; -#endif -} - -MACHINE_START(CATS, "Chalice-CATS") - /* Maintainer: Philip Blundell */ - .atag_offset = 0x100, - .reboot_mode = REBOOT_SOFT, - .fixup = fixup_cats, - .map_io = footbridge_map_io, - .init_irq = footbridge_init_irq, - .init_time = isa_timer_init, - .restart = footbridge_restart, -MACHINE_END diff --git a/arch/arm/mach-footbridge/cats-pci.c b/arch/arm/mach-footbridge/cats-pci.c deleted file mode 100644 index 90b1e9be430e..000000000000 --- a/arch/arm/mach-footbridge/cats-pci.c +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/arch/arm/mach-footbridge/cats-pci.c - * - * PCI bios-type initialisation for PCI machines - * - * Bits taken from various places. - */ -#include -#include -#include - -#include -#include -#include - -/* cats host-specific stuff */ -static int irqmap_cats[] = { IRQ_PCI, IRQ_IN0, IRQ_IN1, IRQ_IN3 }; - -static u8 cats_no_swizzle(struct pci_dev *dev, u8 *pin) -{ - return 0; -} - -static int cats_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - if (dev->irq >= 255) - return -1; /* not a valid interrupt. */ - - if (dev->irq >= 128) - return dev->irq & 0x1f; - - if (dev->irq >= 1 && dev->irq <= 4) - return irqmap_cats[dev->irq - 1]; - - if (dev->irq != 0) - printk("PCI: device %02x:%02x has unknown irq line %x\n", - dev->bus->number, dev->devfn, dev->irq); - - return -1; -} - -/* - * why not the standard PCI swizzle? does this prevent 4-port tulip - * cards being used (ie, pci-pci bridge based cards)? - */ -static struct hw_pci cats_pci __initdata = { - .swizzle = cats_no_swizzle, - .map_irq = cats_map_irq, - .nr_controllers = 1, - .ops = &dc21285_ops, - .setup = dc21285_setup, - .preinit = dc21285_preinit, - .postinit = dc21285_postinit, -}; - -static int __init cats_pci_init(void) -{ - if (machine_is_cats()) - pci_common_init(&cats_pci); - return 0; -} - -subsys_initcall(cats_pci_init); diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c index 629e4676ed77..85c598708c10 100644 --- a/arch/arm/mach-footbridge/common.c +++ b/arch/arm/mach-footbridge/common.c @@ -206,9 +206,6 @@ void __init footbridge_init_irq(void) */ isa_init_irq(IRQ_PCI); - if (machine_is_cats()) - isa_init_irq(IRQ_IN2); - if (machine_is_netwinder()) isa_init_irq(IRQ_IN3); } -- cgit From 0d7bb85e941327064c1f33128af563fac6cb9be3 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 29 Sep 2022 15:38:56 +0200 Subject: ARM: omap1: remove unused board files All board support that was marked as 'unused' earlier can now be removed, leaving the five machines that that still had someone using them in 2022, or that are supported in qemu. Cc: Aaro Koskinen Cc: Janusz Krzysztofik Cc: Tony Lindgren Cc: linux-omap@vger.kernel.org Signed-off-by: Arnd Bergmann --- arch/arm/Kconfig.debug | 36 +-- arch/arm/configs/omap1_defconfig | 2 - arch/arm/mach-omap1/Kconfig | 91 ------ arch/arm/mach-omap1/Makefile | 18 -- arch/arm/mach-omap1/board-fsample.c | 366 --------------------- arch/arm/mach-omap1/board-generic.c | 85 ----- arch/arm/mach-omap1/board-h2-mmc.c | 74 ----- arch/arm/mach-omap1/board-h2.c | 448 -------------------------- arch/arm/mach-omap1/board-h2.h | 38 --- arch/arm/mach-omap1/board-h3-mmc.c | 64 ---- arch/arm/mach-omap1/board-h3.c | 455 -------------------------- arch/arm/mach-omap1/board-h3.h | 35 -- arch/arm/mach-omap1/board-htcherald.c | 585 ---------------------------------- arch/arm/mach-omap1/board-innovator.c | 481 ---------------------------- arch/arm/mach-omap1/board-nand.c | 33 -- arch/arm/mach-omap1/board-palmtt.c | 285 ----------------- arch/arm/mach-omap1/board-palmz71.c | 300 ----------------- arch/arm/mach-omap1/board-perseus2.c | 333 ------------------- arch/arm/mach-omap1/fpga.c | 186 ----------- arch/arm/mach-omap1/fpga.h | 49 --- arch/arm/mach-omap1/gpio7xx.c | 272 ---------------- 21 files changed, 6 insertions(+), 4230 deletions(-) delete mode 100644 arch/arm/mach-omap1/board-fsample.c delete mode 100644 arch/arm/mach-omap1/board-generic.c delete mode 100644 arch/arm/mach-omap1/board-h2-mmc.c delete mode 100644 arch/arm/mach-omap1/board-h2.c delete mode 100644 arch/arm/mach-omap1/board-h2.h delete mode 100644 arch/arm/mach-omap1/board-h3-mmc.c delete mode 100644 arch/arm/mach-omap1/board-h3.c delete mode 100644 arch/arm/mach-omap1/board-h3.h delete mode 100644 arch/arm/mach-omap1/board-htcherald.c delete mode 100644 arch/arm/mach-omap1/board-innovator.c delete mode 100644 arch/arm/mach-omap1/board-nand.c delete mode 100644 arch/arm/mach-omap1/board-palmtt.c delete mode 100644 arch/arm/mach-omap1/board-palmz71.c delete mode 100644 arch/arm/mach-omap1/board-perseus2.c delete mode 100644 arch/arm/mach-omap1/fpga.c delete mode 100644 arch/arm/mach-omap1/fpga.h delete mode 100644 arch/arm/mach-omap1/gpio7xx.c (limited to 'arch/arm') diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 320c93fabb21..c03fd448c59e 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -760,30 +760,6 @@ choice depends on ARCH_OMAP2PLUS select DEBUG_UART_8250 - config DEBUG_OMAP7XXUART1 - bool "Kernel low-level debugging via OMAP730 UART1" - depends on ARCH_OMAP730 - select DEBUG_UART_8250 - help - Say Y here if you want kernel low-level debugging support - on OMAP730 based platforms on the UART1. - - config DEBUG_OMAP7XXUART2 - bool "Kernel low-level debugging via OMAP730 UART2" - depends on ARCH_OMAP730 - select DEBUG_UART_8250 - help - Say Y here if you want kernel low-level debugging support - on OMAP730 based platforms on the UART2. - - config DEBUG_OMAP7XXUART3 - bool "Kernel low-level debugging via OMAP730 UART3" - depends on ARCH_OMAP730 - select DEBUG_UART_8250 - help - Say Y here if you want kernel low-level debugging support - on OMAP730 based platforms on the UART3. - config DEBUG_TI81XXUART1 bool "Kernel low-level debugging messages via TI81XX UART1 (ti8148evm)" depends on ARCH_OMAP2PLUS @@ -1728,9 +1704,9 @@ config DEBUG_UART_PHYS default 0xffe40000 if DEBUG_RCAR_GEN1_SCIF0 default 0xffe42000 if DEBUG_RCAR_GEN1_SCIF2 default 0xfff36000 if DEBUG_HIGHBANK_UART - default 0xfffb0000 if DEBUG_OMAP1UART1 || DEBUG_OMAP7XXUART1 - default 0xfffb0800 if DEBUG_OMAP1UART2 || DEBUG_OMAP7XXUART2 - default 0xfffb9800 if DEBUG_OMAP1UART3 || DEBUG_OMAP7XXUART3 + default 0xfffb0000 if DEBUG_OMAP1UART1 + default 0xfffb0800 if DEBUG_OMAP1UART2 + default 0xfffb9800 if DEBUG_OMAP1UART3 default 0xfffe8600 if DEBUG_BCM63XX_UART default 0xffffee00 if DEBUG_AT91_SAM9263_DBGU default 0xfffff200 if DEBUG_AT91_RM9200_DBGU @@ -1847,9 +1823,9 @@ config DEBUG_UART_VIRT default 0xfec00000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN default 0xfec00003 if ARCH_IXP4XX && CPU_BIG_ENDIAN default 0xfef36000 if DEBUG_HIGHBANK_UART - default 0xff0b0000 if DEBUG_OMAP1UART1 || DEBUG_OMAP7XXUART1 - default 0xff0b0800 if DEBUG_OMAP1UART2 || DEBUG_OMAP7XXUART2 - default 0xff0b9800 if DEBUG_OMAP1UART3 || DEBUG_OMAP7XXUART3 + default 0xff0b0000 if DEBUG_OMAP1UART1 + default 0xff0b0800 if DEBUG_OMAP1UART2 + default 0xff0b9800 if DEBUG_OMAP1UART3 default 0xffd01000 if DEBUG_HIP01_UART default DEBUG_UART_PHYS if !MMU depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \ diff --git a/arch/arm/configs/omap1_defconfig b/arch/arm/configs/omap1_defconfig index 246f1bba7df5..53dd0717cea5 100644 --- a/arch/arm/configs/omap1_defconfig +++ b/arch/arm/configs/omap1_defconfig @@ -20,8 +20,6 @@ CONFIG_ARCH_OMAP=y CONFIG_ARCH_OMAP1=y CONFIG_OMAP_32K_TIMER=y CONFIG_OMAP_DM_TIMER=y -CONFIG_ARCH_OMAP730=y -CONFIG_ARCH_OMAP850=y CONFIG_ARCH_OMAP16XX=y # CONFIG_OMAP_MUX is not set CONFIG_OMAP_RESET_CLOCKS=y diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig index 7ec7ada287e0..03b0ba2e8653 100644 --- a/arch/arm/mach-omap1/Kconfig +++ b/arch/arm/mach-omap1/Kconfig @@ -19,19 +19,6 @@ menu "TI OMAP1 specific features" comment "OMAP Core Type" -config ARCH_OMAP730 - depends on ARCH_MULTI_V5 - bool "OMAP730 Based System" - select ARCH_OMAP_OTG - select CPU_ARM926T - select OMAP_MPU_TIMER - -config ARCH_OMAP850 - depends on ARCH_MULTI_V5 - bool "OMAP850 Based System" - select ARCH_OMAP_OTG - select CPU_ARM926T - config ARCH_OMAP15XX depends on ARCH_MULTI_V4T default y @@ -126,37 +113,6 @@ config ARCH_OMAP_OTG comment "OMAP Board Type" -config MACH_OMAP_INNOVATOR - bool "TI Innovator" - depends on ARCH_OMAP15XX || ARCH_OMAP16XX - depends on UNUSED_BOARD_FILES - help - TI OMAP 1510 or 1610 Innovator board support. Say Y here if you - have such a board. - -config MACH_OMAP_H2 - bool "TI H2 Support" - depends on ARCH_OMAP16XX - depends on UNUSED_BOARD_FILES - help - TI OMAP 1610/1611B H2 board support. Say Y here if you have such - a board. - -config MACH_OMAP_H3 - bool "TI H3 Support" - depends on ARCH_OMAP16XX - depends on UNUSED_BOARD_FILES - help - TI OMAP 1710 H3 board support. Say Y here if you have such - a board. - -config MACH_HERALD - bool "HTC Herald" - depends on ARCH_OMAP850 - depends on UNUSED_BOARD_FILES - help - HTC Herald smartphone support (AKA T-Mobile Wing, ...) - config MACH_OMAP_OSK bool "TI OSK Support" depends on ARCH_OMAP16XX @@ -167,28 +123,11 @@ config MACH_OMAP_OSK config OMAP_OSK_MISTRAL bool "Mistral QVGA board Support" depends on MACH_OMAP_OSK - depends on UNUSED_BOARD_FILES help The OSK supports an optional add-on board with a Quarter-VGA touchscreen, PDA-ish buttons, a resume button, bicolor LED, and camera connector. Say Y here if you have this board. -config MACH_OMAP_PERSEUS2 - bool "TI Perseus2" - depends on ARCH_OMAP730 - depends on UNUSED_BOARD_FILES - help - Support for TI OMAP 730 Perseus2 board. Say Y here if you have such - a board. - -config MACH_OMAP_FSAMPLE - bool "TI F-Sample" - depends on ARCH_OMAP730 - depends on UNUSED_BOARD_FILES - help - Support for TI OMAP 850 F-Sample board. Say Y here if you have such - a board. - config MACH_OMAP_PALMTE bool "Palm Tungsten E" depends on ARCH_OMAP15XX @@ -198,26 +137,6 @@ config MACH_OMAP_PALMTE http://palmtelinux.sourceforge.net/ for more information. Say Y here if you have this PDA model, say N otherwise. -config MACH_OMAP_PALMZ71 - bool "Palm Zire71" - depends on ARCH_OMAP15XX - depends on UNUSED_BOARD_FILES - help - Support for the Palm Zire71 PDA. To boot the kernel, - you'll need a PalmOS compatible bootloader; check out - http://hackndev.com/palm/z71 for more information. - Say Y here if you have such a PDA, say N otherwise. - -config MACH_OMAP_PALMTT - bool "Palm Tungsten|T" - depends on ARCH_OMAP15XX - depends on UNUSED_BOARD_FILES - help - Support for the Palm Tungsten|T PDA. To boot the kernel, you'll - need a PalmOS compatible bootloader (Garux); check out - http://garux.sourceforge.net/ for more information. - Say Y here if you have this PDA model, say N otherwise. - config MACH_SX1 bool "Siemens SX1" depends on ARCH_OMAP15XX @@ -249,16 +168,6 @@ config MACH_AMS_DELTA Support for the Amstrad E3 (codename Delta) videophone. Say Y here if you have such a device. -config MACH_OMAP_GENERIC - bool "Generic OMAP board" - depends on ARCH_OMAP15XX || ARCH_OMAP16XX - depends on UNUSED_BOARD_FILES - help - Support for generic OMAP-1510, 1610 or 1710 board with - no FPGA. Can be used as template for porting Linux to - custom OMAP boards. Say Y here if you have a custom - board. - endmenu endif diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile index 0615cb0ba580..d9e251ea4773 100644 --- a/arch/arm/mach-omap1/Makefile +++ b/arch/arm/mach-omap1/Makefile @@ -29,31 +29,13 @@ usb-fs-$(CONFIG_USB_SUPPORT) := usb.o obj-y += $(usb-fs-m) $(usb-fs-y) # Specific board support -obj-$(CONFIG_MACH_OMAP_H2) += board-h2.o board-h2-mmc.o \ - board-nand.o -obj-$(CONFIG_MACH_OMAP_INNOVATOR) += board-innovator.o -obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o -obj-$(CONFIG_MACH_OMAP_PERSEUS2) += board-perseus2.o board-nand.o -obj-$(CONFIG_MACH_OMAP_FSAMPLE) += board-fsample.o board-nand.o obj-$(CONFIG_MACH_OMAP_OSK) += board-osk.o -obj-$(CONFIG_MACH_OMAP_H3) += board-h3.o board-h3-mmc.o \ - board-nand.o obj-$(CONFIG_MACH_OMAP_PALMTE) += board-palmte.o -obj-$(CONFIG_MACH_OMAP_PALMZ71) += board-palmz71.o -obj-$(CONFIG_MACH_OMAP_PALMTT) += board-palmtt.o obj-$(CONFIG_MACH_NOKIA770) += board-nokia770.o obj-$(CONFIG_MACH_AMS_DELTA) += board-ams-delta.o ams-delta-fiq.o \ ams-delta-fiq-handler.o obj-$(CONFIG_MACH_SX1) += board-sx1.o board-sx1-mmc.o -obj-$(CONFIG_MACH_HERALD) += board-htcherald.o - -ifeq ($(CONFIG_ARCH_OMAP15XX),y) -# Innovator-1510 FPGA -obj-$(CONFIG_MACH_OMAP_INNOVATOR) += fpga.o -endif # GPIO -obj-$(CONFIG_ARCH_OMAP730) += gpio7xx.o -obj-$(CONFIG_ARCH_OMAP850) += gpio7xx.o obj-$(CONFIG_ARCH_OMAP15XX) += gpio15xx.o obj-$(CONFIG_ARCH_OMAP16XX) += gpio16xx.o diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c deleted file mode 100644 index f21e15c7b973..000000000000 --- a/arch/arm/mach-omap1/board-fsample.c +++ /dev/null @@ -1,366 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-omap1/board-fsample.c - * - * Modified from board-perseus2.c - * - * Original OMAP730 support by Jean Pihet - * Updated for 2.6 by Kevin Hilman - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include "tc.h" - -#include "mux.h" -#include "flash.h" -#include "hardware.h" -#include "iomap.h" -#include "common.h" -#include "fpga.h" - -/* fsample is pretty close to p2-sample */ - -#define fsample_cpld_read(reg) __raw_readb(reg) -#define fsample_cpld_write(val, reg) __raw_writeb(val, reg) - -#define FSAMPLE_CPLD_BASE 0xE8100000 -#define FSAMPLE_CPLD_SIZE SZ_4K -#define FSAMPLE_CPLD_START 0x05080000 - -#define FSAMPLE_CPLD_REG_A (FSAMPLE_CPLD_BASE + 0x00) -#define FSAMPLE_CPLD_SWITCH (FSAMPLE_CPLD_BASE + 0x02) -#define FSAMPLE_CPLD_UART (FSAMPLE_CPLD_BASE + 0x02) -#define FSAMPLE_CPLD_REG_B (FSAMPLE_CPLD_BASE + 0x04) -#define FSAMPLE_CPLD_VERSION (FSAMPLE_CPLD_BASE + 0x06) -#define FSAMPLE_CPLD_SET_CLR (FSAMPLE_CPLD_BASE + 0x06) - -#define FSAMPLE_CPLD_BIT_BT_RESET 0 -#define FSAMPLE_CPLD_BIT_LCD_RESET 1 -#define FSAMPLE_CPLD_BIT_CAM_PWDN 2 -#define FSAMPLE_CPLD_BIT_CHARGER_ENABLE 3 -#define FSAMPLE_CPLD_BIT_SD_MMC_EN 4 -#define FSAMPLE_CPLD_BIT_aGPS_PWREN 5 -#define FSAMPLE_CPLD_BIT_BACKLIGHT 6 -#define FSAMPLE_CPLD_BIT_aGPS_EN_RESET 7 -#define FSAMPLE_CPLD_BIT_aGPS_SLEEPx_N 8 -#define FSAMPLE_CPLD_BIT_OTG_RESET 9 - -#define fsample_cpld_set(bit) \ - fsample_cpld_write((((bit) & 15) << 4) | 0x0f, FSAMPLE_CPLD_SET_CLR) - -#define fsample_cpld_clear(bit) \ - fsample_cpld_write(0xf0 | ((bit) & 15), FSAMPLE_CPLD_SET_CLR) - -static const unsigned int fsample_keymap[] = { - KEY(0, 0, KEY_UP), - KEY(1, 0, KEY_RIGHT), - KEY(2, 0, KEY_LEFT), - KEY(3, 0, KEY_DOWN), - KEY(4, 0, KEY_ENTER), - KEY(0, 1, KEY_F10), - KEY(1, 1, KEY_SEND), - KEY(2, 1, KEY_END), - KEY(3, 1, KEY_VOLUMEDOWN), - KEY(4, 1, KEY_VOLUMEUP), - KEY(5, 1, KEY_RECORD), - KEY(0, 2, KEY_F9), - KEY(1, 2, KEY_3), - KEY(2, 2, KEY_6), - KEY(3, 2, KEY_9), - KEY(4, 2, KEY_KPDOT), - KEY(0, 3, KEY_BACK), - KEY(1, 3, KEY_2), - KEY(2, 3, KEY_5), - KEY(3, 3, KEY_8), - KEY(4, 3, KEY_0), - KEY(5, 3, KEY_KPSLASH), - KEY(0, 4, KEY_HOME), - KEY(1, 4, KEY_1), - KEY(2, 4, KEY_4), - KEY(3, 4, KEY_7), - KEY(4, 4, KEY_KPASTERISK), - KEY(5, 4, KEY_POWER), -}; - -static struct smc91x_platdata smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - -static struct resource smc91x_resources[] = { - [0] = { - .start = H2P2_DBG_FPGA_ETHR_START, /* Physical */ - .end = H2P2_DBG_FPGA_ETHR_START + 0xf, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = INT_7XX_MPU_EXT_NIRQ, - .end = 0, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, - }, -}; - -static void __init fsample_init_smc91x(void) -{ - __raw_writeb(1, H2P2_DBG_FPGA_LAN_RESET); - mdelay(50); - __raw_writeb(__raw_readb(H2P2_DBG_FPGA_LAN_RESET) & ~1, - H2P2_DBG_FPGA_LAN_RESET); - mdelay(50); -} - -static struct mtd_partition nor_partitions[] = { - /* bootloader (U-Boot, etc) in first sector */ - { - .name = "bootloader", - .offset = 0, - .size = SZ_128K, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - /* bootloader params in the next sector */ - { - .name = "params", - .offset = MTDPART_OFS_APPEND, - .size = SZ_128K, - .mask_flags = 0, - }, - /* kernel */ - { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_2M, - .mask_flags = 0 - }, - /* rest of flash is a file system */ - { - .name = "rootfs", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0 - }, -}; - -static struct physmap_flash_data nor_data = { - .width = 2, - .set_vpp = omap1_set_vpp, - .parts = nor_partitions, - .nr_parts = ARRAY_SIZE(nor_partitions), -}; - -static struct resource nor_resource = { - .start = OMAP_CS0_PHYS, - .end = OMAP_CS0_PHYS + SZ_32M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device nor_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &nor_data, - }, - .num_resources = 1, - .resource = &nor_resource, -}; - -#define FSAMPLE_NAND_RB_GPIO_PIN 62 - -static int nand_dev_ready(struct nand_chip *chip) -{ - return gpio_get_value(FSAMPLE_NAND_RB_GPIO_PIN); -} - -static struct platform_nand_data nand_data = { - .chip = { - .nr_chips = 1, - .chip_offset = 0, - .options = NAND_SAMSUNG_LP_OPTIONS, - }, - .ctrl = { - .cmd_ctrl = omap1_nand_cmd_ctl, - .dev_ready = nand_dev_ready, - }, -}; - -static struct resource nand_resource = { - .start = OMAP_CS3_PHYS, - .end = OMAP_CS3_PHYS + SZ_4K - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device nand_device = { - .name = "gen_nand", - .id = 0, - .dev = { - .platform_data = &nand_data, - }, - .num_resources = 1, - .resource = &nand_resource, -}; - -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = 0, - .dev = { - .platform_data = &smc91x_info, - }, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, -}; - -static struct resource kp_resources[] = { - [0] = { - .start = INT_7XX_MPUIO_KEYPAD, - .end = INT_7XX_MPUIO_KEYPAD, - .flags = IORESOURCE_IRQ, - }, -}; - -static const struct matrix_keymap_data fsample_keymap_data = { - .keymap = fsample_keymap, - .keymap_size = ARRAY_SIZE(fsample_keymap), -}; - -static struct omap_kp_platform_data kp_data = { - .rows = 8, - .cols = 8, - .keymap_data = &fsample_keymap_data, - .delay = 4, -}; - -static struct platform_device kp_device = { - .name = "omap-keypad", - .id = -1, - .dev = { - .platform_data = &kp_data, - }, - .num_resources = ARRAY_SIZE(kp_resources), - .resource = kp_resources, -}; - -static struct platform_device *devices[] __initdata = { - &nor_device, - &nand_device, - &smc91x_device, - &kp_device, -}; - -static const struct omap_lcd_config fsample_lcd_config = { - .ctrl_name = "internal", -}; - -static void __init omap_fsample_init(void) -{ - /* Early, board-dependent init */ - - /* - * Hold GSM Reset until needed - */ - omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL); - - /* - * UARTs -> done automagically by 8250 driver - */ - - /* - * CSx timings, GPIO Mux ... setup - */ - - /* Flash: CS0 timings setup */ - omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_0); - omap_writel(0x00000088, OMAP7XX_FLASH_ACFG_0); - - /* - * Ethernet support through the debug board - * CS1 timings setup - */ - omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_1); - omap_writel(0x00000000, OMAP7XX_FLASH_ACFG_1); - - /* - * Configure MPU_EXT_NIRQ IO in IO_CONF9 register, - * It is used as the Ethernet controller interrupt - */ - omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFFFFFF, - OMAP7XX_IO_CONF_9); - - fsample_init_smc91x(); - - BUG_ON(gpio_request(FSAMPLE_NAND_RB_GPIO_PIN, "NAND ready") < 0); - gpio_direction_input(FSAMPLE_NAND_RB_GPIO_PIN); - - omap_cfg_reg(L3_1610_FLASH_CS2B_OE); - omap_cfg_reg(M8_1610_FLASH_CS2B_WE); - - /* Mux pins for keypad */ - omap_cfg_reg(E2_7XX_KBR0); - omap_cfg_reg(J7_7XX_KBR1); - omap_cfg_reg(E1_7XX_KBR2); - omap_cfg_reg(F3_7XX_KBR3); - omap_cfg_reg(D2_7XX_KBR4); - omap_cfg_reg(C2_7XX_KBC0); - omap_cfg_reg(D3_7XX_KBC1); - omap_cfg_reg(E4_7XX_KBC2); - omap_cfg_reg(F4_7XX_KBC3); - omap_cfg_reg(E3_7XX_KBC4); - - platform_add_devices(devices, ARRAY_SIZE(devices)); - - omap_serial_init(); - omap_register_i2c_bus(1, 100, NULL, 0); - - omapfb_set_lcd_config(&fsample_lcd_config); -} - -/* Only FPGA needs to be mapped here. All others are done with ioremap */ -static struct map_desc omap_fsample_io_desc[] __initdata = { - { - .virtual = H2P2_DBG_FPGA_BASE, - .pfn = __phys_to_pfn(H2P2_DBG_FPGA_START), - .length = H2P2_DBG_FPGA_SIZE, - .type = MT_DEVICE - }, - { - .virtual = FSAMPLE_CPLD_BASE, - .pfn = __phys_to_pfn(FSAMPLE_CPLD_START), - .length = FSAMPLE_CPLD_SIZE, - .type = MT_DEVICE - } -}; - -static void __init omap_fsample_map_io(void) -{ - omap15xx_map_io(); - iotable_init(omap_fsample_io_desc, - ARRAY_SIZE(omap_fsample_io_desc)); -} - -MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample") -/* Maintainer: Brian Swetland */ - .atag_offset = 0x100, - .map_io = omap_fsample_map_io, - .init_early = omap1_init_early, - .init_irq = omap1_init_irq, - .handle_irq = omap1_handle_irq, - .init_machine = omap_fsample_init, - .init_late = omap1_init_late, - .init_time = omap1_timer_init, - .restart = omap1_restart, -MACHINE_END diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c deleted file mode 100644 index 3b2bcaf4bb01..000000000000 --- a/arch/arm/mach-omap1/board-generic.c +++ /dev/null @@ -1,85 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-omap1/board-generic.c - * - * Modified from board-innovator1510.c - * - * Code for generic OMAP board. Should work on many OMAP systems where - * the device drivers take care of all the necessary hardware initialization. - * Do not put any board specific code to this file; create a new machine - * type if you need custom low-level initializations. - */ -#include -#include -#include -#include - -#include -#include -#include - -#include "hardware.h" -#include "mux.h" -#include "usb.h" -#include "common.h" - -/* assume no Mini-AB port */ - -#ifdef CONFIG_ARCH_OMAP15XX -static struct omap_usb_config generic1510_usb_config __initdata = { - .register_host = 1, - .register_dev = 1, - .hmc_mode = 16, - .pins[0] = 3, -}; -#endif - -#if defined(CONFIG_ARCH_OMAP16XX) -static struct omap_usb_config generic1610_usb_config __initdata = { -#ifdef CONFIG_USB_OTG - .otg = 1, -#endif - .register_host = 1, - .register_dev = 1, - .hmc_mode = 16, - .pins[0] = 6, -}; -#endif - -static void __init omap_generic_init(void) -{ -#ifdef CONFIG_ARCH_OMAP15XX - if (cpu_is_omap15xx()) { - /* mux pins for uarts */ - omap_cfg_reg(UART1_TX); - omap_cfg_reg(UART1_RTS); - omap_cfg_reg(UART2_TX); - omap_cfg_reg(UART2_RTS); - omap_cfg_reg(UART3_TX); - omap_cfg_reg(UART3_RX); - - omap1_usb_init(&generic1510_usb_config); - } -#endif -#if defined(CONFIG_ARCH_OMAP16XX) - if (!cpu_is_omap1510()) { - omap1_usb_init(&generic1610_usb_config); - } -#endif - - omap_serial_init(); - omap_register_i2c_bus(1, 100, NULL, 0); -} - -MACHINE_START(OMAP_GENERIC, "Generic OMAP1510/1610/1710") - /* Maintainer: Tony Lindgren */ - .atag_offset = 0x100, - .map_io = omap16xx_map_io, - .init_early = omap1_init_early, - .init_irq = omap1_init_irq, - .handle_irq = omap1_handle_irq, - .init_machine = omap_generic_init, - .init_late = omap1_init_late, - .init_time = omap1_timer_init, - .restart = omap1_restart, -MACHINE_END diff --git a/arch/arm/mach-omap1/board-h2-mmc.c b/arch/arm/mach-omap1/board-h2-mmc.c deleted file mode 100644 index 06c5404078aa..000000000000 --- a/arch/arm/mach-omap1/board-h2-mmc.c +++ /dev/null @@ -1,74 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-omap1/board-h2-mmc.c - * - * Copyright (C) 2007 Instituto Nokia de Tecnologia - INdT - * Author: Felipe Balbi - * - * This code is based on linux/arch/arm/mach-omap2/board-n800-mmc.c, which is: - * Copyright (C) 2006 Nokia Corporation - */ -#include -#include -#include -#include - -#include "board-h2.h" -#include "mmc.h" - -#if IS_ENABLED(CONFIG_MMC_OMAP) - -static int mmc_set_power(struct device *dev, int slot, int power_on, - int vdd) -{ - gpio_set_value(H2_TPS_GPIO_MMC_PWR_EN, power_on); - return 0; -} - -static int mmc_late_init(struct device *dev) -{ - int ret = gpio_request(H2_TPS_GPIO_MMC_PWR_EN, "MMC power"); - if (ret < 0) - return ret; - - gpio_direction_output(H2_TPS_GPIO_MMC_PWR_EN, 0); - - return ret; -} - -static void mmc_cleanup(struct device *dev) -{ - gpio_free(H2_TPS_GPIO_MMC_PWR_EN); -} - -/* - * H2 could use the following functions tested: - * - mmc_get_cover_state that uses OMAP_MPUIO(1) - * - mmc_get_wp that uses OMAP_MPUIO(3) - */ -static struct omap_mmc_platform_data mmc1_data = { - .nr_slots = 1, - .init = mmc_late_init, - .cleanup = mmc_cleanup, - .slots[0] = { - .set_power = mmc_set_power, - .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, - .name = "mmcblk", - }, -}; - -static struct omap_mmc_platform_data *mmc_data[OMAP16XX_NR_MMC]; - -void __init h2_mmc_init(void) -{ - mmc_data[0] = &mmc1_data; - omap1_init_mmc(mmc_data, OMAP16XX_NR_MMC); -} - -#else - -void __init h2_mmc_init(void) -{ -} - -#endif diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c deleted file mode 100644 index f28a4c3ea501..000000000000 --- a/arch/arm/mach-omap1/board-h2.c +++ /dev/null @@ -1,448 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-omap1/board-h2.c - * - * Board specific inits for OMAP-1610 H2 - * - * Copyright (C) 2001 RidgeRun, Inc. - * Author: Greg Lonnon - * - * Copyright (C) 2002 MontaVista Software, Inc. - * - * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6 - * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen - * - * H2 specific changes and cleanup - * Copyright (C) 2004 Nokia Corporation by Imre Deak - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "tc.h" -#include "mux.h" -#include "flash.h" -#include "hardware.h" -#include "usb.h" -#include "common.h" -#include "board-h2.h" - -/* The first 16 SoC GPIO lines are on this GPIO chip */ -#define OMAP_GPIO_LABEL "gpio-0-15" - -/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */ -#define OMAP1610_ETHR_START 0x04000300 - -static const unsigned int h2_keymap[] = { - KEY(0, 0, KEY_LEFT), - KEY(1, 0, KEY_RIGHT), - KEY(2, 0, KEY_3), - KEY(3, 0, KEY_F10), - KEY(4, 0, KEY_F5), - KEY(5, 0, KEY_9), - KEY(0, 1, KEY_DOWN), - KEY(1, 1, KEY_UP), - KEY(2, 1, KEY_2), - KEY(3, 1, KEY_F9), - KEY(4, 1, KEY_F7), - KEY(5, 1, KEY_0), - KEY(0, 2, KEY_ENTER), - KEY(1, 2, KEY_6), - KEY(2, 2, KEY_1), - KEY(3, 2, KEY_F2), - KEY(4, 2, KEY_F6), - KEY(5, 2, KEY_HOME), - KEY(0, 3, KEY_8), - KEY(1, 3, KEY_5), - KEY(2, 3, KEY_F12), - KEY(3, 3, KEY_F3), - KEY(4, 3, KEY_F8), - KEY(5, 3, KEY_END), - KEY(0, 4, KEY_7), - KEY(1, 4, KEY_4), - KEY(2, 4, KEY_F11), - KEY(3, 4, KEY_F1), - KEY(4, 4, KEY_F4), - KEY(5, 4, KEY_ESC), - KEY(0, 5, KEY_F13), - KEY(1, 5, KEY_F14), - KEY(2, 5, KEY_F15), - KEY(3, 5, KEY_F16), - KEY(4, 5, KEY_SLEEP), -}; - -static struct mtd_partition h2_nor_partitions[] = { - /* bootloader (U-Boot, etc) in first sector */ - { - .name = "bootloader", - .offset = 0, - .size = SZ_128K, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - /* bootloader params in the next sector */ - { - .name = "params", - .offset = MTDPART_OFS_APPEND, - .size = SZ_128K, - .mask_flags = 0, - }, - /* kernel */ - { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_2M, - .mask_flags = 0 - }, - /* file system */ - { - .name = "filesystem", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0 - } -}; - -static struct physmap_flash_data h2_nor_data = { - .width = 2, - .set_vpp = omap1_set_vpp, - .parts = h2_nor_partitions, - .nr_parts = ARRAY_SIZE(h2_nor_partitions), -}; - -static struct resource h2_nor_resource = { - /* This is on CS3, wherever it's mapped */ - .flags = IORESOURCE_MEM, -}; - -static struct platform_device h2_nor_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &h2_nor_data, - }, - .num_resources = 1, - .resource = &h2_nor_resource, -}; - -static struct mtd_partition h2_nand_partitions[] = { -#if 0 - /* REVISIT: enable these partitions if you make NAND BOOT - * work on your H2 (rev C or newer); published versions of - * x-load only support P2 and H3. - */ - { - .name = "xloader", - .offset = 0, - .size = 64 * 1024, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - { - .name = "bootloader", - .offset = MTDPART_OFS_APPEND, - .size = 256 * 1024, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - { - .name = "params", - .offset = MTDPART_OFS_APPEND, - .size = 192 * 1024, - }, - { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = 2 * SZ_1M, - }, -#endif - { - .name = "filesystem", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - }, -}; - -#define H2_NAND_RB_GPIO_PIN 62 - -static int h2_nand_dev_ready(struct nand_chip *chip) -{ - return gpio_get_value(H2_NAND_RB_GPIO_PIN); -} - -static struct platform_nand_data h2_nand_platdata = { - .chip = { - .nr_chips = 1, - .chip_offset = 0, - .nr_partitions = ARRAY_SIZE(h2_nand_partitions), - .partitions = h2_nand_partitions, - .options = NAND_SAMSUNG_LP_OPTIONS, - }, - .ctrl = { - .cmd_ctrl = omap1_nand_cmd_ctl, - .dev_ready = h2_nand_dev_ready, - }, -}; - -static struct resource h2_nand_resource = { - .flags = IORESOURCE_MEM, -}; - -static struct platform_device h2_nand_device = { - .name = "gen_nand", - .id = 0, - .dev = { - .platform_data = &h2_nand_platdata, - }, - .num_resources = 1, - .resource = &h2_nand_resource, -}; - -static struct smc91x_platdata h2_smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - -static struct resource h2_smc91x_resources[] = { - [0] = { - .start = OMAP1610_ETHR_START, /* Physical */ - .end = OMAP1610_ETHR_START + 0xf, - .flags = IORESOURCE_MEM, - }, - [1] = { - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, - }, -}; - -static struct platform_device h2_smc91x_device = { - .name = "smc91x", - .id = 0, - .dev = { - .platform_data = &h2_smc91x_info, - }, - .num_resources = ARRAY_SIZE(h2_smc91x_resources), - .resource = h2_smc91x_resources, -}; - -static struct resource h2_kp_resources[] = { - [0] = { - .start = INT_KEYBOARD, - .end = INT_KEYBOARD, - .flags = IORESOURCE_IRQ, - }, -}; - -static const struct matrix_keymap_data h2_keymap_data = { - .keymap = h2_keymap, - .keymap_size = ARRAY_SIZE(h2_keymap), -}; - -static struct omap_kp_platform_data h2_kp_data = { - .rows = 8, - .cols = 8, - .keymap_data = &h2_keymap_data, - .rep = true, - .delay = 9, - .dbounce = true, -}; - -static struct platform_device h2_kp_device = { - .name = "omap-keypad", - .id = -1, - .dev = { - .platform_data = &h2_kp_data, - }, - .num_resources = ARRAY_SIZE(h2_kp_resources), - .resource = h2_kp_resources, -}; - -static const struct gpio_led h2_gpio_led_pins[] = { - { - .name = "h2:red", - .default_trigger = "heartbeat", - .gpio = 3, - }, - { - .name = "h2:green", - .default_trigger = "cpu0", - .gpio = OMAP_MPUIO(4), - }, -}; - -static struct gpio_led_platform_data h2_gpio_led_data = { - .leds = h2_gpio_led_pins, - .num_leds = ARRAY_SIZE(h2_gpio_led_pins), -}; - -static struct platform_device h2_gpio_leds = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &h2_gpio_led_data, - }, -}; - -static struct platform_device *h2_devices[] __initdata = { - &h2_nor_device, - &h2_nand_device, - &h2_smc91x_device, - &h2_kp_device, - &h2_gpio_leds, -}; - -static void __init h2_init_smc91x(void) -{ - if (gpio_request(0, "SMC91x irq") < 0) { - printk("Error requesting gpio 0 for smc91x irq\n"); - return; - } -} - -static int tps_setup(struct i2c_client *client, void *context) -{ - if (!IS_BUILTIN(CONFIG_TPS65010)) - return -ENOSYS; - - tps65010_config_vregs1(TPS_LDO2_ENABLE | TPS_VLDO2_3_0V | - TPS_LDO1_ENABLE | TPS_VLDO1_3_0V); - - return 0; -} - -static struct tps65010_board tps_board = { - .base = H2_TPS_GPIO_BASE, - .outmask = 0x0f, - .setup = tps_setup, -}; - -static struct i2c_board_info __initdata h2_i2c_board_info[] = { - { - I2C_BOARD_INFO("tps65010", 0x48), - .platform_data = &tps_board, - }, { - .type = "isp1301_omap", - .addr = 0x2d, - .dev_name = "isp1301", - }, -}; - -static struct gpiod_lookup_table isp1301_gpiod_table = { - .dev_id = "isp1301", - .table = { - /* Active low since the irq triggers on falling edge */ - GPIO_LOOKUP(OMAP_GPIO_LABEL, 2, - NULL, GPIO_ACTIVE_LOW), - { }, - }, -}; - -static struct omap_usb_config h2_usb_config __initdata = { - /* usb1 has a Mini-AB port and external isp1301 transceiver */ - .otg = 2, - -#if IS_ENABLED(CONFIG_USB_OMAP) - .hmc_mode = 19, /* 0:host(off) 1:dev|otg 2:disabled */ - /* .hmc_mode = 21,*/ /* 0:host(off) 1:dev(loopback) 2:host(loopback) */ -#elif IS_ENABLED(CONFIG_USB_OHCI_HCD) - /* needs OTG cable, or NONSTANDARD (B-to-MiniB) */ - .hmc_mode = 20, /* 1:dev|otg(off) 1:host 2:disabled */ -#endif - - .pins[1] = 3, -}; - -static const struct omap_lcd_config h2_lcd_config __initconst = { - .ctrl_name = "internal", -}; - -static void __init h2_init(void) -{ - h2_init_smc91x(); - - /* Here we assume the NOR boot config: NOR on CS3 (possibly swapped - * to address 0 by a dip switch), NAND on CS2B. The NAND driver will - * notice whether a NAND chip is enabled at probe time. - * - * FIXME revC boards (and H3) support NAND-boot, with a dip switch to - * put NOR on CS2B and NAND (which on H2 may be 16bit) on CS3. Try - * detecting that in code here, to avoid probing every possible flash - * configuration... - */ - h2_nor_resource.end = h2_nor_resource.start = omap_cs3_phys(); - h2_nor_resource.end += SZ_32M - 1; - - h2_nand_resource.end = h2_nand_resource.start = OMAP_CS2B_PHYS; - h2_nand_resource.end += SZ_4K - 1; - BUG_ON(gpio_request(H2_NAND_RB_GPIO_PIN, "NAND ready") < 0); - gpio_direction_input(H2_NAND_RB_GPIO_PIN); - - gpiod_add_lookup_table(&isp1301_gpiod_table); - - omap_cfg_reg(L3_1610_FLASH_CS2B_OE); - omap_cfg_reg(M8_1610_FLASH_CS2B_WE); - - /* MMC: card detect and WP */ - /* omap_cfg_reg(U19_ARMIO1); */ /* CD */ - omap_cfg_reg(BALLOUT_V8_ARMIO3); /* WP */ - - /* Mux pins for keypad */ - omap_cfg_reg(F18_1610_KBC0); - omap_cfg_reg(D20_1610_KBC1); - omap_cfg_reg(D19_1610_KBC2); - omap_cfg_reg(E18_1610_KBC3); - omap_cfg_reg(C21_1610_KBC4); - omap_cfg_reg(G18_1610_KBR0); - omap_cfg_reg(F19_1610_KBR1); - omap_cfg_reg(H14_1610_KBR2); - omap_cfg_reg(E20_1610_KBR3); - omap_cfg_reg(E19_1610_KBR4); - omap_cfg_reg(N19_1610_KBR5); - - /* GPIO based LEDs */ - omap_cfg_reg(P18_1610_GPIO3); - omap_cfg_reg(MPUIO4); - - h2_smc91x_resources[1].start = gpio_to_irq(0); - h2_smc91x_resources[1].end = gpio_to_irq(0); - platform_add_devices(h2_devices, ARRAY_SIZE(h2_devices)); - omap_serial_init(); - - /* ISP1301 IRQ wired at M14 */ - omap_cfg_reg(M14_1510_GPIO2); - h2_i2c_board_info[0].irq = gpio_to_irq(58); - omap_register_i2c_bus(1, 100, h2_i2c_board_info, - ARRAY_SIZE(h2_i2c_board_info)); - omap1_usb_init(&h2_usb_config); - h2_mmc_init(); - - omapfb_set_lcd_config(&h2_lcd_config); -} - -MACHINE_START(OMAP_H2, "TI-H2") - /* Maintainer: Imre Deak */ - .atag_offset = 0x100, - .map_io = omap16xx_map_io, - .init_early = omap1_init_early, - .init_irq = omap1_init_irq, - .handle_irq = omap1_handle_irq, - .init_machine = h2_init, - .init_late = omap1_init_late, - .init_time = omap1_timer_init, - .restart = omap1_restart, -MACHINE_END diff --git a/arch/arm/mach-omap1/board-h2.h b/arch/arm/mach-omap1/board-h2.h deleted file mode 100644 index 315e2662547e..000000000000 --- a/arch/arm/mach-omap1/board-h2.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * arch/arm/mach-omap1/board-h2.h - * - * Hardware definitions for TI OMAP1610 H2 board. - * - * Cleanup for Linux-2.6 by Dirk Behme - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __ASM_ARCH_OMAP_H2_H -#define __ASM_ARCH_OMAP_H2_H - -#define H2_TPS_GPIO_BASE (OMAP_MAX_GPIO_LINES + 16 /* MPUIO */) -# define H2_TPS_GPIO_MMC_PWR_EN (H2_TPS_GPIO_BASE + 3) - -extern void h2_mmc_init(void); - -#endif /* __ASM_ARCH_OMAP_H2_H */ - diff --git a/arch/arm/mach-omap1/board-h3-mmc.c b/arch/arm/mach-omap1/board-h3-mmc.c deleted file mode 100644 index f595bd4f5024..000000000000 --- a/arch/arm/mach-omap1/board-h3-mmc.c +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-omap1/board-h3-mmc.c - * - * Copyright (C) 2007 Instituto Nokia de Tecnologia - INdT - * Author: Felipe Balbi - * - * This code is based on linux/arch/arm/mach-omap2/board-n800-mmc.c, which is: - * Copyright (C) 2006 Nokia Corporation - */ -#include -#include - -#include - -#include "common.h" -#include "board-h3.h" -#include "mmc.h" - -#if IS_ENABLED(CONFIG_MMC_OMAP) - -static int mmc_set_power(struct device *dev, int slot, int power_on, - int vdd) -{ - gpio_set_value(H3_TPS_GPIO_MMC_PWR_EN, power_on); - return 0; -} - -/* - * H3 could use the following functions tested: - * - mmc_get_cover_state that uses OMAP_MPUIO(1) - * - mmc_get_wp that maybe uses OMAP_MPUIO(3) - */ -static struct omap_mmc_platform_data mmc1_data = { - .nr_slots = 1, - .slots[0] = { - .set_power = mmc_set_power, - .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, - .name = "mmcblk", - }, -}; - -static struct omap_mmc_platform_data *mmc_data[OMAP16XX_NR_MMC]; - -void __init h3_mmc_init(void) -{ - int ret; - - ret = gpio_request(H3_TPS_GPIO_MMC_PWR_EN, "MMC power"); - if (ret < 0) - return; - gpio_direction_output(H3_TPS_GPIO_MMC_PWR_EN, 0); - - mmc_data[0] = &mmc1_data; - omap1_init_mmc(mmc_data, OMAP16XX_NR_MMC); -} - -#else - -void __init h3_mmc_init(void) -{ -} - -#endif diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c deleted file mode 100644 index 1e4c57710fcc..000000000000 --- a/arch/arm/mach-omap1/board-h3.c +++ /dev/null @@ -1,455 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-omap1/board-h3.c - * - * This file contains OMAP1710 H3 specific code. - * - * Copyright (C) 2004 Texas Instruments, Inc. - * Copyright (C) 2002 MontaVista Software, Inc. - * Copyright (C) 2001 RidgeRun, Inc. - * Author: RidgeRun, Inc. - * Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "tc.h" -#include "mux.h" -#include "flash.h" -#include "hardware.h" -#include "irqs.h" -#include "usb.h" -#include "common.h" -#include "board-h3.h" - -/* In OMAP1710 H3 the Ethernet is directly connected to CS1 */ -#define OMAP1710_ETHR_START 0x04000300 - -#define H3_TS_GPIO 48 - -static const unsigned int h3_keymap[] = { - KEY(0, 0, KEY_LEFT), - KEY(1, 0, KEY_RIGHT), - KEY(2, 0, KEY_3), - KEY(3, 0, KEY_F10), - KEY(4, 0, KEY_F5), - KEY(5, 0, KEY_9), - KEY(0, 1, KEY_DOWN), - KEY(1, 1, KEY_UP), - KEY(2, 1, KEY_2), - KEY(3, 1, KEY_F9), - KEY(4, 1, KEY_F7), - KEY(5, 1, KEY_0), - KEY(0, 2, KEY_ENTER), - KEY(1, 2, KEY_6), - KEY(2, 2, KEY_1), - KEY(3, 2, KEY_F2), - KEY(4, 2, KEY_F6), - KEY(5, 2, KEY_HOME), - KEY(0, 3, KEY_8), - KEY(1, 3, KEY_5), - KEY(2, 3, KEY_F12), - KEY(3, 3, KEY_F3), - KEY(4, 3, KEY_F8), - KEY(5, 3, KEY_END), - KEY(0, 4, KEY_7), - KEY(1, 4, KEY_4), - KEY(2, 4, KEY_F11), - KEY(3, 4, KEY_F1), - KEY(4, 4, KEY_F4), - KEY(5, 4, KEY_ESC), - KEY(0, 5, KEY_F13), - KEY(1, 5, KEY_F14), - KEY(2, 5, KEY_F15), - KEY(3, 5, KEY_F16), - KEY(4, 5, KEY_SLEEP), -}; - - -static struct mtd_partition nor_partitions[] = { - /* bootloader (U-Boot, etc) in first sector */ - { - .name = "bootloader", - .offset = 0, - .size = SZ_128K, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - /* bootloader params in the next sector */ - { - .name = "params", - .offset = MTDPART_OFS_APPEND, - .size = SZ_128K, - .mask_flags = 0, - }, - /* kernel */ - { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_2M, - .mask_flags = 0 - }, - /* file system */ - { - .name = "filesystem", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0 - } -}; - -static struct physmap_flash_data nor_data = { - .width = 2, - .set_vpp = omap1_set_vpp, - .parts = nor_partitions, - .nr_parts = ARRAY_SIZE(nor_partitions), -}; - -static struct resource nor_resource = { - /* This is on CS3, wherever it's mapped */ - .flags = IORESOURCE_MEM, -}; - -static struct platform_device nor_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &nor_data, - }, - .num_resources = 1, - .resource = &nor_resource, -}; - -static struct mtd_partition nand_partitions[] = { -#if 0 - /* REVISIT: enable these partitions if you make NAND BOOT work */ - { - .name = "xloader", - .offset = 0, - .size = 64 * 1024, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - { - .name = "bootloader", - .offset = MTDPART_OFS_APPEND, - .size = 256 * 1024, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - { - .name = "params", - .offset = MTDPART_OFS_APPEND, - .size = 192 * 1024, - }, - { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = 2 * SZ_1M, - }, -#endif - { - .name = "filesystem", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - }, -}; - -#define H3_NAND_RB_GPIO_PIN 10 - -static int nand_dev_ready(struct nand_chip *chip) -{ - return gpio_get_value(H3_NAND_RB_GPIO_PIN); -} - -static struct platform_nand_data nand_platdata = { - .chip = { - .nr_chips = 1, - .chip_offset = 0, - .nr_partitions = ARRAY_SIZE(nand_partitions), - .partitions = nand_partitions, - .options = NAND_SAMSUNG_LP_OPTIONS, - }, - .ctrl = { - .cmd_ctrl = omap1_nand_cmd_ctl, - .dev_ready = nand_dev_ready, - - }, -}; - -static struct resource nand_resource = { - .flags = IORESOURCE_MEM, -}; - -static struct platform_device nand_device = { - .name = "gen_nand", - .id = 0, - .dev = { - .platform_data = &nand_platdata, - }, - .num_resources = 1, - .resource = &nand_resource, -}; - -static struct smc91x_platdata smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - -static struct resource smc91x_resources[] = { - [0] = { - .start = OMAP1710_ETHR_START, /* Physical */ - .end = OMAP1710_ETHR_START + 0xf, - .flags = IORESOURCE_MEM, - }, - [1] = { - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, - }, -}; - -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = 0, - .dev = { - .platform_data = &smc91x_info, - }, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, -}; - -static void __init h3_init_smc91x(void) -{ - omap_cfg_reg(W15_1710_GPIO40); - if (gpio_request(40, "SMC91x irq") < 0) { - printk("Error requesting gpio 40 for smc91x irq\n"); - return; - } -} - -#define GPTIMER_BASE 0xFFFB1400 -#define GPTIMER_REGS(x) (0xFFFB1400 + (x * 0x800)) -#define GPTIMER_REGS_SIZE 0x46 - -static struct resource intlat_resources[] = { - [0] = { - .start = GPTIMER_REGS(0), /* Physical */ - .end = GPTIMER_REGS(0) + GPTIMER_REGS_SIZE, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = INT_1610_GPTIMER1, - .end = INT_1610_GPTIMER1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device intlat_device = { - .name = "omap_intlat", - .id = 0, - .num_resources = ARRAY_SIZE(intlat_resources), - .resource = intlat_resources, -}; - -static struct resource h3_kp_resources[] = { - [0] = { - .start = INT_KEYBOARD, - .end = INT_KEYBOARD, - .flags = IORESOURCE_IRQ, - }, -}; - -static const struct matrix_keymap_data h3_keymap_data = { - .keymap = h3_keymap, - .keymap_size = ARRAY_SIZE(h3_keymap), -}; - -static struct omap_kp_platform_data h3_kp_data = { - .rows = 8, - .cols = 8, - .keymap_data = &h3_keymap_data, - .rep = true, - .delay = 9, - .dbounce = true, -}; - -static struct platform_device h3_kp_device = { - .name = "omap-keypad", - .id = -1, - .dev = { - .platform_data = &h3_kp_data, - }, - .num_resources = ARRAY_SIZE(h3_kp_resources), - .resource = h3_kp_resources, -}; - -static struct platform_device h3_lcd_device = { - .name = "lcd_h3", - .id = -1, -}; - -static struct spi_board_info h3_spi_board_info[] __initdata = { - [0] = { - .modalias = "tsc2101", - .bus_num = 2, - .chip_select = 0, - .max_speed_hz = 16000000, - /* .platform_data = &tsc_platform_data, */ - }, -}; - -static const struct gpio_led h3_gpio_led_pins[] = { - { - .name = "h3:red", - .default_trigger = "heartbeat", - .gpio = 3, - }, - { - .name = "h3:green", - .default_trigger = "cpu0", - .gpio = OMAP_MPUIO(4), - }, -}; - -static struct gpio_led_platform_data h3_gpio_led_data = { - .leds = h3_gpio_led_pins, - .num_leds = ARRAY_SIZE(h3_gpio_led_pins), -}; - -static struct platform_device h3_gpio_leds = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &h3_gpio_led_data, - }, -}; - -static struct platform_device *devices[] __initdata = { - &nor_device, - &nand_device, - &smc91x_device, - &intlat_device, - &h3_kp_device, - &h3_lcd_device, - &h3_gpio_leds, -}; - -static struct omap_usb_config h3_usb_config __initdata = { - /* usb1 has a Mini-AB port and external isp1301 transceiver */ - .otg = 2, - -#if IS_ENABLED(CONFIG_USB_OMAP) - .hmc_mode = 19, /* 0:host(off) 1:dev|otg 2:disabled */ -#elif IS_ENABLED(CONFIG_USB_OHCI_HCD) - /* NONSTANDARD CABLE NEEDED (B-to-Mini-B) */ - .hmc_mode = 20, /* 1:dev|otg(off) 1:host 2:disabled */ -#endif - - .pins[1] = 3, -}; - -static const struct omap_lcd_config h3_lcd_config __initconst = { - .ctrl_name = "internal", -}; - -static struct i2c_board_info __initdata h3_i2c_board_info[] = { - { - I2C_BOARD_INFO("tps65013", 0x48), - }, - { - I2C_BOARD_INFO("isp1301_omap", 0x2d), - }, -}; - -static void __init h3_init(void) -{ - h3_init_smc91x(); - - /* Here we assume the NOR boot config: NOR on CS3 (possibly swapped - * to address 0 by a dip switch), NAND on CS2B. The NAND driver will - * notice whether a NAND chip is enabled at probe time. - * - * H3 support NAND-boot, with a dip switch to put NOR on CS2B and NAND - * (which on H2 may be 16bit) on CS3. Try detecting that in code here, - * to avoid probing every possible flash configuration... - */ - nor_resource.end = nor_resource.start = omap_cs3_phys(); - nor_resource.end += SZ_32M - 1; - - nand_resource.end = nand_resource.start = OMAP_CS2B_PHYS; - nand_resource.end += SZ_4K - 1; - BUG_ON(gpio_request(H3_NAND_RB_GPIO_PIN, "NAND ready") < 0); - gpio_direction_input(H3_NAND_RB_GPIO_PIN); - - /* GPIO10 Func_MUX_CTRL reg bit 29:27, Configure V2 to mode1 as GPIO */ - /* GPIO10 pullup/down register, Enable pullup on GPIO10 */ - omap_cfg_reg(V2_1710_GPIO10); - - /* Mux pins for keypad */ - omap_cfg_reg(F18_1610_KBC0); - omap_cfg_reg(D20_1610_KBC1); - omap_cfg_reg(D19_1610_KBC2); - omap_cfg_reg(E18_1610_KBC3); - omap_cfg_reg(C21_1610_KBC4); - omap_cfg_reg(G18_1610_KBR0); - omap_cfg_reg(F19_1610_KBR1); - omap_cfg_reg(H14_1610_KBR2); - omap_cfg_reg(E20_1610_KBR3); - omap_cfg_reg(E19_1610_KBR4); - omap_cfg_reg(N19_1610_KBR5); - - /* GPIO based LEDs */ - omap_cfg_reg(P18_1610_GPIO3); - omap_cfg_reg(MPUIO4); - - smc91x_resources[1].start = gpio_to_irq(40); - smc91x_resources[1].end = gpio_to_irq(40); - platform_add_devices(devices, ARRAY_SIZE(devices)); - h3_spi_board_info[0].irq = gpio_to_irq(H3_TS_GPIO); - spi_register_board_info(h3_spi_board_info, - ARRAY_SIZE(h3_spi_board_info)); - omap_serial_init(); - h3_i2c_board_info[1].irq = gpio_to_irq(14); - omap_register_i2c_bus(1, 100, h3_i2c_board_info, - ARRAY_SIZE(h3_i2c_board_info)); - omap1_usb_init(&h3_usb_config); - h3_mmc_init(); - - omapfb_set_lcd_config(&h3_lcd_config); -} - -MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board") - /* Maintainer: Texas Instruments, Inc. */ - .atag_offset = 0x100, - .map_io = omap16xx_map_io, - .init_early = omap1_init_early, - .init_irq = omap1_init_irq, - .handle_irq = omap1_handle_irq, - .init_machine = h3_init, - .init_late = omap1_init_late, - .init_time = omap1_timer_init, - .restart = omap1_restart, -MACHINE_END diff --git a/arch/arm/mach-omap1/board-h3.h b/arch/arm/mach-omap1/board-h3.h deleted file mode 100644 index 78de535be3c5..000000000000 --- a/arch/arm/mach-omap1/board-h3.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * arch/arm/mach-omap1/board-h3.h - * - * Copyright (C) 2001 RidgeRun, Inc. - * Copyright (C) 2004 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#ifndef __ASM_ARCH_OMAP_H3_H -#define __ASM_ARCH_OMAP_H3_H - -#define H3_TPS_GPIO_BASE (OMAP_MAX_GPIO_LINES + 16 /* MPUIO */) -# define H3_TPS_GPIO_MMC_PWR_EN (H3_TPS_GPIO_BASE + 4) - -extern void h3_mmc_init(void); - -#endif /* __ASM_ARCH_OMAP_H3_H */ diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c deleted file mode 100644 index 291d294b5824..000000000000 --- a/arch/arm/mach-omap1/board-htcherald.c +++ /dev/null @@ -1,585 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * HTC Herald board configuration - * Copyright (C) 2009 Cory Maccarrone - * Copyright (C) 2009 Wing Linux - * - * Based on the board-htcwizard.c file from the linwizard project: - * Copyright (C) 2006 Unai Uribarri - * Copyright (C) 2008 linwizard.sourceforge.net - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "hardware.h" -#include "omap7xx.h" -#include "mmc.h" -#include "irqs.h" -#include "usb.h" -#include "common.h" - -/* LCD register definition */ -#define OMAP_LCDC_CONTROL (0xfffec000 + 0x00) -#define OMAP_LCDC_STATUS (0xfffec000 + 0x10) -#define OMAP_DMA_LCD_CCR (0xfffee300 + 0xc2) -#define OMAP_DMA_LCD_CTRL (0xfffee300 + 0xc4) -#define OMAP_LCDC_CTRL_LCD_EN (1 << 0) -#define OMAP_LCDC_STAT_DONE (1 << 0) - -/* GPIO definitions for the power button and keyboard slide switch */ -#define HTCHERALD_GPIO_POWER 139 -#define HTCHERALD_GPIO_SLIDE 174 -#define HTCHERALD_GIRQ_BTNS 141 - -/* GPIO definitions for the touchscreen */ -#define HTCHERALD_GPIO_TS 76 - -/* HTCPLD definitions */ - -/* - * CPLD Logic - * - * Chip 3 - 0x03 - * - * Function 7 6 5 4 3 2 1 0 - * ------------------------------------ - * DPAD light x x x x x x x 1 - * SoundDev x x x x 1 x x x - * Screen white 1 x x x x x x x - * MMC power on x x x x x 1 x x - * Happy times (n) 0 x x x x 1 x x - * - * Chip 4 - 0x04 - * - * Function 7 6 5 4 3 2 1 0 - * ------------------------------------ - * Keyboard light x x x x x x x 1 - * LCD Bright (4) x x x x x 1 1 x - * LCD Bright (3) x x x x x 0 1 x - * LCD Bright (2) x x x x x 1 0 x - * LCD Bright (1) x x x x x 0 0 x - * LCD Off x x x x 0 x x x - * LCD image (fb) 1 x x x x x x x - * LCD image (white) 0 x x x x x x x - * Caps lock LED x x 1 x x x x x - * - * Chip 5 - 0x05 - * - * Function 7 6 5 4 3 2 1 0 - * ------------------------------------ - * Red (solid) x x x x x 1 x x - * Red (flash) x x x x x x 1 x - * Green (GSM flash) x x x x 1 x x x - * Green (GSM solid) x x x 1 x x x x - * Green (wifi flash) x x 1 x x x x x - * Blue (bt flash) x 1 x x x x x x - * DPAD Int Enable 1 x x x x x x 0 - * - * (Combinations of the above can be made for different colors.) - * The direction pad interrupt enable must be set each time the - * interrupt is handled. - * - * Chip 6 - 0x06 - * - * Function 7 6 5 4 3 2 1 0 - * ------------------------------------ - * Vibrator x x x x 1 x x x - * Alt LED x x x 1 x x x x - * Screen white 1 x x x x x x x - * Screen white x x 1 x x x x x - * Screen white x 0 x x x x x x - * Enable kbd dpad x x x x x x 0 x - * Happy Times 0 1 0 x x x 0 x - */ - -/* - * HTCPLD GPIO lines start 16 after OMAP_MAX_GPIO_LINES to account - * for the 16 MPUIO lines. - */ -#define HTCPLD_GPIO_START_OFFSET (OMAP_MAX_GPIO_LINES + 16) -#define HTCPLD_IRQ(chip, offset) (OMAP_IRQ_END + 8 * (chip) + (offset)) -#define HTCPLD_BASE(chip, offset) \ - (HTCPLD_GPIO_START_OFFSET + 8 * (chip) + (offset)) - -#define HTCPLD_GPIO_LED_DPAD HTCPLD_BASE(0, 0) -#define HTCPLD_GPIO_LED_KBD HTCPLD_BASE(1, 0) -#define HTCPLD_GPIO_LED_CAPS HTCPLD_BASE(1, 5) -#define HTCPLD_GPIO_LED_RED_FLASH HTCPLD_BASE(2, 1) -#define HTCPLD_GPIO_LED_RED_SOLID HTCPLD_BASE(2, 2) -#define HTCPLD_GPIO_LED_GREEN_FLASH HTCPLD_BASE(2, 3) -#define HTCPLD_GPIO_LED_GREEN_SOLID HTCPLD_BASE(2, 4) -#define HTCPLD_GPIO_LED_WIFI HTCPLD_BASE(2, 5) -#define HTCPLD_GPIO_LED_BT HTCPLD_BASE(2, 6) -#define HTCPLD_GPIO_LED_VIBRATE HTCPLD_BASE(3, 3) -#define HTCPLD_GPIO_LED_ALT HTCPLD_BASE(3, 4) - -#define HTCPLD_GPIO_RIGHT_KBD HTCPLD_BASE(6, 7) -#define HTCPLD_GPIO_UP_KBD HTCPLD_BASE(6, 6) -#define HTCPLD_GPIO_LEFT_KBD HTCPLD_BASE(6, 5) -#define HTCPLD_GPIO_DOWN_KBD HTCPLD_BASE(6, 4) - -#define HTCPLD_GPIO_RIGHT_DPAD HTCPLD_BASE(7, 7) -#define HTCPLD_GPIO_UP_DPAD HTCPLD_BASE(7, 6) -#define HTCPLD_GPIO_LEFT_DPAD HTCPLD_BASE(7, 5) -#define HTCPLD_GPIO_DOWN_DPAD HTCPLD_BASE(7, 4) -#define HTCPLD_GPIO_ENTER_DPAD HTCPLD_BASE(7, 3) - -/* Chip 5 */ -#define HTCPLD_IRQ_RIGHT_KBD HTCPLD_IRQ(0, 7) -#define HTCPLD_IRQ_UP_KBD HTCPLD_IRQ(0, 6) -#define HTCPLD_IRQ_LEFT_KBD HTCPLD_IRQ(0, 5) -#define HTCPLD_IRQ_DOWN_KBD HTCPLD_IRQ(0, 4) - -/* Chip 6 */ -#define HTCPLD_IRQ_RIGHT_DPAD HTCPLD_IRQ(1, 7) -#define HTCPLD_IRQ_UP_DPAD HTCPLD_IRQ(1, 6) -#define HTCPLD_IRQ_LEFT_DPAD HTCPLD_IRQ(1, 5) -#define HTCPLD_IRQ_DOWN_DPAD HTCPLD_IRQ(1, 4) -#define HTCPLD_IRQ_ENTER_DPAD HTCPLD_IRQ(1, 3) - -/* Keyboard definition */ - -static const unsigned int htc_herald_keymap[] = { - KEY(0, 0, KEY_RECORD), /* Mail button */ - KEY(1, 0, KEY_CAMERA), /* Camera */ - KEY(2, 0, KEY_PHONE), /* Send key */ - KEY(3, 0, KEY_VOLUMEUP), /* Volume up */ - KEY(4, 0, KEY_F2), /* Right bar (landscape) */ - KEY(5, 0, KEY_MAIL), /* Win key (portrait) */ - KEY(6, 0, KEY_DIRECTORY), /* Right bar (portrait) */ - KEY(0, 1, KEY_LEFTCTRL), /* Windows key */ - KEY(1, 1, KEY_COMMA), - KEY(2, 1, KEY_M), - KEY(3, 1, KEY_K), - KEY(4, 1, KEY_SLASH), /* OK key */ - KEY(5, 1, KEY_I), - KEY(6, 1, KEY_U), - KEY(0, 2, KEY_LEFTALT), - KEY(1, 2, KEY_TAB), - KEY(2, 2, KEY_N), - KEY(3, 2, KEY_J), - KEY(4, 2, KEY_ENTER), - KEY(5, 2, KEY_H), - KEY(6, 2, KEY_Y), - KEY(0, 3, KEY_SPACE), - KEY(1, 3, KEY_L), - KEY(2, 3, KEY_B), - KEY(3, 3, KEY_V), - KEY(4, 3, KEY_BACKSPACE), - KEY(5, 3, KEY_G), - KEY(6, 3, KEY_T), - KEY(0, 4, KEY_CAPSLOCK), /* Shift */ - KEY(1, 4, KEY_C), - KEY(2, 4, KEY_F), - KEY(3, 4, KEY_R), - KEY(4, 4, KEY_O), - KEY(5, 4, KEY_E), - KEY(6, 4, KEY_D), - KEY(0, 5, KEY_X), - KEY(1, 5, KEY_Z), - KEY(2, 5, KEY_S), - KEY(3, 5, KEY_W), - KEY(4, 5, KEY_P), - KEY(5, 5, KEY_Q), - KEY(6, 5, KEY_A), - KEY(0, 6, KEY_CONNECT), /* Voice button */ - KEY(2, 6, KEY_CANCEL), /* End key */ - KEY(3, 6, KEY_VOLUMEDOWN), /* Volume down */ - KEY(4, 6, KEY_F1), /* Left bar (landscape) */ - KEY(5, 6, KEY_WWW), /* OK button (portrait) */ - KEY(6, 6, KEY_CALENDAR), /* Left bar (portrait) */ -}; - -static const struct matrix_keymap_data htc_herald_keymap_data = { - .keymap = htc_herald_keymap, - .keymap_size = ARRAY_SIZE(htc_herald_keymap), -}; - -static struct omap_kp_platform_data htcherald_kp_data = { - .rows = 7, - .cols = 7, - .delay = 20, - .rep = true, - .keymap_data = &htc_herald_keymap_data, -}; - -static struct resource kp_resources[] = { - [0] = { - .start = INT_7XX_MPUIO_KEYPAD, - .end = INT_7XX_MPUIO_KEYPAD, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device kp_device = { - .name = "omap-keypad", - .id = -1, - .dev = { - .platform_data = &htcherald_kp_data, - }, - .num_resources = ARRAY_SIZE(kp_resources), - .resource = kp_resources, -}; - -/* GPIO buttons for keyboard slide and power button */ -static struct gpio_keys_button herald_gpio_keys_table[] = { - {BTN_0, HTCHERALD_GPIO_POWER, 1, "POWER", EV_KEY, 1, 20}, - {SW_LID, HTCHERALD_GPIO_SLIDE, 0, "SLIDE", EV_SW, 1, 20}, - - {KEY_LEFT, HTCPLD_GPIO_LEFT_KBD, 1, "LEFT", EV_KEY, 1, 20}, - {KEY_RIGHT, HTCPLD_GPIO_RIGHT_KBD, 1, "RIGHT", EV_KEY, 1, 20}, - {KEY_UP, HTCPLD_GPIO_UP_KBD, 1, "UP", EV_KEY, 1, 20}, - {KEY_DOWN, HTCPLD_GPIO_DOWN_KBD, 1, "DOWN", EV_KEY, 1, 20}, - - {KEY_LEFT, HTCPLD_GPIO_LEFT_DPAD, 1, "DLEFT", EV_KEY, 1, 20}, - {KEY_RIGHT, HTCPLD_GPIO_RIGHT_DPAD, 1, "DRIGHT", EV_KEY, 1, 20}, - {KEY_UP, HTCPLD_GPIO_UP_DPAD, 1, "DUP", EV_KEY, 1, 20}, - {KEY_DOWN, HTCPLD_GPIO_DOWN_DPAD, 1, "DDOWN", EV_KEY, 1, 20}, - {KEY_ENTER, HTCPLD_GPIO_ENTER_DPAD, 1, "DENTER", EV_KEY, 1, 20}, -}; - -static struct gpio_keys_platform_data herald_gpio_keys_data = { - .buttons = herald_gpio_keys_table, - .nbuttons = ARRAY_SIZE(herald_gpio_keys_table), - .rep = true, -}; - -static struct platform_device herald_gpiokeys_device = { - .name = "gpio-keys", - .id = -1, - .dev = { - .platform_data = &herald_gpio_keys_data, - }, -}; - -/* LEDs for the Herald. These connect to the HTCPLD GPIO device. */ -static const struct gpio_led gpio_leds[] = { - {"dpad", NULL, HTCPLD_GPIO_LED_DPAD, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"kbd", NULL, HTCPLD_GPIO_LED_KBD, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"vibrate", NULL, HTCPLD_GPIO_LED_VIBRATE, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"green_solid", NULL, HTCPLD_GPIO_LED_GREEN_SOLID, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"green_flash", NULL, HTCPLD_GPIO_LED_GREEN_FLASH, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"red_solid", "mmc0", HTCPLD_GPIO_LED_RED_SOLID, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"red_flash", NULL, HTCPLD_GPIO_LED_RED_FLASH, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"wifi", NULL, HTCPLD_GPIO_LED_WIFI, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"bt", NULL, HTCPLD_GPIO_LED_BT, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"caps", NULL, HTCPLD_GPIO_LED_CAPS, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"alt", NULL, HTCPLD_GPIO_LED_ALT, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, -}; - -static struct gpio_led_platform_data gpio_leds_data = { - .leds = gpio_leds, - .num_leds = ARRAY_SIZE(gpio_leds), -}; - -static struct platform_device gpio_leds_device = { - .name = "leds-gpio", - .id = 0, - .dev = { - .platform_data = &gpio_leds_data, - }, -}; - -/* HTC PLD chips */ - -static struct resource htcpld_resources[] = { - [0] = { - .flags = IORESOURCE_IRQ, - }, -}; - -static struct htcpld_chip_platform_data htcpld_chips[] = { - [0] = { - .addr = 0x03, - .reset = 0x04, - .num_gpios = 8, - .gpio_out_base = HTCPLD_BASE(0, 0), - .gpio_in_base = HTCPLD_BASE(4, 0), - }, - [1] = { - .addr = 0x04, - .reset = 0x8e, - .num_gpios = 8, - .gpio_out_base = HTCPLD_BASE(1, 0), - .gpio_in_base = HTCPLD_BASE(5, 0), - }, - [2] = { - .addr = 0x05, - .reset = 0x80, - .num_gpios = 8, - .gpio_out_base = HTCPLD_BASE(2, 0), - .gpio_in_base = HTCPLD_BASE(6, 0), - .irq_base = HTCPLD_IRQ(0, 0), - .num_irqs = 8, - }, - [3] = { - .addr = 0x06, - .reset = 0x40, - .num_gpios = 8, - .gpio_out_base = HTCPLD_BASE(3, 0), - .gpio_in_base = HTCPLD_BASE(7, 0), - .irq_base = HTCPLD_IRQ(1, 0), - .num_irqs = 8, - }, -}; - -static struct htcpld_core_platform_data htcpld_pfdata = { - .i2c_adapter_id = 1, - - .chip = htcpld_chips, - .num_chip = ARRAY_SIZE(htcpld_chips), -}; - -static struct platform_device htcpld_device = { - .name = "i2c-htcpld", - .id = -1, - .resource = htcpld_resources, - .num_resources = ARRAY_SIZE(htcpld_resources), - .dev = { - .platform_data = &htcpld_pfdata, - }, -}; - -/* USB Device */ -static struct omap_usb_config htcherald_usb_config __initdata = { - .otg = 0, - .register_host = 0, - .register_dev = 1, - .hmc_mode = 4, - .pins[0] = 2, -}; - -/* LCD Device resources */ -static const struct omap_lcd_config htcherald_lcd_config __initconst = { - .ctrl_name = "internal", -}; - -static struct platform_device lcd_device = { - .name = "lcd_htcherald", - .id = -1, -}; - -/* MMC Card */ -#if IS_ENABLED(CONFIG_MMC_OMAP) -static struct omap_mmc_platform_data htc_mmc1_data = { - .nr_slots = 1, - .switch_slot = NULL, - .slots[0] = { - .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, - .name = "mmcblk", - .nomux = 1, - .wires = 4, - .switch_pin = -1, - }, -}; - -static struct omap_mmc_platform_data *htc_mmc_data[1]; -#endif - - -/* Platform devices for the Herald */ -static struct platform_device *devices[] __initdata = { - &kp_device, - &lcd_device, - &htcpld_device, - &gpio_leds_device, - &herald_gpiokeys_device, -}; - -/* - * Touchscreen - */ -static const struct ads7846_platform_data htcherald_ts_platform_data = { - .model = 7846, - .keep_vref_on = 1, - .x_plate_ohms = 496, - .gpio_pendown = HTCHERALD_GPIO_TS, - .pressure_max = 10000, - .pressure_min = 5000, - .x_min = 528, - .x_max = 3760, - .y_min = 624, - .y_max = 3760, -}; - -static struct spi_board_info __initdata htcherald_spi_board_info[] = { - { - .modalias = "ads7846", - .platform_data = &htcherald_ts_platform_data, - .max_speed_hz = 2500000, - .bus_num = 2, - .chip_select = 1, - } -}; - -/* - * Init functions from here on - */ - -static void __init htcherald_lcd_init(void) -{ - u32 reg; - unsigned int tries = 200; - - /* disable controller if active */ - reg = omap_readl(OMAP_LCDC_CONTROL); - if (reg & OMAP_LCDC_CTRL_LCD_EN) { - reg &= ~OMAP_LCDC_CTRL_LCD_EN; - omap_writel(reg, OMAP_LCDC_CONTROL); - - /* wait for end of frame */ - while (!(omap_readl(OMAP_LCDC_STATUS) & OMAP_LCDC_STAT_DONE)) { - tries--; - if (!tries) - break; - } - if (!tries) - pr_err("Timeout waiting for end of frame -- LCD may not be available\n"); - - /* turn off DMA */ - reg = omap_readw(OMAP_DMA_LCD_CCR); - reg &= ~(1 << 7); - omap_writew(reg, OMAP_DMA_LCD_CCR); - - reg = omap_readw(OMAP_DMA_LCD_CTRL); - reg &= ~(1 << 8); - omap_writew(reg, OMAP_DMA_LCD_CTRL); - } -} - -static void __init htcherald_map_io(void) -{ - omap7xx_map_io(); - - /* - * The LCD panel must be disabled and DMA turned off here, as doing - * it later causes the LCD never to reinitialize. - */ - htcherald_lcd_init(); - - printk(KERN_INFO "htcherald_map_io done.\n"); -} - -static void __init htcherald_disable_watchdog(void) -{ - /* Disable watchdog if running */ - if (omap_readl(OMAP_WDT_TIMER_MODE) & 0x8000) { - /* - * disable a potentially running watchdog timer before - * it kills us. - */ - printk(KERN_WARNING "OMAP850 Watchdog seems to be activated, disabling it for now.\n"); - omap_writel(0xF5, OMAP_WDT_TIMER_MODE); - omap_writel(0xA0, OMAP_WDT_TIMER_MODE); - } -} - -#define HTCHERALD_GPIO_USB_EN1 33 -#define HTCHERALD_GPIO_USB_EN2 73 -#define HTCHERALD_GPIO_USB_DM 35 -#define HTCHERALD_GPIO_USB_DP 36 - -static void __init htcherald_usb_enable(void) -{ - unsigned int tries = 20; - unsigned int value = 0; - - /* Request the GPIOs we need to control here */ - if (gpio_request(HTCHERALD_GPIO_USB_EN1, "herald_usb") < 0) - goto err1; - - if (gpio_request(HTCHERALD_GPIO_USB_EN2, "herald_usb") < 0) - goto err2; - - if (gpio_request(HTCHERALD_GPIO_USB_DM, "herald_usb") < 0) - goto err3; - - if (gpio_request(HTCHERALD_GPIO_USB_DP, "herald_usb") < 0) - goto err4; - - /* force USB_EN GPIO to 0 */ - do { - /* output low */ - gpio_direction_output(HTCHERALD_GPIO_USB_EN1, 0); - } while ((value = gpio_get_value(HTCHERALD_GPIO_USB_EN1)) == 1 && - --tries); - - if (value == 1) - printk(KERN_WARNING "Unable to reset USB, trying to continue\n"); - - gpio_direction_output(HTCHERALD_GPIO_USB_EN2, 0); /* output low */ - gpio_direction_input(HTCHERALD_GPIO_USB_DM); /* input */ - gpio_direction_input(HTCHERALD_GPIO_USB_DP); /* input */ - - goto done; - -err4: - gpio_free(HTCHERALD_GPIO_USB_DM); -err3: - gpio_free(HTCHERALD_GPIO_USB_EN2); -err2: - gpio_free(HTCHERALD_GPIO_USB_EN1); -err1: - printk(KERN_ERR "Unabled to request GPIO for USB\n"); -done: - printk(KERN_INFO "USB setup complete.\n"); -} - -static void __init htcherald_init(void) -{ - printk(KERN_INFO "HTC Herald init.\n"); - - /* Do board initialization before we register all the devices */ - htcpld_resources[0].start = gpio_to_irq(HTCHERALD_GIRQ_BTNS); - htcpld_resources[0].end = gpio_to_irq(HTCHERALD_GIRQ_BTNS); - platform_add_devices(devices, ARRAY_SIZE(devices)); - - htcherald_disable_watchdog(); - - htcherald_usb_enable(); - omap1_usb_init(&htcherald_usb_config); - - htcherald_spi_board_info[0].irq = gpio_to_irq(HTCHERALD_GPIO_TS); - spi_register_board_info(htcherald_spi_board_info, - ARRAY_SIZE(htcherald_spi_board_info)); - - omap_register_i2c_bus(1, 100, NULL, 0); - -#if IS_ENABLED(CONFIG_MMC_OMAP) - htc_mmc_data[0] = &htc_mmc1_data; - omap1_init_mmc(htc_mmc_data, 1); -#endif - - omapfb_set_lcd_config(&htcherald_lcd_config); -} - -MACHINE_START(HERALD, "HTC Herald") - /* Maintainer: Cory Maccarrone */ - /* Maintainer: wing-linux.sourceforge.net */ - .atag_offset = 0x100, - .map_io = htcherald_map_io, - .init_early = omap1_init_early, - .init_irq = omap1_init_irq, - .handle_irq = omap1_handle_irq, - .init_machine = htcherald_init, - .init_late = omap1_init_late, - .init_time = omap1_timer_init, - .restart = omap1_restart, -MACHINE_END diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c deleted file mode 100644 index 6deb4ca079e9..000000000000 --- a/arch/arm/mach-omap1/board-innovator.c +++ /dev/null @@ -1,481 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-omap1/board-innovator.c - * - * Board specific inits for OMAP-1510 and OMAP-1610 Innovator - * - * Copyright (C) 2001 RidgeRun, Inc. - * Author: Greg Lonnon - * - * Copyright (C) 2002 MontaVista Software, Inc. - * - * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6 - * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "tc.h" -#include "mux.h" -#include "flash.h" -#include "hardware.h" -#include "usb.h" -#include "iomap.h" -#include "common.h" -#include "mmc.h" - -/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */ -#define INNOVATOR1610_ETHR_START 0x04000300 - -static const unsigned int innovator_keymap[] = { - KEY(0, 0, KEY_F1), - KEY(3, 0, KEY_DOWN), - KEY(1, 1, KEY_F2), - KEY(2, 1, KEY_RIGHT), - KEY(0, 2, KEY_F3), - KEY(1, 2, KEY_F4), - KEY(2, 2, KEY_UP), - KEY(2, 3, KEY_ENTER), - KEY(3, 3, KEY_LEFT), -}; - -static struct mtd_partition innovator_partitions[] = { - /* bootloader (U-Boot, etc) in first sector */ - { - .name = "bootloader", - .offset = 0, - .size = SZ_128K, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - /* bootloader params in the next sector */ - { - .name = "params", - .offset = MTDPART_OFS_APPEND, - .size = SZ_128K, - .mask_flags = 0, - }, - /* kernel */ - { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_2M, - .mask_flags = 0 - }, - /* rest of flash1 is a file system */ - { - .name = "rootfs", - .offset = MTDPART_OFS_APPEND, - .size = SZ_16M - SZ_2M - 2 * SZ_128K, - .mask_flags = 0 - }, - /* file system */ - { - .name = "filesystem", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0 - } -}; - -static struct physmap_flash_data innovator_flash_data = { - .width = 2, - .set_vpp = omap1_set_vpp, - .parts = innovator_partitions, - .nr_parts = ARRAY_SIZE(innovator_partitions), -}; - -static struct resource innovator_flash_resource = { - .start = OMAP_CS0_PHYS, - .end = OMAP_CS0_PHYS + SZ_32M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device innovator_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &innovator_flash_data, - }, - .num_resources = 1, - .resource = &innovator_flash_resource, -}; - -static struct resource innovator_kp_resources[] = { - [0] = { - .start = INT_KEYBOARD, - .end = INT_KEYBOARD, - .flags = IORESOURCE_IRQ, - }, -}; - -static const struct matrix_keymap_data innovator_keymap_data = { - .keymap = innovator_keymap, - .keymap_size = ARRAY_SIZE(innovator_keymap), -}; - -static struct omap_kp_platform_data innovator_kp_data = { - .rows = 8, - .cols = 8, - .keymap_data = &innovator_keymap_data, - .delay = 4, -}; - -static struct platform_device innovator_kp_device = { - .name = "omap-keypad", - .id = -1, - .dev = { - .platform_data = &innovator_kp_data, - }, - .num_resources = ARRAY_SIZE(innovator_kp_resources), - .resource = innovator_kp_resources, -}; - -static struct smc91x_platdata innovator_smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - -#ifdef CONFIG_ARCH_OMAP15XX - -#include -#include - - -/* Only FPGA needs to be mapped here. All others are done with ioremap */ -static struct map_desc innovator1510_io_desc[] __initdata = { - { - .virtual = OMAP1510_FPGA_BASE, - .pfn = __phys_to_pfn(OMAP1510_FPGA_START), - .length = OMAP1510_FPGA_SIZE, - .type = MT_DEVICE - } -}; - -static struct resource innovator1510_smc91x_resources[] = { - [0] = { - .start = OMAP1510_FPGA_ETHR_START, /* Physical */ - .end = OMAP1510_FPGA_ETHR_START + 0xf, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = OMAP1510_INT_ETHER, - .end = OMAP1510_INT_ETHER, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, - }, -}; - -static struct platform_device innovator1510_smc91x_device = { - .name = "smc91x", - .id = 0, - .dev = { - .platform_data = &innovator_smc91x_info, - }, - .num_resources = ARRAY_SIZE(innovator1510_smc91x_resources), - .resource = innovator1510_smc91x_resources, -}; - -static struct platform_device innovator1510_lcd_device = { - .name = "lcd_inn1510", - .id = -1, - .dev = { - .platform_data = (void __force *)OMAP1510_FPGA_LCD_PANEL_CONTROL, - } -}; - -static struct platform_device innovator1510_spi_device = { - .name = "spi_inn1510", - .id = -1, -}; - -static struct platform_device *innovator1510_devices[] __initdata = { - &innovator_flash_device, - &innovator1510_smc91x_device, - &innovator_kp_device, - &innovator1510_lcd_device, - &innovator1510_spi_device, -}; - -static int innovator_get_pendown_state(void) -{ - return !(__raw_readb(OMAP1510_FPGA_TOUCHSCREEN) & (1 << 5)); -} - -static const struct ads7846_platform_data innovator1510_ts_info = { - .model = 7846, - .vref_delay_usecs = 100, /* internal, no capacitor */ - .x_plate_ohms = 419, - .y_plate_ohms = 486, - .get_pendown_state = innovator_get_pendown_state, -}; - -static struct spi_board_info __initdata innovator1510_boardinfo[] = { { - /* FPGA (bus "10") CS0 has an ads7846e */ - .modalias = "ads7846", - .platform_data = &innovator1510_ts_info, - .irq = OMAP1510_INT_FPGA_TS, - .max_speed_hz = 120000 /* max sample rate at 3V */ - * 26 /* command + data + overhead */, - .bus_num = 10, - .chip_select = 0, -} }; - -#endif /* CONFIG_ARCH_OMAP15XX */ - -#ifdef CONFIG_ARCH_OMAP16XX - -static struct resource innovator1610_smc91x_resources[] = { - [0] = { - .start = INNOVATOR1610_ETHR_START, /* Physical */ - .end = INNOVATOR1610_ETHR_START + 0xf, - .flags = IORESOURCE_MEM, - }, - [1] = { - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, - }, -}; - -static struct platform_device innovator1610_smc91x_device = { - .name = "smc91x", - .id = 0, - .dev = { - .platform_data = &innovator_smc91x_info, - }, - .num_resources = ARRAY_SIZE(innovator1610_smc91x_resources), - .resource = innovator1610_smc91x_resources, -}; - -static struct platform_device innovator1610_lcd_device = { - .name = "inn1610_lcd", - .id = -1, -}; - -static struct platform_device *innovator1610_devices[] __initdata = { - &innovator_flash_device, - &innovator1610_smc91x_device, - &innovator_kp_device, - &innovator1610_lcd_device, -}; - -#endif /* CONFIG_ARCH_OMAP16XX */ - -static void __init innovator_init_smc91x(void) -{ - if (cpu_is_omap1510()) { - __raw_writeb(__raw_readb(OMAP1510_FPGA_RST) & ~1, - OMAP1510_FPGA_RST); - udelay(750); - } else { - if (gpio_request(0, "SMC91x irq") < 0) { - printk("Error requesting gpio 0 for smc91x irq\n"); - return; - } - } -} - -#ifdef CONFIG_ARCH_OMAP15XX -/* - * Board specific gang-switched transceiver power on/off. - */ -static int innovator_omap_ohci_transceiver_power(int on) -{ - if (on) - __raw_writeb(__raw_readb(INNOVATOR_FPGA_CAM_USB_CONTROL) - | ((1 << 5/*usb1*/) | (1 << 3/*usb2*/)), - INNOVATOR_FPGA_CAM_USB_CONTROL); - else - __raw_writeb(__raw_readb(INNOVATOR_FPGA_CAM_USB_CONTROL) - & ~((1 << 5/*usb1*/) | (1 << 3/*usb2*/)), - INNOVATOR_FPGA_CAM_USB_CONTROL); - - return 0; -} - -static struct omap_usb_config innovator1510_usb_config __initdata = { - /* for bundled non-standard host and peripheral cables */ - .hmc_mode = 4, - - .register_host = 1, - .pins[1] = 6, - .pins[2] = 6, /* Conflicts with UART2 */ - - .register_dev = 1, - .pins[0] = 2, - - .transceiver_power = innovator_omap_ohci_transceiver_power, -}; - -static const struct omap_lcd_config innovator1510_lcd_config __initconst = { - .ctrl_name = "internal", -}; -#endif - -#ifdef CONFIG_ARCH_OMAP16XX -static struct omap_usb_config h2_usb_config __initdata = { - /* usb1 has a Mini-AB port and external isp1301 transceiver */ - .otg = 2, - -#if IS_ENABLED(CONFIG_USB_OMAP) - .hmc_mode = 19, /* 0:host(off) 1:dev|otg 2:disabled */ - /* .hmc_mode = 21,*/ /* 0:host(off) 1:dev(loopback) 2:host(loopback) */ -#elif IS_ENABLED(CONFIG_USB_OHCI_HCD) - /* NONSTANDARD CABLE NEEDED (B-to-Mini-B) */ - .hmc_mode = 20, /* 1:dev|otg(off) 1:host 2:disabled */ -#endif - - .pins[1] = 3, -}; - -static const struct omap_lcd_config innovator1610_lcd_config __initconst = { - .ctrl_name = "internal", -}; -#endif - -#if IS_ENABLED(CONFIG_MMC_OMAP) - -static int mmc_set_power(struct device *dev, int slot, int power_on, - int vdd) -{ - if (power_on) - __raw_writeb(__raw_readb(OMAP1510_FPGA_POWER) | (1 << 3), - OMAP1510_FPGA_POWER); - else - __raw_writeb(__raw_readb(OMAP1510_FPGA_POWER) & ~(1 << 3), - OMAP1510_FPGA_POWER); - - return 0; -} - -/* - * Innovator could use the following functions tested: - * - mmc_get_wp that uses OMAP_MPUIO(3) - * - mmc_get_cover_state that uses FPGA F4 UIO43 - */ -static struct omap_mmc_platform_data mmc1_data = { - .nr_slots = 1, - .slots[0] = { - .set_power = mmc_set_power, - .wires = 4, - .name = "mmcblk", - }, -}; - -static struct omap_mmc_platform_data *mmc_data[OMAP16XX_NR_MMC]; - -static void __init innovator_mmc_init(void) -{ - mmc_data[0] = &mmc1_data; - omap1_init_mmc(mmc_data, OMAP15XX_NR_MMC); -} - -#else -static inline void innovator_mmc_init(void) -{ -} -#endif - -static void __init innovator_init(void) -{ - if (cpu_is_omap1510()) - omap1510_fpga_init_irq(); - innovator_init_smc91x(); - -#ifdef CONFIG_ARCH_OMAP15XX - if (cpu_is_omap1510()) { - unsigned char reg; - - /* mux pins for uarts */ - omap_cfg_reg(UART1_TX); - omap_cfg_reg(UART1_RTS); - omap_cfg_reg(UART2_TX); - omap_cfg_reg(UART2_RTS); - omap_cfg_reg(UART3_TX); - omap_cfg_reg(UART3_RX); - - reg = __raw_readb(OMAP1510_FPGA_POWER); - reg |= OMAP1510_FPGA_PCR_COM1_EN; - __raw_writeb(reg, OMAP1510_FPGA_POWER); - udelay(10); - - reg = __raw_readb(OMAP1510_FPGA_POWER); - reg |= OMAP1510_FPGA_PCR_COM2_EN; - __raw_writeb(reg, OMAP1510_FPGA_POWER); - udelay(10); - - platform_add_devices(innovator1510_devices, ARRAY_SIZE(innovator1510_devices)); - spi_register_board_info(innovator1510_boardinfo, - ARRAY_SIZE(innovator1510_boardinfo)); - } -#endif -#ifdef CONFIG_ARCH_OMAP16XX - if (!cpu_is_omap1510()) { - innovator1610_smc91x_resources[1].start = gpio_to_irq(0); - innovator1610_smc91x_resources[1].end = gpio_to_irq(0); - platform_add_devices(innovator1610_devices, ARRAY_SIZE(innovator1610_devices)); - } -#endif - -#ifdef CONFIG_ARCH_OMAP15XX - if (cpu_is_omap1510()) { - omap1_usb_init(&innovator1510_usb_config); - omapfb_set_lcd_config(&innovator1510_lcd_config); - } -#endif -#ifdef CONFIG_ARCH_OMAP16XX - if (cpu_is_omap1610()) { - omap1_usb_init(&h2_usb_config); - omapfb_set_lcd_config(&innovator1610_lcd_config); - } -#endif - omap_serial_init(); - omap_register_i2c_bus(1, 100, NULL, 0); - innovator_mmc_init(); -} - -/* - * REVISIT: Assume 15xx for now, we don't want to do revision check - * until later on. The right way to fix this is to set up a different - * machine_id for 16xx Innovator, or use device tree. - */ -static void __init innovator_map_io(void) -{ -#ifdef CONFIG_ARCH_OMAP15XX - omap15xx_map_io(); - - iotable_init(innovator1510_io_desc, ARRAY_SIZE(innovator1510_io_desc)); - udelay(10); /* Delay needed for FPGA */ - - /* Dump the Innovator FPGA rev early - useful info for support. */ - pr_debug("Innovator FPGA Rev %d.%d Board Rev %d\n", - __raw_readb(OMAP1510_FPGA_REV_HIGH), - __raw_readb(OMAP1510_FPGA_REV_LOW), - __raw_readb(OMAP1510_FPGA_BOARD_REV)); -#endif -} - -MACHINE_START(OMAP_INNOVATOR, "TI-Innovator") - /* Maintainer: MontaVista Software, Inc. */ - .atag_offset = 0x100, - .map_io = innovator_map_io, - .init_early = omap1_init_early, - .init_irq = omap1_init_irq, - .handle_irq = omap1_handle_irq, - .init_machine = innovator_init, - .init_late = omap1_init_late, - .init_time = omap1_timer_init, - .restart = omap1_restart, -MACHINE_END diff --git a/arch/arm/mach-omap1/board-nand.c b/arch/arm/mach-omap1/board-nand.c deleted file mode 100644 index 479ab9be784d..000000000000 --- a/arch/arm/mach-omap1/board-nand.c +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-omap1/board-nand.c - * - * Common OMAP1 board NAND code - * - * Copyright (C) 2004, 2012 Texas Instruments, Inc. - * Copyright (C) 2002 MontaVista Software, Inc. - * Copyright (C) 2001 RidgeRun, Inc. - * Author: RidgeRun, Inc. - * Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com - */ -#include -#include -#include -#include - -#include "common.h" - -void omap1_nand_cmd_ctl(struct nand_chip *this, int cmd, unsigned int ctrl) -{ - unsigned long mask; - - if (cmd == NAND_CMD_NONE) - return; - - mask = (ctrl & NAND_CLE) ? 0x02 : 0; - if (ctrl & NAND_ALE) - mask |= 0x04; - - writeb(cmd, this->legacy.IO_ADDR_W + mask); -} - diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c deleted file mode 100644 index 537f0e6a2ff7..000000000000 --- a/arch/arm/mach-omap1/board-palmtt.c +++ /dev/null @@ -1,285 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-omap1/board-palmtt.c - * - * Modified from board-palmtt2.c - * - * Modified and amended for Palm Tungsten|T - * by Marek Vasut - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "tc.h" -#include "flash.h" -#include "mux.h" -#include "hardware.h" -#include "usb.h" -#include "common.h" - -#define PALMTT_USBDETECT_GPIO 0 -#define PALMTT_CABLE_GPIO 1 -#define PALMTT_LED_GPIO 3 -#define PALMTT_PENIRQ_GPIO 6 -#define PALMTT_MMC_WP_GPIO 8 -#define PALMTT_HDQ_GPIO 11 - -static const unsigned int palmtt_keymap[] = { - KEY(0, 0, KEY_ESC), - KEY(1, 0, KEY_SPACE), - KEY(2, 0, KEY_LEFTCTRL), - KEY(3, 0, KEY_TAB), - KEY(4, 0, KEY_ENTER), - KEY(0, 1, KEY_LEFT), - KEY(1, 1, KEY_DOWN), - KEY(2, 1, KEY_UP), - KEY(3, 1, KEY_RIGHT), - KEY(0, 2, KEY_SLEEP), - KEY(4, 2, KEY_Y), -}; - -static struct mtd_partition palmtt_partitions[] = { - { - .name = "write8k", - .offset = 0, - .size = SZ_8K, - .mask_flags = 0, - }, - { - .name = "PalmOS-BootLoader(ro)", - .offset = SZ_8K, - .size = 7 * SZ_8K, - .mask_flags = MTD_WRITEABLE, - }, - { - .name = "u-boot", - .offset = MTDPART_OFS_APPEND, - .size = 8 * SZ_8K, - .mask_flags = 0, - }, - { - .name = "PalmOS-FS(ro)", - .offset = MTDPART_OFS_APPEND, - .size = 7 * SZ_1M + 4 * SZ_64K - 16 * SZ_8K, - .mask_flags = MTD_WRITEABLE, - }, - { - .name = "u-boot(rez)", - .offset = MTDPART_OFS_APPEND, - .size = SZ_128K, - .mask_flags = 0 - }, - { - .name = "empty", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0 - } -}; - -static struct physmap_flash_data palmtt_flash_data = { - .width = 2, - .set_vpp = omap1_set_vpp, - .parts = palmtt_partitions, - .nr_parts = ARRAY_SIZE(palmtt_partitions), -}; - -static struct resource palmtt_flash_resource = { - .start = OMAP_CS0_PHYS, - .end = OMAP_CS0_PHYS + SZ_8M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device palmtt_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &palmtt_flash_data, - }, - .num_resources = 1, - .resource = &palmtt_flash_resource, -}; - -static struct resource palmtt_kp_resources[] = { - [0] = { - .start = INT_KEYBOARD, - .end = INT_KEYBOARD, - .flags = IORESOURCE_IRQ, - }, -}; - -static const struct matrix_keymap_data palmtt_keymap_data = { - .keymap = palmtt_keymap, - .keymap_size = ARRAY_SIZE(palmtt_keymap), -}; - -static struct omap_kp_platform_data palmtt_kp_data = { - .rows = 6, - .cols = 3, - .keymap_data = &palmtt_keymap_data, -}; - -static struct platform_device palmtt_kp_device = { - .name = "omap-keypad", - .id = -1, - .dev = { - .platform_data = &palmtt_kp_data, - }, - .num_resources = ARRAY_SIZE(palmtt_kp_resources), - .resource = palmtt_kp_resources, -}; - -static struct platform_device palmtt_lcd_device = { - .name = "lcd_palmtt", - .id = -1, -}; - -static struct platform_device palmtt_spi_device = { - .name = "spi_palmtt", - .id = -1, -}; - -static struct omap_backlight_config palmtt_backlight_config = { - .default_intensity = 0xa0, -}; - -static struct platform_device palmtt_backlight_device = { - .name = "omap-bl", - .id = -1, - .dev = { - .platform_data= &palmtt_backlight_config, - }, -}; - -static struct omap_led_config palmtt_led_config[] = { - { - .cdev = { - .name = "palmtt:led0", - }, - .gpio = PALMTT_LED_GPIO, - }, -}; - -static struct omap_led_platform_data palmtt_led_data = { - .nr_leds = ARRAY_SIZE(palmtt_led_config), - .leds = palmtt_led_config, -}; - -static struct platform_device palmtt_led_device = { - .name = "omap-led", - .id = -1, - .dev = { - .platform_data = &palmtt_led_data, - }, -}; - -static struct platform_device *palmtt_devices[] __initdata = { - &palmtt_flash_device, - &palmtt_kp_device, - &palmtt_lcd_device, - &palmtt_spi_device, - &palmtt_backlight_device, - &palmtt_led_device, -}; - -static int palmtt_get_pendown_state(void) -{ - return !gpio_get_value(6); -} - -static const struct ads7846_platform_data palmtt_ts_info = { - .model = 7846, - .vref_delay_usecs = 100, /* internal, no capacitor */ - .x_plate_ohms = 419, - .y_plate_ohms = 486, - .get_pendown_state = palmtt_get_pendown_state, -}; - -static struct spi_board_info __initdata palmtt_boardinfo[] = { - { - /* MicroWire (bus 2) CS0 has an ads7846e */ - .modalias = "ads7846", - .platform_data = &palmtt_ts_info, - .max_speed_hz = 120000 /* max sample rate at 3V */ - * 26 /* command + data + overhead */, - .bus_num = 2, - .chip_select = 0, - } -}; - -static struct omap_usb_config palmtt_usb_config __initdata = { - .register_dev = 1, - .hmc_mode = 0, - .pins[0] = 2, -}; - -static const struct omap_lcd_config palmtt_lcd_config __initconst = { - .ctrl_name = "internal", -}; - -static void __init omap_mpu_wdt_mode(int mode) { - if (mode) - omap_writew(0x8000, OMAP_WDT_TIMER_MODE); - else { - omap_writew(0x00f5, OMAP_WDT_TIMER_MODE); - omap_writew(0x00a0, OMAP_WDT_TIMER_MODE); - } -} - -static void __init omap_palmtt_init(void) -{ - /* mux pins for uarts */ - omap_cfg_reg(UART1_TX); - omap_cfg_reg(UART1_RTS); - omap_cfg_reg(UART2_TX); - omap_cfg_reg(UART2_RTS); - omap_cfg_reg(UART3_TX); - omap_cfg_reg(UART3_RX); - - omap_mpu_wdt_mode(0); - - platform_add_devices(palmtt_devices, ARRAY_SIZE(palmtt_devices)); - - palmtt_boardinfo[0].irq = gpio_to_irq(6); - spi_register_board_info(palmtt_boardinfo,ARRAY_SIZE(palmtt_boardinfo)); - omap_serial_init(); - omap1_usb_init(&palmtt_usb_config); - omap_register_i2c_bus(1, 100, NULL, 0); - - omapfb_set_lcd_config(&palmtt_lcd_config); -} - -MACHINE_START(OMAP_PALMTT, "OMAP1510 based Palm Tungsten|T") - .atag_offset = 0x100, - .map_io = omap15xx_map_io, - .init_early = omap1_init_early, - .init_irq = omap1_init_irq, - .handle_irq = omap1_handle_irq, - .init_machine = omap_palmtt_init, - .init_late = omap1_init_late, - .init_time = omap1_timer_init, - .restart = omap1_restart, -MACHINE_END diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c deleted file mode 100644 index 47f08ae5a2f3..000000000000 --- a/arch/arm/mach-omap1/board-palmz71.c +++ /dev/null @@ -1,300 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-omap1/board-palmz71.c - * - * Modified from board-generic.c - * - * Support for the Palm Zire71 PDA. - * - * Original version : Laurent Gonzalez - * - * Modified for zire71 : Marek Vasut - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "tc.h" -#include "flash.h" -#include "mux.h" -#include "hardware.h" -#include "usb.h" -#include "common.h" - -#define PALMZ71_USBDETECT_GPIO 0 -#define PALMZ71_PENIRQ_GPIO 6 -#define PALMZ71_MMC_WP_GPIO 8 -#define PALMZ71_HDQ_GPIO 11 - -#define PALMZ71_HOTSYNC_GPIO OMAP_MPUIO(1) -#define PALMZ71_CABLE_GPIO OMAP_MPUIO(2) -#define PALMZ71_SLIDER_GPIO OMAP_MPUIO(3) -#define PALMZ71_MMC_IN_GPIO OMAP_MPUIO(4) - -static const unsigned int palmz71_keymap[] = { - KEY(0, 0, KEY_F1), - KEY(1, 0, KEY_F2), - KEY(2, 0, KEY_F3), - KEY(3, 0, KEY_F4), - KEY(4, 0, KEY_POWER), - KEY(0, 1, KEY_LEFT), - KEY(1, 1, KEY_DOWN), - KEY(2, 1, KEY_UP), - KEY(3, 1, KEY_RIGHT), - KEY(4, 1, KEY_ENTER), - KEY(0, 2, KEY_CAMERA), -}; - -static const struct matrix_keymap_data palmz71_keymap_data = { - .keymap = palmz71_keymap, - .keymap_size = ARRAY_SIZE(palmz71_keymap), -}; - -static struct omap_kp_platform_data palmz71_kp_data = { - .rows = 8, - .cols = 8, - .keymap_data = &palmz71_keymap_data, - .rep = true, - .delay = 80, -}; - -static struct resource palmz71_kp_resources[] = { - [0] = { - .start = INT_KEYBOARD, - .end = INT_KEYBOARD, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device palmz71_kp_device = { - .name = "omap-keypad", - .id = -1, - .dev = { - .platform_data = &palmz71_kp_data, - }, - .num_resources = ARRAY_SIZE(palmz71_kp_resources), - .resource = palmz71_kp_resources, -}; - -static struct mtd_partition palmz71_rom_partitions[] = { - /* PalmOS "Small ROM", contains the bootloader and the debugger */ - { - .name = "smallrom", - .offset = 0, - .size = 0xa000, - .mask_flags = MTD_WRITEABLE, - }, - /* PalmOS "Big ROM", a filesystem with all the OS code and data */ - { - .name = "bigrom", - .offset = SZ_128K, - /* - * 0x5f0000 bytes big in the multi-language ("EFIGS") version, - * 0x7b0000 bytes in the English-only ("enUS") version. - */ - .size = 0x7b0000, - .mask_flags = MTD_WRITEABLE, - }, -}; - -static struct physmap_flash_data palmz71_rom_data = { - .width = 2, - .set_vpp = omap1_set_vpp, - .parts = palmz71_rom_partitions, - .nr_parts = ARRAY_SIZE(palmz71_rom_partitions), -}; - -static struct resource palmz71_rom_resource = { - .start = OMAP_CS0_PHYS, - .end = OMAP_CS0_PHYS + SZ_8M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device palmz71_rom_device = { - .name = "physmap-flash", - .id = -1, - .dev = { - .platform_data = &palmz71_rom_data, - }, - .num_resources = 1, - .resource = &palmz71_rom_resource, -}; - -static struct platform_device palmz71_lcd_device = { - .name = "lcd_palmz71", - .id = -1, -}; - -static struct platform_device palmz71_spi_device = { - .name = "spi_palmz71", - .id = -1, -}; - -static struct omap_backlight_config palmz71_backlight_config = { - .default_intensity = 0xa0, -}; - -static struct platform_device palmz71_backlight_device = { - .name = "omap-bl", - .id = -1, - .dev = { - .platform_data = &palmz71_backlight_config, - }, -}; - -static struct platform_device *devices[] __initdata = { - &palmz71_rom_device, - &palmz71_kp_device, - &palmz71_lcd_device, - &palmz71_spi_device, - &palmz71_backlight_device, -}; - -static int -palmz71_get_pendown_state(void) -{ - return !gpio_get_value(PALMZ71_PENIRQ_GPIO); -} - -static const struct ads7846_platform_data palmz71_ts_info = { - .model = 7846, - .vref_delay_usecs = 100, /* internal, no capacitor */ - .x_plate_ohms = 419, - .y_plate_ohms = 486, - .get_pendown_state = palmz71_get_pendown_state, -}; - -static struct spi_board_info __initdata palmz71_boardinfo[] = { { - /* MicroWire (bus 2) CS0 has an ads7846e */ - .modalias = "ads7846", - .platform_data = &palmz71_ts_info, - .max_speed_hz = 120000 /* max sample rate at 3V */ - * 26 /* command + data + overhead */, - .bus_num = 2, - .chip_select = 0, -} }; - -static struct omap_usb_config palmz71_usb_config __initdata = { - .register_dev = 1, /* Mini-B only receptacle */ - .hmc_mode = 0, - .pins[0] = 2, -}; - -static const struct omap_lcd_config palmz71_lcd_config __initconst = { - .ctrl_name = "internal", -}; - -static irqreturn_t -palmz71_powercable(int irq, void *dev_id) -{ - if (gpio_get_value(PALMZ71_USBDETECT_GPIO)) { - printk(KERN_INFO "PM: Power cable connected\n"); - irq_set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO), - IRQ_TYPE_EDGE_FALLING); - } else { - printk(KERN_INFO "PM: Power cable disconnected\n"); - irq_set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO), - IRQ_TYPE_EDGE_RISING); - } - return IRQ_HANDLED; -} - -static void __init -omap_mpu_wdt_mode(int mode) -{ - if (mode) - omap_writew(0x8000, OMAP_WDT_TIMER_MODE); - else { - omap_writew(0x00f5, OMAP_WDT_TIMER_MODE); - omap_writew(0x00a0, OMAP_WDT_TIMER_MODE); - } -} - -static void __init -palmz71_gpio_setup(int early) -{ - if (early) { - /* Only set GPIO1 so we have a working serial */ - gpio_direction_output(1, 1); - } else { - /* Set MMC/SD host WP pin as input */ - if (gpio_request(PALMZ71_MMC_WP_GPIO, "MMC WP") < 0) { - printk(KERN_ERR "Could not reserve WP GPIO!\n"); - return; - } - gpio_direction_input(PALMZ71_MMC_WP_GPIO); - - /* Monitor the Power-cable-connected signal */ - if (gpio_request(PALMZ71_USBDETECT_GPIO, "USB detect") < 0) { - printk(KERN_ERR - "Could not reserve cable signal GPIO!\n"); - return; - } - gpio_direction_input(PALMZ71_USBDETECT_GPIO); - if (request_irq(gpio_to_irq(PALMZ71_USBDETECT_GPIO), - palmz71_powercable, 0, "palmz71-cable", NULL)) - printk(KERN_ERR - "IRQ request for power cable failed!\n"); - palmz71_powercable(gpio_to_irq(PALMZ71_USBDETECT_GPIO), NULL); - } -} - -static void __init -omap_palmz71_init(void) -{ - /* mux pins for uarts */ - omap_cfg_reg(UART1_TX); - omap_cfg_reg(UART1_RTS); - omap_cfg_reg(UART2_TX); - omap_cfg_reg(UART2_RTS); - omap_cfg_reg(UART3_TX); - omap_cfg_reg(UART3_RX); - - palmz71_gpio_setup(1); - omap_mpu_wdt_mode(0); - - platform_add_devices(devices, ARRAY_SIZE(devices)); - - palmz71_boardinfo[0].irq = gpio_to_irq(PALMZ71_PENIRQ_GPIO); - spi_register_board_info(palmz71_boardinfo, - ARRAY_SIZE(palmz71_boardinfo)); - omap1_usb_init(&palmz71_usb_config); - omap_serial_init(); - omap_register_i2c_bus(1, 100, NULL, 0); - palmz71_gpio_setup(0); - - omapfb_set_lcd_config(&palmz71_lcd_config); -} - -MACHINE_START(OMAP_PALMZ71, "OMAP310 based Palm Zire71") - .atag_offset = 0x100, - .map_io = omap15xx_map_io, - .init_early = omap1_init_early, - .init_irq = omap1_init_irq, - .handle_irq = omap1_handle_irq, - .init_machine = omap_palmz71_init, - .init_late = omap1_init_late, - .init_time = omap1_timer_init, - .restart = omap1_restart, -MACHINE_END diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c deleted file mode 100644 index b041e6f6e9cf..000000000000 --- a/arch/arm/mach-omap1/board-perseus2.c +++ /dev/null @@ -1,333 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-omap1/board-perseus2.c - * - * Modified from board-generic.c - * - * Original OMAP730 support by Jean Pihet - * Updated for 2.6 by Kevin Hilman - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "tc.h" -#include "mux.h" -#include "flash.h" -#include "hardware.h" -#include "iomap.h" -#include "common.h" -#include "fpga.h" - -static const unsigned int p2_keymap[] = { - KEY(0, 0, KEY_UP), - KEY(1, 0, KEY_RIGHT), - KEY(2, 0, KEY_LEFT), - KEY(3, 0, KEY_DOWN), - KEY(4, 0, KEY_ENTER), - KEY(0, 1, KEY_F10), - KEY(1, 1, KEY_SEND), - KEY(2, 1, KEY_END), - KEY(3, 1, KEY_VOLUMEDOWN), - KEY(4, 1, KEY_VOLUMEUP), - KEY(5, 1, KEY_RECORD), - KEY(0, 2, KEY_F9), - KEY(1, 2, KEY_3), - KEY(2, 2, KEY_6), - KEY(3, 2, KEY_9), - KEY(4, 2, KEY_KPDOT), - KEY(0, 3, KEY_BACK), - KEY(1, 3, KEY_2), - KEY(2, 3, KEY_5), - KEY(3, 3, KEY_8), - KEY(4, 3, KEY_0), - KEY(5, 3, KEY_KPSLASH), - KEY(0, 4, KEY_HOME), - KEY(1, 4, KEY_1), - KEY(2, 4, KEY_4), - KEY(3, 4, KEY_7), - KEY(4, 4, KEY_KPASTERISK), - KEY(5, 4, KEY_POWER), -}; - -static struct smc91x_platdata smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - -static struct resource smc91x_resources[] = { - [0] = { - .start = H2P2_DBG_FPGA_ETHR_START, /* Physical */ - .end = H2P2_DBG_FPGA_ETHR_START + 0xf, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = INT_7XX_MPU_EXT_NIRQ, - .end = 0, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, - }, -}; - -static struct mtd_partition nor_partitions[] = { - /* bootloader (U-Boot, etc) in first sector */ - { - .name = "bootloader", - .offset = 0, - .size = SZ_128K, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - /* bootloader params in the next sector */ - { - .name = "params", - .offset = MTDPART_OFS_APPEND, - .size = SZ_128K, - .mask_flags = 0, - }, - /* kernel */ - { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_2M, - .mask_flags = 0 - }, - /* rest of flash is a file system */ - { - .name = "rootfs", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0 - }, -}; - -static struct physmap_flash_data nor_data = { - .width = 2, - .set_vpp = omap1_set_vpp, - .parts = nor_partitions, - .nr_parts = ARRAY_SIZE(nor_partitions), -}; - -static struct resource nor_resource = { - .start = OMAP_CS0_PHYS, - .end = OMAP_CS0_PHYS + SZ_32M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device nor_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &nor_data, - }, - .num_resources = 1, - .resource = &nor_resource, -}; - -#define P2_NAND_RB_GPIO_PIN 62 - -static int nand_dev_ready(struct nand_chip *chip) -{ - return gpio_get_value(P2_NAND_RB_GPIO_PIN); -} - -static struct platform_nand_data nand_data = { - .chip = { - .nr_chips = 1, - .chip_offset = 0, - .options = NAND_SAMSUNG_LP_OPTIONS, - }, - .ctrl = { - .cmd_ctrl = omap1_nand_cmd_ctl, - .dev_ready = nand_dev_ready, - }, -}; - -static struct resource nand_resource = { - .start = OMAP_CS3_PHYS, - .end = OMAP_CS3_PHYS + SZ_4K - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device nand_device = { - .name = "gen_nand", - .id = 0, - .dev = { - .platform_data = &nand_data, - }, - .num_resources = 1, - .resource = &nand_resource, -}; - -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = 0, - .dev = { - .platform_data = &smc91x_info, - }, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, -}; - -static struct resource kp_resources[] = { - [0] = { - .start = INT_7XX_MPUIO_KEYPAD, - .end = INT_7XX_MPUIO_KEYPAD, - .flags = IORESOURCE_IRQ, - }, -}; - -static const struct matrix_keymap_data p2_keymap_data = { - .keymap = p2_keymap, - .keymap_size = ARRAY_SIZE(p2_keymap), -}; - -static struct omap_kp_platform_data kp_data = { - .rows = 8, - .cols = 8, - .keymap_data = &p2_keymap_data, - .delay = 4, - .dbounce = true, -}; - -static struct platform_device kp_device = { - .name = "omap-keypad", - .id = -1, - .dev = { - .platform_data = &kp_data, - }, - .num_resources = ARRAY_SIZE(kp_resources), - .resource = kp_resources, -}; - -static struct platform_device *devices[] __initdata = { - &nor_device, - &nand_device, - &smc91x_device, - &kp_device, -}; - -static const struct omap_lcd_config perseus2_lcd_config __initconst = { - .ctrl_name = "internal", -}; - -static void __init perseus2_init_smc91x(void) -{ - __raw_writeb(1, H2P2_DBG_FPGA_LAN_RESET); - mdelay(50); - __raw_writeb(__raw_readb(H2P2_DBG_FPGA_LAN_RESET) & ~1, - H2P2_DBG_FPGA_LAN_RESET); - mdelay(50); -} - -static void __init omap_perseus2_init(void) -{ - /* Early, board-dependent init */ - - /* - * Hold GSM Reset until needed - */ - omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL); - - /* - * UARTs -> done automagically by 8250 driver - */ - - /* - * CSx timings, GPIO Mux ... setup - */ - - /* Flash: CS0 timings setup */ - omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_0); - omap_writel(0x00000088, OMAP7XX_FLASH_ACFG_0); - - /* - * Ethernet support through the debug board - * CS1 timings setup - */ - omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_1); - omap_writel(0x00000000, OMAP7XX_FLASH_ACFG_1); - - /* - * Configure MPU_EXT_NIRQ IO in IO_CONF9 register, - * It is used as the Ethernet controller interrupt - */ - omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFFFFFF, - OMAP7XX_IO_CONF_9); - - perseus2_init_smc91x(); - - BUG_ON(gpio_request(P2_NAND_RB_GPIO_PIN, "NAND ready") < 0); - gpio_direction_input(P2_NAND_RB_GPIO_PIN); - - omap_cfg_reg(L3_1610_FLASH_CS2B_OE); - omap_cfg_reg(M8_1610_FLASH_CS2B_WE); - - /* Mux pins for keypad */ - omap_cfg_reg(E2_7XX_KBR0); - omap_cfg_reg(J7_7XX_KBR1); - omap_cfg_reg(E1_7XX_KBR2); - omap_cfg_reg(F3_7XX_KBR3); - omap_cfg_reg(D2_7XX_KBR4); - omap_cfg_reg(C2_7XX_KBC0); - omap_cfg_reg(D3_7XX_KBC1); - omap_cfg_reg(E4_7XX_KBC2); - omap_cfg_reg(F4_7XX_KBC3); - omap_cfg_reg(E3_7XX_KBC4); - - if (IS_ENABLED(CONFIG_SPI_OMAP_UWIRE)) { - /* configure pins: MPU_UW_nSCS1, MPU_UW_SDO, MPU_UW_SCLK */ - int val = omap_readl(OMAP7XX_IO_CONF_9) & ~0x00EEE000; - omap_writel(val | 0x00AAA000, OMAP7XX_IO_CONF_9); - } - - platform_add_devices(devices, ARRAY_SIZE(devices)); - - omap_serial_init(); - omap_register_i2c_bus(1, 100, NULL, 0); - - omapfb_set_lcd_config(&perseus2_lcd_config); -} - -/* Only FPGA needs to be mapped here. All others are done with ioremap */ -static struct map_desc omap_perseus2_io_desc[] __initdata = { - { - .virtual = H2P2_DBG_FPGA_BASE, - .pfn = __phys_to_pfn(H2P2_DBG_FPGA_START), - .length = H2P2_DBG_FPGA_SIZE, - .type = MT_DEVICE - } -}; - -static void __init omap_perseus2_map_io(void) -{ - omap7xx_map_io(); - iotable_init(omap_perseus2_io_desc, - ARRAY_SIZE(omap_perseus2_io_desc)); -} - -MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2") - /* Maintainer: Kevin Hilman */ - .atag_offset = 0x100, - .map_io = omap_perseus2_map_io, - .init_early = omap1_init_early, - .init_irq = omap1_init_irq, - .handle_irq = omap1_handle_irq, - .init_machine = omap_perseus2_init, - .init_late = omap1_init_late, - .init_time = omap1_timer_init, - .restart = omap1_restart, -MACHINE_END diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c deleted file mode 100644 index 4c71a195969f..000000000000 --- a/arch/arm/mach-omap1/fpga.c +++ /dev/null @@ -1,186 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-omap1/fpga.c - * - * Interrupt handler for OMAP-1510 Innovator FPGA - * - * Copyright (C) 2001 RidgeRun, Inc. - * Author: Greg Lonnon - * - * Copyright (C) 2002 MontaVista Software, Inc. - * - * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6 - * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "hardware.h" -#include "iomap.h" -#include "common.h" -#include "fpga.h" - -static void fpga_mask_irq(struct irq_data *d) -{ - unsigned int irq = d->irq - OMAP_FPGA_IRQ_BASE; - - if (irq < 8) - __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO) - & ~(1 << irq)), OMAP1510_FPGA_IMR_LO); - else if (irq < 16) - __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_HI) - & ~(1 << (irq - 8))), OMAP1510_FPGA_IMR_HI); - else - __raw_writeb((__raw_readb(INNOVATOR_FPGA_IMR2) - & ~(1 << (irq - 16))), INNOVATOR_FPGA_IMR2); -} - - -static inline u32 get_fpga_unmasked_irqs(void) -{ - return - ((__raw_readb(OMAP1510_FPGA_ISR_LO) & - __raw_readb(OMAP1510_FPGA_IMR_LO))) | - ((__raw_readb(OMAP1510_FPGA_ISR_HI) & - __raw_readb(OMAP1510_FPGA_IMR_HI)) << 8) | - ((__raw_readb(INNOVATOR_FPGA_ISR2) & - __raw_readb(INNOVATOR_FPGA_IMR2)) << 16); -} - - -static void fpga_ack_irq(struct irq_data *d) -{ - /* Don't need to explicitly ACK FPGA interrupts */ -} - -static void fpga_unmask_irq(struct irq_data *d) -{ - unsigned int irq = d->irq - OMAP_FPGA_IRQ_BASE; - - if (irq < 8) - __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO) | (1 << irq)), - OMAP1510_FPGA_IMR_LO); - else if (irq < 16) - __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_HI) - | (1 << (irq - 8))), OMAP1510_FPGA_IMR_HI); - else - __raw_writeb((__raw_readb(INNOVATOR_FPGA_IMR2) - | (1 << (irq - 16))), INNOVATOR_FPGA_IMR2); -} - -static void fpga_mask_ack_irq(struct irq_data *d) -{ - fpga_mask_irq(d); - fpga_ack_irq(d); -} - -static void innovator_fpga_IRQ_demux(struct irq_desc *desc) -{ - u32 stat; - int fpga_irq; - - stat = get_fpga_unmasked_irqs(); - - if (!stat) - return; - - for (fpga_irq = OMAP_FPGA_IRQ_BASE; - (fpga_irq < OMAP_FPGA_IRQ_END) && stat; - fpga_irq++, stat >>= 1) { - if (stat & 1) { - generic_handle_irq(fpga_irq); - } - } -} - -static struct irq_chip omap_fpga_irq_ack = { - .name = "FPGA-ack", - .irq_ack = fpga_mask_ack_irq, - .irq_mask = fpga_mask_irq, - .irq_unmask = fpga_unmask_irq, -}; - - -static struct irq_chip omap_fpga_irq = { - .name = "FPGA", - .irq_ack = fpga_ack_irq, - .irq_mask = fpga_mask_irq, - .irq_unmask = fpga_unmask_irq, -}; - -/* - * All of the FPGA interrupt request inputs except for the touchscreen are - * edge-sensitive; the touchscreen is level-sensitive. The edge-sensitive - * interrupts are acknowledged as a side-effect of reading the interrupt - * status register from the FPGA. The edge-sensitive interrupt inputs - * cause a problem with level interrupt requests, such as Ethernet. The - * problem occurs when a level interrupt request is asserted while its - * interrupt input is masked in the FPGA, which results in a missed - * interrupt. - * - * In an attempt to workaround the problem with missed interrupts, the - * mask_ack routine for all of the FPGA interrupts has been changed from - * fpga_mask_ack_irq() to fpga_ack_irq() so that the specific FPGA interrupt - * being serviced is left unmasked. We can do this because the FPGA cascade - * interrupt is run with all interrupts masked. - * - * Limited testing indicates that this workaround appears to be effective - * for the smc9194 Ethernet driver used on the Innovator. It should work - * on other FPGA interrupts as well, but any drivers that explicitly mask - * interrupts at the interrupt controller via disable_irq/enable_irq - * could pose a problem. - */ -void omap1510_fpga_init_irq(void) -{ - int i, res; - - __raw_writeb(0, OMAP1510_FPGA_IMR_LO); - __raw_writeb(0, OMAP1510_FPGA_IMR_HI); - __raw_writeb(0, INNOVATOR_FPGA_IMR2); - - for (i = OMAP_FPGA_IRQ_BASE; i < OMAP_FPGA_IRQ_END; i++) { - - if (i == OMAP1510_INT_FPGA_TS) { - /* - * The touchscreen interrupt is level-sensitive, so - * we'll use the regular mask_ack routine for it. - */ - irq_set_chip(i, &omap_fpga_irq_ack); - } - else { - /* - * All FPGA interrupts except the touchscreen are - * edge-sensitive, so we won't mask them. - */ - irq_set_chip(i, &omap_fpga_irq); - } - - irq_set_handler(i, handle_edge_irq); - irq_clear_status_flags(i, IRQ_NOREQUEST); - } - - /* - * The FPGA interrupt line is connected to GPIO13. Claim this pin for - * the ARM. - * - * NOTE: For general GPIO/MPUIO access and interrupts, please see - * gpio.[ch] - */ - res = gpio_request(13, "FPGA irq"); - if (res) { - pr_err("%s failed to get gpio\n", __func__); - return; - } - gpio_direction_input(13); - irq_set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); - irq_set_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux); -} diff --git a/arch/arm/mach-omap1/fpga.h b/arch/arm/mach-omap1/fpga.h deleted file mode 100644 index 7e7450edacc1..000000000000 --- a/arch/arm/mach-omap1/fpga.h +++ /dev/null @@ -1,49 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Interrupt handler for OMAP-1510 FPGA - * - * Copyright (C) 2001 RidgeRun, Inc. - * Author: Greg Lonnon - * - * Copyright (C) 2002 MontaVista Software, Inc. - * - * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6 - * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen - */ - -#ifndef __ASM_ARCH_OMAP_FPGA_H -#define __ASM_ARCH_OMAP_FPGA_H - -/* - * --------------------------------------------------------------------------- - * H2/P2 Debug board FPGA - * --------------------------------------------------------------------------- - */ -/* maps in the FPGA registers and the ETHR registers */ -#define H2P2_DBG_FPGA_BASE 0xE8000000 /* VA */ -#define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */ -#define H2P2_DBG_FPGA_START 0x04000000 /* PA */ - -#define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300) -#define H2P2_DBG_FPGA_FPGA_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */ -#define H2P2_DBG_FPGA_BOARD_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */ -#define H2P2_DBG_FPGA_GPIO IOMEM(H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */ -#define H2P2_DBG_FPGA_LEDS IOMEM(H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */ -#define H2P2_DBG_FPGA_MISC_INPUTS IOMEM(H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */ -#define H2P2_DBG_FPGA_LAN_STATUS IOMEM(H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */ -#define H2P2_DBG_FPGA_LAN_RESET IOMEM(H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */ - -/* LEDs definition on debug board (16 LEDs, all physically green) */ -#define H2P2_DBG_FPGA_LED_GREEN (1 << 15) -#define H2P2_DBG_FPGA_LED_AMBER (1 << 14) -#define H2P2_DBG_FPGA_LED_RED (1 << 13) -#define H2P2_DBG_FPGA_LED_BLUE (1 << 12) -/* cpu0 load-meter LEDs */ -#define H2P2_DBG_FPGA_LOAD_METER (1 << 0) // A bit of fun on our board ... -#define H2P2_DBG_FPGA_LOAD_METER_SIZE 11 -#define H2P2_DBG_FPGA_LOAD_METER_MASK ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1) - -#define H2P2_DBG_FPGA_P2_LED_TIMER (1 << 0) -#define H2P2_DBG_FPGA_P2_LED_IDLE (1 << 1) - -#endif diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c deleted file mode 100644 index c372b357eab4..000000000000 --- a/arch/arm/mach-omap1/gpio7xx.c +++ /dev/null @@ -1,272 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * OMAP7xx specific gpio init - * - * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/ - * - * Author: - * Charulatha V - */ - -#include -#include - -#include "irqs.h" -#include "soc.h" - -#define OMAP7XX_GPIO1_BASE 0xfffbc000 -#define OMAP7XX_GPIO2_BASE 0xfffbc800 -#define OMAP7XX_GPIO3_BASE 0xfffbd000 -#define OMAP7XX_GPIO4_BASE 0xfffbd800 -#define OMAP7XX_GPIO5_BASE 0xfffbe000 -#define OMAP7XX_GPIO6_BASE 0xfffbe800 -#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE - -/* mpu gpio */ -static struct resource omap7xx_mpu_gpio_resources[] = { - { - .start = OMAP1_MPUIO_VBASE, - .end = OMAP1_MPUIO_VBASE + SZ_2K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = INT_7XX_MPUIO, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct omap_gpio_reg_offs omap7xx_mpuio_regs = { - .revision = USHRT_MAX, - .direction = OMAP_MPUIO_IO_CNTL / 2, - .datain = OMAP_MPUIO_INPUT_LATCH / 2, - .dataout = OMAP_MPUIO_OUTPUT / 2, - .irqstatus = OMAP_MPUIO_GPIO_INT / 2, - .irqenable = OMAP_MPUIO_GPIO_MASKIT / 2, - .irqenable_inv = true, - .irqctrl = OMAP_MPUIO_GPIO_INT_EDGE >> 1, -}; - -static struct omap_gpio_platform_data omap7xx_mpu_gpio_config = { - .is_mpuio = true, - .bank_width = 16, - .bank_stride = 2, - .regs = &omap7xx_mpuio_regs, -}; - -static struct platform_device omap7xx_mpu_gpio = { - .name = "omap_gpio", - .id = 0, - .dev = { - .platform_data = &omap7xx_mpu_gpio_config, - }, - .num_resources = ARRAY_SIZE(omap7xx_mpu_gpio_resources), - .resource = omap7xx_mpu_gpio_resources, -}; - -/* gpio1 */ -static struct resource omap7xx_gpio1_resources[] = { - { - .start = OMAP7XX_GPIO1_BASE, - .end = OMAP7XX_GPIO1_BASE + SZ_2K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = INT_7XX_GPIO_BANK1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct omap_gpio_reg_offs omap7xx_gpio_regs = { - .revision = USHRT_MAX, - .direction = OMAP7XX_GPIO_DIR_CONTROL, - .datain = OMAP7XX_GPIO_DATA_INPUT, - .dataout = OMAP7XX_GPIO_DATA_OUTPUT, - .irqstatus = OMAP7XX_GPIO_INT_STATUS, - .irqenable = OMAP7XX_GPIO_INT_MASK, - .irqenable_inv = true, - .irqctrl = OMAP7XX_GPIO_INT_CONTROL, -}; - -static struct omap_gpio_platform_data omap7xx_gpio1_config = { - .bank_width = 32, - .regs = &omap7xx_gpio_regs, -}; - -static struct platform_device omap7xx_gpio1 = { - .name = "omap_gpio", - .id = 1, - .dev = { - .platform_data = &omap7xx_gpio1_config, - }, - .num_resources = ARRAY_SIZE(omap7xx_gpio1_resources), - .resource = omap7xx_gpio1_resources, -}; - -/* gpio2 */ -static struct resource omap7xx_gpio2_resources[] = { - { - .start = OMAP7XX_GPIO2_BASE, - .end = OMAP7XX_GPIO2_BASE + SZ_2K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = INT_7XX_GPIO_BANK2, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct omap_gpio_platform_data omap7xx_gpio2_config = { - .bank_width = 32, - .regs = &omap7xx_gpio_regs, -}; - -static struct platform_device omap7xx_gpio2 = { - .name = "omap_gpio", - .id = 2, - .dev = { - .platform_data = &omap7xx_gpio2_config, - }, - .num_resources = ARRAY_SIZE(omap7xx_gpio2_resources), - .resource = omap7xx_gpio2_resources, -}; - -/* gpio3 */ -static struct resource omap7xx_gpio3_resources[] = { - { - .start = OMAP7XX_GPIO3_BASE, - .end = OMAP7XX_GPIO3_BASE + SZ_2K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = INT_7XX_GPIO_BANK3, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct omap_gpio_platform_data omap7xx_gpio3_config = { - .bank_width = 32, - .regs = &omap7xx_gpio_regs, -}; - -static struct platform_device omap7xx_gpio3 = { - .name = "omap_gpio", - .id = 3, - .dev = { - .platform_data = &omap7xx_gpio3_config, - }, - .num_resources = ARRAY_SIZE(omap7xx_gpio3_resources), - .resource = omap7xx_gpio3_resources, -}; - -/* gpio4 */ -static struct resource omap7xx_gpio4_resources[] = { - { - .start = OMAP7XX_GPIO4_BASE, - .end = OMAP7XX_GPIO4_BASE + SZ_2K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = INT_7XX_GPIO_BANK4, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct omap_gpio_platform_data omap7xx_gpio4_config = { - .bank_width = 32, - .regs = &omap7xx_gpio_regs, -}; - -static struct platform_device omap7xx_gpio4 = { - .name = "omap_gpio", - .id = 4, - .dev = { - .platform_data = &omap7xx_gpio4_config, - }, - .num_resources = ARRAY_SIZE(omap7xx_gpio4_resources), - .resource = omap7xx_gpio4_resources, -}; - -/* gpio5 */ -static struct resource omap7xx_gpio5_resources[] = { - { - .start = OMAP7XX_GPIO5_BASE, - .end = OMAP7XX_GPIO5_BASE + SZ_2K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = INT_7XX_GPIO_BANK5, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct omap_gpio_platform_data omap7xx_gpio5_config = { - .bank_width = 32, - .regs = &omap7xx_gpio_regs, -}; - -static struct platform_device omap7xx_gpio5 = { - .name = "omap_gpio", - .id = 5, - .dev = { - .platform_data = &omap7xx_gpio5_config, - }, - .num_resources = ARRAY_SIZE(omap7xx_gpio5_resources), - .resource = omap7xx_gpio5_resources, -}; - -/* gpio6 */ -static struct resource omap7xx_gpio6_resources[] = { - { - .start = OMAP7XX_GPIO6_BASE, - .end = OMAP7XX_GPIO6_BASE + SZ_2K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = INT_7XX_GPIO_BANK6, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct omap_gpio_platform_data omap7xx_gpio6_config = { - .bank_width = 32, - .regs = &omap7xx_gpio_regs, -}; - -static struct platform_device omap7xx_gpio6 = { - .name = "omap_gpio", - .id = 6, - .dev = { - .platform_data = &omap7xx_gpio6_config, - }, - .num_resources = ARRAY_SIZE(omap7xx_gpio6_resources), - .resource = omap7xx_gpio6_resources, -}; - -static struct platform_device *omap7xx_gpio_dev[] __initdata = { - &omap7xx_mpu_gpio, - &omap7xx_gpio1, - &omap7xx_gpio2, - &omap7xx_gpio3, - &omap7xx_gpio4, - &omap7xx_gpio5, - &omap7xx_gpio6, -}; - -/* - * omap7xx_gpio_init needs to be done before - * machine_init functions access gpio APIs. - * Hence omap7xx_gpio_init is a postcore_initcall. - */ -static int __init omap7xx_gpio_init(void) -{ - int i; - - if (!cpu_is_omap7xx()) - return -EINVAL; - - for (i = 0; i < ARRAY_SIZE(omap7xx_gpio_dev); i++) - platform_device_register(omap7xx_gpio_dev[i]); - - return 0; -} -postcore_initcall(omap7xx_gpio_init); -- cgit From 21a3e6eed42367faed4a54332bba1545c67d0fc1 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 23 Nov 2022 22:21:20 +0100 Subject: ARM: omap1: remove osk-mistral add-on board support As Aaro Koskinen points out, nobody should have this one any more, and I noticed the code is rather ugly, so let's removed it but keep the rest of the OSK support that is still used. Link: https://lore.kernel.org/linux-arm-kernel/20221020193511.GB3019@t60.musicnaut.iki.fi/ Signed-off-by: Arnd Bergmann --- arch/arm/mach-omap1/Kconfig | 8 -- arch/arm/mach-omap1/board-osk.c | 267 ---------------------------------------- 2 files changed, 275 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig index 03b0ba2e8653..8df9a4de0e79 100644 --- a/arch/arm/mach-omap1/Kconfig +++ b/arch/arm/mach-omap1/Kconfig @@ -120,14 +120,6 @@ config MACH_OMAP_OSK TI OMAP 5912 OSK (OMAP Starter Kit) board support. Say Y here if you have such a board. -config OMAP_OSK_MISTRAL - bool "Mistral QVGA board Support" - depends on MACH_OMAP_OSK - help - The OSK supports an optional add-on board with a Quarter-VGA - touchscreen, PDA-ish buttons, a resume button, bicolor LED, - and camera connector. Say Y here if you have this board. - config MACH_OMAP_PALMTE bool "Palm Tungsten E" depends on ARCH_OMAP15XX diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index 76684b7a4e87..7049e608b25a 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c @@ -339,267 +339,6 @@ static struct omap_usb_config osk_usb_config __initdata = { .pins[0] = 2, }; -#ifdef CONFIG_OMAP_OSK_MISTRAL -static const struct omap_lcd_config osk_lcd_config __initconst = { - .ctrl_name = "internal", -}; -#endif - -#ifdef CONFIG_OMAP_OSK_MISTRAL - -#include -#include -#include -#include - -#include - -static const struct property_entry mistral_at24_properties[] = { - PROPERTY_ENTRY_U32("pagesize", 16), - { } -}; - -static const struct software_node mistral_at24_node = { - .properties = mistral_at24_properties, -}; - -static struct i2c_board_info __initdata mistral_i2c_board_info[] = { - { - /* NOTE: powered from LCD supply */ - I2C_BOARD_INFO("24c04", 0x50), - .swnode = &mistral_at24_node, - }, - /* TODO when driver support is ready: - * - optionally ov9640 camera sensor at 0x30 - */ -}; - -static const unsigned int osk_keymap[] = { - /* KEY(col, row, code) */ - KEY(0, 0, KEY_F1), /* SW4 */ - KEY(3, 0, KEY_UP), /* (sw2/up) */ - KEY(1, 1, KEY_LEFTCTRL), /* SW5 */ - KEY(2, 1, KEY_LEFT), /* (sw2/left) */ - KEY(0, 2, KEY_SPACE), /* SW3 */ - KEY(1, 2, KEY_ESC), /* SW6 */ - KEY(2, 2, KEY_DOWN), /* (sw2/down) */ - KEY(2, 3, KEY_ENTER), /* (sw2/select) */ - KEY(3, 3, KEY_RIGHT), /* (sw2/right) */ -}; - -static const struct matrix_keymap_data osk_keymap_data = { - .keymap = osk_keymap, - .keymap_size = ARRAY_SIZE(osk_keymap), -}; - -static struct omap_kp_platform_data osk_kp_data = { - .rows = 8, - .cols = 8, - .keymap_data = &osk_keymap_data, - .delay = 9, -}; - -static struct resource osk5912_kp_resources[] = { - [0] = { - .start = INT_KEYBOARD, - .end = INT_KEYBOARD, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device osk5912_kp_device = { - .name = "omap-keypad", - .id = -1, - .dev = { - .platform_data = &osk_kp_data, - }, - .num_resources = ARRAY_SIZE(osk5912_kp_resources), - .resource = osk5912_kp_resources, -}; - -static struct omap_backlight_config mistral_bl_data = { - .default_intensity = 0xa0, -}; - -static struct platform_device mistral_bl_device = { - .name = "omap-bl", - .id = -1, - .dev = { - .platform_data = &mistral_bl_data, - }, -}; - -static struct platform_device osk5912_lcd_device = { - .name = "lcd_osk", - .id = -1, -}; - -static const struct gpio_led mistral_gpio_led_pins[] = { - { - .name = "mistral:red", - .default_trigger = "heartbeat", - .gpio = 3, - }, - { - .name = "mistral:green", - .default_trigger = "cpu0", - .gpio = OMAP_MPUIO(4), - }, -}; - -static struct gpio_led_platform_data mistral_gpio_led_data = { - .leds = mistral_gpio_led_pins, - .num_leds = ARRAY_SIZE(mistral_gpio_led_pins), -}; - -static struct platform_device mistral_gpio_leds = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &mistral_gpio_led_data, - }, -}; - -static struct platform_device *mistral_devices[] __initdata = { - &osk5912_kp_device, - &mistral_bl_device, - &osk5912_lcd_device, - &mistral_gpio_leds, -}; - -static int mistral_get_pendown_state(void) -{ - return !gpio_get_value(4); -} - -static const struct ads7846_platform_data mistral_ts_info = { - .model = 7846, - .vref_delay_usecs = 100, /* internal, no capacitor */ - .x_plate_ohms = 419, - .y_plate_ohms = 486, - .get_pendown_state = mistral_get_pendown_state, -}; - -static struct spi_board_info __initdata mistral_boardinfo[] = { { - /* MicroWire (bus 2) CS0 has an ads7846e */ - .modalias = "ads7846", - .platform_data = &mistral_ts_info, - .max_speed_hz = 120000 /* max sample rate at 3V */ - * 26 /* command + data + overhead */, - .bus_num = 2, - .chip_select = 0, -} }; - -static irqreturn_t -osk_mistral_wake_interrupt(int irq, void *ignored) -{ - return IRQ_HANDLED; -} - -static void __init osk_mistral_init(void) -{ - /* NOTE: we could actually tell if there's a Mistral board - * attached, e.g. by trying to read something from the ads7846. - * But this arch_init() code is too early for that, since we - * can't talk to the ads or even the i2c eeprom. - */ - - /* parallel camera interface */ - omap_cfg_reg(J15_1610_CAM_LCLK); - omap_cfg_reg(J18_1610_CAM_D7); - omap_cfg_reg(J19_1610_CAM_D6); - omap_cfg_reg(J14_1610_CAM_D5); - omap_cfg_reg(K18_1610_CAM_D4); - omap_cfg_reg(K19_1610_CAM_D3); - omap_cfg_reg(K15_1610_CAM_D2); - omap_cfg_reg(K14_1610_CAM_D1); - omap_cfg_reg(L19_1610_CAM_D0); - omap_cfg_reg(L18_1610_CAM_VS); - omap_cfg_reg(L15_1610_CAM_HS); - omap_cfg_reg(M19_1610_CAM_RSTZ); - omap_cfg_reg(Y15_1610_CAM_OUTCLK); - - /* serial camera interface */ - omap_cfg_reg(H19_1610_CAM_EXCLK); - omap_cfg_reg(W13_1610_CCP_CLKM); - omap_cfg_reg(Y12_1610_CCP_CLKP); - /* CCP_DATAM CONFLICTS WITH UART1.TX (and serial console) */ - /* omap_cfg_reg(Y14_1610_CCP_DATAM); */ - omap_cfg_reg(W14_1610_CCP_DATAP); - - /* CAM_PWDN */ - if (gpio_request(11, "cam_pwdn") == 0) { - omap_cfg_reg(N20_1610_GPIO11); - gpio_direction_output(11, 0); - } else - pr_debug("OSK+Mistral: CAM_PWDN is awol\n"); - - - /* omap_cfg_reg(P19_1610_GPIO6); */ /* BUSY */ - gpio_request(6, "ts_busy"); - gpio_direction_input(6); - - omap_cfg_reg(P20_1610_GPIO4); /* PENIRQ */ - gpio_request(4, "ts_int"); - gpio_direction_input(4); - irq_set_irq_type(gpio_to_irq(4), IRQ_TYPE_EDGE_FALLING); - - mistral_boardinfo[0].irq = gpio_to_irq(4); - spi_register_board_info(mistral_boardinfo, - ARRAY_SIZE(mistral_boardinfo)); - - /* the sideways button (SW1) is for use as a "wakeup" button - * - * NOTE: The Mistral board has the wakeup button (SW1) wired - * to the LCD 3.3V rail, which is powered down during suspend. - * To allow this button to wake up the omap, work around this - * HW bug by rewiring SW1 to use the main 3.3V rail. - */ - omap_cfg_reg(N15_1610_MPUIO2); - if (gpio_request(OMAP_MPUIO(2), "wakeup") == 0) { - int ret = 0; - int irq = gpio_to_irq(OMAP_MPUIO(2)); - - gpio_direction_input(OMAP_MPUIO(2)); - irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING); - /* share the IRQ in case someone wants to use the - * button for more than wakeup from system sleep. - */ - ret = request_irq(irq, - &osk_mistral_wake_interrupt, - IRQF_SHARED, "mistral_wakeup", - &osk_mistral_wake_interrupt); - if (ret != 0) { - gpio_free(OMAP_MPUIO(2)); - printk(KERN_ERR "OSK+Mistral: no wakeup irq, %d?\n", - ret); - } else - enable_irq_wake(irq); - } else - printk(KERN_ERR "OSK+Mistral: wakeup button is awol\n"); - - /* LCD: backlight, and power; power controls other devices on the - * board, like the touchscreen, EEPROM, and wakeup (!) switch. - */ - omap_cfg_reg(PWL); - if (gpio_request(2, "lcd_pwr") == 0) - gpio_direction_output(2, 1); - - /* - * GPIO based LEDs - */ - omap_cfg_reg(P18_1610_GPIO3); - omap_cfg_reg(MPUIO4); - - i2c_register_board_info(1, mistral_i2c_board_info, - ARRAY_SIZE(mistral_i2c_board_info)); - - platform_add_devices(mistral_devices, ARRAY_SIZE(mistral_devices)); -} -#else -static void __init osk_mistral_init(void) { } -#endif - #define EMIFS_CS3_VAL (0x88013141) static void __init osk_init(void) @@ -642,12 +381,6 @@ static void __init osk_init(void) osk_i2c_board_info[0].irq = gpio_to_irq(OMAP_MPUIO(1)); omap_register_i2c_bus(1, 400, osk_i2c_board_info, ARRAY_SIZE(osk_i2c_board_info)); - osk_mistral_init(); - -#ifdef CONFIG_OMAP_OSK_MISTRAL - omapfb_set_lcd_config(&osk_lcd_config); -#endif - } MACHINE_START(OMAP_OSK, "TI-OSK") -- cgit From 8825acd7cc8a13af7ae6c2c5e5025af38df6c2e4 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 29 Sep 2022 16:19:44 +0200 Subject: ARM: omap1: remove dead code After the removal of the unused board files, I went through the omap1 code to look for code that no longer has any callers and remove that. In particular, support for the omap7xx/omap8xx family is now completely unused, so I'm only leaving omap15xx/omap16xx/omap59xx. Cc: Aaro Koskinen Cc: Janusz Krzysztofik Cc: linux-omap@vger.kernel.org Reviewed-by: Greg Kroah-Hartman Acked-by: Tony Lindgren Acked-by: Kevin Hilman Signed-off-by: Arnd Bergmann --- arch/arm/mach-omap1/clock_data.c | 17 +-------- arch/arm/mach-omap1/common.h | 8 ---- arch/arm/mach-omap1/devices.c | 58 ++--------------------------- arch/arm/mach-omap1/dma.c | 25 +------------ arch/arm/mach-omap1/i2c.c | 14 ++----- arch/arm/mach-omap1/io.c | 28 -------------- arch/arm/mach-omap1/irq.c | 20 +--------- arch/arm/mach-omap1/irqs.h | 9 ----- arch/arm/mach-omap1/mcbsp.c | 76 -------------------------------------- arch/arm/mach-omap1/mtd-xip.h | 4 -- arch/arm/mach-omap1/mux.c | 52 -------------------------- arch/arm/mach-omap1/pm.c | 76 ++++++-------------------------------- arch/arm/mach-omap1/pm.h | 35 ------------------ arch/arm/mach-omap1/serial.c | 15 -------- arch/arm/mach-omap1/sleep.S | 80 ---------------------------------------- arch/arm/mach-omap1/sram-init.c | 7 +--- arch/arm/mach-omap1/usb.c | 34 ++++------------- 17 files changed, 30 insertions(+), 528 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c index 96d846c37c43..c58d200e4816 100644 --- a/arch/arm/mach-omap1/clock_data.c +++ b/arch/arm/mach-omap1/clock_data.c @@ -720,8 +720,6 @@ int __init omap1_clk_init(void) cpu_mask |= CK_16XX; if (cpu_is_omap1510()) cpu_mask |= CK_1510; - if (cpu_is_omap7xx()) - cpu_mask |= CK_7XX; if (cpu_is_omap310()) cpu_mask |= CK_310; @@ -730,9 +728,6 @@ int __init omap1_clk_init(void) ck_dpll1_p = &ck_dpll1; ck_ref_p = &ck_ref; - if (cpu_is_omap7xx()) - ck_ref.rate = 13000000; - pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), omap_readw(ARM_CKCTL)); @@ -771,12 +766,6 @@ int __init omap1_clk_init(void) } } - if (machine_is_omap_perseus2() || machine_is_omap_fsample()) { - /* Select slicer output as OMAP input clock */ - omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, - OMAP7XX_PCC_UPLD_CTRL); - } - /* Amstrad Delta wants BCLK high when inactive */ if (machine_is_ams_delta()) omap_writel(omap_readl(ULPD_CLOCK_CTRL) | @@ -784,11 +773,7 @@ int __init omap1_clk_init(void) ULPD_CLOCK_CTRL); /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */ - /* (on 730, bit 13 must not be cleared) */ - if (cpu_is_omap7xx()) - omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL); - else - omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); + omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); /* Put DSP/MPUI into reset until needed */ omap_writew(0, ARM_RSTCT1); diff --git a/arch/arm/mach-omap1/common.h b/arch/arm/mach-omap1/common.h index 5ceff05e15c0..3fd9ed9efb12 100644 --- a/arch/arm/mach-omap1/common.h +++ b/arch/arm/mach-omap1/common.h @@ -35,14 +35,6 @@ #include "soc.h" #include "i2c.h" -#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) -void omap7xx_map_io(void); -#else -static inline void omap7xx_map_io(void) -{ -} -#endif - #ifdef CONFIG_ARCH_OMAP15XX void omap1510_fpga_init_irq(void); void omap15xx_map_io(void); diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c index 80e94770582a..42d1631cecc0 100644 --- a/arch/arm/mach-omap1/devices.c +++ b/arch/arm/mach-omap1/devices.c @@ -63,8 +63,6 @@ static void omap_init_rtc(void) static inline void omap_init_rtc(void) {} #endif -static inline void omap_init_mbox(void) { } - /*-------------------------------------------------------------------------*/ #if IS_ENABLED(CONFIG_MMC_OMAP) @@ -73,22 +71,16 @@ static inline void omap1_mmc_mux(struct omap_mmc_platform_data *mmc_controller, int controller_nr) { if (controller_nr == 0) { - if (cpu_is_omap7xx()) { - omap_cfg_reg(MMC_7XX_CMD); - omap_cfg_reg(MMC_7XX_CLK); - omap_cfg_reg(MMC_7XX_DAT0); - } else { - omap_cfg_reg(MMC_CMD); - omap_cfg_reg(MMC_CLK); - omap_cfg_reg(MMC_DAT0); - } + omap_cfg_reg(MMC_CMD); + omap_cfg_reg(MMC_CLK); + omap_cfg_reg(MMC_DAT0); if (cpu_is_omap1710()) { omap_cfg_reg(M15_1710_MMC_CLKI); omap_cfg_reg(P19_1710_MMC_CMDDIR); omap_cfg_reg(P20_1710_MMC_DATDIR0); } - if (mmc_controller->slots[0].wires == 4 && !cpu_is_omap7xx()) { + if (mmc_controller->slots[0].wires == 4) { omap_cfg_reg(MMC_DAT1); /* NOTE: DAT2 can be on W10 (here) or M15 */ if (!mmc_controller->slots[0].nomux) @@ -154,8 +146,6 @@ static int __init omap_mmc_add(const char *name, int id, unsigned long base, res[3].name = "tx"; res[3].flags = IORESOURCE_DMA; - if (cpu_is_omap7xx()) - data->slots[0].features = MMC_OMAP7XX; if (cpu_is_omap15xx()) data->slots[0].features = MMC_OMAP15XX; if (cpu_is_omap16xx()) @@ -224,43 +214,6 @@ void __init omap1_init_mmc(struct omap_mmc_platform_data **mmc_data, /*-------------------------------------------------------------------------*/ -/* OMAP7xx SPI support */ -#if IS_ENABLED(CONFIG_SPI_OMAP_100K) - -struct platform_device omap_spi1 = { - .name = "omap1_spi100k", - .id = 1, -}; - -struct platform_device omap_spi2 = { - .name = "omap1_spi100k", - .id = 2, -}; - -static void omap_init_spi100k(void) -{ - if (!cpu_is_omap7xx()) - return; - - omap_spi1.dev.platform_data = ioremap(OMAP7XX_SPI1_BASE, 0x7ff); - if (omap_spi1.dev.platform_data) - platform_device_register(&omap_spi1); - - omap_spi2.dev.platform_data = ioremap(OMAP7XX_SPI2_BASE, 0x7ff); - if (omap_spi2.dev.platform_data) - platform_device_register(&omap_spi2); -} - -#else -static inline void omap_init_spi100k(void) -{ -} -#endif - -/*-------------------------------------------------------------------------*/ - -static inline void omap_init_sti(void) {} - /* Numbering for the SPI-capable controllers when used for SPI: * spi = 1 * uwire = 2 @@ -363,10 +316,7 @@ static int __init omap1_init_devices(void) * in alphabetical order so they're easier to sort through. */ - omap_init_mbox(); omap_init_rtc(); - omap_init_spi100k(); - omap_init_sti(); omap_init_uwire(); omap1_init_rng(); diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c index c3f280c3c5d7..756966cb715f 100644 --- a/arch/arm/mach-omap1/dma.c +++ b/arch/arm/mach-omap1/dma.c @@ -261,22 +261,6 @@ static const struct platform_device_info omap_dma_dev_info = { .num_res = 1, }; -/* OMAP730, OMAP850 */ -static const struct dma_slave_map omap7xx_sdma_map[] = { - { "omap-mcbsp.1", "tx", SDMA_FILTER_PARAM(8) }, - { "omap-mcbsp.1", "rx", SDMA_FILTER_PARAM(9) }, - { "omap-mcbsp.2", "tx", SDMA_FILTER_PARAM(10) }, - { "omap-mcbsp.2", "rx", SDMA_FILTER_PARAM(11) }, - { "mmci-omap.0", "tx", SDMA_FILTER_PARAM(21) }, - { "mmci-omap.0", "rx", SDMA_FILTER_PARAM(22) }, - { "omap_udc", "rx0", SDMA_FILTER_PARAM(26) }, - { "omap_udc", "rx1", SDMA_FILTER_PARAM(27) }, - { "omap_udc", "rx2", SDMA_FILTER_PARAM(28) }, - { "omap_udc", "tx0", SDMA_FILTER_PARAM(29) }, - { "omap_udc", "tx1", SDMA_FILTER_PARAM(30) }, - { "omap_udc", "tx2", SDMA_FILTER_PARAM(31) }, -}; - /* OMAP1510, OMAP1610*/ static const struct dma_slave_map omap1xxx_sdma_map[] = { { "omap-mcbsp.1", "tx", SDMA_FILTER_PARAM(8) }, @@ -371,13 +355,8 @@ static int __init omap1_system_dma_init(void) p.dma_attr = d; p.errata = configure_dma_errata(); - if (cpu_is_omap7xx()) { - p.slave_map = omap7xx_sdma_map; - p.slavecnt = ARRAY_SIZE(omap7xx_sdma_map); - } else { - p.slave_map = omap1xxx_sdma_map; - p.slavecnt = ARRAY_SIZE(omap1xxx_sdma_map); - } + p.slave_map = omap1xxx_sdma_map; + p.slavecnt = ARRAY_SIZE(omap1xxx_sdma_map); ret = platform_device_add_data(pdev, &p, sizeof(p)); if (ret) { diff --git a/arch/arm/mach-omap1/i2c.c b/arch/arm/mach-omap1/i2c.c index 22f945360599..94d3e7883e02 100644 --- a/arch/arm/mach-omap1/i2c.c +++ b/arch/arm/mach-omap1/i2c.c @@ -25,13 +25,8 @@ static struct platform_device omap_i2c_devices[1] = { static void __init omap1_i2c_mux_pins(int bus_id) { - if (cpu_is_omap7xx()) { - omap_cfg_reg(I2C_7XX_SDA); - omap_cfg_reg(I2C_7XX_SCL); - } else { - omap_cfg_reg(I2C_SDA); - omap_cfg_reg(I2C_SCL); - } + omap_cfg_reg(I2C_SDA); + omap_cfg_reg(I2C_SCL); } int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *pdata, @@ -68,10 +63,7 @@ int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *pdata, /* how the cpu bus is wired up differs for 7xx only */ - if (cpu_is_omap7xx()) - pdata->flags |= OMAP_I2C_FLAG_BUS_SHIFT_1; - else - pdata->flags |= OMAP_I2C_FLAG_BUS_SHIFT_2; + pdata->flags |= OMAP_I2C_FLAG_BUS_SHIFT_2; pdev->dev.platform_data = pdata; diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c index 0074b011a05a..a08406cb2303 100644 --- a/arch/arm/mach-omap1/io.c +++ b/arch/arm/mach-omap1/io.c @@ -22,27 +22,6 @@ * The machine specific code may provide the extra mapping besides the * default mapping provided here. */ -#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850) -static struct map_desc omap7xx_io_desc[] __initdata = { - { - .virtual = OMAP1_IO_VIRT, - .pfn = __phys_to_pfn(OMAP1_IO_PHYS), - .length = OMAP1_IO_SIZE, - .type = MT_DEVICE - }, - { - .virtual = OMAP7XX_DSP_BASE, - .pfn = __phys_to_pfn(OMAP7XX_DSP_START), - .length = OMAP7XX_DSP_SIZE, - .type = MT_DEVICE - }, { - .virtual = OMAP7XX_DSPREG_BASE, - .pfn = __phys_to_pfn(OMAP7XX_DSPREG_START), - .length = OMAP7XX_DSPREG_SIZE, - .type = MT_DEVICE - } -}; -#endif #ifdef CONFIG_ARCH_OMAP15XX static struct map_desc omap1510_io_desc[] __initdata = { @@ -88,13 +67,6 @@ static struct map_desc omap16xx_io_desc[] __initdata = { }; #endif -#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850) -void __init omap7xx_map_io(void) -{ - iotable_init(omap7xx_io_desc, ARRAY_SIZE(omap7xx_io_desc)); -} -#endif - #ifdef CONFIG_ARCH_OMAP15XX void __init omap15xx_map_io(void) { diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c index 70868e9f19ac..9ccc784fd614 100644 --- a/arch/arm/mach-omap1/irq.c +++ b/arch/arm/mach-omap1/irq.c @@ -110,14 +110,6 @@ static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger) irq_bank_writel(val, bank, offset); } -#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850) -static struct omap_irq_bank omap7xx_irq_banks[] = { - { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f }, - { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 }, - { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 }, -}; -#endif - #ifdef CONFIG_ARCH_OMAP15XX static struct omap_irq_bank omap1510_irq_banks[] = { { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff }, @@ -194,12 +186,6 @@ void __init omap1_init_irq(void) int i, j, irq_base; unsigned long nr_irqs; -#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) - if (cpu_is_omap7xx()) { - irq_banks = omap7xx_irq_banks; - irq_bank_count = ARRAY_SIZE(omap7xx_irq_banks); - } -#endif #ifdef CONFIG_ARCH_OMAP15XX if (cpu_is_omap1510()) { irq_banks = omap1510_irq_banks; @@ -230,7 +216,7 @@ void __init omap1_init_irq(void) pr_warn("Couldn't allocate IRQ numbers\n"); irq_base = 0; } - omap_l2_irq = cpu_is_omap7xx() ? irq_base + 1 : irq_base; + omap_l2_irq = irq_base; omap_l2_irq -= NR_IRQS_LEGACY; domain = irq_domain_add_legacy(NULL, nr_irqs, irq_base, 0, @@ -249,10 +235,6 @@ void __init omap1_init_irq(void) irq_bank_writel(0x03, 0, IRQ_CONTROL_REG_OFFSET); irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET); - /* Enable interrupts in global mask */ - if (cpu_is_omap7xx()) - irq_bank_writel(0x0, 0, IRQ_GMR_REG_OFFSET); - /* Install the interrupt handlers for each bank */ for (i = 0; i < irq_bank_count; i++) { for (j = i * 32; j < (i + 1) * 32; j++) { diff --git a/arch/arm/mach-omap1/irqs.h b/arch/arm/mach-omap1/irqs.h index 2851acfe5ff3..3ab7050b1b6b 100644 --- a/arch/arm/mach-omap1/irqs.h +++ b/arch/arm/mach-omap1/irqs.h @@ -231,15 +231,6 @@ #define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE) #define OMAP_IRQ_END (IH_MPUIO_BASE + 16) -/* External FPGA handles interrupts on Innovator boards */ -#define OMAP_FPGA_IRQ_BASE (OMAP_IRQ_END) -#ifdef CONFIG_MACH_OMAP_INNOVATOR -#define OMAP_FPGA_NR_IRQS 24 -#else -#define OMAP_FPGA_NR_IRQS 0 -#endif -#define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS) - #define OMAP_IRQ_BIT(irq) (1 << ((irq - NR_IRQS_LEGACY) % 32)) #ifdef CONFIG_FIQ diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c index b1632cbe37e6..37863bdce9ea 100644 --- a/arch/arm/mach-omap1/mcbsp.c +++ b/arch/arm/mach-omap1/mcbsp.c @@ -89,76 +89,6 @@ static struct omap_mcbsp_ops omap1_mcbsp_ops = { #define OMAP1610_MCBSP2_BASE 0xfffb1000 #define OMAP1610_MCBSP3_BASE 0xe1017000 -struct resource omap7xx_mcbsp_res[][6] = { - { - { - .start = OMAP7XX_MCBSP1_BASE, - .end = OMAP7XX_MCBSP1_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "rx", - .start = INT_7XX_McBSP1RX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "tx", - .start = INT_7XX_McBSP1TX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = 9, - .flags = IORESOURCE_DMA, - }, - { - .name = "tx", - .start = 8, - .flags = IORESOURCE_DMA, - }, - }, - { - { - .start = OMAP7XX_MCBSP2_BASE, - .end = OMAP7XX_MCBSP2_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "rx", - .start = INT_7XX_McBSP2RX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "tx", - .start = INT_7XX_McBSP2TX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = 11, - .flags = IORESOURCE_DMA, - }, - { - .name = "tx", - .start = 10, - .flags = IORESOURCE_DMA, - }, - }, -}; - -#define omap7xx_mcbsp_res_0 omap7xx_mcbsp_res[0] - -static struct omap_mcbsp_platform_data omap7xx_mcbsp_pdata[] = { - { - .ops = &omap1_mcbsp_ops, - }, - { - .ops = &omap1_mcbsp_ops, - }, -}; -#define OMAP7XX_MCBSP_RES_SZ ARRAY_SIZE(omap7xx_mcbsp_res[1]) -#define OMAP7XX_MCBSP_COUNT ARRAY_SIZE(omap7xx_mcbsp_res) - struct resource omap15xx_mcbsp_res[][6] = { { { @@ -397,12 +327,6 @@ static int __init omap1_mcbsp_init(void) if (!cpu_class_is_omap1()) return -ENODEV; - if (cpu_is_omap7xx()) - omap_mcbsp_register_board_cfg(omap7xx_mcbsp_res_0, - OMAP7XX_MCBSP_RES_SZ, - omap7xx_mcbsp_pdata, - OMAP7XX_MCBSP_COUNT); - if (cpu_is_omap15xx()) omap_mcbsp_register_board_cfg(omap15xx_mcbsp_res_0, OMAP15XX_MCBSP_RES_SZ, diff --git a/arch/arm/mach-omap1/mtd-xip.h b/arch/arm/mach-omap1/mtd-xip.h index 5ae312ff08a1..cbeda46dd526 100644 --- a/arch/arm/mach-omap1/mtd-xip.h +++ b/arch/arm/mach-omap1/mtd-xip.h @@ -42,11 +42,7 @@ static inline unsigned long xip_omap_mpu_timer_read(int nr) * (see linux/mtd/xip.h) */ -#ifdef CONFIG_MACH_OMAP_PERSEUS2 -#define xip_elapsed_since(x) (signed)((~xip_omap_mpu_timer_read(0) - (x)) / 7) -#else #define xip_elapsed_since(x) (signed)((~xip_omap_mpu_timer_read(0) - (x)) / 6) -#endif /* * xip_cpu_idle() is used when waiting for a delay equal or larger than diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c index 2d9458ff1d29..4456fbc8aa3d 100644 --- a/arch/arm/mach-omap1/mux.c +++ b/arch/arm/mach-omap1/mux.c @@ -21,52 +21,6 @@ static struct omap_mux_cfg arch_mux_cfg; -#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) -static struct pin_config omap7xx_pins[] = { -MUX_CFG_7XX("E2_7XX_KBR0", 12, 21, 0, 20, 1, 0) -MUX_CFG_7XX("J7_7XX_KBR1", 12, 25, 0, 24, 1, 0) -MUX_CFG_7XX("E1_7XX_KBR2", 12, 29, 0, 28, 1, 0) -MUX_CFG_7XX("F3_7XX_KBR3", 13, 1, 0, 0, 1, 0) -MUX_CFG_7XX("D2_7XX_KBR4", 13, 5, 0, 4, 1, 0) -MUX_CFG_7XX("C2_7XX_KBC0", 13, 9, 0, 8, 1, 0) -MUX_CFG_7XX("D3_7XX_KBC1", 13, 13, 0, 12, 1, 0) -MUX_CFG_7XX("E4_7XX_KBC2", 13, 17, 0, 16, 1, 0) -MUX_CFG_7XX("F4_7XX_KBC3", 13, 21, 0, 20, 1, 0) -MUX_CFG_7XX("E3_7XX_KBC4", 13, 25, 0, 24, 1, 0) - -MUX_CFG_7XX("AA17_7XX_USB_DM", 2, 21, 0, 20, 0, 0) -MUX_CFG_7XX("W16_7XX_USB_PU_EN", 2, 25, 0, 24, 0, 0) -MUX_CFG_7XX("W17_7XX_USB_VBUSI", 2, 29, 6, 28, 1, 0) -MUX_CFG_7XX("W18_7XX_USB_DMCK_OUT",3, 3, 1, 2, 0, 0) -MUX_CFG_7XX("W19_7XX_USB_DCRST", 3, 7, 1, 6, 0, 0) - -/* MMC Pins */ -MUX_CFG_7XX("MMC_7XX_CMD", 2, 9, 0, 8, 1, 0) -MUX_CFG_7XX("MMC_7XX_CLK", 2, 13, 0, 12, 1, 0) -MUX_CFG_7XX("MMC_7XX_DAT0", 2, 17, 0, 16, 1, 0) - -/* I2C interface */ -MUX_CFG_7XX("I2C_7XX_SCL", 5, 1, 0, 0, 1, 0) -MUX_CFG_7XX("I2C_7XX_SDA", 5, 5, 0, 0, 1, 0) - -/* SPI pins */ -MUX_CFG_7XX("SPI_7XX_1", 6, 5, 4, 4, 1, 0) -MUX_CFG_7XX("SPI_7XX_2", 6, 9, 4, 8, 1, 0) -MUX_CFG_7XX("SPI_7XX_3", 6, 13, 4, 12, 1, 0) -MUX_CFG_7XX("SPI_7XX_4", 6, 17, 4, 16, 1, 0) -MUX_CFG_7XX("SPI_7XX_5", 8, 25, 0, 24, 0, 0) -MUX_CFG_7XX("SPI_7XX_6", 9, 5, 0, 4, 0, 0) - -/* UART pins */ -MUX_CFG_7XX("UART_7XX_1", 3, 21, 0, 20, 0, 0) -MUX_CFG_7XX("UART_7XX_2", 8, 1, 6, 0, 0, 0) -}; -#define OMAP7XX_PINS_SZ ARRAY_SIZE(omap7xx_pins) -#else -#define omap7xx_pins NULL -#define OMAP7XX_PINS_SZ 0 -#endif /* CONFIG_ARCH_OMAP730 || CONFIG_ARCH_OMAP850 */ - #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) static struct pin_config omap1xxx_pins[] = { /* @@ -489,12 +443,6 @@ EXPORT_SYMBOL(omap_cfg_reg); int __init omap1_mux_init(void) { - if (cpu_is_omap7xx()) { - arch_mux_cfg.pins = omap7xx_pins; - arch_mux_cfg.size = OMAP7XX_PINS_SZ; - arch_mux_cfg.cfg_reg = omap1_cfg_reg; - } - if (cpu_is_omap15xx() || cpu_is_omap16xx()) { arch_mux_cfg.pins = omap1xxx_pins; arch_mux_cfg.size = OMAP1XXX_PINS_SZ; diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c index fce7d2b572bf..9761d8404949 100644 --- a/arch/arm/mach-omap1/pm.c +++ b/arch/arm/mach-omap1/pm.c @@ -69,7 +69,6 @@ static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE]; static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE]; static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE]; -static unsigned int mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_SIZE]; static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE]; static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE]; @@ -166,10 +165,7 @@ static void omap_pm_wakeup_setup(void) * drivers must still separately call omap_set_gpio_wakeup() to * wake up to a GPIO interrupt. */ - if (cpu_is_omap7xx()) - level1_wake = OMAP_IRQ_BIT(INT_7XX_GPIO_BANK1) | - OMAP_IRQ_BIT(INT_7XX_IH2_IRQ); - else if (cpu_is_omap15xx()) + if (cpu_is_omap15xx()) level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) | OMAP_IRQ_BIT(INT_1510_IH2_IRQ); else if (cpu_is_omap16xx()) @@ -178,12 +174,7 @@ static void omap_pm_wakeup_setup(void) omap_writel(~level1_wake, OMAP_IH1_MIR); - if (cpu_is_omap7xx()) { - omap_writel(~level2_wake, OMAP_IH2_0_MIR); - omap_writel(~(OMAP_IRQ_BIT(INT_7XX_WAKE_UP_REQ) | - OMAP_IRQ_BIT(INT_7XX_MPUIO_KEYPAD)), - OMAP_IH2_1_MIR); - } else if (cpu_is_omap15xx()) { + if (cpu_is_omap15xx()) { level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD); omap_writel(~level2_wake, OMAP_IH2_MIR); } else if (cpu_is_omap16xx()) { @@ -236,17 +227,7 @@ void omap1_pm_suspend(void) * Save interrupt, MPUI, ARM and UPLD control registers. */ - if (cpu_is_omap7xx()) { - MPUI7XX_SAVE(OMAP_IH1_MIR); - MPUI7XX_SAVE(OMAP_IH2_0_MIR); - MPUI7XX_SAVE(OMAP_IH2_1_MIR); - MPUI7XX_SAVE(MPUI_CTRL); - MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG); - MPUI7XX_SAVE(MPUI_DSP_API_CONFIG); - MPUI7XX_SAVE(EMIFS_CONFIG); - MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG); - - } else if (cpu_is_omap15xx()) { + if (cpu_is_omap15xx()) { MPUI1510_SAVE(OMAP_IH1_MIR); MPUI1510_SAVE(OMAP_IH2_MIR); MPUI1510_SAVE(MPUI_CTRL); @@ -288,9 +269,8 @@ void omap1_pm_suspend(void) /* stop DSP */ omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1); - /* shut down dsp_ck */ - if (!cpu_is_omap7xx()) - omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL); + /* shut down dsp_ck */ + omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL); /* temporarily enabling api_ck to access DSP registers */ omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2); @@ -366,13 +346,7 @@ void omap1_pm_suspend(void) ULPD_RESTORE(ULPD_CLOCK_CTRL); ULPD_RESTORE(ULPD_STATUS_REQ); - if (cpu_is_omap7xx()) { - MPUI7XX_RESTORE(EMIFS_CONFIG); - MPUI7XX_RESTORE(EMIFF_SDRAM_CONFIG); - MPUI7XX_RESTORE(OMAP_IH1_MIR); - MPUI7XX_RESTORE(OMAP_IH2_0_MIR); - MPUI7XX_RESTORE(OMAP_IH2_1_MIR); - } else if (cpu_is_omap15xx()) { + if (cpu_is_omap15xx()) { MPUI1510_RESTORE(MPUI_CTRL); MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG); MPUI1510_RESTORE(MPUI_DSP_API_CONFIG); @@ -433,14 +407,7 @@ static int omap_pm_debug_show(struct seq_file *m, void *v) ULPD_SAVE(ULPD_DPLL_CTRL); ULPD_SAVE(ULPD_POWER_CTRL); - if (cpu_is_omap7xx()) { - MPUI7XX_SAVE(MPUI_CTRL); - MPUI7XX_SAVE(MPUI_DSP_STATUS); - MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG); - MPUI7XX_SAVE(MPUI_DSP_API_CONFIG); - MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG); - MPUI7XX_SAVE(EMIFS_CONFIG); - } else if (cpu_is_omap15xx()) { + if (cpu_is_omap15xx()) { MPUI1510_SAVE(MPUI_CTRL); MPUI1510_SAVE(MPUI_DSP_STATUS); MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG); @@ -486,21 +453,7 @@ static int omap_pm_debug_show(struct seq_file *m, void *v) ULPD_SHOW(ULPD_STATUS_REQ), ULPD_SHOW(ULPD_POWER_CTRL)); - if (cpu_is_omap7xx()) { - seq_printf(m, - "MPUI7XX_CTRL_REG 0x%-8x \n" - "MPUI7XX_DSP_STATUS_REG: 0x%-8x \n" - "MPUI7XX_DSP_BOOT_CONFIG_REG: 0x%-8x \n" - "MPUI7XX_DSP_API_CONFIG_REG: 0x%-8x \n" - "MPUI7XX_SDRAM_CONFIG_REG: 0x%-8x \n" - "MPUI7XX_EMIFS_CONFIG_REG: 0x%-8x \n", - MPUI7XX_SHOW(MPUI_CTRL), - MPUI7XX_SHOW(MPUI_DSP_STATUS), - MPUI7XX_SHOW(MPUI_DSP_BOOT_CONFIG), - MPUI7XX_SHOW(MPUI_DSP_API_CONFIG), - MPUI7XX_SHOW(EMIFF_SDRAM_CONFIG), - MPUI7XX_SHOW(EMIFS_CONFIG)); - } else if (cpu_is_omap15xx()) { + if (cpu_is_omap15xx()) { seq_printf(m, "MPUI1510_CTRL_REG 0x%-8x \n" "MPUI1510_DSP_STATUS_REG: 0x%-8x \n" @@ -634,10 +587,7 @@ static int __init omap_pm_init(void) * These routines need to be in SRAM as that's the only * memory the MPU can see when it wakes up. */ - if (cpu_is_omap7xx()) { - omap_sram_suspend = omap_sram_push(omap7xx_cpu_suspend, - omap7xx_cpu_suspend_sz); - } else if (cpu_is_omap15xx()) { + if (cpu_is_omap15xx()) { omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend, omap1510_cpu_suspend_sz); } else if (cpu_is_omap16xx()) { @@ -652,9 +602,7 @@ static int __init omap_pm_init(void) arm_pm_idle = omap1_pm_idle; - if (cpu_is_omap7xx()) - irq = INT_7XX_WAKE_UP_REQ; - else if (cpu_is_omap16xx()) + if (cpu_is_omap16xx()) irq = INT_1610_WAKE_UP_REQ; else irq = -1; @@ -673,9 +621,7 @@ static int __init omap_pm_init(void) omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL); /* Configure IDLECT3 */ - if (cpu_is_omap7xx()) - omap_writel(OMAP7XX_IDLECT3_VAL, OMAP7XX_IDLECT3); - else if (cpu_is_omap16xx()) + if (cpu_is_omap16xx()) omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3); suspend_set_ops(&omap_pm_ops); diff --git a/arch/arm/mach-omap1/pm.h b/arch/arm/mach-omap1/pm.h index 0d1f092821ff..d4373a5c4697 100644 --- a/arch/arm/mach-omap1/pm.h +++ b/arch/arm/mach-omap1/pm.h @@ -100,12 +100,6 @@ #define OMAP1610_IDLECT3 0xfffece24 #define OMAP1610_IDLE_LOOP_REQUEST 0x0400 -#define OMAP7XX_IDLECT1_SLEEP_VAL 0x16c7 -#define OMAP7XX_IDLECT2_SLEEP_VAL 0x09c7 -#define OMAP7XX_IDLECT3_VAL 0x3f -#define OMAP7XX_IDLECT3 0xfffece24 -#define OMAP7XX_IDLE_LOOP_REQUEST 0x0C00 - #ifndef __ASSEMBLER__ #include @@ -118,17 +112,13 @@ extern void allow_idle_sleep(void); extern void omap1_pm_idle(void); extern void omap1_pm_suspend(void); -extern void omap7xx_cpu_suspend(unsigned long, unsigned long); extern void omap1510_cpu_suspend(unsigned long, unsigned long); extern void omap1610_cpu_suspend(unsigned long, unsigned long); -extern void omap7xx_idle_loop_suspend(void); extern void omap1510_idle_loop_suspend(void); extern void omap1610_idle_loop_suspend(void); -extern unsigned int omap7xx_cpu_suspend_sz; extern unsigned int omap1510_cpu_suspend_sz; extern unsigned int omap1610_cpu_suspend_sz; -extern unsigned int omap7xx_idle_loop_suspend_sz; extern unsigned int omap1510_idle_loop_suspend_sz; extern unsigned int omap1610_idle_loop_suspend_sz; @@ -151,10 +141,6 @@ extern void omap_serial_wake_trigger(int enable); #define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x)) #define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] -#define MPUI7XX_SAVE(x) mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x] = omap_readl(x) -#define MPUI7XX_RESTORE(x) omap_writel((mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x]), (x)) -#define MPUI7XX_SHOW(x) mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x] - #define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x) #define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x)) #define MPUI1510_SHOW(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] @@ -228,27 +214,6 @@ enum mpui1510_save_state { #endif }; -enum mpui7xx_save_state { - MPUI7XX_SLEEP_SAVE_START = 0, - /* - * MPUI registers 32 bits - */ - MPUI7XX_SLEEP_SAVE_MPUI_CTRL, - MPUI7XX_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG, - MPUI7XX_SLEEP_SAVE_MPUI_DSP_API_CONFIG, - MPUI7XX_SLEEP_SAVE_MPUI_DSP_STATUS, - MPUI7XX_SLEEP_SAVE_EMIFF_SDRAM_CONFIG, - MPUI7XX_SLEEP_SAVE_EMIFS_CONFIG, - MPUI7XX_SLEEP_SAVE_OMAP_IH1_MIR, - MPUI7XX_SLEEP_SAVE_OMAP_IH2_0_MIR, - MPUI7XX_SLEEP_SAVE_OMAP_IH2_1_MIR, -#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) - MPUI7XX_SLEEP_SAVE_SIZE -#else - MPUI7XX_SLEEP_SAVE_SIZE = 0 -#endif -}; - enum mpui1610_save_state { MPUI1610_SLEEP_SAVE_START = 0, /* diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c index 88928fc33b2e..c7f590645774 100644 --- a/arch/arm/mach-omap1/serial.c +++ b/arch/arm/mach-omap1/serial.c @@ -106,13 +106,6 @@ void __init omap_serial_init(void) { int i; - if (cpu_is_omap7xx()) { - serial_platform_data[0].regshift = 0; - serial_platform_data[1].regshift = 0; - serial_platform_data[0].irq = INT_7XX_UART_MODEM_1; - serial_platform_data[1].irq = INT_7XX_UART_MODEM_IRDA_2; - } - if (cpu_is_omap15xx()) { serial_platform_data[0].uartclk = OMAP1510_BASE_BAUD * 16; serial_platform_data[1].uartclk = OMAP1510_BASE_BAUD * 16; @@ -120,14 +113,6 @@ void __init omap_serial_init(void) } for (i = 0; i < ARRAY_SIZE(serial_platform_data) - 1; i++) { - - /* Don't look at UARTs higher than 2 for omap7xx */ - if (cpu_is_omap7xx() && i > 1) { - serial_platform_data[i].membase = NULL; - serial_platform_data[i].mapbase = 0; - continue; - } - /* Static mapping, never released */ serial_platform_data[i].membase = ioremap(serial_platform_data[i].mapbase, SZ_2K); diff --git a/arch/arm/mach-omap1/sleep.S b/arch/arm/mach-omap1/sleep.S index f111b79512ce..6192f52d531a 100644 --- a/arch/arm/mach-omap1/sleep.S +++ b/arch/arm/mach-omap1/sleep.S @@ -61,86 +61,6 @@ * */ -#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) - .align 3 -ENTRY(omap7xx_cpu_suspend) - - @ save registers on stack - stmfd sp!, {r0 - r12, lr} - - @ Drain write cache - mov r4, #0 - mcr p15, 0, r0, c7, c10, 4 - nop - - @ load base address of Traffic Controller - mov r6, #TCMIF_ASM_BASE & 0xff000000 - orr r6, r6, #TCMIF_ASM_BASE & 0x00ff0000 - orr r6, r6, #TCMIF_ASM_BASE & 0x0000ff00 - - @ prepare to put SDRAM into self-refresh manually - ldr r7, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff] - orr r9, r7, #SELF_REFRESH_MODE & 0xff000000 - orr r9, r9, #SELF_REFRESH_MODE & 0x000000ff - str r9, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff] - - @ prepare to put EMIFS to Sleep - ldr r8, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff] - orr r9, r8, #IDLE_EMIFS_REQUEST & 0xff - str r9, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff] - - @ load base address of ARM_IDLECT1 and ARM_IDLECT2 - mov r4, #CLKGEN_REG_ASM_BASE & 0xff000000 - orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000 - orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00 - - @ turn off clock domains - @ do not disable PERCK (0x04) - mov r5, #OMAP7XX_IDLECT2_SLEEP_VAL & 0xff - orr r5, r5, #OMAP7XX_IDLECT2_SLEEP_VAL & 0xff00 - strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff] - - @ request ARM idle - mov r3, #OMAP7XX_IDLECT1_SLEEP_VAL & 0xff - orr r3, r3, #OMAP7XX_IDLECT1_SLEEP_VAL & 0xff00 - strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff] - - @ disable instruction cache - mrc p15, 0, r9, c1, c0, 0 - bic r2, r9, #0x1000 - mcr p15, 0, r2, c1, c0, 0 - nop - -/* - * Let's wait for the next wake up event to wake us up. r0 can't be - * used here because r0 holds ARM_IDLECT1 - */ - mov r2, #0 - mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt -/* - * omap7xx_cpu_suspend()'s resume point. - * - * It will just start executing here, so we'll restore stuff from the - * stack. - */ - @ re-enable Icache - mcr p15, 0, r9, c1, c0, 0 - - @ reset the ARM_IDLECT1 and ARM_IDLECT2. - strh r1, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff] - strh r0, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff] - - @ Restore EMIFF controls - str r7, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff] - str r8, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff] - - @ restore regs and return - ldmfd sp!, {r0 - r12, pc} - -ENTRY(omap7xx_cpu_suspend_sz) - .word . - omap7xx_cpu_suspend -#endif /* CONFIG_ARCH_OMAP730 || CONFIG_ARCH_OMAP850 */ - #ifdef CONFIG_ARCH_OMAP15XX .align 3 ENTRY(omap1510_cpu_suspend) diff --git a/arch/arm/mach-omap1/sram-init.c b/arch/arm/mach-omap1/sram-init.c index dabf0c4defeb..26427d6be896 100644 --- a/arch/arm/mach-omap1/sram-init.c +++ b/arch/arm/mach-omap1/sram-init.c @@ -94,9 +94,7 @@ static void __init omap_detect_and_map_sram(void) omap_sram_skip = SRAM_BOOTLOADER_SZ; omap_sram_start = OMAP1_SRAM_PA; - if (cpu_is_omap7xx()) - omap_sram_size = 0x32000; /* 200K */ - else if (cpu_is_omap15xx()) + if (cpu_is_omap15xx()) omap_sram_size = 0x30000; /* 192K */ else if (cpu_is_omap1610() || cpu_is_omap1611() || cpu_is_omap1621() || cpu_is_omap1710()) @@ -133,9 +131,6 @@ static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl); void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl) { BUG_ON(!_omap_sram_reprogram_clock); - /* On 730, bit 13 must always be 1 */ - if (cpu_is_omap7xx()) - ckctl |= 0x2000; _omap_sram_reprogram_clock(dpllctl, ckctl); } diff --git a/arch/arm/mach-omap1/usb.c b/arch/arm/mach-omap1/usb.c index 0119f3ddb7a6..08d42abc4a0f 100644 --- a/arch/arm/mach-omap1/usb.c +++ b/arch/arm/mach-omap1/usb.c @@ -190,12 +190,6 @@ static struct platform_device udc_device = { static inline void udc_device_init(struct omap_usb_config *pdata) { - /* IRQ numbers for omap7xx */ - if(cpu_is_omap7xx()) { - udc_resources[1].start = INT_7XX_USB_GENI; - udc_resources[2].start = INT_7XX_USB_NON_ISO; - udc_resources[3].start = INT_7XX_USB_ISO; - } pdata->udc_device = &udc_device; } @@ -238,8 +232,6 @@ static inline void ohci_device_init(struct omap_usb_config *pdata) if (!IS_ENABLED(CONFIG_USB_OHCI_HCD)) return; - if (cpu_is_omap7xx()) - ohci_resources[1].start = INT_7XX_USB_HHC_1; pdata->ohci_device = &ohci_device; pdata->ocpi_enable = &ocpi_enable; } @@ -267,8 +259,6 @@ static struct platform_device otg_device = { static inline void otg_device_init(struct omap_usb_config *pdata) { - if (cpu_is_omap7xx()) - otg_resources[1].start = INT_7XX_USB_OTG; pdata->otg_device = &otg_device; } @@ -297,14 +287,7 @@ static u32 __init omap1_usb0_init(unsigned nwires, unsigned is_device) } if (is_device) { - if (cpu_is_omap7xx()) { - omap_cfg_reg(AA17_7XX_USB_DM); - omap_cfg_reg(W16_7XX_USB_PU_EN); - omap_cfg_reg(W17_7XX_USB_VBUSI); - omap_cfg_reg(W18_7XX_USB_DMCK_OUT); - omap_cfg_reg(W19_7XX_USB_DCRST); - } else - omap_cfg_reg(W4_USB_PUEN); + omap_cfg_reg(W4_USB_PUEN); } if (nwires == 2) { @@ -324,14 +307,11 @@ static u32 __init omap1_usb0_init(unsigned nwires, unsigned is_device) * - OTG support on this port not yet written */ - /* Don't do this for omap7xx -- it causes USB to not work correctly */ - if (!cpu_is_omap7xx()) { - l = omap_readl(USB_TRANSCEIVER_CTRL); - l &= ~(7 << 4); - if (!is_device) - l |= (3 << 1); - omap_writel(l, USB_TRANSCEIVER_CTRL); - } + l = omap_readl(USB_TRANSCEIVER_CTRL); + l &= ~(7 << 4); + if (!is_device) + l |= (3 << 1); + omap_writel(l, USB_TRANSCEIVER_CTRL); return 3 << 16; } @@ -698,7 +678,7 @@ void __init omap1_usb_init(struct omap_usb_config *_pdata) ohci_device_init(pdata); otg_device_init(pdata); - if (cpu_is_omap7xx() || cpu_is_omap16xx()) + if (cpu_is_omap16xx()) omap_otg_init(pdata); else if (cpu_is_omap15xx()) omap_1510_usb_init(pdata); -- cgit From 9a99b142f7ef23bc3cb4cb82bf7f5abc173b11ca Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 4 Jan 2023 13:55:37 +0100 Subject: ARM: omap1: merge omap1_map_io functions The OMAP15xx/OMAP16xx variants are exactly the same, so merge them into one. Signed-off-by: Arnd Bergmann --- arch/arm/mach-omap1/board-ams-delta.c | 2 +- arch/arm/mach-omap1/board-nokia770.c | 2 +- arch/arm/mach-omap1/board-osk.c | 2 +- arch/arm/mach-omap1/board-palmte.c | 2 +- arch/arm/mach-omap1/board-sx1.c | 2 +- arch/arm/mach-omap1/common.h | 21 +------------ arch/arm/mach-omap1/io.c | 56 ++++++++--------------------------- 7 files changed, 18 insertions(+), 69 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c index 651c28d81132..0f67ac4c6fd2 100644 --- a/arch/arm/mach-omap1/board-ams-delta.c +++ b/arch/arm/mach-omap1/board-ams-delta.c @@ -871,7 +871,7 @@ static void __init ams_delta_init_late(void) static void __init ams_delta_map_io(void) { - omap15xx_map_io(); + omap1_map_io(); iotable_init(ams_delta_io_desc, ARRAY_SIZE(ams_delta_io_desc)); } diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c index 8e0e58495023..a501a473ffd6 100644 --- a/arch/arm/mach-omap1/board-nokia770.c +++ b/arch/arm/mach-omap1/board-nokia770.c @@ -288,7 +288,7 @@ static void __init omap_nokia770_init(void) MACHINE_START(NOKIA770, "Nokia 770") .atag_offset = 0x100, - .map_io = omap16xx_map_io, + .map_io = omap1_map_io, .init_early = omap1_init_early, .init_irq = omap1_init_irq, .handle_irq = omap1_handle_irq, diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index 7049e608b25a..df758c1f9237 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c @@ -386,7 +386,7 @@ static void __init osk_init(void) MACHINE_START(OMAP_OSK, "TI-OSK") /* Maintainer: Dirk Behme */ .atag_offset = 0x100, - .map_io = omap16xx_map_io, + .map_io = omap1_map_io, .init_early = omap1_init_early, .init_irq = omap1_init_irq, .handle_irq = omap1_handle_irq, diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c index 72e1979c7a8b..f79c497f04d5 100644 --- a/arch/arm/mach-omap1/board-palmte.c +++ b/arch/arm/mach-omap1/board-palmte.c @@ -256,7 +256,7 @@ static void __init omap_palmte_init(void) MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E") .atag_offset = 0x100, - .map_io = omap15xx_map_io, + .map_io = omap1_map_io, .init_early = omap1_init_early, .init_irq = omap1_init_irq, .handle_irq = omap1_handle_irq, diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c index f0dbb0e8d8e7..0c0cdd5e77c7 100644 --- a/arch/arm/mach-omap1/board-sx1.c +++ b/arch/arm/mach-omap1/board-sx1.c @@ -335,7 +335,7 @@ static void __init omap_sx1_init(void) MACHINE_START(SX1, "OMAP310 based Siemens SX1") .atag_offset = 0x100, - .map_io = omap15xx_map_io, + .map_io = omap1_map_io, .init_early = omap1_init_early, .init_irq = omap1_init_irq, .handle_irq = omap1_handle_irq, diff --git a/arch/arm/mach-omap1/common.h b/arch/arm/mach-omap1/common.h index 3fd9ed9efb12..7a7c3d9eb84a 100644 --- a/arch/arm/mach-omap1/common.h +++ b/arch/arm/mach-omap1/common.h @@ -35,26 +35,6 @@ #include "soc.h" #include "i2c.h" -#ifdef CONFIG_ARCH_OMAP15XX -void omap1510_fpga_init_irq(void); -void omap15xx_map_io(void); -#else -static inline void omap1510_fpga_init_irq(void) -{ -} -static inline void omap15xx_map_io(void) -{ -} -#endif - -#ifdef CONFIG_ARCH_OMAP16XX -void omap16xx_map_io(void); -#else -static inline void omap16xx_map_io(void) -{ -} -#endif - #ifdef CONFIG_OMAP_SERIAL_WAKE int omap_serial_wakeup_init(void); #else @@ -64,6 +44,7 @@ static inline int omap_serial_wakeup_init(void) } #endif +void omap1_map_io(void); void omap1_init_early(void); void omap1_init_irq(void); void __exception_irq_entry omap1_handle_irq(struct pt_regs *regs); diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c index a08406cb2303..1f20fe99be57 100644 --- a/arch/arm/mach-omap1/io.c +++ b/arch/arm/mach-omap1/io.c @@ -22,64 +22,32 @@ * The machine specific code may provide the extra mapping besides the * default mapping provided here. */ - -#ifdef CONFIG_ARCH_OMAP15XX -static struct map_desc omap1510_io_desc[] __initdata = { +static struct map_desc omap1_io_desc[] __initdata = { { .virtual = OMAP1_IO_VIRT, .pfn = __phys_to_pfn(OMAP1_IO_PHYS), .length = OMAP1_IO_SIZE, .type = MT_DEVICE - }, - { - .virtual = OMAP1510_DSP_BASE, - .pfn = __phys_to_pfn(OMAP1510_DSP_START), - .length = OMAP1510_DSP_SIZE, - .type = MT_DEVICE }, { - .virtual = OMAP1510_DSPREG_BASE, - .pfn = __phys_to_pfn(OMAP1510_DSPREG_START), - .length = OMAP1510_DSPREG_SIZE, - .type = MT_DEVICE - } -}; -#endif - -#if defined(CONFIG_ARCH_OMAP16XX) -static struct map_desc omap16xx_io_desc[] __initdata = { - { - .virtual = OMAP1_IO_VIRT, - .pfn = __phys_to_pfn(OMAP1_IO_PHYS), - .length = OMAP1_IO_SIZE, - .type = MT_DEVICE - }, - { - .virtual = OMAP16XX_DSP_BASE, - .pfn = __phys_to_pfn(OMAP16XX_DSP_START), - .length = OMAP16XX_DSP_SIZE, + .virtual = OMAP1_DSP_BASE, + .pfn = __phys_to_pfn(OMAP1_DSP_START), + .length = OMAP1_DSP_SIZE, .type = MT_DEVICE }, { - .virtual = OMAP16XX_DSPREG_BASE, - .pfn = __phys_to_pfn(OMAP16XX_DSPREG_START), - .length = OMAP16XX_DSPREG_SIZE, + .virtual = OMAP1_DSPREG_BASE, + .pfn = __phys_to_pfn(OMAP1_DSPREG_START), + .length = OMAP1_DSPREG_SIZE, .type = MT_DEVICE } }; -#endif -#ifdef CONFIG_ARCH_OMAP15XX -void __init omap15xx_map_io(void) -{ - iotable_init(omap1510_io_desc, ARRAY_SIZE(omap1510_io_desc)); -} -#endif - -#if defined(CONFIG_ARCH_OMAP16XX) -void __init omap16xx_map_io(void) +/* + * Maps common IO regions for omap1 + */ +void __init omap1_map_io(void) { - iotable_init(omap16xx_io_desc, ARRAY_SIZE(omap16xx_io_desc)); + iotable_init(omap1_io_desc, ARRAY_SIZE(omap1_io_desc)); } -#endif /* * Common low-level hardware init for omap1. -- cgit From 76873bb5b89792c9dd6873c1b5567d3787d59b68 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 4 Jan 2023 13:56:57 +0100 Subject: ARM: omap1: remove unused omapxxxx.h headers The only bit that is still in use is the OMAP_IH2_*_* macros, so move them into the existing hardware.h file. Signed-off-by: Arnd Bergmann --- arch/arm/mach-omap1/devices.c | 1 - arch/arm/mach-omap1/hardware.h | 48 +++++++++- arch/arm/mach-omap1/omap1510.h | 162 --------------------------------- arch/arm/mach-omap1/omap16xx.h | 201 ----------------------------------------- arch/arm/mach-omap1/omap7xx.h | 106 ---------------------- 5 files changed, 44 insertions(+), 474 deletions(-) delete mode 100644 arch/arm/mach-omap1/omap1510.h delete mode 100644 arch/arm/mach-omap1/omap16xx.h delete mode 100644 arch/arm/mach-omap1/omap7xx.h (limited to 'arch/arm') diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c index 42d1631cecc0..5304699c7a97 100644 --- a/arch/arm/mach-omap1/devices.c +++ b/arch/arm/mach-omap1/devices.c @@ -21,7 +21,6 @@ #include "tc.h" #include "mux.h" -#include "omap7xx.h" #include "hardware.h" #include "common.h" #include "clock.h" diff --git a/arch/arm/mach-omap1/hardware.h b/arch/arm/mach-omap1/hardware.h index c228234a1ed4..0aa571c9e0eb 100644 --- a/arch/arm/mach-omap1/hardware.h +++ b/arch/arm/mach-omap1/hardware.h @@ -114,6 +114,10 @@ static inline u32 omap_cs3_phys(void) #define OMAP_IH1_BASE 0xfffecb00 #define OMAP_IH2_BASE 0xfffe0000 +#define OMAP_IH2_0_BASE (0xfffe0000) +#define OMAP_IH2_1_BASE (0xfffe0100) +#define OMAP_IH2_2_BASE (0xfffe0200) +#define OMAP_IH2_3_BASE (0xfffe0300) #define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00) #define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04) @@ -131,6 +135,38 @@ static inline u32 omap_cs3_phys(void) #define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c) #define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c) +#define OMAP_IH2_0_ITR (OMAP_IH2_0_BASE + 0x00) +#define OMAP_IH2_0_MIR (OMAP_IH2_0_BASE + 0x04) +#define OMAP_IH2_0_SIR_IRQ (OMAP_IH2_0_BASE + 0x10) +#define OMAP_IH2_0_SIR_FIQ (OMAP_IH2_0_BASE + 0x14) +#define OMAP_IH2_0_CONTROL (OMAP_IH2_0_BASE + 0x18) +#define OMAP_IH2_0_ILR0 (OMAP_IH2_0_BASE + 0x1c) +#define OMAP_IH2_0_ISR (OMAP_IH2_0_BASE + 0x9c) + +#define OMAP_IH2_1_ITR (OMAP_IH2_1_BASE + 0x00) +#define OMAP_IH2_1_MIR (OMAP_IH2_1_BASE + 0x04) +#define OMAP_IH2_1_SIR_IRQ (OMAP_IH2_1_BASE + 0x10) +#define OMAP_IH2_1_SIR_FIQ (OMAP_IH2_1_BASE + 0x14) +#define OMAP_IH2_1_CONTROL (OMAP_IH2_1_BASE + 0x18) +#define OMAP_IH2_1_ILR1 (OMAP_IH2_1_BASE + 0x1c) +#define OMAP_IH2_1_ISR (OMAP_IH2_1_BASE + 0x9c) + +#define OMAP_IH2_2_ITR (OMAP_IH2_2_BASE + 0x00) +#define OMAP_IH2_2_MIR (OMAP_IH2_2_BASE + 0x04) +#define OMAP_IH2_2_SIR_IRQ (OMAP_IH2_2_BASE + 0x10) +#define OMAP_IH2_2_SIR_FIQ (OMAP_IH2_2_BASE + 0x14) +#define OMAP_IH2_2_CONTROL (OMAP_IH2_2_BASE + 0x18) +#define OMAP_IH2_2_ILR2 (OMAP_IH2_2_BASE + 0x1c) +#define OMAP_IH2_2_ISR (OMAP_IH2_2_BASE + 0x9c) + +#define OMAP_IH2_3_ITR (OMAP_IH2_3_BASE + 0x00) +#define OMAP_IH2_3_MIR (OMAP_IH2_3_BASE + 0x04) +#define OMAP_IH2_3_SIR_IRQ (OMAP_IH2_3_BASE + 0x10) +#define OMAP_IH2_3_SIR_FIQ (OMAP_IH2_3_BASE + 0x14) +#define OMAP_IH2_3_CONTROL (OMAP_IH2_3_BASE + 0x18) +#define OMAP_IH2_3_ILR3 (OMAP_IH2_3_BASE + 0x1c) +#define OMAP_IH2_3_ISR (OMAP_IH2_3_BASE + 0x9c) + #define IRQ_ITR_REG_OFFSET 0x00 #define IRQ_MIR_REG_OFFSET 0x04 #define IRQ_SIR_IRQ_REG_OFFSET 0x10 @@ -184,12 +220,16 @@ static inline u32 omap_cs3_phys(void) /* * --------------------------------------------------------------------------- - * Processor specific defines + * DSP * --------------------------------------------------------------------------- */ -#include "omap7xx.h" -#include "omap1510.h" -#include "omap16xx.h" +#define OMAP1_DSP_BASE 0xE0000000 +#define OMAP1_DSP_SIZE 0x28000 +#define OMAP1_DSP_START 0xE0000000 + +#define OMAP1_DSPREG_BASE 0xE1000000 +#define OMAP1_DSPREG_SIZE SZ_128K +#define OMAP1_DSPREG_START 0xE1000000 #endif /* __ASM_ARCH_OMAP_HARDWARE_H */ diff --git a/arch/arm/mach-omap1/omap1510.h b/arch/arm/mach-omap1/omap1510.h deleted file mode 100644 index 3d235244bf5c..000000000000 --- a/arch/arm/mach-omap1/omap1510.h +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Hardware definitions for TI OMAP1510 processor. - * - * Cleanup for Linux-2.6 by Dirk Behme - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __ASM_ARCH_OMAP15XX_H -#define __ASM_ARCH_OMAP15XX_H - -/* - * ---------------------------------------------------------------------------- - * Base addresses - * ---------------------------------------------------------------------------- - */ - -/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */ - -#define OMAP1510_DSP_BASE 0xE0000000 -#define OMAP1510_DSP_SIZE 0x28000 -#define OMAP1510_DSP_START 0xE0000000 - -#define OMAP1510_DSPREG_BASE 0xE1000000 -#define OMAP1510_DSPREG_SIZE SZ_128K -#define OMAP1510_DSPREG_START 0xE1000000 - -#define OMAP1510_DSP_MMU_BASE (0xfffed200) - -/* - * --------------------------------------------------------------------------- - * OMAP-1510 FPGA - * --------------------------------------------------------------------------- - */ -#define OMAP1510_FPGA_BASE 0xE8000000 /* VA */ -#define OMAP1510_FPGA_SIZE SZ_4K -#define OMAP1510_FPGA_START 0x08000000 /* PA */ - -/* Revision */ -#define OMAP1510_FPGA_REV_LOW IOMEM(OMAP1510_FPGA_BASE + 0x0) -#define OMAP1510_FPGA_REV_HIGH IOMEM(OMAP1510_FPGA_BASE + 0x1) -#define OMAP1510_FPGA_LCD_PANEL_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x2) -#define OMAP1510_FPGA_LED_DIGIT IOMEM(OMAP1510_FPGA_BASE + 0x3) -#define INNOVATOR_FPGA_HID_SPI IOMEM(OMAP1510_FPGA_BASE + 0x4) -#define OMAP1510_FPGA_POWER IOMEM(OMAP1510_FPGA_BASE + 0x5) - -/* Interrupt status */ -#define OMAP1510_FPGA_ISR_LO IOMEM(OMAP1510_FPGA_BASE + 0x6) -#define OMAP1510_FPGA_ISR_HI IOMEM(OMAP1510_FPGA_BASE + 0x7) - -/* Interrupt mask */ -#define OMAP1510_FPGA_IMR_LO IOMEM(OMAP1510_FPGA_BASE + 0x8) -#define OMAP1510_FPGA_IMR_HI IOMEM(OMAP1510_FPGA_BASE + 0x9) - -/* Reset registers */ -#define OMAP1510_FPGA_HOST_RESET IOMEM(OMAP1510_FPGA_BASE + 0xa) -#define OMAP1510_FPGA_RST IOMEM(OMAP1510_FPGA_BASE + 0xb) - -#define OMAP1510_FPGA_AUDIO IOMEM(OMAP1510_FPGA_BASE + 0xc) -#define OMAP1510_FPGA_DIP IOMEM(OMAP1510_FPGA_BASE + 0xe) -#define OMAP1510_FPGA_FPGA_IO IOMEM(OMAP1510_FPGA_BASE + 0xf) -#define OMAP1510_FPGA_UART1 IOMEM(OMAP1510_FPGA_BASE + 0x14) -#define OMAP1510_FPGA_UART2 IOMEM(OMAP1510_FPGA_BASE + 0x15) -#define OMAP1510_FPGA_OMAP1510_STATUS IOMEM(OMAP1510_FPGA_BASE + 0x16) -#define OMAP1510_FPGA_BOARD_REV IOMEM(OMAP1510_FPGA_BASE + 0x18) -#define INNOVATOR_FPGA_CAM_USB_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x20c) -#define OMAP1510P1_PPT_DATA IOMEM(OMAP1510_FPGA_BASE + 0x100) -#define OMAP1510P1_PPT_STATUS IOMEM(OMAP1510_FPGA_BASE + 0x101) -#define OMAP1510P1_PPT_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x102) - -#define OMAP1510_FPGA_TOUCHSCREEN IOMEM(OMAP1510_FPGA_BASE + 0x204) - -#define INNOVATOR_FPGA_INFO IOMEM(OMAP1510_FPGA_BASE + 0x205) -#define INNOVATOR_FPGA_LCD_BRIGHT_LO IOMEM(OMAP1510_FPGA_BASE + 0x206) -#define INNOVATOR_FPGA_LCD_BRIGHT_HI IOMEM(OMAP1510_FPGA_BASE + 0x207) -#define INNOVATOR_FPGA_LED_GRN_LO IOMEM(OMAP1510_FPGA_BASE + 0x208) -#define INNOVATOR_FPGA_LED_GRN_HI IOMEM(OMAP1510_FPGA_BASE + 0x209) -#define INNOVATOR_FPGA_LED_RED_LO IOMEM(OMAP1510_FPGA_BASE + 0x20a) -#define INNOVATOR_FPGA_LED_RED_HI IOMEM(OMAP1510_FPGA_BASE + 0x20b) -#define INNOVATOR_FPGA_EXP_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x20d) -#define INNOVATOR_FPGA_ISR2 IOMEM(OMAP1510_FPGA_BASE + 0x20e) -#define INNOVATOR_FPGA_IMR2 IOMEM(OMAP1510_FPGA_BASE + 0x210) - -#define OMAP1510_FPGA_ETHR_START (OMAP1510_FPGA_START + 0x300) - -/* - * Power up Giga UART driver, turn on HID clock. - * Turn off BT power, since we're not using it and it - * draws power. - */ -#define OMAP1510_FPGA_RESET_VALUE 0x42 - -#define OMAP1510_FPGA_PCR_IF_PD0 (1 << 7) -#define OMAP1510_FPGA_PCR_COM2_EN (1 << 6) -#define OMAP1510_FPGA_PCR_COM1_EN (1 << 5) -#define OMAP1510_FPGA_PCR_EXP_PD0 (1 << 4) -#define OMAP1510_FPGA_PCR_EXP_PD1 (1 << 3) -#define OMAP1510_FPGA_PCR_48MHZ_CLK (1 << 2) -#define OMAP1510_FPGA_PCR_4MHZ_CLK (1 << 1) -#define OMAP1510_FPGA_PCR_RSRVD_BIT0 (1 << 0) - -/* - * Innovator/OMAP1510 FPGA HID register bit definitions - */ -#define OMAP1510_FPGA_HID_SCLK (1<<0) /* output */ -#define OMAP1510_FPGA_HID_MOSI (1<<1) /* output */ -#define OMAP1510_FPGA_HID_nSS (1<<2) /* output 0/1 chip idle/select */ -#define OMAP1510_FPGA_HID_nHSUS (1<<3) /* output 0/1 host active/suspended */ -#define OMAP1510_FPGA_HID_MISO (1<<4) /* input */ -#define OMAP1510_FPGA_HID_ATN (1<<5) /* input 0/1 chip idle/ATN */ -#define OMAP1510_FPGA_HID_rsrvd (1<<6) -#define OMAP1510_FPGA_HID_RESETn (1<<7) /* output - 0/1 USAR reset/run */ - -/* The FPGA IRQ is cascaded through GPIO_13 */ -#define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13) - -/* IRQ Numbers for interrupts muxed through the FPGA */ -#define OMAP1510_INT_FPGA_ATN (OMAP_FPGA_IRQ_BASE + 0) -#define OMAP1510_INT_FPGA_ACK (OMAP_FPGA_IRQ_BASE + 1) -#define OMAP1510_INT_FPGA2 (OMAP_FPGA_IRQ_BASE + 2) -#define OMAP1510_INT_FPGA3 (OMAP_FPGA_IRQ_BASE + 3) -#define OMAP1510_INT_FPGA4 (OMAP_FPGA_IRQ_BASE + 4) -#define OMAP1510_INT_FPGA5 (OMAP_FPGA_IRQ_BASE + 5) -#define OMAP1510_INT_FPGA6 (OMAP_FPGA_IRQ_BASE + 6) -#define OMAP1510_INT_FPGA7 (OMAP_FPGA_IRQ_BASE + 7) -#define OMAP1510_INT_FPGA8 (OMAP_FPGA_IRQ_BASE + 8) -#define OMAP1510_INT_FPGA9 (OMAP_FPGA_IRQ_BASE + 9) -#define OMAP1510_INT_FPGA10 (OMAP_FPGA_IRQ_BASE + 10) -#define OMAP1510_INT_FPGA11 (OMAP_FPGA_IRQ_BASE + 11) -#define OMAP1510_INT_FPGA12 (OMAP_FPGA_IRQ_BASE + 12) -#define OMAP1510_INT_ETHER (OMAP_FPGA_IRQ_BASE + 13) -#define OMAP1510_INT_FPGAUART1 (OMAP_FPGA_IRQ_BASE + 14) -#define OMAP1510_INT_FPGAUART2 (OMAP_FPGA_IRQ_BASE + 15) -#define OMAP1510_INT_FPGA_TS (OMAP_FPGA_IRQ_BASE + 16) -#define OMAP1510_INT_FPGA17 (OMAP_FPGA_IRQ_BASE + 17) -#define OMAP1510_INT_FPGA_CAM (OMAP_FPGA_IRQ_BASE + 18) -#define OMAP1510_INT_FPGA_RTC_A (OMAP_FPGA_IRQ_BASE + 19) -#define OMAP1510_INT_FPGA_RTC_B (OMAP_FPGA_IRQ_BASE + 20) -#define OMAP1510_INT_FPGA_CD (OMAP_FPGA_IRQ_BASE + 21) -#define OMAP1510_INT_FPGA22 (OMAP_FPGA_IRQ_BASE + 22) -#define OMAP1510_INT_FPGA23 (OMAP_FPGA_IRQ_BASE + 23) - -#endif /* __ASM_ARCH_OMAP15XX_H */ - diff --git a/arch/arm/mach-omap1/omap16xx.h b/arch/arm/mach-omap1/omap16xx.h deleted file mode 100644 index cd1c724869c7..000000000000 --- a/arch/arm/mach-omap1/omap16xx.h +++ /dev/null @@ -1,201 +0,0 @@ -/* - * Hardware definitions for TI OMAP1610/5912/1710 processors. - * - * Cleanup for Linux-2.6 by Dirk Behme - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __ASM_ARCH_OMAP16XX_H -#define __ASM_ARCH_OMAP16XX_H - -/* - * ---------------------------------------------------------------------------- - * Base addresses - * ---------------------------------------------------------------------------- - */ - -/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */ - -#define OMAP16XX_DSP_BASE 0xE0000000 -#define OMAP16XX_DSP_SIZE 0x28000 -#define OMAP16XX_DSP_START 0xE0000000 - -#define OMAP16XX_DSPREG_BASE 0xE1000000 -#define OMAP16XX_DSPREG_SIZE SZ_128K -#define OMAP16XX_DSPREG_START 0xE1000000 - -#define OMAP16XX_SEC_BASE 0xFFFE4000 -#define OMAP16XX_SEC_DES (OMAP16XX_SEC_BASE + 0x0000) -#define OMAP16XX_SEC_SHA1MD5 (OMAP16XX_SEC_BASE + 0x0800) -#define OMAP16XX_SEC_RNG (OMAP16XX_SEC_BASE + 0x1000) - -/* - * --------------------------------------------------------------------------- - * Interrupts - * --------------------------------------------------------------------------- - */ -#define OMAP_IH2_0_BASE (0xfffe0000) -#define OMAP_IH2_1_BASE (0xfffe0100) -#define OMAP_IH2_2_BASE (0xfffe0200) -#define OMAP_IH2_3_BASE (0xfffe0300) - -#define OMAP_IH2_0_ITR (OMAP_IH2_0_BASE + 0x00) -#define OMAP_IH2_0_MIR (OMAP_IH2_0_BASE + 0x04) -#define OMAP_IH2_0_SIR_IRQ (OMAP_IH2_0_BASE + 0x10) -#define OMAP_IH2_0_SIR_FIQ (OMAP_IH2_0_BASE + 0x14) -#define OMAP_IH2_0_CONTROL (OMAP_IH2_0_BASE + 0x18) -#define OMAP_IH2_0_ILR0 (OMAP_IH2_0_BASE + 0x1c) -#define OMAP_IH2_0_ISR (OMAP_IH2_0_BASE + 0x9c) - -#define OMAP_IH2_1_ITR (OMAP_IH2_1_BASE + 0x00) -#define OMAP_IH2_1_MIR (OMAP_IH2_1_BASE + 0x04) -#define OMAP_IH2_1_SIR_IRQ (OMAP_IH2_1_BASE + 0x10) -#define OMAP_IH2_1_SIR_FIQ (OMAP_IH2_1_BASE + 0x14) -#define OMAP_IH2_1_CONTROL (OMAP_IH2_1_BASE + 0x18) -#define OMAP_IH2_1_ILR1 (OMAP_IH2_1_BASE + 0x1c) -#define OMAP_IH2_1_ISR (OMAP_IH2_1_BASE + 0x9c) - -#define OMAP_IH2_2_ITR (OMAP_IH2_2_BASE + 0x00) -#define OMAP_IH2_2_MIR (OMAP_IH2_2_BASE + 0x04) -#define OMAP_IH2_2_SIR_IRQ (OMAP_IH2_2_BASE + 0x10) -#define OMAP_IH2_2_SIR_FIQ (OMAP_IH2_2_BASE + 0x14) -#define OMAP_IH2_2_CONTROL (OMAP_IH2_2_BASE + 0x18) -#define OMAP_IH2_2_ILR2 (OMAP_IH2_2_BASE + 0x1c) -#define OMAP_IH2_2_ISR (OMAP_IH2_2_BASE + 0x9c) - -#define OMAP_IH2_3_ITR (OMAP_IH2_3_BASE + 0x00) -#define OMAP_IH2_3_MIR (OMAP_IH2_3_BASE + 0x04) -#define OMAP_IH2_3_SIR_IRQ (OMAP_IH2_3_BASE + 0x10) -#define OMAP_IH2_3_SIR_FIQ (OMAP_IH2_3_BASE + 0x14) -#define OMAP_IH2_3_CONTROL (OMAP_IH2_3_BASE + 0x18) -#define OMAP_IH2_3_ILR3 (OMAP_IH2_3_BASE + 0x1c) -#define OMAP_IH2_3_ISR (OMAP_IH2_3_BASE + 0x9c) - -/* - * ---------------------------------------------------------------------------- - * Clocks - * ---------------------------------------------------------------------------- - */ -#define OMAP16XX_ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24) - -/* - * ---------------------------------------------------------------------------- - * Pin configuration registers - * ---------------------------------------------------------------------------- - */ -#define OMAP16XX_CONF_VOLTAGE_VDDSHV6 (1 << 8) -#define OMAP16XX_CONF_VOLTAGE_VDDSHV7 (1 << 9) -#define OMAP16XX_CONF_VOLTAGE_VDDSHV8 (1 << 10) -#define OMAP16XX_CONF_VOLTAGE_VDDSHV9 (1 << 11) -#define OMAP16XX_SUBLVDS_CONF_VALID (1 << 13) - -/* - * ---------------------------------------------------------------------------- - * System control registers - * ---------------------------------------------------------------------------- - */ -#define OMAP1610_RESET_CONTROL 0xfffe1140 - -/* - * --------------------------------------------------------------------------- - * TIPB bus interface - * --------------------------------------------------------------------------- - */ -#define TIPB_SWITCH_BASE (0xfffbc800) -#define OMAP16XX_MMCSD2_SSW_MPU_CONF (TIPB_SWITCH_BASE + 0x160) - -/* UART3 Registers Mapping through MPU bus */ -#define UART3_RHR (OMAP1_UART3_BASE + 0) -#define UART3_THR (OMAP1_UART3_BASE + 0) -#define UART3_DLL (OMAP1_UART3_BASE + 0) -#define UART3_IER (OMAP1_UART3_BASE + 4) -#define UART3_DLH (OMAP1_UART3_BASE + 4) -#define UART3_IIR (OMAP1_UART3_BASE + 8) -#define UART3_FCR (OMAP1_UART3_BASE + 8) -#define UART3_EFR (OMAP1_UART3_BASE + 8) -#define UART3_LCR (OMAP1_UART3_BASE + 0x0C) -#define UART3_MCR (OMAP1_UART3_BASE + 0x10) -#define UART3_XON1_ADDR1 (OMAP1_UART3_BASE + 0x10) -#define UART3_XON2_ADDR2 (OMAP1_UART3_BASE + 0x14) -#define UART3_LSR (OMAP1_UART3_BASE + 0x14) -#define UART3_TCR (OMAP1_UART3_BASE + 0x18) -#define UART3_MSR (OMAP1_UART3_BASE + 0x18) -#define UART3_XOFF1 (OMAP1_UART3_BASE + 0x18) -#define UART3_XOFF2 (OMAP1_UART3_BASE + 0x1C) -#define UART3_SPR (OMAP1_UART3_BASE + 0x1C) -#define UART3_TLR (OMAP1_UART3_BASE + 0x1C) -#define UART3_MDR1 (OMAP1_UART3_BASE + 0x20) -#define UART3_MDR2 (OMAP1_UART3_BASE + 0x24) -#define UART3_SFLSR (OMAP1_UART3_BASE + 0x28) -#define UART3_TXFLL (OMAP1_UART3_BASE + 0x28) -#define UART3_RESUME (OMAP1_UART3_BASE + 0x2C) -#define UART3_TXFLH (OMAP1_UART3_BASE + 0x2C) -#define UART3_SFREGL (OMAP1_UART3_BASE + 0x30) -#define UART3_RXFLL (OMAP1_UART3_BASE + 0x30) -#define UART3_SFREGH (OMAP1_UART3_BASE + 0x34) -#define UART3_RXFLH (OMAP1_UART3_BASE + 0x34) -#define UART3_BLR (OMAP1_UART3_BASE + 0x38) -#define UART3_ACREG (OMAP1_UART3_BASE + 0x3C) -#define UART3_DIV16 (OMAP1_UART3_BASE + 0x3C) -#define UART3_SCR (OMAP1_UART3_BASE + 0x40) -#define UART3_SSR (OMAP1_UART3_BASE + 0x44) -#define UART3_EBLR (OMAP1_UART3_BASE + 0x48) -#define UART3_OSC_12M_SEL (OMAP1_UART3_BASE + 0x4C) -#define UART3_MVR (OMAP1_UART3_BASE + 0x50) - -/* - * --------------------------------------------------------------------------- - * Watchdog timer - * --------------------------------------------------------------------------- - */ - -/* 32-bit Watchdog timer in OMAP 16XX */ -#define OMAP_16XX_WATCHDOG_BASE (0xfffeb000) -#define OMAP_16XX_WIDR (OMAP_16XX_WATCHDOG_BASE + 0x00) -#define OMAP_16XX_WD_SYSCONFIG (OMAP_16XX_WATCHDOG_BASE + 0x10) -#define OMAP_16XX_WD_SYSSTATUS (OMAP_16XX_WATCHDOG_BASE + 0x14) -#define OMAP_16XX_WCLR (OMAP_16XX_WATCHDOG_BASE + 0x24) -#define OMAP_16XX_WCRR (OMAP_16XX_WATCHDOG_BASE + 0x28) -#define OMAP_16XX_WLDR (OMAP_16XX_WATCHDOG_BASE + 0x2c) -#define OMAP_16XX_WTGR (OMAP_16XX_WATCHDOG_BASE + 0x30) -#define OMAP_16XX_WWPS (OMAP_16XX_WATCHDOG_BASE + 0x34) -#define OMAP_16XX_WSPR (OMAP_16XX_WATCHDOG_BASE + 0x48) - -#define WCLR_PRE_SHIFT 5 -#define WCLR_PTV_SHIFT 2 - -#define WWPS_W_PEND_WSPR (1 << 4) -#define WWPS_W_PEND_WTGR (1 << 3) -#define WWPS_W_PEND_WLDR (1 << 2) -#define WWPS_W_PEND_WCRR (1 << 1) -#define WWPS_W_PEND_WCLR (1 << 0) - -#define WSPR_ENABLE_0 (0x0000bbbb) -#define WSPR_ENABLE_1 (0x00004444) -#define WSPR_DISABLE_0 (0x0000aaaa) -#define WSPR_DISABLE_1 (0x00005555) - -#define OMAP16XX_DSP_MMU_BASE (0xfffed200) -#define OMAP16XX_MAILBOX_BASE (0xfffcf000) - -#endif /* __ASM_ARCH_OMAP16XX_H */ - diff --git a/arch/arm/mach-omap1/omap7xx.h b/arch/arm/mach-omap1/omap7xx.h deleted file mode 100644 index 63da994bc609..000000000000 --- a/arch/arm/mach-omap1/omap7xx.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - * Hardware definitions for TI OMAP7XX processor. - * - * Cleanup for Linux-2.6 by Dirk Behme - * Adapted for omap850 by Zebediah C. McClure - * Adapted for omap7xx by Alistair Buxton - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __ASM_ARCH_OMAP7XX_H -#define __ASM_ARCH_OMAP7XX_H - -/* - * ---------------------------------------------------------------------------- - * Base addresses - * ---------------------------------------------------------------------------- - */ - -/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */ - -#define OMAP7XX_DSP_BASE 0xE0000000 -#define OMAP7XX_DSP_SIZE 0x50000 -#define OMAP7XX_DSP_START 0xE0000000 - -#define OMAP7XX_DSPREG_BASE 0xE1000000 -#define OMAP7XX_DSPREG_SIZE SZ_128K -#define OMAP7XX_DSPREG_START 0xE1000000 - -#define OMAP7XX_SPI1_BASE 0xfffc0800 -#define OMAP7XX_SPI2_BASE 0xfffc1000 - -/* - * ---------------------------------------------------------------------------- - * OMAP7XX specific configuration registers - * ---------------------------------------------------------------------------- - */ -#define OMAP7XX_CONFIG_BASE 0xfffe1000 -#define OMAP7XX_IO_CONF_0 0xfffe1070 -#define OMAP7XX_IO_CONF_1 0xfffe1074 -#define OMAP7XX_IO_CONF_2 0xfffe1078 -#define OMAP7XX_IO_CONF_3 0xfffe107c -#define OMAP7XX_IO_CONF_4 0xfffe1080 -#define OMAP7XX_IO_CONF_5 0xfffe1084 -#define OMAP7XX_IO_CONF_6 0xfffe1088 -#define OMAP7XX_IO_CONF_7 0xfffe108c -#define OMAP7XX_IO_CONF_8 0xfffe1090 -#define OMAP7XX_IO_CONF_9 0xfffe1094 -#define OMAP7XX_IO_CONF_10 0xfffe1098 -#define OMAP7XX_IO_CONF_11 0xfffe109c -#define OMAP7XX_IO_CONF_12 0xfffe10a0 -#define OMAP7XX_IO_CONF_13 0xfffe10a4 - -#define OMAP7XX_MODE_1 0xfffe1010 -#define OMAP7XX_MODE_2 0xfffe1014 - -/* CSMI specials: in terms of base + offset */ -#define OMAP7XX_MODE2_OFFSET 0x14 - -/* - * ---------------------------------------------------------------------------- - * OMAP7XX traffic controller configuration registers - * ---------------------------------------------------------------------------- - */ -#define OMAP7XX_FLASH_CFG_0 0xfffecc10 -#define OMAP7XX_FLASH_ACFG_0 0xfffecc50 -#define OMAP7XX_FLASH_CFG_1 0xfffecc14 -#define OMAP7XX_FLASH_ACFG_1 0xfffecc54 - -/* - * ---------------------------------------------------------------------------- - * OMAP7XX DSP control registers - * ---------------------------------------------------------------------------- - */ -#define OMAP7XX_ICR_BASE 0xfffbb800 -#define OMAP7XX_DSP_M_CTL 0xfffbb804 -#define OMAP7XX_DSP_MMU_BASE 0xfffed200 - -/* - * ---------------------------------------------------------------------------- - * OMAP7XX PCC_UPLD configuration registers - * ---------------------------------------------------------------------------- - */ -#define OMAP7XX_PCC_UPLD_CTRL_BASE (0xfffe0900) -#define OMAP7XX_PCC_UPLD_CTRL (OMAP7XX_PCC_UPLD_CTRL_BASE + 0x00) - -#endif /* __ASM_ARCH_OMAP7XX_H */ - -- cgit From 2af4fcc0d3574482c73c34274eea63bac5518d48 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 29 Sep 2022 15:38:29 +0200 Subject: ARM: davinci: remove unused board support All Kconfig entries marked as "depends on UNUSED_BOARD_FILES" and their direct dependencies are removed here as planned. Acked-by: Bartosz Golaszewski Signed-off-by: Arnd Bergmann --- arch/arm/Kconfig.debug | 16 +- arch/arm/mach-davinci/Kconfig | 130 +-- arch/arm/mach-davinci/Makefile | 9 - arch/arm/mach-davinci/board-da830-evm.c | 690 ------------ arch/arm/mach-davinci/board-da850-evm.c | 1550 --------------------------- arch/arm/mach-davinci/board-dm355-evm.c | 444 -------- arch/arm/mach-davinci/board-dm355-leopard.c | 278 ----- arch/arm/mach-davinci/board-dm365-evm.c | 855 --------------- arch/arm/mach-davinci/board-mityomapl138.c | 638 ----------- arch/arm/mach-davinci/board-omapl138-hawk.c | 451 -------- arch/arm/mach-davinci/devices.c | 303 ------ arch/arm/mach-davinci/dm355.c | 832 -------------- arch/arm/mach-davinci/dm365.c | 1094 ------------------- 13 files changed, 5 insertions(+), 7285 deletions(-) delete mode 100644 arch/arm/mach-davinci/board-da830-evm.c delete mode 100644 arch/arm/mach-davinci/board-da850-evm.c delete mode 100644 arch/arm/mach-davinci/board-dm355-evm.c delete mode 100644 arch/arm/mach-davinci/board-dm355-leopard.c delete mode 100644 arch/arm/mach-davinci/board-dm365-evm.c delete mode 100644 arch/arm/mach-davinci/board-mityomapl138.c delete mode 100644 arch/arm/mach-davinci/board-omapl138-hawk.c delete mode 100644 arch/arm/mach-davinci/devices.c delete mode 100644 arch/arm/mach-davinci/dm355.c delete mode 100644 arch/arm/mach-davinci/dm365.c (limited to 'arch/arm') diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index c03fd448c59e..20312792340d 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -323,14 +323,6 @@ choice Say Y here if you want the debug print routines to direct their output to UART2 serial port on DaVinci DA8XX devices. - config DEBUG_DAVINCI_DMx_UART0 - bool "Kernel low-level debugging on DaVinci DMx using UART0" - depends on ARCH_DAVINCI_DMx - select DEBUG_UART_8250 - help - Say Y here if you want the debug print routines to direct - their output to UART0 serial port on DaVinci DMx devices. - config DEBUG_DC21285_PORT bool "Kernel low-level debugging messages via footbridge serial port" depends on FOOTBRIDGE @@ -1590,7 +1582,6 @@ config DEBUG_UART_8250 config DEBUG_UART_PHYS hex "Physical base address of debug UART" - default 0x01c20000 if DEBUG_DAVINCI_DMx_UART0 default 0x01c28000 if DEBUG_SUNXI_UART0 default 0x01c28400 if DEBUG_SUNXI_UART1 default 0x01d0c000 if DEBUG_DAVINCI_DA8XX_UART1 @@ -1810,7 +1801,6 @@ config DEBUG_UART_VIRT default 0xfec03000 if DEBUG_SOCFPGA_CYCLONE5_UART1 default 0xfec12000 if DEBUG_MVEBU_UART0 || DEBUG_MVEBU_UART0_ALTERNATE default 0xfec12100 if DEBUG_MVEBU_UART1_ALTERNATE - default 0xfec20000 if DEBUG_DAVINCI_DMx_UART0 default 0xfec90000 if DEBUG_RK32_UART2 default 0xfed0c000 if DEBUG_DAVINCI_DA8XX_UART1 default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_SD5203_UART @@ -1854,9 +1844,9 @@ config DEBUG_UART_8250_WORD default y if DEBUG_SOCFPGA_UART0 || DEBUG_SOCFPGA_ARRIA10_UART1 || \ DEBUG_SOCFPGA_CYCLONE5_UART1 || DEBUG_KEYSTONE_UART0 || \ DEBUG_KEYSTONE_UART1 || DEBUG_ALPINE_UART0 || \ - DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \ - DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_BCM_IPROC_UART3 || \ - DEBUG_BCM_KONA_UART || DEBUG_RK32_UART2 + DEBUG_DAVINCI_DA8XX_UART1 || DEBUG_DAVINCI_DA8XX_UART2 || \ + DEBUG_BCM_IPROC_UART3 || DEBUG_BCM_KONA_UART || \ + DEBUG_RK32_UART2 config DEBUG_UART_8250_PALMCHIP bool "8250 UART is Palmchip BK-310x" diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index c8cbd9a30791..588213583051 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -14,20 +14,11 @@ menuconfig ARCH_DAVINCI if ARCH_DAVINCI -config ARCH_DAVINCI_DMx - bool - comment "DaVinci Core Type" -config ARCH_DAVINCI_DM355 - bool "DaVinci 355 based system" - depends on ATAGS && UNUSED_BOARD_FILES - select DAVINCI_AINTC - select ARCH_DAVINCI_DMx - config ARCH_DAVINCI_DA830 bool "DA830/OMAP-L137/AM17x based system" - depends on !ARCH_DAVINCI_DMx || (AUTO_ZRELADDR && ARM_PATCH_PHYS_VIRT) + depends on AUTO_ZRELADDR && ARM_PATCH_PHYS_VIRT depends on ATAGS select ARCH_DAVINCI_DA8XX # needed on silicon revs 1.0, 1.1: @@ -36,7 +27,7 @@ config ARCH_DAVINCI_DA830 config ARCH_DAVINCI_DA850 bool "DA850/OMAP-L138/AM18x based system" - depends on !ARCH_DAVINCI_DMx || (AUTO_ZRELADDR && ARM_PATCH_PHYS_VIRT) + depends on AUTO_ZRELADDR && ARM_PATCH_PHYS_VIRT depends on ATAGS select ARCH_DAVINCI_DA8XX select DAVINCI_CP_INTC @@ -44,12 +35,6 @@ config ARCH_DAVINCI_DA850 config ARCH_DAVINCI_DA8XX bool -config ARCH_DAVINCI_DM365 - bool "DaVinci 365 based system" - depends on ATAGS && UNUSED_BOARD_FILES - select DAVINCI_AINTC - select ARCH_DAVINCI_DMx - comment "DaVinci Board Type" config MACH_DA8XX_DT @@ -61,117 +46,6 @@ config MACH_DA8XX_DT Say y here to include support for TI DaVinci DA850 based using Flattened Device Tree. More information at Documentation/devicetree -config MACH_DAVINCI_DM355_EVM - bool "TI DM355 EVM" - default ARCH_DAVINCI_DM355 - depends on ARCH_DAVINCI_DM355 - help - Configure this option to specify the whether the board used - for development is a DM355 EVM - -config MACH_DM355_LEOPARD - bool "DM355 Leopard board" - depends on ARCH_DAVINCI_DM355 - help - Configure this option to specify the whether the board used - for development is a DM355 Leopard board. - -config MACH_DAVINCI_DM365_EVM - bool "TI DM365 EVM" - default ARCH_DAVINCI_DM365 - depends on ARCH_DAVINCI_DM365 - help - Configure this option to specify whether the board used - for development is a DM365 EVM - -config MACH_DAVINCI_DA830_EVM - bool "TI DA830/OMAP-L137/AM17x Reference Platform" - default ARCH_DAVINCI_DA830 - depends on ATAGS && UNUSED_BOARD_FILES - depends on ARCH_DAVINCI_DA830 - select GPIO_PCF857X if I2C - help - Say Y here to select the TI DA830/OMAP-L137/AM17x Evaluation Module. - -choice - prompt "Select DA830/OMAP-L137/AM17x UI board peripheral" - depends on MACH_DAVINCI_DA830_EVM - help - The presence of UI card on the DA830/OMAP-L137/AM17x EVM is - detected automatically based on successful probe of the I2C - based GPIO expander on that board. This option selected in this - menu has an effect only in case of a successful UI card detection. - -config DA830_UI_LCD - bool "LCD" - help - Say Y here to use the LCD as a framebuffer or simple character - display. - -config DA830_UI_NAND - bool "NAND flash" - help - Say Y here to use the NAND flash. Do not forget to setup - the switch correctly. -endchoice - -config MACH_DAVINCI_DA850_EVM - bool "TI DA850/OMAP-L138/AM18x Reference Platform" - depends on ATAGS && UNUSED_BOARD_FILES - default ARCH_DAVINCI_DA850 - depends on ARCH_DAVINCI_DA850 - help - Say Y here to select the TI DA850/OMAP-L138/AM18x Evaluation Module. - -choice - prompt "Select peripherals connected to expander on UI board" - depends on MACH_DAVINCI_DA850_EVM - help - The presence of User Interface (UI) card on the DA850/OMAP-L138/AM18x - EVM is detected automatically based on successful probe of the I2C - based GPIO expander on that card. This option selected in this - menu has an effect only in case of a successful UI card detection. - -config DA850_UI_NONE - bool "No peripheral is enabled" - help - Say Y if you do not want to enable any of the peripherals connected - to TCA6416 expander on DA850/OMAP-L138/AM18x EVM UI card - -config DA850_UI_RMII - bool "RMII Ethernet PHY" - help - Say Y if you want to use the RMII PHY on the DA850/OMAP-L138/AM18x - EVM. This PHY is found on the UI daughter card that is supplied with - the EVM. - NOTE: Please take care while choosing this option, MII PHY will - not be functional if RMII mode is selected. - -config DA850_UI_SD_VIDEO_PORT - bool "Video Port Interface" - help - Say Y if you want to use Video Port Interface (VPIF) on the - DA850/OMAP-L138 EVM. The Video decoders/encoders are found on the - UI daughter card that is supplied with the EVM. - -endchoice - -config MACH_MITYOMAPL138 - bool "Critical Link MityDSP-L138/MityARM-1808 SoM" - depends on ARCH_DAVINCI_DA850 - depends on ATAGS && UNUSED_BOARD_FILES - help - Say Y here to select the Critical Link MityDSP-L138/MityARM-1808 - System on Module. Information on this SoM may be found at - https://www.mitydsp.com - -config MACH_OMAPL138_HAWKBOARD - bool "TI AM1808 / OMAPL-138 Hawkboard platform" - depends on ARCH_DAVINCI_DA850 - depends on ATAGS && UNUSED_BOARD_FILES - help - Say Y here to select the TI AM1808 / OMAPL-138 Hawkboard platform . - config DAVINCI_MUX bool "DAVINCI multiplexing support" depends on ARCH_DAVINCI diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index 3f4894aa7528..5b15a3bbf909 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -10,20 +10,11 @@ obj-y := serial.o usb.o common.o sram.o obj-$(CONFIG_DAVINCI_MUX) += mux.o # Chip specific -obj-$(CONFIG_ARCH_DAVINCI_DM355) += dm355.o devices.o -obj-$(CONFIG_ARCH_DAVINCI_DM365) += dm365.o devices.o obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o devices-da8xx.o usb-da8xx.o obj-$(CONFIG_ARCH_DAVINCI_DA850) += da850.o devices-da8xx.o usb-da8xx.o # Board specific obj-$(CONFIG_MACH_DA8XX_DT) += da8xx-dt.o pdata-quirks.o -obj-$(CONFIG_MACH_DAVINCI_DM355_EVM) += board-dm355-evm.o -obj-$(CONFIG_MACH_DM355_LEOPARD) += board-dm355-leopard.o -obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o -obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o -obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o -obj-$(CONFIG_MACH_MITYOMAPL138) += board-mityomapl138.o -obj-$(CONFIG_MACH_OMAPL138_HAWKBOARD) += board-omapl138-hawk.o # Power Management obj-$(CONFIG_CPU_IDLE) += cpuidle.o diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c deleted file mode 100644 index 6299e5c8f4ea..000000000000 --- a/arch/arm/mach-davinci/board-da830-evm.c +++ /dev/null @@ -1,690 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * TI DA830/OMAP L137 EVM board - * - * Author: Mark A. Greer - * Derived from: arch/arm/mach-davinci/board-dm644x-evm.c - * - * 2007, 2009 (c) MontaVista Software, Inc. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "common.h" -#include "mux.h" -#include "da8xx.h" -#include "irqs.h" - -#define DA830_EVM_PHY_ID "" -/* - * USB1 VBUS is controlled by GPIO1[15], over-current is reported on GPIO2[4]. - */ -#define ON_BD_USB_DRV GPIO_TO_PIN(1, 15) -#define ON_BD_USB_OVC GPIO_TO_PIN(2, 4) - -static const short da830_evm_usb11_pins[] = { - DA830_GPIO1_15, DA830_GPIO2_4, - -1 -}; - -static struct regulator_consumer_supply da830_evm_usb_supplies[] = { - REGULATOR_SUPPLY("vbus", NULL), -}; - -static struct regulator_init_data da830_evm_usb_vbus_data = { - .consumer_supplies = da830_evm_usb_supplies, - .num_consumer_supplies = ARRAY_SIZE(da830_evm_usb_supplies), - .constraints = { - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, -}; - -static struct fixed_voltage_config da830_evm_usb_vbus = { - .supply_name = "vbus", - .microvolts = 33000000, - .init_data = &da830_evm_usb_vbus_data, -}; - -static struct platform_device da830_evm_usb_vbus_device = { - .name = "reg-fixed-voltage", - .id = 0, - .dev = { - .platform_data = &da830_evm_usb_vbus, - }, -}; - -static struct gpiod_lookup_table da830_evm_usb_oc_gpio_lookup = { - .dev_id = "ohci-da8xx", - .table = { - GPIO_LOOKUP("davinci_gpio", ON_BD_USB_OVC, "oc", 0), - { } - }, -}; - -static struct gpiod_lookup_table da830_evm_usb_vbus_gpio_lookup = { - .dev_id = "reg-fixed-voltage.0", - .table = { - GPIO_LOOKUP("davinci_gpio", ON_BD_USB_DRV, NULL, 0), - { } - }, -}; - -static struct gpiod_lookup_table *da830_evm_usb_gpio_lookups[] = { - &da830_evm_usb_oc_gpio_lookup, - &da830_evm_usb_vbus_gpio_lookup, -}; - -static struct da8xx_ohci_root_hub da830_evm_usb11_pdata = { - /* TPS2065 switch @ 5V */ - .potpgt = (3 + 1) / 2, /* 3 ms max */ -}; - -static __init void da830_evm_usb_init(void) -{ - int ret; - - ret = da8xx_register_usb_phy_clocks(); - if (ret) - pr_warn("%s: USB PHY CLK registration failed: %d\n", - __func__, ret); - - gpiod_add_lookup_tables(da830_evm_usb_gpio_lookups, - ARRAY_SIZE(da830_evm_usb_gpio_lookups)); - - ret = da8xx_register_usb_phy(); - if (ret) - pr_warn("%s: USB PHY registration failed: %d\n", - __func__, ret); - - ret = davinci_cfg_reg(DA830_USB0_DRVVBUS); - if (ret) - pr_warn("%s: USB 2.0 PinMux setup failed: %d\n", __func__, ret); - else { - /* - * TPS2065 switch @ 5V supplies 1 A (sustains 1.5 A), - * with the power on to power good time of 3 ms. - */ - ret = da8xx_register_usb20(1000, 3); - if (ret) - pr_warn("%s: USB 2.0 registration failed: %d\n", - __func__, ret); - } - - ret = davinci_cfg_reg_list(da830_evm_usb11_pins); - if (ret) { - pr_warn("%s: USB 1.1 PinMux setup failed: %d\n", __func__, ret); - return; - } - - ret = platform_device_register(&da830_evm_usb_vbus_device); - if (ret) { - pr_warn("%s: Unable to register the vbus supply\n", __func__); - return; - } - - ret = da8xx_register_usb11(&da830_evm_usb11_pdata); - if (ret) - pr_warn("%s: USB 1.1 registration failed: %d\n", __func__, ret); -} - -static const short da830_evm_mcasp1_pins[] = { - DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1, DA830_AHCLKR1, DA830_AFSR1, - DA830_AMUTE1, DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_5, - DA830_ACLKR1, DA830_AXR1_6, DA830_AXR1_7, DA830_AXR1_8, DA830_AXR1_10, - DA830_AXR1_11, - -1 -}; - -static u8 da830_iis_serializer_direction[] = { - RX_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, - INACTIVE_MODE, TX_MODE, INACTIVE_MODE, INACTIVE_MODE, - INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, -}; - -static struct snd_platform_data da830_evm_snd_data = { - .tx_dma_offset = 0x2000, - .rx_dma_offset = 0x2000, - .op_mode = DAVINCI_MCASP_IIS_MODE, - .num_serializer = ARRAY_SIZE(da830_iis_serializer_direction), - .tdm_slots = 2, - .serial_dir = da830_iis_serializer_direction, - .asp_chan_q = EVENTQ_0, - .version = MCASP_VERSION_2, - .txnumevt = 1, - .rxnumevt = 1, -}; - -/* - * GPIO2[1] is used as MMC_SD_WP and GPIO2[2] as MMC_SD_INS. - */ -static const short da830_evm_mmc_sd_pins[] = { - DA830_MMCSD_DAT_0, DA830_MMCSD_DAT_1, DA830_MMCSD_DAT_2, - DA830_MMCSD_DAT_3, DA830_MMCSD_DAT_4, DA830_MMCSD_DAT_5, - DA830_MMCSD_DAT_6, DA830_MMCSD_DAT_7, DA830_MMCSD_CLK, - DA830_MMCSD_CMD, DA830_GPIO2_1, DA830_GPIO2_2, - -1 -}; - -#define DA830_MMCSD_WP_PIN GPIO_TO_PIN(2, 1) -#define DA830_MMCSD_CD_PIN GPIO_TO_PIN(2, 2) - -static struct gpiod_lookup_table mmc_gpios_table = { - .dev_id = "da830-mmc.0", - .table = { - /* gpio chip 1 contains gpio range 32-63 */ - GPIO_LOOKUP("davinci_gpio", DA830_MMCSD_CD_PIN, "cd", - GPIO_ACTIVE_LOW), - GPIO_LOOKUP("davinci_gpio", DA830_MMCSD_WP_PIN, "wp", - GPIO_ACTIVE_LOW), - { } - }, -}; - -static struct davinci_mmc_config da830_evm_mmc_config = { - .wires = 8, - .max_freq = 50000000, - .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, -}; - -static inline void da830_evm_init_mmc(void) -{ - int ret; - - ret = davinci_cfg_reg_list(da830_evm_mmc_sd_pins); - if (ret) { - pr_warn("%s: mmc/sd mux setup failed: %d\n", __func__, ret); - return; - } - - gpiod_add_lookup_table(&mmc_gpios_table); - - ret = da8xx_register_mmcsd0(&da830_evm_mmc_config); - if (ret) { - pr_warn("%s: mmc/sd registration failed: %d\n", __func__, ret); - gpiod_remove_lookup_table(&mmc_gpios_table); - } -} - -#define HAS_MMC IS_ENABLED(CONFIG_MMC_DAVINCI) - -#ifdef CONFIG_DA830_UI_NAND -static struct mtd_partition da830_evm_nand_partitions[] = { - /* bootloader (U-Boot, etc) in first sector */ - [0] = { - .name = "bootloader", - .offset = 0, - .size = SZ_128K, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - /* bootloader params in the next sector */ - [1] = { - .name = "params", - .offset = MTDPART_OFS_APPEND, - .size = SZ_128K, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - /* kernel */ - [2] = { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_2M, - .mask_flags = 0, - }, - /* file system */ - [3] = { - .name = "filesystem", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0, - } -}; - -/* flash bbt descriptors */ -static uint8_t da830_evm_nand_bbt_pattern[] = { 'B', 'b', 't', '0' }; -static uint8_t da830_evm_nand_mirror_pattern[] = { '1', 't', 'b', 'B' }; - -static struct nand_bbt_descr da830_evm_nand_bbt_main_descr = { - .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | - NAND_BBT_WRITE | NAND_BBT_2BIT | - NAND_BBT_VERSION | NAND_BBT_PERCHIP, - .offs = 2, - .len = 4, - .veroffs = 16, - .maxblocks = 4, - .pattern = da830_evm_nand_bbt_pattern -}; - -static struct nand_bbt_descr da830_evm_nand_bbt_mirror_descr = { - .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | - NAND_BBT_WRITE | NAND_BBT_2BIT | - NAND_BBT_VERSION | NAND_BBT_PERCHIP, - .offs = 2, - .len = 4, - .veroffs = 16, - .maxblocks = 4, - .pattern = da830_evm_nand_mirror_pattern -}; - -static struct davinci_aemif_timing da830_evm_nandflash_timing = { - .wsetup = 24, - .wstrobe = 21, - .whold = 14, - .rsetup = 19, - .rstrobe = 50, - .rhold = 0, - .ta = 20, -}; - -static struct davinci_nand_pdata da830_evm_nand_pdata = { - .core_chipsel = 1, - .parts = da830_evm_nand_partitions, - .nr_parts = ARRAY_SIZE(da830_evm_nand_partitions), - .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST, - .ecc_bits = 4, - .bbt_options = NAND_BBT_USE_FLASH, - .bbt_td = &da830_evm_nand_bbt_main_descr, - .bbt_md = &da830_evm_nand_bbt_mirror_descr, - .timing = &da830_evm_nandflash_timing, -}; - -static struct resource da830_evm_nand_resources[] = { - [0] = { /* First memory resource is NAND I/O window */ - .start = DA8XX_AEMIF_CS3_BASE, - .end = DA8XX_AEMIF_CS3_BASE + PAGE_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { /* Second memory resource is AEMIF control registers */ - .start = DA8XX_AEMIF_CTL_BASE, - .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device da830_evm_aemif_devices[] = { - { - .name = "davinci_nand", - .id = 1, - .dev = { - .platform_data = &da830_evm_nand_pdata, - }, - .num_resources = ARRAY_SIZE(da830_evm_nand_resources), - .resource = da830_evm_nand_resources, - }, -}; - -static struct resource da830_evm_aemif_resource[] = { - { - .start = DA8XX_AEMIF_CTL_BASE, - .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct aemif_abus_data da830_evm_aemif_abus_data[] = { - { - .cs = 3, - }, -}; - -static struct aemif_platform_data da830_evm_aemif_pdata = { - .abus_data = da830_evm_aemif_abus_data, - .num_abus_data = ARRAY_SIZE(da830_evm_aemif_abus_data), - .sub_devices = da830_evm_aemif_devices, - .num_sub_devices = ARRAY_SIZE(da830_evm_aemif_devices), - .cs_offset = 2, -}; - -static struct platform_device da830_evm_aemif_device = { - .name = "ti-aemif", - .id = -1, - .dev = { - .platform_data = &da830_evm_aemif_pdata, - }, - .resource = da830_evm_aemif_resource, - .num_resources = ARRAY_SIZE(da830_evm_aemif_resource), -}; - -/* - * UI board NAND/NOR flashes only use 8-bit data bus. - */ -static const short da830_evm_emif25_pins[] = { - DA830_EMA_D_0, DA830_EMA_D_1, DA830_EMA_D_2, DA830_EMA_D_3, - DA830_EMA_D_4, DA830_EMA_D_5, DA830_EMA_D_6, DA830_EMA_D_7, - DA830_EMA_A_0, DA830_EMA_A_1, DA830_EMA_A_2, DA830_EMA_A_3, - DA830_EMA_A_4, DA830_EMA_A_5, DA830_EMA_A_6, DA830_EMA_A_7, - DA830_EMA_A_8, DA830_EMA_A_9, DA830_EMA_A_10, DA830_EMA_A_11, - DA830_EMA_A_12, DA830_EMA_BA_0, DA830_EMA_BA_1, DA830_NEMA_WE, - DA830_NEMA_CS_2, DA830_NEMA_CS_3, DA830_NEMA_OE, DA830_EMA_WAIT_0, - -1 -}; - -static inline void da830_evm_init_nand(int mux_mode) -{ - int ret; - - if (HAS_MMC) { - pr_warn("WARNING: both MMC/SD and NAND are enabled, but they share AEMIF pins\n" - "\tDisable MMC/SD for NAND support\n"); - return; - } - - ret = davinci_cfg_reg_list(da830_evm_emif25_pins); - if (ret) - pr_warn("%s: emif25 mux setup failed: %d\n", __func__, ret); - - ret = platform_device_register(&da830_evm_aemif_device); - if (ret) - pr_warn("%s: AEMIF device not registered\n", __func__); - - gpio_direction_output(mux_mode, 1); -} -#else -static inline void da830_evm_init_nand(int mux_mode) { } -#endif - -#ifdef CONFIG_DA830_UI_LCD -static inline void da830_evm_init_lcdc(int mux_mode) -{ - int ret; - - ret = davinci_cfg_reg_list(da830_lcdcntl_pins); - if (ret) - pr_warn("%s: lcdcntl mux setup failed: %d\n", __func__, ret); - - ret = da8xx_register_lcdc(&sharp_lcd035q3dg01_pdata); - if (ret) - pr_warn("%s: lcd setup failed: %d\n", __func__, ret); - - gpio_direction_output(mux_mode, 0); -} -#else -static inline void da830_evm_init_lcdc(int mux_mode) { } -#endif - -static struct nvmem_cell_info da830_evm_nvmem_cells[] = { - { - .name = "macaddr", - .offset = 0x7f00, - .bytes = ETH_ALEN, - } -}; - -static struct nvmem_cell_table da830_evm_nvmem_cell_table = { - .nvmem_name = "1-00500", - .cells = da830_evm_nvmem_cells, - .ncells = ARRAY_SIZE(da830_evm_nvmem_cells), -}; - -static struct nvmem_cell_lookup da830_evm_nvmem_cell_lookup = { - .nvmem_name = "1-00500", - .cell_name = "macaddr", - .dev_id = "davinci_emac.1", - .con_id = "mac-address", -}; - -static const struct property_entry da830_evm_i2c_eeprom_properties[] = { - PROPERTY_ENTRY_U32("pagesize", 64), - { } -}; - -static const struct software_node da830_evm_i2c_eeprom_node = { - .properties = da830_evm_i2c_eeprom_properties, -}; - -static int __init da830_evm_ui_expander_setup(struct i2c_client *client, - int gpio, unsigned ngpio, void *context) -{ - gpio_request(gpio + 6, "UI MUX_MODE"); - - /* Drive mux mode low to match the default without UI card */ - gpio_direction_output(gpio + 6, 0); - - da830_evm_init_lcdc(gpio + 6); - - da830_evm_init_nand(gpio + 6); - - return 0; -} - -static void da830_evm_ui_expander_teardown(struct i2c_client *client, int gpio, - unsigned ngpio, void *context) -{ - gpio_free(gpio + 6); -} - -static struct pcf857x_platform_data __initdata da830_evm_ui_expander_info = { - .gpio_base = DAVINCI_N_GPIO, - .setup = da830_evm_ui_expander_setup, - .teardown = da830_evm_ui_expander_teardown, -}; - -static struct i2c_board_info __initdata da830_evm_i2c_devices[] = { - { - I2C_BOARD_INFO("24c256", 0x50), - .swnode = &da830_evm_i2c_eeprom_node, - }, - { - I2C_BOARD_INFO("tlv320aic3x", 0x18), - }, - { - I2C_BOARD_INFO("pcf8574", 0x3f), - .platform_data = &da830_evm_ui_expander_info, - }, -}; - -static struct davinci_i2c_platform_data da830_evm_i2c_0_pdata = { - .bus_freq = 100, /* kHz */ - .bus_delay = 0, /* usec */ -}; - -/* - * The following EDMA channels/slots are not being used by drivers (for - * example: Timer, GPIO, UART events etc) on da830/omap-l137 EVM, hence - * they are being reserved for codecs on the DSP side. - */ -static const s16 da830_dma_rsv_chans[][2] = { - /* (offset, number) */ - { 8, 2}, - {12, 2}, - {24, 4}, - {30, 2}, - {-1, -1} -}; - -static const s16 da830_dma_rsv_slots[][2] = { - /* (offset, number) */ - { 8, 2}, - {12, 2}, - {24, 4}, - {30, 26}, - {-1, -1} -}; - -static struct edma_rsv_info da830_edma_rsv[] = { - { - .rsv_chans = da830_dma_rsv_chans, - .rsv_slots = da830_dma_rsv_slots, - }, -}; - -static struct mtd_partition da830evm_spiflash_part[] = { - [0] = { - .name = "DSP-UBL", - .offset = 0, - .size = SZ_8K, - .mask_flags = MTD_WRITEABLE, - }, - [1] = { - .name = "ARM-UBL", - .offset = MTDPART_OFS_APPEND, - .size = SZ_16K + SZ_8K, - .mask_flags = MTD_WRITEABLE, - }, - [2] = { - .name = "U-Boot", - .offset = MTDPART_OFS_APPEND, - .size = SZ_256K - SZ_32K, - .mask_flags = MTD_WRITEABLE, - }, - [3] = { - .name = "U-Boot-Environment", - .offset = MTDPART_OFS_APPEND, - .size = SZ_16K, - .mask_flags = 0, - }, - [4] = { - .name = "Kernel", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0, - }, -}; - -static struct flash_platform_data da830evm_spiflash_data = { - .name = "m25p80", - .parts = da830evm_spiflash_part, - .nr_parts = ARRAY_SIZE(da830evm_spiflash_part), - .type = "w25x32", -}; - -static struct davinci_spi_config da830evm_spiflash_cfg = { - .io_type = SPI_IO_TYPE_DMA, - .c2tdelay = 8, - .t2cdelay = 8, -}; - -static struct spi_board_info da830evm_spi_info[] = { - { - .modalias = "m25p80", - .platform_data = &da830evm_spiflash_data, - .controller_data = &da830evm_spiflash_cfg, - .mode = SPI_MODE_0, - .max_speed_hz = 30000000, - .bus_num = 0, - .chip_select = 0, - }, -}; - -static __init void da830_evm_init(void) -{ - struct davinci_soc_info *soc_info = &davinci_soc_info; - int ret; - - da830_register_clocks(); - - ret = da830_register_gpio(); - if (ret) - pr_warn("%s: GPIO init failed: %d\n", __func__, ret); - - ret = da830_register_edma(da830_edma_rsv); - if (ret) - pr_warn("%s: edma registration failed: %d\n", __func__, ret); - - ret = davinci_cfg_reg_list(da830_i2c0_pins); - if (ret) - pr_warn("%s: i2c0 mux setup failed: %d\n", __func__, ret); - - ret = da8xx_register_i2c(0, &da830_evm_i2c_0_pdata); - if (ret) - pr_warn("%s: i2c0 registration failed: %d\n", __func__, ret); - - da830_evm_usb_init(); - - soc_info->emac_pdata->rmii_en = 1; - soc_info->emac_pdata->phy_id = DA830_EVM_PHY_ID; - - ret = davinci_cfg_reg_list(da830_cpgmac_pins); - if (ret) - pr_warn("%s: cpgmac mux setup failed: %d\n", __func__, ret); - - ret = da8xx_register_emac(); - if (ret) - pr_warn("%s: emac registration failed: %d\n", __func__, ret); - - ret = da8xx_register_watchdog(); - if (ret) - pr_warn("%s: watchdog registration failed: %d\n", - __func__, ret); - - davinci_serial_init(da8xx_serial_device); - - nvmem_add_cell_table(&da830_evm_nvmem_cell_table); - nvmem_add_cell_lookups(&da830_evm_nvmem_cell_lookup, 1); - - i2c_register_board_info(1, da830_evm_i2c_devices, - ARRAY_SIZE(da830_evm_i2c_devices)); - - ret = davinci_cfg_reg_list(da830_evm_mcasp1_pins); - if (ret) - pr_warn("%s: mcasp1 mux setup failed: %d\n", __func__, ret); - - da8xx_register_mcasp(1, &da830_evm_snd_data); - - da830_evm_init_mmc(); - - ret = da8xx_register_rtc(); - if (ret) - pr_warn("%s: rtc setup failed: %d\n", __func__, ret); - - ret = spi_register_board_info(da830evm_spi_info, - ARRAY_SIZE(da830evm_spi_info)); - if (ret) - pr_warn("%s: spi info registration failed: %d\n", - __func__, ret); - - ret = da8xx_register_spi_bus(0, ARRAY_SIZE(da830evm_spi_info)); - if (ret) - pr_warn("%s: spi 0 registration failed: %d\n", __func__, ret); - - regulator_has_full_constraints(); -} - -#ifdef CONFIG_SERIAL_8250_CONSOLE -static int __init da830_evm_console_init(void) -{ - if (!machine_is_davinci_da830_evm()) - return 0; - - return add_preferred_console("ttyS", 2, "115200"); -} -console_initcall(da830_evm_console_init); -#endif - -static void __init da830_evm_map_io(void) -{ - da830_init(); -} - -MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137/AM17x EVM") - .atag_offset = 0x100, - .map_io = da830_evm_map_io, - .init_irq = da830_init_irq, - .init_time = da830_init_time, - .init_machine = da830_evm_init, - .init_late = davinci_init_late, - .dma_zone_size = SZ_128M, -MACHINE_END diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c deleted file mode 100644 index d752ee2b30ff..000000000000 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ /dev/null @@ -1,1550 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * TI DA850/OMAP-L138 EVM board - * - * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/ - * - * Derived from: arch/arm/mach-davinci/board-da830-evm.c - * Original Copyrights follow: - * - * 2007, 2009 (c) MontaVista Software, Inc. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "common.h" -#include "da8xx.h" -#include "mux.h" -#include "irqs.h" -#include "sram.h" - -#include -#include -#include - -#include -#include - -#define DA850_EVM_PHY_ID "davinci_mdio-0:00" -#define DA850_LCD_PWR_PIN GPIO_TO_PIN(2, 8) -#define DA850_LCD_BL_PIN GPIO_TO_PIN(2, 15) - -#define DA850_MII_MDIO_CLKEN_PIN GPIO_TO_PIN(2, 6) - -static struct mtd_partition da850evm_spiflash_part[] = { - [0] = { - .name = "UBL", - .offset = 0, - .size = SZ_64K, - .mask_flags = MTD_WRITEABLE, - }, - [1] = { - .name = "U-Boot", - .offset = MTDPART_OFS_APPEND, - .size = SZ_512K, - .mask_flags = MTD_WRITEABLE, - }, - [2] = { - .name = "U-Boot-Env", - .offset = MTDPART_OFS_APPEND, - .size = SZ_64K, - .mask_flags = MTD_WRITEABLE, - }, - [3] = { - .name = "Kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_2M + SZ_512K, - .mask_flags = 0, - }, - [4] = { - .name = "Filesystem", - .offset = MTDPART_OFS_APPEND, - .size = SZ_4M, - .mask_flags = 0, - }, - [5] = { - .name = "MAC-Address", - .offset = SZ_8M - SZ_64K, - .size = SZ_64K, - .mask_flags = MTD_WRITEABLE, - }, -}; - -static struct nvmem_cell_info da850evm_nvmem_cells[] = { - { - .name = "macaddr", - .offset = 0x0, - .bytes = ETH_ALEN, - } -}; - -static struct nvmem_cell_table da850evm_nvmem_cell_table = { - /* - * The nvmem name differs from the partition name because of the - * internal works of the nvmem framework. - */ - .nvmem_name = "MAC-Address0", - .cells = da850evm_nvmem_cells, - .ncells = ARRAY_SIZE(da850evm_nvmem_cells), -}; - -static struct nvmem_cell_lookup da850evm_nvmem_cell_lookup = { - .nvmem_name = "MAC-Address0", - .cell_name = "macaddr", - .dev_id = "davinci_emac.1", - .con_id = "mac-address", -}; - -static struct flash_platform_data da850evm_spiflash_data = { - .name = "m25p80", - .parts = da850evm_spiflash_part, - .nr_parts = ARRAY_SIZE(da850evm_spiflash_part), - .type = "m25p64", -}; - -static struct davinci_spi_config da850evm_spiflash_cfg = { - .io_type = SPI_IO_TYPE_DMA, - .c2tdelay = 8, - .t2cdelay = 8, -}; - -static struct spi_board_info da850evm_spi_info[] = { - { - .modalias = "m25p80", - .platform_data = &da850evm_spiflash_data, - .controller_data = &da850evm_spiflash_cfg, - .mode = SPI_MODE_0, - .max_speed_hz = 30000000, - .bus_num = 1, - .chip_select = 0, - }, -}; - -static struct mtd_partition da850_evm_norflash_partition[] = { - { - .name = "bootloaders + env", - .offset = 0, - .size = SZ_512K, - .mask_flags = MTD_WRITEABLE, - }, - { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_2M, - .mask_flags = 0, - }, - { - .name = "filesystem", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0, - }, -}; - -static struct physmap_flash_data da850_evm_norflash_data = { - .width = 2, - .parts = da850_evm_norflash_partition, - .nr_parts = ARRAY_SIZE(da850_evm_norflash_partition), -}; - -static struct resource da850_evm_norflash_resource[] = { - { - .start = DA8XX_AEMIF_CS2_BASE, - .end = DA8XX_AEMIF_CS2_BASE + SZ_32M - 1, - .flags = IORESOURCE_MEM, - }, -}; - -/* DA850/OMAP-L138 EVM includes a 512 MByte large-page NAND flash - * (128K blocks). It may be used instead of the (default) SPI flash - * to boot, using TI's tools to install the secondary boot loader - * (UBL) and U-Boot. - */ -static struct mtd_partition da850_evm_nandflash_partition[] = { - { - .name = "u-boot env", - .offset = 0, - .size = SZ_128K, - .mask_flags = MTD_WRITEABLE, - }, - { - .name = "UBL", - .offset = MTDPART_OFS_APPEND, - .size = SZ_128K, - .mask_flags = MTD_WRITEABLE, - }, - { - .name = "u-boot", - .offset = MTDPART_OFS_APPEND, - .size = 4 * SZ_128K, - .mask_flags = MTD_WRITEABLE, - }, - { - .name = "kernel", - .offset = 0x200000, - .size = SZ_2M, - .mask_flags = 0, - }, - { - .name = "filesystem", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0, - }, -}; - -static struct davinci_aemif_timing da850_evm_nandflash_timing = { - .wsetup = 24, - .wstrobe = 21, - .whold = 14, - .rsetup = 19, - .rstrobe = 50, - .rhold = 0, - .ta = 20, -}; - -static struct davinci_nand_pdata da850_evm_nandflash_data = { - .core_chipsel = 1, - .parts = da850_evm_nandflash_partition, - .nr_parts = ARRAY_SIZE(da850_evm_nandflash_partition), - .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST, - .ecc_bits = 4, - .bbt_options = NAND_BBT_USE_FLASH, - .timing = &da850_evm_nandflash_timing, -}; - -static struct resource da850_evm_nandflash_resource[] = { - { - .start = DA8XX_AEMIF_CS3_BASE, - .end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = DA8XX_AEMIF_CTL_BASE, - .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource da850_evm_aemif_resource[] = { - { - .start = DA8XX_AEMIF_CTL_BASE, - .end = DA8XX_AEMIF_CTL_BASE + SZ_32K, - .flags = IORESOURCE_MEM, - } -}; - -static struct aemif_abus_data da850_evm_aemif_abus_data[] = { - { - .cs = 3, - } -}; - -static struct platform_device da850_evm_aemif_devices[] = { - { - .name = "davinci_nand", - .id = 1, - .dev = { - .platform_data = &da850_evm_nandflash_data, - }, - .num_resources = ARRAY_SIZE(da850_evm_nandflash_resource), - .resource = da850_evm_nandflash_resource, - }, - { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &da850_evm_norflash_data, - }, - .num_resources = 1, - .resource = da850_evm_norflash_resource, - } -}; - -static struct aemif_platform_data da850_evm_aemif_pdata = { - .cs_offset = 2, - .abus_data = da850_evm_aemif_abus_data, - .num_abus_data = ARRAY_SIZE(da850_evm_aemif_abus_data), - .sub_devices = da850_evm_aemif_devices, - .num_sub_devices = ARRAY_SIZE(da850_evm_aemif_devices), -}; - -static struct platform_device da850_evm_aemif_device = { - .name = "ti-aemif", - .id = -1, - .dev = { - .platform_data = &da850_evm_aemif_pdata, - }, - .resource = da850_evm_aemif_resource, - .num_resources = ARRAY_SIZE(da850_evm_aemif_resource), -}; - -static const short da850_evm_nand_pins[] = { - DA850_EMA_D_0, DA850_EMA_D_1, DA850_EMA_D_2, DA850_EMA_D_3, - DA850_EMA_D_4, DA850_EMA_D_5, DA850_EMA_D_6, DA850_EMA_D_7, - DA850_EMA_A_1, DA850_EMA_A_2, DA850_NEMA_CS_3, DA850_NEMA_CS_4, - DA850_NEMA_WE, DA850_NEMA_OE, - -1 -}; - -static const short da850_evm_nor_pins[] = { - DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2, - DA850_NEMA_WE, DA850_NEMA_OE, DA850_EMA_D_0, DA850_EMA_D_1, - DA850_EMA_D_2, DA850_EMA_D_3, DA850_EMA_D_4, DA850_EMA_D_5, - DA850_EMA_D_6, DA850_EMA_D_7, DA850_EMA_D_8, DA850_EMA_D_9, - DA850_EMA_D_10, DA850_EMA_D_11, DA850_EMA_D_12, DA850_EMA_D_13, - DA850_EMA_D_14, DA850_EMA_D_15, DA850_EMA_A_0, DA850_EMA_A_1, - DA850_EMA_A_2, DA850_EMA_A_3, DA850_EMA_A_4, DA850_EMA_A_5, - DA850_EMA_A_6, DA850_EMA_A_7, DA850_EMA_A_8, DA850_EMA_A_9, - DA850_EMA_A_10, DA850_EMA_A_11, DA850_EMA_A_12, DA850_EMA_A_13, - DA850_EMA_A_14, DA850_EMA_A_15, DA850_EMA_A_16, DA850_EMA_A_17, - DA850_EMA_A_18, DA850_EMA_A_19, DA850_EMA_A_20, DA850_EMA_A_21, - DA850_EMA_A_22, DA850_EMA_A_23, - -1 -}; - -#define HAS_MMC IS_ENABLED(CONFIG_MMC_DAVINCI) - -static inline void da850_evm_setup_nor_nand(void) -{ - int ret = 0; - - if (!HAS_MMC) { - ret = davinci_cfg_reg_list(da850_evm_nand_pins); - if (ret) - pr_warn("%s: NAND mux setup failed: %d\n", - __func__, ret); - - ret = davinci_cfg_reg_list(da850_evm_nor_pins); - if (ret) - pr_warn("%s: NOR mux setup failed: %d\n", - __func__, ret); - - ret = platform_device_register(&da850_evm_aemif_device); - if (ret) - pr_warn("%s: registering aemif failed: %d\n", - __func__, ret); - } -} - -#ifdef CONFIG_DA850_UI_RMII -static inline void da850_evm_setup_emac_rmii(int rmii_sel) -{ - struct davinci_soc_info *soc_info = &davinci_soc_info; - - soc_info->emac_pdata->rmii_en = 1; - gpio_set_value_cansleep(rmii_sel, 0); -} -#else -static inline void da850_evm_setup_emac_rmii(int rmii_sel) { } -#endif - - -#define DA850_KEYS_DEBOUNCE_MS 10 -/* - * At 200ms polling interval it is possible to miss an - * event by tapping very lightly on the push button but most - * pushes do result in an event; longer intervals require the - * user to hold the button whereas shorter intervals require - * more CPU time for polling. - */ -#define DA850_GPIO_KEYS_POLL_MS 200 - -enum da850_evm_ui_exp_pins { - DA850_EVM_UI_EXP_SEL_C = 5, - DA850_EVM_UI_EXP_SEL_B, - DA850_EVM_UI_EXP_SEL_A, - DA850_EVM_UI_EXP_PB8, - DA850_EVM_UI_EXP_PB7, - DA850_EVM_UI_EXP_PB6, - DA850_EVM_UI_EXP_PB5, - DA850_EVM_UI_EXP_PB4, - DA850_EVM_UI_EXP_PB3, - DA850_EVM_UI_EXP_PB2, - DA850_EVM_UI_EXP_PB1, -}; - -static const char * const da850_evm_ui_exp[] = { - [DA850_EVM_UI_EXP_SEL_C] = "sel_c", - [DA850_EVM_UI_EXP_SEL_B] = "sel_b", - [DA850_EVM_UI_EXP_SEL_A] = "sel_a", - [DA850_EVM_UI_EXP_PB8] = "pb8", - [DA850_EVM_UI_EXP_PB7] = "pb7", - [DA850_EVM_UI_EXP_PB6] = "pb6", - [DA850_EVM_UI_EXP_PB5] = "pb5", - [DA850_EVM_UI_EXP_PB4] = "pb4", - [DA850_EVM_UI_EXP_PB3] = "pb3", - [DA850_EVM_UI_EXP_PB2] = "pb2", - [DA850_EVM_UI_EXP_PB1] = "pb1", -}; - -#define DA850_N_UI_PB 8 - -static struct gpio_keys_button da850_evm_ui_keys[] = { - [0 ... DA850_N_UI_PB - 1] = { - .type = EV_KEY, - .active_low = 1, - .wakeup = 0, - .debounce_interval = DA850_KEYS_DEBOUNCE_MS, - .code = -1, /* assigned at runtime */ - .gpio = -1, /* assigned at runtime */ - .desc = NULL, /* assigned at runtime */ - }, -}; - -static struct gpio_keys_platform_data da850_evm_ui_keys_pdata = { - .buttons = da850_evm_ui_keys, - .nbuttons = ARRAY_SIZE(da850_evm_ui_keys), - .poll_interval = DA850_GPIO_KEYS_POLL_MS, -}; - -static struct platform_device da850_evm_ui_keys_device = { - .name = "gpio-keys-polled", - .id = 0, - .dev = { - .platform_data = &da850_evm_ui_keys_pdata - }, -}; - -static void da850_evm_ui_keys_init(unsigned gpio) -{ - int i; - struct gpio_keys_button *button; - - for (i = 0; i < DA850_N_UI_PB; i++) { - button = &da850_evm_ui_keys[i]; - button->code = KEY_F8 - i; - button->desc = da850_evm_ui_exp[DA850_EVM_UI_EXP_PB8 + i]; - button->gpio = gpio + DA850_EVM_UI_EXP_PB8 + i; - } -} - -#ifdef CONFIG_DA850_UI_SD_VIDEO_PORT -static inline void da850_evm_setup_video_port(int video_sel) -{ - gpio_set_value_cansleep(video_sel, 0); -} -#else -static inline void da850_evm_setup_video_port(int video_sel) { } -#endif - -static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio, - unsigned ngpio, void *c) -{ - int sel_a, sel_b, sel_c, ret; - - sel_a = gpio + DA850_EVM_UI_EXP_SEL_A; - sel_b = gpio + DA850_EVM_UI_EXP_SEL_B; - sel_c = gpio + DA850_EVM_UI_EXP_SEL_C; - - ret = gpio_request(sel_a, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_A]); - if (ret) { - pr_warn("Cannot open UI expander pin %d\n", sel_a); - goto exp_setup_sela_fail; - } - - ret = gpio_request(sel_b, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_B]); - if (ret) { - pr_warn("Cannot open UI expander pin %d\n", sel_b); - goto exp_setup_selb_fail; - } - - ret = gpio_request(sel_c, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_C]); - if (ret) { - pr_warn("Cannot open UI expander pin %d\n", sel_c); - goto exp_setup_selc_fail; - } - - /* deselect all functionalities */ - gpio_direction_output(sel_a, 1); - gpio_direction_output(sel_b, 1); - gpio_direction_output(sel_c, 1); - - da850_evm_ui_keys_init(gpio); - ret = platform_device_register(&da850_evm_ui_keys_device); - if (ret) { - pr_warn("Could not register UI GPIO expander push-buttons"); - goto exp_setup_keys_fail; - } - - pr_info("DA850/OMAP-L138 EVM UI card detected\n"); - - da850_evm_setup_nor_nand(); - - da850_evm_setup_emac_rmii(sel_a); - - da850_evm_setup_video_port(sel_c); - - return 0; - -exp_setup_keys_fail: - gpio_free(sel_c); -exp_setup_selc_fail: - gpio_free(sel_b); -exp_setup_selb_fail: - gpio_free(sel_a); -exp_setup_sela_fail: - return ret; -} - -static void da850_evm_ui_expander_teardown(struct i2c_client *client, - unsigned gpio, unsigned ngpio, void *c) -{ - platform_device_unregister(&da850_evm_ui_keys_device); - - /* deselect all functionalities */ - gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_C, 1); - gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_B, 1); - gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_A, 1); - - gpio_free(gpio + DA850_EVM_UI_EXP_SEL_C); - gpio_free(gpio + DA850_EVM_UI_EXP_SEL_B); - gpio_free(gpio + DA850_EVM_UI_EXP_SEL_A); -} - -/* assign the baseboard expander's GPIOs after the UI board's */ -#define DA850_UI_EXPANDER_N_GPIOS ARRAY_SIZE(da850_evm_ui_exp) -#define DA850_BB_EXPANDER_GPIO_BASE (DAVINCI_N_GPIO + DA850_UI_EXPANDER_N_GPIOS) - -enum da850_evm_bb_exp_pins { - DA850_EVM_BB_EXP_DEEP_SLEEP_EN = 0, - DA850_EVM_BB_EXP_SW_RST, - DA850_EVM_BB_EXP_TP_23, - DA850_EVM_BB_EXP_TP_22, - DA850_EVM_BB_EXP_TP_21, - DA850_EVM_BB_EXP_USER_PB1, - DA850_EVM_BB_EXP_USER_LED2, - DA850_EVM_BB_EXP_USER_LED1, - DA850_EVM_BB_EXP_USER_SW1, - DA850_EVM_BB_EXP_USER_SW2, - DA850_EVM_BB_EXP_USER_SW3, - DA850_EVM_BB_EXP_USER_SW4, - DA850_EVM_BB_EXP_USER_SW5, - DA850_EVM_BB_EXP_USER_SW6, - DA850_EVM_BB_EXP_USER_SW7, - DA850_EVM_BB_EXP_USER_SW8 -}; - -static const char * const da850_evm_bb_exp[] = { - [DA850_EVM_BB_EXP_DEEP_SLEEP_EN] = "deep_sleep_en", - [DA850_EVM_BB_EXP_SW_RST] = "sw_rst", - [DA850_EVM_BB_EXP_TP_23] = "tp_23", - [DA850_EVM_BB_EXP_TP_22] = "tp_22", - [DA850_EVM_BB_EXP_TP_21] = "tp_21", - [DA850_EVM_BB_EXP_USER_PB1] = "user_pb1", - [DA850_EVM_BB_EXP_USER_LED2] = "user_led2", - [DA850_EVM_BB_EXP_USER_LED1] = "user_led1", - [DA850_EVM_BB_EXP_USER_SW1] = "user_sw1", - [DA850_EVM_BB_EXP_USER_SW2] = "user_sw2", - [DA850_EVM_BB_EXP_USER_SW3] = "user_sw3", - [DA850_EVM_BB_EXP_USER_SW4] = "user_sw4", - [DA850_EVM_BB_EXP_USER_SW5] = "user_sw5", - [DA850_EVM_BB_EXP_USER_SW6] = "user_sw6", - [DA850_EVM_BB_EXP_USER_SW7] = "user_sw7", - [DA850_EVM_BB_EXP_USER_SW8] = "user_sw8", -}; - -#define DA850_N_BB_USER_SW 8 - -static struct gpio_keys_button da850_evm_bb_keys[] = { - [0] = { - .type = EV_KEY, - .active_low = 1, - .wakeup = 0, - .debounce_interval = DA850_KEYS_DEBOUNCE_MS, - .code = KEY_PROG1, - .desc = NULL, /* assigned at runtime */ - .gpio = -1, /* assigned at runtime */ - }, - [1 ... DA850_N_BB_USER_SW] = { - .type = EV_SW, - .active_low = 1, - .wakeup = 0, - .debounce_interval = DA850_KEYS_DEBOUNCE_MS, - .code = -1, /* assigned at runtime */ - .desc = NULL, /* assigned at runtime */ - .gpio = -1, /* assigned at runtime */ - }, -}; - -static struct gpio_keys_platform_data da850_evm_bb_keys_pdata = { - .buttons = da850_evm_bb_keys, - .nbuttons = ARRAY_SIZE(da850_evm_bb_keys), - .poll_interval = DA850_GPIO_KEYS_POLL_MS, -}; - -static struct platform_device da850_evm_bb_keys_device = { - .name = "gpio-keys-polled", - .id = 1, - .dev = { - .platform_data = &da850_evm_bb_keys_pdata - }, -}; - -static void da850_evm_bb_keys_init(unsigned gpio) -{ - int i; - struct gpio_keys_button *button; - - button = &da850_evm_bb_keys[0]; - button->desc = da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_PB1]; - button->gpio = gpio + DA850_EVM_BB_EXP_USER_PB1; - - for (i = 0; i < DA850_N_BB_USER_SW; i++) { - button = &da850_evm_bb_keys[i + 1]; - button->code = SW_LID + i; - button->desc = da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_SW1 + i]; - button->gpio = gpio + DA850_EVM_BB_EXP_USER_SW1 + i; - } -} - -static struct gpio_led da850_evm_bb_leds[] = { - { - .name = "user_led2", - }, - { - .name = "user_led1", - }, -}; - -static struct gpio_led_platform_data da850_evm_bb_leds_pdata = { - .leds = da850_evm_bb_leds, - .num_leds = ARRAY_SIZE(da850_evm_bb_leds), -}; - -static struct gpiod_lookup_table da850_evm_bb_leds_gpio_table = { - .dev_id = "leds-gpio", - .table = { - GPIO_LOOKUP_IDX("i2c-bb-expander", - DA850_EVM_BB_EXP_USER_LED2, NULL, - 0, GPIO_ACTIVE_LOW), - GPIO_LOOKUP_IDX("i2c-bb-expander", - DA850_EVM_BB_EXP_USER_LED2 + 1, NULL, - 1, GPIO_ACTIVE_LOW), - - { }, - }, -}; - -static struct platform_device da850_evm_bb_leds_device = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &da850_evm_bb_leds_pdata - } -}; - -static int da850_evm_bb_expander_setup(struct i2c_client *client, - unsigned gpio, unsigned ngpio, - void *c) -{ - int ret; - - /* - * Register the switches and pushbutton on the baseboard as a gpio-keys - * device. - */ - da850_evm_bb_keys_init(gpio); - ret = platform_device_register(&da850_evm_bb_keys_device); - if (ret) { - pr_warn("Could not register baseboard GPIO expander keys"); - goto io_exp_setup_sw_fail; - } - - gpiod_add_lookup_table(&da850_evm_bb_leds_gpio_table); - ret = platform_device_register(&da850_evm_bb_leds_device); - if (ret) { - pr_warn("Could not register baseboard GPIO expander LEDs"); - goto io_exp_setup_leds_fail; - } - - return 0; - -io_exp_setup_leds_fail: - platform_device_unregister(&da850_evm_bb_keys_device); -io_exp_setup_sw_fail: - return ret; -} - -static void da850_evm_bb_expander_teardown(struct i2c_client *client, - unsigned gpio, unsigned ngpio, void *c) -{ - platform_device_unregister(&da850_evm_bb_leds_device); - platform_device_unregister(&da850_evm_bb_keys_device); -} - -static struct pca953x_platform_data da850_evm_ui_expander_info = { - .gpio_base = DAVINCI_N_GPIO, - .setup = da850_evm_ui_expander_setup, - .teardown = da850_evm_ui_expander_teardown, - .names = da850_evm_ui_exp, -}; - -static struct pca953x_platform_data da850_evm_bb_expander_info = { - .gpio_base = DA850_BB_EXPANDER_GPIO_BASE, - .setup = da850_evm_bb_expander_setup, - .teardown = da850_evm_bb_expander_teardown, - .names = da850_evm_bb_exp, -}; - -static struct i2c_board_info __initdata da850_evm_i2c_devices[] = { - { - I2C_BOARD_INFO("tlv320aic3x", 0x18), - }, - { - I2C_BOARD_INFO("tca6416", 0x20), - .dev_name = "ui-expander", - .platform_data = &da850_evm_ui_expander_info, - }, - { - I2C_BOARD_INFO("tca6416", 0x21), - .dev_name = "bb-expander", - .platform_data = &da850_evm_bb_expander_info, - }, -}; - -static struct davinci_i2c_platform_data da850_evm_i2c_0_pdata = { - .bus_freq = 100, /* kHz */ - .bus_delay = 0, /* usec */ -}; - -/* davinci da850 evm audio machine driver */ -static u8 da850_iis_serializer_direction[] = { - INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, - INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, - INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, TX_MODE, - RX_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, -}; - -static struct snd_platform_data da850_evm_snd_data = { - .tx_dma_offset = 0x2000, - .rx_dma_offset = 0x2000, - .op_mode = DAVINCI_MCASP_IIS_MODE, - .num_serializer = ARRAY_SIZE(da850_iis_serializer_direction), - .tdm_slots = 2, - .serial_dir = da850_iis_serializer_direction, - .asp_chan_q = EVENTQ_0, - .ram_chan_q = EVENTQ_1, - .version = MCASP_VERSION_2, - .txnumevt = 1, - .rxnumevt = 1, - .sram_size_playback = SZ_8K, - .sram_size_capture = SZ_8K, -}; - -static const short da850_evm_mcasp_pins[] __initconst = { - DA850_AHCLKX, DA850_ACLKX, DA850_AFSX, - DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE, - DA850_AXR_11, DA850_AXR_12, - -1 -}; - -#define DA850_MMCSD_CD_PIN GPIO_TO_PIN(4, 0) -#define DA850_MMCSD_WP_PIN GPIO_TO_PIN(4, 1) - -static struct gpiod_lookup_table mmc_gpios_table = { - .dev_id = "da830-mmc.0", - .table = { - /* gpio chip 2 contains gpio range 64-95 */ - GPIO_LOOKUP("davinci_gpio", DA850_MMCSD_CD_PIN, "cd", - GPIO_ACTIVE_LOW), - GPIO_LOOKUP("davinci_gpio", DA850_MMCSD_WP_PIN, "wp", - GPIO_ACTIVE_HIGH), - { } - }, -}; - -static struct davinci_mmc_config da850_mmc_config = { - .wires = 4, - .max_freq = 50000000, - .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, -}; - -static const short da850_evm_mmcsd0_pins[] __initconst = { - DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2, - DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD, - DA850_GPIO4_0, DA850_GPIO4_1, - -1 -}; - -static struct property_entry da850_lcd_backlight_props[] = { - PROPERTY_ENTRY_BOOL("default-on"), - { } -}; - -static struct gpiod_lookup_table da850_lcd_backlight_gpio_table = { - .dev_id = "gpio-backlight", - .table = { - GPIO_LOOKUP("davinci_gpio", DA850_LCD_BL_PIN, NULL, 0), - { } - }, -}; - -static const struct platform_device_info da850_lcd_backlight_info = { - .name = "gpio-backlight", - .id = PLATFORM_DEVID_NONE, - .properties = da850_lcd_backlight_props, -}; - -static struct regulator_consumer_supply da850_lcd_supplies[] = { - REGULATOR_SUPPLY("lcd", NULL), -}; - -static struct regulator_init_data da850_lcd_supply_data = { - .consumer_supplies = da850_lcd_supplies, - .num_consumer_supplies = ARRAY_SIZE(da850_lcd_supplies), - .constraints = { - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, -}; - -static struct fixed_voltage_config da850_lcd_supply = { - .supply_name = "lcd", - .microvolts = 33000000, - .init_data = &da850_lcd_supply_data, -}; - -static struct platform_device da850_lcd_supply_device = { - .name = "reg-fixed-voltage", - .id = 1, /* Dummy fixed regulator is 0 */ - .dev = { - .platform_data = &da850_lcd_supply, - }, -}; - -static struct gpiod_lookup_table da850_lcd_supply_gpio_table = { - .dev_id = "reg-fixed-voltage.1", - .table = { - GPIO_LOOKUP("davinci_gpio", DA850_LCD_PWR_PIN, NULL, 0), - { } - }, -}; - -static struct gpiod_lookup_table *da850_lcd_gpio_lookups[] = { - &da850_lcd_backlight_gpio_table, - &da850_lcd_supply_gpio_table, -}; - -static int da850_lcd_hw_init(void) -{ - struct platform_device *backlight; - int status; - - gpiod_add_lookup_tables(da850_lcd_gpio_lookups, - ARRAY_SIZE(da850_lcd_gpio_lookups)); - - backlight = platform_device_register_full(&da850_lcd_backlight_info); - if (IS_ERR(backlight)) - return PTR_ERR(backlight); - - status = platform_device_register(&da850_lcd_supply_device); - if (status) - return status; - - return 0; -} - -/* Fixed regulator support */ -static struct regulator_consumer_supply fixed_supplies[] = { - /* Baseboard 3.3V: 5V -> TPS73701DCQ -> 3.3V */ - REGULATOR_SUPPLY("AVDD", "1-0018"), - REGULATOR_SUPPLY("DRVDD", "1-0018"), - - /* Baseboard 1.8V: 5V -> TPS73701DCQ -> 1.8V */ - REGULATOR_SUPPLY("DVDD", "1-0018"), - - /* UI card 3.3V: 5V -> TPS73701DCQ -> 3.3V */ - REGULATOR_SUPPLY("vcc", "1-0020"), -}; - -/* TPS65070 voltage regulator support */ - -/* 3.3V */ -static struct regulator_consumer_supply tps65070_dcdc1_consumers[] = { - { - .supply = "usb0_vdda33", - }, - { - .supply = "usb1_vdda33", - }, -}; - -/* 3.3V or 1.8V */ -static struct regulator_consumer_supply tps65070_dcdc2_consumers[] = { - { - .supply = "dvdd3318_a", - }, - { - .supply = "dvdd3318_b", - }, - { - .supply = "dvdd3318_c", - }, - REGULATOR_SUPPLY("IOVDD", "1-0018"), -}; - -/* 1.2V */ -static struct regulator_consumer_supply tps65070_dcdc3_consumers[] = { - { - .supply = "cvdd", - }, -}; - -/* 1.8V LDO */ -static struct regulator_consumer_supply tps65070_ldo1_consumers[] = { - { - .supply = "sata_vddr", - }, - { - .supply = "usb0_vdda18", - }, - { - .supply = "usb1_vdda18", - }, - { - .supply = "ddr_dvdd18", - }, -}; - -/* 1.2V LDO */ -static struct regulator_consumer_supply tps65070_ldo2_consumers[] = { - { - .supply = "sata_vdd", - }, - { - .supply = "pll0_vdda", - }, - { - .supply = "pll1_vdda", - }, - { - .supply = "usbs_cvdd", - }, - { - .supply = "vddarnwa1", - }, -}; - -/* We take advantage of the fact that both defdcdc{2,3} are tied high */ -static struct tps6507x_reg_platform_data tps6507x_platform_data = { - .defdcdc_default = true, -}; - -static struct regulator_init_data tps65070_regulator_data[] = { - /* dcdc1 */ - { - .constraints = { - .min_uV = 3150000, - .max_uV = 3450000, - .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS), - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc1_consumers), - .consumer_supplies = tps65070_dcdc1_consumers, - }, - - /* dcdc2 */ - { - .constraints = { - .min_uV = 1710000, - .max_uV = 3450000, - .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS), - .boot_on = 1, - .always_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc2_consumers), - .consumer_supplies = tps65070_dcdc2_consumers, - .driver_data = &tps6507x_platform_data, - }, - - /* dcdc3 */ - { - .constraints = { - .min_uV = 950000, - .max_uV = 1350000, - .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS), - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc3_consumers), - .consumer_supplies = tps65070_dcdc3_consumers, - .driver_data = &tps6507x_platform_data, - }, - - /* ldo1 */ - { - .constraints = { - .min_uV = 1710000, - .max_uV = 1890000, - .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS), - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(tps65070_ldo1_consumers), - .consumer_supplies = tps65070_ldo1_consumers, - }, - - /* ldo2 */ - { - .constraints = { - .min_uV = 1140000, - .max_uV = 1320000, - .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS), - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(tps65070_ldo2_consumers), - .consumer_supplies = tps65070_ldo2_consumers, - }, -}; - -static struct touchscreen_init_data tps6507x_touchscreen_data = { - .poll_period = 30, /* ms between touch samples */ - .min_pressure = 0x30, /* minimum pressure to trigger touch */ - .vendor = 0, /* /sys/class/input/input?/id/vendor */ - .product = 65070, /* /sys/class/input/input?/id/product */ - .version = 0x100, /* /sys/class/input/input?/id/version */ -}; - -static struct tps6507x_board tps_board = { - .tps6507x_pmic_init_data = &tps65070_regulator_data[0], - .tps6507x_ts_init_data = &tps6507x_touchscreen_data, -}; - -static struct i2c_board_info __initdata da850_evm_tps65070_info[] = { - { - I2C_BOARD_INFO("tps6507x", 0x48), - .platform_data = &tps_board, - }, -}; - -static int __init pmic_tps65070_init(void) -{ - return i2c_register_board_info(1, da850_evm_tps65070_info, - ARRAY_SIZE(da850_evm_tps65070_info)); -} - -static const short da850_evm_lcdc_pins[] = { - DA850_GPIO2_8, DA850_GPIO2_15, - -1 -}; - -static const short da850_evm_mii_pins[] = { - DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3, - DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER, - DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3, - DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK, - DA850_MDIO_D, - -1 -}; - -static const short da850_evm_rmii_pins[] = { - DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN, - DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1, - DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK, - DA850_MDIO_D, - -1 -}; - -static struct gpiod_hog da850_evm_emac_gpio_hogs[] = { - { - .chip_label = "davinci_gpio", - .chip_hwnum = DA850_MII_MDIO_CLKEN_PIN, - .line_name = "mdio_clk_en", - .lflags = 0, - /* dflags set in da850_evm_config_emac() */ - }, - { } -}; - -static int __init da850_evm_config_emac(void) -{ - void __iomem *cfg_chip3_base; - int ret; - u32 val; - struct davinci_soc_info *soc_info = &davinci_soc_info; - u8 rmii_en; - - if (!machine_is_davinci_da850_evm()) - return 0; - - rmii_en = soc_info->emac_pdata->rmii_en; - - cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG); - - val = __raw_readl(cfg_chip3_base); - - if (rmii_en) { - val |= BIT(8); - ret = davinci_cfg_reg_list(da850_evm_rmii_pins); - pr_info("EMAC: RMII PHY configured, MII PHY will not be" - " functional\n"); - } else { - val &= ~BIT(8); - ret = davinci_cfg_reg_list(da850_evm_mii_pins); - pr_info("EMAC: MII PHY configured, RMII PHY will not be" - " functional\n"); - } - - if (ret) - pr_warn("%s: CPGMAC/RMII mux setup failed: %d\n", - __func__, ret); - - /* configure the CFGCHIP3 register for RMII or MII */ - __raw_writel(val, cfg_chip3_base); - - ret = davinci_cfg_reg(DA850_GPIO2_6); - if (ret) - pr_warn("%s:GPIO(2,6) mux setup failed\n", __func__); - - da850_evm_emac_gpio_hogs[0].dflags = rmii_en ? GPIOD_OUT_HIGH - : GPIOD_OUT_LOW; - gpiod_add_hogs(da850_evm_emac_gpio_hogs); - - soc_info->emac_pdata->phy_id = DA850_EVM_PHY_ID; - - ret = da8xx_register_emac(); - if (ret) - pr_warn("%s: EMAC registration failed: %d\n", __func__, ret); - - return 0; -} -device_initcall(da850_evm_config_emac); - -/* - * The following EDMA channels/slots are not being used by drivers (for - * example: Timer, GPIO, UART events etc) on da850/omap-l138 EVM, hence - * they are being reserved for codecs on the DSP side. - */ -static const s16 da850_dma0_rsv_chans[][2] = { - /* (offset, number) */ - { 8, 6}, - {24, 4}, - {30, 2}, - {-1, -1} -}; - -static const s16 da850_dma0_rsv_slots[][2] = { - /* (offset, number) */ - { 8, 6}, - {24, 4}, - {30, 50}, - {-1, -1} -}; - -static const s16 da850_dma1_rsv_chans[][2] = { - /* (offset, number) */ - { 0, 28}, - {30, 2}, - {-1, -1} -}; - -static const s16 da850_dma1_rsv_slots[][2] = { - /* (offset, number) */ - { 0, 28}, - {30, 90}, - {-1, -1} -}; - -static struct edma_rsv_info da850_edma_cc0_rsv = { - .rsv_chans = da850_dma0_rsv_chans, - .rsv_slots = da850_dma0_rsv_slots, -}; - -static struct edma_rsv_info da850_edma_cc1_rsv = { - .rsv_chans = da850_dma1_rsv_chans, - .rsv_slots = da850_dma1_rsv_slots, -}; - -static struct edma_rsv_info *da850_edma_rsv[2] = { - &da850_edma_cc0_rsv, - &da850_edma_cc1_rsv, -}; - -#ifdef CONFIG_CPU_FREQ -static __init int da850_evm_init_cpufreq(void) -{ - switch (system_rev & 0xF) { - case 3: - da850_max_speed = 456000; - break; - case 2: - da850_max_speed = 408000; - break; - case 1: - da850_max_speed = 372000; - break; - } - - return da850_register_cpufreq("pll0_sysclk3"); -} -#else -static __init int da850_evm_init_cpufreq(void) { return 0; } -#endif - -#if defined(CONFIG_DA850_UI_SD_VIDEO_PORT) - -#define TVP5147_CH0 "tvp514x-0" -#define TVP5147_CH1 "tvp514x-1" - -/* VPIF capture configuration */ -static struct tvp514x_platform_data tvp5146_pdata = { - .clk_polarity = 0, - .hs_polarity = 1, - .vs_polarity = 1, -}; - -#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) - -static struct vpif_input da850_ch0_inputs[] = { - { - .input = { - .index = 0, - .name = "Composite", - .type = V4L2_INPUT_TYPE_CAMERA, - .capabilities = V4L2_IN_CAP_STD, - .std = TVP514X_STD_ALL, - }, - .input_route = INPUT_CVBS_VI2B, - .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC, - .subdev_name = TVP5147_CH0, - }, -}; - -static struct vpif_input da850_ch1_inputs[] = { - { - .input = { - .index = 0, - .name = "S-Video", - .type = V4L2_INPUT_TYPE_CAMERA, - .capabilities = V4L2_IN_CAP_STD, - .std = TVP514X_STD_ALL, - }, - .input_route = INPUT_SVIDEO_VI2C_VI1C, - .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC, - .subdev_name = TVP5147_CH1, - }, -}; - -static struct vpif_subdev_info da850_vpif_capture_sdev_info[] = { - { - .name = TVP5147_CH0, - .board_info = { - I2C_BOARD_INFO("tvp5146", 0x5d), - .platform_data = &tvp5146_pdata, - }, - }, - { - .name = TVP5147_CH1, - .board_info = { - I2C_BOARD_INFO("tvp5146", 0x5c), - .platform_data = &tvp5146_pdata, - }, - }, -}; - -static struct vpif_capture_config da850_vpif_capture_config = { - .subdev_info = da850_vpif_capture_sdev_info, - .subdev_count = ARRAY_SIZE(da850_vpif_capture_sdev_info), - .i2c_adapter_id = 1, - .chan_config[0] = { - .inputs = da850_ch0_inputs, - .input_count = ARRAY_SIZE(da850_ch0_inputs), - .vpif_if = { - .if_type = VPIF_IF_BT656, - .hd_pol = 1, - .vd_pol = 1, - .fid_pol = 0, - }, - }, - .chan_config[1] = { - .inputs = da850_ch1_inputs, - .input_count = ARRAY_SIZE(da850_ch1_inputs), - .vpif_if = { - .if_type = VPIF_IF_BT656, - .hd_pol = 1, - .vd_pol = 1, - .fid_pol = 0, - }, - }, - .card_name = "DA850/OMAP-L138 Video Capture", -}; - -/* VPIF display configuration */ - -static struct adv7343_platform_data adv7343_pdata = { - .mode_config = { - .dac = { 1, 1, 1 }, - }, - .sd_config = { - .sd_dac_out = { 1 }, - }, -}; - -static struct vpif_subdev_info da850_vpif_subdev[] = { - { - .name = "adv7343", - .board_info = { - I2C_BOARD_INFO("adv7343", 0x2a), - .platform_data = &adv7343_pdata, - }, - }, -}; - -static const struct vpif_output da850_ch0_outputs[] = { - { - .output = { - .index = 0, - .name = "Composite", - .type = V4L2_OUTPUT_TYPE_ANALOG, - .capabilities = V4L2_OUT_CAP_STD, - .std = V4L2_STD_ALL, - }, - .subdev_name = "adv7343", - .output_route = ADV7343_COMPOSITE_ID, - }, - { - .output = { - .index = 1, - .name = "S-Video", - .type = V4L2_OUTPUT_TYPE_ANALOG, - .capabilities = V4L2_OUT_CAP_STD, - .std = V4L2_STD_ALL, - }, - .subdev_name = "adv7343", - .output_route = ADV7343_SVIDEO_ID, - }, -}; - -static struct vpif_display_config da850_vpif_display_config = { - .subdevinfo = da850_vpif_subdev, - .subdev_count = ARRAY_SIZE(da850_vpif_subdev), - .chan_config[0] = { - .outputs = da850_ch0_outputs, - .output_count = ARRAY_SIZE(da850_ch0_outputs), - }, - .card_name = "DA850/OMAP-L138 Video Display", - .i2c_adapter_id = 1, -}; - -static __init void da850_vpif_init(void) -{ - int ret; - - ret = da850_register_vpif(); - if (ret) - pr_warn("da850_evm_init: VPIF setup failed: %d\n", ret); - - ret = davinci_cfg_reg_list(da850_vpif_capture_pins); - if (ret) - pr_warn("da850_evm_init: VPIF capture mux setup failed: %d\n", - ret); - - ret = da850_register_vpif_capture(&da850_vpif_capture_config); - if (ret) - pr_warn("da850_evm_init: VPIF capture setup failed: %d\n", ret); - - ret = davinci_cfg_reg_list(da850_vpif_display_pins); - if (ret) - pr_warn("da850_evm_init: VPIF display mux setup failed: %d\n", - ret); - - ret = da850_register_vpif_display(&da850_vpif_display_config); - if (ret) - pr_warn("da850_evm_init: VPIF display setup failed: %d\n", ret); -} - -#else -static __init void da850_vpif_init(void) {} -#endif - -#define DA850EVM_SATA_REFCLKPN_RATE (100 * 1000 * 1000) - -static __init void da850_evm_init(void) -{ - int ret; - - da850_register_clocks(); - - ret = da850_register_gpio(); - if (ret) - pr_warn("%s: GPIO init failed: %d\n", __func__, ret); - - regulator_register_fixed(0, fixed_supplies, ARRAY_SIZE(fixed_supplies)); - - ret = pmic_tps65070_init(); - if (ret) - pr_warn("%s: TPS65070 PMIC init failed: %d\n", __func__, ret); - - ret = da850_register_edma(da850_edma_rsv); - if (ret) - pr_warn("%s: EDMA registration failed: %d\n", __func__, ret); - - ret = davinci_cfg_reg_list(da850_i2c0_pins); - if (ret) - pr_warn("%s: I2C0 mux setup failed: %d\n", __func__, ret); - - ret = da8xx_register_i2c(0, &da850_evm_i2c_0_pdata); - if (ret) - pr_warn("%s: I2C0 registration failed: %d\n", __func__, ret); - - - ret = da8xx_register_watchdog(); - if (ret) - pr_warn("%s: watchdog registration failed: %d\n", - __func__, ret); - - if (HAS_MMC) { - ret = davinci_cfg_reg_list(da850_evm_mmcsd0_pins); - if (ret) - pr_warn("%s: MMCSD0 mux setup failed: %d\n", - __func__, ret); - - gpiod_add_lookup_table(&mmc_gpios_table); - - ret = da8xx_register_mmcsd0(&da850_mmc_config); - if (ret) - pr_warn("%s: MMCSD0 registration failed: %d\n", - __func__, ret); - } - - davinci_serial_init(da8xx_serial_device); - - nvmem_add_cell_table(&da850evm_nvmem_cell_table); - nvmem_add_cell_lookups(&da850evm_nvmem_cell_lookup, 1); - - i2c_register_board_info(1, da850_evm_i2c_devices, - ARRAY_SIZE(da850_evm_i2c_devices)); - - /* - * shut down uart 0 and 1; they are not used on the board and - * accessing them causes endless "too much work in irq53" messages - * with arago fs - */ - __raw_writel(0, IO_ADDRESS(DA8XX_UART1_BASE) + 0x30); - __raw_writel(0, IO_ADDRESS(DA8XX_UART0_BASE) + 0x30); - - ret = davinci_cfg_reg_list(da850_evm_mcasp_pins); - if (ret) - pr_warn("%s: McASP mux setup failed: %d\n", __func__, ret); - - da850_evm_snd_data.sram_pool = sram_get_gen_pool(); - da8xx_register_mcasp(0, &da850_evm_snd_data); - - ret = davinci_cfg_reg_list(da850_lcdcntl_pins); - if (ret) - pr_warn("%s: LCDC mux setup failed: %d\n", __func__, ret); - - ret = da8xx_register_uio_pruss(); - if (ret) - pr_warn("da850_evm_init: pruss initialization failed: %d\n", - ret); - - /* Handle board specific muxing for LCD here */ - ret = davinci_cfg_reg_list(da850_evm_lcdc_pins); - if (ret) - pr_warn("%s: EVM specific LCD mux setup failed: %d\n", - __func__, ret); - - ret = da850_lcd_hw_init(); - if (ret) - pr_warn("%s: LCD initialization failed: %d\n", __func__, ret); - - ret = da8xx_register_lcdc(&sharp_lk043t1dg01_pdata); - if (ret) - pr_warn("%s: LCDC registration failed: %d\n", __func__, ret); - - ret = da8xx_register_rtc(); - if (ret) - pr_warn("%s: RTC setup failed: %d\n", __func__, ret); - - ret = da850_evm_init_cpufreq(); - if (ret) - pr_warn("%s: cpufreq registration failed: %d\n", __func__, ret); - - ret = da8xx_register_cpuidle(); - if (ret) - pr_warn("%s: cpuidle registration failed: %d\n", __func__, ret); - - davinci_pm_init(); - da850_vpif_init(); - - ret = spi_register_board_info(da850evm_spi_info, - ARRAY_SIZE(da850evm_spi_info)); - if (ret) - pr_warn("%s: spi info registration failed: %d\n", __func__, - ret); - - ret = da8xx_register_spi_bus(1, ARRAY_SIZE(da850evm_spi_info)); - if (ret) - pr_warn("%s: SPI 1 registration failed: %d\n", __func__, ret); - - ret = da850_register_sata(DA850EVM_SATA_REFCLKPN_RATE); - if (ret) - pr_warn("%s: SATA registration failed: %d\n", __func__, ret); - - ret = da8xx_register_rproc(); - if (ret) - pr_warn("%s: dsp/rproc registration failed: %d\n", - __func__, ret); - - regulator_has_full_constraints(); -} - -#ifdef CONFIG_SERIAL_8250_CONSOLE -static int __init da850_evm_console_init(void) -{ - if (!machine_is_davinci_da850_evm()) - return 0; - - return add_preferred_console("ttyS", 2, "115200"); -} -console_initcall(da850_evm_console_init); -#endif - -static void __init da850_evm_map_io(void) -{ - da850_init(); -} - -MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138/AM18x EVM") - .atag_offset = 0x100, - .map_io = da850_evm_map_io, - .init_irq = da850_init_irq, - .init_time = da850_init_time, - .init_machine = da850_evm_init, - .init_late = davinci_init_late, - .dma_zone_size = SZ_128M, - .reserve = da8xx_rproc_reserve_cma, -MACHINE_END diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c deleted file mode 100644 index b48ab1c3e48b..000000000000 --- a/arch/arm/mach-davinci/board-dm355-evm.c +++ /dev/null @@ -1,444 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * TI DaVinci EVM board support - * - * Author: Kevin Hilman, Deep Root Systems, LLC - * - * 2007 (c) MontaVista Software, Inc. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "serial.h" -#include "common.h" -#include "davinci.h" - -/* NOTE: this is geared for the standard config, with a socketed - * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you - * swap chips, maybe with a different block size, partitioning may - * need to be changed. - */ -#define NAND_BLOCK_SIZE SZ_128K - -static struct mtd_partition davinci_nand_partitions[] = { - { - /* UBL (a few copies) plus U-Boot */ - .name = "bootloader", - .offset = 0, - .size = 15 * NAND_BLOCK_SIZE, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, { - /* U-Boot environment */ - .name = "params", - .offset = MTDPART_OFS_APPEND, - .size = 1 * NAND_BLOCK_SIZE, - .mask_flags = 0, - }, { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_4M, - .mask_flags = 0, - }, { - .name = "filesystem1", - .offset = MTDPART_OFS_APPEND, - .size = SZ_512M, - .mask_flags = 0, - }, { - .name = "filesystem2", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0, - } - /* two blocks with bad block table (and mirror) at the end */ -}; - -static struct davinci_nand_pdata davinci_nand_data = { - .core_chipsel = 0, - .mask_chipsel = BIT(14), - .parts = davinci_nand_partitions, - .nr_parts = ARRAY_SIZE(davinci_nand_partitions), - .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST, - .bbt_options = NAND_BBT_USE_FLASH, - .ecc_bits = 4, -}; - -static struct resource davinci_nand_resources[] = { - { - .start = DM355_ASYNC_EMIF_DATA_CE0_BASE, - .end = DM355_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1, - .flags = IORESOURCE_MEM, - }, { - .start = DM355_ASYNC_EMIF_CONTROL_BASE, - .end = DM355_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device davinci_nand_device = { - .name = "davinci_nand", - .id = 0, - - .num_resources = ARRAY_SIZE(davinci_nand_resources), - .resource = davinci_nand_resources, - - .dev = { - .platform_data = &davinci_nand_data, - }, -}; - -#define DM355_I2C_SDA_PIN GPIO_TO_PIN(0, 15) -#define DM355_I2C_SCL_PIN GPIO_TO_PIN(0, 14) - -static struct gpiod_lookup_table i2c_recovery_gpiod_table = { - .dev_id = "i2c_davinci.1", - .table = { - GPIO_LOOKUP("davinci_gpio", DM355_I2C_SDA_PIN, "sda", - GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), - GPIO_LOOKUP("davinci_gpio", DM355_I2C_SCL_PIN, "scl", - GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), - { } - }, -}; - -static struct davinci_i2c_platform_data i2c_pdata = { - .bus_freq = 400 /* kHz */, - .bus_delay = 0 /* usec */, - .gpio_recovery = true, -}; - -static int dm355evm_mmc_gpios = -EINVAL; - -static void dm355evm_mmcsd_gpios(unsigned gpio) -{ - gpio_request(gpio + 0, "mmc0_ro"); - gpio_request(gpio + 1, "mmc0_cd"); - gpio_request(gpio + 2, "mmc1_ro"); - gpio_request(gpio + 3, "mmc1_cd"); - - /* we "know" these are input-only so we don't - * need to call gpio_direction_input() - */ - - dm355evm_mmc_gpios = gpio; -} - -static struct i2c_board_info dm355evm_i2c_info[] = { - { I2C_BOARD_INFO("dm355evm_msp", 0x25), - .platform_data = dm355evm_mmcsd_gpios, - }, - /* { plus irq }, */ - { I2C_BOARD_INFO("tlv320aic33", 0x1b), }, -}; - -static void __init evm_init_i2c(void) -{ - gpiod_add_lookup_table(&i2c_recovery_gpiod_table); - davinci_init_i2c(&i2c_pdata); - - gpio_request(5, "dm355evm_msp"); - gpio_direction_input(5); - dm355evm_i2c_info[0].irq = gpio_to_irq(5); - - i2c_register_board_info(1, dm355evm_i2c_info, - ARRAY_SIZE(dm355evm_i2c_info)); -} - -static struct resource dm355evm_dm9000_rsrc[] = { - { - /* addr */ - .start = 0x04014000, - .end = 0x04014001, - .flags = IORESOURCE_MEM, - }, { - /* data */ - .start = 0x04014002, - .end = 0x04014003, - .flags = IORESOURCE_MEM, - }, { - .flags = IORESOURCE_IRQ - | IORESOURCE_IRQ_HIGHEDGE /* rising (active high) */, - }, -}; - -static struct dm9000_plat_data dm335evm_dm9000_platdata; - -static struct platform_device dm355evm_dm9000 = { - .name = "dm9000", - .id = -1, - .resource = dm355evm_dm9000_rsrc, - .num_resources = ARRAY_SIZE(dm355evm_dm9000_rsrc), - .dev = { - .platform_data = &dm335evm_dm9000_platdata, - }, -}; - -static struct tvp514x_platform_data tvp5146_pdata = { - .clk_polarity = 0, - .hs_polarity = 1, - .vs_polarity = 1 -}; - -#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) -/* Inputs available at the TVP5146 */ -static struct v4l2_input tvp5146_inputs[] = { - { - .index = 0, - .name = "Composite", - .type = V4L2_INPUT_TYPE_CAMERA, - .std = TVP514X_STD_ALL, - }, - { - .index = 1, - .name = "S-Video", - .type = V4L2_INPUT_TYPE_CAMERA, - .std = TVP514X_STD_ALL, - }, -}; - -/* - * this is the route info for connecting each input to decoder - * ouput that goes to vpfe. There is a one to one correspondence - * with tvp5146_inputs - */ -static struct vpfe_route tvp5146_routes[] = { - { - .input = INPUT_CVBS_VI2B, - .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, - }, - { - .input = INPUT_SVIDEO_VI2C_VI1C, - .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, - }, -}; - -static struct vpfe_subdev_info vpfe_sub_devs[] = { - { - .name = "tvp5146", - .grp_id = 0, - .num_inputs = ARRAY_SIZE(tvp5146_inputs), - .inputs = tvp5146_inputs, - .routes = tvp5146_routes, - .can_route = 1, - .ccdc_if_params = { - .if_type = VPFE_BT656, - .hdpol = VPFE_PINPOL_POSITIVE, - .vdpol = VPFE_PINPOL_POSITIVE, - }, - .board_info = { - I2C_BOARD_INFO("tvp5146", 0x5d), - .platform_data = &tvp5146_pdata, - }, - } -}; - -static struct vpfe_config vpfe_cfg = { - .num_subdevs = ARRAY_SIZE(vpfe_sub_devs), - .i2c_adapter_id = 1, - .sub_devs = vpfe_sub_devs, - .card_name = "DM355 EVM", - .ccdc = "DM355 CCDC", -}; - -/* venc standards timings */ -static struct vpbe_enc_mode_info dm355evm_enc_preset_timing[] = { - { - .name = "ntsc", - .timings_type = VPBE_ENC_STD, - .std_id = V4L2_STD_NTSC, - .interlaced = 1, - .xres = 720, - .yres = 480, - .aspect = {11, 10}, - .fps = {30000, 1001}, - .left_margin = 0x79, - .upper_margin = 0x10, - }, - { - .name = "pal", - .timings_type = VPBE_ENC_STD, - .std_id = V4L2_STD_PAL, - .interlaced = 1, - .xres = 720, - .yres = 576, - .aspect = {54, 59}, - .fps = {25, 1}, - .left_margin = 0x7E, - .upper_margin = 0x16 - }, -}; - -#define VENC_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) - -/* - * The outputs available from VPBE + ecnoders. Keep the - * the order same as that of encoders. First those from venc followed by that - * from encoders. Index in the output refers to index on a particular encoder. - * Driver uses this index to pass it to encoder when it supports more than - * one output. Application uses index of the array to set an output. - */ -static struct vpbe_output dm355evm_vpbe_outputs[] = { - { - .output = { - .index = 0, - .name = "Composite", - .type = V4L2_OUTPUT_TYPE_ANALOG, - .std = VENC_STD_ALL, - .capabilities = V4L2_OUT_CAP_STD, - }, - .subdev_name = DM355_VPBE_VENC_SUBDEV_NAME, - .default_mode = "ntsc", - .num_modes = ARRAY_SIZE(dm355evm_enc_preset_timing), - .modes = dm355evm_enc_preset_timing, - .if_params = MEDIA_BUS_FMT_FIXED, - }, -}; - -static struct vpbe_config dm355evm_display_cfg = { - .module_name = "dm355-vpbe-display", - .i2c_adapter_id = 1, - .osd = { - .module_name = DM355_VPBE_OSD_SUBDEV_NAME, - }, - .venc = { - .module_name = DM355_VPBE_VENC_SUBDEV_NAME, - }, - .num_outputs = ARRAY_SIZE(dm355evm_vpbe_outputs), - .outputs = dm355evm_vpbe_outputs, -}; - -static struct platform_device *davinci_evm_devices[] __initdata = { - &dm355evm_dm9000, - &davinci_nand_device, -}; - -static void __init dm355_evm_map_io(void) -{ - dm355_init(); -} - -static int dm355evm_mmc_get_cd(int module) -{ - if (!gpio_is_valid(dm355evm_mmc_gpios)) - return -ENXIO; - /* low == card present */ - return !gpio_get_value_cansleep(dm355evm_mmc_gpios + 2 * module + 1); -} - -static int dm355evm_mmc_get_ro(int module) -{ - if (!gpio_is_valid(dm355evm_mmc_gpios)) - return -ENXIO; - /* high == card's write protect switch active */ - return gpio_get_value_cansleep(dm355evm_mmc_gpios + 2 * module + 0); -} - -static struct davinci_mmc_config dm355evm_mmc_config = { - .get_cd = dm355evm_mmc_get_cd, - .get_ro = dm355evm_mmc_get_ro, - .wires = 4, - .max_freq = 50000000, - .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, -}; - -/* Don't connect anything to J10 unless you're only using USB host - * mode *and* have to do so with some kind of gender-bender. If - * you have proper Mini-B or Mini-A cables (or Mini-A adapters) - * the ID pin won't need any help. - */ -#define USB_ID_VALUE 1 /* ID pulled low */ - -static struct spi_eeprom at25640a = { - .byte_len = SZ_64K / 8, - .name = "at25640a", - .page_size = 32, - .flags = EE_ADDR2, -}; - -static const struct spi_board_info dm355_evm_spi_info[] __initconst = { - { - .modalias = "at25", - .platform_data = &at25640a, - .max_speed_hz = 10 * 1000 * 1000, /* at 3v3 */ - .bus_num = 0, - .chip_select = 0, - .mode = SPI_MODE_0, - }, -}; - -static __init void dm355_evm_init(void) -{ - struct clk *aemif; - int ret; - - dm355_register_clocks(); - - ret = dm355_gpio_register(); - if (ret) - pr_warn("%s: GPIO init failed: %d\n", __func__, ret); - - gpio_request(1, "dm9000"); - gpio_direction_input(1); - dm355evm_dm9000_rsrc[2].start = gpio_to_irq(1); - - aemif = clk_get(&dm355evm_dm9000.dev, "aemif"); - if (!WARN(IS_ERR(aemif), "unable to get AEMIF clock\n")) - clk_prepare_enable(aemif); - - platform_add_devices(davinci_evm_devices, - ARRAY_SIZE(davinci_evm_devices)); - evm_init_i2c(); - davinci_serial_init(dm355_serial_device); - - /* NOTE: NAND flash timings set by the UBL are slower than - * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204 - * but could be 0x0400008c for about 25% faster page reads. - */ - - gpio_request(2, "usb_id_toggle"); - gpio_direction_output(2, USB_ID_VALUE); - /* irlml6401 switches over 1A in under 8 msec */ - davinci_setup_usb(1000, 8); - - davinci_setup_mmc(0, &dm355evm_mmc_config); - davinci_setup_mmc(1, &dm355evm_mmc_config); - - dm355_init_video(&vpfe_cfg, &dm355evm_display_cfg); - - dm355_init_spi0(BIT(0), dm355_evm_spi_info, - ARRAY_SIZE(dm355_evm_spi_info)); - - /* DM335 EVM uses ASP1; line-out is a stereo mini-jack */ - dm355_init_asp1(ASP1_TX_EVT_EN | ASP1_RX_EVT_EN); -} - -MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM") - .atag_offset = 0x100, - .map_io = dm355_evm_map_io, - .init_irq = dm355_init_irq, - .init_time = dm355_init_time, - .init_machine = dm355_evm_init, - .init_late = davinci_init_late, - .dma_zone_size = SZ_128M, -MACHINE_END diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c deleted file mode 100644 index 32b9d607d025..000000000000 --- a/arch/arm/mach-davinci/board-dm355-leopard.c +++ /dev/null @@ -1,278 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * DM355 leopard board support - * - * Based on board-dm355-evm.c - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "common.h" -#include "serial.h" -#include "davinci.h" - -/* NOTE: this is geared for the standard config, with a socketed - * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you - * swap chips, maybe with a different block size, partitioning may - * need to be changed. - */ -#define NAND_BLOCK_SIZE SZ_128K - -static struct mtd_partition davinci_nand_partitions[] = { - { - /* UBL (a few copies) plus U-Boot */ - .name = "bootloader", - .offset = 0, - .size = 15 * NAND_BLOCK_SIZE, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, { - /* U-Boot environment */ - .name = "params", - .offset = MTDPART_OFS_APPEND, - .size = 1 * NAND_BLOCK_SIZE, - .mask_flags = 0, - }, { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_4M, - .mask_flags = 0, - }, { - .name = "filesystem1", - .offset = MTDPART_OFS_APPEND, - .size = SZ_512M, - .mask_flags = 0, - }, { - .name = "filesystem2", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0, - } - /* two blocks with bad block table (and mirror) at the end */ -}; - -static struct davinci_nand_pdata davinci_nand_data = { - .core_chipsel = 0, - .mask_chipsel = BIT(14), - .parts = davinci_nand_partitions, - .nr_parts = ARRAY_SIZE(davinci_nand_partitions), - .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST, - .ecc_placement = NAND_ECC_PLACEMENT_INTERLEAVED, - .ecc_bits = 4, - .bbt_options = NAND_BBT_USE_FLASH, -}; - -static struct resource davinci_nand_resources[] = { - { - .start = DM355_ASYNC_EMIF_DATA_CE0_BASE, - .end = DM355_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1, - .flags = IORESOURCE_MEM, - }, { - .start = DM355_ASYNC_EMIF_CONTROL_BASE, - .end = DM355_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device davinci_nand_device = { - .name = "davinci_nand", - .id = 0, - - .num_resources = ARRAY_SIZE(davinci_nand_resources), - .resource = davinci_nand_resources, - - .dev = { - .platform_data = &davinci_nand_data, - }, -}; - -static struct davinci_i2c_platform_data i2c_pdata = { - .bus_freq = 400 /* kHz */, - .bus_delay = 0 /* usec */, -}; - -static int leopard_mmc_gpio = -EINVAL; - -static void dm355leopard_mmcsd_gpios(unsigned gpio) -{ - gpio_request(gpio + 0, "mmc0_ro"); - gpio_request(gpio + 1, "mmc0_cd"); - gpio_request(gpio + 2, "mmc1_ro"); - gpio_request(gpio + 3, "mmc1_cd"); - - /* we "know" these are input-only so we don't - * need to call gpio_direction_input() - */ - - leopard_mmc_gpio = gpio; -} - -static struct i2c_board_info dm355leopard_i2c_info[] = { - { I2C_BOARD_INFO("dm355leopard_msp", 0x25), - .platform_data = dm355leopard_mmcsd_gpios, - /* plus irq */ }, - /* { I2C_BOARD_INFO("tlv320aic3x", 0x1b), }, */ - /* { I2C_BOARD_INFO("tvp5146", 0x5d), }, */ -}; - -static void __init leopard_init_i2c(void) -{ - davinci_init_i2c(&i2c_pdata); - - gpio_request(5, "dm355leopard_msp"); - gpio_direction_input(5); - dm355leopard_i2c_info[0].irq = gpio_to_irq(5); - - i2c_register_board_info(1, dm355leopard_i2c_info, - ARRAY_SIZE(dm355leopard_i2c_info)); -} - -static struct resource dm355leopard_dm9000_rsrc[] = { - { - /* addr */ - .start = 0x04000000, - .end = 0x04000001, - .flags = IORESOURCE_MEM, - }, { - /* data */ - .start = 0x04000016, - .end = 0x04000017, - .flags = IORESOURCE_MEM, - }, { - .flags = IORESOURCE_IRQ - | IORESOURCE_IRQ_HIGHEDGE /* rising (active high) */, - }, -}; - -static struct platform_device dm355leopard_dm9000 = { - .name = "dm9000", - .id = -1, - .resource = dm355leopard_dm9000_rsrc, - .num_resources = ARRAY_SIZE(dm355leopard_dm9000_rsrc), -}; - -static struct platform_device *davinci_leopard_devices[] __initdata = { - &dm355leopard_dm9000, - &davinci_nand_device, -}; - -static void __init dm355_leopard_map_io(void) -{ - dm355_init(); -} - -static int dm355leopard_mmc_get_cd(int module) -{ - if (!gpio_is_valid(leopard_mmc_gpio)) - return -ENXIO; - /* low == card present */ - return !gpio_get_value_cansleep(leopard_mmc_gpio + 2 * module + 1); -} - -static int dm355leopard_mmc_get_ro(int module) -{ - if (!gpio_is_valid(leopard_mmc_gpio)) - return -ENXIO; - /* high == card's write protect switch active */ - return gpio_get_value_cansleep(leopard_mmc_gpio + 2 * module + 0); -} - -static struct davinci_mmc_config dm355leopard_mmc_config = { - .get_cd = dm355leopard_mmc_get_cd, - .get_ro = dm355leopard_mmc_get_ro, - .wires = 4, - .max_freq = 50000000, - .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, -}; - -/* Don't connect anything to J10 unless you're only using USB host - * mode *and* have to do so with some kind of gender-bender. If - * you have proper Mini-B or Mini-A cables (or Mini-A adapters) - * the ID pin won't need any help. - */ -#define USB_ID_VALUE 1 /* ID pulled low */ - -static struct spi_eeprom at25640a = { - .byte_len = SZ_64K / 8, - .name = "at25640a", - .page_size = 32, - .flags = EE_ADDR2, -}; - -static const struct spi_board_info dm355_leopard_spi_info[] __initconst = { - { - .modalias = "at25", - .platform_data = &at25640a, - .max_speed_hz = 10 * 1000 * 1000, /* at 3v3 */ - .bus_num = 0, - .chip_select = 0, - .mode = SPI_MODE_0, - }, -}; - -static __init void dm355_leopard_init(void) -{ - struct clk *aemif; - int ret; - - dm355_register_clocks(); - - ret = dm355_gpio_register(); - if (ret) - pr_warn("%s: GPIO init failed: %d\n", __func__, ret); - - gpio_request(9, "dm9000"); - gpio_direction_input(9); - dm355leopard_dm9000_rsrc[2].start = gpio_to_irq(9); - - aemif = clk_get(&dm355leopard_dm9000.dev, "aemif"); - if (!WARN(IS_ERR(aemif), "unable to get AEMIF clock\n")) - clk_prepare_enable(aemif); - - platform_add_devices(davinci_leopard_devices, - ARRAY_SIZE(davinci_leopard_devices)); - leopard_init_i2c(); - davinci_serial_init(dm355_serial_device); - - /* NOTE: NAND flash timings set by the UBL are slower than - * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204 - * but could be 0x0400008c for about 25% faster page reads. - */ - - gpio_request(2, "usb_id_toggle"); - gpio_direction_output(2, USB_ID_VALUE); - /* irlml6401 switches over 1A in under 8 msec */ - davinci_setup_usb(1000, 8); - - davinci_setup_mmc(0, &dm355leopard_mmc_config); - davinci_setup_mmc(1, &dm355leopard_mmc_config); - - dm355_init_spi0(BIT(0), dm355_leopard_spi_info, - ARRAY_SIZE(dm355_leopard_spi_info)); -} - -MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard") - .atag_offset = 0x100, - .map_io = dm355_leopard_map_io, - .init_irq = dm355_init_irq, - .init_time = dm355_init_time, - .init_machine = dm355_leopard_init, - .init_late = davinci_init_late, - .dma_zone_size = SZ_128M, -MACHINE_END diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c deleted file mode 100644 index d8c6c360818b..000000000000 --- a/arch/arm/mach-davinci/board-dm365-evm.c +++ /dev/null @@ -1,855 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * TI DaVinci DM365 EVM board support - * - * Copyright (C) 2009 Texas Instruments Incorporated - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include -#include - -#include -#include - -#include "mux.h" -#include "common.h" -#include "serial.h" -#include "davinci.h" - -static inline int have_imager(void) -{ - /* REVISIT when it's supported, trigger via Kconfig */ - return 0; -} - -static inline int have_tvp7002(void) -{ - /* REVISIT when it's supported, trigger via Kconfig */ - return 0; -} - -#define DM365_EVM_PHY_ID "davinci_mdio-0:01" -/* - * A MAX-II CPLD is used for various board control functions. - */ -#define CPLD_OFFSET(a13a8,a2a1) (((a13a8) << 10) + ((a2a1) << 3)) - -#define CPLD_VERSION CPLD_OFFSET(0,0) /* r/o */ -#define CPLD_TEST CPLD_OFFSET(0,1) -#define CPLD_LEDS CPLD_OFFSET(0,2) -#define CPLD_MUX CPLD_OFFSET(0,3) -#define CPLD_SWITCH CPLD_OFFSET(1,0) /* r/o */ -#define CPLD_POWER CPLD_OFFSET(1,1) -#define CPLD_VIDEO CPLD_OFFSET(1,2) -#define CPLD_CARDSTAT CPLD_OFFSET(1,3) /* r/o */ - -#define CPLD_DILC_OUT CPLD_OFFSET(2,0) -#define CPLD_DILC_IN CPLD_OFFSET(2,1) /* r/o */ - -#define CPLD_IMG_DIR0 CPLD_OFFSET(2,2) -#define CPLD_IMG_MUX0 CPLD_OFFSET(2,3) -#define CPLD_IMG_MUX1 CPLD_OFFSET(3,0) -#define CPLD_IMG_DIR1 CPLD_OFFSET(3,1) -#define CPLD_IMG_MUX2 CPLD_OFFSET(3,2) -#define CPLD_IMG_MUX3 CPLD_OFFSET(3,3) -#define CPLD_IMG_DIR2 CPLD_OFFSET(4,0) -#define CPLD_IMG_MUX4 CPLD_OFFSET(4,1) -#define CPLD_IMG_MUX5 CPLD_OFFSET(4,2) - -#define CPLD_RESETS CPLD_OFFSET(4,3) - -#define CPLD_CCD_DIR1 CPLD_OFFSET(0x3e,0) -#define CPLD_CCD_IO1 CPLD_OFFSET(0x3e,1) -#define CPLD_CCD_DIR2 CPLD_OFFSET(0x3e,2) -#define CPLD_CCD_IO2 CPLD_OFFSET(0x3e,3) -#define CPLD_CCD_DIR3 CPLD_OFFSET(0x3f,0) -#define CPLD_CCD_IO3 CPLD_OFFSET(0x3f,1) - -static void __iomem *cpld; - - -/* NOTE: this is geared for the standard config, with a socketed - * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you - * swap chips with a different block size, partitioning will - * need to be changed. This NAND chip MT29F16G08FAA is the default - * NAND shipped with the Spectrum Digital DM365 EVM - */ -#define NAND_BLOCK_SIZE SZ_128K - -static struct mtd_partition davinci_nand_partitions[] = { - { - /* UBL (a few copies) plus U-Boot */ - .name = "bootloader", - .offset = 0, - .size = 30 * NAND_BLOCK_SIZE, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, { - /* U-Boot environment */ - .name = "params", - .offset = MTDPART_OFS_APPEND, - .size = 2 * NAND_BLOCK_SIZE, - .mask_flags = 0, - }, { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_4M, - .mask_flags = 0, - }, { - .name = "filesystem1", - .offset = MTDPART_OFS_APPEND, - .size = SZ_512M, - .mask_flags = 0, - }, { - .name = "filesystem2", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0, - } - /* two blocks with bad block table (and mirror) at the end */ -}; - -static struct davinci_nand_pdata davinci_nand_data = { - .core_chipsel = 0, - .mask_chipsel = BIT(14), - .parts = davinci_nand_partitions, - .nr_parts = ARRAY_SIZE(davinci_nand_partitions), - .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST, - .bbt_options = NAND_BBT_USE_FLASH, - .ecc_bits = 4, -}; - -static struct resource davinci_nand_resources[] = { - { - .start = DM365_ASYNC_EMIF_DATA_CE0_BASE, - .end = DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1, - .flags = IORESOURCE_MEM, - }, { - .start = DM365_ASYNC_EMIF_CONTROL_BASE, - .end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device davinci_aemif_devices[] = { - { - .name = "davinci_nand", - .id = 0, - .num_resources = ARRAY_SIZE(davinci_nand_resources), - .resource = davinci_nand_resources, - .dev = { - .platform_data = &davinci_nand_data, - }, - } -}; - -static struct resource davinci_aemif_resources[] = { - { - .start = DM365_ASYNC_EMIF_CONTROL_BASE, - .end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct aemif_abus_data da850_evm_aemif_abus_data[] = { - { - .cs = 1, - }, -}; - -static struct aemif_platform_data davinci_aemif_pdata = { - .abus_data = da850_evm_aemif_abus_data, - .num_abus_data = ARRAY_SIZE(da850_evm_aemif_abus_data), - .sub_devices = davinci_aemif_devices, - .num_sub_devices = ARRAY_SIZE(davinci_aemif_devices), -}; - -static struct platform_device davinci_aemif_device = { - .name = "ti-aemif", - .id = -1, - .dev = { - .platform_data = &davinci_aemif_pdata, - }, - .resource = davinci_aemif_resources, - .num_resources = ARRAY_SIZE(davinci_aemif_resources), -}; - -static struct nvmem_cell_info davinci_nvmem_cells[] = { - { - .name = "macaddr", - .offset = 0x7f00, - .bytes = ETH_ALEN, - } -}; - -static struct nvmem_cell_table davinci_nvmem_cell_table = { - .nvmem_name = "1-00500", - .cells = davinci_nvmem_cells, - .ncells = ARRAY_SIZE(davinci_nvmem_cells), -}; - -static struct nvmem_cell_lookup davinci_nvmem_cell_lookup = { - .nvmem_name = "1-00500", - .cell_name = "macaddr", - .dev_id = "davinci_emac.1", - .con_id = "mac-address", -}; - -static const struct property_entry eeprom_properties[] = { - PROPERTY_ENTRY_U32("pagesize", 64), - { } -}; - -static const struct software_node eeprom_node = { - .properties = eeprom_properties, -}; - -static struct i2c_board_info i2c_info[] = { - { - I2C_BOARD_INFO("24c256", 0x50), - .swnode = &eeprom_node, - }, - { - I2C_BOARD_INFO("tlv320aic3x", 0x18), - }, -}; - -static struct davinci_i2c_platform_data i2c_pdata = { - .bus_freq = 400 /* kHz */, - .bus_delay = 0 /* usec */, -}; - -/* Fixed regulator support */ -static struct regulator_consumer_supply fixed_supplies_3_3v[] = { - /* Baseboard 3.3V: 5V -> TPS767D301 -> 3.3V */ - REGULATOR_SUPPLY("AVDD", "1-0018"), - REGULATOR_SUPPLY("DRVDD", "1-0018"), - REGULATOR_SUPPLY("IOVDD", "1-0018"), -}; - -static struct regulator_consumer_supply fixed_supplies_1_8v[] = { - /* Baseboard 1.8V: 5V -> TPS767D301 -> 1.8V */ - REGULATOR_SUPPLY("DVDD", "1-0018"), -}; - -static int dm365evm_keyscan_enable(struct device *dev) -{ - return davinci_cfg_reg(DM365_KEYSCAN); -} - -static unsigned short dm365evm_keymap[] = { - KEY_KP2, - KEY_LEFT, - KEY_EXIT, - KEY_DOWN, - KEY_ENTER, - KEY_UP, - KEY_KP1, - KEY_RIGHT, - KEY_MENU, - KEY_RECORD, - KEY_REWIND, - KEY_KPMINUS, - KEY_STOP, - KEY_FASTFORWARD, - KEY_KPPLUS, - KEY_PLAYPAUSE, - 0 -}; - -static struct davinci_ks_platform_data dm365evm_ks_data = { - .device_enable = dm365evm_keyscan_enable, - .keymap = dm365evm_keymap, - .keymapsize = ARRAY_SIZE(dm365evm_keymap), - .rep = 1, - /* Scan period = strobe + interval */ - .strobe = 0x5, - .interval = 0x2, - .matrix_type = DAVINCI_KEYSCAN_MATRIX_4X4, -}; - -static int cpld_mmc_get_cd(int module) -{ - if (!cpld) - return -ENXIO; - - /* low == card present */ - return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0)); -} - -static int cpld_mmc_get_ro(int module) -{ - if (!cpld) - return -ENXIO; - - /* high == card's write protect switch active */ - return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1)); -} - -static struct davinci_mmc_config dm365evm_mmc_config = { - .get_cd = cpld_mmc_get_cd, - .get_ro = cpld_mmc_get_ro, - .wires = 4, - .max_freq = 50000000, - .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, -}; - -static void dm365evm_emac_configure(void) -{ - /* - * EMAC pins are multiplexed with GPIO and UART - * Further details are available at the DM365 ARM - * Subsystem Users Guide(sprufg5.pdf) pages 125 - 127 - */ - davinci_cfg_reg(DM365_EMAC_TX_EN); - davinci_cfg_reg(DM365_EMAC_TX_CLK); - davinci_cfg_reg(DM365_EMAC_COL); - davinci_cfg_reg(DM365_EMAC_TXD3); - davinci_cfg_reg(DM365_EMAC_TXD2); - davinci_cfg_reg(DM365_EMAC_TXD1); - davinci_cfg_reg(DM365_EMAC_TXD0); - davinci_cfg_reg(DM365_EMAC_RXD3); - davinci_cfg_reg(DM365_EMAC_RXD2); - davinci_cfg_reg(DM365_EMAC_RXD1); - davinci_cfg_reg(DM365_EMAC_RXD0); - davinci_cfg_reg(DM365_EMAC_RX_CLK); - davinci_cfg_reg(DM365_EMAC_RX_DV); - davinci_cfg_reg(DM365_EMAC_RX_ER); - davinci_cfg_reg(DM365_EMAC_CRS); - davinci_cfg_reg(DM365_EMAC_MDIO); - davinci_cfg_reg(DM365_EMAC_MDCLK); - - /* - * EMAC interrupts are multiplexed with GPIO interrupts - * Details are available at the DM365 ARM - * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134 - */ - davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH); - davinci_cfg_reg(DM365_INT_EMAC_RXPULSE); - davinci_cfg_reg(DM365_INT_EMAC_TXPULSE); - davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE); -} - -static void dm365evm_mmc_configure(void) -{ - /* - * MMC/SD pins are multiplexed with GPIO and EMIF - * Further details are available at the DM365 ARM - * Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131 - */ - davinci_cfg_reg(DM365_SD1_CLK); - davinci_cfg_reg(DM365_SD1_CMD); - davinci_cfg_reg(DM365_SD1_DATA3); - davinci_cfg_reg(DM365_SD1_DATA2); - davinci_cfg_reg(DM365_SD1_DATA1); - davinci_cfg_reg(DM365_SD1_DATA0); -} - -static struct tvp514x_platform_data tvp5146_pdata = { - .clk_polarity = 0, - .hs_polarity = 1, - .vs_polarity = 1 -}; - -#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) -/* Inputs available at the TVP5146 */ -static struct v4l2_input tvp5146_inputs[] = { - { - .index = 0, - .name = "Composite", - .type = V4L2_INPUT_TYPE_CAMERA, - .std = TVP514X_STD_ALL, - }, - { - .index = 1, - .name = "S-Video", - .type = V4L2_INPUT_TYPE_CAMERA, - .std = TVP514X_STD_ALL, - }, -}; - -/* - * this is the route info for connecting each input to decoder - * ouput that goes to vpfe. There is a one to one correspondence - * with tvp5146_inputs - */ -static struct vpfe_route tvp5146_routes[] = { - { - .input = INPUT_CVBS_VI2B, - .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, - }, -{ - .input = INPUT_SVIDEO_VI2C_VI1C, - .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, - }, -}; - -static struct vpfe_subdev_info vpfe_sub_devs[] = { - { - .name = "tvp5146", - .grp_id = 0, - .num_inputs = ARRAY_SIZE(tvp5146_inputs), - .inputs = tvp5146_inputs, - .routes = tvp5146_routes, - .can_route = 1, - .ccdc_if_params = { - .if_type = VPFE_BT656, - .hdpol = VPFE_PINPOL_POSITIVE, - .vdpol = VPFE_PINPOL_POSITIVE, - }, - .board_info = { - I2C_BOARD_INFO("tvp5146", 0x5d), - .platform_data = &tvp5146_pdata, - }, - }, -}; - -static struct vpfe_config vpfe_cfg = { - .num_subdevs = ARRAY_SIZE(vpfe_sub_devs), - .sub_devs = vpfe_sub_devs, - .i2c_adapter_id = 1, - .card_name = "DM365 EVM", - .ccdc = "ISIF", -}; - -/* venc standards timings */ -static struct vpbe_enc_mode_info dm365evm_enc_std_timing[] = { - { - .name = "ntsc", - .timings_type = VPBE_ENC_STD, - .std_id = V4L2_STD_NTSC, - .interlaced = 1, - .xres = 720, - .yres = 480, - .aspect = {11, 10}, - .fps = {30000, 1001}, - .left_margin = 0x79, - .upper_margin = 0x10, - }, - { - .name = "pal", - .timings_type = VPBE_ENC_STD, - .std_id = V4L2_STD_PAL, - .interlaced = 1, - .xres = 720, - .yres = 576, - .aspect = {54, 59}, - .fps = {25, 1}, - .left_margin = 0x7E, - .upper_margin = 0x16, - }, -}; - -/* venc dv timings */ -static struct vpbe_enc_mode_info dm365evm_enc_preset_timing[] = { - { - .name = "480p59_94", - .timings_type = VPBE_ENC_DV_TIMINGS, - .dv_timings = V4L2_DV_BT_CEA_720X480P59_94, - .interlaced = 0, - .xres = 720, - .yres = 480, - .aspect = {1, 1}, - .fps = {5994, 100}, - .left_margin = 0x8F, - .upper_margin = 0x2D, - }, - { - .name = "576p50", - .timings_type = VPBE_ENC_DV_TIMINGS, - .dv_timings = V4L2_DV_BT_CEA_720X576P50, - .interlaced = 0, - .xres = 720, - .yres = 576, - .aspect = {1, 1}, - .fps = {50, 1}, - .left_margin = 0x8C, - .upper_margin = 0x36, - }, - { - .name = "720p60", - .timings_type = VPBE_ENC_DV_TIMINGS, - .dv_timings = V4L2_DV_BT_CEA_1280X720P60, - .interlaced = 0, - .xres = 1280, - .yres = 720, - .aspect = {1, 1}, - .fps = {60, 1}, - .left_margin = 0x117, - .right_margin = 70, - .upper_margin = 38, - .lower_margin = 3, - .hsync_len = 80, - .vsync_len = 5, - }, - { - .name = "1080i60", - .timings_type = VPBE_ENC_DV_TIMINGS, - .dv_timings = V4L2_DV_BT_CEA_1920X1080I60, - .interlaced = 1, - .xres = 1920, - .yres = 1080, - .aspect = {1, 1}, - .fps = {30, 1}, - .left_margin = 0xc9, - .right_margin = 80, - .upper_margin = 30, - .lower_margin = 3, - .hsync_len = 88, - .vsync_len = 5, - }, -}; - -#define VENC_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) - -/* - * The outputs available from VPBE + ecnoders. Keep the - * the order same as that of encoders. First those from venc followed by that - * from encoders. Index in the output refers to index on a particular - * encoder.Driver uses this index to pass it to encoder when it supports more - * than one output. Application uses index of the array to set an output. - */ -static struct vpbe_output dm365evm_vpbe_outputs[] = { - { - .output = { - .index = 0, - .name = "Composite", - .type = V4L2_OUTPUT_TYPE_ANALOG, - .std = VENC_STD_ALL, - .capabilities = V4L2_OUT_CAP_STD, - }, - .subdev_name = DM365_VPBE_VENC_SUBDEV_NAME, - .default_mode = "ntsc", - .num_modes = ARRAY_SIZE(dm365evm_enc_std_timing), - .modes = dm365evm_enc_std_timing, - .if_params = MEDIA_BUS_FMT_FIXED, - }, - { - .output = { - .index = 1, - .name = "Component", - .type = V4L2_OUTPUT_TYPE_ANALOG, - .capabilities = V4L2_OUT_CAP_DV_TIMINGS, - }, - .subdev_name = DM365_VPBE_VENC_SUBDEV_NAME, - .default_mode = "480p59_94", - .num_modes = ARRAY_SIZE(dm365evm_enc_preset_timing), - .modes = dm365evm_enc_preset_timing, - .if_params = MEDIA_BUS_FMT_FIXED, - }, -}; - -/* - * Amplifiers on the board - */ -static struct ths7303_platform_data ths7303_pdata = { - .ch_1 = 3, - .ch_2 = 3, - .ch_3 = 3, -}; - -static struct amp_config_info vpbe_amp = { - .module_name = "ths7303", - .is_i2c = 1, - .board_info = { - I2C_BOARD_INFO("ths7303", 0x2c), - .platform_data = &ths7303_pdata, - } -}; - -static struct vpbe_config dm365evm_display_cfg = { - .module_name = "dm365-vpbe-display", - .i2c_adapter_id = 1, - .amp = &vpbe_amp, - .osd = { - .module_name = DM365_VPBE_OSD_SUBDEV_NAME, - }, - .venc = { - .module_name = DM365_VPBE_VENC_SUBDEV_NAME, - }, - .num_outputs = ARRAY_SIZE(dm365evm_vpbe_outputs), - .outputs = dm365evm_vpbe_outputs, -}; - -static void __init evm_init_i2c(void) -{ - davinci_init_i2c(&i2c_pdata); - i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info)); -} - -static inline int have_leds(void) -{ -#ifdef CONFIG_LEDS_CLASS - return 1; -#else - return 0; -#endif -} - -struct cpld_led { - struct led_classdev cdev; - u8 mask; -}; - -static const struct { - const char *name; - const char *trigger; -} cpld_leds[] = { - { "dm365evm::ds2", }, - { "dm365evm::ds3", }, - { "dm365evm::ds4", }, - { "dm365evm::ds5", }, - { "dm365evm::ds6", "nand-disk", }, - { "dm365evm::ds7", "mmc1", }, - { "dm365evm::ds8", "mmc0", }, - { "dm365evm::ds9", "heartbeat", }, -}; - -static void cpld_led_set(struct led_classdev *cdev, enum led_brightness b) -{ - struct cpld_led *led = container_of(cdev, struct cpld_led, cdev); - u8 reg = __raw_readb(cpld + CPLD_LEDS); - - if (b != LED_OFF) - reg &= ~led->mask; - else - reg |= led->mask; - __raw_writeb(reg, cpld + CPLD_LEDS); -} - -static enum led_brightness cpld_led_get(struct led_classdev *cdev) -{ - struct cpld_led *led = container_of(cdev, struct cpld_led, cdev); - u8 reg = __raw_readb(cpld + CPLD_LEDS); - - return (reg & led->mask) ? LED_OFF : LED_FULL; -} - -static int __init cpld_leds_init(void) -{ - int i; - - if (!have_leds() || !cpld) - return 0; - - /* setup LEDs */ - __raw_writeb(0xff, cpld + CPLD_LEDS); - for (i = 0; i < ARRAY_SIZE(cpld_leds); i++) { - struct cpld_led *led; - - led = kzalloc(sizeof(*led), GFP_KERNEL); - if (!led) - break; - - led->cdev.name = cpld_leds[i].name; - led->cdev.brightness_set = cpld_led_set; - led->cdev.brightness_get = cpld_led_get; - led->cdev.default_trigger = cpld_leds[i].trigger; - led->mask = BIT(i); - - if (led_classdev_register(NULL, &led->cdev) < 0) { - kfree(led); - break; - } - } - - return 0; -} -/* run after subsys_initcall() for LEDs */ -fs_initcall(cpld_leds_init); - - -static void __init evm_init_cpld(void) -{ - u8 mux, resets; - const char *label; - struct clk *aemif_clk; - int rc; - - /* Make sure we can configure the CPLD through CS1. Then - * leave it on for later access to MMC and LED registers. - */ - aemif_clk = clk_get(NULL, "aemif"); - if (IS_ERR(aemif_clk)) - return; - clk_prepare_enable(aemif_clk); - - if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE, - "cpld") == NULL) - goto fail; - cpld = ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE); - if (!cpld) { - release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, - SECTION_SIZE); -fail: - pr_err("ERROR: can't map CPLD\n"); - clk_disable_unprepare(aemif_clk); - return; - } - - /* External muxing for some signals */ - mux = 0; - - /* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read). - * NOTE: SW4 bus width setting must match! - */ - if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) { - /* external keypad mux */ - mux |= BIT(7); - - rc = platform_device_register(&davinci_aemif_device); - if (rc) - pr_warn("%s(): error registering the aemif device: %d\n", - __func__, rc); - } else { - /* no OneNAND support yet */ - } - - /* Leave external chips in reset when unused. */ - resets = BIT(3) | BIT(2) | BIT(1) | BIT(0); - - /* Static video input config with SN74CBT16214 1-of-3 mux: - * - port b1 == tvp7002 (mux lowbits == 1 or 6) - * - port b2 == imager (mux lowbits == 2 or 7) - * - port b3 == tvp5146 (mux lowbits == 5) - * - * Runtime switching could work too, with limitations. - */ - if (have_imager()) { - label = "HD imager"; - mux |= 2; - - /* externally mux MMC1/ENET/AIC33 to imager */ - mux |= BIT(6) | BIT(5) | BIT(3); - } else { - struct davinci_soc_info *soc_info = &davinci_soc_info; - - /* we can use MMC1 ... */ - dm365evm_mmc_configure(); - davinci_setup_mmc(1, &dm365evm_mmc_config); - - /* ... and ENET ... */ - dm365evm_emac_configure(); - soc_info->emac_pdata->phy_id = DM365_EVM_PHY_ID; - resets &= ~BIT(3); - - /* ... and AIC33 */ - resets &= ~BIT(1); - - if (have_tvp7002()) { - mux |= 1; - resets &= ~BIT(2); - label = "tvp7002 HD"; - } else { - /* default to tvp5146 */ - mux |= 5; - resets &= ~BIT(0); - label = "tvp5146 SD"; - } - } - __raw_writeb(mux, cpld + CPLD_MUX); - __raw_writeb(resets, cpld + CPLD_RESETS); - pr_info("EVM: %s video input\n", label); - - /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */ -} - -static void __init dm365_evm_map_io(void) -{ - dm365_init(); -} - -static struct spi_eeprom at25640 = { - .byte_len = SZ_64K / 8, - .name = "at25640", - .page_size = 32, - .flags = EE_ADDR2, -}; - -static const struct spi_board_info dm365_evm_spi_info[] __initconst = { - { - .modalias = "at25", - .platform_data = &at25640, - .max_speed_hz = 10 * 1000 * 1000, - .bus_num = 0, - .chip_select = 0, - .mode = SPI_MODE_0, - }, -}; - -static __init void dm365_evm_init(void) -{ - int ret; - - dm365_register_clocks(); - - ret = dm365_gpio_register(); - if (ret) - pr_warn("%s: GPIO init failed: %d\n", __func__, ret); - - regulator_register_always_on(0, "fixed-dummy", fixed_supplies_1_8v, - ARRAY_SIZE(fixed_supplies_1_8v), 1800000); - regulator_register_always_on(1, "fixed-dummy", fixed_supplies_3_3v, - ARRAY_SIZE(fixed_supplies_3_3v), 3300000); - - nvmem_add_cell_table(&davinci_nvmem_cell_table); - nvmem_add_cell_lookups(&davinci_nvmem_cell_lookup, 1); - - evm_init_i2c(); - davinci_serial_init(dm365_serial_device); - - dm365evm_emac_configure(); - dm365evm_mmc_configure(); - - davinci_setup_mmc(0, &dm365evm_mmc_config); - - dm365_init_video(&vpfe_cfg, &dm365evm_display_cfg); - - /* maybe setup mmc1/etc ... _after_ mmc0 */ - evm_init_cpld(); - -#ifdef CONFIG_SND_SOC_DM365_AIC3X_CODEC - dm365_init_asp(); -#elif defined(CONFIG_SND_SOC_DM365_VOICE_CODEC) - dm365_init_vc(); -#endif - dm365_init_rtc(); - dm365_init_ks(&dm365evm_ks_data); - - dm365_init_spi0(BIT(0), dm365_evm_spi_info, - ARRAY_SIZE(dm365_evm_spi_info)); -} - -MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM") - .atag_offset = 0x100, - .map_io = dm365_evm_map_io, - .init_irq = dm365_init_irq, - .init_time = dm365_init_time, - .init_machine = dm365_evm_init, - .init_late = davinci_init_late, - .dma_zone_size = SZ_128M, -MACHINE_END diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c deleted file mode 100644 index a46e7b9ff8e0..000000000000 --- a/arch/arm/mach-davinci/board-mityomapl138.c +++ /dev/null @@ -1,638 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Critical Link MityOMAP-L138 SoM - * - * Copyright (C) 2010 Critical Link LLC - https://www.criticallink.com - */ - -#define pr_fmt(fmt) "MityOMAPL138: " fmt - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "common.h" -#include "da8xx.h" -#include "mux.h" - -#include -#include -#include -#include - -#define MITYOMAPL138_PHY_ID "" - -#define FACTORY_CONFIG_MAGIC 0x012C0138 -#define FACTORY_CONFIG_VERSION 0x00010001 - -/* Data Held in On-Board I2C device */ -struct factory_config { - u32 magic; - u32 version; - u8 mac[6]; - u32 fpga_type; - u32 spare; - u32 serialnumber; - char partnum[32]; -}; - -static struct factory_config factory_config; - -#ifdef CONFIG_CPU_FREQ -struct part_no_info { - const char *part_no; /* part number string of interest */ - int max_freq; /* khz */ -}; - -static struct part_no_info mityomapl138_pn_info[] = { - { - .part_no = "L138-C", - .max_freq = 300000, - }, - { - .part_no = "L138-D", - .max_freq = 375000, - }, - { - .part_no = "L138-F", - .max_freq = 456000, - }, - { - .part_no = "1808-C", - .max_freq = 300000, - }, - { - .part_no = "1808-D", - .max_freq = 375000, - }, - { - .part_no = "1808-F", - .max_freq = 456000, - }, - { - .part_no = "1810-D", - .max_freq = 375000, - }, -}; - -static void mityomapl138_cpufreq_init(const char *partnum) -{ - int i, ret; - - for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) { - /* - * the part number has additional characters beyond what is - * stored in the table. This information is not needed for - * determining the speed grade, and would require several - * more table entries. Only check the first N characters - * for a match. - */ - if (!strncmp(partnum, mityomapl138_pn_info[i].part_no, - strlen(mityomapl138_pn_info[i].part_no))) { - da850_max_speed = mityomapl138_pn_info[i].max_freq; - break; - } - } - - ret = da850_register_cpufreq("pll0_sysclk3"); - if (ret) - pr_warn("cpufreq registration failed: %d\n", ret); -} -#else -static void mityomapl138_cpufreq_init(const char *partnum) { } -#endif - -static int read_factory_config(struct notifier_block *nb, - unsigned long event, void *data) -{ - int ret; - const char *partnum = NULL; - struct nvmem_device *nvmem = data; - - if (strcmp(nvmem_dev_name(nvmem), "1-00500") != 0) - return NOTIFY_DONE; - - if (!IS_BUILTIN(CONFIG_NVMEM)) { - pr_warn("Factory Config not available without CONFIG_NVMEM\n"); - goto bad_config; - } - - ret = nvmem_device_read(nvmem, 0, sizeof(factory_config), - &factory_config); - if (ret != sizeof(struct factory_config)) { - pr_warn("Read Factory Config Failed: %d\n", ret); - goto bad_config; - } - - if (factory_config.magic != FACTORY_CONFIG_MAGIC) { - pr_warn("Factory Config Magic Wrong (%X)\n", - factory_config.magic); - goto bad_config; - } - - if (factory_config.version != FACTORY_CONFIG_VERSION) { - pr_warn("Factory Config Version Wrong (%X)\n", - factory_config.version); - goto bad_config; - } - - partnum = factory_config.partnum; - pr_info("Part Number = %s\n", partnum); - -bad_config: - /* default maximum speed is valid for all platforms */ - mityomapl138_cpufreq_init(partnum); - - return NOTIFY_STOP; -} - -static struct notifier_block mityomapl138_nvmem_notifier = { - .notifier_call = read_factory_config, -}; - -/* - * We don't define a cell for factory config as it will be accessed from the - * board file using the nvmem notifier chain. - */ -static struct nvmem_cell_info mityomapl138_nvmem_cells[] = { - { - .name = "macaddr", - .offset = 0x64, - .bytes = ETH_ALEN, - } -}; - -static struct nvmem_cell_table mityomapl138_nvmem_cell_table = { - .nvmem_name = "1-00500", - .cells = mityomapl138_nvmem_cells, - .ncells = ARRAY_SIZE(mityomapl138_nvmem_cells), -}; - -static struct nvmem_cell_lookup mityomapl138_nvmem_cell_lookup = { - .nvmem_name = "1-00500", - .cell_name = "macaddr", - .dev_id = "davinci_emac.1", - .con_id = "mac-address", -}; - -static const struct property_entry mityomapl138_fd_chip_properties[] = { - PROPERTY_ENTRY_U32("pagesize", 8), - PROPERTY_ENTRY_BOOL("read-only"), - { } -}; - -static const struct software_node mityomapl138_fd_chip_node = { - .properties = mityomapl138_fd_chip_properties, -}; - -static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = { - .bus_freq = 100, /* kHz */ - .bus_delay = 0, /* usec */ -}; - -/* TPS65023 voltage regulator support */ -/* 1.2V Core */ -static struct regulator_consumer_supply tps65023_dcdc1_consumers[] = { - { - .supply = "cvdd", - }, -}; - -/* 1.8V */ -static struct regulator_consumer_supply tps65023_dcdc2_consumers[] = { - { - .supply = "usb0_vdda18", - }, - { - .supply = "usb1_vdda18", - }, - { - .supply = "ddr_dvdd18", - }, - { - .supply = "sata_vddr", - }, -}; - -/* 1.2V */ -static struct regulator_consumer_supply tps65023_dcdc3_consumers[] = { - { - .supply = "sata_vdd", - }, - { - .supply = "usb_cvdd", - }, - { - .supply = "pll0_vdda", - }, - { - .supply = "pll1_vdda", - }, -}; - -/* 1.8V Aux LDO, not used */ -static struct regulator_consumer_supply tps65023_ldo1_consumers[] = { - { - .supply = "1.8v_aux", - }, -}; - -/* FPGA VCC Aux (2.5 or 3.3) LDO */ -static struct regulator_consumer_supply tps65023_ldo2_consumers[] = { - { - .supply = "vccaux", - }, -}; - -static struct regulator_init_data tps65023_regulator_data[] = { - /* dcdc1 */ - { - .constraints = { - .min_uV = 1150000, - .max_uV = 1350000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers), - .consumer_supplies = tps65023_dcdc1_consumers, - }, - /* dcdc2 */ - { - .constraints = { - .min_uV = 1800000, - .max_uV = 1800000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers), - .consumer_supplies = tps65023_dcdc2_consumers, - }, - /* dcdc3 */ - { - .constraints = { - .min_uV = 1200000, - .max_uV = 1200000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers), - .consumer_supplies = tps65023_dcdc3_consumers, - }, - /* ldo1 */ - { - .constraints = { - .min_uV = 1800000, - .max_uV = 1800000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers), - .consumer_supplies = tps65023_ldo1_consumers, - }, - /* ldo2 */ - { - .constraints = { - .min_uV = 2500000, - .max_uV = 3300000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers), - .consumer_supplies = tps65023_ldo2_consumers, - }, -}; - -static struct i2c_board_info __initdata mityomap_tps65023_info[] = { - { - I2C_BOARD_INFO("tps65023", 0x48), - .platform_data = &tps65023_regulator_data[0], - }, - { - I2C_BOARD_INFO("24c02", 0x50), - .swnode = &mityomapl138_fd_chip_node, - }, -}; - -static int __init pmic_tps65023_init(void) -{ - return i2c_register_board_info(1, mityomap_tps65023_info, - ARRAY_SIZE(mityomap_tps65023_info)); -} - -/* - * SPI Devices: - * SPI1_CS0: 8M Flash ST-M25P64-VME6G - */ -static struct mtd_partition spi_flash_partitions[] = { - [0] = { - .name = "ubl", - .offset = 0, - .size = SZ_64K, - .mask_flags = MTD_WRITEABLE, - }, - [1] = { - .name = "u-boot", - .offset = MTDPART_OFS_APPEND, - .size = SZ_512K, - .mask_flags = MTD_WRITEABLE, - }, - [2] = { - .name = "u-boot-env", - .offset = MTDPART_OFS_APPEND, - .size = SZ_64K, - .mask_flags = MTD_WRITEABLE, - }, - [3] = { - .name = "periph-config", - .offset = MTDPART_OFS_APPEND, - .size = SZ_64K, - .mask_flags = MTD_WRITEABLE, - }, - [4] = { - .name = "reserved", - .offset = MTDPART_OFS_APPEND, - .size = SZ_256K + SZ_64K, - }, - [5] = { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_2M + SZ_1M, - }, - [6] = { - .name = "fpga", - .offset = MTDPART_OFS_APPEND, - .size = SZ_2M, - }, - [7] = { - .name = "spare", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - }, -}; - -static struct flash_platform_data mityomapl138_spi_flash_data = { - .name = "m25p80", - .parts = spi_flash_partitions, - .nr_parts = ARRAY_SIZE(spi_flash_partitions), - .type = "m24p64", -}; - -static struct davinci_spi_config spi_eprom_config = { - .io_type = SPI_IO_TYPE_DMA, - .c2tdelay = 8, - .t2cdelay = 8, -}; - -static struct spi_board_info mityomapl138_spi_flash_info[] = { - { - .modalias = "m25p80", - .platform_data = &mityomapl138_spi_flash_data, - .controller_data = &spi_eprom_config, - .mode = SPI_MODE_0, - .max_speed_hz = 30000000, - .bus_num = 1, - .chip_select = 0, - }, -}; - -/* - * MityDSP-L138 includes a 256 MByte large-page NAND flash - * (128K blocks). - */ -static struct mtd_partition mityomapl138_nandflash_partition[] = { - { - .name = "rootfs", - .offset = 0, - .size = SZ_128M, - .mask_flags = 0, /* MTD_WRITEABLE, */ - }, - { - .name = "homefs", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0, - }, -}; - -static struct davinci_nand_pdata mityomapl138_nandflash_data = { - .core_chipsel = 1, - .parts = mityomapl138_nandflash_partition, - .nr_parts = ARRAY_SIZE(mityomapl138_nandflash_partition), - .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST, - .bbt_options = NAND_BBT_USE_FLASH, - .options = NAND_BUSWIDTH_16, - .ecc_bits = 1, /* 4 bit mode is not supported with 16 bit NAND */ -}; - -static struct resource mityomapl138_nandflash_resource[] = { - { - .start = DA8XX_AEMIF_CS3_BASE, - .end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = DA8XX_AEMIF_CTL_BASE, - .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device mityomapl138_aemif_devices[] = { - { - .name = "davinci_nand", - .id = 1, - .dev = { - .platform_data = &mityomapl138_nandflash_data, - }, - .num_resources = ARRAY_SIZE(mityomapl138_nandflash_resource), - .resource = mityomapl138_nandflash_resource, - }, -}; - -static struct resource mityomapl138_aemif_resources[] = { - { - .start = DA8XX_AEMIF_CTL_BASE, - .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct aemif_abus_data mityomapl138_aemif_abus_data[] = { - { - .cs = 1, - }, -}; - -static struct aemif_platform_data mityomapl138_aemif_pdata = { - .abus_data = mityomapl138_aemif_abus_data, - .num_abus_data = ARRAY_SIZE(mityomapl138_aemif_abus_data), - .sub_devices = mityomapl138_aemif_devices, - .num_sub_devices = ARRAY_SIZE(mityomapl138_aemif_devices), -}; - -static struct platform_device mityomapl138_aemif_device = { - .name = "ti-aemif", - .id = -1, - .dev = { - .platform_data = &mityomapl138_aemif_pdata, - }, - .resource = mityomapl138_aemif_resources, - .num_resources = ARRAY_SIZE(mityomapl138_aemif_resources), -}; - -static void __init mityomapl138_setup_nand(void) -{ - if (platform_device_register(&mityomapl138_aemif_device)) - pr_warn("%s: Cannot register AEMIF device\n", __func__); -} - -static const short mityomap_mii_pins[] = { - DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3, - DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER, - DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3, - DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK, - DA850_MDIO_D, - -1 -}; - -static const short mityomap_rmii_pins[] = { - DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN, - DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1, - DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK, - DA850_MDIO_D, - -1 -}; - -static void __init mityomapl138_config_emac(void) -{ - void __iomem *cfg_chip3_base; - int ret; - u32 val; - struct davinci_soc_info *soc_info = &davinci_soc_info; - - soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */ - - cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG); - val = __raw_readl(cfg_chip3_base); - - if (soc_info->emac_pdata->rmii_en) { - val |= BIT(8); - ret = davinci_cfg_reg_list(mityomap_rmii_pins); - pr_info("RMII PHY configured\n"); - } else { - val &= ~BIT(8); - ret = davinci_cfg_reg_list(mityomap_mii_pins); - pr_info("MII PHY configured\n"); - } - - if (ret) { - pr_warn("mii/rmii mux setup failed: %d\n", ret); - return; - } - - /* configure the CFGCHIP3 register for RMII or MII */ - __raw_writel(val, cfg_chip3_base); - - soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID; - - ret = da8xx_register_emac(); - if (ret) - pr_warn("emac registration failed: %d\n", ret); -} - -static void __init mityomapl138_init(void) -{ - int ret; - - da850_register_clocks(); - - /* for now, no special EDMA channels are reserved */ - ret = da850_register_edma(NULL); - if (ret) - pr_warn("edma registration failed: %d\n", ret); - - ret = da8xx_register_watchdog(); - if (ret) - pr_warn("watchdog registration failed: %d\n", ret); - - davinci_serial_init(da8xx_serial_device); - - nvmem_register_notifier(&mityomapl138_nvmem_notifier); - nvmem_add_cell_table(&mityomapl138_nvmem_cell_table); - nvmem_add_cell_lookups(&mityomapl138_nvmem_cell_lookup, 1); - - ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata); - if (ret) - pr_warn("i2c0 registration failed: %d\n", ret); - - ret = pmic_tps65023_init(); - if (ret) - pr_warn("TPS65023 PMIC init failed: %d\n", ret); - - mityomapl138_setup_nand(); - - ret = spi_register_board_info(mityomapl138_spi_flash_info, - ARRAY_SIZE(mityomapl138_spi_flash_info)); - if (ret) - pr_warn("spi info registration failed: %d\n", ret); - - ret = da8xx_register_spi_bus(1, - ARRAY_SIZE(mityomapl138_spi_flash_info)); - if (ret) - pr_warn("spi 1 registration failed: %d\n", ret); - - mityomapl138_config_emac(); - - ret = da8xx_register_rtc(); - if (ret) - pr_warn("rtc setup failed: %d\n", ret); - - ret = da8xx_register_cpuidle(); - if (ret) - pr_warn("cpuidle registration failed: %d\n", ret); - - davinci_pm_init(); -} - -#ifdef CONFIG_SERIAL_8250_CONSOLE -static int __init mityomapl138_console_init(void) -{ - if (!machine_is_mityomapl138()) - return 0; - - return add_preferred_console("ttyS", 1, "115200"); -} -console_initcall(mityomapl138_console_init); -#endif - -static void __init mityomapl138_map_io(void) -{ - da850_init(); -} - -MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808") - .atag_offset = 0x100, - .map_io = mityomapl138_map_io, - .init_irq = da850_init_irq, - .init_time = da850_init_time, - .init_machine = mityomapl138_init, - .init_late = davinci_init_late, - .dma_zone_size = SZ_128M, -MACHINE_END diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c deleted file mode 100644 index 8a80115999ad..000000000000 --- a/arch/arm/mach-davinci/board-omapl138-hawk.c +++ /dev/null @@ -1,451 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Hawkboard.org based on TI's OMAP-L138 Platform - * - * Initial code: Syed Mohammed Khasim - * - * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "common.h" -#include "da8xx.h" -#include "mux.h" - -#define HAWKBOARD_PHY_ID "davinci_mdio-0:07" - -#define DA850_USB1_VBUS_PIN GPIO_TO_PIN(2, 4) -#define DA850_USB1_OC_PIN GPIO_TO_PIN(6, 13) - -static short omapl138_hawk_mii_pins[] __initdata = { - DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3, - DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER, - DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3, - DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK, - DA850_MDIO_D, - -1 -}; - -static __init void omapl138_hawk_config_emac(void) -{ - void __iomem *cfgchip3 = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG); - int ret; - u32 val; - struct davinci_soc_info *soc_info = &davinci_soc_info; - - val = __raw_readl(cfgchip3); - val &= ~BIT(8); - ret = davinci_cfg_reg_list(omapl138_hawk_mii_pins); - if (ret) { - pr_warn("%s: CPGMAC/MII mux setup failed: %d\n", __func__, ret); - return; - } - - /* configure the CFGCHIP3 register for MII */ - __raw_writel(val, cfgchip3); - pr_info("EMAC: MII PHY configured\n"); - - soc_info->emac_pdata->phy_id = HAWKBOARD_PHY_ID; - - ret = da8xx_register_emac(); - if (ret) - pr_warn("%s: EMAC registration failed: %d\n", __func__, ret); -} - -/* - * The following EDMA channels/slots are not being used by drivers (for - * example: Timer, GPIO, UART events etc) on da850/omap-l138 EVM/Hawkboard, - * hence they are being reserved for codecs on the DSP side. - */ -static const s16 da850_dma0_rsv_chans[][2] = { - /* (offset, number) */ - { 8, 6}, - {24, 4}, - {30, 2}, - {-1, -1} -}; - -static const s16 da850_dma0_rsv_slots[][2] = { - /* (offset, number) */ - { 8, 6}, - {24, 4}, - {30, 50}, - {-1, -1} -}; - -static const s16 da850_dma1_rsv_chans[][2] = { - /* (offset, number) */ - { 0, 28}, - {30, 2}, - {-1, -1} -}; - -static const s16 da850_dma1_rsv_slots[][2] = { - /* (offset, number) */ - { 0, 28}, - {30, 90}, - {-1, -1} -}; - -static struct edma_rsv_info da850_edma_cc0_rsv = { - .rsv_chans = da850_dma0_rsv_chans, - .rsv_slots = da850_dma0_rsv_slots, -}; - -static struct edma_rsv_info da850_edma_cc1_rsv = { - .rsv_chans = da850_dma1_rsv_chans, - .rsv_slots = da850_dma1_rsv_slots, -}; - -static struct edma_rsv_info *da850_edma_rsv[2] = { - &da850_edma_cc0_rsv, - &da850_edma_cc1_rsv, -}; - -static const short hawk_mmcsd0_pins[] = { - DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2, - DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD, - DA850_GPIO3_12, DA850_GPIO3_13, - -1 -}; - -#define DA850_HAWK_MMCSD_CD_PIN GPIO_TO_PIN(3, 12) -#define DA850_HAWK_MMCSD_WP_PIN GPIO_TO_PIN(3, 13) - -static struct gpiod_lookup_table mmc_gpios_table = { - .dev_id = "da830-mmc.0", - .table = { - GPIO_LOOKUP("davinci_gpio", DA850_HAWK_MMCSD_CD_PIN, "cd", - GPIO_ACTIVE_LOW), - GPIO_LOOKUP("davinci_gpio", DA850_HAWK_MMCSD_WP_PIN, "wp", - GPIO_ACTIVE_LOW), - }, -}; - -static struct davinci_mmc_config da850_mmc_config = { - .wires = 4, - .max_freq = 50000000, - .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, -}; - -static __init void omapl138_hawk_mmc_init(void) -{ - int ret; - - ret = davinci_cfg_reg_list(hawk_mmcsd0_pins); - if (ret) { - pr_warn("%s: MMC/SD0 mux setup failed: %d\n", __func__, ret); - return; - } - - gpiod_add_lookup_table(&mmc_gpios_table); - - ret = da8xx_register_mmcsd0(&da850_mmc_config); - if (ret) { - pr_warn("%s: MMC/SD0 registration failed: %d\n", __func__, ret); - goto mmc_setup_mmcsd_fail; - } - - return; - -mmc_setup_mmcsd_fail: - gpiod_remove_lookup_table(&mmc_gpios_table); -} - -static struct mtd_partition omapl138_hawk_nandflash_partition[] = { - { - .name = "u-boot env", - .offset = 0, - .size = SZ_128K, - .mask_flags = MTD_WRITEABLE, - }, - { - .name = "u-boot", - .offset = MTDPART_OFS_APPEND, - .size = SZ_512K, - .mask_flags = MTD_WRITEABLE, - }, - { - .name = "free space", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0, - }, -}; - -static struct davinci_aemif_timing omapl138_hawk_nandflash_timing = { - .wsetup = 24, - .wstrobe = 21, - .whold = 14, - .rsetup = 19, - .rstrobe = 50, - .rhold = 0, - .ta = 20, -}; - -static struct davinci_nand_pdata omapl138_hawk_nandflash_data = { - .core_chipsel = 1, - .parts = omapl138_hawk_nandflash_partition, - .nr_parts = ARRAY_SIZE(omapl138_hawk_nandflash_partition), - .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST, - .ecc_bits = 4, - .bbt_options = NAND_BBT_USE_FLASH, - .options = NAND_BUSWIDTH_16, - .timing = &omapl138_hawk_nandflash_timing, - .mask_chipsel = 0, - .mask_ale = 0, - .mask_cle = 0, -}; - -static struct resource omapl138_hawk_nandflash_resource[] = { - { - .start = DA8XX_AEMIF_CS3_BASE, - .end = DA8XX_AEMIF_CS3_BASE + SZ_32M, - .flags = IORESOURCE_MEM, - }, - { - .start = DA8XX_AEMIF_CTL_BASE, - .end = DA8XX_AEMIF_CTL_BASE + SZ_32K, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource omapl138_hawk_aemif_resource[] = { - { - .start = DA8XX_AEMIF_CTL_BASE, - .end = DA8XX_AEMIF_CTL_BASE + SZ_32K, - .flags = IORESOURCE_MEM, - } -}; - -static struct aemif_abus_data omapl138_hawk_aemif_abus_data[] = { - { - .cs = 3, - } -}; - -static struct platform_device omapl138_hawk_aemif_devices[] = { - { - .name = "davinci_nand", - .id = -1, - .dev = { - .platform_data = &omapl138_hawk_nandflash_data, - }, - .resource = omapl138_hawk_nandflash_resource, - .num_resources = ARRAY_SIZE(omapl138_hawk_nandflash_resource), - } -}; - -static struct aemif_platform_data omapl138_hawk_aemif_pdata = { - .cs_offset = 2, - .abus_data = omapl138_hawk_aemif_abus_data, - .num_abus_data = ARRAY_SIZE(omapl138_hawk_aemif_abus_data), - .sub_devices = omapl138_hawk_aemif_devices, - .num_sub_devices = ARRAY_SIZE(omapl138_hawk_aemif_devices), -}; - -static struct platform_device omapl138_hawk_aemif_device = { - .name = "ti-aemif", - .id = -1, - .dev = { - .platform_data = &omapl138_hawk_aemif_pdata, - }, - .resource = omapl138_hawk_aemif_resource, - .num_resources = ARRAY_SIZE(omapl138_hawk_aemif_resource), -}; - -static const short omapl138_hawk_nand_pins[] = { - DA850_EMA_WAIT_1, DA850_NEMA_OE, DA850_NEMA_WE, DA850_NEMA_CS_3, - DA850_EMA_D_0, DA850_EMA_D_1, DA850_EMA_D_2, DA850_EMA_D_3, - DA850_EMA_D_4, DA850_EMA_D_5, DA850_EMA_D_6, DA850_EMA_D_7, - DA850_EMA_D_8, DA850_EMA_D_9, DA850_EMA_D_10, DA850_EMA_D_11, - DA850_EMA_D_12, DA850_EMA_D_13, DA850_EMA_D_14, DA850_EMA_D_15, - DA850_EMA_A_1, DA850_EMA_A_2, - -1 -}; - -static int omapl138_hawk_register_aemif(void) -{ - int ret; - - ret = davinci_cfg_reg_list(omapl138_hawk_nand_pins); - if (ret) - pr_warn("%s: NAND mux setup failed: %d\n", __func__, ret); - - return platform_device_register(&omapl138_hawk_aemif_device); -} - -static const short da850_hawk_usb11_pins[] = { - DA850_GPIO2_4, DA850_GPIO6_13, - -1 -}; - -static struct regulator_consumer_supply hawk_usb_supplies[] = { - REGULATOR_SUPPLY("vbus", NULL), -}; - -static struct regulator_init_data hawk_usb_vbus_data = { - .consumer_supplies = hawk_usb_supplies, - .num_consumer_supplies = ARRAY_SIZE(hawk_usb_supplies), - .constraints = { - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, -}; - -static struct fixed_voltage_config hawk_usb_vbus = { - .supply_name = "vbus", - .microvolts = 3300000, - .init_data = &hawk_usb_vbus_data, -}; - -static struct platform_device hawk_usb_vbus_device = { - .name = "reg-fixed-voltage", - .id = 0, - .dev = { - .platform_data = &hawk_usb_vbus, - }, -}; - -static struct gpiod_lookup_table hawk_usb_oc_gpio_lookup = { - .dev_id = "ohci-da8xx", - .table = { - GPIO_LOOKUP("davinci_gpio", DA850_USB1_OC_PIN, "oc", 0), - { } - }, -}; - -static struct gpiod_lookup_table hawk_usb_vbus_gpio_lookup = { - .dev_id = "reg-fixed-voltage.0", - .table = { - GPIO_LOOKUP("davinci_gpio", DA850_USB1_VBUS_PIN, NULL, 0), - { } - }, -}; - -static struct gpiod_lookup_table *hawk_usb_gpio_lookups[] = { - &hawk_usb_oc_gpio_lookup, - &hawk_usb_vbus_gpio_lookup, -}; - -static struct da8xx_ohci_root_hub omapl138_hawk_usb11_pdata = { - /* TPS2087 switch @ 5V */ - .potpgt = (3 + 1) / 2, /* 3 ms max */ -}; - -static __init void omapl138_hawk_usb_init(void) -{ - int ret; - - ret = davinci_cfg_reg_list(da850_hawk_usb11_pins); - if (ret) { - pr_warn("%s: USB 1.1 PinMux setup failed: %d\n", __func__, ret); - return; - } - - ret = da8xx_register_usb_phy_clocks(); - if (ret) - pr_warn("%s: USB PHY CLK registration failed: %d\n", - __func__, ret); - - gpiod_add_lookup_tables(hawk_usb_gpio_lookups, - ARRAY_SIZE(hawk_usb_gpio_lookups)); - - ret = da8xx_register_usb_phy(); - if (ret) - pr_warn("%s: USB PHY registration failed: %d\n", - __func__, ret); - - ret = platform_device_register(&hawk_usb_vbus_device); - if (ret) { - pr_warn("%s: Unable to register the vbus supply\n", __func__); - return; - } - - ret = da8xx_register_usb11(&omapl138_hawk_usb11_pdata); - if (ret) - pr_warn("%s: USB 1.1 registration failed: %d\n", __func__, ret); - - return; -} - -static __init void omapl138_hawk_init(void) -{ - int ret; - - da850_register_clocks(); - - ret = da850_register_gpio(); - if (ret) - pr_warn("%s: GPIO init failed: %d\n", __func__, ret); - - davinci_serial_init(da8xx_serial_device); - - omapl138_hawk_config_emac(); - - ret = da850_register_edma(da850_edma_rsv); - if (ret) - pr_warn("%s: EDMA registration failed: %d\n", __func__, ret); - - omapl138_hawk_mmc_init(); - - omapl138_hawk_usb_init(); - - ret = omapl138_hawk_register_aemif(); - if (ret) - pr_warn("%s: aemif registration failed: %d\n", __func__, ret); - - ret = da8xx_register_watchdog(); - if (ret) - pr_warn("%s: watchdog registration failed: %d\n", - __func__, ret); - - ret = da8xx_register_rproc(); - if (ret) - pr_warn("%s: dsp/rproc registration failed: %d\n", - __func__, ret); - - regulator_has_full_constraints(); -} - -#ifdef CONFIG_SERIAL_8250_CONSOLE -static int __init omapl138_hawk_console_init(void) -{ - if (!machine_is_omapl138_hawkboard()) - return 0; - - return add_preferred_console("ttyS", 2, "115200"); -} -console_initcall(omapl138_hawk_console_init); -#endif - -static void __init omapl138_hawk_map_io(void) -{ - da850_init(); -} - -MACHINE_START(OMAPL138_HAWKBOARD, "AM18x/OMAP-L138 Hawkboard") - .atag_offset = 0x100, - .map_io = omapl138_hawk_map_io, - .init_irq = da850_init_irq, - .init_time = da850_init_time, - .init_machine = omapl138_hawk_init, - .init_late = davinci_init_late, - .dma_zone_size = SZ_128M, - .reserve = da8xx_rproc_reserve_cma, -MACHINE_END diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c deleted file mode 100644 index 199c26d9a2b6..000000000000 --- a/arch/arm/mach-davinci/devices.c +++ /dev/null @@ -1,303 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * mach-davinci/devices.c - * - * DaVinci platform device setup/initialization - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "hardware.h" -#include "cputype.h" -#include "mux.h" -#include "davinci.h" -#include "irqs.h" - -#define DAVINCI_I2C_BASE 0x01C21000 -#define DAVINCI_ATA_BASE 0x01C66000 -#define DAVINCI_MMCSD0_BASE 0x01E10000 -#define DM355_MMCSD0_BASE 0x01E11000 -#define DM355_MMCSD1_BASE 0x01E00000 -#define DM365_MMCSD0_BASE 0x01D11000 -#define DM365_MMCSD1_BASE 0x01D00000 - -void __iomem *davinci_sysmod_base; - -void davinci_map_sysmod(void) -{ - davinci_sysmod_base = ioremap(DAVINCI_SYSTEM_MODULE_BASE, - 0x800); - /* - * Throw a bug since a lot of board initialization code depends - * on system module availability. ioremap() failing this early - * need careful looking into anyway. - */ - BUG_ON(!davinci_sysmod_base); -} - -static struct resource i2c_resources[] = { - { - .start = DAVINCI_I2C_BASE, - .end = DAVINCI_I2C_BASE + 0x40, - .flags = IORESOURCE_MEM, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_I2C), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device davinci_i2c_device = { - .name = "i2c_davinci", - .id = 1, - .num_resources = ARRAY_SIZE(i2c_resources), - .resource = i2c_resources, -}; - -void __init davinci_init_i2c(struct davinci_i2c_platform_data *pdata) -{ - if (cpu_is_davinci_dm644x()) - davinci_cfg_reg(DM644X_I2C); - - davinci_i2c_device.dev.platform_data = pdata; - (void) platform_device_register(&davinci_i2c_device); -} - -static struct resource ide_resources[] = { - { - .start = DAVINCI_ATA_BASE, - .end = DAVINCI_ATA_BASE + 0x7ff, - .flags = IORESOURCE_MEM, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_IDE), - .end = DAVINCI_INTC_IRQ(IRQ_IDE), - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 ide_dma_mask = DMA_BIT_MASK(32); - -static struct platform_device ide_device = { - .name = "palm_bk3710", - .id = -1, - .resource = ide_resources, - .num_resources = ARRAY_SIZE(ide_resources), - .dev = { - .dma_mask = &ide_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -void __init davinci_init_ide(void) -{ - if (cpu_is_davinci_dm644x()) { - davinci_cfg_reg(DM644X_HPIEN_DISABLE); - davinci_cfg_reg(DM644X_ATAEN); - davinci_cfg_reg(DM644X_HDIREN); - } else if (cpu_is_davinci_dm646x()) { - /* IRQ_DM646X_IDE is the same as IRQ_IDE */ - davinci_cfg_reg(DM646X_ATAEN); - } else { - WARN_ON(1); - return; - } - - platform_device_register(&ide_device); -} - -#if IS_ENABLED(CONFIG_MMC_DAVINCI) - -static u64 mmcsd0_dma_mask = DMA_BIT_MASK(32); - -static struct resource mmcsd0_resources[] = { - { - /* different on dm355 */ - .start = DAVINCI_MMCSD0_BASE, - .end = DAVINCI_MMCSD0_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - /* IRQs: MMC/SD, then SDIO */ - { - .start = DAVINCI_INTC_IRQ(IRQ_MMCINT), - .flags = IORESOURCE_IRQ, - }, { - /* different on dm355 */ - .start = DAVINCI_INTC_IRQ(IRQ_SDIOINT), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device davinci_mmcsd0_device = { - .name = "dm6441-mmc", - .id = 0, - .dev = { - .dma_mask = &mmcsd0_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(mmcsd0_resources), - .resource = mmcsd0_resources, -}; - -static u64 mmcsd1_dma_mask = DMA_BIT_MASK(32); - -static struct resource mmcsd1_resources[] = { - { - .start = DM355_MMCSD1_BASE, - .end = DM355_MMCSD1_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - /* IRQs: MMC/SD, then SDIO */ - { - .start = DAVINCI_INTC_IRQ(IRQ_DM355_MMCINT1), - .flags = IORESOURCE_IRQ, - }, { - .start = DAVINCI_INTC_IRQ(IRQ_DM355_SDIOINT1), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device davinci_mmcsd1_device = { - .name = "dm6441-mmc", - .id = 1, - .dev = { - .dma_mask = &mmcsd1_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(mmcsd1_resources), - .resource = mmcsd1_resources, -}; - - -void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config) -{ - struct platform_device *pdev = NULL; - - if (WARN_ON(cpu_is_davinci_dm646x())) - return; - - /* REVISIT: update PINMUX, ARM_IRQMUX, and EDMA_EVTMUX here too; - * for example if MMCSD1 is used for SDIO, maybe DAT2 is unused. - * - * FIXME dm6441 (no MMC/SD), dm357 (one), and dm335 (two) are - * not handled right here ... - */ - switch (module) { - case 1: - if (cpu_is_davinci_dm355()) { - /* REVISIT we may not need all these pins if e.g. this - * is a hard-wired SDIO device... - */ - davinci_cfg_reg(DM355_SD1_CMD); - davinci_cfg_reg(DM355_SD1_CLK); - davinci_cfg_reg(DM355_SD1_DATA0); - davinci_cfg_reg(DM355_SD1_DATA1); - davinci_cfg_reg(DM355_SD1_DATA2); - davinci_cfg_reg(DM355_SD1_DATA3); - } else if (cpu_is_davinci_dm365()) { - /* Configure pull down control */ - unsigned v; - - v = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_PUPDCTL1)); - __raw_writel(v & ~0xfc0, - DAVINCI_SYSMOD_VIRT(SYSMOD_PUPDCTL1)); - - mmcsd1_resources[0].start = DM365_MMCSD1_BASE; - mmcsd1_resources[0].end = DM365_MMCSD1_BASE + - SZ_4K - 1; - mmcsd1_resources[2].start = DAVINCI_INTC_IRQ( - IRQ_DM365_SDIOINT1); - davinci_mmcsd1_device.name = "da830-mmc"; - } else - break; - - pdev = &davinci_mmcsd1_device; - break; - case 0: - if (cpu_is_davinci_dm355()) { - mmcsd0_resources[0].start = DM355_MMCSD0_BASE; - mmcsd0_resources[0].end = DM355_MMCSD0_BASE + SZ_4K - 1; - mmcsd0_resources[2].start = DAVINCI_INTC_IRQ( - IRQ_DM355_SDIOINT0); - - /* expose all 6 MMC0 signals: CLK, CMD, DATA[0..3] */ - davinci_cfg_reg(DM355_MMCSD0); - - /* enable RX EDMA */ - davinci_cfg_reg(DM355_EVT26_MMC0_RX); - } else if (cpu_is_davinci_dm365()) { - mmcsd0_resources[0].start = DM365_MMCSD0_BASE; - mmcsd0_resources[0].end = DM365_MMCSD0_BASE + - SZ_4K - 1; - mmcsd0_resources[2].start = DAVINCI_INTC_IRQ( - IRQ_DM365_SDIOINT0); - davinci_mmcsd0_device.name = "da830-mmc"; - } else if (cpu_is_davinci_dm644x()) { - /* REVISIT: should this be in board-init code? */ - /* Power-on 3.3V IO cells */ - __raw_writel(0, - DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN)); - /*Set up the pull regiter for MMC */ - davinci_cfg_reg(DM644X_MSTK); - } - - pdev = &davinci_mmcsd0_device; - break; - } - - if (WARN_ON(!pdev)) - return; - - pdev->dev.platform_data = config; - platform_device_register(pdev); -} - -#else - -void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config) -{ -} - -#endif - -/*-------------------------------------------------------------------------*/ - -static struct resource wdt_resources[] = { - { - .start = DAVINCI_WDOG_BASE, - .end = DAVINCI_WDOG_BASE + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device davinci_wdt_device = { - .name = "davinci-wdt", - .id = -1, - .num_resources = ARRAY_SIZE(wdt_resources), - .resource = wdt_resources, -}; - -int davinci_init_wdt(void) -{ - return platform_device_register(&davinci_wdt_device); -} - -static struct platform_device davinci_gpio_device = { - .name = "davinci_gpio", - .id = -1, -}; - -int davinci_gpio_register(struct resource *res, int size, void *pdata) -{ - davinci_gpio_device.resource = res; - davinci_gpio_device.num_resources = size; - davinci_gpio_device.dev.platform_data = pdata; - return platform_device_register(&davinci_gpio_device); -} diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c deleted file mode 100644 index a12ba859beca..000000000000 --- a/arch/arm/mach-davinci/dm355.c +++ /dev/null @@ -1,832 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * TI DaVinci DM355 chip specific setup - * - * Author: Kevin Hilman, Deep Root Systems, LLC - * - * 2007 (c) Deep Root Systems, LLC. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include - -#include "common.h" -#include "cputype.h" -#include "serial.h" -#include "asp.h" -#include "davinci.h" -#include "irqs.h" -#include "mux.h" - -#define DM355_UART2_BASE (IO_PHYS + 0x206000) -#define DM355_OSD_BASE (IO_PHYS + 0x70200) -#define DM355_VENC_BASE (IO_PHYS + 0x70400) - -/* - * Device specific clocks - */ -#define DM355_REF_FREQ 24000000 /* 24 or 36 MHz */ - -static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32); - -static struct resource dm355_spi0_resources[] = { - { - .start = 0x01c66000, - .end = 0x01c667ff, - .flags = IORESOURCE_MEM, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM355_SPINT0_0), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct davinci_spi_platform_data dm355_spi0_pdata = { - .version = SPI_VERSION_1, - .num_chipselect = 2, - .cshold_bug = true, - .dma_event_q = EVENTQ_1, - .prescaler_limit = 1, -}; -static struct platform_device dm355_spi0_device = { - .name = "spi_davinci", - .id = 0, - .dev = { - .dma_mask = &dm355_spi0_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &dm355_spi0_pdata, - }, - .num_resources = ARRAY_SIZE(dm355_spi0_resources), - .resource = dm355_spi0_resources, -}; - -void __init dm355_init_spi0(unsigned chipselect_mask, - const struct spi_board_info *info, unsigned len) -{ - /* for now, assume we need MISO */ - davinci_cfg_reg(DM355_SPI0_SDI); - - /* not all slaves will be wired up */ - if (chipselect_mask & BIT(0)) - davinci_cfg_reg(DM355_SPI0_SDENA0); - if (chipselect_mask & BIT(1)) - davinci_cfg_reg(DM355_SPI0_SDENA1); - - spi_register_board_info(info, len); - - platform_device_register(&dm355_spi0_device); -} - -/*----------------------------------------------------------------------*/ - -#define INTMUX 0x18 -#define EVTMUX 0x1c - -/* - * Device specific mux setup - * - * soc description mux mode mode mux dbg - * reg offset mask mode - */ -static const struct mux_config dm355_pins[] = { -#ifdef CONFIG_DAVINCI_MUX -MUX_CFG(DM355, MMCSD0, 4, 2, 1, 0, false) - -MUX_CFG(DM355, SD1_CLK, 3, 6, 1, 1, false) -MUX_CFG(DM355, SD1_CMD, 3, 7, 1, 1, false) -MUX_CFG(DM355, SD1_DATA3, 3, 8, 3, 1, false) -MUX_CFG(DM355, SD1_DATA2, 3, 10, 3, 1, false) -MUX_CFG(DM355, SD1_DATA1, 3, 12, 3, 1, false) -MUX_CFG(DM355, SD1_DATA0, 3, 14, 3, 1, false) - -MUX_CFG(DM355, I2C_SDA, 3, 19, 1, 1, false) -MUX_CFG(DM355, I2C_SCL, 3, 20, 1, 1, false) - -MUX_CFG(DM355, MCBSP0_BDX, 3, 0, 1, 1, false) -MUX_CFG(DM355, MCBSP0_X, 3, 1, 1, 1, false) -MUX_CFG(DM355, MCBSP0_BFSX, 3, 2, 1, 1, false) -MUX_CFG(DM355, MCBSP0_BDR, 3, 3, 1, 1, false) -MUX_CFG(DM355, MCBSP0_R, 3, 4, 1, 1, false) -MUX_CFG(DM355, MCBSP0_BFSR, 3, 5, 1, 1, false) - -MUX_CFG(DM355, SPI0_SDI, 4, 1, 1, 0, false) -MUX_CFG(DM355, SPI0_SDENA0, 4, 0, 1, 0, false) -MUX_CFG(DM355, SPI0_SDENA1, 3, 28, 1, 1, false) - -INT_CFG(DM355, INT_EDMA_CC, 2, 1, 1, false) -INT_CFG(DM355, INT_EDMA_TC0_ERR, 3, 1, 1, false) -INT_CFG(DM355, INT_EDMA_TC1_ERR, 4, 1, 1, false) - -EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false) -EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false) -EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false) - -MUX_CFG(DM355, VOUT_FIELD, 1, 18, 3, 1, false) -MUX_CFG(DM355, VOUT_FIELD_G70, 1, 18, 3, 0, false) -MUX_CFG(DM355, VOUT_HVSYNC, 1, 16, 1, 0, false) -MUX_CFG(DM355, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false) -MUX_CFG(DM355, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false) - -MUX_CFG(DM355, VIN_PCLK, 0, 14, 1, 1, false) -MUX_CFG(DM355, VIN_CAM_WEN, 0, 13, 1, 1, false) -MUX_CFG(DM355, VIN_CAM_VD, 0, 12, 1, 1, false) -MUX_CFG(DM355, VIN_CAM_HD, 0, 11, 1, 1, false) -MUX_CFG(DM355, VIN_YIN_EN, 0, 10, 1, 1, false) -MUX_CFG(DM355, VIN_CINL_EN, 0, 0, 0xff, 0x55, false) -MUX_CFG(DM355, VIN_CINH_EN, 0, 8, 3, 3, false) -#endif -}; - -static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = { - [IRQ_DM355_CCDC_VDINT0] = 2, - [IRQ_DM355_CCDC_VDINT1] = 6, - [IRQ_DM355_CCDC_VDINT2] = 6, - [IRQ_DM355_IPIPE_HST] = 6, - [IRQ_DM355_H3AINT] = 6, - [IRQ_DM355_IPIPE_SDR] = 6, - [IRQ_DM355_IPIPEIFINT] = 6, - [IRQ_DM355_OSDINT] = 7, - [IRQ_DM355_VENCINT] = 6, - [IRQ_ASQINT] = 6, - [IRQ_IMXINT] = 6, - [IRQ_USBINT] = 4, - [IRQ_DM355_RTOINT] = 4, - [IRQ_DM355_UARTINT2] = 7, - [IRQ_DM355_TINT6] = 7, - [IRQ_CCINT0] = 5, /* dma */ - [IRQ_CCERRINT] = 5, /* dma */ - [IRQ_TCERRINT0] = 5, /* dma */ - [IRQ_TCERRINT] = 5, /* dma */ - [IRQ_DM355_SPINT2_1] = 7, - [IRQ_DM355_TINT7] = 4, - [IRQ_DM355_SDIOINT0] = 7, - [IRQ_MBXINT] = 7, - [IRQ_MBRINT] = 7, - [IRQ_MMCINT] = 7, - [IRQ_DM355_MMCINT1] = 7, - [IRQ_DM355_PWMINT3] = 7, - [IRQ_DDRINT] = 7, - [IRQ_AEMIFINT] = 7, - [IRQ_DM355_SDIOINT1] = 4, - [IRQ_TINT0_TINT12] = 2, /* clockevent */ - [IRQ_TINT0_TINT34] = 2, /* clocksource */ - [IRQ_TINT1_TINT12] = 7, /* DSP timer */ - [IRQ_TINT1_TINT34] = 7, /* system tick */ - [IRQ_PWMINT0] = 7, - [IRQ_PWMINT1] = 7, - [IRQ_PWMINT2] = 7, - [IRQ_I2C] = 3, - [IRQ_UARTINT0] = 3, - [IRQ_UARTINT1] = 3, - [IRQ_DM355_SPINT0_0] = 3, - [IRQ_DM355_SPINT0_1] = 3, - [IRQ_DM355_GPIO0] = 3, - [IRQ_DM355_GPIO1] = 7, - [IRQ_DM355_GPIO2] = 4, - [IRQ_DM355_GPIO3] = 4, - [IRQ_DM355_GPIO4] = 7, - [IRQ_DM355_GPIO5] = 7, - [IRQ_DM355_GPIO6] = 7, - [IRQ_DM355_GPIO7] = 7, - [IRQ_DM355_GPIO8] = 7, - [IRQ_DM355_GPIO9] = 7, - [IRQ_DM355_GPIOBNK0] = 7, - [IRQ_DM355_GPIOBNK1] = 7, - [IRQ_DM355_GPIOBNK2] = 7, - [IRQ_DM355_GPIOBNK3] = 7, - [IRQ_DM355_GPIOBNK4] = 7, - [IRQ_DM355_GPIOBNK5] = 7, - [IRQ_DM355_GPIOBNK6] = 7, - [IRQ_COMMTX] = 7, - [IRQ_COMMRX] = 7, - [IRQ_EMUINT] = 7, -}; - -/*----------------------------------------------------------------------*/ - -static s8 queue_priority_mapping[][2] = { - /* {event queue no, Priority} */ - {0, 3}, - {1, 7}, - {-1, -1}, -}; - -static const struct dma_slave_map dm355_edma_map[] = { - { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 2) }, - { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 3) }, - { "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 8) }, - { "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 9) }, - { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) }, - { "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) }, - { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) }, - { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) }, - { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) }, - { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) }, - { "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) }, - { "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) }, - { "dm6441-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) }, - { "dm6441-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) }, -}; - -static struct edma_soc_info dm355_edma_pdata = { - .queue_priority_mapping = queue_priority_mapping, - .default_queue = EVENTQ_1, - .slave_map = dm355_edma_map, - .slavecnt = ARRAY_SIZE(dm355_edma_map), -}; - -static struct resource edma_resources[] = { - { - .name = "edma3_cc", - .start = 0x01c00000, - .end = 0x01c00000 + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma3_tc0", - .start = 0x01c10000, - .end = 0x01c10000 + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma3_tc1", - .start = 0x01c10400, - .end = 0x01c10400 + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma3_ccint", - .start = DAVINCI_INTC_IRQ(IRQ_CCINT0), - .flags = IORESOURCE_IRQ, - }, - { - .name = "edma3_ccerrint", - .start = DAVINCI_INTC_IRQ(IRQ_CCERRINT), - .flags = IORESOURCE_IRQ, - }, - /* not using (or muxing) TC*_ERR */ -}; - -static const struct platform_device_info dm355_edma_device __initconst = { - .name = "edma", - .id = 0, - .dma_mask = DMA_BIT_MASK(32), - .res = edma_resources, - .num_res = ARRAY_SIZE(edma_resources), - .data = &dm355_edma_pdata, - .size_data = sizeof(dm355_edma_pdata), -}; - -static struct resource dm355_asp1_resources[] = { - { - .name = "mpu", - .start = DAVINCI_ASP1_BASE, - .end = DAVINCI_ASP1_BASE + SZ_8K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = DAVINCI_DMA_ASP1_TX, - .end = DAVINCI_DMA_ASP1_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = DAVINCI_DMA_ASP1_RX, - .end = DAVINCI_DMA_ASP1_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device dm355_asp1_device = { - .name = "davinci-mcbsp", - .id = 1, - .num_resources = ARRAY_SIZE(dm355_asp1_resources), - .resource = dm355_asp1_resources, -}; - -static void dm355_ccdc_setup_pinmux(void) -{ - davinci_cfg_reg(DM355_VIN_PCLK); - davinci_cfg_reg(DM355_VIN_CAM_WEN); - davinci_cfg_reg(DM355_VIN_CAM_VD); - davinci_cfg_reg(DM355_VIN_CAM_HD); - davinci_cfg_reg(DM355_VIN_YIN_EN); - davinci_cfg_reg(DM355_VIN_CINL_EN); - davinci_cfg_reg(DM355_VIN_CINH_EN); -} - -static struct resource dm355_vpss_resources[] = { - { - /* VPSS BL Base address */ - .name = "vpss", - .start = 0x01c70800, - .end = 0x01c70800 + 0xff, - .flags = IORESOURCE_MEM, - }, - { - /* VPSS CLK Base address */ - .name = "vpss", - .start = 0x01c70000, - .end = 0x01c70000 + 0xf, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device dm355_vpss_device = { - .name = "vpss", - .id = -1, - .dev.platform_data = "dm355_vpss", - .num_resources = ARRAY_SIZE(dm355_vpss_resources), - .resource = dm355_vpss_resources, -}; - -static struct resource vpfe_resources[] = { - { - .start = DAVINCI_INTC_IRQ(IRQ_VDINT0), - .end = DAVINCI_INTC_IRQ(IRQ_VDINT0), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_VDINT1), - .end = DAVINCI_INTC_IRQ(IRQ_VDINT1), - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32); -static struct resource dm355_ccdc_resource[] = { - /* CCDC Base address */ - { - .flags = IORESOURCE_MEM, - .start = 0x01c70600, - .end = 0x01c70600 + 0x1ff, - }, -}; -static struct platform_device dm355_ccdc_dev = { - .name = "dm355_ccdc", - .id = -1, - .num_resources = ARRAY_SIZE(dm355_ccdc_resource), - .resource = dm355_ccdc_resource, - .dev = { - .dma_mask = &vpfe_capture_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = dm355_ccdc_setup_pinmux, - }, -}; - -static struct platform_device vpfe_capture_dev = { - .name = CAPTURE_DRV_NAME, - .id = -1, - .num_resources = ARRAY_SIZE(vpfe_resources), - .resource = vpfe_resources, - .dev = { - .dma_mask = &vpfe_capture_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct resource dm355_osd_resources[] = { - { - .start = DM355_OSD_BASE, - .end = DM355_OSD_BASE + 0x17f, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device dm355_osd_dev = { - .name = DM355_VPBE_OSD_SUBDEV_NAME, - .id = -1, - .num_resources = ARRAY_SIZE(dm355_osd_resources), - .resource = dm355_osd_resources, - .dev = { - .dma_mask = &vpfe_capture_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct resource dm355_venc_resources[] = { - { - .start = DAVINCI_INTC_IRQ(IRQ_VENCINT), - .end = DAVINCI_INTC_IRQ(IRQ_VENCINT), - .flags = IORESOURCE_IRQ, - }, - /* venc registers io space */ - { - .start = DM355_VENC_BASE, - .end = DM355_VENC_BASE + 0x17f, - .flags = IORESOURCE_MEM, - }, - /* VDAC config register io space */ - { - .start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG, - .end = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource dm355_v4l2_disp_resources[] = { - { - .start = DAVINCI_INTC_IRQ(IRQ_VENCINT), - .end = DAVINCI_INTC_IRQ(IRQ_VENCINT), - .flags = IORESOURCE_IRQ, - }, - /* venc registers io space */ - { - .start = DM355_VENC_BASE, - .end = DM355_VENC_BASE + 0x17f, - .flags = IORESOURCE_MEM, - }, -}; - -static int dm355_vpbe_setup_pinmux(u32 if_type, int field) -{ - switch (if_type) { - case MEDIA_BUS_FMT_SGRBG8_1X8: - davinci_cfg_reg(DM355_VOUT_FIELD_G70); - break; - case MEDIA_BUS_FMT_YUYV10_1X20: - if (field) - davinci_cfg_reg(DM355_VOUT_FIELD); - else - davinci_cfg_reg(DM355_VOUT_FIELD_G70); - break; - default: - return -EINVAL; - } - - davinci_cfg_reg(DM355_VOUT_COUTL_EN); - davinci_cfg_reg(DM355_VOUT_COUTH_EN); - - return 0; -} - -static int dm355_venc_setup_clock(enum vpbe_enc_timings_type type, - unsigned int pclock) -{ - void __iomem *vpss_clk_ctrl_reg; - - vpss_clk_ctrl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL); - - switch (type) { - case VPBE_ENC_STD: - writel(VPSS_DACCLKEN_ENABLE | VPSS_VENCCLKEN_ENABLE, - vpss_clk_ctrl_reg); - break; - case VPBE_ENC_DV_TIMINGS: - if (pclock > 27000000) - /* - * For HD, use external clock source since we cannot - * support HD mode with internal clocks. - */ - writel(VPSS_MUXSEL_EXTCLK_ENABLE, vpss_clk_ctrl_reg); - break; - default: - return -EINVAL; - } - - return 0; -} - -static struct platform_device dm355_vpbe_display = { - .name = "vpbe-v4l2", - .id = -1, - .num_resources = ARRAY_SIZE(dm355_v4l2_disp_resources), - .resource = dm355_v4l2_disp_resources, - .dev = { - .dma_mask = &vpfe_capture_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct venc_platform_data dm355_venc_pdata = { - .setup_pinmux = dm355_vpbe_setup_pinmux, - .setup_clock = dm355_venc_setup_clock, -}; - -static struct platform_device dm355_venc_dev = { - .name = DM355_VPBE_VENC_SUBDEV_NAME, - .id = -1, - .num_resources = ARRAY_SIZE(dm355_venc_resources), - .resource = dm355_venc_resources, - .dev = { - .dma_mask = &vpfe_capture_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = (void *)&dm355_venc_pdata, - }, -}; - -static struct platform_device dm355_vpbe_dev = { - .name = "vpbe_controller", - .id = -1, - .dev = { - .dma_mask = &vpfe_capture_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct resource dm355_gpio_resources[] = { - { /* registers */ - .start = DAVINCI_GPIO_BASE, - .end = DAVINCI_GPIO_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - { /* interrupt */ - .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK0), - .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK0), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK1), - .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK1), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK2), - .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK2), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK3), - .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK3), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK4), - .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK4), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK5), - .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK5), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK6), - .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK6), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct davinci_gpio_platform_data dm355_gpio_platform_data = { - .no_auto_base = true, - .base = 0, - .ngpio = 104, -}; - -int __init dm355_gpio_register(void) -{ - return davinci_gpio_register(dm355_gpio_resources, - ARRAY_SIZE(dm355_gpio_resources), - &dm355_gpio_platform_data); -} -/*----------------------------------------------------------------------*/ - -static struct map_desc dm355_io_desc[] = { - { - .virtual = IO_VIRT, - .pfn = __phys_to_pfn(IO_PHYS), - .length = IO_SIZE, - .type = MT_DEVICE - }, -}; - -/* Contents of JTAG ID register used to identify exact cpu type */ -static struct davinci_id dm355_ids[] = { - { - .variant = 0x0, - .part_no = 0xb73b, - .manufacturer = 0x00f, - .cpu_id = DAVINCI_CPU_ID_DM355, - .name = "dm355", - }, -}; - -/* - * Bottom half of timer0 is used for clockevent, top half is used for - * clocksource. - */ -static const struct davinci_timer_cfg dm355_timer_cfg = { - .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K), - .irq = { - DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)), - DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)), - }, -}; - -static struct plat_serial8250_port dm355_serial0_platform_data[] = { - { - .mapbase = DAVINCI_UART0_BASE, - .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0), - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_IOREMAP, - .iotype = UPIO_MEM, - .regshift = 2, - }, - { - .flags = 0, - } -}; -static struct plat_serial8250_port dm355_serial1_platform_data[] = { - { - .mapbase = DAVINCI_UART1_BASE, - .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1), - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_IOREMAP, - .iotype = UPIO_MEM, - .regshift = 2, - }, - { - .flags = 0, - } -}; -static struct plat_serial8250_port dm355_serial2_platform_data[] = { - { - .mapbase = DM355_UART2_BASE, - .irq = DAVINCI_INTC_IRQ(IRQ_DM355_UARTINT2), - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_IOREMAP, - .iotype = UPIO_MEM, - .regshift = 2, - }, - { - .flags = 0, - } -}; - -struct platform_device dm355_serial_device[] = { - { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = dm355_serial0_platform_data, - } - }, - { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM1, - .dev = { - .platform_data = dm355_serial1_platform_data, - } - }, - { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM2, - .dev = { - .platform_data = dm355_serial2_platform_data, - } - }, - { - } -}; - -static const struct davinci_soc_info davinci_soc_info_dm355 = { - .io_desc = dm355_io_desc, - .io_desc_num = ARRAY_SIZE(dm355_io_desc), - .jtag_id_reg = 0x01c40028, - .ids = dm355_ids, - .ids_num = ARRAY_SIZE(dm355_ids), - .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE, - .pinmux_pins = dm355_pins, - .pinmux_pins_num = ARRAY_SIZE(dm355_pins), - .sram_dma = 0x00010000, - .sram_len = SZ_32K, -}; - -void __init dm355_init_asp1(u32 evt_enable) -{ - /* we don't use ASP1 IRQs, or we'd need to mux them ... */ - if (evt_enable & ASP1_TX_EVT_EN) - davinci_cfg_reg(DM355_EVT8_ASP1_TX); - - if (evt_enable & ASP1_RX_EVT_EN) - davinci_cfg_reg(DM355_EVT9_ASP1_RX); - - platform_device_register(&dm355_asp1_device); -} - -void __init dm355_init(void) -{ - davinci_common_init(&davinci_soc_info_dm355); - davinci_map_sysmod(); -} - -void __init dm355_init_time(void) -{ - void __iomem *pll1, *psc; - struct clk *clk; - int rv; - - clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM355_REF_FREQ); - - pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K); - dm355_pll1_init(NULL, pll1, NULL); - - psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K); - dm355_psc_init(NULL, psc); - - clk = clk_get(NULL, "timer0"); - if (WARN_ON(IS_ERR(clk))) { - pr_err("Unable to get the timer clock\n"); - return; - } - - rv = davinci_timer_register(clk, &dm355_timer_cfg); - WARN(rv, "Unable to register the timer: %d\n", rv); -} - -static struct resource dm355_pll2_resources[] = { - { - .start = DAVINCI_PLL2_BASE, - .end = DAVINCI_PLL2_BASE + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device dm355_pll2_device = { - .name = "dm355-pll2", - .id = -1, - .resource = dm355_pll2_resources, - .num_resources = ARRAY_SIZE(dm355_pll2_resources), -}; - -void __init dm355_register_clocks(void) -{ - /* PLL1 and PSC are registered in dm355_init_time() */ - platform_device_register(&dm355_pll2_device); -} - -int __init dm355_init_video(struct vpfe_config *vpfe_cfg, - struct vpbe_config *vpbe_cfg) -{ - if (vpfe_cfg || vpbe_cfg) - platform_device_register(&dm355_vpss_device); - - if (vpfe_cfg) { - vpfe_capture_dev.dev.platform_data = vpfe_cfg; - platform_device_register(&dm355_ccdc_dev); - platform_device_register(&vpfe_capture_dev); - } - - if (vpbe_cfg) { - dm355_vpbe_dev.dev.platform_data = vpbe_cfg; - platform_device_register(&dm355_osd_dev); - platform_device_register(&dm355_venc_dev); - platform_device_register(&dm355_vpbe_dev); - platform_device_register(&dm355_vpbe_display); - } - - return 0; -} - -static const struct davinci_aintc_config dm355_aintc_config = { - .reg = { - .start = DAVINCI_ARM_INTC_BASE, - .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - .num_irqs = 64, - .prios = dm355_default_priorities, -}; - -void __init dm355_init_irq(void) -{ - davinci_aintc_init(&dm355_aintc_config); -} - -static int __init dm355_init_devices(void) -{ - struct platform_device *edma_pdev; - int ret = 0; - - if (!cpu_is_davinci_dm355()) - return 0; - - davinci_cfg_reg(DM355_INT_EDMA_CC); - edma_pdev = platform_device_register_full(&dm355_edma_device); - if (IS_ERR(edma_pdev)) { - pr_warn("%s: Failed to register eDMA\n", __func__); - return PTR_ERR(edma_pdev); - } - - ret = davinci_init_wdt(); - if (ret) - pr_warn("%s: watchdog init failed: %d\n", __func__, ret); - - return ret; -} -postcore_initcall(dm355_init_devices); diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c deleted file mode 100644 index 7538bb87f373..000000000000 --- a/arch/arm/mach-davinci/dm365.c +++ /dev/null @@ -1,1094 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * TI DaVinci DM365 chip specific setup - * - * Copyright (C) 2009 Texas Instruments - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include - -#include "common.h" -#include "cputype.h" -#include "serial.h" -#include "asp.h" -#include "davinci.h" -#include "irqs.h" -#include "mux.h" - -#define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */ -#define DM365_RTC_BASE 0x01c69000 -#define DM365_KEYSCAN_BASE 0x01c69400 -#define DM365_OSD_BASE 0x01c71c00 -#define DM365_VENC_BASE 0x01c71e00 -#define DAVINCI_DM365_VC_BASE 0x01d0c000 -#define DAVINCI_DMA_VC_TX 2 -#define DAVINCI_DMA_VC_RX 3 -#define DM365_EMAC_BASE 0x01d07000 -#define DM365_EMAC_MDIO_BASE (DM365_EMAC_BASE + 0x4000) -#define DM365_EMAC_CNTRL_OFFSET 0x0000 -#define DM365_EMAC_CNTRL_MOD_OFFSET 0x3000 -#define DM365_EMAC_CNTRL_RAM_OFFSET 0x1000 -#define DM365_EMAC_CNTRL_RAM_SIZE 0x2000 - -#define INTMUX 0x18 -#define EVTMUX 0x1c - - -static const struct mux_config dm365_pins[] = { -#ifdef CONFIG_DAVINCI_MUX -MUX_CFG(DM365, MMCSD0, 0, 24, 1, 0, false) - -MUX_CFG(DM365, SD1_CLK, 0, 16, 3, 1, false) -MUX_CFG(DM365, SD1_CMD, 4, 30, 3, 1, false) -MUX_CFG(DM365, SD1_DATA3, 4, 28, 3, 1, false) -MUX_CFG(DM365, SD1_DATA2, 4, 26, 3, 1, false) -MUX_CFG(DM365, SD1_DATA1, 4, 24, 3, 1, false) -MUX_CFG(DM365, SD1_DATA0, 4, 22, 3, 1, false) - -MUX_CFG(DM365, I2C_SDA, 3, 23, 3, 2, false) -MUX_CFG(DM365, I2C_SCL, 3, 21, 3, 2, false) - -MUX_CFG(DM365, AEMIF_AR_A14, 2, 0, 3, 1, false) -MUX_CFG(DM365, AEMIF_AR_BA0, 2, 0, 3, 2, false) -MUX_CFG(DM365, AEMIF_A3, 2, 2, 3, 1, false) -MUX_CFG(DM365, AEMIF_A7, 2, 4, 3, 1, false) -MUX_CFG(DM365, AEMIF_D15_8, 2, 6, 1, 1, false) -MUX_CFG(DM365, AEMIF_CE0, 2, 7, 1, 0, false) -MUX_CFG(DM365, AEMIF_CE1, 2, 8, 1, 0, false) -MUX_CFG(DM365, AEMIF_WE_OE, 2, 9, 1, 0, false) - -MUX_CFG(DM365, MCBSP0_BDX, 0, 23, 1, 1, false) -MUX_CFG(DM365, MCBSP0_X, 0, 22, 1, 1, false) -MUX_CFG(DM365, MCBSP0_BFSX, 0, 21, 1, 1, false) -MUX_CFG(DM365, MCBSP0_BDR, 0, 20, 1, 1, false) -MUX_CFG(DM365, MCBSP0_R, 0, 19, 1, 1, false) -MUX_CFG(DM365, MCBSP0_BFSR, 0, 18, 1, 1, false) - -MUX_CFG(DM365, SPI0_SCLK, 3, 28, 1, 1, false) -MUX_CFG(DM365, SPI0_SDI, 3, 26, 3, 1, false) -MUX_CFG(DM365, SPI0_SDO, 3, 25, 1, 1, false) -MUX_CFG(DM365, SPI0_SDENA0, 3, 29, 3, 1, false) -MUX_CFG(DM365, SPI0_SDENA1, 3, 26, 3, 2, false) - -MUX_CFG(DM365, UART0_RXD, 3, 20, 1, 1, false) -MUX_CFG(DM365, UART0_TXD, 3, 19, 1, 1, false) -MUX_CFG(DM365, UART1_RXD, 3, 17, 3, 2, false) -MUX_CFG(DM365, UART1_TXD, 3, 15, 3, 2, false) -MUX_CFG(DM365, UART1_RTS, 3, 23, 3, 1, false) -MUX_CFG(DM365, UART1_CTS, 3, 21, 3, 1, false) - -MUX_CFG(DM365, EMAC_TX_EN, 3, 17, 3, 1, false) -MUX_CFG(DM365, EMAC_TX_CLK, 3, 15, 3, 1, false) -MUX_CFG(DM365, EMAC_COL, 3, 14, 1, 1, false) -MUX_CFG(DM365, EMAC_TXD3, 3, 13, 1, 1, false) -MUX_CFG(DM365, EMAC_TXD2, 3, 12, 1, 1, false) -MUX_CFG(DM365, EMAC_TXD1, 3, 11, 1, 1, false) -MUX_CFG(DM365, EMAC_TXD0, 3, 10, 1, 1, false) -MUX_CFG(DM365, EMAC_RXD3, 3, 9, 1, 1, false) -MUX_CFG(DM365, EMAC_RXD2, 3, 8, 1, 1, false) -MUX_CFG(DM365, EMAC_RXD1, 3, 7, 1, 1, false) -MUX_CFG(DM365, EMAC_RXD0, 3, 6, 1, 1, false) -MUX_CFG(DM365, EMAC_RX_CLK, 3, 5, 1, 1, false) -MUX_CFG(DM365, EMAC_RX_DV, 3, 4, 1, 1, false) -MUX_CFG(DM365, EMAC_RX_ER, 3, 3, 1, 1, false) -MUX_CFG(DM365, EMAC_CRS, 3, 2, 1, 1, false) -MUX_CFG(DM365, EMAC_MDIO, 3, 1, 1, 1, false) -MUX_CFG(DM365, EMAC_MDCLK, 3, 0, 1, 1, false) - -MUX_CFG(DM365, KEYSCAN, 2, 0, 0x3f, 0x3f, false) - -MUX_CFG(DM365, PWM0, 1, 0, 3, 2, false) -MUX_CFG(DM365, PWM0_G23, 3, 26, 3, 3, false) -MUX_CFG(DM365, PWM1, 1, 2, 3, 2, false) -MUX_CFG(DM365, PWM1_G25, 3, 29, 3, 2, false) -MUX_CFG(DM365, PWM2_G87, 1, 10, 3, 2, false) -MUX_CFG(DM365, PWM2_G88, 1, 8, 3, 2, false) -MUX_CFG(DM365, PWM2_G89, 1, 6, 3, 2, false) -MUX_CFG(DM365, PWM2_G90, 1, 4, 3, 2, false) -MUX_CFG(DM365, PWM3_G80, 1, 20, 3, 3, false) -MUX_CFG(DM365, PWM3_G81, 1, 18, 3, 3, false) -MUX_CFG(DM365, PWM3_G85, 1, 14, 3, 2, false) -MUX_CFG(DM365, PWM3_G86, 1, 12, 3, 2, false) - -MUX_CFG(DM365, SPI1_SCLK, 4, 2, 3, 1, false) -MUX_CFG(DM365, SPI1_SDI, 3, 31, 1, 1, false) -MUX_CFG(DM365, SPI1_SDO, 4, 0, 3, 1, false) -MUX_CFG(DM365, SPI1_SDENA0, 4, 4, 3, 1, false) -MUX_CFG(DM365, SPI1_SDENA1, 4, 0, 3, 2, false) - -MUX_CFG(DM365, SPI2_SCLK, 4, 10, 3, 1, false) -MUX_CFG(DM365, SPI2_SDI, 4, 6, 3, 1, false) -MUX_CFG(DM365, SPI2_SDO, 4, 8, 3, 1, false) -MUX_CFG(DM365, SPI2_SDENA0, 4, 12, 3, 1, false) -MUX_CFG(DM365, SPI2_SDENA1, 4, 8, 3, 2, false) - -MUX_CFG(DM365, SPI3_SCLK, 0, 0, 3, 2, false) -MUX_CFG(DM365, SPI3_SDI, 0, 2, 3, 2, false) -MUX_CFG(DM365, SPI3_SDO, 0, 6, 3, 2, false) -MUX_CFG(DM365, SPI3_SDENA0, 0, 4, 3, 2, false) -MUX_CFG(DM365, SPI3_SDENA1, 0, 6, 3, 3, false) - -MUX_CFG(DM365, SPI4_SCLK, 4, 18, 3, 1, false) -MUX_CFG(DM365, SPI4_SDI, 4, 14, 3, 1, false) -MUX_CFG(DM365, SPI4_SDO, 4, 16, 3, 1, false) -MUX_CFG(DM365, SPI4_SDENA0, 4, 20, 3, 1, false) -MUX_CFG(DM365, SPI4_SDENA1, 4, 16, 3, 2, false) - -MUX_CFG(DM365, CLKOUT0, 4, 20, 3, 3, false) -MUX_CFG(DM365, CLKOUT1, 4, 16, 3, 3, false) -MUX_CFG(DM365, CLKOUT2, 4, 8, 3, 3, false) - -MUX_CFG(DM365, GPIO20, 3, 21, 3, 0, false) -MUX_CFG(DM365, GPIO30, 4, 6, 3, 0, false) -MUX_CFG(DM365, GPIO31, 4, 8, 3, 0, false) -MUX_CFG(DM365, GPIO32, 4, 10, 3, 0, false) -MUX_CFG(DM365, GPIO33, 4, 12, 3, 0, false) -MUX_CFG(DM365, GPIO40, 4, 26, 3, 0, false) -MUX_CFG(DM365, GPIO64_57, 2, 6, 1, 0, false) - -MUX_CFG(DM365, VOUT_FIELD, 1, 18, 3, 1, false) -MUX_CFG(DM365, VOUT_FIELD_G81, 1, 18, 3, 0, false) -MUX_CFG(DM365, VOUT_HVSYNC, 1, 16, 1, 0, false) -MUX_CFG(DM365, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false) -MUX_CFG(DM365, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false) -MUX_CFG(DM365, VIN_CAM_WEN, 0, 14, 3, 0, false) -MUX_CFG(DM365, VIN_CAM_VD, 0, 13, 1, 0, false) -MUX_CFG(DM365, VIN_CAM_HD, 0, 12, 1, 0, false) -MUX_CFG(DM365, VIN_YIN4_7_EN, 0, 0, 0xff, 0, false) -MUX_CFG(DM365, VIN_YIN0_3_EN, 0, 8, 0xf, 0, false) - -INT_CFG(DM365, INT_EDMA_CC, 2, 1, 1, false) -INT_CFG(DM365, INT_EDMA_TC0_ERR, 3, 1, 1, false) -INT_CFG(DM365, INT_EDMA_TC1_ERR, 4, 1, 1, false) -INT_CFG(DM365, INT_EDMA_TC2_ERR, 22, 1, 1, false) -INT_CFG(DM365, INT_EDMA_TC3_ERR, 23, 1, 1, false) -INT_CFG(DM365, INT_PRTCSS, 10, 1, 1, false) -INT_CFG(DM365, INT_EMAC_RXTHRESH, 14, 1, 1, false) -INT_CFG(DM365, INT_EMAC_RXPULSE, 15, 1, 1, false) -INT_CFG(DM365, INT_EMAC_TXPULSE, 16, 1, 1, false) -INT_CFG(DM365, INT_EMAC_MISCPULSE, 17, 1, 1, false) -INT_CFG(DM365, INT_IMX0_ENABLE, 0, 1, 0, false) -INT_CFG(DM365, INT_IMX0_DISABLE, 0, 1, 1, false) -INT_CFG(DM365, INT_HDVICP_ENABLE, 0, 1, 1, false) -INT_CFG(DM365, INT_HDVICP_DISABLE, 0, 1, 0, false) -INT_CFG(DM365, INT_IMX1_ENABLE, 24, 1, 1, false) -INT_CFG(DM365, INT_IMX1_DISABLE, 24, 1, 0, false) -INT_CFG(DM365, INT_NSF_ENABLE, 25, 1, 1, false) -INT_CFG(DM365, INT_NSF_DISABLE, 25, 1, 0, false) - -EVT_CFG(DM365, EVT2_ASP_TX, 0, 1, 0, false) -EVT_CFG(DM365, EVT3_ASP_RX, 1, 1, 0, false) -EVT_CFG(DM365, EVT2_VC_TX, 0, 1, 1, false) -EVT_CFG(DM365, EVT3_VC_RX, 1, 1, 1, false) -#endif -}; - -static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32); - -static struct davinci_spi_platform_data dm365_spi0_pdata = { - .version = SPI_VERSION_1, - .num_chipselect = 2, - .dma_event_q = EVENTQ_3, - .prescaler_limit = 1, -}; - -static struct resource dm365_spi0_resources[] = { - { - .start = 0x01c66000, - .end = 0x01c667ff, - .flags = IORESOURCE_MEM, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM365_SPIINT0_0), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dm365_spi0_device = { - .name = "spi_davinci", - .id = 0, - .dev = { - .dma_mask = &dm365_spi0_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &dm365_spi0_pdata, - }, - .num_resources = ARRAY_SIZE(dm365_spi0_resources), - .resource = dm365_spi0_resources, -}; - -void __init dm365_init_spi0(unsigned chipselect_mask, - const struct spi_board_info *info, unsigned len) -{ - davinci_cfg_reg(DM365_SPI0_SCLK); - davinci_cfg_reg(DM365_SPI0_SDI); - davinci_cfg_reg(DM365_SPI0_SDO); - - /* not all slaves will be wired up */ - if (chipselect_mask & BIT(0)) - davinci_cfg_reg(DM365_SPI0_SDENA0); - if (chipselect_mask & BIT(1)) - davinci_cfg_reg(DM365_SPI0_SDENA1); - - spi_register_board_info(info, len); - - platform_device_register(&dm365_spi0_device); -} - -static struct resource dm365_gpio_resources[] = { - { /* registers */ - .start = DAVINCI_GPIO_BASE, - .end = DAVINCI_GPIO_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - { /* interrupt */ - .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO0), - .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO0), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO1), - .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO1), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO2), - .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO2), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO3), - .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO3), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO4), - .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO4), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO5), - .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO5), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO6), - .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO6), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO7), - .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO7), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct davinci_gpio_platform_data dm365_gpio_platform_data = { - .no_auto_base = true, - .base = 0, - .ngpio = 104, - .gpio_unbanked = 8, -}; - -int __init dm365_gpio_register(void) -{ - return davinci_gpio_register(dm365_gpio_resources, - ARRAY_SIZE(dm365_gpio_resources), - &dm365_gpio_platform_data); -} - -static struct emac_platform_data dm365_emac_pdata = { - .ctrl_reg_offset = DM365_EMAC_CNTRL_OFFSET, - .ctrl_mod_reg_offset = DM365_EMAC_CNTRL_MOD_OFFSET, - .ctrl_ram_offset = DM365_EMAC_CNTRL_RAM_OFFSET, - .ctrl_ram_size = DM365_EMAC_CNTRL_RAM_SIZE, - .version = EMAC_VERSION_2, -}; - -static struct resource dm365_emac_resources[] = { - { - .start = DM365_EMAC_BASE, - .end = DM365_EMAC_BASE + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXTHRESH), - .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXTHRESH), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXPULSE), - .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXPULSE), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_TXPULSE), - .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_TXPULSE), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_MISCPULSE), - .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_MISCPULSE), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dm365_emac_device = { - .name = "davinci_emac", - .id = 1, - .dev = { - .platform_data = &dm365_emac_pdata, - }, - .num_resources = ARRAY_SIZE(dm365_emac_resources), - .resource = dm365_emac_resources, -}; - -static struct resource dm365_mdio_resources[] = { - { - .start = DM365_EMAC_MDIO_BASE, - .end = DM365_EMAC_MDIO_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device dm365_mdio_device = { - .name = "davinci_mdio", - .id = 0, - .num_resources = ARRAY_SIZE(dm365_mdio_resources), - .resource = dm365_mdio_resources, -}; - -static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = { - [IRQ_VDINT0] = 2, - [IRQ_VDINT1] = 6, - [IRQ_VDINT2] = 6, - [IRQ_HISTINT] = 6, - [IRQ_H3AINT] = 6, - [IRQ_PRVUINT] = 6, - [IRQ_RSZINT] = 6, - [IRQ_DM365_INSFINT] = 7, - [IRQ_VENCINT] = 6, - [IRQ_ASQINT] = 6, - [IRQ_IMXINT] = 6, - [IRQ_DM365_IMCOPINT] = 4, - [IRQ_USBINT] = 4, - [IRQ_DM365_RTOINT] = 7, - [IRQ_DM365_TINT5] = 7, - [IRQ_DM365_TINT6] = 5, - [IRQ_CCINT0] = 5, - [IRQ_CCERRINT] = 5, - [IRQ_TCERRINT0] = 5, - [IRQ_TCERRINT] = 7, - [IRQ_PSCIN] = 4, - [IRQ_DM365_SPINT2_1] = 7, - [IRQ_DM365_TINT7] = 7, - [IRQ_DM365_SDIOINT0] = 7, - [IRQ_MBXINT] = 7, - [IRQ_MBRINT] = 7, - [IRQ_MMCINT] = 7, - [IRQ_DM365_MMCINT1] = 7, - [IRQ_DM365_PWMINT3] = 7, - [IRQ_AEMIFINT] = 2, - [IRQ_DM365_SDIOINT1] = 2, - [IRQ_TINT0_TINT12] = 7, - [IRQ_TINT0_TINT34] = 7, - [IRQ_TINT1_TINT12] = 7, - [IRQ_TINT1_TINT34] = 7, - [IRQ_PWMINT0] = 7, - [IRQ_PWMINT1] = 3, - [IRQ_PWMINT2] = 3, - [IRQ_I2C] = 3, - [IRQ_UARTINT0] = 3, - [IRQ_UARTINT1] = 3, - [IRQ_DM365_RTCINT] = 3, - [IRQ_DM365_SPIINT0_0] = 3, - [IRQ_DM365_SPIINT3_0] = 3, - [IRQ_DM365_GPIO0] = 3, - [IRQ_DM365_GPIO1] = 7, - [IRQ_DM365_GPIO2] = 4, - [IRQ_DM365_GPIO3] = 4, - [IRQ_DM365_GPIO4] = 7, - [IRQ_DM365_GPIO5] = 7, - [IRQ_DM365_GPIO6] = 7, - [IRQ_DM365_GPIO7] = 7, - [IRQ_DM365_EMAC_RXTHRESH] = 7, - [IRQ_DM365_EMAC_RXPULSE] = 7, - [IRQ_DM365_EMAC_TXPULSE] = 7, - [IRQ_DM365_EMAC_MISCPULSE] = 7, - [IRQ_DM365_GPIO12] = 7, - [IRQ_DM365_GPIO13] = 7, - [IRQ_DM365_GPIO14] = 7, - [IRQ_DM365_GPIO15] = 7, - [IRQ_DM365_KEYINT] = 7, - [IRQ_DM365_TCERRINT2] = 7, - [IRQ_DM365_TCERRINT3] = 7, - [IRQ_DM365_EMUINT] = 7, -}; - -/* Four Transfer Controllers on DM365 */ -static s8 dm365_queue_priority_mapping[][2] = { - /* {event queue no, Priority} */ - {0, 7}, - {1, 7}, - {2, 7}, - {3, 0}, - {-1, -1}, -}; - -static const struct dma_slave_map dm365_edma_map[] = { - { "davinci-mcbsp", "tx", EDMA_FILTER_PARAM(0, 2) }, - { "davinci-mcbsp", "rx", EDMA_FILTER_PARAM(0, 3) }, - { "davinci_voicecodec", "tx", EDMA_FILTER_PARAM(0, 2) }, - { "davinci_voicecodec", "rx", EDMA_FILTER_PARAM(0, 3) }, - { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) }, - { "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) }, - { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) }, - { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) }, - { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) }, - { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) }, - { "spi_davinci.3", "tx", EDMA_FILTER_PARAM(0, 18) }, - { "spi_davinci.3", "rx", EDMA_FILTER_PARAM(0, 19) }, - { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) }, - { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) }, - { "da830-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) }, - { "da830-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) }, -}; - -static struct edma_soc_info dm365_edma_pdata = { - .queue_priority_mapping = dm365_queue_priority_mapping, - .default_queue = EVENTQ_3, - .slave_map = dm365_edma_map, - .slavecnt = ARRAY_SIZE(dm365_edma_map), -}; - -static struct resource edma_resources[] = { - { - .name = "edma3_cc", - .start = 0x01c00000, - .end = 0x01c00000 + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma3_tc0", - .start = 0x01c10000, - .end = 0x01c10000 + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma3_tc1", - .start = 0x01c10400, - .end = 0x01c10400 + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma3_tc2", - .start = 0x01c10800, - .end = 0x01c10800 + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma3_tc3", - .start = 0x01c10c00, - .end = 0x01c10c00 + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma3_ccint", - .start = DAVINCI_INTC_IRQ(IRQ_CCINT0), - .flags = IORESOURCE_IRQ, - }, - { - .name = "edma3_ccerrint", - .start = DAVINCI_INTC_IRQ(IRQ_CCERRINT), - .flags = IORESOURCE_IRQ, - }, - /* not using TC*_ERR */ -}; - -static const struct platform_device_info dm365_edma_device __initconst = { - .name = "edma", - .id = 0, - .dma_mask = DMA_BIT_MASK(32), - .res = edma_resources, - .num_res = ARRAY_SIZE(edma_resources), - .data = &dm365_edma_pdata, - .size_data = sizeof(dm365_edma_pdata), -}; - -static struct resource dm365_asp_resources[] = { - { - .name = "mpu", - .start = DAVINCI_DM365_ASP0_BASE, - .end = DAVINCI_DM365_ASP0_BASE + SZ_8K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = DAVINCI_DMA_ASP0_TX, - .end = DAVINCI_DMA_ASP0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = DAVINCI_DMA_ASP0_RX, - .end = DAVINCI_DMA_ASP0_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device dm365_asp_device = { - .name = "davinci-mcbsp", - .id = -1, - .num_resources = ARRAY_SIZE(dm365_asp_resources), - .resource = dm365_asp_resources, -}; - -static struct resource dm365_vc_resources[] = { - { - .start = DAVINCI_DM365_VC_BASE, - .end = DAVINCI_DM365_VC_BASE + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = DAVINCI_DMA_VC_TX, - .end = DAVINCI_DMA_VC_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = DAVINCI_DMA_VC_RX, - .end = DAVINCI_DMA_VC_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device dm365_vc_device = { - .name = "davinci_voicecodec", - .id = -1, - .num_resources = ARRAY_SIZE(dm365_vc_resources), - .resource = dm365_vc_resources, -}; - -static struct resource dm365_rtc_resources[] = { - { - .start = DM365_RTC_BASE, - .end = DM365_RTC_BASE + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM365_RTCINT), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dm365_rtc_device = { - .name = "rtc_davinci", - .id = 0, - .num_resources = ARRAY_SIZE(dm365_rtc_resources), - .resource = dm365_rtc_resources, -}; - -static struct map_desc dm365_io_desc[] = { - { - .virtual = IO_VIRT, - .pfn = __phys_to_pfn(IO_PHYS), - .length = IO_SIZE, - .type = MT_DEVICE - }, -}; - -static struct resource dm365_ks_resources[] = { - { - /* registers */ - .start = DM365_KEYSCAN_BASE, - .end = DM365_KEYSCAN_BASE + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - /* interrupt */ - .start = DAVINCI_INTC_IRQ(IRQ_DM365_KEYINT), - .end = DAVINCI_INTC_IRQ(IRQ_DM365_KEYINT), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dm365_ks_device = { - .name = "davinci_keyscan", - .id = 0, - .num_resources = ARRAY_SIZE(dm365_ks_resources), - .resource = dm365_ks_resources, -}; - -/* Contents of JTAG ID register used to identify exact cpu type */ -static struct davinci_id dm365_ids[] = { - { - .variant = 0x0, - .part_no = 0xb83e, - .manufacturer = 0x017, - .cpu_id = DAVINCI_CPU_ID_DM365, - .name = "dm365_rev1.1", - }, - { - .variant = 0x8, - .part_no = 0xb83e, - .manufacturer = 0x017, - .cpu_id = DAVINCI_CPU_ID_DM365, - .name = "dm365_rev1.2", - }, -}; - -/* - * Bottom half of timer0 is used for clockevent, top half is used for - * clocksource. - */ -static const struct davinci_timer_cfg dm365_timer_cfg = { - .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_128), - .irq = { - DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)), - DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)), - }, -}; - -#define DM365_UART1_BASE (IO_PHYS + 0x106000) - -static struct plat_serial8250_port dm365_serial0_platform_data[] = { - { - .mapbase = DAVINCI_UART0_BASE, - .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0), - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_IOREMAP, - .iotype = UPIO_MEM, - .regshift = 2, - }, - { - .flags = 0, - } -}; -static struct plat_serial8250_port dm365_serial1_platform_data[] = { - { - .mapbase = DM365_UART1_BASE, - .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1), - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_IOREMAP, - .iotype = UPIO_MEM, - .regshift = 2, - }, - { - .flags = 0, - } -}; - -struct platform_device dm365_serial_device[] = { - { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = dm365_serial0_platform_data, - } - }, - { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM1, - .dev = { - .platform_data = dm365_serial1_platform_data, - } - }, - { - } -}; - -static const struct davinci_soc_info davinci_soc_info_dm365 = { - .io_desc = dm365_io_desc, - .io_desc_num = ARRAY_SIZE(dm365_io_desc), - .jtag_id_reg = 0x01c40028, - .ids = dm365_ids, - .ids_num = ARRAY_SIZE(dm365_ids), - .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE, - .pinmux_pins = dm365_pins, - .pinmux_pins_num = ARRAY_SIZE(dm365_pins), - .emac_pdata = &dm365_emac_pdata, - .sram_dma = 0x00010000, - .sram_len = SZ_32K, -}; - -void __init dm365_init_asp(void) -{ - davinci_cfg_reg(DM365_MCBSP0_BDX); - davinci_cfg_reg(DM365_MCBSP0_X); - davinci_cfg_reg(DM365_MCBSP0_BFSX); - davinci_cfg_reg(DM365_MCBSP0_BDR); - davinci_cfg_reg(DM365_MCBSP0_R); - davinci_cfg_reg(DM365_MCBSP0_BFSR); - davinci_cfg_reg(DM365_EVT2_ASP_TX); - davinci_cfg_reg(DM365_EVT3_ASP_RX); - platform_device_register(&dm365_asp_device); -} - -void __init dm365_init_vc(void) -{ - davinci_cfg_reg(DM365_EVT2_VC_TX); - davinci_cfg_reg(DM365_EVT3_VC_RX); - platform_device_register(&dm365_vc_device); -} - -void __init dm365_init_ks(struct davinci_ks_platform_data *pdata) -{ - dm365_ks_device.dev.platform_data = pdata; - platform_device_register(&dm365_ks_device); -} - -void __init dm365_init_rtc(void) -{ - davinci_cfg_reg(DM365_INT_PRTCSS); - platform_device_register(&dm365_rtc_device); -} - -void __init dm365_init(void) -{ - davinci_common_init(&davinci_soc_info_dm365); - davinci_map_sysmod(); -} - -void __init dm365_init_time(void) -{ - void __iomem *pll1, *pll2, *psc; - struct clk *clk; - int rv; - - clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM365_REF_FREQ); - - pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K); - dm365_pll1_init(NULL, pll1, NULL); - - pll2 = ioremap(DAVINCI_PLL2_BASE, SZ_1K); - dm365_pll2_init(NULL, pll2, NULL); - - psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K); - dm365_psc_init(NULL, psc); - - clk = clk_get(NULL, "timer0"); - if (WARN_ON(IS_ERR(clk))) { - pr_err("Unable to get the timer clock\n"); - return; - } - - rv = davinci_timer_register(clk, &dm365_timer_cfg); - WARN(rv, "Unable to register the timer: %d\n", rv); -} - -void __init dm365_register_clocks(void) -{ - /* all clocks are currently registered in dm365_init_time() */ -} - -static struct resource dm365_vpss_resources[] = { - { - /* VPSS ISP5 Base address */ - .name = "isp5", - .start = 0x01c70000, - .end = 0x01c70000 + 0xff, - .flags = IORESOURCE_MEM, - }, - { - /* VPSS CLK Base address */ - .name = "vpss", - .start = 0x01c70200, - .end = 0x01c70200 + 0xff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device dm365_vpss_device = { - .name = "vpss", - .id = -1, - .dev.platform_data = "dm365_vpss", - .num_resources = ARRAY_SIZE(dm365_vpss_resources), - .resource = dm365_vpss_resources, -}; - -static struct resource vpfe_resources[] = { - { - .start = DAVINCI_INTC_IRQ(IRQ_VDINT0), - .end = DAVINCI_INTC_IRQ(IRQ_VDINT0), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_VDINT1), - .end = DAVINCI_INTC_IRQ(IRQ_VDINT1), - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32); -static struct platform_device vpfe_capture_dev = { - .name = CAPTURE_DRV_NAME, - .id = -1, - .num_resources = ARRAY_SIZE(vpfe_resources), - .resource = vpfe_resources, - .dev = { - .dma_mask = &vpfe_capture_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static void dm365_isif_setup_pinmux(void) -{ - davinci_cfg_reg(DM365_VIN_CAM_WEN); - davinci_cfg_reg(DM365_VIN_CAM_VD); - davinci_cfg_reg(DM365_VIN_CAM_HD); - davinci_cfg_reg(DM365_VIN_YIN4_7_EN); - davinci_cfg_reg(DM365_VIN_YIN0_3_EN); -} - -static struct resource isif_resource[] = { - /* ISIF Base address */ - { - .start = 0x01c71000, - .end = 0x01c71000 + 0x1ff, - .flags = IORESOURCE_MEM, - }, - /* ISIF Linearization table 0 */ - { - .start = 0x1C7C000, - .end = 0x1C7C000 + 0x2ff, - .flags = IORESOURCE_MEM, - }, - /* ISIF Linearization table 1 */ - { - .start = 0x1C7C400, - .end = 0x1C7C400 + 0x2ff, - .flags = IORESOURCE_MEM, - }, -}; -static struct platform_device dm365_isif_dev = { - .name = "isif", - .id = -1, - .num_resources = ARRAY_SIZE(isif_resource), - .resource = isif_resource, - .dev = { - .dma_mask = &vpfe_capture_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = dm365_isif_setup_pinmux, - }, -}; - -static struct resource dm365_osd_resources[] = { - { - .start = DM365_OSD_BASE, - .end = DM365_OSD_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, -}; - -static u64 dm365_video_dma_mask = DMA_BIT_MASK(32); - -static struct platform_device dm365_osd_dev = { - .name = DM365_VPBE_OSD_SUBDEV_NAME, - .id = -1, - .num_resources = ARRAY_SIZE(dm365_osd_resources), - .resource = dm365_osd_resources, - .dev = { - .dma_mask = &dm365_video_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct resource dm365_venc_resources[] = { - { - .start = DAVINCI_INTC_IRQ(IRQ_VENCINT), - .end = DAVINCI_INTC_IRQ(IRQ_VENCINT), - .flags = IORESOURCE_IRQ, - }, - /* venc registers io space */ - { - .start = DM365_VENC_BASE, - .end = DM365_VENC_BASE + 0x177, - .flags = IORESOURCE_MEM, - }, - /* vdaccfg registers io space */ - { - .start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG, - .end = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource dm365_v4l2_disp_resources[] = { - { - .start = DAVINCI_INTC_IRQ(IRQ_VENCINT), - .end = DAVINCI_INTC_IRQ(IRQ_VENCINT), - .flags = IORESOURCE_IRQ, - }, - /* venc registers io space */ - { - .start = DM365_VENC_BASE, - .end = DM365_VENC_BASE + 0x177, - .flags = IORESOURCE_MEM, - }, -}; - -static int dm365_vpbe_setup_pinmux(u32 if_type, int field) -{ - switch (if_type) { - case MEDIA_BUS_FMT_SGRBG8_1X8: - davinci_cfg_reg(DM365_VOUT_FIELD_G81); - davinci_cfg_reg(DM365_VOUT_COUTL_EN); - davinci_cfg_reg(DM365_VOUT_COUTH_EN); - break; - case MEDIA_BUS_FMT_YUYV10_1X20: - if (field) - davinci_cfg_reg(DM365_VOUT_FIELD); - else - davinci_cfg_reg(DM365_VOUT_FIELD_G81); - davinci_cfg_reg(DM365_VOUT_COUTL_EN); - davinci_cfg_reg(DM365_VOUT_COUTH_EN); - break; - default: - return -EINVAL; - } - - return 0; -} - -static int dm365_venc_setup_clock(enum vpbe_enc_timings_type type, - unsigned int pclock) -{ - void __iomem *vpss_clkctl_reg; - u32 val; - - vpss_clkctl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL); - - switch (type) { - case VPBE_ENC_STD: - val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE; - break; - case VPBE_ENC_DV_TIMINGS: - if (pclock <= 27000000) { - val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE; - } else { - /* set sysclk4 to output 74.25 MHz from pll1 */ - val = VPSS_PLLC2SYSCLK5_ENABLE | VPSS_DACCLKEN_ENABLE | - VPSS_VENCCLKEN_ENABLE; - } - break; - default: - return -EINVAL; - } - writel(val, vpss_clkctl_reg); - - return 0; -} - -static struct platform_device dm365_vpbe_display = { - .name = "vpbe-v4l2", - .id = -1, - .num_resources = ARRAY_SIZE(dm365_v4l2_disp_resources), - .resource = dm365_v4l2_disp_resources, - .dev = { - .dma_mask = &dm365_video_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct venc_platform_data dm365_venc_pdata = { - .setup_pinmux = dm365_vpbe_setup_pinmux, - .setup_clock = dm365_venc_setup_clock, -}; - -static struct platform_device dm365_venc_dev = { - .name = DM365_VPBE_VENC_SUBDEV_NAME, - .id = -1, - .num_resources = ARRAY_SIZE(dm365_venc_resources), - .resource = dm365_venc_resources, - .dev = { - .dma_mask = &dm365_video_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = (void *)&dm365_venc_pdata, - }, -}; - -static struct platform_device dm365_vpbe_dev = { - .name = "vpbe_controller", - .id = -1, - .dev = { - .dma_mask = &dm365_video_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -int __init dm365_init_video(struct vpfe_config *vpfe_cfg, - struct vpbe_config *vpbe_cfg) -{ - if (vpfe_cfg || vpbe_cfg) - platform_device_register(&dm365_vpss_device); - - if (vpfe_cfg) { - vpfe_capture_dev.dev.platform_data = vpfe_cfg; - platform_device_register(&dm365_isif_dev); - platform_device_register(&vpfe_capture_dev); - } - if (vpbe_cfg) { - dm365_vpbe_dev.dev.platform_data = vpbe_cfg; - platform_device_register(&dm365_osd_dev); - platform_device_register(&dm365_venc_dev); - platform_device_register(&dm365_vpbe_dev); - platform_device_register(&dm365_vpbe_display); - } - - return 0; -} - -static const struct davinci_aintc_config dm365_aintc_config = { - .reg = { - .start = DAVINCI_ARM_INTC_BASE, - .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - .num_irqs = 64, - .prios = dm365_default_priorities, -}; - -void __init dm365_init_irq(void) -{ - davinci_aintc_init(&dm365_aintc_config); -} - -static int __init dm365_init_devices(void) -{ - struct platform_device *edma_pdev; - int ret = 0; - - if (!cpu_is_davinci_dm365()) - return 0; - - davinci_cfg_reg(DM365_INT_EDMA_CC); - edma_pdev = platform_device_register_full(&dm365_edma_device); - if (IS_ERR(edma_pdev)) { - pr_warn("%s: Failed to register eDMA\n", __func__); - return PTR_ERR(edma_pdev); - } - - platform_device_register(&dm365_mdio_device); - platform_device_register(&dm365_emac_device); - - ret = davinci_init_wdt(); - if (ret) - pr_warn("%s: watchdog init failed: %d\n", __func__, ret); - - return ret; -} -postcore_initcall(dm365_init_devices); -- cgit From c3848db316d51dcc0fb10554151b1e7e8ff8c3e2 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 29 Sep 2022 16:14:18 +0200 Subject: ARM: davinci: drop DAVINCI_DMxxx references Support for all the dm3xx/dm64xx SoCs is no longer available, so drop all other references to those. Acked-by: Stephen Boyd Signed-off-by: Arnd Bergmann --- arch/arm/mach-davinci/cputype.h | 32 -------------------------------- arch/arm/mach-davinci/serial.c | 4 ---- arch/arm/mach-davinci/usb.c | 13 ------------- 3 files changed, 49 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-davinci/cputype.h b/arch/arm/mach-davinci/cputype.h index 4590afdbe449..87ee56068a16 100644 --- a/arch/arm/mach-davinci/cputype.h +++ b/arch/arm/mach-davinci/cputype.h @@ -25,10 +25,6 @@ struct davinci_id { }; /* Can use lower 16 bits of cpu id for a variant when required */ -#define DAVINCI_CPU_ID_DM6446 0x64460000 -#define DAVINCI_CPU_ID_DM6467 0x64670000 -#define DAVINCI_CPU_ID_DM355 0x03550000 -#define DAVINCI_CPU_ID_DM365 0x03650000 #define DAVINCI_CPU_ID_DA830 0x08300000 #define DAVINCI_CPU_ID_DA850 0x08500000 @@ -38,37 +34,9 @@ static inline int is_davinci_ ##type(void) \ return (davinci_soc_info.cpu_id == (id)); \ } -IS_DAVINCI_CPU(dm644x, DAVINCI_CPU_ID_DM6446) -IS_DAVINCI_CPU(dm646x, DAVINCI_CPU_ID_DM6467) -IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355) -IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365) IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830) IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850) -#ifdef CONFIG_ARCH_DAVINCI_DM644x -#define cpu_is_davinci_dm644x() is_davinci_dm644x() -#else -#define cpu_is_davinci_dm644x() 0 -#endif - -#ifdef CONFIG_ARCH_DAVINCI_DM646x -#define cpu_is_davinci_dm646x() is_davinci_dm646x() -#else -#define cpu_is_davinci_dm646x() 0 -#endif - -#ifdef CONFIG_ARCH_DAVINCI_DM355 -#define cpu_is_davinci_dm355() is_davinci_dm355() -#else -#define cpu_is_davinci_dm355() 0 -#endif - -#ifdef CONFIG_ARCH_DAVINCI_DM365 -#define cpu_is_davinci_dm365() is_davinci_dm365() -#else -#define cpu_is_davinci_dm365() 0 -#endif - #ifdef CONFIG_ARCH_DAVINCI_DA830 #define cpu_is_davinci_da830() is_davinci_da830() #else diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c index 7f7814807bb5..ac1929bb0ef2 100644 --- a/arch/arm/mach-davinci/serial.c +++ b/arch/arm/mach-davinci/serial.c @@ -40,10 +40,6 @@ static void __init davinci_serial_reset(struct plat_serial8250_port *p) pwremu |= (0x3 << 13); pwremu |= 0x1; serial_write_reg(p, UART_DAVINCI_PWREMU, pwremu); - - if (cpu_is_davinci_dm646x()) - serial_write_reg(p, UART_DM646X_SCR, - UART_DM646X_SCR_TX_WATERMARK); } int __init davinci_serial_init(struct platform_device *serial_dev) diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c index a9e5c6e91e5d..9dc14c7977b3 100644 --- a/arch/arm/mach-davinci/usb.c +++ b/arch/arm/mach-davinci/usb.c @@ -41,11 +41,6 @@ static struct resource usb_resources[] = { .flags = IORESOURCE_IRQ, .name = "mc" }, - { - /* placeholder for the dedicated CPPI IRQ */ - .flags = IORESOURCE_IRQ, - .name = "dma" - }, }; static u64 usb_dmamask = DMA_BIT_MASK(32); @@ -67,14 +62,6 @@ void __init davinci_setup_usb(unsigned mA, unsigned potpgt_ms) usb_data.power = mA > 510 ? 255 : mA / 2; usb_data.potpgt = (potpgt_ms + 1) / 2; - if (cpu_is_davinci_dm646x()) { - /* Override the defaults as DM6467 uses different IRQs. */ - usb_dev.resource[1].start = DAVINCI_INTC_IRQ(IRQ_DM646X_USBINT); - usb_dev.resource[2].start = DAVINCI_INTC_IRQ( - IRQ_DM646X_USBDMAINT); - } else /* other devices don't have dedicated CPPI IRQ */ - usb_dev.num_resources = 2; - platform_device_register(&usb_dev); } -- cgit From dec85a95167a98a4e237df11e234eed8ee718e78 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 20 Sep 2022 00:16:17 +0200 Subject: ARM: davinci: clean up platform support With the board file support gone, and the platform using DT only, a lot of the remaining code is no longer referenced and can be removed. Technically, the DT file only references DA850, but since that is very similar to DA830, I'm leaving the latter. Acked-by: Bartosz Golaszewski Signed-off-by: Arnd Bergmann --- arch/arm/mach-davinci/Kconfig | 16 - arch/arm/mach-davinci/Makefile | 9 +- arch/arm/mach-davinci/asp.h | 57 -- arch/arm/mach-davinci/common.h | 7 +- arch/arm/mach-davinci/cputype.h | 21 - arch/arm/mach-davinci/da830.c | 274 --------- arch/arm/mach-davinci/da850.c | 400 +----------- arch/arm/mach-davinci/da8xx.h | 95 +-- arch/arm/mach-davinci/davinci.h | 136 ---- arch/arm/mach-davinci/devices-da8xx.c | 1095 --------------------------------- arch/arm/mach-davinci/irqs.h | 217 ------- arch/arm/mach-davinci/mux.c | 15 - arch/arm/mach-davinci/mux.h | 315 ---------- arch/arm/mach-davinci/psc.h | 64 -- arch/arm/mach-davinci/serial.c | 88 --- arch/arm/mach-davinci/serial.h | 35 -- arch/arm/mach-davinci/usb-da8xx.c | 146 ----- arch/arm/mach-davinci/usb.c | 74 --- 18 files changed, 11 insertions(+), 3053 deletions(-) delete mode 100644 arch/arm/mach-davinci/asp.h delete mode 100644 arch/arm/mach-davinci/davinci.h delete mode 100644 arch/arm/mach-davinci/serial.c delete mode 100644 arch/arm/mach-davinci/serial.h delete mode 100644 arch/arm/mach-davinci/usb-da8xx.c delete mode 100644 arch/arm/mach-davinci/usb.c (limited to 'arch/arm') diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 588213583051..4316e1370627 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -18,8 +18,6 @@ comment "DaVinci Core Type" config ARCH_DAVINCI_DA830 bool "DA830/OMAP-L137/AM17x based system" - depends on AUTO_ZRELADDR && ARM_PATCH_PHYS_VIRT - depends on ATAGS select ARCH_DAVINCI_DA8XX # needed on silicon revs 1.0, 1.1: select CPU_DCACHE_WRITETHROUGH if !CPU_DCACHE_DISABLE @@ -27,25 +25,11 @@ config ARCH_DAVINCI_DA830 config ARCH_DAVINCI_DA850 bool "DA850/OMAP-L138/AM18x based system" - depends on AUTO_ZRELADDR && ARM_PATCH_PHYS_VIRT - depends on ATAGS - select ARCH_DAVINCI_DA8XX select DAVINCI_CP_INTC config ARCH_DAVINCI_DA8XX bool -comment "DaVinci Board Type" - -config MACH_DA8XX_DT - bool "Support DA8XX platforms using device tree" - default y - depends on ARCH_DAVINCI_DA850 - select PINCTRL - help - Say y here to include support for TI DaVinci DA850 based using - Flattened Device Tree. More information at Documentation/devicetree - config DAVINCI_MUX bool "DAVINCI multiplexing support" depends on ARCH_DAVINCI diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index 5b15a3bbf909..450883ea0e73 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -5,16 +5,15 @@ # # # Common objects -obj-y := serial.o usb.o common.o sram.o +obj-y := common.o sram.o devices-da8xx.o obj-$(CONFIG_DAVINCI_MUX) += mux.o # Chip specific -obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o devices-da8xx.o usb-da8xx.o -obj-$(CONFIG_ARCH_DAVINCI_DA850) += da850.o devices-da8xx.o usb-da8xx.o +obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o +obj-$(CONFIG_ARCH_DAVINCI_DA850) += da850.o pdata-quirks.o -# Board specific -obj-$(CONFIG_MACH_DA8XX_DT) += da8xx-dt.o pdata-quirks.o +obj-y += da8xx-dt.o # Power Management obj-$(CONFIG_CPU_IDLE) += cpuidle.o diff --git a/arch/arm/mach-davinci/asp.h b/arch/arm/mach-davinci/asp.h deleted file mode 100644 index d0ecd1d0f084..000000000000 --- a/arch/arm/mach-davinci/asp.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * TI DaVinci Audio definitions - */ -#ifndef __ASM_ARCH_DAVINCI_ASP_H -#define __ASM_ARCH_DAVINCI_ASP_H - -/* Bases of dm644x and dm355 register banks */ -#define DAVINCI_ASP0_BASE 0x01E02000 -#define DAVINCI_ASP1_BASE 0x01E04000 - -/* Bases of dm365 register banks */ -#define DAVINCI_DM365_ASP0_BASE 0x01D02000 - -/* Bases of dm646x register banks */ -#define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000 -#define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800 - -/* Bases of da850/da830 McASP0 register banks */ -#define DAVINCI_DA8XX_MCASP0_REG_BASE 0x01D00000 - -/* Bases of da830 McASP1 register banks */ -#define DAVINCI_DA830_MCASP1_REG_BASE 0x01D04000 - -/* Bases of da830 McASP2 register banks */ -#define DAVINCI_DA830_MCASP2_REG_BASE 0x01D08000 - -/* EDMA channels of dm644x and dm355 */ -#define DAVINCI_DMA_ASP0_TX 2 -#define DAVINCI_DMA_ASP0_RX 3 -#define DAVINCI_DMA_ASP1_TX 8 -#define DAVINCI_DMA_ASP1_RX 9 - -/* EDMA channels of dm646x */ -#define DAVINCI_DM646X_DMA_MCASP0_AXEVT0 6 -#define DAVINCI_DM646X_DMA_MCASP0_AREVT0 9 -#define DAVINCI_DM646X_DMA_MCASP1_AXEVT1 12 - -/* EDMA channels of da850/da830 McASP0 */ -#define DAVINCI_DA8XX_DMA_MCASP0_AREVT 0 -#define DAVINCI_DA8XX_DMA_MCASP0_AXEVT 1 - -/* EDMA channels of da830 McASP1 */ -#define DAVINCI_DA830_DMA_MCASP1_AREVT 2 -#define DAVINCI_DA830_DMA_MCASP1_AXEVT 3 - -/* EDMA channels of da830 McASP2 */ -#define DAVINCI_DA830_DMA_MCASP2_AREVT 4 -#define DAVINCI_DA830_DMA_MCASP2_AXEVT 5 - -/* Interrupts */ -#define DAVINCI_ASP0_RX_INT DAVINCI_INTC_IRQ(IRQ_MBRINT) -#define DAVINCI_ASP0_TX_INT DAVINCI_INTC_IRQ(IRQ_MBXINT) -#define DAVINCI_ASP1_RX_INT DAVINCI_INTC_IRQ(IRQ_MBRINT) -#define DAVINCI_ASP1_TX_INT DAVINCI_INTC_IRQ(IRQ_MBXINT) - -#endif /* __ASM_ARCH_DAVINCI_ASP_H */ diff --git a/arch/arm/mach-davinci/common.h b/arch/arm/mach-davinci/common.h index 772b51e0ac5e..b4fd0e9acf6c 100644 --- a/arch/arm/mach-davinci/common.h +++ b/arch/arm/mach-davinci/common.h @@ -17,8 +17,8 @@ #include -#define DAVINCI_INTC_START NR_IRQS -#define DAVINCI_INTC_IRQ(_irqnum) (DAVINCI_INTC_START + (_irqnum)) +#define DAVINCI_INTC_START NR_IRQS +#define DAVINCI_INTC_IRQ(_irqnum) (DAVINCI_INTC_START + (_irqnum)) struct davinci_gpio_controller; @@ -45,9 +45,6 @@ struct davinci_soc_info { unsigned gpio_num; unsigned gpio_irq; unsigned gpio_unbanked; - struct davinci_gpio_controller *gpio_ctlrs; - int gpio_ctlrs_num; - struct emac_platform_data *emac_pdata; dma_addr_t sram_dma; unsigned sram_len; }; diff --git a/arch/arm/mach-davinci/cputype.h b/arch/arm/mach-davinci/cputype.h index 87ee56068a16..148a738391dc 100644 --- a/arch/arm/mach-davinci/cputype.h +++ b/arch/arm/mach-davinci/cputype.h @@ -28,25 +28,4 @@ struct davinci_id { #define DAVINCI_CPU_ID_DA830 0x08300000 #define DAVINCI_CPU_ID_DA850 0x08500000 -#define IS_DAVINCI_CPU(type, id) \ -static inline int is_davinci_ ##type(void) \ -{ \ - return (davinci_soc_info.cpu_id == (id)); \ -} - -IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830) -IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850) - -#ifdef CONFIG_ARCH_DAVINCI_DA830 -#define cpu_is_davinci_da830() is_davinci_da830() -#else -#define cpu_is_davinci_da830() 0 -#endif - -#ifdef CONFIG_ARCH_DAVINCI_DA850 -#define cpu_is_davinci_da850() is_davinci_da850() -#else -#define cpu_is_davinci_da850() 0 -#endif - #endif diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c index eab5fac18806..2e497745b624 100644 --- a/arch/arm/mach-davinci/da830.c +++ b/arch/arm/mach-davinci/da830.c @@ -12,7 +12,6 @@ #include #include #include -#include #include @@ -448,181 +447,6 @@ static const struct mux_config da830_pins[] = { #endif }; -const short da830_emif25_pins[] __initconst = { - DA830_EMA_D_0, DA830_EMA_D_1, DA830_EMA_D_2, DA830_EMA_D_3, - DA830_EMA_D_4, DA830_EMA_D_5, DA830_EMA_D_6, DA830_EMA_D_7, - DA830_EMA_D_8, DA830_EMA_D_9, DA830_EMA_D_10, DA830_EMA_D_11, - DA830_EMA_D_12, DA830_EMA_D_13, DA830_EMA_D_14, DA830_EMA_D_15, - DA830_EMA_A_0, DA830_EMA_A_1, DA830_EMA_A_2, DA830_EMA_A_3, - DA830_EMA_A_4, DA830_EMA_A_5, DA830_EMA_A_6, DA830_EMA_A_7, - DA830_EMA_A_8, DA830_EMA_A_9, DA830_EMA_A_10, DA830_EMA_A_11, - DA830_EMA_A_12, DA830_EMA_BA_0, DA830_EMA_BA_1, DA830_EMA_CLK, - DA830_EMA_SDCKE, DA830_NEMA_CS_4, DA830_NEMA_CS_5, DA830_NEMA_WE, - DA830_NEMA_CS_0, DA830_NEMA_CS_2, DA830_NEMA_CS_3, DA830_NEMA_OE, - DA830_NEMA_WE_DQM_1, DA830_NEMA_WE_DQM_0, DA830_EMA_WAIT_0, - -1 -}; - -const short da830_spi0_pins[] __initconst = { - DA830_SPI0_SOMI_0, DA830_SPI0_SIMO_0, DA830_SPI0_CLK, DA830_NSPI0_ENA, - DA830_NSPI0_SCS_0, - -1 -}; - -const short da830_spi1_pins[] __initconst = { - DA830_SPI1_SOMI_0, DA830_SPI1_SIMO_0, DA830_SPI1_CLK, DA830_NSPI1_ENA, - DA830_NSPI1_SCS_0, - -1 -}; - -const short da830_mmc_sd_pins[] __initconst = { - DA830_MMCSD_DAT_0, DA830_MMCSD_DAT_1, DA830_MMCSD_DAT_2, - DA830_MMCSD_DAT_3, DA830_MMCSD_DAT_4, DA830_MMCSD_DAT_5, - DA830_MMCSD_DAT_6, DA830_MMCSD_DAT_7, DA830_MMCSD_CLK, - DA830_MMCSD_CMD, - -1 -}; - -const short da830_uart0_pins[] __initconst = { - DA830_NUART0_CTS, DA830_NUART0_RTS, DA830_UART0_RXD, DA830_UART0_TXD, - -1 -}; - -const short da830_uart1_pins[] __initconst = { - DA830_UART1_RXD, DA830_UART1_TXD, - -1 -}; - -const short da830_uart2_pins[] __initconst = { - DA830_UART2_RXD, DA830_UART2_TXD, - -1 -}; - -const short da830_usb20_pins[] __initconst = { - DA830_USB0_DRVVBUS, DA830_USB_REFCLKIN, - -1 -}; - -const short da830_usb11_pins[] __initconst = { - DA830_USB_REFCLKIN, - -1 -}; - -const short da830_uhpi_pins[] __initconst = { - DA830_UHPI_HD_0, DA830_UHPI_HD_1, DA830_UHPI_HD_2, DA830_UHPI_HD_3, - DA830_UHPI_HD_4, DA830_UHPI_HD_5, DA830_UHPI_HD_6, DA830_UHPI_HD_7, - DA830_UHPI_HD_8, DA830_UHPI_HD_9, DA830_UHPI_HD_10, DA830_UHPI_HD_11, - DA830_UHPI_HD_12, DA830_UHPI_HD_13, DA830_UHPI_HD_14, DA830_UHPI_HD_15, - DA830_UHPI_HCNTL0, DA830_UHPI_HCNTL1, DA830_UHPI_HHWIL, DA830_UHPI_HRNW, - DA830_NUHPI_HAS, DA830_NUHPI_HCS, DA830_NUHPI_HDS1, DA830_NUHPI_HDS2, - DA830_NUHPI_HINT, DA830_NUHPI_HRDY, - -1 -}; - -const short da830_cpgmac_pins[] __initconst = { - DA830_RMII_TXD_0, DA830_RMII_TXD_1, DA830_RMII_TXEN, DA830_RMII_CRS_DV, - DA830_RMII_RXD_0, DA830_RMII_RXD_1, DA830_RMII_RXER, DA830_MDIO_CLK, - DA830_MDIO_D, - -1 -}; - -const short da830_emif3c_pins[] __initconst = { - DA830_EMB_SDCKE, DA830_EMB_CLK_GLUE, DA830_EMB_CLK, DA830_NEMB_CS_0, - DA830_NEMB_CAS, DA830_NEMB_RAS, DA830_NEMB_WE, DA830_EMB_BA_1, - DA830_EMB_BA_0, DA830_EMB_A_0, DA830_EMB_A_1, DA830_EMB_A_2, - DA830_EMB_A_3, DA830_EMB_A_4, DA830_EMB_A_5, DA830_EMB_A_6, - DA830_EMB_A_7, DA830_EMB_A_8, DA830_EMB_A_9, DA830_EMB_A_10, - DA830_EMB_A_11, DA830_EMB_A_12, DA830_NEMB_WE_DQM_3, - DA830_NEMB_WE_DQM_2, DA830_EMB_D_0, DA830_EMB_D_1, DA830_EMB_D_2, - DA830_EMB_D_3, DA830_EMB_D_4, DA830_EMB_D_5, DA830_EMB_D_6, - DA830_EMB_D_7, DA830_EMB_D_8, DA830_EMB_D_9, DA830_EMB_D_10, - DA830_EMB_D_11, DA830_EMB_D_12, DA830_EMB_D_13, DA830_EMB_D_14, - DA830_EMB_D_15, DA830_EMB_D_16, DA830_EMB_D_17, DA830_EMB_D_18, - DA830_EMB_D_19, DA830_EMB_D_20, DA830_EMB_D_21, DA830_EMB_D_22, - DA830_EMB_D_23, DA830_EMB_D_24, DA830_EMB_D_25, DA830_EMB_D_26, - DA830_EMB_D_27, DA830_EMB_D_28, DA830_EMB_D_29, DA830_EMB_D_30, - DA830_EMB_D_31, DA830_NEMB_WE_DQM_1, DA830_NEMB_WE_DQM_0, - -1 -}; - -const short da830_mcasp0_pins[] __initconst = { - DA830_AHCLKX0, DA830_ACLKX0, DA830_AFSX0, - DA830_AHCLKR0, DA830_ACLKR0, DA830_AFSR0, DA830_AMUTE0, - DA830_AXR0_0, DA830_AXR0_1, DA830_AXR0_2, DA830_AXR0_3, - DA830_AXR0_4, DA830_AXR0_5, DA830_AXR0_6, DA830_AXR0_7, - DA830_AXR0_8, DA830_AXR0_9, DA830_AXR0_10, DA830_AXR0_11, - DA830_AXR0_12, DA830_AXR0_13, DA830_AXR0_14, DA830_AXR0_15, - -1 -}; - -const short da830_mcasp1_pins[] __initconst = { - DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1, - DA830_AHCLKR1, DA830_ACLKR1, DA830_AFSR1, DA830_AMUTE1, - DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_3, - DA830_AXR1_4, DA830_AXR1_5, DA830_AXR1_6, DA830_AXR1_7, - DA830_AXR1_8, DA830_AXR1_9, DA830_AXR1_10, DA830_AXR1_11, - -1 -}; - -const short da830_mcasp2_pins[] __initconst = { - DA830_AHCLKX2, DA830_ACLKX2, DA830_AFSX2, - DA830_AHCLKR2, DA830_ACLKR2, DA830_AFSR2, DA830_AMUTE2, - DA830_AXR2_0, DA830_AXR2_1, DA830_AXR2_2, DA830_AXR2_3, - -1 -}; - -const short da830_i2c0_pins[] __initconst = { - DA830_I2C0_SDA, DA830_I2C0_SCL, - -1 -}; - -const short da830_i2c1_pins[] __initconst = { - DA830_I2C1_SCL, DA830_I2C1_SDA, - -1 -}; - -const short da830_lcdcntl_pins[] __initconst = { - DA830_LCD_D_0, DA830_LCD_D_1, DA830_LCD_D_2, DA830_LCD_D_3, - DA830_LCD_D_4, DA830_LCD_D_5, DA830_LCD_D_6, DA830_LCD_D_7, - DA830_LCD_D_8, DA830_LCD_D_9, DA830_LCD_D_10, DA830_LCD_D_11, - DA830_LCD_D_12, DA830_LCD_D_13, DA830_LCD_D_14, DA830_LCD_D_15, - DA830_LCD_PCLK, DA830_LCD_HSYNC, DA830_LCD_VSYNC, DA830_NLCD_AC_ENB_CS, - DA830_LCD_MCLK, - -1 -}; - -const short da830_pwm_pins[] __initconst = { - DA830_ECAP0_APWM0, DA830_ECAP1_APWM1, DA830_EPWM0B, DA830_EPWM0A, - DA830_EPWMSYNCI, DA830_EPWMSYNC0, DA830_ECAP2_APWM2, DA830_EHRPWMGLUETZ, - DA830_EPWM2B, DA830_EPWM2A, DA830_EPWM1B, DA830_EPWM1A, - -1 -}; - -const short da830_ecap0_pins[] __initconst = { - DA830_ECAP0_APWM0, - -1 -}; - -const short da830_ecap1_pins[] __initconst = { - DA830_ECAP1_APWM1, - -1 -}; - -const short da830_ecap2_pins[] __initconst = { - DA830_ECAP2_APWM2, - -1 -}; - -const short da830_eqep0_pins[] __initconst = { - DA830_EQEP0I, DA830_EQEP0S, DA830_EQEP0A, DA830_EQEP0B, - -1 -}; - -const short da830_eqep1_pins[] __initconst = { - DA830_EQEP1I, DA830_EQEP1S, DA830_EQEP1A, DA830_EQEP1B, - -1 -}; - static struct map_desc da830_io_desc[] = { { .virtual = IO_VIRT, @@ -663,30 +487,6 @@ static struct davinci_id da830_ids[] = { }, }; -static struct davinci_gpio_platform_data da830_gpio_platform_data = { - .no_auto_base = true, - .base = 0, - .ngpio = 128, -}; - -int __init da830_register_gpio(void) -{ - return da8xx_register_gpio(&da830_gpio_platform_data); -} - -/* - * Bottom half of timer0 is used both for clock even and clocksource. - * Top half is used by DSP. - */ -static const struct davinci_timer_cfg da830_timer_cfg = { - .reg = DEFINE_RES_IO(DA8XX_TIMER64P0_BASE, SZ_4K), - .irq = { - DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA830_T12CMPINT0_0)), - DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0)), - }, - .cmp_off = DA830_CMP12_0, -}; - static const struct davinci_soc_info davinci_soc_info_da830 = { .io_desc = da830_io_desc, .io_desc_num = ARRAY_SIZE(da830_io_desc), @@ -696,7 +496,6 @@ static const struct davinci_soc_info davinci_soc_info_da830 = { .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120, .pinmux_pins = da830_pins, .pinmux_pins_num = ARRAY_SIZE(da830_pins), - .emac_pdata = &da8xx_emac_pdata, }; void __init da830_init(void) @@ -706,76 +505,3 @@ void __init da830_init(void) da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K); WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"); } - -static const struct davinci_cp_intc_config da830_cp_intc_config = { - .reg = { - .start = DA8XX_CP_INTC_BASE, - .end = DA8XX_CP_INTC_BASE + SZ_8K - 1, - .flags = IORESOURCE_MEM, - }, - .num_irqs = DA830_N_CP_INTC_IRQ, -}; - -void __init da830_init_irq(void) -{ - davinci_cp_intc_init(&da830_cp_intc_config); -} - -void __init da830_init_time(void) -{ - void __iomem *pll; - struct clk *clk; - int rv; - - clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DA830_REF_FREQ); - - pll = ioremap(DA8XX_PLL0_BASE, SZ_4K); - - da830_pll_init(NULL, pll, NULL); - - clk = clk_get(NULL, "timer0"); - if (WARN_ON(IS_ERR(clk))) { - pr_err("Unable to get the timer clock\n"); - return; - } - - rv = davinci_timer_register(clk, &da830_timer_cfg); - WARN(rv, "Unable to register the timer: %d\n", rv); -} - -static struct resource da830_psc0_resources[] = { - { - .start = DA8XX_PSC0_BASE, - .end = DA8XX_PSC0_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device da830_psc0_device = { - .name = "da830-psc0", - .id = -1, - .resource = da830_psc0_resources, - .num_resources = ARRAY_SIZE(da830_psc0_resources), -}; - -static struct resource da830_psc1_resources[] = { - { - .start = DA8XX_PSC1_BASE, - .end = DA8XX_PSC1_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device da830_psc1_device = { - .name = "da830-psc1", - .id = -1, - .resource = da830_psc1_resources, - .num_resources = ARRAY_SIZE(da830_psc1_resources), -}; - -void __init da830_register_clocks(void) -{ - /* PLL is registered in da830_init_time() */ - platform_device_register(&da830_psc0_device); - platform_device_register(&da830_psc1_device); -} diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 635e88daf5dd..287dd987908e 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -10,19 +10,10 @@ * 2009 (c) MontaVista Software, Inc. */ -#include -#include -#include -#include #include #include #include -#include #include -#include -#include -#include -#include #include #include #include @@ -33,6 +24,7 @@ #include "common.h" #include "cputype.h" #include "da8xx.h" +#include "hardware.h" #include "pm.h" #include "irqs.h" #include "mux.h" @@ -258,45 +250,6 @@ static const struct mux_config da850_pins[] = { #endif }; -const short da850_i2c0_pins[] __initconst = { - DA850_I2C0_SDA, DA850_I2C0_SCL, - -1 -}; - -const short da850_i2c1_pins[] __initconst = { - DA850_I2C1_SCL, DA850_I2C1_SDA, - -1 -}; - -const short da850_lcdcntl_pins[] __initconst = { - DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3, - DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7, - DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11, - DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15, - DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS, - -1 -}; - -const short da850_vpif_capture_pins[] __initconst = { - DA850_VPIF_DIN0, DA850_VPIF_DIN1, DA850_VPIF_DIN2, DA850_VPIF_DIN3, - DA850_VPIF_DIN4, DA850_VPIF_DIN5, DA850_VPIF_DIN6, DA850_VPIF_DIN7, - DA850_VPIF_DIN8, DA850_VPIF_DIN9, DA850_VPIF_DIN10, DA850_VPIF_DIN11, - DA850_VPIF_DIN12, DA850_VPIF_DIN13, DA850_VPIF_DIN14, DA850_VPIF_DIN15, - DA850_VPIF_CLKIN0, DA850_VPIF_CLKIN1, DA850_VPIF_CLKIN2, - DA850_VPIF_CLKIN3, - -1 -}; - -const short da850_vpif_display_pins[] __initconst = { - DA850_VPIF_DOUT0, DA850_VPIF_DOUT1, DA850_VPIF_DOUT2, DA850_VPIF_DOUT3, - DA850_VPIF_DOUT4, DA850_VPIF_DOUT5, DA850_VPIF_DOUT6, DA850_VPIF_DOUT7, - DA850_VPIF_DOUT8, DA850_VPIF_DOUT9, DA850_VPIF_DOUT10, - DA850_VPIF_DOUT11, DA850_VPIF_DOUT12, DA850_VPIF_DOUT13, - DA850_VPIF_DOUT14, DA850_VPIF_DOUT15, DA850_VPIF_CLKO2, - DA850_VPIF_CLKO3, - -1 -}; - static struct map_desc da850_io_desc[] = { { .virtual = IO_VIRT, @@ -330,204 +283,9 @@ static struct davinci_id da850_ids[] = { }, }; -/* - * Bottom half of timer 0 is used for clock_event, top half for - * clocksource. - */ -static const struct davinci_timer_cfg da850_timer_cfg = { - .reg = DEFINE_RES_IO(DA8XX_TIMER64P0_BASE, SZ_4K), - .irq = { - DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0)), - DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_0)), - }, -}; - -#ifdef CONFIG_CPU_FREQ -/* - * Notes: - * According to the TRM, minimum PLLM results in maximum power savings. - * The OPP definitions below should keep the PLLM as low as possible. - * - * The output of the PLLM must be between 300 to 600 MHz. - */ -struct da850_opp { - unsigned int freq; /* in KHz */ - unsigned int prediv; - unsigned int mult; - unsigned int postdiv; - unsigned int cvdd_min; /* in uV */ - unsigned int cvdd_max; /* in uV */ -}; - -static const struct da850_opp da850_opp_456 = { - .freq = 456000, - .prediv = 1, - .mult = 19, - .postdiv = 1, - .cvdd_min = 1300000, - .cvdd_max = 1350000, -}; - -static const struct da850_opp da850_opp_408 = { - .freq = 408000, - .prediv = 1, - .mult = 17, - .postdiv = 1, - .cvdd_min = 1300000, - .cvdd_max = 1350000, -}; - -static const struct da850_opp da850_opp_372 = { - .freq = 372000, - .prediv = 2, - .mult = 31, - .postdiv = 1, - .cvdd_min = 1200000, - .cvdd_max = 1320000, -}; - -static const struct da850_opp da850_opp_300 = { - .freq = 300000, - .prediv = 1, - .mult = 25, - .postdiv = 2, - .cvdd_min = 1200000, - .cvdd_max = 1320000, -}; - -static const struct da850_opp da850_opp_200 = { - .freq = 200000, - .prediv = 1, - .mult = 25, - .postdiv = 3, - .cvdd_min = 1100000, - .cvdd_max = 1160000, -}; - -static const struct da850_opp da850_opp_96 = { - .freq = 96000, - .prediv = 1, - .mult = 20, - .postdiv = 5, - .cvdd_min = 1000000, - .cvdd_max = 1050000, -}; - -#define OPP(freq) \ - { \ - .driver_data = (unsigned int) &da850_opp_##freq, \ - .frequency = freq * 1000, \ - } - -static struct cpufreq_frequency_table da850_freq_table[] = { - OPP(456), - OPP(408), - OPP(372), - OPP(300), - OPP(200), - OPP(96), - { - .driver_data = 0, - .frequency = CPUFREQ_TABLE_END, - }, -}; - -#ifdef CONFIG_REGULATOR -static int da850_set_voltage(unsigned int index); -static int da850_regulator_init(void); -#endif - -static struct davinci_cpufreq_config cpufreq_info = { - .freq_table = da850_freq_table, -#ifdef CONFIG_REGULATOR - .init = da850_regulator_init, - .set_voltage = da850_set_voltage, -#endif -}; - -#ifdef CONFIG_REGULATOR -static struct regulator *cvdd; - -static int da850_set_voltage(unsigned int index) -{ - struct da850_opp *opp; - - if (!cvdd) - return -ENODEV; - - opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data; - - return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max); -} - -static int da850_regulator_init(void) -{ - cvdd = regulator_get(NULL, "cvdd"); - if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;" - " voltage scaling unsupported\n")) { - return PTR_ERR(cvdd); - } - - return 0; -} -#endif - -static struct platform_device da850_cpufreq_device = { - .name = "cpufreq-davinci", - .dev = { - .platform_data = &cpufreq_info, - }, - .id = -1, -}; - -unsigned int da850_max_speed = 300000; - -int da850_register_cpufreq(char *async_clk) -{ - int i; - - /* cpufreq driver can help keep an "async" clock constant */ - if (async_clk) - clk_add_alias("async", da850_cpufreq_device.name, - async_clk, NULL); - for (i = 0; i < ARRAY_SIZE(da850_freq_table); i++) { - if (da850_freq_table[i].frequency <= da850_max_speed) { - cpufreq_info.freq_table = &da850_freq_table[i]; - break; - } - } - - return platform_device_register(&da850_cpufreq_device); -} -#else -int __init da850_register_cpufreq(char *async_clk) -{ - return 0; -} -#endif - /* VPIF resource, platform data */ static u64 da850_vpif_dma_mask = DMA_BIT_MASK(32); -static struct resource da850_vpif_resource[] = { - { - .start = DA8XX_VPIF_BASE, - .end = DA8XX_VPIF_BASE + 0xfff, - .flags = IORESOURCE_MEM, - } -}; - -static struct platform_device da850_vpif_dev = { - .name = "vpif", - .id = -1, - .dev = { - .dma_mask = &da850_vpif_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = da850_vpif_resource, - .num_resources = ARRAY_SIZE(da850_vpif_resource), -}; - static struct resource da850_vpif_display_resource[] = { { .start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT), @@ -571,11 +329,6 @@ static struct platform_device da850_vpif_capture_dev = { .num_resources = ARRAY_SIZE(da850_vpif_capture_resource), }; -int __init da850_register_vpif(void) -{ - return platform_device_register(&da850_vpif_dev); -} - int __init da850_register_vpif_display(struct vpif_display_config *display_config) { @@ -590,17 +343,6 @@ int __init da850_register_vpif_capture(struct vpif_capture_config return platform_device_register(&da850_vpif_capture_dev); } -static struct davinci_gpio_platform_data da850_gpio_platform_data = { - .no_auto_base = true, - .base = 0, - .ngpio = 144, -}; - -int __init da850_register_gpio(void) -{ - return da8xx_register_gpio(&da850_gpio_platform_data); -} - static const struct davinci_soc_info davinci_soc_info_da850 = { .io_desc = da850_io_desc, .io_desc_num = ARRAY_SIZE(da850_io_desc), @@ -610,7 +352,6 @@ static const struct davinci_soc_info davinci_soc_info_da850 = { .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120, .pinmux_pins = da850_pins, .pinmux_pins_num = ARRAY_SIZE(da850_pins), - .emac_pdata = &da8xx_emac_pdata, .sram_dma = DA8XX_SHARED_RAM_BASE, .sram_len = SZ_128K, }; @@ -626,142 +367,3 @@ void __init da850_init(void) da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K); WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"); } - -static const struct davinci_cp_intc_config da850_cp_intc_config = { - .reg = { - .start = DA8XX_CP_INTC_BASE, - .end = DA8XX_CP_INTC_BASE + SZ_8K - 1, - .flags = IORESOURCE_MEM, - }, - .num_irqs = DA850_N_CP_INTC_IRQ, -}; - -void __init da850_init_irq(void) -{ - davinci_cp_intc_init(&da850_cp_intc_config); -} - -void __init da850_init_time(void) -{ - void __iomem *pll0; - struct regmap *cfgchip; - struct clk *clk; - int rv; - - clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DA850_REF_FREQ); - - pll0 = ioremap(DA8XX_PLL0_BASE, SZ_4K); - cfgchip = da8xx_get_cfgchip(); - - da850_pll0_init(NULL, pll0, cfgchip); - - clk = clk_get(NULL, "timer0"); - if (WARN_ON(IS_ERR(clk))) { - pr_err("Unable to get the timer clock\n"); - return; - } - - rv = davinci_timer_register(clk, &da850_timer_cfg); - WARN(rv, "Unable to register the timer: %d\n", rv); -} - -static struct resource da850_pll1_resources[] = { - { - .start = DA850_PLL1_BASE, - .end = DA850_PLL1_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct davinci_pll_platform_data da850_pll1_pdata; - -static struct platform_device da850_pll1_device = { - .name = "da850-pll1", - .id = -1, - .resource = da850_pll1_resources, - .num_resources = ARRAY_SIZE(da850_pll1_resources), - .dev = { - .platform_data = &da850_pll1_pdata, - }, -}; - -static struct resource da850_psc0_resources[] = { - { - .start = DA8XX_PSC0_BASE, - .end = DA8XX_PSC0_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device da850_psc0_device = { - .name = "da850-psc0", - .id = -1, - .resource = da850_psc0_resources, - .num_resources = ARRAY_SIZE(da850_psc0_resources), -}; - -static struct resource da850_psc1_resources[] = { - { - .start = DA8XX_PSC1_BASE, - .end = DA8XX_PSC1_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device da850_psc1_device = { - .name = "da850-psc1", - .id = -1, - .resource = da850_psc1_resources, - .num_resources = ARRAY_SIZE(da850_psc1_resources), -}; - -static struct da8xx_cfgchip_clk_platform_data da850_async1_pdata; - -static struct platform_device da850_async1_clksrc_device = { - .name = "da850-async1-clksrc", - .id = -1, - .dev = { - .platform_data = &da850_async1_pdata, - }, -}; - -static struct da8xx_cfgchip_clk_platform_data da850_async3_pdata; - -static struct platform_device da850_async3_clksrc_device = { - .name = "da850-async3-clksrc", - .id = -1, - .dev = { - .platform_data = &da850_async3_pdata, - }, -}; - -static struct da8xx_cfgchip_clk_platform_data da850_tbclksync_pdata; - -static struct platform_device da850_tbclksync_device = { - .name = "da830-tbclksync", - .id = -1, - .dev = { - .platform_data = &da850_tbclksync_pdata, - }, -}; - -void __init da850_register_clocks(void) -{ - /* PLL0 is registered in da850_init_time() */ - - da850_pll1_pdata.cfgchip = da8xx_get_cfgchip(); - platform_device_register(&da850_pll1_device); - - da850_async1_pdata.cfgchip = da8xx_get_cfgchip(); - platform_device_register(&da850_async1_clksrc_device); - - da850_async3_pdata.cfgchip = da8xx_get_cfgchip(); - platform_device_register(&da850_async3_clksrc_device); - - platform_device_register(&da850_psc0_device); - - platform_device_register(&da850_psc1_device); - - da850_tbclksync_pdata.cfgchip = da8xx_get_cfgchip(); - platform_device_register(&da850_tbclksync_device); -} diff --git a/arch/arm/mach-davinci/da8xx.h b/arch/arm/mach-davinci/da8xx.h index 382811dbbc3b..54a255b8d8d8 100644 --- a/arch/arm/mach-davinci/da8xx.h +++ b/arch/arm/mach-davinci/da8xx.h @@ -9,38 +9,20 @@ #ifndef __ASM_ARCH_DAVINCI_DA8XX_H #define __ASM_ARCH_DAVINCI_DA8XX_H -#include