From a797a0e242b94548af8b41e6454349b515b66eca Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Sat, 12 Dec 2009 14:27:40 +0000 Subject: Blackfin: NOMPU: skip DMA ICPLB hole when it is redundant Normally there is no user-reserved memory after the DMA region which means there is no user-reserved ICPLB coverage. So the DMA hole can be covered by the large hole that is always added to cover up to the async bank. We only need an explicit DMA whole when we also add an explicit mapping for the user-reserved memory. Signed-off-by: Mike Frysinger --- arch/blackfin/kernel/cplb-nompu/cplbinit.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) (limited to 'arch/blackfin/kernel/cplb-nompu') diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c index c9b0a4d53dc1..282a7919821b 100644 --- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c +++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c @@ -147,12 +147,13 @@ void __init generate_cplb_tables_all(void) /* Normal RAM, including MTD FS. */ icplb_bounds[i_i].eaddr = uncached_end; icplb_bounds[i_i++].data = SDRAM_IGENERIC; - /* DMA uncached region. */ - if (DMA_UNCACHED_REGION) { - icplb_bounds[i_i].eaddr = _ramend; - icplb_bounds[i_i++].data = 0; - } if (_ramend != physical_mem_end) { + /* DMA uncached region. */ + if (DMA_UNCACHED_REGION) { + /* Normally this hole is caught by the async below. */ + icplb_bounds[i_i].eaddr = _ramend; + icplb_bounds[i_i++].data = 0; + } /* Reserved memory. */ icplb_bounds[i_i].eaddr = physical_mem_end; icplb_bounds[i_i++].data = (reserved_mem_icache_on ? -- cgit