From 8d20a541b089ecb67a88a673548161b686ed7b85 Mon Sep 17 00:00:00 2001 From: Mikael Starvik Date: Wed, 27 Jul 2005 11:44:42 -0700 Subject: [PATCH] CRIS update: SMP Patches to support SMP. * Each CPU has its own current_pgd. * flush_tlb_range is implemented as flush_tlb_mm. * Atomic operations implemented with spinlocks. * Semaphores implemented with spinlocks. Signed-off-by: Mikael Starvik Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/cris/arch-v10/mm/fault.c | 26 ++--------------------- arch/cris/arch-v10/mm/init.c | 2 +- arch/cris/arch-v10/mm/tlb.c | 49 +------------------------------------------ 3 files changed, 4 insertions(+), 73 deletions(-) (limited to 'arch/cris') diff --git a/arch/cris/arch-v10/mm/fault.c b/arch/cris/arch-v10/mm/fault.c index 6805cdb25a53..fe2615022b97 100644 --- a/arch/cris/arch-v10/mm/fault.c +++ b/arch/cris/arch-v10/mm/fault.c @@ -14,6 +14,7 @@ #include #include #include +#include /* debug of low-level TLB reload */ #undef DEBUG @@ -24,8 +25,6 @@ #define D(x) #endif -extern volatile pgd_t *current_pgd; - extern const struct exception_table_entry *search_exception_tables(unsigned long addr); @@ -46,7 +45,7 @@ handle_mmu_bus_fault(struct pt_regs *regs) int page_id; int acc, inv; #endif - pgd_t* pgd = (pgd_t*)current_pgd; + pgd_t* pgd = (pgd_t*)per_cpu(current_pgd, smp_processor_id()); pmd_t *pmd; pte_t pte; int miss, we, writeac; @@ -94,24 +93,3 @@ handle_mmu_bus_fault(struct pt_regs *regs) *R_TLB_LO = pte_val(pte); local_irq_restore(flags); } - -/* Called from arch/cris/mm/fault.c to find fixup code. */ -int -find_fixup_code(struct pt_regs *regs) -{ - const struct exception_table_entry *fixup; - - if ((fixup = search_exception_tables(regs->irp)) != 0) { - /* Adjust the instruction pointer in the stackframe. */ - regs->irp = fixup->fixup; - - /* - * Don't return by restoring the CPU state, so switch - * frame-type. - */ - regs->frametype = CRIS_FRAME_NORMAL; - return 1; - } - - return 0; -} diff --git a/arch/cris/arch-v10/mm/init.c b/arch/cris/arch-v10/mm/init.c index a9f975a9cfb5..ff3481e76dd4 100644 --- a/arch/cris/arch-v10/mm/init.c +++ b/arch/cris/arch-v10/mm/init.c @@ -42,7 +42,7 @@ paging_init(void) * switch_mm) */ - current_pgd = init_mm.pgd; + per_cpu(current_pgd, smp_processor_id()) = init_mm.pgd; /* initialise the TLB (tlb.c) */ diff --git a/arch/cris/arch-v10/mm/tlb.c b/arch/cris/arch-v10/mm/tlb.c index 9d06125ff5a2..70a5523eff78 100644 --- a/arch/cris/arch-v10/mm/tlb.c +++ b/arch/cris/arch-v10/mm/tlb.c @@ -139,53 +139,6 @@ flush_tlb_page(struct vm_area_struct *vma, local_irq_restore(flags); } -/* invalidate a page range */ - -void -flush_tlb_range(struct vm_area_struct *vma, - unsigned long start, - unsigned long end) -{ - struct mm_struct *mm = vma->vm_mm; - int page_id = mm->context.page_id; - int i; - unsigned long flags; - - D(printk("tlb: flush range %p<->%p in context %d (%p)\n", - start, end, page_id, mm)); - - if(page_id == NO_CONTEXT) - return; - - start &= PAGE_MASK; /* probably not necessary */ - end &= PAGE_MASK; /* dito */ - - /* invalidate those TLB entries that match both the mm context - * and the virtual address range - */ - - local_save_flags(flags); - local_irq_disable(); - for(i = 0; i < NUM_TLB_ENTRIES; i++) { - unsigned long tlb_hi, vpn; - *R_TLB_SELECT = IO_FIELD(R_TLB_SELECT, index, i); - tlb_hi = *R_TLB_HI; - vpn = tlb_hi & PAGE_MASK; - if (IO_EXTRACT(R_TLB_HI, page_id, tlb_hi) == page_id && - vpn >= start && vpn < end) { - *R_TLB_HI = ( IO_FIELD(R_TLB_HI, page_id, INVALID_PAGEID ) | - IO_FIELD(R_TLB_HI, vpn, i & 0xf ) ); - - *R_TLB_LO = ( IO_STATE(R_TLB_LO, global,no ) | - IO_STATE(R_TLB_LO, valid, no ) | - IO_STATE(R_TLB_LO, kernel,no ) | - IO_STATE(R_TLB_LO, we, no ) | - IO_FIELD(R_TLB_LO, pfn, 0 ) ); - } - } - local_irq_restore(flags); -} - /* dump the entire TLB for debug purposes */ #if 0 @@ -237,7 +190,7 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next, * the pgd. */ - current_pgd = next->pgd; + per_cpu(current_pgd, smp_processor_id()) = next->pgd; /* switch context in the MMU */ -- cgit