From 35de674982aa13de98cf470c640895164017563e Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Mon, 4 Jul 2011 15:30:55 +1000 Subject: m68k: fix some atomic operation asm address modes for ColdFire The ColdFire processors have a much more limited set of addressing modes that can be used for most instructions. A number of the atomic operations have already been fixed to limit the addressing modes used with add and sub instructions when building for ColdFire. But we missed a few. Fix the remaining atomic operations to be clean for ColdFire processors. Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/atomic.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/m68k/include/asm/atomic.h') diff --git a/arch/m68k/include/asm/atomic.h b/arch/m68k/include/asm/atomic.h index 03ae3d14cd4a..307a573881ad 100644 --- a/arch/m68k/include/asm/atomic.h +++ b/arch/m68k/include/asm/atomic.h @@ -169,18 +169,18 @@ static inline int atomic_add_negative(int i, atomic_t *v) char c; __asm__ __volatile__("addl %2,%1; smi %0" : "=d" (c), "+m" (*v) - : "id" (i)); + : ASM_DI (i)); return c != 0; } static inline void atomic_clear_mask(unsigned long mask, unsigned long *v) { - __asm__ __volatile__("andl %1,%0" : "+m" (*v) : "id" (~(mask))); + __asm__ __volatile__("andl %1,%0" : "+m" (*v) : ASM_DI (~(mask))); } static inline void atomic_set_mask(unsigned long mask, unsigned long *v) { - __asm__ __volatile__("orl %1,%0" : "+m" (*v) : "id" (mask)); + __asm__ __volatile__("orl %1,%0" : "+m" (*v) : ASM_DI (mask)); } static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) -- cgit