From a12cf0a8c6e2763ac865aa31f296557e07432b8a Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Tue, 9 Nov 2010 10:12:29 +1000 Subject: m68knommu: create bit definitions for the version 2 ColdFire cache controller The version 2 ColdFire CPU based cores all contain a similar cache controller unit. Create a set of bit flag definitions for the supporting registers. Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m520xsim.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/m68k/include/asm/m520xsim.h') diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h index 8cd8bce38594..88ed8239fe4e 100644 --- a/arch/m68k/include/asm/m520xsim.h +++ b/arch/m68k/include/asm/m520xsim.h @@ -14,6 +14,8 @@ #define CPU_NAME "COLDFIRE(m520x)" #define CPU_INSTR_PER_JIFFY 3 +#include + /* * Define the 520x SIM register set addresses. */ @@ -57,6 +59,9 @@ #define MCFSIM_SDCS0 0x000a8110 /* SDRAM Chip Select 0 Configuration */ #define MCFSIM_SDCS1 0x000a8114 /* SDRAM Chip Select 1 Configuration */ +/* + * EPORT and GPIO registers. + */ #define MCFEPORT_EPDDR 0xFC088002 #define MCFEPORT_EPDR 0xFC088004 #define MCFEPORT_EPPDR 0xFC088005 -- cgit