From 162e134aedcacc9ab9d5648349ceb5409f9ec880 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Tue, 21 Feb 2023 13:16:57 +0000 Subject: MIPS: Loongson64: Remove CPU_HAS_WB Q: Do we have really have write buffer A: Yes, on newer Loongson processors there is a "store fill buffer" that will collect *cached* writes, on all Loongson processors AXI crossbar will buffer all writes. Q: Then why do we want to remove CPU_HAS_WB? A: Because CPU_HAS_WB introduces wbflush, which intends to flush all write reuqests to mmio device. We won't be affected by store fill buffer because it won't buffer uncached writes. And a regular memory barrier is sufficient to flush crossbar write buffer. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/mips/Kconfig') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index e2f3ca73f40d..6f275ace27be 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -490,7 +490,6 @@ config MACH_LOONGSON64 select BOARD_SCACHE select CSRC_R4K select CEVT_R4K - select CPU_HAS_WB select FORCE_PCI select ISA select I8259 -- cgit