From 9bd9f9cba6f914bc414c90e790d8ae2307bf17c3 Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Tue, 8 Jul 2014 16:53:18 +0200 Subject: MIPS: BCM63xx: Remove !RUNTIME_DETECT from irq setup code Signed-off-by: Jonas Gorski Cc: linux-mips@linux-mips.org Cc: John Crispin Cc: Maxime Bizon Cc: Florian Fainelli Cc: Kevin Cernekee Patchwork: https://patchwork.linux-mips.org/patch/7267/ Signed-off-by: Ralf Baechle --- arch/mips/bcm63xx/irq.c | 109 ------------------------------------------------ 1 file changed, 109 deletions(-) (limited to 'arch/mips/bcm63xx') diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c index 1525f8a3841b..30c6803b5403 100644 --- a/arch/mips/bcm63xx/irq.c +++ b/arch/mips/bcm63xx/irq.c @@ -26,114 +26,6 @@ static void __internal_irq_mask_64(unsigned int irq) __maybe_unused; static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused; static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused; -#ifndef BCMCPU_RUNTIME_DETECT -#ifdef CONFIG_BCM63XX_CPU_3368 -#define irq_stat_reg PERF_IRQSTAT_3368_REG -#define irq_mask_reg PERF_IRQMASK_3368_REG -#define irq_bits 32 -#define is_ext_irq_cascaded 0 -#define ext_irq_start 0 -#define ext_irq_end 0 -#define ext_irq_count 4 -#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_3368 -#define ext_irq_cfg_reg2 0 -#endif -#ifdef CONFIG_BCM63XX_CPU_6328 -#define irq_stat_reg PERF_IRQSTAT_6328_REG -#define irq_mask_reg PERF_IRQMASK_6328_REG -#define irq_bits 64 -#define is_ext_irq_cascaded 1 -#define ext_irq_start (BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE) -#define ext_irq_end (BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE) -#define ext_irq_count 4 -#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6328 -#define ext_irq_cfg_reg2 0 -#endif -#ifdef CONFIG_BCM63XX_CPU_6338 -#define irq_stat_reg PERF_IRQSTAT_6338_REG -#define irq_mask_reg PERF_IRQMASK_6338_REG -#define irq_bits 32 -#define is_ext_irq_cascaded 0 -#define ext_irq_start 0 -#define ext_irq_end 0 -#define ext_irq_count 4 -#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6338 -#define ext_irq_cfg_reg2 0 -#endif -#ifdef CONFIG_BCM63XX_CPU_6345 -#define irq_stat_reg PERF_IRQSTAT_6345_REG -#define irq_mask_reg PERF_IRQMASK_6345_REG -#define irq_bits 32 -#define is_ext_irq_cascaded 0 -#define ext_irq_start 0 -#define ext_irq_end 0 -#define ext_irq_count 4 -#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6345 -#define ext_irq_cfg_reg2 0 -#endif -#ifdef CONFIG_BCM63XX_CPU_6348 -#define irq_stat_reg PERF_IRQSTAT_6348_REG -#define irq_mask_reg PERF_IRQMASK_6348_REG -#define irq_bits 32 -#define is_ext_irq_cascaded 0 -#define ext_irq_start 0 -#define ext_irq_end 0 -#define ext_irq_count 4 -#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6348 -#define ext_irq_cfg_reg2 0 -#endif -#ifdef CONFIG_BCM63XX_CPU_6358 -#define irq_stat_reg PERF_IRQSTAT_6358_REG -#define irq_mask_reg PERF_IRQMASK_6358_REG -#define irq_bits 32 -#define is_ext_irq_cascaded 1 -#define ext_irq_start (BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE) -#define ext_irq_end (BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE) -#define ext_irq_count 4 -#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6358 -#define ext_irq_cfg_reg2 0 -#endif -#ifdef CONFIG_BCM63XX_CPU_6362 -#define irq_stat_reg PERF_IRQSTAT_6362_REG -#define irq_mask_reg PERF_IRQMASK_6362_REG -#define irq_bits 64 -#define is_ext_irq_cascaded 1 -#define ext_irq_start (BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE) -#define ext_irq_end (BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE) -#define ext_irq_count 4 -#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6362 -#define ext_irq_cfg_reg2 0 -#endif -#ifdef CONFIG_BCM63XX_CPU_6368 -#define irq_stat_reg PERF_IRQSTAT_6368_REG -#define irq_mask_reg PERF_IRQMASK_6368_REG -#define irq_bits 64 -#define is_ext_irq_cascaded 1 -#define ext_irq_start (BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE) -#define ext_irq_end (BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE) -#define ext_irq_count 6 -#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6368 -#define ext_irq_cfg_reg2 PERF_EXTIRQ_CFG_REG2_6368 -#endif - -#if irq_bits == 32 -#define dispatch_internal __dispatch_internal -#define internal_irq_mask __internal_irq_mask_32 -#define internal_irq_unmask __internal_irq_unmask_32 -#else -#define dispatch_internal __dispatch_internal_64 -#define internal_irq_mask __internal_irq_mask_64 -#define internal_irq_unmask __internal_irq_unmask_64 -#endif - -#define irq_stat_addr (bcm63xx_regset_address(RSET_PERF) + irq_stat_reg) -#define irq_mask_addr (bcm63xx_regset_address(RSET_PERF) + irq_mask_reg) - -static inline void bcm63xx_init_irq(void) -{ -} -#else /* ! BCMCPU_RUNTIME_DETECT */ - static u32 irq_stat_addr, irq_mask_addr; static void (*dispatch_internal)(void); static int is_ext_irq_cascaded; @@ -234,7 +126,6 @@ static void bcm63xx_init_irq(void) internal_irq_unmask = __internal_irq_unmask_64; } } -#endif /* ! BCMCPU_RUNTIME_DETECT */ static inline u32 get_ext_irq_perf_reg(int irq) { -- cgit From fe0a5f1c28467842e943d7f91cc450cc532d9923 Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Tue, 8 Jul 2014 16:53:19 +0200 Subject: MIPS: BCM63xx: Remove !RUNTIME_DETECT from reset code Signed-off-by: Jonas Gorski Cc: linux-mips@linux-mips.org Cc: John Crispin Cc: Maxime Bizon Cc: Florian Fainelli Cc: Kevin Cernekee Patchwork: https://patchwork.linux-mips.org/patch/7268/ Signed-off-by: Ralf Baechle --- arch/mips/bcm63xx/reset.c | 60 ----------------------------------------------- 1 file changed, 60 deletions(-) (limited to 'arch/mips/bcm63xx') diff --git a/arch/mips/bcm63xx/reset.c b/arch/mips/bcm63xx/reset.c index acbeb1fe7c57..d1fe51edf5e6 100644 --- a/arch/mips/bcm63xx/reset.c +++ b/arch/mips/bcm63xx/reset.c @@ -125,8 +125,6 @@ #define BCM6368_RESET_PCIE 0 #define BCM6368_RESET_PCIE_EXT 0 -#ifdef BCMCPU_RUNTIME_DETECT - /* * core reset bits */ @@ -188,64 +186,6 @@ static int __init bcm63xx_reset_bits_init(void) return 0; } -#else - -#ifdef CONFIG_BCM63XX_CPU_3368 -static const u32 bcm63xx_reset_bits[] = { - __GEN_RESET_BITS_TABLE(3368) -}; -#define reset_reg PERF_SOFTRESET_6358_REG -#endif - -#ifdef CONFIG_BCM63XX_CPU_6328 -static const u32 bcm63xx_reset_bits[] = { - __GEN_RESET_BITS_TABLE(6328) -}; -#define reset_reg PERF_SOFTRESET_6328_REG -#endif - -#ifdef CONFIG_BCM63XX_CPU_6338 -static const u32 bcm63xx_reset_bits[] = { - __GEN_RESET_BITS_TABLE(6338) -}; -#define reset_reg PERF_SOFTRESET_REG -#endif - -#ifdef CONFIG_BCM63XX_CPU_6345 -static const u32 bcm63xx_reset_bits[] = { }; -#define reset_reg 0 -#endif - -#ifdef CONFIG_BCM63XX_CPU_6348 -static const u32 bcm63xx_reset_bits[] = { - __GEN_RESET_BITS_TABLE(6348) -}; -#define reset_reg PERF_SOFTRESET_REG -#endif - -#ifdef CONFIG_BCM63XX_CPU_6358 -static const u32 bcm63xx_reset_bits[] = { - __GEN_RESET_BITS_TABLE(6358) -}; -#define reset_reg PERF_SOFTRESET_6358_REG -#endif - -#ifdef CONFIG_BCM63XX_CPU_6362 -static const u32 bcm63xx_reset_bits[] = { - __GEN_RESET_BITS_TABLE(6362) -}; -#define reset_reg PERF_SOFTRESET_6362_REG -#endif - -#ifdef CONFIG_BCM63XX_CPU_6368 -static const u32 bcm63xx_reset_bits[] = { - __GEN_RESET_BITS_TABLE(6368) -}; -#define reset_reg PERF_SOFTRESET_6368_REG -#endif - -static int __init bcm63xx_reset_bits_init(void) { return 0; } -#endif static DEFINE_SPINLOCK(reset_mutex); -- cgit From 53a02272e49260713f05c798953c6c9e04be4175 Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Tue, 8 Jul 2014 16:53:20 +0200 Subject: MIPS: BCM63xx: Remove !RUNTIME_DETECT code from gpio code Signed-off-by: Jonas Gorski Cc: linux-mips@linux-mips.org Cc: John Crispin Cc: Maxime Bizon Cc: Florian Fainelli Cc: Kevin Cernekee Patchwork: https://patchwork.linux-mips.org/patch/7269/ Signed-off-by: Ralf Baechle --- arch/mips/bcm63xx/gpio.c | 14 -------------- 1 file changed, 14 deletions(-) (limited to 'arch/mips/bcm63xx') diff --git a/arch/mips/bcm63xx/gpio.c b/arch/mips/bcm63xx/gpio.c index a6c2135dbf38..468bc7b99cd3 100644 --- a/arch/mips/bcm63xx/gpio.c +++ b/arch/mips/bcm63xx/gpio.c @@ -18,19 +18,6 @@ #include #include -#ifndef BCMCPU_RUNTIME_DETECT -#define gpio_out_low_reg GPIO_DATA_LO_REG -#ifdef CONFIG_BCM63XX_CPU_6345 -#ifdef gpio_out_low_reg -#undef gpio_out_low_reg -#define gpio_out_low_reg GPIO_DATA_LO_REG_6345 -#endif /* gpio_out_low_reg */ -#endif /* CONFIG_BCM63XX_CPU_6345 */ - -static inline void bcm63xx_gpio_out_low_reg_init(void) -{ -} -#else /* ! BCMCPU_RUNTIME_DETECT */ static u32 gpio_out_low_reg; static void bcm63xx_gpio_out_low_reg_init(void) @@ -44,7 +31,6 @@ static void bcm63xx_gpio_out_low_reg_init(void) break; } } -#endif /* ! BCMCPU_RUNTIME_DETECT */ static DEFINE_SPINLOCK(bcm63xx_gpio_lock); static u32 gpio_out_low, gpio_out_high; -- cgit From ee685808243742becae89f5f4553893387543f08 Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Tue, 8 Jul 2014 16:53:21 +0200 Subject: MIPS: BCM63xx: Remove !RUNTIME_DETECT from spi code Signed-off-by: Jonas Gorski Cc: linux-mips@linux-mips.org Cc: John Crispin Cc: Maxime Bizon Cc: Florian Fainelli Cc: Kevin Cernekee Patchwork: https://patchwork.linux-mips.org/patch/7271/ Signed-off-by: Ralf Baechle --- arch/mips/bcm63xx/dev-spi.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch/mips/bcm63xx') diff --git a/arch/mips/bcm63xx/dev-spi.c b/arch/mips/bcm63xx/dev-spi.c index d12daed749bc..ad448e41e3bd 100644 --- a/arch/mips/bcm63xx/dev-spi.c +++ b/arch/mips/bcm63xx/dev-spi.c @@ -18,7 +18,6 @@ #include #include -#ifdef BCMCPU_RUNTIME_DETECT /* * register offsets */ @@ -41,9 +40,6 @@ static __init void bcm63xx_spi_regs_init(void) BCMCPU_IS_6362() || BCMCPU_IS_6368()) bcm63xx_regs_spi = bcm6358_regs_spi; } -#else -static __init void bcm63xx_spi_regs_init(void) { } -#endif static struct resource spi_resources[] = { { -- cgit From e7101c2ae2a6a2b10e9bb256205dfe9100840777 Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Tue, 8 Jul 2014 16:53:22 +0200 Subject: MIPS: BCM63xx: Remove !RUNTIME_DETECT usage from enet code Cc: linux-mips@linux-mips.org Cc: John Crispin Cc: Maxime Bizon Cc: Florian Fainelli Cc: Kevin Cernekee Patchwork: https://patchwork.linux-mips.org/patch/7270/ Signed-off-by: Ralf Baechle --- arch/mips/bcm63xx/dev-enet.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch/mips/bcm63xx') diff --git a/arch/mips/bcm63xx/dev-enet.c b/arch/mips/bcm63xx/dev-enet.c index 52bc01df9bfe..e8284771d620 100644 --- a/arch/mips/bcm63xx/dev-enet.c +++ b/arch/mips/bcm63xx/dev-enet.c @@ -14,7 +14,6 @@ #include #include -#ifdef BCMCPU_RUNTIME_DETECT static const unsigned long bcm6348_regs_enetdmac[] = { [ENETDMAC_CHANCFG] = ENETDMAC_CHANCFG_REG, [ENETDMAC_IR] = ENETDMAC_IR_REG, @@ -43,9 +42,6 @@ static __init void bcm63xx_enetdmac_regs_init(void) else bcm63xx_regs_enetdmac = bcm6348_regs_enetdmac; } -#else -static __init void bcm63xx_enetdmac_regs_init(void) { } -#endif static struct resource shared_res[] = { { -- cgit From e86ae9e2e0c3badc74c81f3449b9d59513d8845c Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Tue, 8 Jul 2014 16:53:24 +0200 Subject: MIPS: BCM63xx: Remove !RUNTIME_DETECT code for bcmcpu_get_id Use the same pattern as with get_*_cpu_type() to allow the compiler to remove code for non enabled SoC types. Signed-off-by: Jonas Gorski Cc: linux-mips@linux-mips.org Cc: John Crispin Cc: Maxime Bizon Cc: Florian Fainelli Cc: Kevin Cernekee Patchwork: https://patchwork.linux-mips.org/patch/7273/ Signed-off-by: Ralf Baechle --- arch/mips/bcm63xx/cpu.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) (limited to 'arch/mips/bcm63xx') diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c index fd4e76c00a42..536f64443031 100644 --- a/arch/mips/bcm63xx/cpu.c +++ b/arch/mips/bcm63xx/cpu.c @@ -24,7 +24,9 @@ EXPORT_SYMBOL(bcm63xx_regs_base); const int *bcm63xx_irqs; EXPORT_SYMBOL(bcm63xx_irqs); -static u16 bcm63xx_cpu_id; +u16 bcm63xx_cpu_id __read_mostly; +EXPORT_SYMBOL(bcm63xx_cpu_id); + static u8 bcm63xx_cpu_rev; static unsigned int bcm63xx_cpu_freq; static unsigned int bcm63xx_memory_size; @@ -97,13 +99,6 @@ static const int bcm6368_irqs[] = { }; -u16 __bcm63xx_get_cpu_id(void) -{ - return bcm63xx_cpu_id; -} - -EXPORT_SYMBOL(__bcm63xx_get_cpu_id); - u8 bcm63xx_get_cpu_rev(void) { return bcm63xx_cpu_rev; -- cgit From a221a6b2826f2b49a60ffa77bd8b0b4c56d0aced Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Sat, 12 Jul 2014 12:49:33 +0200 Subject: MIPS: BCM63xx: Add width to __dispatch_internal Make it follow the same naming convention as the other functions. Signed-off-by: Jonas Gorski Cc: linux-mips@linux-mips.org Cc: John Crispin Cc: Maxime Bizon Cc: Florian Fainelli Cc: Kevin Cernekee Cc: Gregory Fong Patchwork: https://patchwork.linux-mips.org/patch/7314/ Signed-off-by: Ralf Baechle --- arch/mips/bcm63xx/irq.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/mips/bcm63xx') diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c index 30c6803b5403..a9fb564b194c 100644 --- a/arch/mips/bcm63xx/irq.c +++ b/arch/mips/bcm63xx/irq.c @@ -19,7 +19,7 @@ #include #include -static void __dispatch_internal(void) __maybe_unused; +static void __dispatch_internal_32(void) __maybe_unused; static void __dispatch_internal_64(void) __maybe_unused; static void __internal_irq_mask_32(unsigned int irq) __maybe_unused; static void __internal_irq_mask_64(unsigned int irq) __maybe_unused; @@ -117,7 +117,7 @@ static void bcm63xx_init_irq(void) } if (irq_bits == 32) { - dispatch_internal = __dispatch_internal; + dispatch_internal = __dispatch_internal_32; internal_irq_mask = __internal_irq_mask_32; internal_irq_unmask = __internal_irq_unmask_32; } else { @@ -149,7 +149,7 @@ static inline void handle_internal(int intbit) * will resume the loop where it ended the last time we left this * function. */ -static void __dispatch_internal(void) +static void __dispatch_internal_32(void) { u32 pending; static int i; -- cgit From a6dfde817cb45934e87d4493df0df3c12a6604e1 Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Sat, 12 Jul 2014 12:49:34 +0200 Subject: MIPS: BCM63xx: Move bcm63xx_init_irq down Allows up to drop the prototypes from the top. Signed-off-by: Jonas Gorski Cc: linux-mips@linux-mips.org Cc: John Crispin Cc: Maxime Bizon Cc: Florian Fainelli Cc: Kevin Cernekee Cc: Gregory Fong Patchwork: https://patchwork.linux-mips.org/patch/7315/ Signed-off-by: Ralf Baechle --- arch/mips/bcm63xx/irq.c | 190 +++++++++++++++++++++++------------------------- 1 file changed, 92 insertions(+), 98 deletions(-) (limited to 'arch/mips/bcm63xx') diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c index a9fb564b194c..f6c933a68c75 100644 --- a/arch/mips/bcm63xx/irq.c +++ b/arch/mips/bcm63xx/irq.c @@ -19,13 +19,6 @@ #include #include -static void __dispatch_internal_32(void) __maybe_unused; -static void __dispatch_internal_64(void) __maybe_unused; -static void __internal_irq_mask_32(unsigned int irq) __maybe_unused; -static void __internal_irq_mask_64(unsigned int irq) __maybe_unused; -static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused; -static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused; - static u32 irq_stat_addr, irq_mask_addr; static void (*dispatch_internal)(void); static int is_ext_irq_cascaded; @@ -35,97 +28,6 @@ static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2; static void (*internal_irq_mask)(unsigned int irq); static void (*internal_irq_unmask)(unsigned int irq); -static void bcm63xx_init_irq(void) -{ - int irq_bits; - - irq_stat_addr = bcm63xx_regset_address(RSET_PERF); - irq_mask_addr = bcm63xx_regset_address(RSET_PERF); - - switch (bcm63xx_get_cpu_id()) { - case BCM3368_CPU_ID: - irq_stat_addr += PERF_IRQSTAT_3368_REG; - irq_mask_addr += PERF_IRQMASK_3368_REG; - irq_bits = 32; - ext_irq_count = 4; - ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368; - break; - case BCM6328_CPU_ID: - irq_stat_addr += PERF_IRQSTAT_6328_REG; - irq_mask_addr += PERF_IRQMASK_6328_REG; - irq_bits = 64; - ext_irq_count = 4; - is_ext_irq_cascaded = 1; - ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE; - ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE; - ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328; - break; - case BCM6338_CPU_ID: - irq_stat_addr += PERF_IRQSTAT_6338_REG; - irq_mask_addr += PERF_IRQMASK_6338_REG; - irq_bits = 32; - ext_irq_count = 4; - ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338; - break; - case BCM6345_CPU_ID: - irq_stat_addr += PERF_IRQSTAT_6345_REG; - irq_mask_addr += PERF_IRQMASK_6345_REG; - irq_bits = 32; - ext_irq_count = 4; - ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345; - break; - case BCM6348_CPU_ID: - irq_stat_addr += PERF_IRQSTAT_6348_REG; - irq_mask_addr += PERF_IRQMASK_6348_REG; - irq_bits = 32; - ext_irq_count = 4; - ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348; - break; - case BCM6358_CPU_ID: - irq_stat_addr += PERF_IRQSTAT_6358_REG; - irq_mask_addr += PERF_IRQMASK_6358_REG; - irq_bits = 32; - ext_irq_count = 4; - is_ext_irq_cascaded = 1; - ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE; - ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE; - ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358; - break; - case BCM6362_CPU_ID: - irq_stat_addr += PERF_IRQSTAT_6362_REG; - irq_mask_addr += PERF_IRQMASK_6362_REG; - irq_bits = 64; - ext_irq_count = 4; - is_ext_irq_cascaded = 1; - ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE; - ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE; - ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362; - break; - case BCM6368_CPU_ID: - irq_stat_addr += PERF_IRQSTAT_6368_REG; - irq_mask_addr += PERF_IRQMASK_6368_REG; - irq_bits = 64; - ext_irq_count = 6; - is_ext_irq_cascaded = 1; - ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE; - ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE; - ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368; - ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368; - break; - default: - BUG(); - } - - if (irq_bits == 32) { - dispatch_internal = __dispatch_internal_32; - internal_irq_mask = __internal_irq_mask_32; - internal_irq_unmask = __internal_irq_unmask_32; - } else { - dispatch_internal = __dispatch_internal_64; - internal_irq_mask = __internal_irq_mask_64; - internal_irq_unmask = __internal_irq_unmask_64; - } -} static inline u32 get_ext_irq_perf_reg(int irq) { @@ -451,6 +353,98 @@ static struct irqaction cpu_ext_cascade_action = { .flags = IRQF_NO_THREAD, }; +static void bcm63xx_init_irq(void) +{ + int irq_bits; + + irq_stat_addr = bcm63xx_regset_address(RSET_PERF); + irq_mask_addr = bcm63xx_regset_address(RSET_PERF); + + switch (bcm63xx_get_cpu_id()) { + case BCM3368_CPU_ID: + irq_stat_addr += PERF_IRQSTAT_3368_REG; + irq_mask_addr += PERF_IRQMASK_3368_REG; + irq_bits = 32; + ext_irq_count = 4; + ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368; + break; + case BCM6328_CPU_ID: + irq_stat_addr += PERF_IRQSTAT_6328_REG; + irq_mask_addr += PERF_IRQMASK_6328_REG; + irq_bits = 64; + ext_irq_count = 4; + is_ext_irq_cascaded = 1; + ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE; + ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE; + ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328; + break; + case BCM6338_CPU_ID: + irq_stat_addr += PERF_IRQSTAT_6338_REG; + irq_mask_addr += PERF_IRQMASK_6338_REG; + irq_bits = 32; + ext_irq_count = 4; + ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338; + break; + case BCM6345_CPU_ID: + irq_stat_addr += PERF_IRQSTAT_6345_REG; + irq_mask_addr += PERF_IRQMASK_6345_REG; + irq_bits = 32; + ext_irq_count = 4; + ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345; + break; + case BCM6348_CPU_ID: + irq_stat_addr += PERF_IRQSTAT_6348_REG; + irq_mask_addr += PERF_IRQMASK_6348_REG; + irq_bits = 32; + ext_irq_count = 4; + ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348; + break; + case BCM6358_CPU_ID: + irq_stat_addr += PERF_IRQSTAT_6358_REG; + irq_mask_addr += PERF_IRQMASK_6358_REG; + irq_bits = 32; + ext_irq_count = 4; + is_ext_irq_cascaded = 1; + ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE; + ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE; + ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358; + break; + case BCM6362_CPU_ID: + irq_stat_addr += PERF_IRQSTAT_6362_REG; + irq_mask_addr += PERF_IRQMASK_6362_REG; + irq_bits = 64; + ext_irq_count = 4; + is_ext_irq_cascaded = 1; + ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE; + ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE; + ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362; + break; + case BCM6368_CPU_ID: + irq_stat_addr += PERF_IRQSTAT_6368_REG; + irq_mask_addr += PERF_IRQMASK_6368_REG; + irq_bits = 64; + ext_irq_count = 6; + is_ext_irq_cascaded = 1; + ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE; + ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE; + ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368; + ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368; + break; + default: + BUG(); + } + + if (irq_bits == 32) { + dispatch_internal = __dispatch_internal_32; + internal_irq_mask = __internal_irq_mask_32; + internal_irq_unmask = __internal_irq_unmask_32; + } else { + dispatch_internal = __dispatch_internal_64; + internal_irq_mask = __internal_irq_mask_64; + internal_irq_unmask = __internal_irq_unmask_64; + } +} + void __init arch_init_irq(void) { int i; -- cgit From 86ee4333ba991654f21b7a9e7a7bff0b319f0800 Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Sat, 12 Jul 2014 12:49:35 +0200 Subject: MIPS: BCM63xx: Replace irq dispatch code with a generic version The generic version uses a variable length of u32 registers instead of u32/u64. This allows easier support for "wider" registers without having to rewrite everything. This "generic" version is as fast as the old version in the best case (i == next set bit), and twice as fast in the worst case in 64 bits. Using a macro was chosen over a (forced) inline version because gcc generated more compact code with the macro. The change from (signed) int to unsigned int for i and to_call was intentional as the value can be only between 0 and (width - 1) anyway, and allowed gcc to optimise the code a bit further. Signed-off-by: Jonas Gorski Cc: linux-mips@linux-mips.org Cc: John Crispin Cc: Maxime Bizon Cc: Florian Fainelli Cc: Kevin Cernekee Cc: Gregory Fong Patchwork: https://patchwork.linux-mips.org/patch/7316/ Signed-off-by: Ralf Baechle --- arch/mips/bcm63xx/irq.c | 130 +++++++++++++++++++++--------------------------- 1 file changed, 56 insertions(+), 74 deletions(-) (limited to 'arch/mips/bcm63xx') diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c index f6c933a68c75..db9f2ef76ebe 100644 --- a/arch/mips/bcm63xx/irq.c +++ b/arch/mips/bcm63xx/irq.c @@ -51,47 +51,65 @@ static inline void handle_internal(int intbit) * will resume the loop where it ended the last time we left this * function. */ -static void __dispatch_internal_32(void) -{ - u32 pending; - static int i; - - pending = bcm_readl(irq_stat_addr) & bcm_readl(irq_mask_addr); - - if (!pending) - return ; - - while (1) { - int to_call = i; - i = (i + 1) & 0x1f; - if (pending & (1 << to_call)) { - handle_internal(to_call); - break; - } - } +#define BUILD_IPIC_INTERNAL(width) \ +void __dispatch_internal_##width(void) \ +{ \ + u32 pending[width / 32]; \ + unsigned int src, tgt; \ + bool irqs_pending = false; \ + static unsigned int i; \ + \ + /* read registers in reverse order */ \ + for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \ + u32 val; \ + \ + val = bcm_readl(irq_stat_addr + src * sizeof(u32)); \ + val &= bcm_readl(irq_mask_addr + src * sizeof(u32)); \ + pending[--tgt] = val; \ + \ + if (val) \ + irqs_pending = true; \ + } \ + \ + if (!irqs_pending) \ + return; \ + \ + while (1) { \ + unsigned int to_call = i; \ + \ + i = (i + 1) & (width - 1); \ + if (pending[to_call / 32] & (1 << (to_call & 0x1f))) { \ + handle_internal(to_call); \ + break; \ + } \ + } \ +} \ + \ +static void __internal_irq_mask_##width(unsigned int irq) \ +{ \ + u32 val; \ + unsigned reg = (irq / 32) ^ (width/32 - 1); \ + unsigned bit = irq & 0x1f; \ + \ + val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \ + val &= ~(1 << bit); \ + bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \ +} \ + \ +static void __internal_irq_unmask_##width(unsigned int irq) \ +{ \ + u32 val; \ + unsigned reg = (irq / 32) ^ (width/32 - 1); \ + unsigned bit = irq & 0x1f; \ + \ + val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \ + val |= (1 << bit); \ + bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \ } -static void __dispatch_internal_64(void) -{ - u64 pending; - static int i; - - pending = bcm_readq(irq_stat_addr) & bcm_readq(irq_mask_addr); - - if (!pending) - return ; - - while (1) { - int to_call = i; - - i = (i + 1) & 0x3f; - if (pending & (1ull << to_call)) { - handle_internal(to_call); - break; - } - } -} +BUILD_IPIC_INTERNAL(32); +BUILD_IPIC_INTERNAL(64); asmlinkage void plat_irq_dispatch(void) { @@ -128,42 +146,6 @@ asmlinkage void plat_irq_dispatch(void) * internal IRQs operations: only mask/unmask on PERF irq mask * register. */ -static void __internal_irq_mask_32(unsigned int irq) -{ - u32 mask; - - mask = bcm_readl(irq_mask_addr); - mask &= ~(1 << irq); - bcm_writel(mask, irq_mask_addr); -} - -static void __internal_irq_mask_64(unsigned int irq) -{ - u64 mask; - - mask = bcm_readq(irq_mask_addr); - mask &= ~(1ull << irq); - bcm_writeq(mask, irq_mask_addr); -} - -static void __internal_irq_unmask_32(unsigned int irq) -{ - u32 mask; - - mask = bcm_readl(irq_mask_addr); - mask |= (1 << irq); - bcm_writel(mask, irq_mask_addr); -} - -static void __internal_irq_unmask_64(unsigned int irq) -{ - u64 mask; - - mask = bcm_readq(irq_mask_addr); - mask |= (1ull << irq); - bcm_writeq(mask, irq_mask_addr); -} - static void bcm63xx_internal_irq_mask(struct irq_data *d) { internal_irq_mask(d->irq - IRQ_INTERNAL_BASE); -- cgit From cc81d7f37273ccb34db99a1f7ce688953a04289d Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Sat, 12 Jul 2014 12:49:36 +0200 Subject: MIPS: BCM63xx: Append irq line to irq_{stat,mask}* The SMP capable irq controllers have two interrupt output pins which are controlled through separate registers, so make the variables arrays. Signed-off-by: Jonas Gorski Cc: linux-mips@linux-mips.org Cc: John Crispin Cc: Maxime Bizon Cc: Florian Fainelli Cc: Kevin Cernekee Cc: Gregory Fong Patchwork: https://patchwork.linux-mips.org/patch/7318/ Signed-off-by: Ralf Baechle --- arch/mips/bcm63xx/irq.c | 51 +++++++++++++++++++++++++------------------------ 1 file changed, 26 insertions(+), 25 deletions(-) (limited to 'arch/mips/bcm63xx') diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c index db9f2ef76ebe..91d1765561b5 100644 --- a/arch/mips/bcm63xx/irq.c +++ b/arch/mips/bcm63xx/irq.c @@ -19,7 +19,8 @@ #include #include -static u32 irq_stat_addr, irq_mask_addr; +static u32 irq_stat_addr[2]; +static u32 irq_mask_addr[2]; static void (*dispatch_internal)(void); static int is_ext_irq_cascaded; static unsigned int ext_irq_count; @@ -64,8 +65,8 @@ void __dispatch_internal_##width(void) \ for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \ u32 val; \ \ - val = bcm_readl(irq_stat_addr + src * sizeof(u32)); \ - val &= bcm_readl(irq_mask_addr + src * sizeof(u32)); \ + val = bcm_readl(irq_stat_addr[0] + src * sizeof(u32)); \ + val &= bcm_readl(irq_mask_addr[0] + src * sizeof(u32)); \ pending[--tgt] = val; \ \ if (val) \ @@ -92,9 +93,9 @@ static void __internal_irq_mask_##width(unsigned int irq) \ unsigned reg = (irq / 32) ^ (width/32 - 1); \ unsigned bit = irq & 0x1f; \ \ - val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \ + val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32)); \ val &= ~(1 << bit); \ - bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \ + bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32)); \ } \ \ static void __internal_irq_unmask_##width(unsigned int irq) \ @@ -103,9 +104,9 @@ static void __internal_irq_unmask_##width(unsigned int irq) \ unsigned reg = (irq / 32) ^ (width/32 - 1); \ unsigned bit = irq & 0x1f; \ \ - val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \ + val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32)); \ val |= (1 << bit); \ - bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \ + bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32)); \ } BUILD_IPIC_INTERNAL(32); @@ -339,20 +340,20 @@ static void bcm63xx_init_irq(void) { int irq_bits; - irq_stat_addr = bcm63xx_regset_address(RSET_PERF); - irq_mask_addr = bcm63xx_regset_address(RSET_PERF); + irq_stat_addr[0] = bcm63xx_regset_address(RSET_PERF); + irq_mask_addr[0] = bcm63xx_regset_address(RSET_PERF); switch (bcm63xx_get_cpu_id()) { case BCM3368_CPU_ID: - irq_stat_addr += PERF_IRQSTAT_3368_REG; - irq_mask_addr += PERF_IRQMASK_3368_REG; + irq_stat_addr[0] += PERF_IRQSTAT_3368_REG; + irq_mask_addr[0] += PERF_IRQMASK_3368_REG; irq_bits = 32; ext_irq_count = 4; ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368; break; case BCM6328_CPU_ID: - irq_stat_addr += PERF_IRQSTAT_6328_REG; - irq_mask_addr += PERF_IRQMASK_6328_REG; + irq_stat_addr[0] += PERF_IRQSTAT_6328_REG(0); + irq_mask_addr[0] += PERF_IRQMASK_6328_REG(0); irq_bits = 64; ext_irq_count = 4; is_ext_irq_cascaded = 1; @@ -361,29 +362,29 @@ static void bcm63xx_init_irq(void) ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328; break; case BCM6338_CPU_ID: - irq_stat_addr += PERF_IRQSTAT_6338_REG; - irq_mask_addr += PERF_IRQMASK_6338_REG; + irq_stat_addr[0] += PERF_IRQSTAT_6338_REG; + irq_mask_addr[0] += PERF_IRQMASK_6338_REG; irq_bits = 32; ext_irq_count = 4; ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338; break; case BCM6345_CPU_ID: - irq_stat_addr += PERF_IRQSTAT_6345_REG; - irq_mask_addr += PERF_IRQMASK_6345_REG; + irq_stat_addr[0] += PERF_IRQSTAT_6345_REG; + irq_mask_addr[0] += PERF_IRQMASK_6345_REG; irq_bits = 32; ext_irq_count = 4; ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345; break; case BCM6348_CPU_ID: - irq_stat_addr += PERF_IRQSTAT_6348_REG; - irq_mask_addr += PERF_IRQMASK_6348_REG; + irq_stat_addr[0] += PERF_IRQSTAT_6348_REG; + irq_mask_addr[0] += PERF_IRQMASK_6348_REG; irq_bits = 32; ext_irq_count = 4; ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348; break; case BCM6358_CPU_ID: - irq_stat_addr += PERF_IRQSTAT_6358_REG; - irq_mask_addr += PERF_IRQMASK_6358_REG; + irq_stat_addr[0] += PERF_IRQSTAT_6358_REG(0); + irq_mask_addr[0] += PERF_IRQMASK_6358_REG(0); irq_bits = 32; ext_irq_count = 4; is_ext_irq_cascaded = 1; @@ -392,8 +393,8 @@ static void bcm63xx_init_irq(void) ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358; break; case BCM6362_CPU_ID: - irq_stat_addr += PERF_IRQSTAT_6362_REG; - irq_mask_addr += PERF_IRQMASK_6362_REG; + irq_stat_addr[0] += PERF_IRQSTAT_6362_REG(0); + irq_mask_addr[0] += PERF_IRQMASK_6362_REG(0); irq_bits = 64; ext_irq_count = 4; is_ext_irq_cascaded = 1; @@ -402,8 +403,8 @@ static void bcm63xx_init_irq(void) ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362; break; case BCM6368_CPU_ID: - irq_stat_addr += PERF_IRQSTAT_6368_REG; - irq_mask_addr += PERF_IRQMASK_6368_REG; + irq_stat_addr[0] += PERF_IRQSTAT_6368_REG(0); + irq_mask_addr[0] += PERF_IRQMASK_6368_REG(0); irq_bits = 64; ext_irq_count = 6; is_ext_irq_cascaded = 1; -- cgit From 3534b5ce0547790429d40b19bb444e099f6ba1cf Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Sat, 12 Jul 2014 12:49:37 +0200 Subject: MIPS: BCM63xx: Populate irq_{stat,mask}_addr for second cpu Set it to zero if there is no second set. Signed-off-by: Jonas Gorski Cc: linux-mips@linux-mips.org Cc: John Crispin Cc: Maxime Bizon Cc: Florian Fainelli Cc: Kevin Cernekee Cc: Gregory Fong Patchwork: https://patchwork.linux-mips.org/patch/7319/ Signed-off-by: Ralf Baechle --- arch/mips/bcm63xx/irq.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/mips/bcm63xx') diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c index 91d1765561b5..f467e447bb0e 100644 --- a/arch/mips/bcm63xx/irq.c +++ b/arch/mips/bcm63xx/irq.c @@ -342,11 +342,15 @@ static void bcm63xx_init_irq(void) irq_stat_addr[0] = bcm63xx_regset_address(RSET_PERF); irq_mask_addr[0] = bcm63xx_regset_address(RSET_PERF); + irq_stat_addr[1] = bcm63xx_regset_address(RSET_PERF); + irq_mask_addr[1] = bcm63xx_regset_address(RSET_PERF); switch (bcm63xx_get_cpu_id()) { case BCM3368_CPU_ID: irq_stat_addr[0] += PERF_IRQSTAT_3368_REG; irq_mask_addr[0] += PERF_IRQMASK_3368_REG; + irq_stat_addr[1] = 0; + irq_stat_addr[1] = 0; irq_bits = 32; ext_irq_count = 4; ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368; @@ -354,6 +358,8 @@ static void bcm63xx_init_irq(void) case BCM6328_CPU_ID: irq_stat_addr[0] += PERF_IRQSTAT_6328_REG(0); irq_mask_addr[0] += PERF_IRQMASK_6328_REG(0); + irq_stat_addr[1] += PERF_IRQSTAT_6328_REG(1); + irq_stat_addr[1] += PERF_IRQMASK_6328_REG(1); irq_bits = 64; ext_irq_count = 4; is_ext_irq_cascaded = 1; @@ -364,6 +370,8 @@ static void bcm63xx_init_irq(void) case BCM6338_CPU_ID: irq_stat_addr[0] += PERF_IRQSTAT_6338_REG; irq_mask_addr[0] += PERF_IRQMASK_6338_REG; + irq_stat_addr[1] = 0; + irq_mask_addr[1] = 0; irq_bits = 32; ext_irq_count = 4; ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338; @@ -371,6 +379,8 @@ static void bcm63xx_init_irq(void) case BCM6345_CPU_ID: irq_stat_addr[0] += PERF_IRQSTAT_6345_REG; irq_mask_addr[0] += PERF_IRQMASK_6345_REG; + irq_stat_addr[1] = 0; + irq_mask_addr[1] = 0; irq_bits = 32; ext_irq_count = 4; ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345; @@ -378,6 +388,8 @@ static void bcm63xx_init_irq(void) case BCM6348_CPU_ID: irq_stat_addr[0] += PERF_IRQSTAT_6348_REG; irq_mask_addr[0] += PERF_IRQMASK_6348_REG; + irq_stat_addr[1] = 0; + irq_mask_addr[1] = 0; irq_bits = 32; ext_irq_count = 4; ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348; @@ -385,6 +397,8 @@ static void bcm63xx_init_irq(void) case BCM6358_CPU_ID: irq_stat_addr[0] += PERF_IRQSTAT_6358_REG(0); irq_mask_addr[0] += PERF_IRQMASK_6358_REG(0); + irq_stat_addr[1] += PERF_IRQSTAT_6358_REG(1); + irq_mask_addr[1] += PERF_IRQMASK_6358_REG(1); irq_bits = 32; ext_irq_count = 4; is_ext_irq_cascaded = 1; @@ -395,6 +409,8 @@ static void bcm63xx_init_irq(void) case BCM6362_CPU_ID: irq_stat_addr[0] += PERF_IRQSTAT_6362_REG(0); irq_mask_addr[0] += PERF_IRQMASK_6362_REG(0); + irq_stat_addr[1] += PERF_IRQSTAT_6362_REG(1); + irq_mask_addr[1] += PERF_IRQMASK_6362_REG(1); irq_bits = 64; ext_irq_count = 4; is_ext_irq_cascaded = 1; @@ -405,6 +421,8 @@ static void bcm63xx_init_irq(void) case BCM6368_CPU_ID: irq_stat_addr[0] += PERF_IRQSTAT_6368_REG(0); irq_mask_addr[0] += PERF_IRQMASK_6368_REG(0); + irq_stat_addr[1] += PERF_IRQSTAT_6368_REG(1); + irq_mask_addr[1] += PERF_IRQMASK_6368_REG(1); irq_bits = 64; ext_irq_count = 6; is_ext_irq_cascaded = 1; -- cgit From 7a9fd14d4c4796d3b0d4aec9c91183560d201b4d Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Sat, 12 Jul 2014 12:49:38 +0200 Subject: MIPS: BCM63xx: Add cpu argument to dispatch internal Signed-off-by: Jonas Gorski Cc: linux-mips@linux-mips.org Cc: John Crispin Cc: Maxime Bizon Cc: Florian Fainelli Cc: Kevin Cernekee Cc: Gregory Fong Patchwork: https://patchwork.linux-mips.org/patch/7320/ Signed-off-by: Ralf Baechle --- arch/mips/bcm63xx/irq.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) (limited to 'arch/mips/bcm63xx') diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c index f467e447bb0e..53be291c3d94 100644 --- a/arch/mips/bcm63xx/irq.c +++ b/arch/mips/bcm63xx/irq.c @@ -19,9 +19,10 @@ #include #include + static u32 irq_stat_addr[2]; static u32 irq_mask_addr[2]; -static void (*dispatch_internal)(void); +static void (*dispatch_internal)(int cpu); static int is_ext_irq_cascaded; static unsigned int ext_irq_count; static unsigned int ext_irq_start, ext_irq_end; @@ -54,19 +55,20 @@ static inline void handle_internal(int intbit) */ #define BUILD_IPIC_INTERNAL(width) \ -void __dispatch_internal_##width(void) \ +void __dispatch_internal_##width(int cpu) \ { \ u32 pending[width / 32]; \ unsigned int src, tgt; \ bool irqs_pending = false; \ - static unsigned int i; \ + static unsigned int i[2]; \ + unsigned int *next = &i[cpu]; \ \ /* read registers in reverse order */ \ for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \ u32 val; \ \ - val = bcm_readl(irq_stat_addr[0] + src * sizeof(u32)); \ - val &= bcm_readl(irq_mask_addr[0] + src * sizeof(u32)); \ + val = bcm_readl(irq_stat_addr[cpu] + src * sizeof(u32)); \ + val &= bcm_readl(irq_mask_addr[cpu] + src * sizeof(u32)); \ pending[--tgt] = val; \ \ if (val) \ @@ -77,9 +79,9 @@ void __dispatch_internal_##width(void) \ return; \ \ while (1) { \ - unsigned int to_call = i; \ + unsigned int to_call = *next; \ \ - i = (i + 1) & (width - 1); \ + *next = (*next + 1) & (width - 1); \ if (pending[to_call / 32] & (1 << (to_call & 0x1f))) { \ handle_internal(to_call); \ break; \ @@ -129,7 +131,7 @@ asmlinkage void plat_irq_dispatch(void) if (cause & CAUSEF_IP1) do_IRQ(1); if (cause & CAUSEF_IP2) - dispatch_internal(); + dispatch_internal(0); if (!is_ext_irq_cascaded) { if (cause & CAUSEF_IP3) do_IRQ(IRQ_EXT_0); -- cgit From 74b8ca3f3160b062207be6ee88785409c0a777ea Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Sat, 12 Jul 2014 12:49:39 +0200 Subject: MIPS: BCM63xx: Protect irq register accesses Since we will have the chance of accessing the registers concurrently, protect any accesses through a spinlock. Signed-off-by: Jonas Gorski Cc: linux-mips@linux-mips.org Cc: John Crispin Cc: Maxime Bizon Cc: Florian Fainelli Cc: Kevin Cernekee Cc: Gregory Fong Patchwork: https://patchwork.linux-mips.org/patch/7321/ Signed-off-by: Ralf Baechle --- arch/mips/bcm63xx/irq.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/mips/bcm63xx') diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c index 53be291c3d94..2f1939122bc3 100644 --- a/arch/mips/bcm63xx/irq.c +++ b/arch/mips/bcm63xx/irq.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -20,6 +21,9 @@ #include +static DEFINE_SPINLOCK(ipic_lock); +static DEFINE_SPINLOCK(epic_lock); + static u32 irq_stat_addr[2]; static u32 irq_mask_addr[2]; static void (*dispatch_internal)(int cpu); @@ -62,8 +66,10 @@ void __dispatch_internal_##width(int cpu) \ bool irqs_pending = false; \ static unsigned int i[2]; \ unsigned int *next = &i[cpu]; \ + unsigned long flags; \ \ /* read registers in reverse order */ \ + spin_lock_irqsave(&ipic_lock, flags); \ for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \ u32 val; \ \ @@ -74,6 +80,7 @@ void __dispatch_internal_##width(int cpu) \ if (val) \ irqs_pending = true; \ } \ + spin_unlock_irqrestore(&ipic_lock, flags); \ \ if (!irqs_pending) \ return; \ @@ -94,10 +101,13 @@ static void __internal_irq_mask_##width(unsigned int irq) \ u32 val; \ unsigned reg = (irq / 32) ^ (width/32 - 1); \ unsigned bit = irq & 0x1f; \ + unsigned long flags; \ \ + spin_lock_irqsave(&ipic_lock, flags); \ val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32)); \ val &= ~(1 << bit); \ bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32)); \ + spin_unlock_irqrestore(&ipic_lock, flags); \ } \ \ static void __internal_irq_unmask_##width(unsigned int irq) \ @@ -105,10 +115,13 @@ static void __internal_irq_unmask_##width(unsigned int irq) \ u32 val; \ unsigned reg = (irq / 32) ^ (width/32 - 1); \ unsigned bit = irq & 0x1f; \ + unsigned long flags; \ \ + spin_lock_irqsave(&ipic_lock, flags); \ val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32)); \ val |= (1 << bit); \ bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32)); \ + spin_unlock_irqrestore(&ipic_lock, flags); \ } BUILD_IPIC_INTERNAL(32); @@ -167,8 +180,10 @@ static void bcm63xx_external_irq_mask(struct irq_data *d) { unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; u32 reg, regaddr; + unsigned long flags; regaddr = get_ext_irq_perf_reg(irq); + spin_lock_irqsave(&epic_lock, flags); reg = bcm_perf_readl(regaddr); if (BCMCPU_IS_6348()) @@ -177,6 +192,8 @@ static void bcm63xx_external_irq_mask(struct irq_data *d) reg &= ~EXTIRQ_CFG_MASK(irq % 4); bcm_perf_writel(reg, regaddr); + spin_unlock_irqrestore(&epic_lock, flags); + if (is_ext_irq_cascaded) internal_irq_mask(irq + ext_irq_start); } @@ -185,8 +202,10 @@ static void bcm63xx_external_irq_unmask(struct irq_data *d) { unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; u32 reg, regaddr; + unsigned long flags; regaddr = get_ext_irq_perf_reg(irq); + spin_lock_irqsave(&epic_lock, flags); reg = bcm_perf_readl(regaddr); if (BCMCPU_IS_6348()) @@ -195,6 +214,7 @@ static void bcm63xx_external_irq_unmask(struct irq_data *d) reg |= EXTIRQ_CFG_MASK(irq % 4); bcm_perf_writel(reg, regaddr); + spin_unlock_irqrestore(&epic_lock, flags); if (is_ext_irq_cascaded) internal_irq_unmask(irq + ext_irq_start); @@ -204,8 +224,10 @@ static void bcm63xx_external_irq_clear(struct irq_data *d) { unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; u32 reg, regaddr; + unsigned long flags; regaddr = get_ext_irq_perf_reg(irq); + spin_lock_irqsave(&epic_lock, flags); reg = bcm_perf_readl(regaddr); if (BCMCPU_IS_6348()) @@ -214,6 +236,7 @@ static void bcm63xx_external_irq_clear(struct irq_data *d) reg |= EXTIRQ_CFG_CLEAR(irq % 4); bcm_perf_writel(reg, regaddr); + spin_unlock_irqrestore(&epic_lock, flags); } static int bcm63xx_external_irq_set_type(struct irq_data *d, @@ -222,6 +245,7 @@ static int bcm63xx_external_irq_set_type(struct irq_data *d, unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; u32 reg, regaddr; int levelsense, sense, bothedge; + unsigned long flags; flow_type &= IRQ_TYPE_SENSE_MASK; @@ -256,6 +280,7 @@ static int bcm63xx_external_irq_set_type(struct irq_data *d, } regaddr = get_ext_irq_perf_reg(irq); + spin_lock_irqsave(&epic_lock, flags); reg = bcm_perf_readl(regaddr); irq %= 4; @@ -300,6 +325,7 @@ static int bcm63xx_external_irq_set_type(struct irq_data *d, } bcm_perf_writel(reg, regaddr); + spin_unlock_irqrestore(&epic_lock, flags); irqd_set_trigger_type(d, flow_type); if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) -- cgit From 56d53eaec1ad402cb1055e816adad102d2f5b6bf Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Sat, 12 Jul 2014 12:49:40 +0200 Subject: MIPS: BCM63xx: Wire up the second cpu's irq line Signed-off-by: Jonas Gorski Cc: linux-mips@linux-mips.org Cc: John Crispin Cc: Maxime Bizon Cc: Florian Fainelli Cc: Kevin Cernekee Cc: Gregory Fong Patchwork: https://patchwork.linux-mips.org/patch/7322/ Signed-off-by: Ralf Baechle --- arch/mips/bcm63xx/irq.c | 44 +++++++++++++++++++++++++++++++++++++------- 1 file changed, 37 insertions(+), 7 deletions(-) (limited to 'arch/mips/bcm63xx') diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c index 2f1939122bc3..615b25bb34f5 100644 --- a/arch/mips/bcm63xx/irq.c +++ b/arch/mips/bcm63xx/irq.c @@ -102,11 +102,17 @@ static void __internal_irq_mask_##width(unsigned int irq) \ unsigned reg = (irq / 32) ^ (width/32 - 1); \ unsigned bit = irq & 0x1f; \ unsigned long flags; \ + int cpu; \ \ spin_lock_irqsave(&ipic_lock, flags); \ - val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32)); \ - val &= ~(1 << bit); \ - bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32)); \ + for_each_present_cpu(cpu) { \ + if (!irq_mask_addr[cpu]) \ + break; \ + \ + val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\ + val &= ~(1 << bit); \ + bcm_writel(val, irq_mask_addr[cpu] + reg * sizeof(u32));\ + } \ spin_unlock_irqrestore(&ipic_lock, flags); \ } \ \ @@ -116,11 +122,20 @@ static void __internal_irq_unmask_##width(unsigned int irq) \ unsigned reg = (irq / 32) ^ (width/32 - 1); \ unsigned bit = irq & 0x1f; \ unsigned long flags; \ + int cpu; \ \ spin_lock_irqsave(&ipic_lock, flags); \ - val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32)); \ - val |= (1 << bit); \ - bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32)); \ + for_each_present_cpu(cpu) { \ + if (!irq_mask_addr[cpu]) \ + break; \ + \ + val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\ + if (cpu_online(cpu)) \ + val |= (1 << bit); \ + else \ + val &= ~(1 << bit); \ + bcm_writel(val, irq_mask_addr[cpu] + reg * sizeof(u32));\ + } \ spin_unlock_irqrestore(&ipic_lock, flags); \ } @@ -145,7 +160,10 @@ asmlinkage void plat_irq_dispatch(void) do_IRQ(1); if (cause & CAUSEF_IP2) dispatch_internal(0); - if (!is_ext_irq_cascaded) { + if (is_ext_irq_cascaded) { + if (cause & CAUSEF_IP3) + dispatch_internal(1); + } else { if (cause & CAUSEF_IP3) do_IRQ(IRQ_EXT_0); if (cause & CAUSEF_IP4) @@ -358,6 +376,14 @@ static struct irqaction cpu_ip2_cascade_action = { .flags = IRQF_NO_THREAD, }; +#ifdef CONFIG_SMP +static struct irqaction cpu_ip3_cascade_action = { + .handler = no_action, + .name = "cascade_ip3", + .flags = IRQF_NO_THREAD, +}; +#endif + static struct irqaction cpu_ext_cascade_action = { .handler = no_action, .name = "cascade_extirq", @@ -494,4 +520,8 @@ void __init arch_init_irq(void) } setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action); +#ifdef CONFIG_SMP + if (is_ext_irq_cascaded) + setup_irq(MIPS_CPU_IRQ_BASE + 3, &cpu_ip3_cascade_action); +#endif } -- cgit From 553e25b3da2f1c8e30cc20499ae3593815df97e9 Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Sat, 12 Jul 2014 12:49:41 +0200 Subject: MIPS: BCM63xx: Use irq_desc as argument for (un)mask In preparation for applying affinity, use the irq descriptor as the argument for (un)mask. Signed-off-by: Jonas Gorski Cc: linux-mips@linux-mips.org Cc: John Crispin Cc: Maxime Bizon Cc: Florian Fainelli Cc: Kevin Cernekee Cc: Gregory Fong Patchwork: https://patchwork.linux-mips.org/patch/7317/ Signed-off-by: Ralf Baechle --- arch/mips/bcm63xx/irq.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) (limited to 'arch/mips/bcm63xx') diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c index 615b25bb34f5..a53305fbedb8 100644 --- a/arch/mips/bcm63xx/irq.c +++ b/arch/mips/bcm63xx/irq.c @@ -31,8 +31,8 @@ static int is_ext_irq_cascaded; static unsigned int ext_irq_count; static unsigned int ext_irq_start, ext_irq_end; static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2; -static void (*internal_irq_mask)(unsigned int irq); -static void (*internal_irq_unmask)(unsigned int irq); +static void (*internal_irq_mask)(struct irq_data *d); +static void (*internal_irq_unmask)(struct irq_data *d); static inline u32 get_ext_irq_perf_reg(int irq) @@ -96,9 +96,10 @@ void __dispatch_internal_##width(int cpu) \ } \ } \ \ -static void __internal_irq_mask_##width(unsigned int irq) \ +static void __internal_irq_mask_##width(struct irq_data *d) \ { \ u32 val; \ + unsigned irq = d->irq - IRQ_INTERNAL_BASE; \ unsigned reg = (irq / 32) ^ (width/32 - 1); \ unsigned bit = irq & 0x1f; \ unsigned long flags; \ @@ -116,9 +117,10 @@ static void __internal_irq_mask_##width(unsigned int irq) \ spin_unlock_irqrestore(&ipic_lock, flags); \ } \ \ -static void __internal_irq_unmask_##width(unsigned int irq) \ +static void __internal_irq_unmask_##width(struct irq_data *d) \ { \ u32 val; \ + unsigned irq = d->irq - IRQ_INTERNAL_BASE; \ unsigned reg = (irq / 32) ^ (width/32 - 1); \ unsigned bit = irq & 0x1f; \ unsigned long flags; \ @@ -182,12 +184,12 @@ asmlinkage void plat_irq_dispatch(void) */ static void bcm63xx_internal_irq_mask(struct irq_data *d) { - internal_irq_mask(d->irq - IRQ_INTERNAL_BASE); + internal_irq_mask(d); } static void bcm63xx_internal_irq_unmask(struct irq_data *d) { - internal_irq_unmask(d->irq - IRQ_INTERNAL_BASE); + internal_irq_unmask(d); } /* @@ -213,7 +215,7 @@ static void bcm63xx_external_irq_mask(struct irq_data *d) spin_unlock_irqrestore(&epic_lock, flags); if (is_ext_irq_cascaded) - internal_irq_mask(irq + ext_irq_start); + internal_irq_mask(irq_get_irq_data(irq + ext_irq_start)); } static void bcm63xx_external_irq_unmask(struct irq_data *d) @@ -235,7 +237,7 @@ static void bcm63xx_external_irq_unmask(struct irq_data *d) spin_unlock_irqrestore(&epic_lock, flags); if (is_ext_irq_cascaded) - internal_irq_unmask(irq + ext_irq_start); + internal_irq_unmask(irq_get_irq_data(irq + ext_irq_start)); } static void bcm63xx_external_irq_clear(struct irq_data *d) -- cgit From b37f0f691e69b0325b6f448679e0e338dbd076e2 Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Sat, 12 Jul 2014 12:49:42 +0200 Subject: MIPS: BCM63xx: Allow setting affinity for IPIC Wire up the set_affinity call for the internal PIC if booting on a cpu supporting it. Affinity is kept to boot cpu as default. Signed-off-by: Jonas Gorski Cc: linux-mips@linux-mips.org Cc: John Crispin Cc: Maxime Bizon Cc: Florian Fainelli Cc: Kevin Cernekee Cc: Gregory Fong Patchwork: https://patchwork.linux-mips.org/patch/7323/ Signed-off-by: Ralf Baechle --- arch/mips/bcm63xx/irq.c | 46 ++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 40 insertions(+), 6 deletions(-) (limited to 'arch/mips/bcm63xx') diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c index a53305fbedb8..37eb2d1fa69a 100644 --- a/arch/mips/bcm63xx/irq.c +++ b/arch/mips/bcm63xx/irq.c @@ -32,7 +32,7 @@ static unsigned int ext_irq_count; static unsigned int ext_irq_start, ext_irq_end; static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2; static void (*internal_irq_mask)(struct irq_data *d); -static void (*internal_irq_unmask)(struct irq_data *d); +static void (*internal_irq_unmask)(struct irq_data *d, const struct cpumask *m); static inline u32 get_ext_irq_perf_reg(int irq) @@ -51,6 +51,20 @@ static inline void handle_internal(int intbit) do_IRQ(intbit + IRQ_INTERNAL_BASE); } +static inline int enable_irq_for_cpu(int cpu, struct irq_data *d, + const struct cpumask *m) +{ + bool enable = cpu_online(cpu); + +#ifdef CONFIG_SMP + if (m) + enable &= cpu_isset(cpu, *m); + else if (irqd_affinity_was_set(d)) + enable &= cpu_isset(cpu, *d->affinity); +#endif + return enable; +} + /* * dispatch internal devices IRQ (uart, enet, watchdog, ...). do not * prioritize any interrupt relatively to another. the static counter @@ -117,7 +131,8 @@ static void __internal_irq_mask_##width(struct irq_data *d) \ spin_unlock_irqrestore(&ipic_lock, flags); \ } \ \ -static void __internal_irq_unmask_##width(struct irq_data *d) \ +static void __internal_irq_unmask_##width(struct irq_data *d, \ + const struct cpumask *m) \ { \ u32 val; \ unsigned irq = d->irq - IRQ_INTERNAL_BASE; \ @@ -132,7 +147,7 @@ static void __internal_irq_unmask_##width(struct irq_data *d) \ break; \ \ val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\ - if (cpu_online(cpu)) \ + if (enable_irq_for_cpu(cpu, d, m)) \ val |= (1 << bit); \ else \ val &= ~(1 << bit); \ @@ -189,7 +204,7 @@ static void bcm63xx_internal_irq_mask(struct irq_data *d) static void bcm63xx_internal_irq_unmask(struct irq_data *d) { - internal_irq_unmask(d); + internal_irq_unmask(d, NULL); } /* @@ -237,7 +252,8 @@ static void bcm63xx_external_irq_unmask(struct irq_data *d) spin_unlock_irqrestore(&epic_lock, flags); if (is_ext_irq_cascaded) - internal_irq_unmask(irq_get_irq_data(irq + ext_irq_start)); + internal_irq_unmask(irq_get_irq_data(irq + ext_irq_start), + NULL); } static void bcm63xx_external_irq_clear(struct irq_data *d) @@ -356,6 +372,18 @@ static int bcm63xx_external_irq_set_type(struct irq_data *d, return IRQ_SET_MASK_OK_NOCOPY; } +#ifdef CONFIG_SMP +static int bcm63xx_internal_set_affinity(struct irq_data *data, + const struct cpumask *dest, + bool force) +{ + if (!irqd_irq_disabled(data)) + internal_irq_unmask(data, dest); + + return 0; +} +#endif + static struct irq_chip bcm63xx_internal_irq_chip = { .name = "bcm63xx_ipic", .irq_mask = bcm63xx_internal_irq_mask, @@ -523,7 +551,13 @@ void __init arch_init_irq(void) setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action); #ifdef CONFIG_SMP - if (is_ext_irq_cascaded) + if (is_ext_irq_cascaded) { setup_irq(MIPS_CPU_IRQ_BASE + 3, &cpu_ip3_cascade_action); + bcm63xx_internal_irq_chip.irq_set_affinity = + bcm63xx_internal_set_affinity; + + cpumask_clear(irq_default_affinity); + cpumask_set_cpu(smp_processor_id(), irq_default_affinity); + } #endif } -- cgit