From 83f865d7e32e40b4903b1f83537c63fc5cdf1eb8 Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Wed, 17 Jun 2020 12:50:36 +0200 Subject: mips: bmips: dts: add BCM6328 reset controller support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit BCM6328 SoCs have a reset controller for certain components. Signed-off-by: Álvaro Fernández Rojas Acked-by: Florian Fainelli Reviewed-by: Rob Herring Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/brcm/bcm6328.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/mips/boot/dts/brcm') diff --git a/arch/mips/boot/dts/brcm/bcm6328.dtsi b/arch/mips/boot/dts/brcm/bcm6328.dtsi index 1f9edd710392..9dc558763c46 100644 --- a/arch/mips/boot/dts/brcm/bcm6328.dtsi +++ b/arch/mips/boot/dts/brcm/bcm6328.dtsi @@ -57,6 +57,12 @@ #clock-cells = <1>; }; + periph_rst: reset-controller@10000010 { + compatible = "brcm,bcm6345-reset"; + reg = <0x10000010 0x4>; + #reset-cells = <1>; + }; + periph_intc: interrupt-controller@10000020 { compatible = "brcm,bcm6345-l1-intc"; reg = <0x10000020 0x10>, -- cgit