From bc75dffadc063eb46200611cc41d1e2373219e11 Mon Sep 17 00:00:00 2001 From: Justin Swartz Date: Fri, 8 Mar 2024 17:56:14 +0200 Subject: mips: dts: ralink: mt7621: associate uart1_pins with serial0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add missing pinctrl-name and pinctrl-0 properties to declare that the uart1_pins group is associated with serial0. Acked-by: Sergio Paracuellos Signed-off-by: Justin Swartz Reviewed-by: Arınç ÜNAL Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/ralink/mt7621.dtsi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/mips/boot/dts/ralink') diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi index 35a10258f235..dca415fddd90 100644 --- a/arch/mips/boot/dts/ralink/mt7621.dtsi +++ b/arch/mips/boot/dts/ralink/mt7621.dtsi @@ -123,6 +123,9 @@ reg-shift = <2>; reg-io-width = <4>; no-loopback-test; + + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; }; spi0: spi@b00 { -- cgit From 82394085bf0368a2b2ab9c41d3a5cebf05cff02e Mon Sep 17 00:00:00 2001 From: Justin Swartz Date: Fri, 8 Mar 2024 17:56:15 +0200 Subject: mips: dts: ralink: mt7621: reorder serial0 properties MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reorder serial0 properties according to the guidelines laid out in Documentation/devicetree/bindings/dts-coding-style.rst Acked-by: Sergio Paracuellos Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Justin Swartz Reviewed-by: Arınç ÜNAL Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/ralink/mt7621.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/mips/boot/dts/ralink') diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi index dca415fddd90..68467fca3fc9 100644 --- a/arch/mips/boot/dts/ralink/mt7621.dtsi +++ b/arch/mips/boot/dts/ralink/mt7621.dtsi @@ -115,13 +115,14 @@ compatible = "ns16550a"; reg = <0xc00 0x100>; + reg-io-width = <4>; + reg-shift = <2>; + clocks = <&sysc MT7621_CLK_UART1>; interrupt-parent = <&gic>; interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; no-loopback-test; pinctrl-names = "default"; -- cgit From 7fdfd3d81b2a02ecbcc4b285311d25e8b5f4cbf9 Mon Sep 17 00:00:00 2001 From: Justin Swartz Date: Fri, 8 Mar 2024 17:56:16 +0200 Subject: mips: dts: ralink: mt7621: add serial1 and serial2 nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add serial1 and serial2 nodes to define the existence of the MT7621's second and third UARTs. Acked-by: Sergio Paracuellos Signed-off-by: Justin Swartz Reviewed-by: Arınç ÜNAL Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/ralink/mt7621.dtsi | 40 +++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'arch/mips/boot/dts/ralink') diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi index 68467fca3fc9..02e1f2491db0 100644 --- a/arch/mips/boot/dts/ralink/mt7621.dtsi +++ b/arch/mips/boot/dts/ralink/mt7621.dtsi @@ -129,6 +129,46 @@ pinctrl-0 = <&uart1_pins>; }; + serial1: serial@d00 { + compatible = "ns16550a"; + reg = <0xd00 0x100>; + + reg-io-width = <4>; + reg-shift = <2>; + + clocks = <&sysc MT7621_CLK_UART2>; + + interrupt-parent = <&gic>; + interrupts = ; + + no-loopback-test; + + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + + status = "disabled"; + }; + + serial2: serial@e00 { + compatible = "ns16550a"; + reg = <0xe00 0x100>; + + reg-io-width = <4>; + reg-shift = <2>; + + clocks = <&sysc MT7621_CLK_UART3>; + + interrupt-parent = <&gic>; + interrupts = ; + + no-loopback-test; + + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + + status = "disabled"; + }; + spi0: spi@b00 { status = "disabled"; -- cgit From 850778617121aa0e1c8f4b3ab4f33eff8a064431 Mon Sep 17 00:00:00 2001 From: Justin Swartz Date: Fri, 8 Mar 2024 18:11:30 +0200 Subject: mips: dts: ralink: mt7621: add cell count properties to usb MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add default #address-cells and #size-cells properties to the usb node, which should be suitable for hubs and devices without explicitly declared interface nodes, as: "#address-cells": description: should be 1 for hub nodes with device nodes, should be 2 for device nodes with interface nodes. enum: [1, 2] "#size-cells": const: 0 -- from Documentation/devicetree/bindings/usb/usb-device.yaml Acked-by: Sergio Paracuellos Signed-off-by: Justin Swartz Reviewed-by: Arınç ÜNAL Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/ralink/mt7621.dtsi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/mips/boot/dts/ralink') diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi index 02e1f2491db0..6e95e6f19a6a 100644 --- a/arch/mips/boot/dts/ralink/mt7621.dtsi +++ b/arch/mips/boot/dts/ralink/mt7621.dtsi @@ -307,6 +307,9 @@ 0x1e1d0700 0x0100>; reg-names = "mac", "ippc"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&sysc MT7621_CLK_XTAL>; clock-names = "sys_ck"; -- cgit