From 3ba7f44d2b19166b34031db48ce613d1bddbd384 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Fri, 9 Jun 2017 17:26:40 -0700 Subject: MIPS: cmpxchg: Implement 1 byte & 2 byte cmpxchg() Implement support for 1 & 2 byte cmpxchg() using read-modify-write atop a 4 byte cmpxchg(). This allows us to support these atomic operations despite the MIPS ISA only providing 4 & 8 byte atomic operations. This is required in order to support queued rwlocks (qrwlock) in a later patch, since these make use of a 1 byte cmpxchg() in their slow path. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16355/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/cmpxchg.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/mips/include/asm/cmpxchg.h') diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h index a633bf845689..a633f61c5545 100644 --- a/arch/mips/include/asm/cmpxchg.h +++ b/arch/mips/include/asm/cmpxchg.h @@ -142,10 +142,17 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz __ret; \ }) +extern unsigned long __cmpxchg_small(volatile void *ptr, unsigned long old, + unsigned long new, unsigned int size); + static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, unsigned int size) { switch (size) { + case 1: + case 2: + return __cmpxchg_small(ptr, old, new, size); + case 4: return __cmpxchg_asm("ll", "sc", (volatile u32 *)ptr, old, new); -- cgit