From 9bac624b0fe0e51a7d5d2519634ed06ceeceb775 Mon Sep 17 00:00:00 2001 From: Ganesan Ramalingam Date: Tue, 24 Jul 2012 17:28:54 +0200 Subject: MIPS: Netlogic: XLP PCIe controller support. Adds support for the XLP on-chip PCIe controller. On XLP, the on-chip devices(including the 4 PCIe links) appear in the PCIe configuration space of the XLP as PCI devices. The changes are to initialize and register the PCIe controller, enable hardware byte swap in the PCIe IO and MEM space, and to enable PCIe interrupts. Signed-off-by: Ganesan Ramalingam Signed-off-by: Jayachandran C Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3760/ Patchwork: https://patchwork.linux-mips.org/patch/4104/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/netlogic/xlp-hal/xlp.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'arch/mips/include/asm/netlogic/xlp-hal/xlp.h') diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h index 1540588e396d..dc6e98eb441e 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h @@ -35,8 +35,12 @@ #ifndef _NLM_HAL_XLP_H #define _NLM_HAL_XLP_H -#define PIC_UART_0_IRQ 17 -#define PIC_UART_1_IRQ 18 +#define PIC_UART_0_IRQ 17 +#define PIC_UART_1_IRQ 18 +#define PIC_PCIE_LINK_0_IRQ 19 +#define PIC_PCIE_LINK_1_IRQ 20 +#define PIC_PCIE_LINK_2_IRQ 21 +#define PIC_PCIE_LINK_3_IRQ 22 #ifndef __ASSEMBLY__ -- cgit