From 61fa969f27ec58296544bf94d058f3aa704cb8d9 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Thu, 16 Aug 2012 11:39:57 +0000 Subject: MIPS: lantiq: split up IRQ IM ranges Up to now all our SoCs had the 5 IM ranges in a consecutive order. To accomodate the SVIP we need to support IM ranges that are scattered inside the register range. Signed-off-by: John Crispin Patchwork: http://patchwork.linux-mips.org/patch/4237/ --- arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h | 2 ++ arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h | 2 ++ 2 files changed, 4 insertions(+) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h index 318f982f04ff..c6b63a409641 100644 --- a/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h +++ b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h @@ -20,4 +20,6 @@ #define MIPS_CPU_TIMER_IRQ 7 +#define MAX_IM 5 + #endif /* _FALCON_IRQ__ */ diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h index aa0b3b866f84..5eadfe582529 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h @@ -21,4 +21,6 @@ #define MIPS_CPU_TIMER_IRQ 7 +#define MAX_IM 5 + #endif -- cgit From e316cb2b16bbfbe48387b56e7e6b5d32ec686f82 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Sun, 20 May 2012 00:33:56 +0200 Subject: OF: pinctrl: MIPS: lantiq: adds support for FALCON SoC Implement support for pinctrl on lantiq/falcon socs. The FALCON has 5 banks of up to 32 pins. Signed-off-by: John Crispin Signed-off-by: Thomas Langer Acked-by: Linus Walleij Cc: devicetree-discuss@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org --- arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h index b385252584ee..fccac3592651 100644 --- a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h @@ -57,6 +57,10 @@ extern __iomem void *ltq_sys1_membase; #define ltq_sys1_w32_mask(clear, set, reg) \ ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg) +/* allow the gpio and pinctrl drivers to talk to eachother */ +extern int pinctrl_falcon_get_range_size(int id); +extern void pinctrl_falcon_add_gpio_range(struct pinctrl_gpio_range *range); + /* * to keep the irq code generic we need to define this to 0 as falcon * has no EIU/EBU -- cgit From 6a88a0f762a61f212d4bbcf1ad45369f28014484 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Wed, 15 Aug 2012 15:41:50 +0200 Subject: MIPS: lantiq: make use of __gpio_to_irq The gpio_chip struct allows us to set a .to_irq callback. Once this is set we can rely on the generic __gpio_to_irq() function to map gpio->irq allowing more than one gpio_chip to register an interrupt Signed-off-by: John Crispin --- arch/mips/include/asm/mach-lantiq/gpio.h | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/mach-lantiq/gpio.h b/arch/mips/include/asm/mach-lantiq/gpio.h index f79505b43609..9ba1caebca5f 100644 --- a/arch/mips/include/asm/mach-lantiq/gpio.h +++ b/arch/mips/include/asm/mach-lantiq/gpio.h @@ -1,10 +1,7 @@ #ifndef __ASM_MIPS_MACH_LANTIQ_GPIO_H #define __ASM_MIPS_MACH_LANTIQ_GPIO_H -static inline int gpio_to_irq(unsigned int gpio) -{ - return -1; -} +#define gpio_to_irq __gpio_to_irq #define gpio_get_value __gpio_get_value #define gpio_set_value __gpio_set_value -- cgit